FR 3101218 A1 20210326 FR 1910460 A 20190923 A system for controlling equalization applied to a received signal comprising an equalizer configured to equalize on a received signal to generate an equalized signal, and a clock recovery module configured to recover a clock signal from the equalized signal or the received signal. A clock adjustment system is configured to receive the clock signal, and at least one control signal, to create a sampling clock signal. A filter is configured to filter the equalized signal to create a filtered signal. A sampling unit samples the filtered signal or the equalized signal such that the output of the sampling unit is provided to a controller. The controller is configured to receive and process the output of the sampling unit to generate a boost signal, and the controller is further configured to provide the boost signal to the equalizer to control the amount of equalization performed by the equalizer. EQUALIZER ADAPTATION BASED ON EYE MONITOR MEASUREMENTS Field of the Invention The invention relates to data communications and in particular to a method and apparatus for equalizer control. Related Art Data communication is widespread in modern society as a means to communicate data between remote locations and between data processing systems. Data communication systems enable telecommunications, Internet data, financial transactions, entertainment, and many other applications utilizing data communications. Foundational to data communications is the transmission of data from one location to another. These locations may be in the same data processing system or many kilometers apart. One challenge for data communication systems, particularly as data transmission rates increase, is to overcome the effects of the channel on the transmitted signal. While a signal with accurate transitions may be transmitted onto the channel upon receipt at a receiver the signal will be affected by the channel such that the transmitted signal is distorted by the channel. With increasing data rates, the channel distortion may be a limiting factor in overall transmit rates and will thus limit the distance the signal may travel, the data rate, and the nature of the signal that may be transmitted. To address this challenge in the prior art, numerous solutions have been proposed. One such solution is to limit data transit rates and distances. While effective, it is not a suitable solution because it does not improve data transmit rates to keep pace with new technology demands. Another proposed solution is to utilize advanced systems, such as an equalizer, for processing the received signal. This solution is widely used, but prior art equalizer systems are limited in their ability to correct for channel distortion. There can be many different types of channels to equalize, and the channel can change over time. As a result, the equalizer needs to be trained to find the optimal settings. Furthermore, prior art solutions required numerous hardware elements which increased costs and space consumption. To overcome the drawbacks of the prior art, an improved method and apparatus are provided for signal equalization and equalizer configuration and control. Brief Description of the Drawings The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the different views. illustrates a block diagram of an exemplary communication system. illustrates a block diagram of an exemplary first environment of use. illustrates a block diagram of an exemplary second environment of use. illustrates an eye diagram plot of an under equalized signal. [Fig. 2B] illustrates an eye diagram plot of a properly equalized signal. [Fig. 2C] illustrates an eye diagram plot of an over equalized signal. illustrates a block diagram of an example embodiment of an equalizer control system. and [Fig. 4B] illustrate an example method of operation. illustrates a block diagram of an exemplary alternative embodiment. illustrates an exemplary eye diagram plot showing offset. A method of adapting equalizer settings comprising: processing a received signal with an equalizer to create an equalizer output; low pass filtering the equalizer output to generate a low pass filtered signal; processing the equalizer output with a CDR to isolate a clock signal; processing the clock signal with a phase interpolator to generate a sampling clock; sampling the low pass filtered signal with an analog to digital converter to generate a first sampled equalizer output, the sampling timing controlled by the sampling clock; providing the first sampled equalizer output to a controller; processing the first sampled equalizer output with the controller to calculate target values; sampling the equalizer output with the analog to digital converter based on the sampling clock to generate a second sampled equalizer output; providing the second sampled equalizer output to the controller; processing the second sampled equalizer output with the controller to calculate average signal values; comparing the target values with the average values to adjust a boost signal; and providing the boost signal to the equalizer, the boost signal controlling the amount of equalization applied to the received signal. The method of claim 1 wherein the equalizer is a continuous time linear equalizer. The method of claim 1 wherein the low pass filtered signal comprises low frequency signal components. The method of claim 1 wherein the method occurs in a crosspoint switch. The method of claim 1 wherein the target values comprise a maximum target value and a minimum target value and the average signal values comprise an average maximum value and an average minimum value. The method of claim 1 wherein the sampling occurs at a lower data rate than a data rate of the received signal. A method of adapting equalizer setting comprising: processing a received signal with an equalizer to create an equalizer output; filtering the equalizer output to generate a filtered signal; processing the equalizer output with a re-timing module to isolate a clock signal; processing the clock signal to generate a sampling clock; sampling the filtered signal to generate a first sampled equalizer output, the sample timing controlled by the sampling clock; processing the first sampled equalizer output with the controller to calculate a target value; sampling the equalizer output to generate a second sampled equalizer output, the sampling timing controlled by the sampling clock; processing the second sampled equalizer output to calculate an average maximum signal value; comparing the target value with the average maximum signal value; based on the comparing, calculating a boost signal; and providing the boost signal to the equalizer to control the amount of equalization applied to the received signal. The method of claim 7 wherein the filter isolates low frequency components in the received signal. The method of claim 7 wherein the target values comprise a minimum target value and a maximum target value. The method of claim 7 wherein the sampling occurs with an analog to digital converter and the sampling occurs at a lower data rate than a data rate of the received signal. The method of claim 7 wherein the second sampled equalizer output represents low and high frequency components of the received signal. The method of claim 7 wherein sampling clock is created by a phase interpolator. A system for controlling the amount of equalization applied to a received signal comprising: an equalizer configured to perform equalization on a received signal to generate an equalized signal; a clock recovery module configured to recover a clock signal from the equalized signal; a clock adjustment system configured to receive the clock signal and at least one control signal and create a sampling clock signal; a filter configured to filter the equalized signal to create a filtered signal; a sampling unit configured to sample the filtered signal or the equalized signal to create a sampled filtered signal and a sampled equalized signal; a controller configured to receive and processes the output of the sampling unit to generate a boost signal, the controller further configured to provide the boost signal to the equalizer to control the amount of equalization performed by the equalizer. The system of claim 13 wherein the equalizer comprises a continuous time linear equalizer. The system of claim 13 wherein the clock recovery module comprises a clock and data recovery module. The system of claim 13 wherein the clock adjustment system comprises a phase interpolator and a phase detector. The system of claim 13 wherein the sampling unit comprises an analog to digital converter. The system of claim 13 wherein the filter is a low pass filter. The system of claim 13 wherein during a first phase of operation the controller receives a sampled filtered signal and during a second phase of operation the controller receives a sampled equalizer output. The system of claim 13 wherein the sampling by the sampling unit occurs at a lower rate than a data rate of the received signal.