FR 3096172 A1 20201120 FR 1904958 A 20190513 Description Title of Invention: Transfer Printing for RF Applications [0001] The present invention concerns transfer printing for RF applications and in pai-ticuhu- micro transfer printing of GaN components onto an SOI wafer. [0002] GaN is a relatively new technology compared to other semiconductors, such as Si and GaAs, but it has become the technology of choice for high-RF, power-hungry applications like those required to transmit signais over long distances or at high-end power levels. GaN transistors provide high power density, high operating temperatures, improved efficiency, low on-resistance, and they can be operated in different frequency bands ranging from 1 GHz w 110GHz. Figure 1 shows a schematic diagram of a cross-section of a GaN transistor 2. The GaN layer 4 is formed on a high resistivity (HR) silicon substrate 6 and an AlGaN buffer layer 8. Heavily doped n++ reeions 10 of the GaN are connected to metal contacts 12 (drain and source). The gate 14 is isolated from the GaN layer 4 by a thin MN layer 16. [0003] GaN-on-SiC combines the high power density capabilities of GaN with the superior thermal conductivity and low RF losses of SiC (Silicon Carbide). GaN-on-SiC is the combination of choice for high power density RF performance. [0004] GaN-on-Si combination has a much poorer thermal performance and hieher RF losses but is cheaper. GaN-on-Si is the combination of choice for price-sensitive power electronics applications. [0005] Silicon on insulator (SOI) technology is used in semiconductor manufacturing, es- pecially microelectronics, to reduce parasitic capacitance by having a layered siliconinsulator-silicon substrate structure (rallier than buik Si). SOI CMOS provides lower power consumption for analogue and digital RF mixed circuits in the design of low power RF transceivers thanks to iLs low leakage capabilities. [0006] To achieve some of the advantages of both GaN and SOI in high power applications, attempts have been made to grow GaN on SOI, usine french etching to isolate GaN transistors. Careful strain engineering is required to control the stress built up in the wafer during growth. [0007] Altcrnativcly, micro-transfer printing [1] can be used to transfer a GaN device from a native/source wafcr to a target SOI wafer. In this process, the GaN device is dctached/ lifted from the native wafer it was grown on and re-attached on the SOI wafer. [0008] 1] R.Lcner, and ail "Heterogeneous I ntcgration of Microscalc Gallium Nitride Transistors by Micro-Transfer-Printing". 2016 IEEE 66th Electronic Components and Technology Conference, pp 1186-1189. [0009] Aspects of the present invention provide semiconductor structures for RF ap- plications and methods of manufacturing such as set out in the accompanying daims. 2 [0010] Preferred ernbodirnents of the invention will now be described, hy way of example only, with reference to the accompanying drawings. [0011] [fig.1] Figure 1 is a schematic cross-section of a GaN transistor on a sil icon substratc ; [0012] [fig.2a] Figure 2a is a schematic diagram of a monolithic hyhrid switch hranch according to an embodiment; [0013] [fig.2h] Figure 2h is a schematic diagram of a cross-section of a scmiconductor structure according to an embodiment, the structure having a GaN transistor microtransfer printcd onto a SOI wafer; [0014] [fig.3a] Figure 3a shows the layout of an SPDT (Single Pole Double Throw) switch using hyhrid branches according to an embodiment; [0015] [fig.3h] Figure 3h shows the layout of an SPDT using pure GaN branches according to an embodiment; [0016] [fig.4] Figure 4 is a circuit diagram of a semiconductor structure according to an em- bodiment; [0017] [fig.5] Figure 5 is a circuit diagram of a semiconductor structure according to another embodiment; [0018] [fig.6] Figure 6 is a circuit diagram of a semiconductor structure according to another embodiment; [0019] [fig.7] Figure 7 is a circuit diagram of an SPDT switch according to an embodiment; [0020] [fig.8] Figure 8 is a circuit diagram of an SPDT switch according to another em- bodiment; [0021] [fig.9] Figure 9 is a circuit diagram of an SPDT switch according to an embodiment with hybrid switching branches; [0022] [fig.10] Figure 10 is a circuit diagram of an SPDT switch according to another em- bodiment with hybrid switching branches; [0023] [fig.11] Figure 11 shows a schematic diagram of an amplifying cell according to an embodiment; [0024] [fig.12] Figure 12 is a circuit diagram comprising a Low Noise Amplifier (LNA) according to an embodiment; [0025] [fig.13] Figure 13 shows graphs with simulated 2 port S-parameters of an LNA according to an embodiment plotted against frequency; [0026] [fig.14] Figure 14 shows the simulated noise figure (NF) on the left and K factor on the right of an LNA according to the embodiment plotted against frequency; [0027] [fig.15] Figure 15 shows the upper and lower 01P3 as a function of the central frequency of an LNA according to the embodiment; [0028] [fig.16] Figure 16 is a circuit diagram of a serniconductor structure according to an embodiment; 3 [0029] [fig.17] Figure 17 is a circuit diagram of a semiconductor structure according to another cmhodi ment; [0030] [fig.18] Figure 18 is a circuit diagram of an LNA with a cascodc structure according to an embodiment; [0031] [fig.19] Figure 19 is schcmatic diagram of a two stage amplifier according to an cm- bodiment; [0032] [fig.20a] Figure 20a is an cicctrical schcmatic of a two stage amplifier; [0033] [fig.20h] Figure 201, is an clectrical schcmatic of a two stage amplifier according to an embodi ment using micro-transfer printcd GaN transistors for the second stage; [0034] [fig.21] Figure 21 is a circuit diagram of an LNA according to an ernbodiment using micro-transfer printed GaN transistors; [0035] [fig.22] Figure 22 is a circuit diagram of a two stage LNA according to an cm- bodiment using micro-transfer printcd GaN transistors for the second stage; [0036] [fig.23] Figure 23 is a circuit diagram of a two stage LNA according to another cm- bodiment using micro-transfer printcd GaN transistors for the first and second stage; [0037] [fig.24] Figure 24 is a circuit diagram of an N stage LNA according to an cm- hodimcnt using micro-transfer printcd GaN transistors; and [0038] [fig.25] Figure 25 is a circuit diagram of an N stage LNA according to anothcr em- bodiment using an SOI cascode structure and micro-transfer printed GaN transistors. [0039] More and more applications nowadays require high lincarity, high power handl ing, low noise figure and low power consumption. As these requirements are in most cases antagonistic, they are very hard to achieve in MMIC (Monolithic Microwave Integrated Circuit) circuit y. For that reason, it is common to use system in package (SiP) techniques to enclose in a single module several integrated circuits from several technologies, to benefit from the best of each one of them. Dies will then be connected together using bonding wires or bumps. This SiP technique allows a system level integration of several dies/technologies. [0040] Embodiments described herein allow monolithic integration of the GaN and SOI technologies by micro-transfer printing. The CMOS devices as well as the highelectron mobility transistors (HEMTs) are fabricated separately in their process environments and can have different wafer diarneters. The idea will be to design most of the circuit on SOI technology and print only a few HEMTs on the top of the SOI wafer to enhance the overall RF circuit performance. [0041] An advantage of this technique is having a monolithic circuit resulting in a smaller, cheaper and less complex circuit than a system in package. In addition to the reduction of the complexity and cost, this heterogeneous design method can achieve better control of parasitic elements and performance. Another advantage is linked to the GaN transistor performance. The vertical isolation of the existing GaN on Silicon technology is poor. The micro-transfcr printing can significantly rcducc this vertical leakage and thug improvcs the HEMT voltage hrcakdown. [0042] This heterogencous design tnethod allows the l'est of both GaN and SOI to he combined. Thus, achicving good Noise Figure (NF), gond isolation and vcry high power handling capabilities with high intcgration in one single chip is possible. [0043] Base station applications requirc the switches to handlc a large power ranging from a fcw watts (W) up to more than 100 W. Actual switching solutions arc ohtaincd using PIN diodes, which arc able to handlc large powcrs. Thc major drawback is thcir static power consumption decreasing the ovcrall energy cfficiency of the systcm. GaN transistors may hc a scrious contcndcr as thcy show high power handling, low static power consumption (cssentially duc to gatc leakage) and also good lincarity comparcd to MOS transistors. [0044] On the othcr hand, SOI is the lcading technology for switching applications. SOI MOS transistors offcr rcally gond low power performances with low RonxCoff (R' x Coff, key figure of ment, FOM, of switchcs). SOI is a cost effective technology for RF systcm on chip (SOC) for applications up to 10 GHz without significant performance loss, and also reduces cross-talk. To attain such performances it is required to use advanced SOI technology with low voltage sustaining, which is the only drawback of the technology. [0045] Thc power handling capability can hc cnhanced by stacking multiple transistors, but is limited due to a saturation effect of stacked transistors: Zhu, Y., Klimashov, O., & Baille, D. (2014, November). "Analytical model of voltage division inside stackedFET switch". In 2014 Asia-Pacific Microwave Conference (pp. 750-752). IEEE. [0046] According to an embodiment, GaN micro-transfer printing (pTP) on a SOI wafer enables monolithic designs with shorter interconnections, which can prevent losses and transitions between chips and substrates. Interconnections are provided directly between the two stacked chips with metal (e.g. thick copper) a.k.a. redistribution layer (RDL). When micro-transfer printing, one or more chiplets each containing one or more GaN devices is lifted from the native Silicon substrate and placed on the SOI wafer. [0047] Embodiments described herein can overcome SOI and GaN technology bottlenecks by combining them using micro-printing technology. In one embodiment, at least some of the existing problems are solved by a hybrid branch. It is composed of one or several stacked GaN p-Hemt (high electron mobility transistor) and stacked SOI MOS devices. [0048] Figure 2a shows a schematic diagram of a monolithic hybrid switch branch 18. The branch 18 has two or more stacked SOI MOS transistors 20 connected in sertes with two or more stacked GaN p-Hemts 22. The stacked SOI transistors 20 are controlled by a SOI gate control network 24 and the stackcd GaN transistors arc controllcd by a GaN gate control nctwork 26. In this configuration, the Coff is driven by the lowest value (SOI transistor) and the Ron is determined by the highest value (GaN transistor). It is possible to choose a trade-off while sizing hoth transistors to achieve specified isolation, return loss and insertion loss. The second parametcr to take into account is the voltage distribution across the transistors. GaN irnpcdance is much lower than that of a MOS transistor in the OFF state. It is necessary to use large MOS transistors to match the GaN impedance in the OFF state. This combination of GaN and SOI technologies can offer enhanced low power performance comparcd to GaN alone and allows improvcd high power handling comparcd to SOI alone. [0049] Figure 3a shows a top vicw of the layout of a GaN and SOI hybrid design 30 and Figure 3h shows a similar top vicw of a design 32 purcly using GaN p-Heurt (stil) micro-printed on an SOI wafer) for comparison. Both layouts represent single pole double throw (SPDT) switchcs. The operating frequency band of the designs ranges from DC to 6 GHz. The power handling required is 47 dBm and sizes arc optimized to achieve the lowcst insertion loss at 6 GHz. The top thick copper layer 34 connects the GaN transistors to SOI components. [0050] The simulated performances of hoth SPDT designs arc shown in table 1. The per- formances arc taken at chip love' and no de-cmbedding was applicd. Interconnections arc simulatcd using Momentum clectromagnetic simulator from Kcysight whilc transistors are either taken as an electrical model for the GaN transistors or an extracted view for the SOI transistors. Except for return losses, the hybrid combination exhibits better performance across all considered operational bandwidths. Isolations are enhanced by an average 5 dB. [0051] Table 1 - Simulated performance of SPDT designs [0052] [Table 1] Freq.( GHz) RL(dB) IL(dB) Iso AtoRF(dB) Iso RFtoRF(dB) Pure GaN Hybrid Pure GaN Hybrid Pure GaN Hybrid Pure GaN Hybrid 1 43.1 32.8 0.47 0.49 24.3 29.6 24.8 30.1 3 35.5 25.9 0.58 0.58 16.2 21.2 16.7 21.7 6 27.6 19.9 0.94 0.76 10.5 15.7 11.1 16 [0053] Figures 4 to 9 show circuit diagrams of embodiments described herein. Similar or conesponding features of embodiments in diffèrent figures have been given the same reference numerals to aid understanding. Figure 4 shows a MTP (i.e. micro transfer printed) GaN transistor 40 (i.e. a GaN transistor micro-printed onto a SOI wafer) with 6 a resistor 42 conncctcd to the gatc of the transistor 40. The resistor 42 is formed on the SOI and/or on the pTP GaN chiplet. Thc resistor formcd on the SOI wafer can lie connected to the GaN transistor 40, aftcr micro-printing, hy a thick copper redistribution layer (RDL). [0054] Figure 5 shows two pTP GaN transistors 40 in stries. Both transistors 40 arc connected to thcir respective rcsistors 42 on the SOI wafer/dic (`die' referring to the diced chip alter cutting the wafer). Each resistor 42 may have the sanie or différent resistances. Both transistors 40 arc preferably transferrcd to the SOI wafer in the sanie proccss step. Having two or more GaN transistors in stries in a switching branch on an SOI wafer/die can improve the switching performance hy incrcasing the maximum voltage that can be handled Each pTP GaN transistor 40 should be able to handl° a pcak voltage of about 50 V. Two transistors in stries would idcally support a 100 V RF voltage which corresponds to 50 dBm/100 W (with a 50 Q load). It may be beneficial to have some margin on the power handling, and thus one or several further transistors can be addcd in stries to decrease the drain to source voltage across the first two transistors. The power handling can be increased hy stacking more GaN transistors. [0055] Figure 6 shows a p.TP GaN transistor 40 in stries with one or more SOI transistors 44. The gate of the GaN transistor 40 is connected to a resistor 42 and the gates and the bodies of the SOI transistors arc conncctcd to thcir respective rcsistors 42. Thc rcsistors 42 conncctcd to the SOI transistors 44 arc made on SOI. The resistor 42 connected to the GaN transistor 40 could be made in either GaN or SOI. The GaN transistor 40 can be connected to the SOI resistor 42 and to the SOI transistors 44 by a thick copper RDL. [0056] Figure 7 shows a SPDT switch 46 circuit diagram according to an embodiment. The two switching branches 48 and 50 are connected to RF port 1 52 and RF port 2 54 respectively and to an antenna 56. Each branch comprises three pTP GaN transistors 40 in series. [0057] All the gates are connected to a resistor 42 in parallel with a diode 58. The purpose of the resistor 42 is to avoid any RF leakage from the drain or source to the gate, as well as having a floating RF node at the gate so the gate power level moves in sync with the drain or source. The purpose of the diode 58 is to give a path to the pTP GaN gate DC current. Without this diode 58, the DC gate current would create a voltage drop across the gate resistor Rg and the voltage actually applied to the gate would be the DC Mas modified by this voltage drop. This could become a problem in the OFF state, where the DC gate current is not negligible. The gate voltage can be modified significantly by this voltage drop, so the transistors 40 would be less open than expected. [0058] All the gates are biased using a Mas block 60, which delivers a negative voltage to turn the switch OFF. The pTP GaN switches are nornnally ON, thus applying the 7 ground on the gate is sufficicnt to turn it ON. A switch driver 62 is uscd to deliver the right DC voltage on the right gate. Other architectures could have 1, 3 or 4 arms/ branches etc connected to respective RF ports. [0059] Figure 8 shows a circuit diagram, similar to that in Figure 7, but with only two pTP GaN transistors 40 in cach switching hranch 48 and 50. Each gatc of the transistors 40 is connected to a resistor 42 in parallel with a diode 58. [0060] Figure 9 shows a circuit diagram of an SPDT switch 46 with hyhrid branches 64 and 66. Each hranch comprises one pTP GaN transistor 40 and stackcd SOI transistors 44. A second Nias block 68 and switch driver 70 arc uscd to control the SOI transistors 44, although in other embodiments a single Nias block and switch driver can be uscd to control all the GaN transistors 40 and the SOI transistors 44. Figure 10 shows a circuit diagram of a similar SPDT switch 46, but with two pTP GaN transistors 40 in stries in cach hranch 64 and 66. [0061] Although cach of Figures 7 to 10 illustrates an architecture with two switching branches, the designs can be extended to comprise furthcr switching branches. For example, an embodiment can comprise four RF ports, cach connected to a switching hranch comprising one or more pTP GaN transistors. The architecture can be gencralized to an NPMT switch (with N antennas and M RF ports, i.c. N Polos and M Throws). [0062] One embodiment comprises a Low Noise Amplifier (LNA) using a heterogencous in- tegration of GaN technology with SOI technology to enhance the linearity of the circuit. [0063] Figure 11 shows a tell 74 that can be used in an LNA according to an embodiment for amplifying an RF signal. The tell 74 comprises a common source SOI nMOS transistor 76 in series with a common gate rnicro-printed GaN HEMT78 forming a cascode structure (having a common source transistor directly in series with a common gate transistor). [0064] An advantage of this topology is the improvement of the overall linearity of the SOI technology using a discrete GaN HEMT. These µTP GaN transistors are able to handle a large supply voltage which is the main weakness of silicon-based transistors. It enables the structure to develop larger output power and therefore larger IP3 (FOM used to characterize LNA linearity). Furthennore. the GaN HEMT is used as a cascode because the IP3 of a system composed of n-cascaded stages is imposed by the last stage as shown in Equation 1. (I) 8 [0065] For these rcasons, using the GaN as the cascade transistor will improve the LNA lincarity performances (OIP3, Output third order interception point) comparcd to using a full SOI LNA. [0066] Another rcason to use this heterogeneous oeil 74 is to providc low continuons power consumption compared to pure GaN designs. The SOI technology provides low leakage as well as a low current MOS transistor, which can he particularly advantagcous for this application. [0067] An LNA design 80 is shown in Figure 12. It uses a degenerated LNA architecture including the tell 74 with the SOI transistor 76 and pTP GaN transistor 78 shown in Figure 11 used as an amplifier coll. The different passive and active parts arc implemented on PCB 84, formed on SOI 82 (i.e. native SOI cornponcnts), or microprintcd (i.c. the pTP GaN transistor 78). The SOI chip can he flip-chipped on a PCB for characterization purposcs. [0068] The LNA can satisfy the 5G NR (suh 6GHz) standard. The operating hand is from 5.9GHz to 7.1GHz and corresponds to a US unlicensed hand. The supply voltage is set to 5.5V and corresponds to typical hase station voltage. The common source transistor gate voltage is set to achieve the IP3 spécification of 28 dBm across the hand. The common gatc Nias voltage is thon adjustcd so the nMOS drain voltage is set to 1.2 V, which is its typical value. [0069] The circuit was simulated and the 5-parameter simulation results arc shown in Figure 13 and the NF 86 and K factor 88 in Figure 14. The continuous power consumption was 165 mW. The input and output are well matched to 50 Q in the band. The amplifier exhibits 16.6 dB of gain at maximum in the band and a minimum isolation of -26 dB. The amplifier is unconditionally stable up to 10 GHz. NF is lower than 1.7 dB in the band with a minimum of 1.24 dB at 6.8 GHz. [0070] The 01P3 simulated results are given in Figure 15. The power of the two input fun- damental tones was set to -30 dBm with a 1 MHz tone separation. The upper 01P3 90 and lower 01P3 92 are above 28 dBm from 6.35 GHz up to 7.1 GHz. The maximum 01P3 is 30.6 dBm at 6.8 GHz. [0071] All the performances as well as the specifications are summarized in Table 2 and given at 6.5 GHz, which is at the middle of the band. [0072] Table 2 - DC, small signal (SP), and noise (NF) performance summary [0073] 9 [Table 2] Heterogeneous LNA Specification Unit DC power 110 165 mW Frequency 5.9-7.1 5.9-7.1 GHz Gain 16.2 >15 dB NF 1.28 1.7 dB 511 -14.5 -10 dB S22 -41 -10 dB 512 -26 -20 dB 01P3 30.6 28 dBm [0074] Table 3 compares the LNA design with existing products. Performance is equivalent except for the power consumption which is reduced by a factor 3 compared to analog devices and a factor 5 compared to Qorvo [3]. The size of the chip is not representative as it is a demonstrator. [0075] Table 3 - Comparison with existing devices [0076] [Table 3] Productref. Technology Freq (GHz) Supply (V) Idc (na) Gain (dB) Analog devices HMC392A 12] GaAs 3.5-7 5 59 17.2 Qorvo GaN on SiC TQGaN25 2-6 10 110 25 TGA2611 [3] Standard LNA 0.1pm GaN on XR013 5.9-7.1 5.5 20 16.2 10077] Table 3 continued 10078] [Table 3] Productref. Technology 01P3 (dBm) NF (dB) S 1 I (dB) S22 (dB) Area (mm2) Analog dcvices HMC392A [2] GaAs 32.5 1.7 12 18 1.3 Qorvo GaN on SIC TQGaN25 32 1.5 >10 >10 3.15 TGA2611 [3] Standard LNA 0.1pm GaN on XR013 30.6t 1.28 14.5 41.3 2.48 [0079] HMC982A-Die: GaAs MMIC Low Noise Amplifier, 3.5-7.0 GHz Data Sheet, https://www.analog.com/en/products/hmc392a-die.html#product-documentation [0080] Preliminary Product Data Sheet TGA2611 2-6GHz GaN LNA, https://w [0081] ww.gorvo.com/products/p/TGA2611 [0082] The micro-printing technique enables the co-integration of different technologies on die level. The performance of the circuit can be enhanced whilst maintaining its small area. [0083] Figure 16 shows a cell 94 for an LNA or a PA with two !HP GaN p-Heurts 96 in series on an SOI wafer/die. The pTP GaN transistors could be on the same chiplet or on separate chiplets. Figure 17 shows a cell 94 for an LNA with a RTP GaN p-Hemt 96 with an inductor 98 connected to its source. The inductor 98 is formed on the SOI wafer and connected to the GaN HEMT with RDL. [0084] Figure 18 shows a circuit diagram of an LNA design 80 comprising a cascode cell 74 comprising an SOI transistor 76 in series with a µTP GaN p-Hemt 78 and a linearizer 100 between both transistors to improve linearity. The diode in series with the capacitance in parallel with the resistor permits to a non-linear current to be generated at the third order inteimodulation frequency to cancel the MOS drain component at the same frequency. The linearizer 100 is formed on the SOI wafer. [0085] Another LNA design for satisfying the 5G millimeter wave standard is desclibed. It is designed using two stages 102 and 104 in cascade as shown in Figure 19. The IP3 of the overall system when cascading n stages is imposed by the last stage as expressed by Equation 1. [0086] Thus, using the GaN for the second stage LNA 104 will improve the LNA linearity performance (IIP3 and CP1) compared to using full SOI LNA. For the first stage 102, an SOI transistor can be used to benefit lrom its gond noise performance. [0087] To evaluate the advantage of using the GaN in the second stage, two circuits were designed at 28 GHz: 11 - The first one using full SOI architecture for the first and second stages. - For the second design, a GaN transistor was employed for the second stage. [0088] The schernatics of the two LNAs is shown in Figures 20a and 20h respectively. In Figure 20a two stages 106 and 108 mounted in cascode were cascaded for the fully SOI circuit. Conccrning the heterogeneous LNA in Figure 20h, the first stage 110 is in cascode. As the nominal drain source voltage for the GaN transistor 112 should be higher than the SOI transistors, the second stage 114 is dcsigned using common source architecture. The purpose is to use the same power supply as the first stage 110. [0089] The simulatcd DC, small signal (SP) and noise (NF) performances of the two LNA versions arc summari7ed in Table 4. The performance is si milar between the two versions and hoth of them satisfy the spccification (i.c. the 5G standard requirements). [0090] Table 4 - DC. small signal (SP) and noise (NF) performance of two LNA versions [0091] [Table 4] Fully SOI LNA Heteroge-nous LNA Specili-cation Unit DC power 29.5 (2.4V * 12.3 mA) 29.5 (2.4V * 12.3 mA) 30 mW Fre-quency 27.5-30.5 27.5-30.5 27.5-30.5 GHz Gain @ 29G 16.3 15.2 15 dB Max Gain 17.2 16.3 15 dB NF @ 29 G 3.7 3.4 4 dB Sll -17.7 -15 -10 dB S22 -13.9 -23.7 -10 dB S12 -46.1 -20.9 -20 dB Kf > 1.4 >1 >1 [0092] Two figures of merit are used to quantify the linearity of circuits: - Input compression point CP1. - Input third intercept point 1iP3. [0093] The use of the GaN transistor 112 in the second stage 114 improves these parameters by almost 10 dB. The simulated CP1 of the heterogeneous solution is about -13 dBm versus -21 dBm for the full SOI LNA. Concerning the 1P3, the simulation showed 6 dBm for the heterogeneous LNA and -10 dBm for the full SOI version. [0094] The designed LNA with the micro-printed GaN transistor has been benchmarked with other LNAs dcsigned with different technologies which prcsent hieh intcgration capabilities (CMOS and SiGc). As can he seen in Table 5, the LNA described hercin 12 presents higher lincarity thanks to the use of the GaN on SOI transistor with comparable performances of the other parameters. [0095] Table 5 - LNA henchmarking [0096] [Table 4] Unit [4] [5] [6] [7] LNA embodiment Process 130 nm CMOS 40 nm Bulk CMOS 90 nm CMOS 0.25 pm SiGc GaN/130 nm SOI Topology 3-stage cascode 3-stage 2-stage cascode 3-stages 2-stages Frequency GHz 27.2 27.1 28.5 29 29 Pdc mW 24 31.4 16.25 134 29.5 Gain dB 20 27.1 20 26.4 15.2 NF dB 5.2-7.5 3.3-4.3 2.9-4.2 2.1-3.5 3.4 CP1 dBm -21.6 -17 -14.9 -13 IIP3 dBm -12.6 -7.5 -5 6 [0097] J.Luo, and all "A 28 GHz LNA using defected ground structure for 5G application". Microw Opt Technol Lett. 2018;60 1067-1318. 100981 M.Elkholy, and all "A Wideband Variable Gain LNA With High 01P3 for 5G Using 40-nm Bulk CMOS". 2017 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS. 100991 E.Adahi, B. Heydari, M. Bohsali, and A. M. Niknejad, "30 GHz CMOS low noise amplifier," in Proc. IEEE Radio Freq. Integr. Circuits (RFIC) Symp., Jun. 2007, pp. 625-628. 101001 Q. Ma, D. M. W. Leenaerts, and P. G. M. Battus, "Silicon-hased truetime-delay phased-array front-ends at Ka-band," IEEE Trans. Microw. Theory Techn., vol. 63, no. 9, pp. 2942-2952, Sep. 2015. 101011 Figure 21 shows a circuit diagram of an LNA 116 according to an embodiment. The LNA 116 comprises a pTP GaN transistor 112 on SOI connected to other SOI components. The source of the GaN transistor is connected to an inductor 118 formed on the SOI wafer. 101021 Figure 22 shows a circuit diagram of a two stage amplifier 120 comprising two connected LNAs 116 and 122. The first LNA 122 (the first stage) comprises two SOI transistors 124 in a cascode structure and the second LNA 116 (the second stage) comprises a pTP GaN transistor 112 in common source. The second LNA 116 is 13 equivalent to the one shown in Figure 21. A single Nias block 126 formcd on the SOI wafer is used ta power hoth stages 116 and 122. Both stages 116 and 122 prcferahly use the sanie power supply. [0103] Figurc 23 shows a circuit diagram of anothcr two stage amplifier 120 comprising two connected LNAs 116 on an SOI wafer/die. Both LNAs comprise a respective itTP GaN transistor 112 in common source. [0104] Figurc 24 shows a circuit diagram of an N stage amplifier 124 (with N > 2 ampli- fication stages) according ta an embodiment. Three LNAs 116a,b,c arc shown and a dottcd line hetwecn the output of the second LNA 11611 and the input of the third LNA 116c indicates an arhitrary numbcr of furthcr LNAs connected in hetwecn Each amplification stage can bc formcd from an LNA such as the one illustrated in Figure 21. Each LNA comprises onepTP GaN transistor 112. Each LNA 116a,b,c can he powercd hy the same power supply or by separate power supplies. The Nias block 126 and othcr components of the circuit arc formcd dircctly on the SOI wafer. [0105] Figurc 25 shows a circuit diagram of an N stage amplifier sitnilar to that of Figure 24, but where the first stage comprises an SOI cascodc structure 122 with SOI transistors 124. [0106] While spccific cmhodiments of the invention have hcen described ahove, it will he appreciated that the invention may be practiccd otherwisc than as described. Thc descriptions ahove arc intended to he illustrativc, not limiting. It will be apparent to one skilled in the art that modifications may be made to the invention as described without departing from the scope of the daims set out below. [0107] Each feature disclosed or illustrated in the present specification may be incorporated in the invention, REVENDICATIONS1. A scmiconductor structure for RF applications comprising: - a first pTP GaN transistor on an SOI wafcr or die; and - a first resistor connected to the gatc of said first transistor. A scmiconductor structure according to daim 1, furthcr comprising: - a second pTP GaN transistor on the SOI wafcr or die; and - a second resistor connected to the gatc of said second transistor. A scmiconductor structure according to daim 1 or 2, furthcr comprising: - an SOI transistor formed on said SOI wafer in series with said first pTP GaN transistor; - a second resistor connected to the gate of said SOI transistor; and - a third resistor connected the body of said SOI transistor. A semiconductor structure according to daim 1, 2 or 3, further comprising two or more stacked SOI transistors foimaed on said SOI wafer in series with said first .iTP GaN transistor. A semiconductor structure according to any one of daims 1 to 4, further comprising: - a first switching branch comprising one or more mTP GaN transistors on the SOI wafer and connected to a first RF port; - a second switching branch comprising one or more pTP GaN transistors on the SOI wafer or die and connected to a second RF port, wherein each µTP GaN transistor in the first and second switching branch has a gate connected to a respective resistor. A semiconductor structure according to daim 5, wherein the first and second switching branches each comprises three pTP GaN transistors. A semiconductor structure according to daim 5 or 6, wherein each respective resistor is connected in pai-allel to a diode. A semiconductor structure according to daim 5, 6 or 7, wherein said GaN transistors in said first switching branch and/or said µTP GaN transistor in said second switching branch are on the same chiplet. A semiconductor structure according to any one of daims 5 to 8, further comprising: - a switch driver formed on the SOI wafer and connected to said first and second switching branches; - a bias block connected to said switch driver. A semiconductor structure according to any one of daims 5 to 9, 15 whcrein the first and second switching branches cach comprises stacked SOI transistors connected in stries with said one or more pTP GaN transistors. [Claim 11] A semiconductor structure according to claim 10, further comprising a second switch driver and a second Nias block formed on the SOI wafer for controlling said stacked SOI transistors. [Claim 12] A semiconductor structure according to any preceding daim, whcrein said structure is an SPDT switch. [Claim 13] A semiconductor structure according to any one of daims 5 to 11, furthcr comprising one or more furthcr switching branches, wherein the or cadi further switching branch comprises one or more '1TP GaN transistors on the SOT wafer or die. [Claim 14] A semiconductor structure according to claim 13, wherein said structure is an NPMT (N Poles and M Throws) switch. [Claim 15] A semiconductor structure for amplifying an RF signal comprising: - a cascode structure comprising a pTP GaN transistor on an SOI wafer or die. [Claim 16] A semiconductor structure according to claim 15, wherein said cascodc structure further comprises an SOI transistor formed on the SOI wafer and connected to said pTP GaN transistor. [Claim 17] A serniconductor structure according to daim 15, wherein said cascode structure further comprises a second pTP GaN transistor on the SOI wafer or die and connected to said VIT GaN transistor. [Claim 18] A serniconductor structure according to daim 15, 16 or 17, further comprising an inductor connected to the source of said pTP GaN transistor. [Claim 19] A serniconductor structure according to any one of daims 15 to 18, further comprising a linearizer formed on the SOI wafer. [Claim 20] A serniconductor structure for amplifying an RF signal comprising: - a first LNA on an SOI wafer; and - a second LNA on the SOI wafer connected to said first LNA, wherein said second LNA comprises a pTP GaN transistor. [Claim 21] A serniconductor structure according to daim 20, wherein said first LNA comprises a cascode structure comprising a first and a second transistor in selles. [Claim 22] A semiconductor structure according to daim 21, wherein said first and/or said second transistor is a SOI transistor formed on the SOI wafer. 16 [Claim 23] A semiconductor structure according to claim 22, wherein said first LNA comprises a pTP GaN transistor. [Claim 24] A semiconductor structure according to any one of daims 20 to 23, further comprising one or more further LNAs on the SOT wafer connected together so as to amplify an RF signal applicd to said first LNA when in use. [Claim 25] A semiconductor structure according to any one of daims 20 to 24, wherein the first and second LNAs arc powcred by the sanie power supply. [Claim 26] A method of manufacturing a structure as claimed in any preceding daim using a micro transfer printing process.