Brevet FR3042049A1 (20170407)
REVENDICATIONS1) a computer system where - a host processor is connected to one or several memory chips, these memory chips integrating one or several data processors, the connection between these memory chips and the host processor being done by a data bus wider than the data port of these memory chips, these memory chips being connected to the data bus in a data parallel fashion to accommodate the data bus width. - a linear, or linear by segment, address space, is defined, this address space enabling to access linearly, or linearly by segment, the memory of each memory chip, - an address conversion function between this new address space and the original address space of the host processor, enables the host processor to access this new address space.\n<CLM>\1\tThe system of claim 1 where the address conversion function is implemented directly in hardware,\n<CLM>\1\tThe system of claim 2, where the address conversion hardware function is configurable, and where this function changes according to configurable memory segments.\n<CLM>\1\tThe system of claims 1-3 where - the new address space comprises itself sub-address spaces, these sub-address spaces being used by the data processors integrated into the memory chips, providing them a linear, or linear by segment, access to their accessible memories, - these sub-address spaces are linearly, or linearly by segment, mapped into the new address space.\n<CLM>\1\tThe system of claims 1-4 where - the host processor has a data cache, or an universal cache equally acting as a data cache, - a cache line permutation is done in order to change the address conversion function, and make this later linear by segment, enabling the host processor to correctly access the memory accessible to the data processor integrated into the memory chips, when the host processor uses load, store, or any instruction accessing the memory, whose memory access width is wider than the data port of the concerned memory chips.\n<CLM>\1\tThe system of claims 5 where the cache line permutation is done entirely by software.\n<CLM>\1\tthe system of claim 5 where the cache line permutation is done entirely by hardware.\n<CLM>\1\tthe system of claim 5 where the cache line permutation is partially done by software, partially done by hardware. 20 3042049\n<CLM>\1\tthe system of claim 5 where the burst data pattern correspond natively to the cache line permutation, this being equivalent to having always a cache line permutation when the cache line is loaded from, or stored to, memory.\n<CLM>\1\tthe system of claim 5, 7 and 8, where - several types of cache line permutations are supported, - configuration means enable to specify address segments, and which kind of cache line permutation has to be done when an access is inside one of these segments.\n<CLM>\1\tthe system of claims 1-10 where - the memory chips integrate one or several command registers wider than the memory chip data port, - a command colour scheme is used, a change in command colour being requested for a new command to be valid in the concerned command register.\n<CLM>\1\tthe system of claims 1-11 where the host processor is an system on chip comprising several processor cores.\n<CLM>\1\tthe system of claims 1-12 where the host processor is a system on chip comprising several memory buses.\n<CLM>\1\ta larger system comprising several system, as defined by the claims 1-13, connected together and belonging to a same cache coherency domain, in order to build a multisocket server.\n<CLM>\1\ta System of claims 1-14 where each given memory chips is enlarged, both in memory capacity and in data port width, in order to allow the transfer, during the totality of a burst transaction, of an ECC code covering the totality of the non enlarged data transferred during this burst transaction from, or to, this given memory chip.\n<CLM>\1\ta System of claims 1-14 where - each given memory chips is enlarged in memory capacity in order to be able to store ECC, - burst transactions are lengthened allowing the transfer of an ECC code during a burst transaction, - such that the transferred ECC code protect the totality of the non ECC data transferred, from, or to, this given memory chip during a burst transaction.\n<CLM>\1\tThe system of claims 1-16 where the data processor is not integrated into the memory chips, but into one or several additional circuits, placed between the host processor and the memory chips.\n<CLM>\1\tA system of claims 1-8/10-17 where the address conversion and/or cache line permutation is/are partially or entirely done inside one or several additional circuits placed between the host processor and the memory chips.\n<CLM>\1\tA computing device comprising: a first processor; 21 3042049 a plurality of memory devices, at least a first of the memory devices integrating one or more further processors; a data bus coupling the first processor to each of the memory devices, wherein each of the memory devices has a data port m bits wide and the data bus has a width of n bits, where n is larger than m, the first processor being adapted to provide a first address for an n-bit data value to be read or written via the data bus, wherein the first processor and/or a further circuit is adapted read or write the n-bit data value to or from the first memory device by: - converting the first address into a plurality of addresses corresponding to m-bit memory locations in the first memory device, at least two of the plurality of addresses being contiguous addresses; and - performing the read or write operation of the n-bit data value to the first memory device over a plurality memory access operations. 22