FR 3072476 A1 20190419 FR 1759623 A 20171013 B16012 17-ZV2-0089 1 LOGICAL MEMORY UNIT FOR FLASH MEMORY FIELD The present disclosure relates ta the field of Flash memories, and in particular ta an interface between a processing unit and Flash memory. BACKGROUND Flash memories are increasingly used in electronic devices as a means of storing data in a non-volatile fashion. Flash memories have advantages over other forms of non-volatile memory, such as EEPROM (electronically erasable programmable read- only memory), in terms of speed. In particular, whereas an EEPROM generally allows individual bytes ta be programmed and erased, in a Flash memory, the granularity for write operations remains relatively low, but the granularity for erase operations is generally at a page or block level. The erase operation itself being relatively slow, the overall speed of the memory can be increasedby onlyperforming erase operations for relatively large memory zones and thereby reducing the number of erase operations that are performed. It would thus be desirable in some applications ta 20 replace EEPROM incorporated in existing processing systems by Flash memory. However, there are technical difficulties in doing sa. Indeed, the memory management in the case of Flash memory is B16012 17-ZV2-0089 2 relatively complex due ta the programming constraints of such a memory. For example, decisions should be made as ta whether ta write new data ta new pages, or whether ta erase existing pages ta make room. Furthermore, the cells of a Flash memory may be 5 subjected ta only a limited number of write cycles, and therefore ta ensure a long overall lifespan of the memory, it is generally an objective of the memory management algorithms ta evenly distribute the memory across the Flash memory array. Modifying the software of a CPU in order ta allow such a complex memory 10 management represents a significant task. There is thus a need in the art for a solution permitting a Flash memory ta be integrated into a processing system in a relatively simple fashion. SUMMARY 15 It is an aim of embodiments of the present description ta at least partially address one or more needs in the prior art. According ta one aspect, there is provided a Flash memory interface comprising: a memory management unit including a comparator configured ta determine whether an address of a Flash memory access operation corresponds ta logical or physical address by comparing the address with one or more address ranges; a logical memory unit configured ta convert logical addresses into physical addresses and ta provide the physical addresses ta the Flash memory; wherein the memory management unit is configured ta direct physical addresses ta the Flash memory and ta direct logical addresses ta the logical memory unit for conversion into physical addresses. According ta one embodiment, the memory management unit further comprises a configuration memory storing an indication of 30 the one or more address ranges. According ta one embodiment, the logical memory unit comprises: an address generator configured ta generate a physical address based on the logical address and on a block identifier identifying one or more blocks in the Flash memory, wherein the 35 address generator comprises an address converter configured ta B16012 17-ZV2-0089 3 convert each logical address into a corresponding block identifier. According ta one embodiment, the address generator comprises one or more of: a storekeeper configured ta manage the 5 use of blocks and/or pages in the Flash memory; a translator configured ta map logical addresses and/or block identifiers ta physical addresses in the Flash memory based on at least one offset; a rotation unit configured ta assign physical addresses in the Flash memory ta logical addresses and/or block identifiers 10 by rotation among the available physical addresses; and a cryptographic circuit configured ta generate physical addresses based on a decryption of the logical address. According ta one embodiment, the memory management unit and the logical memory unit are further configured: ta provide 15 each physical address ta a write controller of the Flash memory if the Flash memory access operation corresponds ta a write operation; and ta provide each physical address ta a read input of the Flash memory if the Flash memory access operation corresponds ta a read operation. 20 According ta one embodiment, the memory management unit is implemented by one of: software executed by one or more processors; or one or more hardware circuits; or a combination of software executed by one or more processor and one or more hardware circuits. 25 According ta one embodiment, the logical memory unit is implemented by one of: software executed by one or more processors; or one or more hardware circuits; or a combination of software executed by one or more processor and one or more hardware circuits. According ta a further aspect, there is provided a data processing system comprising: a processing unit; a Flash memory; and the above Flash memory interface. According ta one embodiment, the Flash memory comprises a program/erase controller. According ta a further aspect, there is provided a method of accessing a Flash memory, the method comprising: B16012 17-ZV2-0089 4 determining whether an address of a Flash memory access operation corresponds to logical or physical address by comparing the address with one or more address ranges; if it is determined that the address is a physical address, directing the physical address 5 to the Flash memory; and if it is determined that the address is a logical address, converting the logical address into a physical address and providing the physical address to the Flash memory. According to one embodiment, the one or more address ranges are stored in a configuration memory. 10 According to one embodiment, converting the logical address into a physical address comprises: converting the logical address into an identifier of one or more blocks in the Flash memory; and generating a physical address based on the logical address and on the identifier. 15 According to one embodiment, generating the physical address based on the identifier comprises one or more of: the management of blocks and/or of pages in the Flash memory by a storekeeper; the mapping of the logical address and/or block identifier to a physical address in the Flash memory based on at 20 least one offset; the assignment of a physical address in the Flash memory to a logical address and/or block identifier by rotation among the available physical addresses; and the decryption of the logical address. According to one embodiment, the method further 25 comprises: providing each physical address to a write controller of the Flash memory if the Flash memory access operation corresponds to a write operation; and providing each physical address to a read input of the Flash memory if the Flash memory access operation corresponds to a read operation. 30 BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other features and advantages will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which: 35 Figure 1 schematically illustrates a data processing system according to example embodiment of the present disclosure; B16012 17-ZV2-0089 5 Figure 2 schematically illustrates a Flash memory of the data processing system of Figure 1 in more detail according to example embodiment; Figure 3 schematically illustrates an interface circuit 5 of the data processing system of Figure 1 in more detail according to example embodiment; and Figure 4 is a flow diagram representing operations in a method of accessing a Flash memory according to an example embodiment of the present disclosure. 10 DETAILED DESCRIPTION Throughout the present disclosure, the term "connected" is used to designate a direct connection between elements, whereas the term "coupled" is used to designate a connection between elements that may be direct, or that may be via one or more 15 intermediate elements such as buffers, capacitors, etc. For clarity, only those steps and elements useful for an understanding of the embodiments of the present disclosure will be described in detail and illustrated in the drawings. Other features, such as the electronic behaviour of a Flash memory 20 during write, read and erase operations, has not been detailed, the described embodiments being compatible with standard Flash memory technologies that will be known to those skilled in the art. Figure 1 schematically illustrates a data processing 25 system 100 comprising a processing unit (P) 102, which for example comprises one or more processors under control of instructions stored in an instruction memory (RAM) 104, which is for example a RAM (random access memory). The processing unit 102 is further coupled to a Flash memory (FLASH) 106 via a memory interface 30 (INTERFACE) 108. The processing system 100 also for example comprises an input/output interface (I/O) 110 coupled to the processing unit 102, allowing communication with other devices. As known by those skilled in the art, while the granularity of operations in an EEPROM is generally at the byte 35 level, in a Flash memory, memory cells are erasable with a higher granularity, for example at the page or block level. For example, B16012 17-ZV2-0089 6 in some Flash memories, it is possible to write individual bytes to the pages of the Flash memory, but the number of times that each page can be written in between erase operations of the page may be restricted to one. Erase operations generally concern a 5 minimum unit size of one page, or of one block, wherein a block for example comprises two or more pages. While in the erased state, the cells of a Flash memory are generally at a logic "1", and cells can subsequently be programmed to maintain the logic "1", or transition to a logic 10 "0". However, once a cell has transitioned to a logic "0", that cell can only be programmed back to a logic "1" by an erase operation. This means that in some cases it may be permissible to program a saine byte more than once between erase operations, as long as this does not involve returning any bit from the logic 15 "0" to the logic "1" state. For example, the byte "1110 1111" could be reprogrammed to "1100 1111". With reference again to Figure 1, it is assumed that the Flash memory 106 has replaced an EEPROM in the data processing system (100). According to embodiments of the present disclosure, 20 rather than modifying the operation of the processing unit 102 to accommodate this change, the Flash memory interface 108 is implemented between the processing unit 102 and the Flash memory 106. For example, the Flash memory interface 108 is implemented in a separate chip to the processing unit 102 and the Flash memory 25 106. Alternatively, the Flash memory interface 108 could be integrated on the Flash memory chip. The processing unit 102 for example knows only that it may access a non-volatile memory, without knowing the particular form of this memory. Thus the processing unit 102 need not take into account the particular 30 programming constraints of the Flash memory, such as the granularity of erase operations, page management, etc. Figure 2 schematically illustrates the Flash memory 106 in more detail according to example embodiment. The Flash memory 106 for example comprises a 35 program/erase controller (P/E CONTROLLER) 202, which is B16012 17-ZV2-0089 7 responsible for writing to and erasing pages or blocks of pages of the non-volatile storage portion 204 of the Flash memory. The non-volatile storage portion 204 for example includes a zone (CODE) 206 storing program code to be executed by 5 the processing unit 102. The non-volatile storage portion 204 also for example comprises one or more physical memory zones (PHYSICAL) (208) and one or more logical memory zones (LOGICAL) 210. The physical memory zones 208 are zones which are accessed by the processing unit 102 directly using physical addresses. The logical 10 memory zones 210 are however accessed by the processing unit 102 using logical addresses. As known to those skilled in the art, while physical addresses directly identify physical memory locations in a memory, logical addresses do not directly correspond to specific physical memory locations, but are seen 15 and treated by the processing unit as if they did. The logical addresses are converted into physical addresses by the Flash memory interface 108. This conversion may be implemented using memory management algorithms and may vary over time. In some embodiments, the processing unit 102 is not aware of which 20 addresses are physical addresses, and which are logical addresses. In some embodiments, the physical address zones 208 are used to store data that is updated relatively rarely, such as certain parameters, encryption keys, passwords, etc. The logical address zones 210 are for example used to store data that is more 25 dynamic, and is likely to be modified on a more regular basis, such as counters, variables, etc. An indication of the address ranges corresponding to the physical and logical address zones 208, 210 is for example stored by or otherwise accessible to the interface circuit 108, as will 30 be described in more detail below. Figure 3 schematically illustrates the Flash memory interface 108 of Figure 1 in more detail according to example embodiment. The interface 108 for example comprises a memory 35 management unit (MIVIIJ) 302 and a logical memory unit (LMU) 304. Each of the units 302 and 304 may be implemented entirely by B16012 17-ZV2-0089 8 hardware, entirely using software executed by a suitable processor (not illustrated), or by a combination of hardware and software. For example, in some embodiments, either or both of the units 302, 304 could be implemented by an ASIC (application specific 5 integrated circuit) and/or by an FPGA (field-programmable gate array). The MMU 302 for example receives, from the processing unit 102, the addresses (ADDRESS R/W) of read and write operations to the Flash memory 106. The MMU 302 for example comprises an 10 address comparator (ADDRESS COMPARATOR) 306, which compares each address with one or more address ranges defining the physical and/or logical memory locations in the Flash memory 106. For example, the MMU 302 comprises a configuration memory (MEM) 308 storing an indication of the address ranges of the physical memory 15 locations and/or of the logical memory locations. The memory 308 is for example accessed by the address comparator 306 in order to determine whether a given address falls within the physical memory address range or the logical memory address range. Addresses falling within the physical address zone 208 are considered to be 20 physical addresses, and are for example forwarded to the Flash memory 106. Furthermore, addresses in the zone 206 of Figure 2 relating to code are also for example considered by the system to correspond to physical addresses, and are for example forwarded to the Flash memory 106. However, addresses falling within the 25 logical address zone 210 are considered to be logical addresses and are forwarded to the LMU 304. In some embodiments, the MMU 302 further comprises a read/write switch (READ/WRITE) 310. Addresses that are identified by the comparator 306 as being physical addresses are for example 30 provided to the Flash memory 106 via the switch 310, which forwards them to a write or read input of the Flash memory 106 based on whether they concern read or write operations. For example, the MMU 302 also receives from the processing unit 102, with the address, a read-enable RE and/or write-enable WE signal indicating 35 whether the operation concerns a read or write operation, and this signal is provided to the switch 310. For read operations, the B16012 17-ZV2-0089 9 address is for example provided directly ta a read input R of the program/erase controller 202 of the Flash memory 106. For write operations, the address is for example provided ta a write control circuit (WRITE CTRL) 311 of the Flash memory 106, which in turn 5 provides the address ta a write input W of the program/erase controller 202. The program/erase controller 202 also for example receives the data ta be written (DATA) from the processing unit 102. The LMU 304 for example comprises a physical address 10 generator (PHYSICAL ADDRESS GENERATOR) 312, which receives the logical addresses from the MMU 302, and generates physical addresses based on the logical addresses. In some embodiments, the generator 312 comprises an address ta block ID converter (ADDRESS TO BLOCK ID CONVERTER) 314, which converts each logical 15 address into a block identifier of the block in the Flash memory containing the physical address corresponding ta the logical address. For example, the generator 312 comprises, or otherwise has access ta, a memory (MEM) 316 and generates the physical address based on reference data stored in this memory. This memory 20 316 stores for example a correspondence table indicating the mapping between block identifiers and physical addresses. The correspondence table is for example updated each time a page or block in the memory is erased, and the physical addresses of the pages and blocks are updated. 25 In one embodiment, the physical address generator 312 comprises a storekeeper (STOREKEEPER) 318 adapted ta manage the storage of data in the Flash memory 106, and in particular ta manage the use of blocks and/or pages in the Flash memory 106. For example, the storekeeper 318 implements the storage method 30 described in French patent application PR 16/54490, corresponding ta European patent application EP 16198176, US patent application US 15/380509 and Chinese patent application CN 201611054274.4, the content of these applications being incorporated herein by reference ta the extent permitted by the law. Furthermore, the 35 storekeeper 318 may additionally or alternatively implement the indexing method described in French patent application B16012 17-ZV2-0089 10 opérations de lecture, l'adresse est par exemple directement fournie à une entrée de lecture R du contrôleur de programmation/effacement 202 de la mémoire Flash 106. Pour les opérations d'écriture, l'adresse est par exemple fournie à un 5 circuit de commande d'écriture (WRITE CTRL) 311 de la mémoire Flash 106, qui fournit à son tour l'adresse à une entrée d'écriture W du contrôleur de programmation/effacement 202. Le contrôleur de programmation/effacement 202 reçoit également par exemple les données à écrire (DATA) de l'unité de traitement 102. 10 L'unité LMU 304 comprend par exemple un générateur d'adresses physiques (PHYSICAL ADDRESS GENERATOR) 312, qui reçoit les adresses logiques de l'unité MMU 302 et génère des adresses physiques à Partir des adresses logiques. Dans certains modes de réalisation, le générateur 312 comprend un convertisseur d'adresse 15 en identificateur de bloc (ADDRESS TO BLOCK ID CONVERTER) 314, qui convertit chaque adresse logique en un identificateur de bloc du bloc de la mémoire Flash contenant l'adresse physique correspondant à l'adresse logique. Par exemple, le générateur 312 comprend ou bien a accès à une mémoire (MEM) 316 et génère 20 l'adresse physique à partir de données de référence stockées dans cette mémoire. Cette mémoire 316 stocke par exemple une table de correspondance indiquant la mise en correspondance entre identificateurs de bloc et adresses physiques. La table de correspondance est par exemple mise à jour à chaque fois qu'une 25 page ou un bloc de la mémoire est effacé, et les adresses physiques des pages et des blocs sont mises à jour. Dans un mode de réalisation, le générateur d'adresses physiques 312 comprend un élément de gestion de stockage (STOREKEEPER) 318 capable de gérer le stockage de données dans la mémoire 30 Flash 106 et en particulier de gérer l'utilisation de blocs et/ou de pages dans la mémoire Flash 106. Par exemple, l'élément de gestion de stockage 318 met en oeuvre le procédé de stockage décrit dans la demande de brevet français FR 16/54490, correspondant à la demande de brevet européen EP 16198176, la demande de brevet 35 des Etats-Unis d'Amérique US 15/380509 et la demande de brevet chinois CN 201611054274.4. Par ailleurs, l'élément de gestion de B16012 17-ZV2-0089 11 stockage 318 peut en outre ou à titre de variante mettre en oeuvre le procédé d'indexation décrit dans la demande de brevet français FR 16/58442, correspondant à la demande de brevet européen EP 17156412, à la demande de brevet des Etats-Unis d'Amérique 5 US 15/444746 et à la demande de brevet chinois CN 201710178831.1. En outre, ou à titre_ de variante, le générateur d'adresses physiques 312 peut comprendre un traducteur (TRANSLATOR) 320 configuré pour mettre en correspondance les adresses logiques et/ou les identificateurs de bloc avec des 10 adresses physiques dans la mémoire Flash 106 à partir d'au moins un décalage. Le décalage à appliquer pour chaque adresse logique/identificateur de bloc est par exemple constant, et est par exemple indiqué dans la mémoire 316. En outre ou à titre de variante, le générateur d'adresse 15 physique 312 peut comprendre un module de rotation (ROTATION UNIT) 322 configuré pour attribuer des adresses physiques dans la mémoire Flash à des adresses logiques et/ou des identificateurs de bloc par rotation entre les adresses physiques disponibles. Par exemple, le module de rotation 322 met en OEuvre un système 20 semblable à une mémoire FIFO (first-in-first-out, premier entré premier sorti), selon lequel les pages adressables de la mémoire Flash sont utilisées tour à tour, répartissant de la sorte l'usure sur l'ensemble de la matrice de mémoire. En outre ou à titre de variante, le générateur 25 d'adresses physiques 312 peut comprendre un circuit cryptographique (CRYPTO CIRCUIT) 324 configuré pour générer des adresses physiques en décryptant l'adresse logique. En effet, dans certains modes de réalisation, on prévoit une sécurité supplémentaire par cryptage d'au moins certaines des adresses physiques de la mémoire 30 Flash 106 pour générer les adresses logiques utilisées par l'unité de traitement 102. De la sorte, l'emplacement des données dans la B16012 17-ZV2-0089 12 the address is passed, in an operation 406, ta the write controller 311. An advantage of the Flash memory interface described herein is that it permits access ta a Flash memory in a manner 5 that is transparent ta the processing unit 102. Thus the operation of the processing unit need not take into account the particular constraints of a Flash memory. Furthermore, by providing bath physical and logical address zones in the memory, is possible ta provide relatively quick access ta the Flash memory for parameters 10 that vary relatively little, and which can be accessed directly using their physical address, and only logical addresses are processed by the LMU. As such, the processing burden of the LMU can be reduced. Having thus described at least one illustrative 15 embodiment, various alterations, modifications and improvements will readily occur ta those skilled in the art. For example, while a physical address generator 312 has been illustrated in Figure 3 as comprising a storekeeper, a translator, a rotation unit and a cryptographic circuit, it will be apparent ta those skilled in 20 the art that in some embodiments only one or some of these elements could be implemented in the address generator. Furthermore, it will be apparent ta those skilled in the art that in some embodiments the read/write switches 310, 326 could be omitted from the MMU 302 and/or LMU 304, REVENDICATIONS1. Une interface de mémoire Flash comprenant : une unité de gestion de mémoire (302) comprenant un comparateur (306) configuré pour déterminer si l'adresse d'une opération d'accès à la mémoire Flash correspond à une adresse logique ou physique en comparant cette adresse à une ou plusieurs plages d'adresses ; une unité logique de mémoire (304) configurée pour convertir les adresses logiques en adresses physiques et pour fournir les adresses physiques à la mémoire Flash ; dans laquelle l'unité de gestion de mémoire (302) est configurée pour envoyer les adresses physiques vers la mémoire Flash et pour envoyer les adresses logiques vers l'unité logique de mémoire (302) pour les convertir en adresses physiques. 2. Interface de mémoire Flash selon la revendication 1, 15 dans laquelle l'unité de gestion de mémoire (302) comprend en outre une mémoire de configuration (308) stockant une indication desdites une ou plusieurs plages d'adresses. 3. Interface de mémoire Flash selon la revendication 1 ou 2, dans laquelle l'unité de mémoire logique (304) comprend : 20 un générateur d'adresse (312) configuré pour générer une adresse physique à partir de l'adresse logique et d'un identificateur de bloc identifiant un ou plusieurs blocs dans la mémoire Flash, dans lequel le générateur d'adresse (312) comprend un convertisseur d'adresse (314) configuré pour convertir chaque 25 adresse logique en un identificateur de bloc correspondant. 4. Interface de mémoire Flash selon la revendication 3, dans laquelle le générateur d'adresses (312) comprend un ou plusieurs des éléments suivants : un élément de gestion de stockage (318) configuré pour 30 gérer l'utilisation de blocs et/ou de pages dans la mémoire Flash ; un traducteur (320) configuré pour mettre en correspondance les adresses logiques et/ou les identificateurs de bloc B16012 17-ZV2-0089 16 avec des adresses physiques dans la mémoire Flash à partir d'au moins un décalage ; un module de rotation (322) configuré pour attribuer des adresses physiques dans la mémoire Flash à des adresses logiques 5 et/ou à des identificateurs de bloc par rotation entre les adresses physiques disponibles ; et un circuit cryptographique (324) configuré pour générer des adresses physiques à partir d'un décryptage de l'adresse logique. 10 5. Interface de mémoire Flash selon l'une quelconque des revendications 1 à 4, dans laquelle l'unité de gestion de mémoire (302) et l'unité logique de mémoire (304) sont en outre configurées pour : fournir chaque adresse physique à un contrôleur 15 d'écriture (311) de la mémoire Flash si l'opération d'accès à la mémoire Flash correspond à une opération d'écriture ; et fournir chaque adresse physique à un contrôleur de lecture de la mémoire Flash si l'opération d'accès à la mémoire Flash correspond à une opération de lecture. 20 6. Interface de mémoire Flash selon l'une quelconque des revendications 1 à 5, dans laquelle l'unité de gestion de mémoire (302) est mise en oeuvre par l'un des éléments suivants : un logiciel exécuté par un ou plusieurs processeurs ; ou 25 un ou plusieurs circuits matériels ; ou une combinaison d'un logiciel exécuté par un ou plu- sieurs processeurs et d'un ou plusieurs circuits matériels. 7. Interface de mémoire Flash selon l'une quelconque des revendications 1 à 6, dans laquelle l'unité de mémoire logique 30 (302) est mise en oeuvre par l'un des éléments suivants : un logiciel exécuté par un ou plusieurs processeurs ; OU un ou plusieurs circuits matériels ; ou une combinaison d'un logiciel exécuté par un ou plu-35 sieurs processeurs et d'un ou plusieurs circuits matériels. 8. Système de traitement de données comprenant : B16012 17-ZV2-0089 17 une unité de traitement (102) ; une mémoire Flash (106) ; et une interface de mémoire Flash (108) selon l'une quelconque des revendications 1 à 7. 5 9. Système de traitement de données selon la revendication 8, dans lequel la mémoire Flash (106) comprend un contrôleur de programmation/effacement (202). 10. Procédé d'accès à une mémoire Flash, consistant à : déterminer si une adresse d'une opération d'accès en 10 mémoire Flash correspond à une adresse logique ou physique en comparant l'adresse avec une ou plusieurs plages d'adresses ; si l'on détermine que l'adresse est une adresse physique, diriger l'adresse physique vers la mémoire Flash ; et si l'on détermine que l'adresse est une adresse logique, 15 convertir l'adresse logique en une adresse physique et fournir l'adresse physique à la mémoire Flash. 11. Procédé selon la revendication 10, dans lequel les une ou plusieurs plages d'adresses sont stockées dans une mémoire de configuration (308). 20 12. Procédé selon la revendication 10 ou 11, dans lequel la conversion de l'adresse logique en adresse physique consiste a: convertir l'adresse logique en identificateur d'un ou plusieurs blocs dans la mémoire Flash ; et 25 générer une adresse physique à partir de l'adresse logique et de l'identificateur. 13. Procédé selon la revendication 12, dans lequel la génération de l'adresse physique à partir de l'identificateur comprend une ou plusieurs des actions suivantes : 30 la gestion de blocs et/ou de pages dans la mémoire Flash par un élément de gestion de stockage ; la mise en correspondance de l'adresse logique et/ou de l'identificateur de bloc avec une adresse physique dans la mémoire Flash à partir d'au moins un décalage ; B16012 17-ZV2-0089 18 l'attribution d'une adresse physique dans la mémoire Flash à une adresse logique et/ou à un identificateur de bloc par rotation entre les adresses physiques disponibles ; et le décryptage de l'adresse logique. 5 14. Procédé selon l'une quelconque des revendications 10 à 13, consistant en outre à : fournir chaque adresse physique à un contrôleur d'écriture (311) de la mémoire Flash si l'opération d'accès à la mémoire Flash correspond à une opération d'écriture ; et 10 fournir chaque adresse physique à un contrôleur de lecture de la mémoire Flash si l'opération d'accès à la mémoire Flash correspond à une opération de lecture.