FR 3031254 A1 20160701 FR 1463384 A 20141229 B13783 1 ASYNCHRONOUS DATA LINK FIELD The present disclosure relates to the field of asynchronous communications, and in particular to a two-phase asynchronous transmission circuit, a two-phase asynchronous 5 reception circuit and to an asynchronous data link. BACKGROUND The design of a fully synchronous system on chip is becoming a challenging task, particularly for advanced nodes and 3D designs. Indeed, local and global variability means that the 10 timing closure is becoming an overwhelming task. The Globally Asynchronous Locally Synchronous (GALS) design style provides a useful alternative to a fully synchronous approach, as it provides improved robustness against local and inter-die variability. For example, asynchronous 15 communications may be implemented using Quasi Delay Insensitive (QDI) protocols, which have the advantage of being almost free of timing constraints. In view of its similarities to standard binary signals, the use of four-phase QDI encoding is often a preferred choice for on chip communications. A four-phase 20 asynchronous protocol involves implementing, for each data symbol to be transmitted, a handshake protocol involving four transmission phases. 3031254 B13783 2 A difficulty is that the use of four-phase asynchronous protocols for communications off chip and over 3D interfaces tends to introduce unacceptable interface delays, and leads to high dynamic power consumption. Two-phase transmissions protocols provide an interesting alternative to four-phase protocols for off chip communications. However, existing two-phase transmission protocols tend to be complex to implement. There is thus a need in the art for an asynchronous protocol allowing data communications with relatively low interface delays, low dynamic power consumption, and/or permitting relatively high data throughput. There is also a need for relatively simple and compact circuits for implementing such an asynchronous protocol. SUMMARY It is an aim of embodiments of the present description to at least partially address one or more needs in the prior art. According to one aspect, there is provided a two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit comprising: N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines. According to a further aspect, there is provided a four-phase to two-phase asynchronous protocol converter comprising: the above transmission circuit; and N data input lines, each of the input lines being associated with a corresponding one of the N data symbols, wherein the transmission circuit is adapted to generate each symbol to be 3031254 B13783 3 transmitted by detecting a first logic state on a corresponding one of the N data input lines. According to a further aspect, there is provided a four-phase to two-phase asynchronous protocol converter 5 comprising: a transmission circuit comprising: N data output lines, where N is an integer equal to 2 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission 10 circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line; and N data input lines, each of the input lines being associated with a corresponding one of the N data symbols, wherein the transmission circuit is adapted to generate each symbol to be 15 transmitted by detecting a first logic state on a corresponding one of the N data input lines, and wherein the transmission circuit comprises, for each of the N input data lines, a logic circuit having an input coupled to the corresponding data input line and adapted to generate a transition at its output in 20 response to a rising edge on the input data line. According to one embodiment, each logic circuit comprises a flip-flop, and wherein: the input of the logic circuit is a clock input of the flip-flop coupled to the corresponding input data line; and the output of the flip-flop 25 is coupled to a data input of the flip-flop via an inverter. According to one embodiment, the four-phase to twophase converter further comprises: a two-phase acknowledgement input line for receiving a two-phase acknowledgement signal indicating that a data symbol has been successfully received, 30 wherein the two-phase acknowledgement signal comprises a voltage transition on the two-phase acknowledgement input line; a four-phase acknowledgement output line for transmitting a four-phase acknowledgement signal indicating that a data symbol has been successfully received; and a four-phase acknowledgement 35 generation circuit adapted to generate the four-phase 3031254 B13783 4 acknowledgement signal based on the two-phase acknowledgement signal. According to one embodiment, the four-phase acknowledgement signal comprises, in response to the reception of each 5 data symbol, the application of a second voltage state on the four-phase acknowledgement output line, and in response to the reception of a spacer by the four-phase to two-phase converter, the application of the first voltage state on the four-phase acknowledgement output line, and wherein the four-phase 10 acknowledgement generation circuit is adapted to apply the second voltage state on the four-phase acknowledgement output line when a rising edge is detected on one of the N data input lines, and to apply the first voltage state on the four-phase acknowledgement output line when a transition is detected on one 15 of the N data output lines and on a two-phase acknowledgement input line. According to one embodiment, the four-phase acknowledgement generation circuit comprises a first XOR gate adapted to apply the XOR function to the N data output lines and a 20 second XOR gate having one input coupled to the output of the first XOR gate and another input coupled to the two-phase acknowledgement input line. According to one embodiment, the four-phase acknowledgement generation circuit further comprises a NOR gate having 25 N inputs coupled respectively to the N input lines, and an asymmetric C-element having a first input coupled to an output of the NOR gate and a second input coupled to an output of second XOR gate via an inverter, wherein the asymmetric Celement is adapted to generate a rising edge on the four-phase 30 acknowledgement output line in response to a rising edge at the outputs of the NOR gate and the inverter, and to generate a falling edge on the four-phase acknowledgement output line in response to a falling edge at the output of the NOR gate. According to a further aspect, there is provided a 35 two-phase asynchronous reception circuit for receiving data encoded according to a two-phase asynchronous protocol, the 3031254 B13783 5 reception circuit comprising: N data input lines, where N is an integer equal to 3 or more, wherein the reception circuit is capable of receiving N unique data symbols, each of the data input lines being associated with a corresponding one of the N 5 data symbols, and wherein the reception circuit is adapted to generate each data symbol by detecting a voltage transition on a corresponding one of the data input lines independently of the voltage state of the other data input lines. According to a further aspect, there is provided a 10 two-phase to four-phase asynchronous protocol converter comprising: the above reception circuit; and N data output lines, each of the data output lines being associated with a corresponding one of the N data symbols, wherein the reception circuit is adapted to transmit each data symbol by applying a 15 first logic state on a corresponding one of the data output lines. According to one embodiment, the two-phase to four-phase converter further comprising a four-phase acknowledgement input line for receiving a four-phase acknowledgement signal 20 indicating that a data symbol has been successfully received, wherein the four-phase acknowledgement signal comprises, in response to the reception of each data symbol, the application of a second logic state on the four-phase acknowledgement input line, and in response to the transmission of a spacer by the 25 reception circuit, the application of the first logic state on the four-phase acknowledgement output line. According to a further aspect, there is provided a two-phase to four-phase asynchronous protocol converter comprising: a reception circuit for receiving data encoded 30 according to a two-phase asynchronous protocol, the reception circuit comprising: N data input lines, where N is an integer equal to 2 or more, wherein the reception circuit is capable of receiving N unique data symbols, each of the data input lines being associated with a corresponding one of the N data symbols, 35 and wherein the reception circuit is adapted to generate each data symbol by detecting a voltage transition on a corresponding 3031254 B13783 6 one of the data input lines; and N data output lines, each of the data output lines being associated with a corresponding one of the N data symbols, wherein the reception circuit is adapted to transmit each data symbol by applying a first logic state on 5 a corresponding one of the data output lines; the reception circuit comprising, for each data input line: a first latch having an input coupled to the data input line; a second latch having an input coupled to an output of the first latch; and a logic gate coupled to the output of the first latch and to an 10 output of the second latch and adapted to generate a data symbol. According to one embodiment, the first latches are enabled by a first logic state of the four-phase acknowledgement signal and the second latches are enabled by a second logic 15 state of the four-phase acknowledgement signal. According to one embodiment, the two-phase to four-phase converter further comprises: a two-phase acknowledgement output line for transmitting a two-phase acknowledgement signal indicating that a data symbol has been successfully received, 20 wherein the two-phase acknowledgement signal comprises a voltage transition on the two-phase acknowledgement output line; and a two-phase acknowledgement generation circuit adapted to generate the two-phase acknowledgement signal by detecting a transition at the output of one of the second latches. 25 According to a further aspect, there is provided a data link comprising: the above two-phase transmission circuit; the above two-phase reception circuit; and a wired interface comprising N lines interconnecting the N output lines of the two-phase transmission circuit to the N input lines of the two- 30 phase reception circuit. According to one embodiment, the wired interface comprises a 3D via. GRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other features and advantages will 35 become apparent from the following detailed description of 3031254 B13783 7 embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which: Figure 1 is a cross-section view of a system level 3D interconnection according to an embodiment of the present 5 disclosure; Figure 2 is a perspective view schematically illustrating a 3D architecture comprising a pair of stacked integrated circuits according to an embodiment of the present disclosure; 10 Figure 3 schematically illustrates a data link according to an embodiment of the present disclosure; Figure 4A is a state diagram showing an example of a four-phase asynchronous protocol over two data lines according to an example embodiment; 15 Figure 4B is a state diagram showing an example of a two-phase transition encoding asynchronous protocol over two data lines according to an example embodiment; Figure SA schematically illustrates a four-phase to two-phase asynchronous protocol converter according to an 20 example embodiment of the present disclosure; Figure 5B schematically illustrates a two-phase to four-phase asynchronous protocol converter according to an example embodiment of the present disclosure; Figure 6A is a table representing a four-phase 25 asynchronous protocol using four data lines according to an example embodiment of the present disclosure; Figure 6B is a table representing a two-phase asynchronous protocol using four data lines according to an example embodiment of the present disclosure; 30 Figure 7A schematically illustrates a four-phase to two-phase asynchronous protocol converter according to an example embodiment of the present disclosure; Figure 7B is a timing diagram showing signals in the converter of Figure 7A according to an example embodiment; 3031254 B13783 8 Figure 8A schematically illustrates a two-phase to four-phase asynchronous protocol converter according to an example embodiment of the present disclosure; and Figure 8B is a timing diagram showing signais in the 5 converter of Figure 8A according to an example embodiment. DE TAILED DESCRIPTION Figure 1 is a cross-section view schematically illustrating a system level 3D interconnection using 3D technology. In the example of Figure 1, there are three 10 integrated circuits 102, 104 and 106 interconnected by a silicon interposer 108. Each of the integrated circuits 102 to 106 may use different voltage levels and/or different operating frequencies, and it can be designed with different technologies. The integrated circuits 102 to 106 are for example coupled to 15 the silicon interposer 108 by microbumps 110. The interposer 108 for example comprises an interconnection level 111, and a silicon layer 112 through which one or more Through Silicon Vias (TSV) 114 are formed. The TSVs 114 are each connected to a corresponding flip chip bump 116, which is in turn connected to 20 a package substrate 118. The package substrate 118 is for example further coupled via BGA (bail grid array) balls 120 to a motherboard or the like. The microbumps 110, TSVs 114 and flip chip bumps 116 of the interposer 108 provide 3D interfaces between the 25 integrated circuits 102, 104 and 106 and/or with other circuits. However, a difficulty is that there elements introduce propagation delays. Furthermore the interposer 108 may comprise test logic and/or micro-buffer cells (not illustrated in Figure 1) comprising buffers, ESD (electrostatic discharge) protection 30 circuits and/or level shifters, adding further propagation delays to the signais transmitted to or from the integrated circuits 102, 104, 106. Figure 2 illustrates an example of a 3D circuit design comprising an integrated circuit 202 superposed over an 35 integrated circuit 204. Each of the integrated circuits 202, 204 for example comprises a network-on-chip (NoC) comprising a grid 3031254 B13783 9 of interconnecting buses 206, with a router 208 at each crossing point between the buses 206. Each router 208 is for example coupled to a corresponding processing device 210 provided on each integrated circuit 202, 204. At least some of the 5 interconnection routers 208 of the integrated circuit 202 are coupled, via 3D interfaces 212 for example comprising TSVs, with interconnection routers 208 of the integrated circuit 204. Again, the 3D interfaces 212 of the embodiment of Figure 2 for example introduce propagation delays. Therefore, 10 while at least some of the on chip communications over the buses 206 of each integrated circuit 202, 204 may be performed using an asynchronous four-phase protocol, the use of such a protocol over the 3D interfaces 212 is likely to lead to unacceptable propagation delays and thus low data throughput and high dynamic 15 power consumption. Figure 3 schematically illustrates a data link 300, which is for example used for communications between the interposer 108 and the integrated circuits 102, 104 and 106 in Figure 1, and/or between the integrated circuits 202 or 204 of 20 Figure 2. The data link 300 comprises circuits 302 and 304 that communicate with each other using a two-phase transition encoding asynchronous protocol. The circuit 302 for example comprises a protocol 25 conversion circuit 306 coupled to input lines 308 for receiving data symbols transmitted according to a four-phase asynchronous protocol. For example, while not shown in Figure 3, the signais on the input lines 308 are provided by a further transmission interface that uses the four-phase asynchronous protocol. 30 The circuit 306 comprises a four-phase to two-phase asynchronous protocol converter 310 having inputs coupled to the lines 308, and providing, on output lines 312, data symbols encoded according to a two-phase asynchronous protocol. The lines 312 are for example coupled via an interface circuit 314, 35 for example comprising buffers, ESD protection circuits and/or level shifters, to a wired interface 316. The wired interface 3031254 B13783 10 316 for example comprises a 3D interface, such as a TSV, or other type of 2D or 3D connection. The circuit 302 also receives on lines 318 data symbols transmitted according to the two-phase asynchronous 5 protocol. The fines 318 are for example coupled to a further wired interface 320 between the circuits 302 and 304 via a further interface circuit 322. The fines 318 are provided to a two-phase to four-phase asynchronous protocol converter 324, which provides, on output fines 326, data symbols encoded 10 according to the four-phase asynchronous protocol. For example, the output fines 326 are coupled to a further transmission interface that uses the four-phase asynchronous protocol. The circuit 304 for example comprises the same elements as the circuit 302, which are labelled with like 15 reference numerals and will not be described again in detail. However, the converter 310 in the circuit 304 has its output fines 312 coupled to the wired interface 320, for example via the 3D interface circuit 314, and the converter 324 in the circuit 304 has its input fines 318 coupled to the wired 20 interface 316, for example via the 3D interface circuit 322. Figure 4A is a state diagram illustrating an example of a four-phase asynchronous protocol based on two data fines, which we will call AO and Al, and a single acknowledgement wire. There are three states, a state 00 in which both fines AO and Al 25 are at a low logic level, a state 01 in which the line Al is at a low logic level and the line AO is at a high logic level, and a state 10 in which the line Al is at a high logic level and the line AO is at a low logic level. From the initial state 00, in a first phase a binary 30 "0" is transmitted by moving to the state 01, in other words by bringing the line AO to a high logic level, or a binary "1" is transmitted by moving to the state 10, in other words by bringing the line Al to a high logic level. In a second phase, an acknowledgement signal ACK is received, causing, in a third 35 phase, a return to the state 00, by bringing both of the fines AO and Al to a low logic level. This corresponds to a spacer 3031254 B13783 11 separating transmission of consecutive data symbols. In the fourth phase, another acknowledgement signal ACK is received, meaning that a new data symbol may be transmitted. Thus, according to the four-phase asynchronous 5 protocol, the data is encoded in a way quite closely resembling standard binary signals. Each line is associated with one of the data symbols, in this example a "0" and a "1". A logic high state on each line is used to represent each data symbol. Figure 4B is a state diagram illustrating an example 10 of a two-phase asynchronous protocol, which will be called herein a two-phase transition encoding asynchronous protocol. The example of Figure 4B is based on two data lines, which we will again call AO and Al, and a single acknowledgement wire. There are four states, a state 00 in which both lines AO and Al 15 are at a low logic level, a state 01 in which the line Al is at a low logic level and the line AO is at a high logic level, a state 10 in which the line Al is at a high logic level and the line AO is at a low logic level, and a state 11 in which both lines are at a high logic level. 20 From any initial state, the data symbol "0" is encoded by a voltage transition on the line A0, and the data symbol "1" is encoded by a voltage transition on the line Al, independently of the state of the other line. As used herein, a voltage transition means a transition from a low logic level to a high 25 logic level or from a high logic level to a low logic level. Thus, starting in the state 00, in a first phase, a binary "0" is transmitted by moving to the state 01, in other words by bringing the line AO to a high logic level, or a binary "1" is transmitted by moving to the state 10, in other words by 30 bringing the line Al to a high logic level. In a second phase, an acknowledgement signal ACK is received. A new data symbol can then be transmitted. For example, from the state 01, a binary "1" is transmitted by moving to the state 11, in other words by bringing the line Al to a high logic level, or a binary "0" is 35 transmitted by moving back to the state 00, in other words by bringing the line AO to a low logic level. From the state 11, a 3031254 B13783 12 binary "1" is transmitted by moving to the state 01, in other words by bringing the line Al to a low logic level, or a binary "0" is transmitted by moving to the state 10, in other words by bringing the line A0 to a low logic level. From the state 10, a 5 binary "1" is transmitted by moving to the state 00, in other words by bringing the line Al to a low logic level, or a binary "0" is transmitted by moving to the state 11, in other words by bringing the line A0 to a high logic level. Thus, the two-phase asynchronous protocol is similar 10 to the four-phase asynchronous protocol in that each line is again associated with one of the data symbols. However, the data symbol is selected by a transition, rather than by a high logic level, on a given line. Figure SA schematically illustrates the inputs and 15 outputs of the four-phase to two-phase converter 310 of Figure 3 in more detail according to an example in which the input lines 308 comprise four data lines labelled A0, Al, A2 and A3 and an acknowledgement line ACK, and the output lines 312 comprise four data lines labelled Al', A2' and A3', and an 20 acknowledgement line ACK'. Figure 5B schematically illustrates the inputs and outputs of the two-phase to four-phase converter 324 of Figure 3 in more detail according to an example in which the input lines 318 comprise four data lines labelled Al', A2' and A3' and 25 an acknowledgement line ACK', and the output lines 326 comprise four data lines labelled A0, Al, A2 and A3, and an acknowledgement line ACK. Figure 6A. is a table representing the four-phase asynchronous protocol of Figure 4A adapted to the four data 30 lines A0, Al, A2 and A3 of Figures aA and 5B. There are for example four unique data symbols labelled "0", "1", "2", "3", which for example respectively correspond to binary values 00, 01, 10 and 11. Each symbol "0" to "3" is associated with a corresponding one of the lines A0 to 35 A3, such that a high logic level on a given line transmits the corresponding data symbol. 3031254 B13783 13 Figure 6B is a table representing the two-phase asynchronous protocol of Figure 4B adapted to the four data lines AO', Al', A2' and A3' of Figures 5A and 5B. Each symbol "0" to "3" is associated with a corresponding one of the lines 5 AO' to A3', such that a voltage transition on a given line transmits the corresponding data symbol, independently of the voltage state on the other lines. While the examples of Figures 5A, 5B, 6A and 6B involve four data lines for the four-phase signals and for the 10 two-phase signals, in other embodiments there could be N data lines used for transmitting the data symbols of each protocol, where N is for example an integer equal to or greater than 2, and in some embodiments is an integer equal to or greater than 3. 15 Figure 7A schematically illustrates the four-phase to two-phase converter 310 of Figure 5A in more detail according to an example embodiment. The data line AO receives a signal 4ph data 0 and is coupled to a clock input of a flip-flop 702. The flip-flop 702 20 has its Q output 704 coupled to the data line AO' of the twophase protocol. The output 704 is also coupled, via an inverter 706, to the data input of the flip-flop 702. The data line Al receives a signal 4ph data 1 and is coupled to a clock input of a flip-flop 708. The flip-flop 708 25 has its Q output 710 coupled to the data line Al' of the twophase protocol. The output 710 is also coupled, via an inverter 712, to the data input of the flip-flop 708. The data line A2 receives a signal 4ph data 2 and is coupled to a clock input of a flip-flop 714. The flip-flop 714 30 has its Q output 716 coupled to the data line A2' of the twophase protocol. The output 716 is also coupled, via an inverter 718, to the data input of the flip-flop 714. The data line A3 receives a signal 4ph data 3 and is coupled to a clock input of a flip-flop 720. The flip-flop 720 35 has its Q output 722 coupled to the data line A3' of the two- 3031254 B13783 14 phase protocol. The output 722 is also coupled, via an inverter 724, to the data input of the flip-flop 720. The converter 310 also comprises a four-phase acknowledgement generation circuit 726, which provides the 5 acknowledgement signal 4ph ack out to the four-phase side on the line ACK, and receives an acknowledgement signal 2ph ack in from the two-phase side on the line ACK'. The circuit 726 generates the acknowledgement signal 4ph ack out based on the signals 4ph data 0 to 4ph data 3 on the lines A0 to A3 and on the 10 signals 2ph data 0 to 2ph data 3 on the lines A0' to A3'. For example, the data lines AO to A3 are coupled to corresponding inputs of a four-input NOR gate 728, which has its output coupled to one input of an asymmetric C element 730, also known as a Müller circuit. The lines AO' to A3' are for example 15 coupled to corresponding inputs of a four-input XOR gate 732, the output of which is coupled to one of two inputs of an XOR gate 734. The other input of the gate 734 is coupled to the line ACK'. The output of the XOR gate 734 is coupled via an inverter 736 to the second input of the asymmetric C element 730. 20 The XOR gates described herein with two or more inputs have the function of generating a voltage transition at their outputs in response to detecting a voltage transition at any one of their inputs. The asymmetric C-element 730 for example has an 25 asymmetric fall. For example, it has the following truth table for input A coming from the NOR gate 728, input B coming from the inverter 736, and output Z, where Zn_i means that the output of the C-element remains unchanged: A B Z 1 1 1 0 1 Zn-1 1 0 Zn-1 0 0 Thus the output of the C-element 730, which is for 30 example initially at a high logic value, will be brought to a 3031254 B13783 15 low logic level if one of the lines AO to A3 transitions to a high logic level. The output of the C-element will then be brought high again if ail of the lines AO to A3 are at a low logic level and a transition occurs on the line ACK'. 5 Operation of the circuit of Figure 7A will now be described in more detail with reference to the timing diagram of Figure 7B for an example in which the data symbol "0" is transmitted. It will be apparent to those skilled in the art that operation will be similar for the transmission of the other 10 data symbols. Figure 7B illustrates the signais 4ph data 0 and 4ph ack out of the four-phase protocol, and the signais 2ph data 0 and 2ph ack in of the two-phase protocol. The sequence is initiated by a rising edge 740 of the 15 signal 4ph data 0. Thus the flip-flop 702 will be clocked by this rising edge, triggering a transition labelled 742 of the signal 2ph data 0 on the data line A0'. It is assumed that the output signal 4ph ack out of the C-element 730 is initially high and that the output of the 20 XOR gate 734 is initially low. The transition on the data line AO causes the output of the NOR gate 728 to go low, thereby bringing the output of the C-element 730 low, as shown by a falling edge 744 of the signal 4ph ack out. The data transition 742 will also cause, sometime 25 later, a transition 746 in the acknowledgement signal 2ph ack in on line ACK'. Furthermore, the falling edge 744 of the acknowledgement signal 4ph ack out will cause the transmitting circuit to bring the signal 4ph data 0 low, as shown by a falling edge 748. This corresponds to a spacer transmitted on 30 the data lines AO to A3, which causes the output of NOR gate 728 to go high. The combination of these events will cause the two inputs of the C-element 730 to go high, thereby causing the acknowledgement signal 4ph ack out to go high, as shown by a rising edge 450. The circuit is then ready to receive a 35 subsequent data symbol. 3031254 B13783 16 Figure 8A schematically illustrates the two-phase to four-phase converter 324 of Figure 5B in more detail according to an example embodiment. The data line AO' receives a signal 2ph data 0 and is 5 coupled to a data input of a latch 802. The output 804 of the latch 802 is coupled to a data input of a further latch 806, which has its output 808 coupled to one input of a two-input XOR gate 810. The other input of XOR gate 810 is coupled to the output 804 of latch 802. The output of XOR gate 810 is coupled 10 to the data line AO of the four-phase protocol. The data line Al' receives a signal 2ph data 1 and is coupled to a data input of a latch 812. The output 814 of the latch 812 is coupled to a data input of a further latch 816, which has its output 818 coupled to one input of a two-input XOR 15 gate 820. The other input of XOR gate 820 is coupled to the output 814 of latch 812. The output of XOR gate 820 is coupled to the data line Al of the four-phase protocol. The data line A2' receives a signal 2ph data 2 and is coupled to a data input of a latch 822. The output 824 of the 20 latch 822 is coupled to a data input of a further latch 826, which has its output 828 coupled to one input of a two-input XOR gate 830. The other input of XOR gate 830 is coupled to the output 824 of latch 822. The output of XOR gate 830 is coupled to the data line A2 of the four-phase protocol. 25 The data line A3' receives a signal 2ph data 3 and is coupled to a data input of a latch 832. The output 834 of the latch 832 is coupled to a data input of a further latch 836, which has its output 838 coupled to one input of a two-input XOR gate 840. The other input of XOR gate 840 is coupled to the 30 output 834 of latch 832. The output of XOR gate 840 is coupled to the data line A3 of the four-phase protocol. In the converter 324, the acknowledgement signal 2ph ack out on line ACK' is generated by an XOR gate 842 having four inputs coupled respectively to the outputs 808, 818, 828 35 and 838 of the latches 806, 816, 826 and 836. Furthermore, the acknowledgement signal 4ph ack in provided by the four-phase 3031254 B13783 17 protocol on line ACK is coupled to an enable input of each of the latches 802, 812, 822 and 832, which are each enabled by a logic high value of this signal, and to an enable input of each of the latches 806, 816, 826 and 836, which are each enabled by 5 a logic low value of this signal. Thus the pair of latches associated with each data line is arranged in a master-slave configuration in which data will be latched by the first latch when the signal 4ph ack in is high, and then latched by the second latch when the signal 4ph ack in is low. 10 Operation of the circuit of Figure 8A will now be described in more detail with reference to Figure 8B for an example in which the data symbol "0" is transmitted. It will be apparent to those skilled in the art that operation will be similar for the transmission of the other data symbols. 15 Figure 8B is a timing diagram illustrating the signals 2ph data 0 and 2ph ack out of the two-phase protocol, and the signals 4ph data 0 and 4ph ack in of the four-phase protocol. Initially the acknowledgement signal 4ph ack in is at a high logic level, such that the latches 802, 812, 822 and 832 20 are enabled, whereas the latches 806, 816, 826 and 836 maintain, at their outputs, their previous state. The sequence is initiated by a transition 850 of the signal 2ph data 0. This causes a transition at the output 804 of the latch 802, triggering, a short time later, a rising edge 852 25 of the signal 4ph data O. Once this data symbol has been received on the four-phase side, the acknowledgement signal 4ph ack in will be brought low, as shown by a falling edge 854. This will cause the latches 806, 816, 826 and 836 to be enabled while the input stages 802, 812, 822 and 832 are disabled, such 30 that the output of latch 806 will equal its input, and the output of XOR gate 810 will go low, as shown by a falling edge 856 of the signal 4ph data 0. Furthermore, the transition at the output of the latch 808 will cause the signal 2ph ack out at the output of the XOR gate 842 to transition, as shown labelled 858. 35 Furthermore, the falling edge 856 of the signal 4ph data 0 will cause, sometime later, the acknowledgement signal 4ph ack in to 3031254 B13783 18 go high again as shown by a rising edge 860, thereby enabling again the latches 802, 812, 822 and 832 ready for reception of a subsequent data symbol. An advantage of the two-phase transition encoding 5 asynchronous protocol described herein, with a number of data lines N advantageously equal to 3 or more, is that it provides a relatively high throughput and relatively low dynamic power consumption when compared to a four-phase asynchronous protocol. A further advantage is that by use of such an asynchronous 10 protocol for communications between integrated circuits, the problem of synchronisation between the circuits will be considerably reduced. Furthermore, an advantage of the circuits of Figures 7A and 8A for converting between the two-phase and four-phase protocols is that that are compact circuits with 15 relatively few gates and thus relatively low power consumption. Having thus described at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art. For example, while embodiments have been described in 20 Figure 7A and 8A in which there are four data lines, it will be apparent to those skilled in the art how there circuits could be adapted to any number N of data lines and corresponding data symbols. Furthermore, it will be apparent to those skilled in 25 the art that the application of the two-phase asynchronous protocol to a 3D interface is merely one example, and that it could be applied to a broad range of interfaces for which the propagation delay is relatively high. REVENDICATIONS1. A two-phase asynchronous transmission circuit for transmitting data over a wired interface (316, 320) according to a two-phase asynchronous protocol, the transmission circuit comprising: N data output lines (A0' to A3'), where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols ("0" to "3"), each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines. 2. A four-phase to two-phase asynchronous protocol converter comprising: the transmission circuit of claim 1; and N data input lines (A0 to A3), each of the input lines being associated with a corresponding one of the N data symbols ("0" to "3"), wherein the transmission circuit is adapted to generate each symbol to be transmitted by detecting a first 20 logic state on a corresponding one of the N data input lines. 3. The four-phase to two-phase converter of claim 2, wherein the transmission circuit comprises, for each of the N input data lines, a logic circuit (702, 708, 714, 720) having an input coupled to the corresponding data input line and adapted 25 to generate a transition at its output in response to a rising edge on the input data line. 4. The four-phase to two-phase converter of claim 3, wherein each logic circuit comprises a flip-flop (702, 708, 714, 720), and wherein: 30 said input of the logic circuit is a clock input of the flip-flop coupled to the corresponding input data line; and the output of the flip-flop is coupled to a data input of the flip-flop via an inverter (706, 712, 718, 724). 3031254 B13783 5. The four-phase to two-phase converter of any of claims 2 to 4, further comprising: a two-phase acknowledgement input line (ACK') for receiving a two-phase acknowledgement signal indicating that a 5 data symbol has been successfully received, wherein the twophase acknowledgement signal comprises a voltage transition on the two-phase acknowledgement input line (ACK'); a four-phase acknowledgement output line (ACK) for transmitting a four-phase acknowledgement signal indicating that 10 a data symbol has been successfully received; and a four-phase acknowledgement generation circuit (726) adapted to generate the four-phase acknowledgement signal based on the two-phase acknowledgement signal. 6. The four-phase to two-phase converter of claim 5, 15 wherein the four-phase acknowledgement signal comprises, in response to the reception of each data symbol, the application of a second voltage state on the four-phase acknowledgement output line (ACK), and in response to the reception of a spacer by the four-phase to two-phase converter, the application of the 20 first voltage state on the four-phase acknowledgement output line (ACK), and wherein the four-phase acknowledgement generation circuit (726) is adapted to apply the second voltage state on the four-phase acknowledgement output line (ACK) when a rising edge is detected on one of the N data input lines, and to apply the first voltage state on the four-phase acknowledgement output line when a transition is detected on one of the N data output lines and on the two-phase acknowledgement input line (ACK') . 7. The four-phase to two-phase converter of claim 5 or 6, wherein the four-phase acknowledgement generation circuit (726) comprises a first XOR gate (732) adapted to apply the XOR function to the N data output lines and a second XOR gate (734) having one input coupled to the output of the first XOR gate (732) and another input coupled to the two-phase acknowledgement input line (ACK'). 3031254 B13783 21 8. The four-phase to two-phase converter of claim 7, wherein the four-phase acknowledgement generation circuit (726) further comprises a NOR gate (728) having N inputs coupled respectively to the N input lines, and an asymmetric C-element 5 (730) having a first input coupled to an output of the NOR gate (728) and a second input coupled to an output of the second XOR gate (734) via an inverter (736), wherein the asymmetric Celement (730) is adapted to generate a rising edge on the four-phase acknowledgement output line (ACK) in response to a rising 10 edge at the outputs of the NOR gate (728) and the inverter (736), and to generate a falling edge on the four-phase acknowledgement output line (ACK) in response to a falling edge at the output of the NOR gate (728). 9. A two-phase asynchronous reception circuit for 15 receiving data encoded according to a two-phase asynchronous protocol, the reception circuit comprising: N data input lines (A0' to A3'), where N is an integer equal to 3 or more, wherein the reception circuit is capable of receiving N unique data symbols, each of the data input lines 20 being associated with a corresponding one of the N data symbols, and wherein the reception circuit is adapted to generate each data symbol by detecting a voltage transition on a corresponding one of the data input lines independently of the voltage state of the other data input lines. 25 10. A two-phase to four-phase asynchronous protocol converter comprising: the reception circuit of claim 9; and N data output lines (A0 to A3), each of the data output lines being associated with a corresponding one of the N 30 data symbols, wherein the reception circuit is adapted to transmit each data symbol by applying a first logic state on a corresponding one of the data output lines. 11. The two-phase to four-phase converter of claim 10, further comprising a four-phase acknowledgement input line (ACK) 35 for receiving a four-phase acknowledgement signal indicating that a data symbol has been successfully received, wherein the 3031254 B13783 22 four-phase acknowledgement signal comprises, in response to the reception of each data symbol, the application of a second logic state on the four-phase acknowledgement input line (ACK), and in response to the transmission of a spacer by the reception 5 circuit, the application of the first logic state on the four-phase acknowledgement output line (ACK). 12. The two-phase to four-phase converter of claim 10 or 11, comprising, for each data input line: a first latch (802, 812, 822, 832) having an input 10 coupled to the data input line; a second latch (806, 816, 826, 836) having an input coupled to an output of the first latch; and a logic gate (810, 820, 830, 840) coupled to the output of the first latch and to an output of the second latch 15 and adapted to generate a data symbol, wherein the first latches are enabled by a first logic state of the four-phase acknowledgement signal and the second latches are enabled by a second logic state of the four-phase acknowledgement signal. 13. The two-phase to four-phase converter of claim 12, 20 further comprising: a two-phase acknowledgement output line (ACK') for transmitting a two-phase acknowledgement signal indicating that a data symbol has been successfully received, wherein the twophase acknowledgement signal comprises a voltage transition on 25 the two-phase acknowledgement output line (ACK'); and a two-phase acknowledgement generation circuit (842) adapted to generate the two-phase acknowledgement signal by detecting a transition at the output of one of the second latches. 30 14. A data link comprising: the two-phase transmission circuit of claim 1; the two-phase reception circuit of claim 9; and a wired interface (316, 320) comprising N lines interconnecting the N output lines of the two-phase transmission 35 circuit to the N input lines of the two-phase reception circuit. 3031254 B13783 23 15. The data transmission link of claim 14, wherein the wired interface (316, 320) comprises a 3D via (114, 212).