==== Celeron "(dual-core)" ========= "Allendale" (65 nm) =====*All models support: "MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)"* Steppings: M0===== "Wolfdale-3M" (45 nm) =====* Based on Core microarchitecture* All models support: "MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x"* Steppings: R0* Die size: 82 mm2=== Nehalem based Celerons ======= Celeron "(dual-core)" ========= "Clarkdale" (MCP, 32 nm) =====* Based on Westmere microarchitecture* All models support: "MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Smart Cache.
=== Микроархитектура P6 ====== Микроархитектура Netburst ====== Микроархитектура Core ====== Микроархитектура Nehalem ======= «Clarkdale» (32 нм) ====* Основаны на микроархитектуре Westmere* Все модели поддерживают: "MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Smart Cache.