=== Nehalem based Celerons =======Celeron "(dual-core)"========= "Arrandale" (MCP, 32 nm) =====* Based on Westmere microarchitecture* All models support: "MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Smart Cache"* P4505 and U3405 support memory ECC RAM and PCIe bifurcation.
=== Микроархитектура P6 ====== Микроархитектура Netburst ====== Микроархитектура Core ====== Микроархитектура Nehalem ======= «Arrandale» (32 нм) ====* Основаны на микроархитектуре Westmere* Все модели поддерживают: "MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Smart Cache.