# Job Position
**Position:** Senior ASIC Design Engineer -Risc-V / UVM

**Company:** European Recruitment

**Location:** San Jose, CA

**Work Type:** Full-time

**Experience Level:** Mid-Senior level

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## Job Description

Senior ASIC Design Engineer- RTL Design / UVM
We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification Engineer to join their team in California.
If this is you please continue reading below!
Responsibilities:
Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks.SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly diag validation)Architect and implement complex RTL designs.Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the d