You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Ayla Lin and other students
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_led_matrix_ayla_lin(
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




module TOP(
    input sysclk,
    input reset,
    input enable_n,
    output spi_clk,
    output spi_cs_n,
    output spi_mosi);

wire enable;
wire [6:0] address;
wire [47:0] data;
wire spi_ready;
wire spi_load;
reg [4:0] counter;
wire clk;

assign enable = ~enable_n;
assign spi_clk = clk;

// To ensure SPI work correctly with level shifter,
// reduce clock frequencye to 1/32.
// Zybo Z7 FPGA has output clock rate of 33MHZ
// TinyTapeout has output colock rate of 33MHZ
assign clk = counter[4];
always @(posedge sysclk) begin
  if (reset) begin
    counter <= 0;
  end else begin
    counter <= counter + 1;
  end
end

CONTROLLER controller_inst (
  .clk(clk),
  .reset(reset),
  .enable(enable),
  .spi_ready(spi_ready),
  .address(address),
  .spi_load(spi_load)
);

ROM rom_inst (
  .clk(clk),
  .address(address),
  .data(data)
);

SPI spi_inst (
    .clk(clk),
    .reset(reset),
    .load(spi_load),
    .data(data),
    .ready(spi_ready),
    .cs_n(spi_cs_n),
    .mosi(spi_mosi)
);

endmodule


module CONTROLLER(
    input clk,
    input reset,
    input enable,
    input spi_ready,
    output reg [6:0] address,
    output reg spi_load);

reg [2:0] state;
reg [21:0] counter;
reg spi_load_next;
reg spi_load_pending;
reg spi_ready_delay;

// States
// IDLE:
//   Wait for `spi_ready` to become 1.
//   Set `address` to the first for setup and
//   chage state to STEUP.
// STEUP:
//   Send instructions for setup to LED Driver.
//   This is done by sending addresses of setup
//   instructions to ROM, and `spi_load` to SPI.
// DISPLAY:
//   Send bitmaps to LED Dr
//   Each column of a bitmap is loaded from ROM
//   and sent to SPI once. At the end of each
//   bitmap, SPI is paused by several seconds.
// PAUSE:
//   Pause SPI by 2^21 clocks.
localparam IDLE = 3'b000;
localparam SETUP = 3'b001;
localparam DISPLAY = 3'b010;
localparam PAUSE = 3'b011;

always @(posedge clk) begin
  spi_ready_delay <= spi_ready;
  spi_load_pending <= spi_load_next;
  spi_load <= spi_load_pending;
  if (reset || !enable) begin
    state <= IDLE;
    counter <= 0;
    spi_load_next <= 1'b0;

  end else begin
    case (state)
      IDLE: begin
        spi_load_next <= 1'b0;
        if (spi_ready) begin
          address <= 7'b1111111;
          state <= SETUP;
          counter <= 64;
        end
      end
        
      SETUP: begin
        if (spi_ready && !spi_load_next && counter > 62) begin
          address <= address + 1;
          spi_load_next <= 1'b1;
          counter <= 0;
          if (address == 7'b0000011) begin
            state <= DISPLAY;
          end
        end else begin
          spi_load_next <= 1'b0;
          counter <= counter + 1;
        end
      end
          
      DISPLAY: begin
        if (spi_ready && !spi_load_next && counter > 62) begin
          spi_load_next <= 1'b1;
          counter <= 0;
          
          // At the end of each bitmap, change state
          // to PAUSE so the bitmap will be displayed
          // for a few seconds.
          if (address == 7'b0001011 ||
              address == 7'b0010011) begin
            state <= PAUSE;
          end

          // If it's at the end of the last bitmap
          // move to the begining of the first bitmap;
          // otherwise, move to next column of the
          // same bitmap or the first column of the next
          // bitmap.
          if (address == 7'b0010011) begin
              address <= 7'b0000011;
          end else begin
            address <= address + 1;
          end
        end else begin
          spi_load_next <= 1'b0;
          counter <= counter + 1;
        end
      end

      PAUSE: begin
        spi_load_next <= 1'b0;
        counter <= counter + 1;
        if (counter == 22'b1111111111111111111111) begin
          state <= DISPLAY;
        end
      end

      default: begin
        state <= IDLE;
        counter <= 22'b0000000000000000000000;
        spi_load_next <= 1'b0;
      end
    endcase
  end
  end

endmodule


module ROM (
    input clk,
    input [6:0] address,    // 5-bit address input
    output reg [47:0] data  // 4 bit address + 8 bit data
);

always @(posedge clk) begin
    data <=
           // Instructions for setting up LED Driver.
           (address == 7'b0000000) ? {12'b101000001111, 12'b101000001111, 12'b101000001111, 12'b101000001111} :
           (address == 7'b0000001) ? {12'b110000000001, 12'b110000000001, 12'b110000000001, 12'b110000000001} :
           (address == 7'b0000010) ? {12'b101100001111, 12'b101100001111, 12'b101100001111, 12'b101100001111} :
           (address == 7'b0000011) ? {12'b100100000000, 12'b100100000000, 12'b100100000000, 12'b100100000000} :
           // Bitmaps, each address corresponding to 32 LEDs.
           (address == 7'b0000100) ? {12'b000100000000, 12'b000100010111, 12'b000100000000, 12'b000100000000} :
           (address == 7'b0000101) ? {12'b001000000000, 12'b001011010110, 12'b001000000000, 12'b001000000000} :
           (address == 7'b0000110) ? {12'b001100000111, 12'b001111110100, 12'b001111110000, 12'b001100100000} :
           (address == 7'b0000111) ? {12'b010000011111, 12'b010011111000, 12'b010010000000, 12'b010000100000} :
           (address == 7'b0001000) ? {12'b010101111111, 12'b010111110000, 12'b010111000111, 12'b010110111100} :
           (address == 7'b0001001) ? {12'b011001111111, 12'b011011110000, 12'b011010000000, 12'b011000100000} :
           (address == 7'b0001010) ? {12'b011101111000, 12'b011111010000, 12'b011111110000, 12'b011100100000} :
           (address == 7'b0001011) ? {12'b100000110000, 12'b100000010000, 12'b100000000000, 12'b100000000000} :
           // Bitmaps, each address corresponding to 32 LEDs.
           (address == 7'b0001100) ? {12'b000100000000, 12'b000100000000, 12'b000100000000, 12'b000100000000} :
           (address == 7'b0001101) ? {12'b001000111110, 12'b001001111111, 12'b001001101111, 12'b001000000000} :
           (address == 7'b0001110) ? {12'b001100111110, 12'b001100000011, 12'b001101101111, 12'b001101000001} :
           (address == 7'b0001111) ? {12'b010001001001, 12'b010001111111, 12'b010001101011, 12'b010001111111} :
           (address == 7'b0010000) ? {12'b010101001001, 12'b010101111111, 12'b010101101011, 12'b010101111111} :
           (address == 7'b0010001) ? {12'b011001111111, 12'b011000000011, 12'b011001111011, 12'b011001000001} :
           (address == 7'b0010010) ? {12'b011101111111, 12'b011101111111, 12'b011101111011, 12'b011100000000} :
                                     {12'b100000000000, 12'b100000000000, 12'b100000000000, 12'b100000000000};
end

endmodule


module SPI(
    input clk,
    input reset,
    input load,
    input [47:0] data,
    output ready,
    output cs_n,
    output mosi);

localparam BUFFER_WIDTH = 64;

// States
// IDLE:
//   Set `ready` to 1.
//   Wait for `load` input to become 1.
//   When it happens, load `data` into `buffer`.
// SEND:
//   Send `buffer` bit-by-bit to `mosi`.
//   Set `cs_n` to 0 (active).
// PAUSE:
//   Pause (do not accept new `data`) for some time
//   to give the LED Driver time to finish processing.
localparam IDLE = 2'b00;
localparam SEND = 2'b01;
localparam PAUSE = 2'b10;

reg [63:0] buffer;
reg [6:0] counter;
reg [1:0] state;

assign mosi = buffer[BUFFER_WIDTH-1];
assign cs_n = !(state == SEND);
assign ready = (state == IDLE);

wire clk_copy;
assign clk_copy = clk;

always @(posedge clk_copy) begin
  if (reset) begin
    buffer <= 0;
    counter <= 0;
    state <= IDLE;
    end

  else begin
    case (state)
      IDLE: begin
        counter <= 0;
        if (load) begin
          buffer[11:0] <= data[11:0];
          buffer[15:12] <= 0;
          buffer[27:16] <= data[23:12];
          buffer[31:28] <= 0;
          buffer[43:32] <= data[35:24];
          buffer[47:44] <= 0;
          buffer[59:48] <= data[47:36];
          buffer[63:60] <= 0;
          state <= SEND;
        end
      end

      SEND: begin
        buffer[BUFFER_WIDTH-1:1] <= buffer[BUFFER_WIDTH-2:0];
        counter <= counter + 1;
        if (counter == BUFFER_WIDTH - 1) begin
          state <= IDLE;
        end
      end

      PAUSE: begin
        buffer[BUFFER_WIDTH-1:1] <= buffer[BUFFER_WIDTH-2:0];
        counter <= counter + 1;
        if (counter == 7'b1111111) begin
          state <= IDLE;
        end
      end

      default: begin
        buffer <= 0;
        counter <= 0;
        state <= IDLE;
      end
    endcase
  end
end

endmodule


Reference solution:
rtl/generated.v: 
wire reset;
wire enable_n;
assign reset = !rst_n;
assign enable_n = !ena;

TOP top_inst(
    .sysclk(clk),
    .reset(reset),
    .enable_n(enable_n),
    .spi_clk(uo_out[0]),
    .spi_cs_n(uo_out[1]),
    .spi_mosi(uo_out[2])
);

// All output pins must be assigned. If not used, assign to 0.
assign uo_out[7:3]  = 0;
assign uio_out = 0;
assign uio_oe  = 0;

// List all unused inputs to prevent warnings
wire _unused = &{ui_in, uio_in, 1'b0};