You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Ephren Manning
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_ephrenm_tsal (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

  // All output pins must be assigned. If not used, assign to 0.
  assign uo_out[7:2]  = 6'd0; 
  assign uio_out[7:4] = 4'd0;
  assign uio_out[2:1] = 2'd0;
  assign uio_oe  = 8'b00001001;

  // List all unused inputs to prevent warnings
  wire _unused = &{ena, clk, rst_n, 1'b0};

  top #() top_instance (
    .clk(clk),
    .rst_btn(rst_n),
    .s_data(uio_in[1]), //input
    .comparison_value(ui_in[7:0]),
    .s_clk(uio_out[3]), //output
    .cs(uio_out[0]), //output
    .green_led(uo_out[0]),
    .red_led(uo_out[1])
  );

endmodule


module top (
    input wire      clk, 
    input wire      rst_btn,

    input wire      s_data,

    input wire [7:0] comparison_value,
    
    output wire     s_clk,
    output wire     cs,

    output wire     red_led,
    output wire     green_led
);

    wire rst;
    assign rst = ~rst_btn;
 
    reg [7:0]   in;

    always @ (posedge clk) begin
        in <= comparison_value;
    end

    adc_controller #(
        .clk_speed(8000000),
        .sclk_speed(100000)
    ) adc_inst (
        .rst(rst),
        .clk(clk),

        .data_in(s_data),

        .cs(cs),
        .sclk(s_clk),

        .adc_data(adc_data),
        .data_ready(data_ready)
    );

    wire [11:0] adc_data;
    wire        data_ready;

    comparator comparator_inst (
        .clk(clk),
        .rst(rst),
        .data_ready(data_ready),
        .data(adc_data[11:4]),
        .in(in),
        .red_enable(red_enable),
        .green_enable(green_enable)
    );

    wire        red_enable;
    wire        green_enable;

    pulse_generator pulse_generator_inst (
        .clk(clk),
        .rst(rst),
        .red_ctrl(red_enable),
        .green_ctrl(green_enable),
        .green_led(green_led),
        .red_led(red_led)
    );

endmodule



/*
Author: Ephren Manning
Title: adc_controller.v
Purpose: Control logic for AD7476A 12-bit SAR ADC
Clock Frequency: 8 MHz
*/

module adc_controller #(
    parameter clk_speed = 8000000,
    parameter sclk_speed = 100000 //20kHz min, 20MHz max
) (
    input wire          rst,
    input wire          clk,

    input wire          data_in,

    output reg          cs,
    output reg          sclk,

    output reg [11:0]   adc_data,
    output reg          data_ready
);

    integer sclk_period = (clk_speed / sclk_speed) - 1;
    integer sclk_half_period = ((clk_speed / sclk_speed) / 2) - 1;

    reg[5:0]            bit_counter;
    reg[9:0]            clk_counter;

    reg                 data_in_reg;

    always @ (posedge clk) begin

        if (rst == 1'b1) begin
            cs <= 1'b1;
            sclk <= 1'b0;
            //adc_data <= 8'd0;
            data_ready <= 1'b0;
            bit_counter <= 6'b0;
            clk_counter <= 10'b0;
            data_in_reg <= 1'b0;
        end else begin
            data_in_reg <= data_in;

            if (clk_counter == 10'd0) begin
                if (cs == 1'b1 & bit_counter == 6'b0) begin //adc read has been finished and is idle
                    cs <= 1'b0; //set chip select low, starting conversion
                    bit_counter <= 6'd32;
                    clk_counter <= sclk_half_period; // wait 1/2 sclk period to read first bit
                    data_ready <= 1'b0;
                end else if (cs == 1'b0 & bit_counter == 6'b0) begin //adc read has finished
                    cs <= 1'b1; 
                    clk_counter <= sclk_period;
                    data_ready <= 1'b1;
                end else begin
                    sclk <= ~sclk;
                    clk_counter <= sclk_half_period;
                    bit_counter <= bit_counter - 1;
                end
            end else begin
                clk_counter <= clk_counter - 1;
            end
        end
    end

    always @ (posedge sclk) begin
        if (rst == 1'b1) begin
            adc_data <= 12'd0;
        end else begin
            adc_data <= {adc_data[10:0], data_in_reg};
        end
    end

endmodule

module comparator (
  input wire		clk,
  input wire		rst,
  
  input wire		data_ready,
  input wire [7:0]  data,
  
  input wire [7:0]	in,
  
  output reg		red_enable,
  output reg		green_enable
);
  
  reg [7:0]			comp_reg;
  reg [7:0]			input_reg;
  
  always @ (posedge clk) begin
    if (rst == 1'b1) begin
      red_enable <= 1'b0;
      green_enable <= 1'b0;
      comp_reg <= 8'd0;
      input_reg <= 8'd0;
    end else if (data_ready == 1'b1) begin
      comp_reg <= data;
      input_reg <= in;
    end
    
    if (comp_reg >= input_reg) begin
      red_enable <= 1'b1;
      green_enable <= 1'b0;
    end else begin
      green_enable <= 1'b1;
      red_enable <= 1'b0;
    end
  end
  
  
endmodule


module pulse_generator (
    input wire  clk,
    input wire  rst,

    input wire  red_ctrl,
    input wire  green_ctrl,

    output reg  red_led,
    output reg  green_led
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule



Reference solution:
rtl/generated.v: 
    reg [23:0] red_ctrl_counter;

    //Red LED
    always @ (posedge clk) begin
        if(rst == 1'b1) begin
            red_led <= 1'b0;
            //green_led <= 1'b0;
            red_ctrl_counter <= 24'd0;
        end else if (red_ctrl == 1'b1) begin
            if (red_ctrl_counter == 24'd1000000 - 1) begin
                red_led <= ~red_led;
                red_ctrl_counter <= 24'd0;
            end else begin
                red_ctrl_counter <= red_ctrl_counter + 1;
            end
        end else begin
            red_led <= 1'b0;
        end
    end

    //Green LED
    always @ (posedge clk) begin
        if(rst == 1'b1) begin
            green_led <= 1'b0;
        end else begin
            green_led <= green_ctrl;
        end
    end