You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 JING Shuangyu
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none


module tt_um_shuangyu_top (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);


    // List all unused inputs to prevent warnings
    wire _unused = &{ena, ui_in[7:4], uio_in[7:0], 1'b0};

    /* verilator lint_off UNUSED */
    // All output pins must be assigned. If not used, assign to 0.
    assign uio_oe = 8'b1111_1111;
    assign uio_out[0] = 1'b0;

    wire [3:0] IO_P4_COL;
    wire [2:0] Enable;
    wire [7:0] SevenSegment;
    assign uio_out[7:4] = IO_P4_COL;
    assign uio_out[3:1] = Enable;
    assign uo_out[7:0] = SevenSegment;
    /* verilator lint_on UNUSED */

    calculator inst_calculator(
        .clk(clk),
        .rst_n(rst_n),
        .IO_P4_ROW(ui_in[3:0]),
        .IO_P4_COL(IO_P4_COL),
        .Enable(Enable),
        .SevenSegment(SevenSegment)
    );


endmodule


/*
 * Copyright (c) 2024 JING Shuangyu
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module calculator(
    input clk,
    input rst_n,
	input [3:0] IO_P4_ROW,
    output reg [3:0] IO_P4_COL,
	output reg [2:0] Enable,
	output reg [7:0] SevenSegment
);


localparam [1:0]
	OP_PLUS = 2'd0,
	OP_MINUS = 2'd1,
	OP_MULTIPLY = 2'd2,
	OP_DIVIDE = 2'd3;


//calculator state
reg [3:0] state; 
localparam [3:0] 
   state_clear = 4'd0,
   state_read = 4'd1,
   state_digit_pressed = 4'd2,
   state_plus_pressed = 4'd3,
   state_minus_pressed = 4'd4,
   state_multiply_pressed = 4'd5,
   state_divide_pressed = 4'd6,
   state_calculate = 4'd7,
   state_dividing = 4'd8,
   state_display_arg = 4'd9,
   state_display_result = 4'd10;


//calculator registers
reg [9:0] reg_arg;
reg [9:0] reg_result;
reg [9:0] reg_display;
reg [1:0] reg_operator;
reg [1:0] reg_operator_next;

wire key_pressed;
reg key_pressed_prev;  //check if new key come in



//component
wire [3:0] keypad_out;
wire [3:0] keypad_poller_row;
wire [3:0] keypad_poller_column;
reg divider_start;
reg [9:0] numerator;
reg [9:0] denominator;
wire [9:0] quotient;
//wire [9:0] remainder;
wire divider_done;
wire [11:0] bcd;

keypad_poller inst_keypad_poller(
    .clk(clk),
    .rst_n(rst_n),
    .keypad_row_in(IO_P4_ROW), 
    .keypad_col_out(keypad_poller_column),
    .row_out(keypad_poller_row),
    .key_pressed(key_pressed)
);

keypad_encoder inst_keypad_encoder(
    .clk(clk),
    .rst_n(rst_n),
    .rows(keypad_poller_row),
    .cols(keypad_poller_column),
    .key(keypad_out)
);

divider #(10) inst_divider (
    .clk(clk), 
    .rst_n(rst_n), 
    .numerator(numerator), 
    .denominator(denominator), 
    .start(divider_start), 
    .quotient(quotient), 
    //.remainder(remainder), 
    .done(divider_done)
);

bin2bcd inst_bin2bcd(
	.bin_in(reg_display),
	.bcd_out(bcd)
);

drive inst_drive(
	.clk(clk),
	.rst_n(rst_n),
	.en(1'b1),
	.bcd(bcd),
	.Enable(Enable),
	.SevenSegment(SevenSegment)
);
 
 

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n) begin
		state <= state_clear;
	end 
	else begin
		case(state)
			state_clear:
				begin
					reg_arg <= 0;
					reg_result <= 0;
					reg_display <= 0;
					reg_operator <= OP_PLUS;
					state <= state_read;
				end
			state_read:
				begin
					//check if a new key came in
					if(key_pressed && !key_pressed_prev) begin
						if(keypad_out < 4'hA) 
							state <= state_digit_pressed;
						else if(keypad_out >= 4'hE) //clear
							state <= state_clear;
						else if(keypad_out == 4'hA) //plus
							state <= state_plus_pressed;
						else if(keypad_out == 4'hB) //minus
							state <= state_minus_pressed;
						else if(keypad_out == 4'hC) //multiply (B)
							state <= state_multiply_pressed;
						else if(keypad_out == 4'hD) //divide (D)
						 	state <= state_divide_pressed;
					end
					key_pressed_prev <= key_pressed;
				end
			state_digit_pressed:
				begin
					/* verilator lint_off WIDTHEXPAND */
					//don't consume another keypress after hundreds
					if(reg_arg < 10'd100) 
					begin
						reg_arg <= reg_arg * 10 + keypad_out;
					end
					state <= state_display_arg;			
					/* verilator lint_on WIDTHEXPAND */		
				end
			state_plus_pressed:
				begin
					reg_operator_next <= OP_PLUS;
					state <= state_calculate; 
				end
			state_minus_pressed:
				begin
					reg_operator_next <= OP_MINUS;
					state <= state_calculate;
				end
			state_multiply_pressed:
				begin
					reg_operator_next <= OP_MULTIPLY;
					state <= state_calculate;
				end
			state_divide_pressed:
				begin
					reg_operator_next <= OP_DIVIDE;
					state <= state_calculate;
				end
			state_calculate:
				begin
					if(reg_operator == OP_PLUS) begin
						reg_result <= reg_result + reg_arg;
						state <= state_display_result;
					end 
					else if(reg_operator == OP_MINUS) begin
						reg_result <= reg_result - reg_arg;
						state <= state_display_result;
					end 
					else if(reg_operator == OP_MULTIPLY) begin
						reg_result <= reg_result * reg_arg;
						state <= state_display_result;
					end 
					else begin 
						divider_start <= 1'b1;
						numerator <= reg_result;
						denominator <= reg_arg;
						state <= state_dividing;
					end
					reg_operator <= reg_operator_next;
					reg_arg <= 0;
				end
			state_dividing:
				begin
					divider_start <= 1'b0;
					if(divider_done)
					begin
						reg_result <= quotient;
						state <= state_display_result;
					end
				end
			state_display_arg: 
				begin
					reg_display <= reg_arg;
					state <= state_read;
				end
			state_display_result:
				begin
					reg_display <= reg_result;
					state <= state_read;
				end
			default:
				begin
				end			
		endcase
	end
end

assign IO_P4_COL = keypad_poller_column;

endmodule


/*
this algorithm finds a remainder
while N = D do
  N := N - D
  Q := Q + 1
end
R := N
return (Q,R)
*/

module divider #(parameter SIZE=10) (
	input clk,
	input rst_n,
	input [SIZE-1:0] numerator,
	input [SIZE-1:0] denominator,
	input start,
	output [SIZE-1:0] quotient,
	//output [SIZE-1:0] remainder,
	output reg done
 );

//working registers
reg [SIZE-1:0] n;
reg [SIZE-1:0] d;
reg [SIZE-1:0] q; //the quotient is the number of times we subtracted n - d
reg busy;


always @(posedge clk or negedge rst_n) 
begin
	if(!rst_n) begin
		//reset working registers
		n <= 0;
		d <= 0;
		q <= 0;
		done <= 1'b0;
	end
	else begin
		if(start) begin
			n <= numerator;
			d <= denominator;
			busy <= 1'b1;
			done <= 1'b0;
		end 
		else if(busy) begin
			if(n >= d) begin
				q <= q + 1;
				n <= n - d;
			end
			else begin
				busy <= 1'b0;
				done <= 1'b1;
			end
		end
	end
end

assign quotient = q;
//assign remainder = n;

endmodule


//`timescale 1ns / 1ps

module keypad_poller(
	input clk,
	input rst_n, 
	input [3:0] keypad_row_in, //check which row receive 
	output reg [3:0] keypad_col_out, //generate 0001 0010 0100 1000 to scan each column
	output reg [3:0] row_out,
	output reg key_pressed
);


reg [2:0] state;
localparam [2:0]
	state_init  = 3'd0,
	state_shift_column  = 3'd1, 
	state_wait_debounce = 3'd2,
	state_check_row1 = 3'd3,
	state_keypress_hold  = 3'd4,
	state_check_row2  = 3'd5;
	
reg [16:0] clk_counter;
localparam [16:0] 
	// ignore the unstable transition stage
	ticks_debounce = 17'd10_0000,   //10ms clk:10Mhz 
	// hold key press state
	ticks_hold = 17'd2_0000;         //2ms
	
localparam [3:0] NO_KEY = 4'b0000;  //none of the four rows receive => no key press
	


// rotate column (0001, 0010, 0100, 1000)
// check if we get any output - if not, rotate again
// check if the output is held, emit the read row pins ???

always @(posedge clk or negedge rst_n) 
begin
	if(!rst_n) begin
		row_out <= NO_KEY;
		state <= state_init;
		keypad_col_out <= 4'b0001;
		key_pressed <= 1'b0;
	end else begin
		case(state)
			state_init:
				begin
					row_out <= NO_KEY;
					state <= state_shift_column;
					key_pressed <= 1'b0;
				end
			state_shift_column:
				begin
                    // rotate column (0001, 0010, 0100, 1000)
					keypad_col_out <= { keypad_col_out[2:0], keypad_col_out[3] };  
					state <= state_wait_debounce;
					clk_counter <= 17'h0;
				end
			state_wait_debounce:
				begin
					clk_counter <= clk_counter + 1;
					if(clk_counter == ticks_debounce)  
						state <= state_check_row1;
				end
			state_check_row1:
				//if no key pressed, check next column
				if(keypad_row_in == NO_KEY) 
					state <= state_shift_column;
				// detect key press then hold the state
				else begin  
					row_out <= keypad_row_in;
					state <= state_keypress_hold;  
					clk_counter <= 17'h0;
				end
			state_keypress_hold:
				begin
					clk_counter <= clk_counter + 1;
					if(clk_counter == ticks_hold)
						state <= state_check_row2;
				end
			state_check_row2: 
				begin
					// hold the press state utill the key is released
					if (keypad_row_in != NO_KEY)
					begin
						state <= state_keypress_hold;
						clk_counter <= 17'h0;
						key_pressed <= 1'b1;
					end else
					begin
						state <= state_init;
					end
				end

			default: begin
			end
		endcase
	end
end

endmodule


//`timescale 1ns / 1ps

/*
-- 16 digit keypad encoder module
-- hex encode
-- 1 2 3 A
-- 4 5 6 B
-- 7 8 9 C
-- E 0 F D	
*/

module keypad_encoder(
	input clk,
	input rst_n,
	input [3:0] rows,
	input [3:0] cols, 
	output reg [3:0] key
 );

localparam [3:0] 
	// unknown = 4'bxxxx,
	none = 4'b0000,
	one = 4'b0001,
	two = 4'b0010,
	three = 4'b0100,
	four = 4'b1000;
	
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
	 	key <= none;
	end else begin
		case(cols)
			one:
				case(rows)
					one: key   <= 4'h1;
					two: key   <= 4'h4;
					three: key <= 4'h7;
					four: key  <= 4'he;
					default: key <= none;
				endcase
			two:
				case(rows)
					one: key   <= 4'h2;
					two: key   <= 4'h5;
					three: key <= 4'h8;
					four: key  <= 4'h0;
					default: key <= none;
				endcase
			three:
				case(rows)
					one: key   <= 4'h3;
					two: key   <= 4'h6;
					three: key <= 4'h9;
					four: key  <= 4'hf;
					default: key <= none;
				endcase
			four:
				case(rows)
					one: key   <= 4'ha;
					two: key   <= 4'hb;
					three: key <= 4'hc;
					four: key  <= 4'hd;
					default: key <= none;
				endcase
			default: key <= none;
		endcase
	end
end

endmodule


`default_nettype none

module bin2bcd(
	input [9:0]	bin_in,
	output reg [11:0] bcd_out
    );
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




`default_nettype none

module drive(
    input clk,      
    input rst_n,   
    input en,
    input [11:0] bcd,  //3 digits          
    output reg [2:0] Enable,  //select which segment to display
    output reg [7:0] SevenSegment  //the current display segment
);



/*count 1_0000 clk cycle (1ms)，output a flag*/
reg [13:0] cnt0;
reg flag; 
always @ (posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt0 <= 14'b0;
        flag <= 1'b0;
    end
    else if (cnt0 < 14'd1_0000 - 1'b1) begin
        cnt0 <= cnt0 + 1'b1;
        flag <= 1'b0;
    end
    else begin
        cnt0 <= 14'b0;
        flag <= 1'b1;
    end
end


/*select digit to display*/
reg [1:0] cnt_sel  ; // 0 1 2 
reg [3:0] num_disp ; // current display number     
always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        cnt_sel <= 2'b0;
    else if(flag) begin
        if(cnt_sel < 2'd2)
            cnt_sel <= cnt_sel + 1'b1;
        else
            cnt_sel <= 2'b0;
    end
    else
        cnt_sel <= cnt_sel;
end


always @ (posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        Enable <= 3'b111;              //位选信号低电平有效(共阳极数码管，低电平导通)
        num_disp <= 4'b0;           
    end
    else begin
        if(en) begin
            case (cnt_sel)
                2'd0: begin
                    Enable <= 3'b110;      //当前数码管是哪个数码管
                    num_disp <= bcd[3:0];      //当前数码管显示什么值
                end
                2'd1: begin
                    Enable <= 3'b101;  
                    num_disp <= bcd[7:4];
                end
                2'd2: begin
                    Enable <= 3'b011;  
                    num_disp <= bcd[11:8];
                 
                end
                default: begin
                    Enable <= 3'b111;
                    num_disp <= 4'b0;
                end
            endcase
        end
        else begin
            Enable <= 3'b111;
            num_disp <= 4'b0;
        end
    end
end


/*decode*/
always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        SevenSegment <= 8'b1100_0000; //0
    else begin
        case (num_disp)
            4'd0 : SevenSegment <= {1'b1,7'b1000000}; //0
            4'd1 : SevenSegment <= {1'b1,7'b1111001}; //1
            4'd2 : SevenSegment <= {1'b1,7'b0100100}; //2
            4'd3 : SevenSegment <= {1'b1,7'b0110000}; //3
            4'd4 : SevenSegment <= {1'b1,7'b0011001}; //4
            4'd5 : SevenSegment <= {1'b1,7'b0010010}; //5
            4'd6 : SevenSegment <= {1'b1,7'b0000010}; //6
            4'd7 : SevenSegment <= {1'b1,7'b1111000}; //7
            4'd8 : SevenSegment <= {1'b1,7'b0000000}; //8
            4'd9 : SevenSegment <= {1'b1,7'b0010000}; //9
            4'd10: SevenSegment <= 8'b11111111;        //disable
            //4'd11: SevenSegment <= 8'b10111111;        //minus sign
            default: 
                SevenSegment <= {1'b1,7'b1000000};
        endcase
    end
end

endmodule


Reference solution:
rtl/generated.v: 	
reg [3:0] ones;
reg [3:0] tens;
reg [3:0] hundreds;

integer i;
always @(*) begin
	ones = 4'd0;
	tens = 4'd0;
	hundreds = 4'd0;
	for(i = 9; i >= 0; i = i - 1) begin
		if(ones >= 4'd5)  ones = ones + 4'd3;
		if(tens >= 4'd5)  tens = tens + 4'd3;
		if(hundreds >= 4'd5)  hundreds = hundreds + 4'd3;
		hundreds = {hundreds[2:0], tens[3]};
		tens = {tens[2:0],ones[3]};
		ones = {ones[2:0],bin_in[i]};
	end
end	
assign bcd_out = {hundreds, tens, ones};