You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Tórur Biskopstø Strøm
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none (* keep_hierarchy *)

module tt_um_torurstrom_async_lock (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

  // All output pins must be assigned. If not used, assign to 0.
  assign uo_out  = acks_0;
  assign uio_out = 0;
  assign uio_oe  = 0;

  // List all unused inputs to prevent warnings
  wire _unused = &{ena, clk, rst_n, uio_in, 1'b0};
  
  assign reqs_0 = ui_in;
  
  wire [7:0] reqs_0;
  wire [3:0] reqs_1;
  wire [1:0] reqs_2;
  wire reqs_3;
  
  wire [7:0] acks_0;
  wire [3:0] acks_1;
  wire [1:0] acks_2;
  wire acks_3;
  
  async_arbiter arb_0_0(acks_1[0], reqs_0[0], reqs_0[1], acks_0[0], acks_0[1], reqs_1[0]);
  async_arbiter arb_0_1(acks_1[1], reqs_0[2], reqs_0[3], acks_0[2], acks_0[3], reqs_1[1]);
  async_arbiter arb_0_2(acks_1[2], reqs_0[4], reqs_0[5], acks_0[4], acks_0[5], reqs_1[2]);
  async_arbiter arb_0_3(acks_1[3], reqs_0[6], reqs_0[7], acks_0[6], acks_0[7], reqs_1[3]);
  
  async_arbiter arb_1_0(acks_2[0], reqs_1[0], reqs_1[1], acks_1[0], acks_1[1], reqs_2[0]);
  async_arbiter arb_1_1(acks_2[1], reqs_1[2], reqs_1[3], acks_1[2], acks_1[3], reqs_2[1]);
  
  async_arbiter arb_2_0(acks_3, reqs_2[0], reqs_2[1], acks_2[0], acks_2[1], reqs_3);
  
  assign acks_3 = reqs_3;

endmodule


/*
 * Copyright (c) 2024 Tórur Biskopstø Strøm
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none (* keep_hierarchy *)

module async_arbiter (
  input ack,
  input req1,
  input req2,
  output ack1,
  output ack2,
  output req
);

  wire gnt1 /* synthesis keep */;
  wire gnt2 /* synthesis keep */;

  wire y1 /* synthesis keep */;
  wire y2 /* synthesis keep */;

  async_mutex mutex(req1, req2, gnt1, gnt2);

  assign y1 = gnt1 & ~ack2;
  assign y2 = gnt2 & ~ack1;

  c_element c_ack1(ack, y1, ack1);
  c_element c_ack2(ack, y2, ack2);

  assign req = y1 | y2;

endmodule


/*
 * Copyright (c) 2024 Tórur Biskopstø Strøm
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none (* keep_hierarchy *)

module async_mutex (
  input req1,
  input req2,
  output gnt1,
  output gnt2
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule



module nandm (
  input a,
  input b,
  output y
);

  assign y = ~(a & b);

endmodule


/*
 * Copyright (c) 2024 Tórur Biskopstø Strøm
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none (* keep_hierarchy *)

module c_element (
  input a,
  input b,
  output y
);

  //assign y = (a & b) | (y & (a | b));

  orm orm_y((a & b), (y & (a | b)), y);

endmodule

module orm (
  input a,
  input b,
  output y
);

  assign y = a | b;

endmodule


Reference solution:
rtl/generated.v: 
  wire o1 /* synthesis keep */;
  wire o2 /* synthesis keep */;

  // assign o1 = ~(req1 & o2);
  // assign o2 = ~(req2 & o1);

  nandm nandm_o1(req1, o2, o1);
  nandm nandm_o2(req2, o1, o2);

  assign gnt1 = ~o1 & o2;
  assign gnt2 = ~o2 & o1;