You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2025 Alida Bruka
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_Alida_DutyCycleMeter (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
  
  assign uio_oe = 8'b0000_0000;
  assign uio_out = 8'b0000_0000;

  DutyCycleMeter DutyCycleMeter(

    .clk(clk),              // Clock di sistema (es. 100 MHz)
    .rst(rst_n),          	 // Reset asincrono attivo basso
    .sig_in(ui_in[0]),           // Segnale da misurare
    .duty_out(uo_out[6:0]),  	 // Duty cycle in scala 0-127 (7 bit)
    .valid(uo_out[7])             // Segnale di validità misura
	);

  // List all unused inputs to prevent warnings
  wire _unused = &{ena, ui_in[7:1], uio_in,  1'b0};

endmodule


/*
 * Copyright (c) 2025 Alida Bruka
 * SPDX-License-Identifier: Apache-2.0
 */

module DutyCycleMeter(

    input wire clk,              // Clock di sistema (es. 100 MHz)
    input wire rst,           // Reset asincrono attivo basso
    input wire sig_in,          // Segnale da misurare
    output reg [6:0] duty_out,  // Duty cycle in scala 0-127 (7 bit)
    output reg valid            // Segnale di validità misura
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule

 


Reference solution:
rtl/generated.v: 
    // Stati FSM
    parameter IDLE    = 2'b00;
    parameter MEASURE = 2'b01;
    parameter CALC    = 2'b10;

    reg [1:0] state, next_state;

    // Edge detector
    reg sig_d1, sig_d2;
    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            sig_d1 <= 0;
            sig_d2 <= 0;
        end else begin
            sig_d1 <= sig_in;
            sig_d2 <= sig_d1;
        end
    end

    wire rising_edge  = (sig_d1 & ~sig_d2);

    // Contatori
    reg [10:0] ton_counter = 0;
    reg [10:0] tperiod_counter = 0;
    reg [10:0] ton_latched = 0;
    reg [10:0] tperiod_latched = 0;

    // FSM: transizione di stato
    always @(posedge clk or negedge rst) begin
        if (!rst)
            state <= IDLE;
        else
            state <= next_state;
    end

    // FSM: logica di transizione
    always @(*) begin
        case (state)
            IDLE:
                if (rising_edge) next_state = MEASURE;
                else             next_state = IDLE;

            MEASURE:
                if (rising_edge) next_state = CALC;
                else             next_state = MEASURE;

            CALC:
                next_state = IDLE;

            default:
                next_state = IDLE;
        endcase
    end

    // FSM: logica di uscita
    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            ton_counter <= 0;
            tperiod_counter <= 0;
            duty_out <= 0;
            valid <= 0;
            ton_latched <= 0;
            tperiod_latched <= 0;
        end else begin
            valid <= 0;
            case (state)
                IDLE: begin
                    ton_counter <= 0;
                    tperiod_counter <= 0;
                end

                MEASURE: begin
                    tperiod_counter <= tperiod_counter + 1;
                    if (sig_in)
                        ton_counter <= ton_counter + 1;
                end

                CALC: begin
                    ton_latched <= ton_counter;
                    tperiod_latched <= tperiod_counter;
                    if (tperiod_counter != 0) begin
//                        duty_out <= (ton_counter * 127) / tperiod_counter;
			duty_out <= (ton_latched << 7) / tperiod_latched;
                        valid <= 1;
                    end else begin
                        duty_out <= 0;
                    end
                end
            endcase
        end
    end