You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 some-cool-org
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_romless_cordic_engine (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




module CORDIC_Engine_v1 #(
	parameter DATA_WIDTH = 18,
    parameter N_PE = 16
)
(
    input i_clk,
    input i_rst_n,
    input signed [DATA_WIDTH - 1 : 0] in_x,
    input signed [DATA_WIDTH - 1 : 0] in_y,
    input signed [DATA_WIDTH - 1 : 0] in_alpha,
    input signed [DATA_WIDTH - 1 : 0] in_atan,
    input [1:0] i_quadrant,
    input valid_in,
    
    output reg signed [DATA_WIDTH - 1 : 0] out_x = 0,
    output reg signed [DATA_WIDTH - 1 : 0] out_y = 0,
    output reg signed [DATA_WIDTH - 1 : 0] out_alpha = 0,
    output reg [1:0] out_quadrant = 0,
    output reg valid_out = 0
);


reg [$clog2(N_PE) : 0] count;
reg signed [DATA_WIDTH-1 : 0] r_alpha;
reg signed [DATA_WIDTH-1 : 0] r_x;
reg signed [DATA_WIDTH-1 : 0] r_y;
reg state;

always @(posedge i_clk) begin
    if(!i_rst_n) begin
        count <= 0;
        state <= 0;
        r_alpha <= 0;
        r_x <= 0;
        r_y <= 0;
        out_x <= 0;
        out_y <= 0;
        out_alpha <= 0;
        valid_out <= 0;
        out_quadrant <= 0;
    end
    else begin
        case(state)
            0: begin
                valid_out <= 0;
                out_quadrant <= out_quadrant;
                if(valid_in) begin
                    count <= count + 1;
                    state <= 1;
                    if(in_alpha[DATA_WIDTH - 1] == 1'b0) begin
                        r_alpha <= in_alpha + ~(in_atan) + 1; 
                        r_x <= in_x - (in_y >>> count);
                        r_y <= in_y + (in_x >>> count);
                    end
                    else begin
                        r_alpha <= in_alpha + (in_atan);
                        r_x <= in_x + (in_y >>> count);
                        r_y <= in_y - (in_x >>> count);
                    end
                end
                else begin
                    r_alpha <= r_alpha;
                    r_x <= r_x;
                    r_y <= r_y;
                    count <= count;
                    state <= 0;
                end
            end

            1: begin
                if(count == N_PE) begin
                    count <= 0; // Reset counter after reaching N_PE
                    state <= 0; // Go back to initial state
                    valid_out <= 1; // Indicate valid output
                    out_quadrant <= i_quadrant; // Update quadrant
                    out_alpha <= r_alpha;
                    out_x <= r_x;
                    out_y <= r_y;
                end
                else begin
                    count <= count + 1;
                    if(r_alpha[DATA_WIDTH - 1] == 1'b0) begin
                        r_alpha <= r_alpha + ~(in_atan) + 1; 
                        r_x <= r_x - (r_y >>> count);
                        r_y <= r_y + (r_x >>> count);
                    end
                    else begin
                        r_alpha <= r_alpha + (in_atan);
                        r_x <= r_x + (r_y >>> count);
                        r_y <= r_y - (r_x >>> count);
                    end
                end
            end
        endcase
    end
end

endmodule


module dynamic_atan#(
    parameter N_PE = 16,
    parameter DATA_WIDTH = 18
)(
    input i_clk,
    input i_rstn,

    input [DATA_WIDTH-1:0] i_data,
    input i_valid,

    output reg [DATA_WIDTH-1:0] o_atan_data,
    output reg o_valid,
    output reg o_done
);

    /* ------ Dynamic generation of atan coefficients for CORDIC_PE ------ */
    /*
        It uses hybrid mechnaism to generate atan coefficients
        Iteration 0: Take the actaul value of atan(2^0) from the input
        Iteration 1-5: Compute using Taylor series expansion
                    2^(-i) - ((2^(-3i)/4)+(2^(-3i)/16)+(2^(-3i)/64))  (Same as, x-(x^3)/3)
        Iteration 6-last: atan(2^(-i)) = 2^(-i)
    */

    reg [$clog2(N_PE)-1:0] atan_counter;
    reg state;

    wire [DATA_WIDTH-1:0] inv_2_pow_i;
    wire [DATA_WIDTH-1:0] inv_2_pow_3i;

    assign inv_2_pow_i = 16'b0001000000000000 >> atan_counter;
    assign inv_2_pow_3i = 16'b0001000000000000 >> 3*atan_counter; 

    always@(posedge i_clk) begin
        if(!i_rstn) begin
            atan_counter <= 0;
            state <= 0;
            o_atan_data <= 0;
            o_valid <= 0;
            o_done <= 0;
        end else begin
            case(state)
                0: begin
                    o_done <= 0;
                    if(i_valid) begin
                        o_atan_data <= i_data;
                        o_valid <= 1;
                        state <= 1;
                        atan_counter <= atan_counter + 1;
                    end
                    else begin
                        o_valid <= 0;
                        state <= 0;
                        atan_counter <= atan_counter;
                    end
                end

                1: begin
                    if(atan_counter>=1 && atan_counter<5) begin
                        atan_counter <= atan_counter + 1;
                        o_valid <= 1;
                        o_atan_data <= inv_2_pow_i - ((inv_2_pow_3i >> 2) + (inv_2_pow_3i >> 4) + (inv_2_pow_3i >> 6));
                    end
                    else if(atan_counter>=5) begin
                        if(atan_counter == N_PE) begin
                            atan_counter <= 0; // Reset counter after reaching N_PE
                            state <= 0; // Go back to initial state
                            o_valid <= 0; // Reset valid signal
                            o_done <= 1; // Indicate completion
                        end else begin
                            o_atan_data <= inv_2_pow_i;
                            atan_counter <= atan_counter + 1;
                            o_valid <= 1;
                        end
                    end
                end

                default: begin
                    o_valid <= 0;
                    state <= 0; // Reset to initial state
                    atan_counter <= 0; // Reset counter
                end

            endcase
        end
    end
endmodule

module SPI_Slave #(
    parameter DATA_WIDTH = 8
)(
    // System signals
    input  wire clk,           // System clock
    input  wire rst_n,         // Active low reset
    
    // SPI interface
    input  wire sclk,          // SPI clock from master
    input  wire mosi,          // Master Out, Slave In
    output reg  miso,          // Master In, Slave Out
    input  wire cs_n,          // Chip select (active low)
    
    // Data interface
    input  wire [DATA_WIDTH-1:0] tx_data,    // Data to transmit
    output reg  [DATA_WIDTH-1:0] rx_data,    // Received data
    output reg  tx_req,                      // Request for new transmit data
    output reg  rx_valid                     // Received data valid
    
    // Control signals
    //input  wire cpol,          // Clock polarity (0: idle low, 1: idle high)
    //input  wire cpha           // Clock phase (0: sample on first edge, 1: sample on second edge)
);
    wire cpol;
    wire cpha;
    
    assign cpol = 1'b0;
    assign cpha = 1'b0;
    
    // Internal signals
    reg [2:0] sclk_sync;       // Sync for sclk
    reg [2:0] cs_n_sync;       // Sync for cs_n
    reg sclk_prev;             // Previous sclk state
    reg cs_active;             // Chip select active flag
    
    // Shift registers
    reg [DATA_WIDTH-1:0] tx_shift_reg;
    reg [DATA_WIDTH-1:0] rx_shift_reg;
    
    // Bit counter
    reg [$clog2(DATA_WIDTH):0] bit_count;
    
    // Edge detection
    wire sclk_posedge, sclk_negedge;
    wire sample_edge, shift_edge;
    wire cs_falling, cs_rising;
    
    // Synchronize external signals to system clock
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            sclk_sync <= 3'b000;
            cs_n_sync <= 3'b111;
        end else begin
            sclk_sync <= {sclk_sync[1:0], sclk};
            cs_n_sync <= {cs_n_sync[1:0], cs_n};
        end
    end
    
    // Edge detection
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            sclk_prev <= 1'b0;
        end else begin
            sclk_prev <= sclk_sync[2];
        end
    end
    
    assign sclk_posedge = !sclk_prev && sclk_sync[2];
    assign sclk_negedge = sclk_prev && !sclk_sync[2];
    assign cs_falling = cs_n_sync[2:1] == 2'b10;
    assign cs_rising = cs_n_sync[2:1] == 2'b01;
    
    // Determine sampling and shifting edges based on CPOL and CPHA
    assign sample_edge = (cpol == cpha) ? sclk_posedge : sclk_negedge;
    assign shift_edge = (cpol == cpha) ? sclk_negedge : sclk_posedge;
    
    // Chip select active detection
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            cs_active <= 1'b0;
        end else begin
            if (cs_falling) begin
                cs_active <= 1'b1;
            end else if (cs_rising) begin
                cs_active <= 1'b0;
            end
        end
    end
    
    // Bit counter
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            bit_count <= {($clog2(DATA_WIDTH)+1){1'b0}};
        end else begin
            if (!cs_active) begin
                bit_count <= {($clog2(DATA_WIDTH)+1){1'b0}};
            end else if (sample_edge && cs_active) begin
                if (bit_count == DATA_WIDTH - 1) begin
                    bit_count <= {($clog2(DATA_WIDTH)+1){1'b0}};
                end else begin
                    bit_count <= bit_count + 1;
                end
            end
        end
    end
    
    // Transmit shift register and MISO output
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            tx_shift_reg <= {DATA_WIDTH{1'b0}};
            miso <= 1'b0;
        end else begin
            if (cs_falling) begin
                // Load new data at start of transaction
                tx_shift_reg <= tx_data;
                miso <= tx_data[DATA_WIDTH-1];
            end else if (shift_edge && cs_active) begin
                // Shift out next bit
                tx_shift_reg <= {tx_shift_reg[DATA_WIDTH-2:0], 1'b0};
                miso <= tx_shift_reg[DATA_WIDTH-2];
            end else if (!cs_active) begin
                miso <= 1'b0;
            end
        end
    end 

    
    // Receive shift register
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            rx_shift_reg <= {DATA_WIDTH{1'b0}};
        end else begin
            if (sample_edge && cs_active) begin
                rx_shift_reg <= {rx_shift_reg[DATA_WIDTH-2:0], mosi};
            end
        end
    end
    
    // Output received data
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            rx_data <= {DATA_WIDTH{1'b0}};
        end else begin
            if (sample_edge && cs_active && (bit_count == DATA_WIDTH - 1)) begin
                rx_data <= {rx_shift_reg[DATA_WIDTH-2:0], mosi};
            end
        end
    end
    
    // Generate control signals
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            rx_valid <= 1'b0;
            tx_req <= 1'b0;
        end else begin
            // rx_valid pulse when byte is completely received
            rx_valid <= sample_edge && cs_active && (bit_count == DATA_WIDTH - 1);
            
            // tx_req pulse when byte transmission is complete (request next byte)
            tx_req <= shift_edge && cs_active && (bit_count == DATA_WIDTH - 1);
        end
    end

endmodule

module top_CORDIC_Engine_v1#(
    parameter DATA_WIDTH = 18,
    parameter N_PE = 15
)
(
    input i_clk,
    input i_rst_n,
    
    input signed [DATA_WIDTH - 1 : 0] in_x,
    input signed [DATA_WIDTH - 1 : 0] in_y,
    input signed [DATA_WIDTH - 1 : 0] in_alpha,
    input [DATA_WIDTH -1 : 0] in_atan_0,
    input i_valid_in,

    output reg signed [DATA_WIDTH - 1 : 0] out_costheta,
    output reg signed [DATA_WIDTH - 1 : 0] out_sintheta,
    output reg signed [DATA_WIDTH - 1 : 0] out_alpha,
    output reg o_valid_out
);

   


    /* ---- Pre-processing: Mapping the input angle to appropriate quadrants ---- */
    // Note: Angle should be in the radians in [0,2*pi]
    
    reg signed [DATA_WIDTH-1 : 0] r_i_alpha1, r_i_alpha2;
    reg signed [DATA_WIDTH-1 : 0] diff1, diff2, diff3;
    reg diff_valid;

    always@(posedge i_clk) begin
        if(i_valid_in) begin
            diff1 <= in_alpha - 16'h1922;
            diff2 <= in_alpha - 16'h3244;
            diff3 <= in_alpha - 16'h4b66;
            r_i_alpha1 <= in_alpha;
            diff_valid <= 1'b1;
        end
        else diff_valid <= 1'b0;
    end

    wire v1, v2, v3;
    assign v1 = diff1[DATA_WIDTH-1];
    assign v2 = diff2[DATA_WIDTH-1];
    assign v3 = diff3[DATA_WIDTH-1];

    wire [1:0] w_i_quadrant;
    assign w_i_quadrant[1] = ~v1&~v2;
    assign w_i_quadrant[0] = ~v1&(~(v2^v3));

    reg [1:0] quadrant;
    reg quadrant_valid;
    always@(posedge i_clk) begin
        if(diff_valid) begin
            case(w_i_quadrant)
                2'b00: begin 
                    quadrant <= 2'b00; // Q1
                    quadrant_valid <= 1'b1;
                    r_i_alpha2 <= r_i_alpha1;
                end

                2'b01: begin
                    quadrant <= 2'b01; // Q2
                    quadrant_valid <= 1'b1;
                    r_i_alpha2 <= diff1;
                end

                2'b10: begin
                    quadrant <= 2'b10; // Q2
                    quadrant_valid <= 1'b1;
                    r_i_alpha2 <= diff2;
                end

                2'b11: begin
                    quadrant <= 2'b11;
                    quadrant_valid <= 1'b1;
                    r_i_alpha2 <= diff3;
                end

                default: quadrant_valid <= 1'b0;
            endcase
        end
        else quadrant_valid <= 1'b0;
    end

    reg r_quadrant_valid;
    always@(posedge i_clk) r_quadrant_valid <= quadrant_valid;

    wire [1:0] w_quadrant;

    wire [DATA_WIDTH-1 : 0] w_costheta, w_sintheta;

    wire [DATA_WIDTH-1 : 0] w_o_alpha;

    wire w_o_valid;

    wire [DATA_WIDTH-1 : 0] w_atan;

    /* ------------------ Dynamic_atan_coefficient_generator ------------ */
    dynamic_atan #(
        .N_PE(N_PE),
        .DATA_WIDTH(DATA_WIDTH)
    )
    dynamic_atan_inst (
        .i_clk(i_clk),
        .i_rstn(i_rst_n),
        .i_data(in_atan_0),
        .i_valid(quadrant_valid),
        .o_atan_data(w_atan),
        .o_valid(),
        .o_done()
    );
    
    
    /* ------------------ CORDIC ENGINE ----------------------- */
    CORDIC_Engine_v1 # (
        .DATA_WIDTH(DATA_WIDTH),
        .N_PE(N_PE)
    )
    CORDIC_Engine_v1_inst (
        .i_clk(i_clk),
        .i_rst_n(i_rst_n),
        .in_x(in_x),
        .in_y(in_y),
        .in_alpha(r_i_alpha2),
        .in_atan(w_atan),
        .i_quadrant(quadrant),
        .valid_in(r_quadrant_valid),
        .out_x(w_costheta),
        .out_y(w_sintheta),
        .out_alpha(w_o_alpha),
        .out_quadrant(w_quadrant),
        .valid_out(w_o_valid)
    );


    /* ---------------------- Post-processing the CORDIC Engine result ---------------- */
    wire [DATA_WIDTH-1 : 0] twos_comp_costheta, twos_comp_sintheta;
    assign twos_comp_costheta = ~w_costheta + 1;
    assign twos_comp_sintheta = ~w_sintheta + 1;

    always@(posedge i_clk) begin
        if(w_o_valid) begin
	        out_alpha <= w_o_alpha;
            case(w_quadrant)
                2'b00: begin
                    out_costheta <= w_costheta;
                    out_sintheta <= w_sintheta;
                    o_valid_out <= 1'b1;
                end 

                2'b01: begin
                    out_costheta <= twos_comp_sintheta;
                    out_sintheta <= w_costheta;
                    o_valid_out <= 1'b1;
                end

                2'b10: begin
                    out_costheta <= twos_comp_costheta;
                    out_sintheta <= twos_comp_sintheta;
                    o_valid_out <= 1'b1;
                end

                2'b11: begin
                    out_costheta <= w_sintheta;
                    out_sintheta <= twos_comp_costheta;
                    o_valid_out <= 1'b1;
                end

                default: o_valid_out <= 1'b0;
            endcase
        end

        else o_valid_out <= 1'b0;
    end


endmodule


module cordic_fsm #(
    parameter DATA_WIDTH_CORDIC = 16,
    parameter DATA_WIDTH_SPI = 8,
    parameter N_PE = 13
)(
    input  wire                    i_clk,
    input  wire                    rst_n,
    input  wire                    sclk,
    input  wire                    mosi,
    output wire                    miso,
    input  wire                    cs_n,
    output reg                     data_ready 
);

    // SPI interface
    reg  [DATA_WIDTH_SPI-1:0] spi_tx_data;
    wire [DATA_WIDTH_SPI-1:0] spi_rx_data;     
    wire spi_rx_valid;
    wire spi_tx_req;

    SPI_Slave #(
        .DATA_WIDTH(DATA_WIDTH_SPI)
    ) spi_slave_inst (
        .clk(i_clk),
        .rst_n(rst_n),
        .sclk(sclk),
        .mosi(mosi),
        .miso(miso),
        .cs_n(cs_n),
        .tx_data(spi_tx_data),
        .rx_data(spi_rx_data),
        .tx_req(spi_tx_req),
        .rx_valid(spi_rx_valid)
    );

    // CORDIC
    wire [DATA_WIDTH_CORDIC-1:0] in_x, in_y, in_alpha, in_atan_0;
    wire [DATA_WIDTH_CORDIC-1:0] out_costheta, out_sintheta, out_alpha;
    wire o_valid_out;

    top_CORDIC_Engine_v1 #(
        .DATA_WIDTH(DATA_WIDTH_CORDIC),
        .N_PE(N_PE)
    ) cordic_inst (
        .i_clk(i_clk),
        .i_rst_n(rst_n),
        .in_x(in_x),
        .in_y(in_y),
        .in_alpha(in_alpha),
        .in_atan_0(in_atan_0),
        .i_valid_in(valid_cordic_angle),
        .out_costheta(out_costheta),
        .out_sintheta(out_sintheta),
        .out_alpha(out_alpha),
        .o_valid_out(o_valid_out)
    );

    // FSM States
    localparam [2:0] S_IDLE       = 3'd0,
                     S_RX         = 3'd1,
                     S_WAIT       = 3'd2,
                     S_LOAD       = 3'd3,
                     S_TX         = 3'd4,
                     S_DONE       = 3'd5;

    reg [2:0] state;
    reg [3:0] rx_byte_count;
    reg [2:0] tx_byte_count;
    reg [63:0] r_spi_rx_data;
    reg [47:0] r_spi_tx_data;
    reg valid_cordic_angle;

    assign in_x      = r_spi_rx_data[15:0];
    assign in_y      = r_spi_rx_data[31:16];
    assign in_alpha  = r_spi_rx_data[47:32];
    assign in_atan_0 = r_spi_rx_data[63:48];

    always @(posedge i_clk ) begin
        if (!rst_n) begin
            state              <= S_IDLE;
            rx_byte_count      <= 0;
            tx_byte_count      <= 0;
            r_spi_rx_data      <= 0;
            r_spi_tx_data      <= 0;
            valid_cordic_angle <= 0;
            spi_tx_data        <= 0;
            data_ready         <= 0;
        end else begin
            case (state)
                S_IDLE: begin
                    valid_cordic_angle <= 0;
                    tx_byte_count      <= 0;
                    rx_byte_count      <= 0;
                    data_ready         <= 0;
                    if (spi_rx_valid) begin
                        r_spi_rx_data[7:0] <= spi_rx_data;
                        rx_byte_count <= 1;
                        state <= S_RX;
                    end
                end

                S_RX: begin
                    valid_cordic_angle <= 0;
                    if (spi_rx_valid) begin
                        r_spi_rx_data[((rx_byte_count+1)*8)-1 -: 8] <= spi_rx_data;
                        rx_byte_count <= rx_byte_count + 1;
                        if (rx_byte_count == 7) begin
                            valid_cordic_angle <= 1;
                            state <= S_WAIT;
                        end
                    end
                end

                S_WAIT: begin
                    valid_cordic_angle <= 0;
                    if (o_valid_out) begin
                        r_spi_tx_data <= {out_alpha, out_costheta, out_sintheta}; // 56 bits
                        state <= S_LOAD;
                        data_ready <= 1'b1;
                    end
                end

                S_LOAD: begin
                    spi_tx_data   <= r_spi_tx_data[7:0];
                    tx_byte_count <= 1; 
                    state <= S_TX;
                end

                S_TX: begin
                    if (spi_tx_req) begin
                        spi_tx_data   <= r_spi_tx_data[15:8];
                        r_spi_tx_data <= r_spi_tx_data >> 8;
                        tx_byte_count <= tx_byte_count + 1;
                        if (tx_byte_count == 6) begin
                            state <= S_DONE;
                    end
                    end
                end

                S_DONE: begin
                    if (cs_n) begin
                        state <= S_IDLE;
                        data_ready <= 1'b0;
                    end
                end

                default: state <= S_IDLE;
            endcase
        end
    end

endmodule


Reference solution:
rtl/generated.v: 
  // All output pins must be assigned. If not used, assign to 0.
  assign uio_out = 0;
  assign uio_oe  = 0;

  // List all unused inputs to prevent warnings
   wire _unused = &{ena,uio_in,ui_in[7:3],1'b0};


    localparam DATA_WIDTH_CORDIC = 16;
    localparam N_PE = 13;
    localparam DATA_WIDTH_SPI = 8;
    
    // internal wires to interface with cordic 
    wire   sclk;
    wire   mosi;
    wire   miso;
    wire   cs_n;
    wire   data_ready;


   // assiging the ports to the dedicated io's
    assign sclk = ui_in[0];
    assign mosi = ui_in[1];
    assign cs_n = ui_in[2];

    // assign the output port 
    assign uo_out[0] = miso;
    assign uo_out[1] = data_ready;
    assign uo_out[7:2] = 6'b0;
        
    cordic_fsm # (.DATA_WIDTH_CORDIC(DATA_WIDTH_CORDIC),
                  .DATA_WIDTH_SPI(DATA_WIDTH_SPI),
                  .N_PE(N_PE)
    ) top_cordic_inst (
       .i_clk(clk),
       .rst_n(rst_n),
       .sclk(sclk),
       .mosi(mosi),
       .miso(miso),
       .cs_n(cs_n),
       .data_ready(data_ready)
    );