You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Your Name
 * SPDX-License-Identifier: Apache-2.0
 */

`define default_netname none

module tt_um_ian_keypad_controller (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // will go high when the design is enabled
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

  // All output pins must be assigned. If not used, assign to 0.
  assign uio_out[7:6] = 0;
  assign uio_oe  = 8'b00111111;

  assign uo_out[7] = 0;
  wire reset = !rst_n;
  wire [3:0] key;

  // the keypad scanner
  keypad keypad (
    .clk(clk),
    .reset(reset),
    .rows(ui_in[3:0]), // input
    .cols(uio_out[3:0]), // output
    .counter_cols(uio_out[5:4]),
    .key(key)
  );
  
  // the digit decoder
  decoder decoder (
    .key(key),
    .segments(uo_out[6:0])
  );

endmodule


`default_nettype none

module keypad(
    input wire clk,
    input wire reset,
    input [3:0] rows, // inputs
    output reg [3:0] cols, // outputs
    output reg [1:0] counter_cols,
    output reg [3:0] key
);

// Debounced Rows

// Instantiate the debounce module for each row
wire [3:0] debounced_rows; // Debounced signals for each row

debounce #(.HIST_LEN(8)) debounce_row0 (
    .clk(clk),
    .reset(reset),
    .button(rows[0]),
    .debounced(debounced_rows[0])
);

debounce #(.HIST_LEN(8)) debounce_row1 (
    .clk(clk),
    .reset(reset),
    .button(rows[1]),
    .debounced(debounced_rows[1])
);

debounce #(.HIST_LEN(8)) debounce_row2 (
    .clk(clk),
    .reset(reset),
    .button(rows[2]),
    .debounced(debounced_rows[2])
);

debounce #(.HIST_LEN(8)) debounce_row3 (
    .clk(clk),
    .reset(reset),
    .button(rows[3]),
    .debounced(debounced_rows[3])
);


// Drive power to cols

reg [4:0]   col_update_count;
always @(posedge clk or posedge reset) begin
    if(reset) begin
        col_update_count <= 5'h0;
        counter_cols <= 2'b00;
    end else begin
        col_update_count <= col_update_count + 1;
        if (col_update_count == 5'h0)
           counter_cols <= counter_cols + 1;
    end
end


always @(*) begin
    case(counter_cols)
        2'b00: cols = 4'b0001;
        2'b01: cols = 4'b0010;
        2'b10: cols = 4'b0100;
        2'b11: cols = 4'b1000;
        default: cols = 4'b0000;
    endcase
end



task match_one; begin $display("1 was clicked"); end endtask
task match_two; begin $display("2 was clicked"); end endtask
task match_three; begin $display("3 was clicked"); end endtask
task match_a; begin $display("A was clicked"); end endtask
task match_four; begin $display("4 was clicked"); end endtask
task match_five; begin $display("5 was clicked"); end endtask
task match_six; begin $display("6 was clicked"); end endtask
task match_b; begin $display("B was clicked"); end endtask
task match_seven; begin $display("7 was clicked"); end endtask
task match_eight; begin $display("8 was clicked"); end endtask
task match_nine; begin $display("9 was clicked"); end endtask
task match_c; begin $display("C was clicked"); end endtask
task match_star; begin $display("* was clicked"); end endtask
task match_zero; begin $display("0 was clicked"); end endtask
task match_hashtag; begin $display("# was clicked"); end endtask
task match_d; begin $display("D was clicked"); end endtask



always @(*) begin
    key = 0;


    if (cols == 4'b0001 && debounced_rows == 4'b0001) begin
        key = 1;
    end else if (cols == 4'b0001 && debounced_rows == 4'b0010) begin
        key = 4;
    end else if (cols == 4'b0001 && debounced_rows == 4'b0100) begin
        key = 7;
    end else if (cols == 4'b0001 && debounced_rows == 4'b1000) begin
        key = 15;
    end else if (cols == 4'b0010 && debounced_rows == 4'b0001) begin
        key = 2;
    end else if (cols == 4'b0010 && debounced_rows == 4'b0010) begin
        key = 5;
    end else if (cols == 4'b0010 && debounced_rows == 4'b0100) begin
        key = 8;
    end else if (cols == 4'b0010 && debounced_rows == 4'b1000) begin
        key = 0;
    end else if (cols == 4'b0100 && debounced_rows == 4'b0001) begin
        key = 3;
    end else if (cols == 4'b0100 && debounced_rows == 4'b0010) begin
        key = 6;
    end else if (cols == 4'b0100 && debounced_rows == 4'b0100) begin
        key = 9;
    end else if (cols == 4'b0100 && debounced_rows == 4'b1000) begin
        key = 14;
    end else if (cols == 4'b1000 && debounced_rows == 4'b0001) begin
        key = 10;
    end else if (cols == 4'b1000 && debounced_rows == 4'b0010) begin
        key = 11;
    end else if (cols == 4'b1000 && debounced_rows == 4'b0100) begin
        key = 12;
    end else if (cols == 4'b1000 && debounced_rows == 4'b1000) begin
        key = 13;
    end
end

endmodule


`default_nettype none

module debounce #(
    parameter HIST_LEN = 8
)(
    input wire clk,
    input wire reset,
    input wire button,
    output reg debounced
);
    localparam on_value = 2 ** HIST_LEN - 1;
    reg [HIST_LEN-1:0] button_hist;

    always @(posedge clk) begin
        if(reset) begin

            button_hist <= 0;
            debounced <= 1'b0;

        end else begin

            button_hist <= {button_hist[HIST_LEN-2:0], button};

            if(button_hist == on_value)
                debounced <= 1'b1;

            else if(button_hist == {HIST_LEN{1'b0}})
                debounced <= 1'b0;
       end
    end

endmodule


`default_nettype none

module decoder(
    input [3:0] key, // inputs
    output reg [6:0] segments // outputs
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




Reference solution:
rtl/generated.v: 
    always @(*) begin
        case(key)
            //                7654321
            0:  segments = 7'b0111111;
            1:  segments = 7'b0000110;
            2:  segments = 7'b1011011;
            3:  segments = 7'b1001111;
            4:  segments = 7'b1100110;
            5:  segments = 7'b1101101;
            6:  segments = 7'b1111100;
            7:  segments = 7'b0000111;
            8:  segments = 7'b1111111;
            9:  segments = 7'b1100111;
            default:
                segments = 7'b0000000;
        endcase
    end