You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Your Name
 * SPDX-License-Identifier: Apache-2.0
 */// name of my parent directory; the top level module

`default_nettype none

module tt_um_juarez_jimenez(
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

  // All output pins must be assigned. If not used, assign to 0.
  //assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in
  assign uio_out = 0;
  assign uio_oe  = 0;

  // List all unused inputs to prevent warnings
  // wire _unused = &{ena, clk, rst_n, 1'b0};

//define all wires here :p 

//lfsrout, ris, fall, pulse, signal, ogfeedback, selected feedback reset 
wire [7:0] lfsroutput;
wire risingedge, fallingedge, signal, pulse, ogfeedback, feedbackselected;
wire reset = ~rst_n; 

assign uo_out = lfsroutput;

assign ogfeedback = lfsroutput[7] ^ lfsroutput[5] ^ lfsroutput[4] ^ lfsroutput[3]; // calculaiting feedback



lfsr lfsr_func(.clk(clk), .reset_i(reset), .en_i(1'b1),  .seed(ui_in), .feedback(feedbackselected), .q_o(lfsroutput)); //feedback from feedback selector

//edge detection on lfsr output bit 0 
edgedetector edge_func(.clk(clk), .reset_i(reset), .lfsroutput(lfsroutput[0]), .risingedge(risingedge), .fallingedge(fallingedge));

//EXCITED SYNAPSES YAYAYAYYAYA
exictatorysynapses ec_fun(.clk(clk), .reset_i(reset), .edgedetectoroutput(risingedge), .excitedpulse(pulse));


//chill synapses #boring
inhibatorysynapses ih_func(.clk(clk), .reset_i(reset), .edgedetectoroutput(fallingedge), .inhibitorysignal(signal));

feedback feedbackfunc(.ogfeedback(ogfeedback), .excitedpulse(pulse), .inhibitorysignal(signal), .feedbackselected(feedbackselected));

endmodule


`default_nettype none

module dff (
    input [0:0] clk,
    input [0:0] en_i,
    input [0:0] d_in,
    input [0:0] seed,
    input [0:0] reset_i,
    output[0:0] q_o
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule



`default_nettype none

module edgedetector( 
    input [0:0] clk,
    input [0:0] reset_i,

    //the output of the lfsr will be the inputs to edge detector
    input [0:0] lfsroutput,
    
    //output will determine whether exictatory or inhibatory synapses w/ 1s and 0s
    output [0:0] risingedge,
    output[0:0] fallingedge
);

reg[0:0] prevedge;
reg[0:0] risingedge_r; 
reg[0:0] fallingedge_r; 

// edge detector from 125 , instead of buttons, its the edges 
always @(posedge clk) begin
    if (reset_i) begin
        // resetting all reg
        prevedge <= 1'b0;
        risingedge_r <= 1'b0;
        fallingedge_r <= 1'b0;
    end else begin
    
        // pulse for one clk cycle on rising edge of lfsr output
        if ((lfsroutput == 1'b1) && (prevedge == 1'b0)) begin
            risingedge_r <= 1'b1;
        end else begin
            risingedge_r <= 1'b0;
        end
            
        // pulse for one clk cycle on falling edge of lfsr output
        if((lfsroutput == 1'b0) && (prevedge == 1'b1)) begin
            fallingedge_r <= 1'b1;
        end else begin
            fallingedge_r <= 1'b0;
        end
        // upd8 the prev edge state
        prevedge <= lfsroutput;
    end
end


assign risingedge = risingedge_r;
assign fallingedge = fallingedge_r;

endmodule

`default_nettype none

module exictatorysynapses( 
    input [0:0] clk,
    input [0:0] reset_i,

    //the output of the edgedetector that were excitatory will be the inputs
    input [0:0] edgedetectoroutput,
    
    //output will return a excited pulse that we will use in the downstream circuitry
    output [0:0] excitedpulse

);


reg [0:0] excitedpulse_r; 

// only shows excited pulses if the edge detector output was high 
always @(posedge clk)
    if(reset_i) begin
        excitedpulse_r <= 1'b0;
    end else if (edgedetectoroutput) begin
        excitedpulse_r <= 1'b1;
    end else begin
        excitedpulse_r <= 1'b0;
    end

assign excitedpulse = excitedpulse_r;

endmodule

`default_nettype none

module inhibatorysynapses( 
    input [0:0] clk,
    input [0:0] reset_i,
    
    //the output of the edgedetector that were inhibitory will be the inputs
    input [0:0] edgedetectoroutput,
    
    //output will return a inhibitory signal that we will use in the downstream circuitry
    output [0:0] inhibitorysignal
    
);

reg [0:0] inhibitorysignal_r;

// only shows inhibitory signals if the 
always @(posedge clk)
    if(reset_i) begin
        inhibitorysignal_r <= 1'b0;
    end else if (edgedetectoroutput) begin
        inhibitorysignal_r <= 1'b1;
    end else begin
        inhibitorysignal_r <= 1'b0;
    end

assign inhibitorysignal = inhibitorysignal_r;
endmodule

`default_nettype none

module feedback (
    input wire ogfeedback, // < xor feedback
    input wire excitedpulse, // < 1
    input wire inhibitorysignal, // < 0
    output wire feedbackselected //mod signal that gets passed into lfsr 
);

//reg [0:0] feedbackselected_r;
// takes og feedback generated by lfsr and allows the synapses to modify it 
// 
assign feedbackselected = (ogfeedback | excitedpulse) & ~inhibitorysignal;

//assign feedbackselected = feedbackselected_r;


//if both synapses are inactive (no excitation or inhibition), selected_feedback will just equal original_feedback, maintaining the LFSR’s usual behavior.
//if excitatory pulse is active, it will make the feedback more likely to be 1, pushing the LFSR to toggle its state more actively.
//if inhibitory signal is active, it will force the feedback to 0, which suppresses the feedback and dampens the LFSR's toggle.

endmodule


`default_nettype none

module lfsr( 
    input [0:0] clk, 
    input [0:0] en_i,
    input [0:0] reset_i,
    input  [0:0] feedback, // feedback calculations will be done in top mod
    input [7:0] seed, 
    //input [7:0] d_i, // input bits
    output [7:0] q_o
);


//parameter[7:0] seed = 8'b00000001;
wire[7:0] d_i ; 
assign d_i[0] = feedback;
assign d_i[7:1] = q_r[6:0];

reg [7:0] q_r;

// always @(posedge clk) begin
//     if (reset_i) begin
//         q_r <= seed;
//     end else if (en_i) begin
//         q_r <= {q_r[6:0], feedback};
//     end
// end



dff dff0(.seed(seed[0]), .clk(clk) , .d_in(d_i[0]) , .en_i(en_i) , .reset_i(reset_i), .q_o(q_r[0]));
dff dff1(.seed(seed[1]), .clk(clk) , .d_in(d_i[1]) , .en_i(en_i) , .reset_i(reset_i), .q_o(q_r[1]));
dff dff2(.seed(seed[2]), .clk(clk) , .d_in(d_i[2]) , .en_i(en_i) , .reset_i(reset_i), .q_o(q_r[2]));
dff dff3(.seed(seed[3]), .clk(clk) , .d_in(d_i[3]) , .en_i(en_i) , .reset_i(reset_i), .q_o(q_r[3]));
dff dff4(.seed(seed[4]), .clk(clk) , .d_in(d_i[4]) , .en_i(en_i) , .reset_i(reset_i), .q_o(q_r[4]));
dff dff5(.seed(seed[5]), .clk(clk) , .d_in(d_i[5]) , .en_i(en_i) , .reset_i(reset_i), .q_o(q_r[5]));
dff dff6(.seed(seed[6]), .clk(clk) , .d_in(d_i[6]) , .en_i(en_i) , .reset_i(reset_i), .q_o(q_r[6]));
dff dff7(.seed(seed[7]), .clk(clk) , .d_in(d_i[7]) , .en_i(en_i) , .reset_i(reset_i), .q_o(q_r[7]));


assign q_o = q_r; 

endmodule

Reference solution:
rtl/generated.v: 
//internal reg
reg [0:0] q_r;



always @(posedge clk) begin
    if (reset_i) begin
        q_r <= seed;  // feed the seed into it 
    end else if (en_i) begin // can also just switch it to a basic else instead of en_i 
        q_r <= d_in;
    end
end




assign q_o = q_r;