You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2025 Daniel Theunissen
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_led_matrix_driver (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

  // I/O Pins

  // Assign unused pins to 0
  assign uio_out = 0;
  assign uio_oe = 0;
  assign uo_out[7:5] = 0;

  // SCK
  wire SCK;
  assign SCK = ui_in[0];

  // SDI
  wire SDI;
  assign SDI = ui_in[1];

  // CS
  wire CS;
  assign CS = ui_in[2];

  // RESET
  wire RESET;
  assign RESET = rst_n;

  // CLK
  wire CLK;
  assign CLK = clk;

  // DIN
  wire DIN;
  assign uo_out[0] = DIN;

  // LED1
  wire LED1;
  assign uo_out[1] = LED1;

  // LED2
  wire LED2;
  assign uo_out[2] = LED2;

  wire [1:0] status;
  assign uo_out[4:3] = status;

  serial_matrix_driver driver (
      .CLK(CLK),
      .RESET(RESET),
      .SCK(SCK),
      .SDI(SDI),
      .CS(CS),
      .DIN(DIN),
      .LED1(LED1),
      .LED2(LED2),
      .status(status)
  );

endmodule


// Cause yosys to throw an error when we implicitly declare nets
`default_nettype none

// Simulation timestep
// `timescale 1ns / 10ps

module serial_matrix_driver (
    input CLK,
    input RESET,
    input SCK,
    input SDI,
    input CS,
    output DIN,
    output LED1,
    output LED2,
    output [1:0] status
);

  assign LED2 = !CS;

  wire [23:0] shift_register_data;
  wire latch_en;

  spi spi (
      .sck(SCK),
      .clk(CLK),
      .sdi(SDI),
      .cs(CS),
      .received_data(shift_register_data),
      .pixel_received(latch_en)
  );

  always @(posedge CLK) begin
    if (latch_en & ready) begin
      pixel_data <= shift_register_data;
    end
  end

  reg [23:0] pixel_data;
  wire ready;

  assign LED1 = ready;

  wire new_pixel_en;
  assign new_pixel_en = latch_en & !CS;

  led_driver led_driver (
      .clk(CLK),
      .reset_n(RESET),
      .data(pixel_data),
      .new_pixel(new_pixel_en),
      .ready(ready),
      .din(DIN),
      .status(status)
  );


endmodule



// Cause yosys to throw an error when we implicitly declare nets
`default_nettype none

// Simulation timestep
// `timescale 1ns / 10ps

module spi (
    input sck,
    input clk,
    input sdi,
    input cs,
    output reg [23:0] received_data,
    output reg pixel_received
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule





// Cause yosys to throw an error when we implicitly declare nets
`default_nettype none

// Simulation timestep
// `timescale 1ns / 10ps

module led_driver (
    input clk,
    input reset_n,
    input [23:0] data,
    input new_pixel,
    output reg din,
    output reg ready,
    output [1:0] status
);

  // assign new_pixel = BTN2;
  // Define timing parameters according to WS2812B datasheet
  localparam T0H = 400e-9;  // width of '0' high pulse (400ns)
  localparam T1H = 800e-9;  // width of '1' high pulse (800ns)
  localparam T0L = 850e-9;  // width of '0' low pulse (850ns)
  localparam T1L = 450e-9;  // width of '1' low pulse (450ns)
  localparam PERIOD = 1250e-9;  // total period of one bit (1250ns)
  localparam RES_DELAY = 300e-6;  // reset duration (300us)

  // Calculate clock cycles needed based on input clock frequency
  parameter CLOCK_FREQ = 12e6;  // 12MHz clock frequency

  // Calculate clock cycles for each timing parameter
  localparam [15:0] CYCLES_PERIOD = $floor(CLOCK_FREQ * PERIOD);
  localparam [15:0] CYCLES_T0H = $floor(CLOCK_FREQ * T0H);
  localparam [15:0] CYCLES_T1H = $floor(CLOCK_FREQ * T1H);
  localparam [15:0] CYCLES_T0L = CYCLES_PERIOD - CYCLES_T0H;
  localparam [15:0] CYCLES_T1L = CYCLES_PERIOD - CYCLES_T1H;
  localparam [15:0] CYCLES_RESET = $floor(CLOCK_FREQ * RES_DELAY);

  // state machine
  parameter RST = 0, READY = 1, SENDING = 2;
  reg [1:0] state;
  assign status = state;
  reg [ 4:0] bit_index;
  reg [15:0] time_counter = 0;

  always @(posedge clk, negedge reset_n) begin
    if (!reset_n) begin
      state <= RST;
      time_counter <= 0;
      din <= 0;
      ready <= 0;
      bit_index <= 0;
    end else begin
      case (state)
        RST: begin
          if (time_counter < CYCLES_RESET - 1) begin
            time_counter <= time_counter + 1;
          end else begin
            state <= READY;
          end
        end

        READY: begin
          if (new_pixel) begin
            state <= SENDING;
            din <= 1;
            bit_index <= 0;
            time_counter <= 0;
          end else begin
            din   <= 0;
            ready <= 1;
          end
        end

        SENDING: begin
          if (time_counter < CYCLES_PERIOD - 1) begin
            ready <= 0;
            time_counter <= time_counter + 1;
            if (time_counter < (data[5'd23-bit_index] ? CYCLES_T1H : CYCLES_T0H)) begin
              din <= 1;
            end else begin
              din <= 0;
            end
          end else if (bit_index < 5'd23) begin
            time_counter <= 0;
            bit_index <= bit_index + 1;
          end else begin
            state <= READY;
          end
        end

        default: begin
          state <= RST;
        end
      endcase
    end
  end

endmodule



Reference solution:
rtl/generated.v: 
  // Oversampling everything to take it into the FPGA/ASIC clock domain
  reg [2:0] sck_reg;
  reg [2:0] cs_reg;
  reg [1:0] sdi_reg;

  always @(posedge clk) begin
    sck_reg <= {sck_reg[1:0], sck};
    cs_reg  <= {cs_reg[1:0], cs};
    sdi_reg <= {sdi_reg[0], sdi};
  end

  wire sck_rising_edge = (sck_reg[2:1] == 2'b01);
  wire cs_active = !cs_reg[1];
  wire sdi_data = sdi_reg[1];

  // Receive 24 bits
  reg [4:0] bit_count;

  always @(posedge clk) begin
    if (!cs_active) begin
      bit_count <= 5'b00000;
    end else if (sck_rising_edge) begin  // Sample SDI on rising edge
      bit_count <= bit_count + 5'b00001;
      received_data <= {received_data[22:0], sdi_data};
      if (bit_count == 5'b10111) begin
        bit_count <= 0;
      end
    end
  end

  always @(posedge clk) begin
    pixel_received <= cs_active && sck_rising_edge && (bit_count == 5'b10111);
  end