You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Your Name
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_lif1 (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

  // All output pins must be assigned. If not used, assign to 0.
  //assign ui_in [6:0] = 0;
  //assign uio_in [6:0] = 0;
  assign uio_out = 0;
  assign uio_oe  = 0;

  // List all unused inputs to prevent warnings
  wire _unused = &{ena, ui_in[6:0], uio_in[6:0], 1'b0};
  stdp stdp (.pre_spike(ui_in[7]), .post_spike(uio_in[7]), .clk(clk), .reset(rst_n), .weight(uo_out));

endmodule


`default_nettype none
module stdp (
    input wire clk,
    input wire reset,
    input wire pre_spike,
    input wire post_spike,
    output reg [7:0] weight
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




Reference solution:
rtl/generated.v: 
parameter [15:0] B_POTENTIATION = 16'b0000101000000000; // can change
parameter [15:0] B_DEPRESSION = 16'b0000001010000000;   // can change
parameter [7:0] WEIGHT_MAX = 8'b11111111;
parameter [7:0] WEIGHT_MIN = 8'b00000000;

reg [15:0] trace_u;
reg signed [15:0] delta_t;
reg pre_spike_detected;
reg post_spike_detected;


always @(posedge clk) begin
    if (reset) begin
        pre_spike_detected <= 0;
        post_spike_detected <= 0;
        delta_t <= 0;
        trace_u <= 16'b0;
        weight <= 8'b10000000; // can change
    end else begin
        // Update pre_spike_detected and post_spike_detected
        if (pre_spike) begin
            if (!pre_spike_detected && !post_spike_detected) begin
                pre_spike_detected <= 1;
                delta_t <= delta_t + 1;
            end else if (post_spike_detected) begin
                pre_spike_detected <= 1;
                delta_t <= delta_t-1;
            end
        end

        if (post_spike) begin
            if (!post_spike_detected && !pre_spike_detected) begin
                post_spike_detected <= 1;
                delta_t <= delta_t - 1;
            end else if (pre_spike_detected) begin
                post_spike_detected <= 1;
                delta_t <= delta_t + 1;
            end
        end

        //if (!pre_spike_detected || !post_spike_detected) begin
        //delta_t <= delta_t + 1;
        //end
        // Update trace_u
        if (pre_spike_detected && !post_spike_detected) begin  
            trace_u <= ((B_POTENTIATION * trace_u) >> 8) + 16'b0000100000000000;
        end else if (!pre_spike_detected && post_spike_detected) begin  
            trace_u <= ((B_DEPRESSION * trace_u) >> 8) - 16'b0000100000000000;
        end

        // Update weight
        if (pre_spike_detected && post_spike_detected) begin
            if (delta_t > 0) begin
                if ((weight + (trace_u >> 8)) > WEIGHT_MAX) begin
                    weight <= WEIGHT_MAX;
                end else begin
                    weight <= weight + (trace_u >> 8);
                end
            end else if (delta_t < 0) begin
                if ((weight + (trace_u >> 8)) < WEIGHT_MIN) begin
                    weight <= WEIGHT_MIN;
                end else begin
                    weight <= weight + (trace_u >> 8);
                end
            end
            delta_t <= 0;  
            trace_u <= 0;
            pre_spike_detected <= 0;
            post_spike_detected <= 0;
        end
    end
end