You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

`default_nettype	none
module tt_um_rkarl_Spiral(
  input  wire [7:0] ui_in,    // Dedicated inputs
  output wire [7:0] uo_out,   // Dedicated outputs
  input  wire [7:0] uio_in,   // IOs: Input path
  output wire [7:0] uio_out,  // IOs: Output path
  output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
  input  wire       ena,      // always 1 when the design is powered, so you can ignore it
  input  wire       clk,      // clock
  input  wire       rst_n     // reset_n - low to reset
);
  assign uio_out = 0;
  assign uio_oe  = 0;
  wire _unused = &{ena, clk, rst_n, 1'b0,uio_in};


  wire hsync;
  wire vsync;
  wire [1:0] R;
  wire [1:0] G;
  wire [1:0] B;
  wire video_active;
  wire [9:0] pix_x;
  wire [9:0] pix_y;
  
  wire [1:0] speed = {ui_in[0],~ui_in[1]};//Make the default 2
  wire [2:0] background = ui_in[4:2];
  wire [2:0] foreGround = ui_in[7:5];
  hvsync_generator hvsync_gen(
    .clk(clk),
    .reset(~rst_n),
    .hsync(hsync),
    .vsync(vsync),
    .display_on(video_active),
    .hpos(pix_x),
    .vpos(pix_y)
  );
  
  wire signed [9:0] normilizedX = (pix_x -323);
  wire signed [9:0] normilizedY = (pix_y -243);
  wire [3:0] angle;
  reg [4:0] angleOffset;
  wire [3:0] adjustedAngle = angle + angleOffset[4:1];

  always @(posedge vsync)
	begin
		angleOffset <= angleOffset+{3'b000,speed};
	end 
  
  topolar cordicAlg(
  .i_clk(clk),
  .i_reset(~rst_n),
  .i_ce(1'b1),
  .i_xval(normilizedX[9:3]),
  .i_yval(normilizedY[9:3]),
  .o_phase(angle)
  );
  
  assign uo_out = {hsync, B[0], G[0], R[0], vsync, B[1], G[1], R[1]};

  wire [3:0] r;
  
  hypCal hypotenuse(.x_pos(normilizedX),
							.y_pos(normilizedY),
							.clk(clk),
							.rst(~rst_n),
							.r_sqroot(r)
							);

	assign R = video_active ? ((r[3:0] == adjustedAngle[3:0])? {~foreGround[0],~foreGround[0]} : {background[0],background[0]}) : 2'b00;
	assign G = video_active ? ((r[3:0] == adjustedAngle[3:0])? {foreGround[1],foreGround[1]} : {background[1],background[1]}) : 2'b00;
	assign B = video_active ? ((r[3:0] == adjustedAngle[3:0])? {foreGround[2],foreGround[2]} : {background[2],background[2]}) : 2'b00;




endmodule

`default_nettype none
module hypCal (
	input wire [9:0] x_pos,
	input wire [9:0] y_pos,
	input wire clk, rst,
	output reg [3:0] r_sqroot
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




module hvsync_generator(clk, reset, hsync, vsync, display_on, hpos, vpos);
    input clk;
    input reset;
    output reg hsync, vsync;
    output display_on;
    output reg [9:0] hpos;
    output reg [9:0] vpos;

    // declarations for TV-simulator sync parameters
    // horizontal constants
    parameter H_DISPLAY       = 640; // horizontal display width
    parameter H_BACK          =  48; // horizontal left border (back porch)
    parameter H_FRONT         =  16; // horizontal right border (front porch)
    parameter H_SYNC          =  96; // horizontal sync width
    // vertical constants
    parameter V_DISPLAY       = 480; // vertical display height
    parameter V_TOP           =  33; // vertical top border
    parameter V_BOTTOM        =  10; // vertical bottom border
    parameter V_SYNC          =   2; // vertical sync # lines
    // derived constants
    parameter H_SYNC_START    = H_DISPLAY + H_FRONT;
    parameter H_SYNC_END      = H_DISPLAY + H_FRONT + H_SYNC - 1;
    parameter H_MAX           = H_DISPLAY + H_BACK + H_FRONT + H_SYNC - 1;
    parameter V_SYNC_START    = V_DISPLAY + V_BOTTOM;
    parameter V_SYNC_END      = V_DISPLAY + V_BOTTOM + V_SYNC - 1;
    parameter V_MAX           = V_DISPLAY + V_TOP + V_BOTTOM + V_SYNC - 1;

    wire hmaxxed = (hpos == H_MAX) || reset;  // set when hpos is maximum
    wire vmaxxed = (vpos == V_MAX) || reset;  // set when vpos is maximum
    
    // horizontal position counter
    always @(posedge clk)
    begin
      hsync <= (hpos>=H_SYNC_START && hpos<=H_SYNC_END);
      if(hmaxxed)
        hpos <= 0;
      else
        hpos <= hpos + 1;
    end

    // vertical position counter
    always @(posedge clk)
    begin
      vsync <= (vpos>=V_SYNC_START && vpos<=V_SYNC_END);
      if(hmaxxed)
        if (vmaxxed)
          vpos <= 0;
        else
          vpos <= vpos + 1;
    end
    
    // display_on is set when beam is in "safe" visible frame
    assign display_on = (hpos<H_DISPLAY) && (vpos<V_DISPLAY);
endmodule



`default_nettype	none
//
module	topolar(i_clk, i_reset, i_ce, i_xval, i_yval,
		o_phase);
	localparam	IW=7,	// The number of bits in our inputs
			OW=4,// The number of output bits to produce
			NSTAGES=3,
			WW=7,	// Our working bit-width
			PW=4;	// Bits in our phase variables
	input					i_clk, i_reset, i_ce;
	input	wire	signed	[(IW-1):0]	i_xval, i_yval;
	output	reg		[(OW-1):0]	o_phase;

	wire	signed [(WW-1):0]	e_xval, e_yval;
	assign	e_xval = i_xval;
	assign	e_yval = i_yval;

	// Declare variables for all of the separate stages
	reg	signed	[(WW-1):0]	xv	[0:NSTAGES];
	reg	signed	[(WW-1):0]	yv	[0:NSTAGES];
	reg		[(PW-1):0]	ph	[0:NSTAGES];



	// First stage, map to within +/- 45 degrees
	always @(posedge i_clk)
	if (i_reset)
	begin
		xv[0] <= 0;
		yv[0] <= 0;
		ph[0] <= 0;
	end else if (i_ce)
		case({i_xval[IW-1], i_yval[IW-1]})
		2'b01: begin // Rotate by -315 degrees
			xv[0] <=  e_xval - e_yval;
			yv[0] <=  e_xval + e_yval;
//			ph[0] <= 19'h70000 >> (19-PW-1);
			ph[0] <= 4'hC;
			end
		2'b10: begin // Rotate by -135 degrees
			xv[0] <= -e_xval + e_yval;
			yv[0] <= -e_xval - e_yval;
//			ph[0] <= 19'h30000 >> (19-PW-1);
			ph[0] <= 4'hC;
			end
		2'b11: begin // Rotate by -225 degrees
			xv[0] <= -e_xval - e_yval;
			yv[0] <=  e_xval - e_yval;
//			ph[0] <= 19'h50000>> (19-PW-1);
			ph[0] <= 4'h4;
			end
		default: begin // Rotate by -45 degrees
			xv[0] <=  e_xval + e_yval;
			yv[0] <= -e_xval + e_yval;
//			ph[0] <= 19'h10000>> (19-PW-1);
			ph[0] <= 4'h4;
			end
		endcase
	wire	[(PW-1):0]	cordic_angle [0:(NSTAGES-1)];
//	assign	cordic_angle[ 0] = 19'h0_9720>> (19-PW-1); //  26.565051 deg
//	assign	cordic_angle[ 1] = 19'h0_4fd9>> (19-PW-1); //  14.036243 deg
//	assign	cordic_angle[ 2] = 19'h0_2888>> (19-PW-1); //   7.125016 deg

	assign	cordic_angle[ 0] = 4'h2; //  26.565051 deg
	assign	cordic_angle[ 1] = 4'h1; //  14.036243 deg
	assign	cordic_angle[ 2] = 4'h0; //   7.125016 deg
	
	genvar	i;
	generate for(i=0; i<NSTAGES; i=i+1) begin : TOPOLARloop
		always @(posedge i_clk)
		// Here's where we are going to put the actual CORDIC
		// rectangular to polar loop.  Everything up to this
		// point has simply been necessary preliminaries.
		if (i_reset)
		begin
			xv[i+1] <= 0;
			yv[i+1] <= 0;
			ph[i+1] <= 0;
		end else if (i_ce)
		begin
			if ((cordic_angle[i] == 0)||(i >= WW))
			begin // Do nothing but move our vector
			// forward one stage, since we have more
			// stages than valid data
				xv[i+1] <= xv[i];
				yv[i+1] <= yv[i];
				ph[i+1] <= ph[i];
			end else if (yv[i][(WW-1)]) // Below the axis
			begin
				// If the vector is below the x-axis, rotate by
				// the CORDIC angle in a positive direction.
				xv[i+1] <= xv[i] - (yv[i]>>>(i+1));
				yv[i+1] <= yv[i] + (xv[i]>>>(i+1));
				ph[i+1] <= ph[i] - cordic_angle[i];
			end else begin
				// On the other hand, if the vector is above the
				// x-axis, then rotate in the other direction
				xv[i+1] <= xv[i] + (yv[i]>>>(i+1));
				yv[i+1] <= yv[i] - (xv[i]>>>(i+1));
				ph[i+1] <= ph[i] + cordic_angle[i];
			end
		end
	end endgenerate

always @(posedge i_clk)
	if (i_reset)
	begin
		o_phase <= 0;
	end else if (i_ce)
	begin
		o_phase <= ph[NSTAGES][(PW-1):(PW-OW)];
	end

endmodule

Reference solution:
rtl/generated.v: wire [12:0] xy_pos;
wire _unused = &{x_pos[1:0],y_pos[1:0]};

wire  [6:0] norm_x = (x_pos[9] == 1'b0) ? x_pos[8:2] : ~(x_pos[8:2]);
wire  [6:0] norm_y = (y_pos[9] == 1'b0) ? y_pos[8:2] : ~(y_pos[8:2]);

reg [6:0]mutlReg;
reg stateCheck;
wire [12:0]multSignal = mutlReg*mutlReg;
reg[12:0] multX, multY;
always @(posedge clk) begin
	if (rst) begin
		mutlReg <= 7'h00;
		stateCheck <= 'b0;
	end else begin
		if (stateCheck == 'b0) begin
			multY <=multSignal;
			mutlReg <= norm_x;
			stateCheck <= 'b1;
		end else begin
			multX <=multSignal;
			mutlReg <= norm_y;
			stateCheck <= 'b0;
		end
	end
end
		

//assign xy_pos = (norm_y[8:2]*norm_y[8:2] + norm_x[8:2]*norm_x[8:2]) >> 6;
assign xy_pos = (multX + multY) >> 6;
always @(xy_pos) begin
	case(xy_pos)
		'h00 : r_sqroot <= 'h0;
		'h01 : r_sqroot <= 'h3;
		'h02 : r_sqroot <= 'h5;
		'h03 : r_sqroot <= 'h6;
		'h04 : r_sqroot <= 'h7;
		'h05 : r_sqroot <= 'h8;
		'h06 : r_sqroot <= 'h8;
		'h07 : r_sqroot <= 'h9;
		'h08 : r_sqroot <= 'ha;
		'h09 : r_sqroot <= 'ha;
		'h0a : r_sqroot <= 'hb;
		'h0b : r_sqroot <= 'hc;
		'h0c : r_sqroot <= 'hc;
		'h0d : r_sqroot <= 'hd;
		'h0e : r_sqroot <= 'hd;
		'h0f : r_sqroot <= 'he;
		'h10 : r_sqroot <= 'he;
		'h11 : r_sqroot <= 'he;
		'h12 : r_sqroot <= 'hf;
		'h13 : r_sqroot <= 'hf;
		'h14 : r_sqroot <= 'h0;
		'h15 : r_sqroot <= 'h0;
		'h16 : r_sqroot <= 'h0;
		'h17 : r_sqroot <= 'h1;
		'h18 : r_sqroot <= 'h1;
		'h19 : r_sqroot <= 'h2;
		'h1a : r_sqroot <= 'h2;
		'h1b : r_sqroot <= 'h2;
		'h1c : r_sqroot <= 'h3;
		'h1d : r_sqroot <= 'h3;
		'h1e : r_sqroot <= 'h3;
		'h1f : r_sqroot <= 'h4;
		'h20 : r_sqroot <= 'h4;
		'h21 : r_sqroot <= 'h4;
		'h22 : r_sqroot <= 'h5;
		'h23 : r_sqroot <= 'h5;
		'h24 : r_sqroot <= 'h5;
		'h25 : r_sqroot <= 'h6;
		'h26 : r_sqroot <= 'h6;
		'h27 : r_sqroot <= 'h6;
		'h28 : r_sqroot <= 'h6;
		'h29 : r_sqroot <= 'h7;
		'h2a : r_sqroot <= 'h7;
		'h2b : r_sqroot <= 'h7;
		'h2c : r_sqroot <= 'h8;
		'h2d : r_sqroot <= 'h8;
		'h2e : r_sqroot <= 'h8;
		'h2f : r_sqroot <= 'h8;
		'h30 : r_sqroot <= 'h9;
		'h31 : r_sqroot <= 'h9;
		'h32 : r_sqroot <= 'h9;
		'h33 : r_sqroot <= 'h9;
		'h34 : r_sqroot <= 'ha;
		'h35 : r_sqroot <= 'ha;
		'h36 : r_sqroot <= 'ha;
		'h37 : r_sqroot <= 'ha;
		'h38 : r_sqroot <= 'hb;
		'h39 : r_sqroot <= 'hb;
		'h3a : r_sqroot <= 'hb;
		'h3b : r_sqroot <= 'hb;
		'h3c : r_sqroot <= 'hc;
		'h3d : r_sqroot <= 'hc;
		'h3e : r_sqroot <= 'hc;
		'h3f : r_sqroot <= 'hc;
		'h40 : r_sqroot <= 'hc;
		'h41 : r_sqroot <= 'hd;
		'h42 : r_sqroot <= 'hd;
		'h43 : r_sqroot <= 'hd;
		'h44 : r_sqroot <= 'hd;
		'h45 : r_sqroot <= 'he;
		'h46 : r_sqroot <= 'he;
		'h47 : r_sqroot <= 'he;
		'h48 : r_sqroot <= 'he;
		'h49 : r_sqroot <= 'he;
		'h4a : r_sqroot <= 'hf;
		'h4b : r_sqroot <= 'hf;
		'h4c : r_sqroot <= 'hf;
		'h4d : r_sqroot <= 'hf;
		'h4e : r_sqroot <= 'hf;
		'h4f : r_sqroot <= 'h0;
		'h50 : r_sqroot <= 'h0;
		'h51 : r_sqroot <= 'h0;
		'h52 : r_sqroot <= 'h0;
		'h53 : r_sqroot <= 'h0;
		'h54 : r_sqroot <= 'h1;
		'h55 : r_sqroot <= 'h1;
		'h56 : r_sqroot <= 'h1;
		'h57 : r_sqroot <= 'h1;
		'h58 : r_sqroot <= 'h1;
		'h59 : r_sqroot <= 'h2;
		'h5a : r_sqroot <= 'h2;
		'h5b : r_sqroot <= 'h2;
		'h5c : r_sqroot <= 'h2;
		'h5d : r_sqroot <= 'h2;
		'h5e : r_sqroot <= 'h3;
		'h5f : r_sqroot <= 'h3;
		'h60 : r_sqroot <= 'h3;
		'h61 : r_sqroot <= 'h3;
		'h62 : r_sqroot <= 'h3;
		'h63 : r_sqroot <= 'h4;
		'h64 : r_sqroot <= 'h4;
		'h65 : r_sqroot <= 'h4;
		'h66 : r_sqroot <= 'h4;
		'h67 : r_sqroot <= 'h4;
		'h68 : r_sqroot <= 'h4;
		'h69 : r_sqroot <= 'h5;
		'h6a : r_sqroot <= 'h5;
		'h6b : r_sqroot <= 'h5;
		'h6c : r_sqroot <= 'h5;
		'h6d : r_sqroot <= 'h5;
		'h6e : r_sqroot <= 'h5;
		'h6f : r_sqroot <= 'h6;
		'h70 : r_sqroot <= 'h6;
		'h71 : r_sqroot <= 'h6;
		'h72 : r_sqroot <= 'h6;
		'h73 : r_sqroot <= 'h6;
		'h74 : r_sqroot <= 'h6;
		'h75 : r_sqroot <= 'h7;
		'h76 : r_sqroot <= 'h7;
		'h77 : r_sqroot <= 'h7;
		'h78 : r_sqroot <= 'h7;
		'h79 : r_sqroot <= 'h7;
		'h7a : r_sqroot <= 'h7;
		'h7b : r_sqroot <= 'h8;
		'h7c : r_sqroot <= 'h8;
		'h7d : r_sqroot <= 'h8;
		'h7e : r_sqroot <= 'h8;
		'h7f : r_sqroot <= 'h8;
		'h80 : r_sqroot <= 'h8;
		'h81 : r_sqroot <= 'h9;
		'h82 : r_sqroot <= 'h9;
		'h83 : r_sqroot <= 'h9;
		'h84 : r_sqroot <= 'h9;
		'h85 : r_sqroot <= 'h9;
		'h86 : r_sqroot <= 'h9;
		'h87 : r_sqroot <= 'ha;
		'h88 : r_sqroot <= 'ha;
		'h89 : r_sqroot <= 'ha;
		'h8a : r_sqroot <= 'ha;
		'h8b : r_sqroot <= 'ha;
		'h8c : r_sqroot <= 'ha;
		'h8d : r_sqroot <= 'ha;
		'h8e : r_sqroot <= 'hb;
		'h8f : r_sqroot <= 'hb;
		'h90 : r_sqroot <= 'hb;
		'h91 : r_sqroot <= 'hb;
		'h92 : r_sqroot <= 'hb;
		'h93 : r_sqroot <= 'hb;
		'h94 : r_sqroot <= 'hc;
		'h95 : r_sqroot <= 'hc;
		'h96 : r_sqroot <= 'hc;
		'h97 : r_sqroot <= 'hc;
		'h98 : r_sqroot <= 'hc;
		'h99 : r_sqroot <= 'hc;
		'h9a : r_sqroot <= 'hc;
		'h9b : r_sqroot <= 'hd;
		'h9c : r_sqroot <= 'hd;
		'h9d : r_sqroot <= 'hd;
		'h9e : r_sqroot <= 'hd;
		'h9f : r_sqroot <= 'hd;
		'ha0 : r_sqroot <= 'hd;
		'ha1 : r_sqroot <= 'hd;
		'ha2 : r_sqroot <= 'he;
		'ha3 : r_sqroot <= 'he;
		'ha4 : r_sqroot <= 'he;
		'ha5 : r_sqroot <= 'he;
		'ha6 : r_sqroot <= 'he;
		'ha7 : r_sqroot <= 'he;
		'ha8 : r_sqroot <= 'he;
		'ha9 : r_sqroot <= 'hf;
		'haa : r_sqroot <= 'hf;
		'hab : r_sqroot <= 'hf;
		'hac : r_sqroot <= 'hf;
		'had : r_sqroot <= 'hf;
		'hae : r_sqroot <= 'hf;
		'haf : r_sqroot <= 'hf;
		'hb0 : r_sqroot <= 'h0;
		'hb1 : r_sqroot <= 'h0;
		'hb2 : r_sqroot <= 'h0;
		'hb3 : r_sqroot <= 'h0;
		'hb4 : r_sqroot <= 'h0;
		'hb5 : r_sqroot <= 'h0;
		'hb6 : r_sqroot <= 'h0;
		'hb7 : r_sqroot <= 'h0;
		'hb8 : r_sqroot <= 'h1;
		'hb9 : r_sqroot <= 'h1;
		'hba : r_sqroot <= 'h1;
		'hbb : r_sqroot <= 'h1;
		'hbc : r_sqroot <= 'h1;
		'hbd : r_sqroot <= 'h1;
		'hbe : r_sqroot <= 'h1;
		'hbf : r_sqroot <= 'h2;
		'hc0 : r_sqroot <= 'h2;
		'hc1 : r_sqroot <= 'h2;
		'hc2 : r_sqroot <= 'h2;
		'hc3 : r_sqroot <= 'h2;
		'hc4 : r_sqroot <= 'h2;
		'hc5 : r_sqroot <= 'h2;
		'hc6 : r_sqroot <= 'h2;
		'hc7 : r_sqroot <= 'h3;
		'hc8 : r_sqroot <= 'h3;
		'hc9 : r_sqroot <= 'h3;
		'hca : r_sqroot <= 'h3;
		'hcb : r_sqroot <= 'h3;
		'hcc : r_sqroot <= 'h3;
		'hcd : r_sqroot <= 'h3;
		'hce : r_sqroot <= 'h3;
		'hcf : r_sqroot <= 'h4;
		'hd0 : r_sqroot <= 'h4;
		'hd1 : r_sqroot <= 'h4;
		'hd2 : r_sqroot <= 'h4;
		'hd3 : r_sqroot <= 'h4;
		'hd4 : r_sqroot <= 'h4;
		'hd5 : r_sqroot <= 'h4;
		'hd6 : r_sqroot <= 'h4;
		'hd7 : r_sqroot <= 'h5;
		'hd8 : r_sqroot <= 'h5;
		'hd9 : r_sqroot <= 'h5;
		'hda : r_sqroot <= 'h5;
		'hdb : r_sqroot <= 'h5;
		'hdc : r_sqroot <= 'h5;
		'hdd : r_sqroot <= 'h5;
		'hde : r_sqroot <= 'h5;
		'hdf : r_sqroot <= 'h6;
		'he0 : r_sqroot <= 'h6;
		'he1 : r_sqroot <= 'h6;
		'he2 : r_sqroot <= 'h6;
		'he3 : r_sqroot <= 'h6;
		'he4 : r_sqroot <= 'h6;
		'he5 : r_sqroot <= 'h6;
		'he6 : r_sqroot <= 'h6;
		'he7 : r_sqroot <= 'h7;
		'he8 : r_sqroot <= 'h7;
		'he9 : r_sqroot <= 'h7;
		'hea : r_sqroot <= 'h7;
		'heb : r_sqroot <= 'h7;
		'hec : r_sqroot <= 'h7;
		'hed : r_sqroot <= 'h7;
		'hee : r_sqroot <= 'h7;
		'hef : r_sqroot <= 'h7;
		'hf0 : r_sqroot <= 'h8;
		'hf1 : r_sqroot <= 'h8;
		'hf2 : r_sqroot <= 'h8;
		'hf3 : r_sqroot <= 'h8;
		'hf4 : r_sqroot <= 'h8;
		'hf5 : r_sqroot <= 'h8;
		'hf6 : r_sqroot <= 'h8;
		'hf7 : r_sqroot <= 'h8;
		'hf8 : r_sqroot <= 'h9;
		'hf9 : r_sqroot <= 'h9;
		'hfa : r_sqroot <= 'h9;
		'hfb : r_sqroot <= 'h9;
		'hfc : r_sqroot <= 'h9;
		'hfd : r_sqroot <= 'h9;
		'hfe : r_sqroot <= 'h9;
		'hff : r_sqroot <= 'h9;
		'h100 : r_sqroot <= 'h9;
		'h101 : r_sqroot <= 'ha;
		'h102 : r_sqroot <= 'ha;
		'h103 : r_sqroot <= 'ha;
		'h104 : r_sqroot <= 'ha;
		'h105 : r_sqroot <= 'ha;
		'h106 : r_sqroot <= 'ha;
		'h107 : r_sqroot <= 'ha;
		'h108 : r_sqroot <= 'ha;
		'h109 : r_sqroot <= 'ha;
		'h10a : r_sqroot <= 'hb;
		'h10b : r_sqroot <= 'hb;
		'h10c : r_sqroot <= 'hb;
		'h10d : r_sqroot <= 'hb;
		'h10e : r_sqroot <= 'hb;
		'h10f : r_sqroot <= 'hb;
		'h110 : r_sqroot <= 'hb;
		'h111 : r_sqroot <= 'hb;
		'h112 : r_sqroot <= 'hb;
		'h113 : r_sqroot <= 'hc;
		'h114 : r_sqroot <= 'hc;
		'h115 : r_sqroot <= 'hc;
		'h116 : r_sqroot <= 'hc;
		'h117 : r_sqroot <= 'hc;
		'h118 : r_sqroot <= 'hc;
		'h119 : r_sqroot <= 'hc;
		'h11a : r_sqroot <= 'hc;
		'h11b : r_sqroot <= 'hc;
		'h11c : r_sqroot <= 'hd;
		'h11d : r_sqroot <= 'hd;
		'h11e : r_sqroot <= 'hd;
		'h11f : r_sqroot <= 'hd;
		'h120 : r_sqroot <= 'hd;
		'h121 : r_sqroot <= 'hd;
		'h122 : r_sqroot <= 'hd;
		'h123 : r_sqroot <= 'hd;
		'h124 : r_sqroot <= 'hd;
		'h125 : r_sqroot <= 'hd;
		'h126 : r_sqroot <= 'he;
		'h127 : r_sqroot <= 'he;
		'h128 : r_sqroot <= 'he;
		'h129 : r_sqroot <= 'he;
		'h12a : r_sqroot <= 'he;
		'h12b : r_sqroot <= 'he;
		'h12c : r_sqroot <= 'he;
		'h12d : r_sqroot <= 'he;
		'h12e : r_sqroot <= 'he;
		'h12f : r_sqroot <= 'hf;
		'h130 : r_sqroot <= 'hf;
		'h131 : r_sqroot <= 'hf;
		'h132 : r_sqroot <= 'hf;
		'h133 : r_sqroot <= 'hf;
		'h134 : r_sqroot <= 'hf;
		'h135 : r_sqroot <= 'hf;
		'h136 : r_sqroot <= 'hf;
		'h137 : r_sqroot <= 'hf;
		'h138 : r_sqroot <= 'hf;
		default: r_sqroot <= 'h0;
	endcase
end