You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Pietro Paolo Scimia
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_Scimia_oscillator_tester (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

  // All output pins must be assigned. If not used, assign to 0.
  
  wire rst;
  assign rst = ~rst_n;
  assign uio_oe = 8'b0000_0001;
  assign uio_out[7:1] = 7'b0000_000;
  
  oscillator_tester oscillator_tester (
    .osc(ui_in[0]), 			// input signal to be checked
    .clk(clk),				// system clock
    .rst(rst),				// system reset (active high)
    .measure(uo_out),			// frequency data out
    .data_valid(uio_out[0])		// data valid signal
);

  // List all unused inputs to prevent warnings
  wire _unused = &{ena, ui_in[7:1], uio_in, 1'b0};

endmodule



//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 21.06.2025 11:06:25
// Design Name: 
// Module Name: counter_1k_cycles
// Project Name: oscillator_tester
// Target Devices: 
// Tool Versions: 
// Description: 10 bit counter for oscillator tester. Aim of the module is conversion from Hz to kHz. 
//              Threshold is set to 999, where the output signal incr goes high.
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module counter_1k_cycles (
    input wire clk,
    input wire rst,
    input wire start,
    output reg incr
);

reg [9:0] count;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        count <= 10'd0;
    end else if (start) begin
        if (count < 10'd999) begin
            count <= count + 1;
        end else begin
            count <= 10'd0;
        end
    end
end

always @(*) begin
    if (count == 10'd999)
        incr = 1'b1;
    else
        incr = 1'b0;
     
end

endmodule



//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 21.06.2025 10:51:09
// Design Name: 
// Module Name: counter_8bit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 8 bit counter for oscillator tester. Input clk from output of 1kHz-counter. Final value correspond to frequency measured.
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module counter_8bit (
    input wire clk,
    input wire rst,
    output reg [7:0] count
);

always @(posedge clk or posedge rst) begin
    if (rst) begin
        count <= 8'b00000000;
    end else begin
        count <= count + 1;
    end
end

endmodule



// FSM for oscillator_tester. Main purpose is to define the 1s time interval of the frequency measurement. 
//Provides start, reset and output enable signals to modules.  


module FSM (
    input wire clk,
    input wire rst,
    input wire osc,
    input wire end_meas,
    output reg start_stop,
    output reg reset,
    output reg data_valid,
    output reg reg_out);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule





//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 21.06.2025 11:50:45
// Design Name: 
// Module Name: oscillator_tester
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: The circuit is designed to test any ring oscillator output frequency. 
//              Frequency range: 1-250kHz;
//              Resolution: 1kHz.
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module oscillator_tester (
    input wire osc,
    input wire clk,
    input wire rst,
    output wire [7:0] measure,
    output wire data_valid
);

wire start, reset, osc_sync, reg_out, up_count, end_meas;
wire [7:0] reg_in;

// Structural description
FSM fsm_inst (
    .osc(osc_sync),
    .rst(rst),
    .clk(clk),
    .end_meas(end_meas),
    .start_stop(start),
    .reset(reset),
    .data_valid(data_valid),
    .reg_out(reg_out)
);

Timer timer_inst (
    .clk(clk),
    .start(start),
    .rst(reset),
    .end_meas(end_meas)
);

synchronizer sync_inst (
    .clk(clk),
    .data_in(osc),
    .data_out(osc_sync)
);

counter_1k_cycles counter_1k_inst (
    .clk(osc_sync),
    .rst(reset),
    .start(start),
    .incr(up_count)
);

counter_8bit counter_8bit_inst (
    .clk(up_count),
    .rst(reset),
    .count(reg_in)
);

PIPO_8bit out_reg_inst (
    .clk(reg_out),
    .rst(reset),
    .data_in(reg_in),
    .data_out(measure)
);

endmodule



//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 21.06.2025 10:38:23
// Design Name: 
// Module Name: PIPO_8bit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: Output 8 bit PIPO register. Keeps a stable output while the measurement is running. 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PIPO_8bit (
    input wire clk,
    input wire rst,
    input wire [7:0] data_in,
    output reg [7:0] data_out
);

always @(posedge clk or posedge rst) begin
    if (rst)
        data_out <= 8'b0;   
    else
        data_out <= data_in;
end

endmodule



//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 21.06.2025 10:38:23
// Design Name: 
// Module Name: PIPO_8bit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: Two-stage FF, reducing input related instability
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module synchronizer (
    input wire clk,
    input wire data_in,
    output reg data_out
);

reg first_stage_sample;

always @(posedge clk) begin
    first_stage_sample <= data_in;
    data_out <= first_stage_sample;
end

endmodule



//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 21.06.2025 11:30:11
// Design Name: 
// Module Name: Timer
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 26 bit timer for measurement time interval definition. Thresold set to 49.999.999 cycles defines a 1s interval due a 50MHz clk. 
//              Provides a end_meas signal to FSM.
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Timer (
    input wire clk,
    input wire start,
    input wire rst,
    output reg end_meas
);

reg [25:0] tempo;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        tempo <= 26'd0;
    end else if (start) begin
        if (tempo < 26'd49999999) begin
            tempo <= tempo + 1;
        end
    end
end

always @(*) begin
    if (tempo == 26'd49999999)
        end_meas = 1'b1;
    else
        end_meas = 1'b0;
end

endmodule



Reference solution:
rtl/generated.v: 
    // State def:
 reg [1:0] state, next_state;
 
 parameter IDLE  = 2'b00, RUN   = 2'b01, WRITE = 2'b10, DATA_VALID = 2'b11;



    // State update:
    always @(posedge clk) 
     begin
     if (rst) begin
     	state <= IDLE;
     	end
     else
        state <= next_state;
    end

    // State evo function:
    always @(*) begin
        case (state)
            IDLE: begin
            	start_stop = 1'b0;
        	reset      = 1'b1;
        	reg_out    = 1'b0;
        	data_valid = 1'b0;
                if (osc == 1'b1)
                    next_state = RUN;
                else
                    next_state = IDLE;
            end

            RUN: begin
            	start_stop = 1'b1;
        	reset      = 1'b0;
        	reg_out    = 1'b0;
        	data_valid = 1'b0;
                if (end_meas == 1'b1)
                    next_state = WRITE;
                else
                    next_state = RUN;
            end

            WRITE: begin
                next_state = DATA_VALID;
                start_stop = 1'b0;
        	reset      = 1'b0;
        	reg_out    = 1'b1;
        	data_valid = 1'b0;
            end
	    
	    DATA_VALID: begin
	    	next_state = IDLE;
	    	start_stop = 1'b0;
        	reset        = 1'b0;
        	reg_out    = 1'b0;
        	data_valid = 1'b1;
            end 
            
            default: begin
            	next_state = IDLE;
            	start_stop = 1'b0;
        	reset      = 1'b0;
        	reg_out    = 1'b0;
        	data_valid = 1'b0;
            end
        endcase
    end