You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2025 tgrillz
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_tgrillz_sixSidedDie #(parameter STATE = 8'b1000_0001)(
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path 
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // ^ this is enables this IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

    // All output pins must be assigned. If not used, assign to 0.
    // assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in
    assign uio_out = 0;
    assign uio_oe  = 0;
    assign uo_out[7] = 1'b0;

    // List all unused inputs to prevent warnings
    // wire _unused = &{ena, clk, rst_n, 1'b0};
    wire _unused = &{ena, uio_in, ui_in[7:1], 1'b0};
  
    reg [7:0] roll;
    reg [7:0] thisRoll;
    reg [7:0] outRoll;
    reg lastReset;
    reg [6:0] outNum;
    
    // Creats a "randomly" generated number using lfsr
    // Note this will always turn on to 0 if the dip switch is set to on at start up
    // A reset or a reset of the dipswitch is needed to adjust
    // Assumes an explicit reset at initilization
    
    eightBitlfsr lfsr(.clk(clk), .rst_n(rst_n), .seed(STATE), .out(thisRoll));

    always @(posedge clk) begin  

        if (!rst_n) begin    
            roll <= 8'b0000_0000;
            outRoll <= 8'b0000_0000;
            lastReset <= 1'b1;

        end else begin

            // if "on"
            if (ui_in[0]) begin
                // if new roll after reset get new number
                if (!lastReset) begin
                    roll <= thisRoll;
                // otherwise hold number until next roll
                end else begin
                    roll <= roll;
                end

            // if "off" keep cycling through numbers                
            end else begin
                roll <= thisRoll;
            end

            // update tracker of last reset value
            if (outNum == 7'b0000000)
                lastReset <= 1'b0;
            else
                lastReset <= rst_n;
        end

        // Outputs 0 if in "off" state
        if (ui_in[0]) begin
            outRoll <= roll;
        end else begin
            outRoll <= 0;
        end

    end

    // Output number to 7 segment display
    sevenSeg sevenSegment(.clk(clk), .rst_n(rst_n), .inputNum(outRoll), .out(outNum));

    // Assign 7 segment bits to LSB of outwire
    assign uo_out[6:0] = outNum;

endmodule

`default_nettype none

module eightBitlfsr # (parameter BITNUM = 8)(
    input wire clk,
    input wire rst_n,
    input wire [7:0] seed,
    output wire [7:0] out
    );

    reg [BITNUM-1:0] state = 8'b1000_0001;
    reg [7:0] lfsrVal;
    reg [7:0] insideRoll;

    always @(posedge clk) begin     
        if(!rst_n) begin
            state <= seed;
        end else begin
            state <= seed;
            if (state == 8'b0000_0000) begin
                state <= 8'b1000_0001;
            end else begin
                // Create a "randomly" generated number using lfsr
                state <= {state[6:0], (state[0] ^ state[3] ^ state[7])};
            end

            lfsrVal <= {5'b00000, state[2:0]};   // isolates 3 LSB
            
            if (lfsrVal < 6) begin
                insideRoll <= lfsrVal + 1;      // number between 1 and 6
            end else begin
                insideRoll <= insideRoll;         // hold until next valid number 
            end

        end
    end        

    assign out = insideRoll;

endmodule


`default_nettype none

module sevenSeg (
    input wire clk,
    input wire rst_n,
    input wire [7:0] inputNum,
    output wire [6:0] out
    );
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule



Reference solution:
rtl/generated.v: 
    reg [7:0] displayIt;
    reg [6:0] outNum;

    always @(posedge clk) begin
        if (!rst_n) begin
            displayIt <= 0;
        end else begin
            displayIt <= inputNum;
        end
    end

    always @(*) begin
       // Output number to 7 segment display
        case(displayIt)
            0:  outNum = 7'b0111111;
            1:  outNum = 7'b0000110;
            2:  outNum = 7'b1011011;
            3:  outNum = 7'b1001111;
            4:  outNum = 7'b1100110;
            5:  outNum = 7'b1101101;
            6:  outNum = 7'b1111100;
            7:  outNum = 7'b0000111;
            8:  outNum = 7'b1111111;
            9:  outNum = 7'b1100111;
            default:
                outNum = 7'b0000000;
        endcase
    end

    assign out = outNum;