You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Your Name
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_dac12 (
    input  wire [7:0] ui_in,   // Dedicated inputs [11:4]
    output wire [7:0] uo_out,  // Dedicated outputs
    input  wire [7:0] uio_in,  // IOs: Input path [3:0]
    output wire [7:0] uio_out, // IOs: Output path
    output wire [7:0] uio_oe,  // IOs: Enable path
    input  wire       ena,
    input  wire       clk,
    input  wire       rst_n
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




`default_nettype none
`timescale 1ns/1ps

module pwm_dac_12bit (
    input wire clk,
    input wire rst_n,
    input wire [11:0] dac_in,  // Your 12-bit digital input
    output wire pwm_out      // The 1-bit PWM output
);

    // A free-running 12-bit counter that increments on each clock cycle.
    reg [11:0] counter = 0;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            counter <= 12'd0;
        end else begin
            counter <= counter + 1;
        end
    end

    // The core PWM logic:
    // The output is high as long as the counter's value is less than the input value.
    // A larger dac_in value means the output stays high for more of the counter's cycle.
    assign pwm_out = (counter < dac_in);

endmodule


Reference solution:
rtl/generated.v: 
    // --- 12-Bit DAC Implementation ---

    // 1. Combine inputs to form a 12-bit data word.
    //    Using ui_in for the most significant 8 bits and uio_in for the least significant 4 bits.
    wire [11:0] dac_input = {ui_in, uio_in[3:0]};

    // 2. This wire will carry the 1-bit PWM signal from our DAC module.
    wire pwm_signal;

    // 3. Instantiate the 12-bit PWM DAC module.
    pwm_dac_12bit my_pwm_dac (
        .clk(clk),
        .rst_n(rst_n),
        .dac_in(dac_input),
        .pwm_out(pwm_signal)
    );

    // --- Pin Assignments ---

    // 4. Route the PWM signal to a digital output pin.
    assign uo_out[0] = pwm_signal;

    // Tie off all other unused digital outputs to ground.
    assign uo_out[7:1] = 7'b0;
    assign uio_out     = 8'b0;

    // 5. Configure the bidirectional IO pins.
    //    Set uio_oe[3:0] to 0 to use them as inputs.
    //    The rest are also inputs.
    assign uio_oe = 8'b00000000; // All uio pins are inputs