You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

`default_nettype none
`timescale 1ns/1ns

module tt_um_triple_watchdog (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // will go high when the design is enabled
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




`default_nettype none
`timescale 1ns/1ns
module watchdog (
    input wire clk,          // Clock input
    input wire rst_n,        // Reset input
    input wire [7:0] ui_in,  // Dedicated inputs
    output wire watchdog_expired // Watchdog expiration signal
);

// Parameters
parameter TIMEOUT_VALUE = 100000; // Timeout value (in clock cycles)

// Internal signals
reg [7:0] ui_in_reg;
reg [31:0] counter;
reg [1:0] state;

// Watchdog states
parameter IDLE = 2'b00;
parameter ACTIVE = 2'b01;

// Watchdog expiration flag
reg expired;

// Watchdog expiration detection logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        counter <= 0;
        state <= IDLE;
        expired <= 0;
        ui_in_reg<=0;
    end else begin
        case (state)
            IDLE: begin
                if (ui_in != ui_in_reg) begin
                    state <= ACTIVE;
                    expired <= 0;
                    counter <= 0;
                    ui_in_reg <= ui_in;
                end
            end
            ACTIVE: begin
                if (ui_in == ui_in_reg) begin
                    counter <= counter + 1;
                    if (counter == TIMEOUT_VALUE) begin
                        expired <= 1;
                        state<=IDLE;
                    end
                end else begin
                    counter <= 0;
                    state <= IDLE;
                end
            end
        endcase
    end
end

// Output expiration signal when expired
assign watchdog_expired = expired;


endmodule


Reference solution:
rtl/generated.v: 
// Instantiate three watchdog instances
watchdog watchdog1(
    .clk(clk),
    .rst_n(rst_n),
    .ui_in(ui_in),
    .watchdog_expired(uo_out[0])
);

watchdog watchdog2(
    .clk(clk),
    .rst_n(rst_n),
    .ui_in(ui_in),
    .watchdog_expired(uo_out[1])
);

watchdog watchdog3(
    .clk(clk),
    .rst_n(rst_n),
    .ui_in(ui_in),
    .watchdog_expired(uo_out[2])
);


assign uo_out[7:3] = 0; // Clear undriven bits while preserving driven bits
assign uio_out=0;
assign uio_oe=0;