You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 andrewtron3000
 * SPDX-License-Identifier: Apache-2.0
 */

`define default_netname none

module tt_um_andrewtron3000 (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // will go high when the design is enabled
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

  // Held in reset while ena is not set
  wire reset_n;
  assign reset_n = rst_n & ena;

  assign uio_oe  = 8'b00000000; // All bidirectional outputs disabled
  assign uio_out = 0;
  
  // Assign output
  assign uo_out[0] = 0;
  assign uo_out[1] = 0;
  assign uo_out[2] = 0;
  assign uo_out[3] = 0;
  assign uo_out[4] = driver_sout;   // uo_out[4] is UART TX
  assign uo_out[5] = 0;
  assign uo_out[6] = 0;
  assign uo_out[7] = 0;

  // ports of submodule driver
  wire driver_sin, driver_sout;
  assign driver_sin = 0;

  wire startup_input_ready;
  wire startup_input_enable;
  wire operation_mode_ready;
  wire operation_mode_enable;

  // submodule rule_30_driver
  mkRule30Driver rule_30_driver(.CLK(clk),
				.RST_N(reset_n),

        .operation_mode_arg(uio_in),
        .EN_operation_mode(operation_mode_enable),
        .RDY_operation_mode(operation_mode_ready),

				.startup_value_v(ui_in),
				.EN_startup_value(startup_input_enable),
				.RDY_startup_value(startup_input_ready),

				.txrx_SIN(driver_sin),
				.txrx_SOUT(driver_sout));

  assign startup_input_enable = startup_input_ready;
  assign operation_mode_enable = operation_mode_ready;

endmodule


//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:53 EDT 2024
//
//
// Ports:
// Name                         I/O  size props
// RDY_operation_mode             O     1
// RDY_startup_value              O     1
// txrx_SOUT                      O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// operation_mode_arg             I     8
// startup_value_v                I     8
// txrx_SIN                       I     1 reg
// EN_operation_mode              I     1
// EN_startup_value               I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkRule30Driver(CLK,
		      RST_N,

		      operation_mode_arg,
		      EN_operation_mode,
		      RDY_operation_mode,

		      startup_value_v,
		      EN_startup_value,
		      RDY_startup_value,

		      txrx_SIN,

		      txrx_SOUT);
  input  CLK;
  input  RST_N;

  // action method operation_mode
  input  [7 : 0] operation_mode_arg;
  input  EN_operation_mode;
  output RDY_operation_mode;

  // action method startup_value
  input  [7 : 0] startup_value_v;
  input  EN_startup_value;
  output RDY_startup_value;

  // action method txrx_sin
  input  txrx_SIN;

  // value method txrx_sout
  output txrx_SOUT;

  // signals for module outputs
  wire RDY_operation_mode, RDY_startup_value, txrx_SOUT;

  // inlined wires
  wire uart_fifoXmit_r_enq$whas,
       uart_pwRecvCellCountReset$whas,
       uart_pwRecvEnableBitCount$whas,
       uart_pwRecvResetBitCount$whas,
       uart_pwXmitCellCountReset$whas,
       uart_pwXmitEnableBitCount$whas,
       uart_pwXmitLoadBuffer$whas,
       xmas_fsm_start_wire$whas,
       xmas_fsm_state_set_pw$whas;

  // register a
  reg [7 : 0] a;
  wire [7 : 0] a$D_IN;
  wire a$EN;

  // register op_mode
  reg op_mode;
  wire op_mode$D_IN, op_mode$EN;

  // register transmit_state
  reg [1 : 0] transmit_state;
  wire [1 : 0] transmit_state$D_IN;
  wire transmit_state$EN;

  // register uart_rRecvBitCount
  reg [3 : 0] uart_rRecvBitCount;
  wire [3 : 0] uart_rRecvBitCount$D_IN;
  wire uart_rRecvBitCount$EN;

  // register uart_rRecvCellCount
  reg [3 : 0] uart_rRecvCellCount;
  wire [3 : 0] uart_rRecvCellCount$D_IN;
  wire uart_rRecvCellCount$EN;

  // register uart_rRecvData
  reg uart_rRecvData;
  wire uart_rRecvData$D_IN, uart_rRecvData$EN;

  // register uart_rRecvState
  reg [2 : 0] uart_rRecvState;
  reg [2 : 0] uart_rRecvState$D_IN;
  wire uart_rRecvState$EN;

  // register uart_rXmitBitCount
  reg [3 : 0] uart_rXmitBitCount;
  wire [3 : 0] uart_rXmitBitCount$D_IN;
  wire uart_rXmitBitCount$EN;

  // register uart_rXmitCellCount
  reg [3 : 0] uart_rXmitCellCount;
  wire [3 : 0] uart_rXmitCellCount$D_IN;
  wire uart_rXmitCellCount$EN;

  // register uart_rXmitDataOut
  reg uart_rXmitDataOut;
  reg uart_rXmitDataOut$D_IN;
  wire uart_rXmitDataOut$EN;

  // register uart_rXmitState
  reg [2 : 0] uart_rXmitState;
  reg [2 : 0] uart_rXmitState$D_IN;
  wire uart_rXmitState$EN;

  // register uart_vrRecvBuffer_0
  reg uart_vrRecvBuffer_0;
  wire uart_vrRecvBuffer_0$D_IN, uart_vrRecvBuffer_0$EN;

  // register uart_vrRecvBuffer_1
  reg uart_vrRecvBuffer_1;
  wire uart_vrRecvBuffer_1$D_IN, uart_vrRecvBuffer_1$EN;

  // register uart_vrRecvBuffer_2
  reg uart_vrRecvBuffer_2;
  wire uart_vrRecvBuffer_2$D_IN, uart_vrRecvBuffer_2$EN;

  // register uart_vrRecvBuffer_3
  reg uart_vrRecvBuffer_3;
  wire uart_vrRecvBuffer_3$D_IN, uart_vrRecvBuffer_3$EN;

  // register uart_vrRecvBuffer_4
  reg uart_vrRecvBuffer_4;
  wire uart_vrRecvBuffer_4$D_IN, uart_vrRecvBuffer_4$EN;

  // register uart_vrRecvBuffer_5
  reg uart_vrRecvBuffer_5;
  wire uart_vrRecvBuffer_5$D_IN, uart_vrRecvBuffer_5$EN;

  // register uart_vrRecvBuffer_6
  reg uart_vrRecvBuffer_6;
  wire uart_vrRecvBuffer_6$D_IN, uart_vrRecvBuffer_6$EN;

  // register uart_vrRecvBuffer_7
  reg uart_vrRecvBuffer_7;
  wire uart_vrRecvBuffer_7$D_IN, uart_vrRecvBuffer_7$EN;

  // register uart_vrXmitBuffer_0
  reg uart_vrXmitBuffer_0;
  wire uart_vrXmitBuffer_0$D_IN, uart_vrXmitBuffer_0$EN;

  // register uart_vrXmitBuffer_1
  reg uart_vrXmitBuffer_1;
  wire uart_vrXmitBuffer_1$D_IN, uart_vrXmitBuffer_1$EN;

  // register uart_vrXmitBuffer_2
  reg uart_vrXmitBuffer_2;
  wire uart_vrXmitBuffer_2$D_IN, uart_vrXmitBuffer_2$EN;

  // register uart_vrXmitBuffer_3
  reg uart_vrXmitBuffer_3;
  wire uart_vrXmitBuffer_3$D_IN, uart_vrXmitBuffer_3$EN;

  // register uart_vrXmitBuffer_4
  reg uart_vrXmitBuffer_4;
  wire uart_vrXmitBuffer_4$D_IN, uart_vrXmitBuffer_4$EN;

  // register uart_vrXmitBuffer_5
  reg uart_vrXmitBuffer_5;
  wire uart_vrXmitBuffer_5$D_IN, uart_vrXmitBuffer_5$EN;

  // register uart_vrXmitBuffer_6
  reg uart_vrXmitBuffer_6;
  wire uart_vrXmitBuffer_6$D_IN, uart_vrXmitBuffer_6$EN;

  // register uart_vrXmitBuffer_7
  reg uart_vrXmitBuffer_7;
  wire uart_vrXmitBuffer_7$D_IN, uart_vrXmitBuffer_7$EN;

  // register xmas_fsm_start_reg
  reg xmas_fsm_start_reg;
  wire xmas_fsm_start_reg$D_IN, xmas_fsm_start_reg$EN;

  // register xmas_fsm_start_reg_1
  reg xmas_fsm_start_reg_1;
  wire xmas_fsm_start_reg_1$D_IN, xmas_fsm_start_reg_1$EN;

  // register xmas_fsm_state_fired
  reg xmas_fsm_state_fired;
  wire xmas_fsm_state_fired$D_IN, xmas_fsm_state_fired$EN;

  // register xmas_fsm_state_mkFSMstate
  reg [4 : 0] xmas_fsm_state_mkFSMstate;
  reg [4 : 0] xmas_fsm_state_mkFSMstate$D_IN;
  wire xmas_fsm_state_mkFSMstate$EN;

  // ports of submodule rule30
  wire [7 : 0] rule30$getResult, rule30$start_a;
  wire rule30$EN_getResult,
       rule30$EN_start,
       rule30$RDY_getResult,
       rule30$RDY_start;

  // ports of submodule uart_baudGen_rBaudCounter
  wire [15 : 0] uart_baudGen_rBaudCounter$DATA_A,
		uart_baudGen_rBaudCounter$DATA_B,
		uart_baudGen_rBaudCounter$DATA_C,
		uart_baudGen_rBaudCounter$DATA_F,
		uart_baudGen_rBaudCounter$Q_OUT;
  wire uart_baudGen_rBaudCounter$ADDA,
       uart_baudGen_rBaudCounter$ADDB,
       uart_baudGen_rBaudCounter$SETC,
       uart_baudGen_rBaudCounter$SETF;

  // ports of submodule uart_baudGen_rBaudTickCounter
  wire [2 : 0] uart_baudGen_rBaudTickCounter$DATA_A,
	       uart_baudGen_rBaudTickCounter$DATA_B,
	       uart_baudGen_rBaudTickCounter$DATA_C,
	       uart_baudGen_rBaudTickCounter$DATA_F,
	       uart_baudGen_rBaudTickCounter$Q_OUT;
  wire uart_baudGen_rBaudTickCounter$ADDA,
       uart_baudGen_rBaudTickCounter$ADDB,
       uart_baudGen_rBaudTickCounter$SETC,
       uart_baudGen_rBaudTickCounter$SETF;

  // ports of submodule uart_fifoRecv
  wire [7 : 0] uart_fifoRecv$D_IN;
  wire uart_fifoRecv$CLR,
       uart_fifoRecv$DEQ,
       uart_fifoRecv$EMPTY_N,
       uart_fifoRecv$ENQ;

  // ports of submodule uart_fifoXmit
  reg [7 : 0] uart_fifoXmit$D_IN;
  wire [7 : 0] uart_fifoXmit$D_OUT;
  wire uart_fifoXmit$CLR,
       uart_fifoXmit$DEQ,
       uart_fifoXmit$EMPTY_N,
       uart_fifoXmit$ENQ,
       uart_fifoXmit$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_compute,
       CAN_FIRE_RL_dump_rx,
       CAN_FIRE_RL_get_result,
       CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
       CAN_FIRE_RL_uart_baudGen_baud_count_wire,
       CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire,
       CAN_FIRE_RL_uart_baudGen_count_baudtick_16x,
       CAN_FIRE_RL_uart_baud_generator_clock_enable,
       CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter,
       CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter,
       CAN_FIRE_RL_uart_receive_bit_cell_time_counter,
       CAN_FIRE_RL_uart_receive_bit_counter,
       CAN_FIRE_RL_uart_receive_buffer_shift,
       CAN_FIRE_RL_uart_receive_find_center_of_bit_cell,
       CAN_FIRE_RL_uart_receive_parity_bit,
       CAN_FIRE_RL_uart_receive_sample_pin,
       CAN_FIRE_RL_uart_receive_stop_first_bit,
       CAN_FIRE_RL_uart_receive_stop_last_bit,
       CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
       CAN_FIRE_RL_uart_receive_wait_for_start_bit,
       CAN_FIRE_RL_uart_transmit_bit_cell_time_counter,
       CAN_FIRE_RL_uart_transmit_bit_counter,
       CAN_FIRE_RL_uart_transmit_buffer_load,
       CAN_FIRE_RL_uart_transmit_buffer_shift,
       CAN_FIRE_RL_uart_transmit_send_parity_bit,
       CAN_FIRE_RL_uart_transmit_send_start_bit,
       CAN_FIRE_RL_uart_transmit_send_stop_bit,
       CAN_FIRE_RL_uart_transmit_send_stop_bit1_5,
       CAN_FIRE_RL_uart_transmit_send_stop_bit2,
       CAN_FIRE_RL_uart_transmit_shift_next_bit,
       CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
       CAN_FIRE_RL_uart_transmit_wait_for_start_command,
       CAN_FIRE_RL_xmas_fsm_action_l42c32,
       CAN_FIRE_RL_xmas_fsm_action_l43c32,
       CAN_FIRE_RL_xmas_fsm_action_l44c32,
       CAN_FIRE_RL_xmas_fsm_action_l45c32,
       CAN_FIRE_RL_xmas_fsm_action_l46c32,
       CAN_FIRE_RL_xmas_fsm_action_l47c32,
       CAN_FIRE_RL_xmas_fsm_action_l48c32,
       CAN_FIRE_RL_xmas_fsm_action_l49c32,
       CAN_FIRE_RL_xmas_fsm_action_l50c32,
       CAN_FIRE_RL_xmas_fsm_action_l51c32,
       CAN_FIRE_RL_xmas_fsm_action_l52c32,
       CAN_FIRE_RL_xmas_fsm_action_l53c32,
       CAN_FIRE_RL_xmas_fsm_action_l54c32,
       CAN_FIRE_RL_xmas_fsm_action_l55c32,
       CAN_FIRE_RL_xmas_fsm_action_l56c32,
       CAN_FIRE_RL_xmas_fsm_action_l57c32,
       CAN_FIRE_RL_xmas_fsm_action_l58c32,
       CAN_FIRE_RL_xmas_fsm_action_l59c32,
       CAN_FIRE_RL_xmas_fsm_action_l60c32,
       CAN_FIRE_RL_xmas_fsm_action_l61c32,
       CAN_FIRE_RL_xmas_fsm_action_l62c32,
       CAN_FIRE_RL_xmas_fsm_action_l63c32,
       CAN_FIRE_RL_xmas_fsm_action_l64c32,
       CAN_FIRE_RL_xmas_fsm_action_l65c32,
       CAN_FIRE_RL_xmas_fsm_action_l66c32,
       CAN_FIRE_RL_xmas_fsm_fsm_start,
       CAN_FIRE_RL_xmas_fsm_idle_l40c27,
       CAN_FIRE_RL_xmas_fsm_idle_l40c27_1,
       CAN_FIRE_RL_xmas_fsm_restart,
       CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update,
       CAN_FIRE_RL_xmas_fsm_state_every,
       CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update,
       CAN_FIRE_RL_xmas_fsm_state_handle_abort,
       CAN_FIRE___me_check_34,
       CAN_FIRE___me_check_35,
       CAN_FIRE___me_check_36,
       CAN_FIRE___me_check_37,
       CAN_FIRE___me_check_38,
       CAN_FIRE___me_check_39,
       CAN_FIRE___me_check_40,
       CAN_FIRE___me_check_41,
       CAN_FIRE___me_check_42,
       CAN_FIRE___me_check_43,
       CAN_FIRE___me_check_44,
       CAN_FIRE___me_check_45,
       CAN_FIRE___me_check_46,
       CAN_FIRE___me_check_47,
       CAN_FIRE___me_check_48,
       CAN_FIRE___me_check_49,
       CAN_FIRE___me_check_50,
       CAN_FIRE___me_check_51,
       CAN_FIRE___me_check_52,
       CAN_FIRE___me_check_53,
       CAN_FIRE___me_check_54,
       CAN_FIRE___me_check_55,
       CAN_FIRE___me_check_56,
       CAN_FIRE___me_check_57,
       CAN_FIRE_operation_mode,
       CAN_FIRE_startup_value,
       CAN_FIRE_txrx_sin,
       WILL_FIRE_RL_compute,
       WILL_FIRE_RL_dump_rx,
       WILL_FIRE_RL_get_result,
       WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
       WILL_FIRE_RL_uart_baudGen_baud_count_wire,
       WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire,
       WILL_FIRE_RL_uart_baudGen_count_baudtick_16x,
       WILL_FIRE_RL_uart_baud_generator_clock_enable,
       WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter,
       WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter,
       WILL_FIRE_RL_uart_receive_bit_cell_time_counter,
       WILL_FIRE_RL_uart_receive_bit_counter,
       WILL_FIRE_RL_uart_receive_buffer_shift,
       WILL_FIRE_RL_uart_receive_find_center_of_bit_cell,
       WILL_FIRE_RL_uart_receive_parity_bit,
       WILL_FIRE_RL_uart_receive_sample_pin,
       WILL_FIRE_RL_uart_receive_stop_first_bit,
       WILL_FIRE_RL_uart_receive_stop_last_bit,
       WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
       WILL_FIRE_RL_uart_receive_wait_for_start_bit,
       WILL_FIRE_RL_uart_transmit_bit_cell_time_counter,
       WILL_FIRE_RL_uart_transmit_bit_counter,
       WILL_FIRE_RL_uart_transmit_buffer_load,
       WILL_FIRE_RL_uart_transmit_buffer_shift,
       WILL_FIRE_RL_uart_transmit_send_parity_bit,
       WILL_FIRE_RL_uart_transmit_send_start_bit,
       WILL_FIRE_RL_uart_transmit_send_stop_bit,
       WILL_FIRE_RL_uart_transmit_send_stop_bit1_5,
       WILL_FIRE_RL_uart_transmit_send_stop_bit2,
       WILL_FIRE_RL_uart_transmit_shift_next_bit,
       WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
       WILL_FIRE_RL_uart_transmit_wait_for_start_command,
       WILL_FIRE_RL_xmas_fsm_action_l42c32,
       WILL_FIRE_RL_xmas_fsm_action_l43c32,
       WILL_FIRE_RL_xmas_fsm_action_l44c32,
       WILL_FIRE_RL_xmas_fsm_action_l45c32,
       WILL_FIRE_RL_xmas_fsm_action_l46c32,
       WILL_FIRE_RL_xmas_fsm_action_l47c32,
       WILL_FIRE_RL_xmas_fsm_action_l48c32,
       WILL_FIRE_RL_xmas_fsm_action_l49c32,
       WILL_FIRE_RL_xmas_fsm_action_l50c32,
       WILL_FIRE_RL_xmas_fsm_action_l51c32,
       WILL_FIRE_RL_xmas_fsm_action_l52c32,
       WILL_FIRE_RL_xmas_fsm_action_l53c32,
       WILL_FIRE_RL_xmas_fsm_action_l54c32,
       WILL_FIRE_RL_xmas_fsm_action_l55c32,
       WILL_FIRE_RL_xmas_fsm_action_l56c32,
       WILL_FIRE_RL_xmas_fsm_action_l57c32,
       WILL_FIRE_RL_xmas_fsm_action_l58c32,
       WILL_FIRE_RL_xmas_fsm_action_l59c32,
       WILL_FIRE_RL_xmas_fsm_action_l60c32,
       WILL_FIRE_RL_xmas_fsm_action_l61c32,
       WILL_FIRE_RL_xmas_fsm_action_l62c32,
       WILL_FIRE_RL_xmas_fsm_action_l63c32,
       WILL_FIRE_RL_xmas_fsm_action_l64c32,
       WILL_FIRE_RL_xmas_fsm_action_l65c32,
       WILL_FIRE_RL_xmas_fsm_action_l66c32,
       WILL_FIRE_RL_xmas_fsm_fsm_start,
       WILL_FIRE_RL_xmas_fsm_idle_l40c27,
       WILL_FIRE_RL_xmas_fsm_idle_l40c27_1,
       WILL_FIRE_RL_xmas_fsm_restart,
       WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update,
       WILL_FIRE_RL_xmas_fsm_state_every,
       WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update,
       WILL_FIRE_RL_xmas_fsm_state_handle_abort,
       WILL_FIRE___me_check_34,
       WILL_FIRE___me_check_35,
       WILL_FIRE___me_check_36,
       WILL_FIRE___me_check_37,
       WILL_FIRE___me_check_38,
       WILL_FIRE___me_check_39,
       WILL_FIRE___me_check_40,
       WILL_FIRE___me_check_41,
       WILL_FIRE___me_check_42,
       WILL_FIRE___me_check_43,
       WILL_FIRE___me_check_44,
       WILL_FIRE___me_check_45,
       WILL_FIRE___me_check_46,
       WILL_FIRE___me_check_47,
       WILL_FIRE___me_check_48,
       WILL_FIRE___me_check_49,
       WILL_FIRE___me_check_50,
       WILL_FIRE___me_check_51,
       WILL_FIRE___me_check_52,
       WILL_FIRE___me_check_53,
       WILL_FIRE___me_check_54,
       WILL_FIRE___me_check_55,
       WILL_FIRE___me_check_56,
       WILL_FIRE___me_check_57,
       WILL_FIRE_operation_mode,
       WILL_FIRE_startup_value,
       WILL_FIRE_txrx_sin;

  // inputs to muxes for submodule ports
  reg [2 : 0] MUX_uart_rRecvState$write_1__VAL_3;
  wire [2 : 0] MUX_uart_rRecvState$write_1__VAL_1,
	       MUX_uart_rRecvState$write_1__VAL_2,
	       MUX_uart_rRecvState$write_1__VAL_4,
	       MUX_uart_rXmitState$write_1__VAL_1,
	       MUX_uart_rXmitState$write_1__VAL_2,
	       MUX_uart_rXmitState$write_1__VAL_3,
	       MUX_uart_rXmitState$write_1__VAL_4,
	       MUX_uart_rXmitState$write_1__VAL_5,
	       MUX_uart_rXmitState$write_1__VAL_6,
	       MUX_uart_rXmitState$write_1__VAL_7;
  wire MUX_transmit_state$write_1__SEL_1,
       MUX_uart_fifoXmit$enq_1__SEL_11,
       MUX_uart_fifoXmit$enq_1__SEL_15,
       MUX_uart_fifoXmit$enq_1__SEL_16,
       MUX_uart_fifoXmit$enq_1__SEL_17,
       MUX_uart_fifoXmit$enq_1__SEL_2,
       MUX_uart_fifoXmit$enq_1__SEL_3,
       MUX_uart_rRecvState$write_1__SEL_6,
       MUX_uart_rXmitDataOut$write_1__SEL_1,
       MUX_uart_rXmitDataOut$write_1__SEL_2,
       MUX_uart_rXmitDataOut$write_1__SEL_3,
       MUX_xmas_fsm_start_reg$write_1__SEL_1,
       MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1;

  // remaining internal signals
  wire [3 : 0] x__h2985, x__h4689, x__h6445, x__h6471;
  wire _dor2uart_pwXmitCellCountReset$EN_wset,
       uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29,
       xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302;

  // action method operation_mode
  assign RDY_operation_mode =
	     transmit_state == 2'd0 && !op_mode &&
	     xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
	     !xmas_fsm_start_reg ;
  assign CAN_FIRE_operation_mode =
	     transmit_state == 2'd0 && !op_mode &&
	     xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
	     !xmas_fsm_start_reg ;
  assign WILL_FIRE_operation_mode = EN_operation_mode ;

  // action method startup_value
  assign RDY_startup_value = transmit_state == 2'd0 && !op_mode ;
  assign CAN_FIRE_startup_value = transmit_state == 2'd0 && !op_mode ;
  assign WILL_FIRE_startup_value = EN_startup_value ;

  // action method txrx_sin
  assign CAN_FIRE_txrx_sin = 1'd1 ;
  assign WILL_FIRE_txrx_sin = 1'd1 ;

  // value method txrx_sout
  assign txrx_SOUT = uart_rXmitDataOut ;

  // submodule rule30
  mkRule30 rule30(.CLK(CLK),
		  .RST_N(RST_N),
		  .start_a(rule30$start_a),
		  .EN_start(rule30$EN_start),
		  .EN_getResult(rule30$EN_getResult),
		  .RDY_start(rule30$RDY_start),
		  .getResult(rule30$getResult),
		  .RDY_getResult(rule30$RDY_getResult));

  // submodule uart_baudGen_rBaudCounter
  Counter #(.width(32'd16), .init(16'd0)) uart_baudGen_rBaudCounter(.CLK(CLK),
								    .RST(RST_N),
								    .DATA_A(uart_baudGen_rBaudCounter$DATA_A),
								    .DATA_B(uart_baudGen_rBaudCounter$DATA_B),
								    .DATA_C(uart_baudGen_rBaudCounter$DATA_C),
								    .DATA_F(uart_baudGen_rBaudCounter$DATA_F),
								    .ADDA(uart_baudGen_rBaudCounter$ADDA),
								    .ADDB(uart_baudGen_rBaudCounter$ADDB),
								    .SETC(uart_baudGen_rBaudCounter$SETC),
								    .SETF(uart_baudGen_rBaudCounter$SETF),
								    .Q_OUT(uart_baudGen_rBaudCounter$Q_OUT));

  // submodule uart_baudGen_rBaudTickCounter
  Counter #(.width(32'd3),
	    .init(3'd0)) uart_baudGen_rBaudTickCounter(.CLK(CLK),
						       .RST(RST_N),
						       .DATA_A(uart_baudGen_rBaudTickCounter$DATA_A),
						       .DATA_B(uart_baudGen_rBaudTickCounter$DATA_B),
						       .DATA_C(uart_baudGen_rBaudTickCounter$DATA_C),
						       .DATA_F(uart_baudGen_rBaudTickCounter$DATA_F),
						       .ADDA(uart_baudGen_rBaudTickCounter$ADDA),
						       .ADDB(uart_baudGen_rBaudTickCounter$ADDB),
						       .SETC(uart_baudGen_rBaudTickCounter$SETC),
						       .SETF(uart_baudGen_rBaudTickCounter$SETF),
						       .Q_OUT(uart_baudGen_rBaudTickCounter$Q_OUT));

  // submodule uart_fifoRecv
  SizedFIFO #(.p1width(32'd8),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(1'd1)) uart_fifoRecv(.RST(RST_N),
					    .CLK(CLK),
					    .D_IN(uart_fifoRecv$D_IN),
					    .ENQ(uart_fifoRecv$ENQ),
					    .DEQ(uart_fifoRecv$DEQ),
					    .CLR(uart_fifoRecv$CLR),
					    .D_OUT(),
					    .FULL_N(),
					    .EMPTY_N(uart_fifoRecv$EMPTY_N));

  // submodule uart_fifoXmit
  SizedFIFO #(.p1width(32'd8),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(1'd1)) uart_fifoXmit(.RST(RST_N),
					    .CLK(CLK),
					    .D_IN(uart_fifoXmit$D_IN),
					    .ENQ(uart_fifoXmit$ENQ),
					    .DEQ(uart_fifoXmit$DEQ),
					    .CLR(uart_fifoXmit$CLR),
					    .D_OUT(uart_fifoXmit$D_OUT),
					    .FULL_N(uart_fifoXmit$FULL_N),
					    .EMPTY_N(uart_fifoXmit$EMPTY_N));

  // rule RL_dump_rx
  assign CAN_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
  assign WILL_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;

  // rule RL_compute
  assign CAN_FIRE_RL_compute =
	     rule30$RDY_start && transmit_state == 2'd1 && !op_mode ;
  assign WILL_FIRE_RL_compute = CAN_FIRE_RL_compute ;

  // rule RL_uart_baudGen_baud_count_wire
  assign CAN_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
  assign WILL_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;

  // rule RL_uart_baud_generator_clock_enable
  assign CAN_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
  assign WILL_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;

  // rule RL_uart_receive_wait_for_start_bit
  assign CAN_FIRE_RL_uart_receive_wait_for_start_bit =
	     uart_rRecvState == 3'd0 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_receive_wait_for_start_bit =
	     CAN_FIRE_RL_uart_receive_wait_for_start_bit ;

  // rule RL_uart_receive_find_center_of_bit_cell
  assign CAN_FIRE_RL_uart_receive_find_center_of_bit_cell =
	     uart_rRecvState == 3'd1 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_receive_find_center_of_bit_cell =
	     CAN_FIRE_RL_uart_receive_find_center_of_bit_cell ;

  // rule RL_uart_receive_wait_bit_cell_time_for_sample
  assign CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
	     uart_rRecvState == 3'd2 && uart_rRecvCellCount == 4'hF &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
	     CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ;

  // rule RL_uart_receive_sample_pin
  assign CAN_FIRE_RL_uart_receive_sample_pin =
	     CAN_FIRE_RL_uart_receive_buffer_shift ;
  assign WILL_FIRE_RL_uart_receive_sample_pin =
	     CAN_FIRE_RL_uart_receive_buffer_shift ;

  // rule RL_uart_receive_parity_bit
  assign CAN_FIRE_RL_uart_receive_parity_bit =
	     uart_rRecvState == 3'd4 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_receive_parity_bit =
	     CAN_FIRE_RL_uart_receive_parity_bit ;

  // rule RL_uart_receive_stop_first_bit
  assign CAN_FIRE_RL_uart_receive_stop_first_bit =
	     uart_rRecvState == 3'd5 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_receive_stop_first_bit =
	     CAN_FIRE_RL_uart_receive_stop_first_bit ;

  // rule RL_uart_receive_bit_counter
  assign CAN_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
  assign WILL_FIRE_RL_uart_receive_bit_counter = 1'd1 ;

  // rule RL_uart_receive_stop_last_bit
  assign CAN_FIRE_RL_uart_receive_stop_last_bit =
	     uart_rRecvState == 3'd6 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_receive_stop_last_bit =
	     CAN_FIRE_RL_uart_receive_stop_last_bit ;

  // rule RL_uart_receive_bit_cell_time_counter
  assign CAN_FIRE_RL_uart_receive_bit_cell_time_counter =
	     CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
  assign WILL_FIRE_RL_uart_receive_bit_cell_time_counter =
	     CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;

  // rule RL_uart_receive_buffer_shift
  assign CAN_FIRE_RL_uart_receive_buffer_shift =
	     uart_rRecvState == 3'd3 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_receive_buffer_shift =
	     CAN_FIRE_RL_uart_receive_buffer_shift ;

  // rule RL_uart_transmit_wait_for_start_command
  assign CAN_FIRE_RL_uart_transmit_wait_for_start_command =
	     uart_rXmitState == 3'd0 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_transmit_wait_for_start_command =
	     CAN_FIRE_RL_uart_transmit_wait_for_start_command ;

  // rule RL_get_result
  assign CAN_FIRE_RL_get_result =
	     rule30$RDY_getResult && uart_fifoXmit$FULL_N &&
	     transmit_state == 2'd2 &&
	     !op_mode &&
	     xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
	     !xmas_fsm_start_reg ;
  assign WILL_FIRE_RL_get_result = CAN_FIRE_RL_get_result ;

  // rule RL_uart_transmit_send_start_bit
  assign CAN_FIRE_RL_uart_transmit_send_start_bit =
	     uart_rXmitState == 3'd1 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_transmit_send_start_bit =
	     CAN_FIRE_RL_uart_transmit_send_start_bit ;

  // rule RL_uart_transmit_wait_1_bit_cell_time
  assign CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
	     uart_rXmitState == 3'd2 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
	     CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;

  // rule RL_uart_transmit_bit_counter
  assign CAN_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
  assign WILL_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;

  // rule RL_uart_transmit_shift_next_bit
  assign CAN_FIRE_RL_uart_transmit_shift_next_bit =
	     uart_rXmitState == 3'd3 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_transmit_shift_next_bit =
	     CAN_FIRE_RL_uart_transmit_shift_next_bit ;

  // rule RL_uart_transmit_buffer_load
  assign CAN_FIRE_RL_uart_transmit_buffer_load =
	     uart_fifoXmit$EMPTY_N && uart_pwXmitLoadBuffer$whas ;
  assign WILL_FIRE_RL_uart_transmit_buffer_load =
	     CAN_FIRE_RL_uart_transmit_buffer_load ;

  // rule RL_uart_transmit_buffer_shift
  assign CAN_FIRE_RL_uart_transmit_buffer_shift =
	     !uart_pwXmitLoadBuffer$whas &&
	     CAN_FIRE_RL_uart_transmit_shift_next_bit ;
  assign WILL_FIRE_RL_uart_transmit_buffer_shift =
	     CAN_FIRE_RL_uart_transmit_buffer_shift ;

  // rule RL_uart_transmit_send_parity_bit
  assign CAN_FIRE_RL_uart_transmit_send_parity_bit =
	     uart_rXmitState == 3'd7 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_transmit_send_parity_bit =
	     CAN_FIRE_RL_uart_transmit_send_parity_bit ;

  // rule RL_uart_transmit_send_stop_bit
  assign CAN_FIRE_RL_uart_transmit_send_stop_bit =
	     uart_rXmitState == 3'd4 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_transmit_send_stop_bit =
	     CAN_FIRE_RL_uart_transmit_send_stop_bit ;

  // rule RL_uart_transmit_send_stop_bit1_5
  assign CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 =
	     uart_rXmitState == 3'd5 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 =
	     CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 ;

  // rule RL_uart_transmit_send_stop_bit2
  assign CAN_FIRE_RL_uart_transmit_send_stop_bit2 =
	     uart_rXmitState == 3'd6 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_transmit_send_stop_bit2 =
	     CAN_FIRE_RL_uart_transmit_send_stop_bit2 ;

  // rule RL_uart_transmit_bit_cell_time_counter
  assign CAN_FIRE_RL_uart_transmit_bit_cell_time_counter =
	     CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
  assign WILL_FIRE_RL_uart_transmit_bit_cell_time_counter =
	     CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;

  // rule RL_uart_baudGen_baud_tick_count_wire
  assign CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
  assign WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;

  // rule RL_uart_baudGen_assert_2x_baud_tick
  assign CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
	     uart_baudGen_rBaudTickCounter$Q_OUT == 3'd0 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
	     CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick ;

  // rule RL_uart_baudGen_count_baudtick_16x
  assign CAN_FIRE_RL_uart_baudGen_count_baudtick_16x =
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign WILL_FIRE_RL_uart_baudGen_count_baudtick_16x =
	     CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;

  // rule RL_uart_fifoRecv__updateLevelCounter
  assign CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter =
	     CAN_FIRE_RL_uart_receive_stop_last_bit != uart_fifoRecv$EMPTY_N ;
  assign WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter =
	     CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter ;

  // rule RL_xmas_fsm_restart
  assign CAN_FIRE_RL_xmas_fsm_restart =
	     xmas_fsm_start_reg_1 && !xmas_fsm_state_fired ;
  assign WILL_FIRE_RL_xmas_fsm_restart = CAN_FIRE_RL_xmas_fsm_restart ;

  // rule RL_xmas_fsm_action_l43c32
  assign CAN_FIRE_RL_xmas_fsm_action_l43c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd1 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l43c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l43c32 ;

  // rule RL_xmas_fsm_action_l44c32
  assign CAN_FIRE_RL_xmas_fsm_action_l44c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd2 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l44c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l44c32 ;

  // rule RL_xmas_fsm_action_l45c32
  assign CAN_FIRE_RL_xmas_fsm_action_l45c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd3 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l45c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l45c32 ;

  // rule RL_xmas_fsm_action_l46c32
  assign CAN_FIRE_RL_xmas_fsm_action_l46c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd4 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l46c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l46c32 ;

  // rule RL_xmas_fsm_action_l47c32
  assign CAN_FIRE_RL_xmas_fsm_action_l47c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd5 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l47c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l47c32 ;

  // rule RL_xmas_fsm_action_l48c32
  assign CAN_FIRE_RL_xmas_fsm_action_l48c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd6 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l48c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l48c32 ;

  // rule RL_xmas_fsm_action_l49c32
  assign CAN_FIRE_RL_xmas_fsm_action_l49c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd7 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l49c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l49c32 ;

  // rule RL_xmas_fsm_action_l50c32
  assign CAN_FIRE_RL_xmas_fsm_action_l50c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd8 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l50c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l50c32 ;

  // rule RL_xmas_fsm_action_l51c32
  assign CAN_FIRE_RL_xmas_fsm_action_l51c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd9 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l51c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l51c32 ;

  // rule RL_xmas_fsm_action_l52c32
  assign CAN_FIRE_RL_xmas_fsm_action_l52c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd10 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l52c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l52c32 ;

  // rule RL_xmas_fsm_action_l53c32
  assign CAN_FIRE_RL_xmas_fsm_action_l53c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd11 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l53c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l53c32 ;

  // rule RL_xmas_fsm_action_l54c32
  assign CAN_FIRE_RL_xmas_fsm_action_l54c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd12 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l54c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l54c32 ;

  // rule RL_xmas_fsm_action_l55c32
  assign CAN_FIRE_RL_xmas_fsm_action_l55c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd13 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l55c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l55c32 ;

  // rule RL_xmas_fsm_action_l56c32
  assign CAN_FIRE_RL_xmas_fsm_action_l56c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd14 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l56c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l56c32 ;

  // rule RL_xmas_fsm_action_l57c32
  assign CAN_FIRE_RL_xmas_fsm_action_l57c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd15 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l57c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l57c32 ;

  // rule RL_xmas_fsm_action_l58c32
  assign CAN_FIRE_RL_xmas_fsm_action_l58c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd16 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l58c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l58c32 ;

  // rule RL_xmas_fsm_action_l59c32
  assign CAN_FIRE_RL_xmas_fsm_action_l59c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd17 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l59c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l59c32 ;

  // rule RL_xmas_fsm_action_l60c32
  assign CAN_FIRE_RL_xmas_fsm_action_l60c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd18 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l60c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l60c32 ;

  // rule RL_xmas_fsm_action_l61c32
  assign CAN_FIRE_RL_xmas_fsm_action_l61c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd19 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l61c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l61c32 ;

  // rule RL_xmas_fsm_action_l62c32
  assign CAN_FIRE_RL_xmas_fsm_action_l62c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd20 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l62c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l62c32 ;

  // rule RL_xmas_fsm_action_l63c32
  assign CAN_FIRE_RL_xmas_fsm_action_l63c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd21 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l63c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l63c32 ;

  // rule RL_xmas_fsm_action_l64c32
  assign CAN_FIRE_RL_xmas_fsm_action_l64c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd22 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l64c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l64c32 ;

  // rule RL_xmas_fsm_action_l65c32
  assign CAN_FIRE_RL_xmas_fsm_action_l65c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd23 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l65c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l65c32 ;

  // rule RL_xmas_fsm_action_l66c32
  assign CAN_FIRE_RL_xmas_fsm_action_l66c32 =
	     uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd24 ;
  assign WILL_FIRE_RL_xmas_fsm_action_l66c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l66c32 ;

  // rule __me_check_35
  assign CAN_FIRE___me_check_35 = 1'b1 ;
  assign WILL_FIRE___me_check_35 = 1'b1 ;

  // rule __me_check_36
  assign CAN_FIRE___me_check_36 = 1'b1 ;
  assign WILL_FIRE___me_check_36 = 1'b1 ;

  // rule __me_check_37
  assign CAN_FIRE___me_check_37 = 1'b1 ;
  assign WILL_FIRE___me_check_37 = 1'b1 ;

  // rule __me_check_38
  assign CAN_FIRE___me_check_38 = 1'b1 ;
  assign WILL_FIRE___me_check_38 = 1'b1 ;

  // rule __me_check_39
  assign CAN_FIRE___me_check_39 = 1'b1 ;
  assign WILL_FIRE___me_check_39 = 1'b1 ;

  // rule __me_check_40
  assign CAN_FIRE___me_check_40 = 1'b1 ;
  assign WILL_FIRE___me_check_40 = 1'b1 ;

  // rule __me_check_41
  assign CAN_FIRE___me_check_41 = 1'b1 ;
  assign WILL_FIRE___me_check_41 = 1'b1 ;

  // rule __me_check_43
  assign CAN_FIRE___me_check_43 = 1'b1 ;
  assign WILL_FIRE___me_check_43 = 1'b1 ;

  // rule __me_check_42
  assign CAN_FIRE___me_check_42 = 1'b1 ;
  assign WILL_FIRE___me_check_42 = 1'b1 ;

  // rule __me_check_44
  assign CAN_FIRE___me_check_44 = 1'b1 ;
  assign WILL_FIRE___me_check_44 = 1'b1 ;

  // rule __me_check_45
  assign CAN_FIRE___me_check_45 = 1'b1 ;
  assign WILL_FIRE___me_check_45 = 1'b1 ;

  // rule __me_check_46
  assign CAN_FIRE___me_check_46 = 1'b1 ;
  assign WILL_FIRE___me_check_46 = 1'b1 ;

  // rule __me_check_47
  assign CAN_FIRE___me_check_47 = 1'b1 ;
  assign WILL_FIRE___me_check_47 = 1'b1 ;

  // rule __me_check_48
  assign CAN_FIRE___me_check_48 = 1'b1 ;
  assign WILL_FIRE___me_check_48 = 1'b1 ;

  // rule __me_check_49
  assign CAN_FIRE___me_check_49 = 1'b1 ;
  assign WILL_FIRE___me_check_49 = 1'b1 ;

  // rule __me_check_51
  assign CAN_FIRE___me_check_51 = 1'b1 ;
  assign WILL_FIRE___me_check_51 = 1'b1 ;

  // rule __me_check_50
  assign CAN_FIRE___me_check_50 = 1'b1 ;
  assign WILL_FIRE___me_check_50 = 1'b1 ;

  // rule __me_check_52
  assign CAN_FIRE___me_check_52 = 1'b1 ;
  assign WILL_FIRE___me_check_52 = 1'b1 ;

  // rule __me_check_53
  assign CAN_FIRE___me_check_53 = 1'b1 ;
  assign WILL_FIRE___me_check_53 = 1'b1 ;

  // rule __me_check_54
  assign CAN_FIRE___me_check_54 = 1'b1 ;
  assign WILL_FIRE___me_check_54 = 1'b1 ;

  // rule __me_check_55
  assign CAN_FIRE___me_check_55 = 1'b1 ;
  assign WILL_FIRE___me_check_55 = 1'b1 ;

  // rule __me_check_56
  assign CAN_FIRE___me_check_56 = 1'b1 ;
  assign WILL_FIRE___me_check_56 = 1'b1 ;

  // rule __me_check_57
  assign CAN_FIRE___me_check_57 = 1'b1 ;
  assign WILL_FIRE___me_check_57 = 1'b1 ;

  // rule RL_xmas_fsm_idle_l40c27_1
  assign CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 =
	     !op_mode && xmas_fsm_state_mkFSMstate == 5'd25 ;
  assign WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 =
	     CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 ;

  // rule RL_xmas_fsm_fsm_start
  assign CAN_FIRE_RL_xmas_fsm_fsm_start =
	     (op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
	      op_mode && xmas_fsm_state_mkFSMstate == 5'd27 ||
	      !op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
	      !op_mode &&
	      (xmas_fsm_state_mkFSMstate == 5'd25 ||
	       xmas_fsm_state_mkFSMstate == 5'd27)) &&
	     (!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) &&
	     xmas_fsm_start_reg ;
  assign WILL_FIRE_RL_xmas_fsm_fsm_start = CAN_FIRE_RL_xmas_fsm_fsm_start ;

  // rule RL_xmas_fsm_action_l42c32
  assign CAN_FIRE_RL_xmas_fsm_action_l42c32 =
	     uart_fifoXmit$FULL_N &&
	     (op_mode && xmas_fsm_start_wire$whas &&
	      xmas_fsm_state_mkFSMstate == 5'd0 ||
	      op_mode && xmas_fsm_state_mkFSMstate == 5'd25) ;
  assign WILL_FIRE_RL_xmas_fsm_action_l42c32 =
	     CAN_FIRE_RL_xmas_fsm_action_l42c32 ;

  // rule __me_check_34
  assign CAN_FIRE___me_check_34 = 1'b1 ;
  assign WILL_FIRE___me_check_34 = 1'b1 ;

  // rule RL_uart_fifoXmit__updateLevelCounter
  assign CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter =
	     uart_fifoXmit_r_enq$whas !=
	     CAN_FIRE_RL_uart_transmit_buffer_load ;
  assign WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter =
	     CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter ;

  // rule RL_xmas_fsm_idle_l40c27
  assign CAN_FIRE_RL_xmas_fsm_idle_l40c27 =
	     !op_mode && xmas_fsm_start_wire$whas &&
	     xmas_fsm_state_mkFSMstate == 5'd0 ;
  assign WILL_FIRE_RL_xmas_fsm_idle_l40c27 =
	     CAN_FIRE_RL_xmas_fsm_idle_l40c27 ;

  // rule RL_xmas_fsm_start_reg__dreg_update
  assign CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
  assign WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;

  // rule RL_xmas_fsm_state_handle_abort
  assign CAN_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
  assign WILL_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;

  // rule RL_xmas_fsm_state_every
  assign CAN_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
  assign WILL_FIRE_RL_xmas_fsm_state_every = 1'd1 ;

  // rule RL_xmas_fsm_state_fired__dreg_update
  assign CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
  assign WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;

  // inputs to muxes for submodule ports
  assign MUX_transmit_state$write_1__SEL_1 =
	     WILL_FIRE_RL_get_result || EN_startup_value ;
  assign MUX_uart_fifoXmit$enq_1__SEL_2 =
	     WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l65c32 ;
  assign MUX_uart_fifoXmit$enq_1__SEL_3 =
	     WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l47c32 ;
  assign MUX_uart_fifoXmit$enq_1__SEL_11 =
	     WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l50c32 ;
  assign MUX_uart_fifoXmit$enq_1__SEL_15 =
	     WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l44c32 ;
  assign MUX_uart_fifoXmit$enq_1__SEL_16 =
	     WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l51c32 ;
  assign MUX_uart_fifoXmit$enq_1__SEL_17 =
	     WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l58c32 ;
  assign MUX_uart_rRecvState$write_1__SEL_6 =
	     WILL_FIRE_RL_uart_receive_parity_bit ||
	     WILL_FIRE_RL_uart_receive_sample_pin ;
  assign MUX_uart_rXmitDataOut$write_1__SEL_1 =
	     WILL_FIRE_RL_uart_transmit_shift_next_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
  assign MUX_uart_rXmitDataOut$write_1__SEL_2 =
	     WILL_FIRE_RL_uart_transmit_send_parity_bit ||
	     WILL_FIRE_RL_uart_transmit_send_start_bit ;
  assign MUX_uart_rXmitDataOut$write_1__SEL_3 =
	     WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
  assign MUX_xmas_fsm_start_reg$write_1__SEL_1 =
	     EN_operation_mode && operation_mode_arg == 8'hA5 ;
  assign MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 =
	     WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
	     WILL_FIRE_RL_xmas_fsm_idle_l40c27 ;
  assign MUX_uart_rRecvState$write_1__VAL_1 = uart_rRecvData ? 3'd0 : 3'd1 ;
  assign MUX_uart_rRecvState$write_1__VAL_2 =
	     (uart_rRecvCellCount == 4'h4) ?
	       (uart_rRecvData ? 3'd0 : 3'd2) :
	       3'd1 ;
  always@(uart_rRecvBitCount)
  begin
    case (uart_rRecvBitCount)
      4'd8, 4'd9, 4'd10: MUX_uart_rRecvState$write_1__VAL_3 = 3'd6;
      default: MUX_uart_rRecvState$write_1__VAL_3 = 3'd3;
    endcase
  end
  assign MUX_uart_rRecvState$write_1__VAL_4 = uart_rRecvData ? 3'd2 : 3'd0 ;
  assign MUX_uart_rXmitState$write_1__VAL_1 =
	     uart_fifoXmit$EMPTY_N ? 3'd1 : 3'd0 ;
  assign MUX_uart_rXmitState$write_1__VAL_2 =
	     (uart_rXmitCellCount == 4'hF) ? 3'd2 : 3'd1 ;
  assign MUX_uart_rXmitState$write_1__VAL_3 =
	     (uart_rXmitCellCount == 4'hF) ?
	       ((uart_rXmitBitCount == 4'd7) ? 3'd4 : 3'd3) :
	       3'd2 ;
  assign MUX_uart_rXmitState$write_1__VAL_4 =
	     (uart_rXmitCellCount == 4'hF) ? 3'd4 : 3'd7 ;
  assign MUX_uart_rXmitState$write_1__VAL_5 =
	     (uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd4 ;
  assign MUX_uart_rXmitState$write_1__VAL_6 =
	     (uart_rXmitCellCount == 4'h7) ? 3'd0 : 3'd5 ;
  assign MUX_uart_rXmitState$write_1__VAL_7 =
	     (uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd6 ;

  // inlined wires
  assign xmas_fsm_start_wire$whas =
	     WILL_FIRE_RL_xmas_fsm_fsm_start ||
	     WILL_FIRE_RL_xmas_fsm_restart ;
  assign uart_pwRecvCellCountReset$whas =
	     WILL_FIRE_RL_uart_receive_find_center_of_bit_cell &&
	     uart_rRecvCellCount == 4'h4 ||
	     WILL_FIRE_RL_uart_receive_stop_last_bit ||
	     WILL_FIRE_RL_uart_receive_stop_first_bit ||
	     WILL_FIRE_RL_uart_receive_parity_bit ||
	     WILL_FIRE_RL_uart_receive_sample_pin ||
	     WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
	     WILL_FIRE_RL_uart_receive_wait_for_start_bit ;
  assign uart_pwRecvResetBitCount$whas =
	     WILL_FIRE_RL_uart_receive_wait_for_start_bit && uart_rRecvData ;
  assign uart_pwRecvEnableBitCount$whas =
	     WILL_FIRE_RL_uart_receive_stop_first_bit ||
	     WILL_FIRE_RL_uart_receive_parity_bit ||
	     WILL_FIRE_RL_uart_receive_sample_pin ;
  assign uart_fifoXmit_r_enq$whas =
	     WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
  assign uart_pwXmitCellCountReset$whas =
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
	     uart_fifoXmit$EMPTY_N ||
	     _dor2uart_pwXmitCellCountReset$EN_wset &&
	     uart_rXmitCellCount == 4'hF ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 &&
	     uart_rXmitCellCount == 4'h7 ;
  assign uart_pwXmitEnableBitCount$whas =
	     WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time &&
	     uart_rXmitCellCount == 4'hF &&
	     uart_rXmitBitCount != 4'd7 ;
  assign uart_pwXmitLoadBuffer$whas =
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
	     uart_fifoXmit$EMPTY_N ;
  assign xmas_fsm_state_set_pw$whas =
	     WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
	     WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
	     WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l42c32 ;

  // register a
  assign a$D_IN = EN_startup_value ? startup_value_v : rule30$getResult ;
  assign a$EN = EN_startup_value || WILL_FIRE_RL_get_result ;

  // register op_mode
  assign op_mode$D_IN = 1'd1 ;
  assign op_mode$EN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;

  // register transmit_state
  assign transmit_state$D_IN =
	     MUX_transmit_state$write_1__SEL_1 ? 2'd1 : 2'd2 ;
  assign transmit_state$EN =
	     WILL_FIRE_RL_get_result || EN_startup_value ||
	     WILL_FIRE_RL_compute ;

  // register uart_rRecvBitCount
  assign uart_rRecvBitCount$D_IN =
	     uart_pwRecvResetBitCount$whas ? 4'd0 : x__h4689 ;
  assign uart_rRecvBitCount$EN =
	     uart_pwRecvResetBitCount$whas || uart_pwRecvEnableBitCount$whas ;

  // register uart_rRecvCellCount
  assign uart_rRecvCellCount$D_IN =
	     uart_pwRecvCellCountReset$whas ? 4'd0 : x__h2985 ;
  assign uart_rRecvCellCount$EN =
	     CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;

  // register uart_rRecvData
  assign uart_rRecvData$D_IN = txrx_SIN ;
  assign uart_rRecvData$EN = 1'd1 ;

  // register uart_rRecvState
  always@(WILL_FIRE_RL_uart_receive_wait_for_start_bit or
	  MUX_uart_rRecvState$write_1__VAL_1 or
	  WILL_FIRE_RL_uart_receive_find_center_of_bit_cell or
	  MUX_uart_rRecvState$write_1__VAL_2 or
	  WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample or
	  MUX_uart_rRecvState$write_1__VAL_3 or
	  WILL_FIRE_RL_uart_receive_stop_first_bit or
	  MUX_uart_rRecvState$write_1__VAL_4 or
	  WILL_FIRE_RL_uart_receive_stop_last_bit or
	  MUX_uart_rRecvState$write_1__SEL_6)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_uart_receive_wait_for_start_bit:
	  uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_1;
      WILL_FIRE_RL_uart_receive_find_center_of_bit_cell:
	  uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_2;
      WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample:
	  uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_3;
      WILL_FIRE_RL_uart_receive_stop_first_bit:
	  uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_4;
      WILL_FIRE_RL_uart_receive_stop_last_bit: uart_rRecvState$D_IN = 3'd0;
      MUX_uart_rRecvState$write_1__SEL_6: uart_rRecvState$D_IN = 3'd2;
      default: uart_rRecvState$D_IN = 3'b010 /* unspecified value */ ;
    endcase
  end
  assign uart_rRecvState$EN =
	     WILL_FIRE_RL_uart_receive_wait_for_start_bit ||
	     WILL_FIRE_RL_uart_receive_find_center_of_bit_cell ||
	     WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
	     WILL_FIRE_RL_uart_receive_stop_first_bit ||
	     WILL_FIRE_RL_uart_receive_stop_last_bit ||
	     WILL_FIRE_RL_uart_receive_parity_bit ||
	     WILL_FIRE_RL_uart_receive_sample_pin ;

  // register uart_rXmitBitCount
  assign uart_rXmitBitCount$D_IN =
	     CAN_FIRE_RL_uart_transmit_wait_for_start_command ?
	       4'd0 :
	       x__h6471 ;
  assign uart_rXmitBitCount$EN =
	     CAN_FIRE_RL_uart_transmit_wait_for_start_command ||
	     uart_pwXmitEnableBitCount$whas ;

  // register uart_rXmitCellCount
  assign uart_rXmitCellCount$D_IN =
	     uart_pwXmitCellCountReset$whas ? 4'd0 : x__h6445 ;
  assign uart_rXmitCellCount$EN =
	     CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;

  // register uart_rXmitDataOut
  always@(MUX_uart_rXmitDataOut$write_1__SEL_1 or
	  uart_vrXmitBuffer_0 or
	  MUX_uart_rXmitDataOut$write_1__SEL_2 or
	  MUX_uart_rXmitDataOut$write_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_uart_rXmitDataOut$write_1__SEL_1:
	  uart_rXmitDataOut$D_IN = uart_vrXmitBuffer_0;
      MUX_uart_rXmitDataOut$write_1__SEL_2: uart_rXmitDataOut$D_IN = 1'b0;
      MUX_uart_rXmitDataOut$write_1__SEL_3: uart_rXmitDataOut$D_IN = 1'b1;
      default: uart_rXmitDataOut$D_IN = 1'b0 /* unspecified value */ ;
    endcase
  end
  assign uart_rXmitDataOut$EN =
	     WILL_FIRE_RL_uart_transmit_shift_next_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
	     WILL_FIRE_RL_uart_transmit_send_parity_bit ||
	     WILL_FIRE_RL_uart_transmit_send_start_bit ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command ;

  // register uart_rXmitState
  always@(WILL_FIRE_RL_uart_transmit_wait_for_start_command or
	  MUX_uart_rXmitState$write_1__VAL_1 or
	  WILL_FIRE_RL_uart_transmit_send_start_bit or
	  MUX_uart_rXmitState$write_1__VAL_2 or
	  WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time or
	  MUX_uart_rXmitState$write_1__VAL_3 or
	  WILL_FIRE_RL_uart_transmit_send_parity_bit or
	  MUX_uart_rXmitState$write_1__VAL_4 or
	  WILL_FIRE_RL_uart_transmit_send_stop_bit or
	  MUX_uart_rXmitState$write_1__VAL_5 or
	  WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 or
	  MUX_uart_rXmitState$write_1__VAL_6 or
	  WILL_FIRE_RL_uart_transmit_send_stop_bit2 or
	  MUX_uart_rXmitState$write_1__VAL_7 or
	  WILL_FIRE_RL_uart_transmit_shift_next_bit)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_uart_transmit_wait_for_start_command:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_1;
      WILL_FIRE_RL_uart_transmit_send_start_bit:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_2;
      WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_3;
      WILL_FIRE_RL_uart_transmit_send_parity_bit:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_4;
      WILL_FIRE_RL_uart_transmit_send_stop_bit:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_5;
      WILL_FIRE_RL_uart_transmit_send_stop_bit1_5:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_6;
      WILL_FIRE_RL_uart_transmit_send_stop_bit2:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_7;
      WILL_FIRE_RL_uart_transmit_shift_next_bit: uart_rXmitState$D_IN = 3'd2;
      default: uart_rXmitState$D_IN = 3'b010 /* unspecified value */ ;
    endcase
  end
  assign uart_rXmitState$EN =
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command ||
	     WILL_FIRE_RL_uart_transmit_send_start_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
	     WILL_FIRE_RL_uart_transmit_send_parity_bit ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
	     WILL_FIRE_RL_uart_transmit_shift_next_bit ;

  // register uart_vrRecvBuffer_0
  assign uart_vrRecvBuffer_0$D_IN = uart_vrRecvBuffer_1 ;
  assign uart_vrRecvBuffer_0$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;

  // register uart_vrRecvBuffer_1
  assign uart_vrRecvBuffer_1$D_IN = uart_vrRecvBuffer_2 ;
  assign uart_vrRecvBuffer_1$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;

  // register uart_vrRecvBuffer_2
  assign uart_vrRecvBuffer_2$D_IN = uart_vrRecvBuffer_3 ;
  assign uart_vrRecvBuffer_2$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;

  // register uart_vrRecvBuffer_3
  assign uart_vrRecvBuffer_3$D_IN = uart_vrRecvBuffer_4 ;
  assign uart_vrRecvBuffer_3$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;

  // register uart_vrRecvBuffer_4
  assign uart_vrRecvBuffer_4$D_IN = uart_vrRecvBuffer_5 ;
  assign uart_vrRecvBuffer_4$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;

  // register uart_vrRecvBuffer_5
  assign uart_vrRecvBuffer_5$D_IN = uart_vrRecvBuffer_6 ;
  assign uart_vrRecvBuffer_5$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;

  // register uart_vrRecvBuffer_6
  assign uart_vrRecvBuffer_6$D_IN = uart_vrRecvBuffer_7 ;
  assign uart_vrRecvBuffer_6$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;

  // register uart_vrRecvBuffer_7
  assign uart_vrRecvBuffer_7$D_IN = uart_rRecvData ;
  assign uart_vrRecvBuffer_7$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;

  // register uart_vrXmitBuffer_0
  assign uart_vrXmitBuffer_0$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[0] :
	       uart_vrXmitBuffer_1 ;
  assign uart_vrXmitBuffer_0$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_1
  assign uart_vrXmitBuffer_1$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[1] :
	       uart_vrXmitBuffer_2 ;
  assign uart_vrXmitBuffer_1$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_2
  assign uart_vrXmitBuffer_2$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[2] :
	       uart_vrXmitBuffer_3 ;
  assign uart_vrXmitBuffer_2$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_3
  assign uart_vrXmitBuffer_3$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[3] :
	       uart_vrXmitBuffer_4 ;
  assign uart_vrXmitBuffer_3$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_4
  assign uart_vrXmitBuffer_4$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[4] :
	       uart_vrXmitBuffer_5 ;
  assign uart_vrXmitBuffer_4$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_5
  assign uart_vrXmitBuffer_5$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[5] :
	       uart_vrXmitBuffer_6 ;
  assign uart_vrXmitBuffer_5$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_6
  assign uart_vrXmitBuffer_6$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[6] :
	       uart_vrXmitBuffer_7 ;
  assign uart_vrXmitBuffer_6$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_7
  assign uart_vrXmitBuffer_7$D_IN =
	     !WILL_FIRE_RL_uart_transmit_buffer_load ||
	     uart_fifoXmit$D_OUT[7] ;
  assign uart_vrXmitBuffer_7$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register xmas_fsm_start_reg
  assign xmas_fsm_start_reg$D_IN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
  assign xmas_fsm_start_reg$EN =
	     EN_operation_mode && operation_mode_arg == 8'hA5 ||
	     WILL_FIRE_RL_xmas_fsm_fsm_start ;

  // register xmas_fsm_start_reg_1
  assign xmas_fsm_start_reg_1$D_IN = xmas_fsm_start_wire$whas ;
  assign xmas_fsm_start_reg_1$EN = 1'd1 ;

  // register xmas_fsm_state_fired
  assign xmas_fsm_state_fired$D_IN = xmas_fsm_state_set_pw$whas ;
  assign xmas_fsm_state_fired$EN = 1'd1 ;

  // register xmas_fsm_state_mkFSMstate
  always@(MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 or
	  WILL_FIRE_RL_xmas_fsm_action_l42c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l43c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l44c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l45c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l46c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l47c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l48c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l49c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l50c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l51c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l52c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l53c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l54c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l55c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l56c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l57c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l58c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l59c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l60c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l61c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l62c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l63c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l64c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l65c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l66c32)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd0;
      WILL_FIRE_RL_xmas_fsm_action_l42c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd1;
      WILL_FIRE_RL_xmas_fsm_action_l43c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd2;
      WILL_FIRE_RL_xmas_fsm_action_l44c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd3;
      WILL_FIRE_RL_xmas_fsm_action_l45c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd4;
      WILL_FIRE_RL_xmas_fsm_action_l46c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd5;
      WILL_FIRE_RL_xmas_fsm_action_l47c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd6;
      WILL_FIRE_RL_xmas_fsm_action_l48c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd7;
      WILL_FIRE_RL_xmas_fsm_action_l49c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd8;
      WILL_FIRE_RL_xmas_fsm_action_l50c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd9;
      WILL_FIRE_RL_xmas_fsm_action_l51c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd10;
      WILL_FIRE_RL_xmas_fsm_action_l52c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd11;
      WILL_FIRE_RL_xmas_fsm_action_l53c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd12;
      WILL_FIRE_RL_xmas_fsm_action_l54c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd13;
      WILL_FIRE_RL_xmas_fsm_action_l55c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd14;
      WILL_FIRE_RL_xmas_fsm_action_l56c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd15;
      WILL_FIRE_RL_xmas_fsm_action_l57c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd16;
      WILL_FIRE_RL_xmas_fsm_action_l58c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd17;
      WILL_FIRE_RL_xmas_fsm_action_l59c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd18;
      WILL_FIRE_RL_xmas_fsm_action_l60c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd19;
      WILL_FIRE_RL_xmas_fsm_action_l61c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd20;
      WILL_FIRE_RL_xmas_fsm_action_l62c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd21;
      WILL_FIRE_RL_xmas_fsm_action_l63c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd22;
      WILL_FIRE_RL_xmas_fsm_action_l64c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd23;
      WILL_FIRE_RL_xmas_fsm_action_l65c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd24;
      WILL_FIRE_RL_xmas_fsm_action_l66c32:
	  xmas_fsm_state_mkFSMstate$D_IN = 5'd25;
      default: xmas_fsm_state_mkFSMstate$D_IN =
		   5'b01010 /* unspecified value */ ;
    endcase
  end
  assign xmas_fsm_state_mkFSMstate$EN =
	     WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
	     WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
	     WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l66c32 ;

  // submodule rule30
  assign rule30$start_a = a ;
  assign rule30$EN_start = CAN_FIRE_RL_compute ;
  assign rule30$EN_getResult = CAN_FIRE_RL_get_result ;

  // submodule uart_baudGen_rBaudCounter
  assign uart_baudGen_rBaudCounter$DATA_A = 16'd1 ;
  assign uart_baudGen_rBaudCounter$DATA_B = 16'h0 ;
  assign uart_baudGen_rBaudCounter$DATA_C = 16'h0 ;
  assign uart_baudGen_rBaudCounter$DATA_F = 16'd0 ;
  assign uart_baudGen_rBaudCounter$ADDA =
	     uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
  assign uart_baudGen_rBaudCounter$ADDB = 1'b0 ;
  assign uart_baudGen_rBaudCounter$SETC = 1'b0 ;
  assign uart_baudGen_rBaudCounter$SETF =
	     CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;

  // submodule uart_baudGen_rBaudTickCounter
  assign uart_baudGen_rBaudTickCounter$DATA_A = 3'd1 ;
  assign uart_baudGen_rBaudTickCounter$DATA_B = 3'h0 ;
  assign uart_baudGen_rBaudTickCounter$DATA_C = 3'h0 ;
  assign uart_baudGen_rBaudTickCounter$DATA_F = 3'h0 ;
  assign uart_baudGen_rBaudTickCounter$ADDA =
	     CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
  assign uart_baudGen_rBaudTickCounter$ADDB = 1'b0 ;
  assign uart_baudGen_rBaudTickCounter$SETC = 1'b0 ;
  assign uart_baudGen_rBaudTickCounter$SETF = 1'b0 ;

  // submodule uart_fifoRecv
  assign uart_fifoRecv$D_IN =
	     { uart_vrRecvBuffer_7,
	       uart_vrRecvBuffer_6,
	       uart_vrRecvBuffer_5,
	       uart_vrRecvBuffer_4,
	       uart_vrRecvBuffer_3,
	       uart_vrRecvBuffer_2,
	       uart_vrRecvBuffer_1,
	       uart_vrRecvBuffer_0 } ;
  assign uart_fifoRecv$ENQ = CAN_FIRE_RL_uart_receive_stop_last_bit ;
  assign uart_fifoRecv$DEQ = uart_fifoRecv$EMPTY_N ;
  assign uart_fifoRecv$CLR = 1'b0 ;

  // submodule uart_fifoXmit
  always@(WILL_FIRE_RL_get_result or
	  rule30$getResult or
	  MUX_uart_fifoXmit$enq_1__SEL_2 or
	  MUX_uart_fifoXmit$enq_1__SEL_3 or
	  WILL_FIRE_RL_xmas_fsm_action_l64c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l53c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l54c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l55c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l42c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l57c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l48c32 or
	  MUX_uart_fifoXmit$enq_1__SEL_11 or
	  WILL_FIRE_RL_xmas_fsm_action_l43c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l49c32 or
	  WILL_FIRE_RL_xmas_fsm_action_l62c32 or
	  MUX_uart_fifoXmit$enq_1__SEL_15 or
	  MUX_uart_fifoXmit$enq_1__SEL_16 or
	  MUX_uart_fifoXmit$enq_1__SEL_17 or
	  WILL_FIRE_RL_xmas_fsm_action_l46c32)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_get_result: uart_fifoXmit$D_IN = rule30$getResult;
      MUX_uart_fifoXmit$enq_1__SEL_2: uart_fifoXmit$D_IN = 8'h09;
      MUX_uart_fifoXmit$enq_1__SEL_3: uart_fifoXmit$D_IN = 8'h20;
      WILL_FIRE_RL_xmas_fsm_action_l64c32: uart_fifoXmit$D_IN = 8'h21;
      WILL_FIRE_RL_xmas_fsm_action_l53c32: uart_fifoXmit$D_IN = 8'h27;
      WILL_FIRE_RL_xmas_fsm_action_l54c32: uart_fifoXmit$D_IN = 8'h32;
      WILL_FIRE_RL_xmas_fsm_action_l55c32: uart_fifoXmit$D_IN = 8'h34;
      WILL_FIRE_RL_xmas_fsm_action_l42c32: uart_fifoXmit$D_IN = 8'h4D;
      WILL_FIRE_RL_xmas_fsm_action_l57c32: uart_fifoXmit$D_IN = 8'h53;
      WILL_FIRE_RL_xmas_fsm_action_l48c32: uart_fifoXmit$D_IN = 8'h58;
      MUX_uart_fifoXmit$enq_1__SEL_11: uart_fifoXmit$D_IN = 8'h61;
      WILL_FIRE_RL_xmas_fsm_action_l43c32: uart_fifoXmit$D_IN = 8'h65;
      WILL_FIRE_RL_xmas_fsm_action_l49c32: uart_fifoXmit$D_IN = 8'h6D;
      WILL_FIRE_RL_xmas_fsm_action_l62c32: uart_fifoXmit$D_IN = 8'h6F;
      MUX_uart_fifoXmit$enq_1__SEL_15: uart_fifoXmit$D_IN = 8'h72;
      MUX_uart_fifoXmit$enq_1__SEL_16: uart_fifoXmit$D_IN = 8'h73;
      MUX_uart_fifoXmit$enq_1__SEL_17: uart_fifoXmit$D_IN = 8'h74;
      WILL_FIRE_RL_xmas_fsm_action_l46c32: uart_fifoXmit$D_IN = 8'h79;
      default: uart_fifoXmit$D_IN = 8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign uart_fifoXmit$ENQ =
	     WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
	     WILL_FIRE_RL_xmas_fsm_action_l46c32 ;
  assign uart_fifoXmit$DEQ = CAN_FIRE_RL_uart_transmit_buffer_load ;
  assign uart_fifoXmit$CLR = 1'b0 ;

  // remaining internal signals
  assign _dor2uart_pwXmitCellCountReset$EN_wset =
	     WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit ||
	     WILL_FIRE_RL_uart_transmit_send_parity_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
	     WILL_FIRE_RL_uart_transmit_send_start_bit ;
  assign uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 =
	     uart_baudGen_rBaudCounter$Q_OUT + 16'd1 < 16'd27 ;
  assign x__h2985 = uart_rRecvCellCount + 4'd1 ;
  assign x__h4689 = uart_rRecvBitCount + 4'd1 ;
  assign x__h6445 = uart_rXmitCellCount + 4'd1 ;
  assign x__h6471 = uart_rXmitBitCount + 4'd1 ;
  assign xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 =
	     (xmas_fsm_state_mkFSMstate == 5'd0 ||
	      xmas_fsm_state_mkFSMstate == 5'd25 ||
	      xmas_fsm_state_mkFSMstate == 5'd27) &&
	     (!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        a <= `BSV_ASSIGNMENT_DELAY 8'b0;
	op_mode <= `BSV_ASSIGNMENT_DELAY 1'd0;
	transmit_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
	uart_rRecvData <= `BSV_ASSIGNMENT_DELAY 1'd1;
	xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
	xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 5'd0;
      end
    else
      begin
        if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN;
	if (op_mode$EN) op_mode <= `BSV_ASSIGNMENT_DELAY op_mode$D_IN;
	if (transmit_state$EN)
	  transmit_state <= `BSV_ASSIGNMENT_DELAY transmit_state$D_IN;
	if (uart_rRecvData$EN)
	  uart_rRecvData <= `BSV_ASSIGNMENT_DELAY uart_rRecvData$D_IN;
	if (xmas_fsm_start_reg$EN)
	  xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY xmas_fsm_start_reg$D_IN;
	if (xmas_fsm_start_reg_1$EN)
	  xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
	      xmas_fsm_start_reg_1$D_IN;
	if (xmas_fsm_state_fired$EN)
	  xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY
	      xmas_fsm_state_fired$D_IN;
	if (xmas_fsm_state_mkFSMstate$EN)
	  xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
	      xmas_fsm_state_mkFSMstate$D_IN;
      end
    if (uart_vrRecvBuffer_0$EN)
      uart_vrRecvBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_0$D_IN;
    if (uart_vrRecvBuffer_1$EN)
      uart_vrRecvBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_1$D_IN;
    if (uart_vrRecvBuffer_2$EN)
      uart_vrRecvBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_2$D_IN;
    if (uart_vrRecvBuffer_3$EN)
      uart_vrRecvBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_3$D_IN;
    if (uart_vrRecvBuffer_4$EN)
      uart_vrRecvBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_4$D_IN;
    if (uart_vrRecvBuffer_5$EN)
      uart_vrRecvBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_5$D_IN;
    if (uart_vrRecvBuffer_6$EN)
      uart_vrRecvBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_6$D_IN;
    if (uart_vrRecvBuffer_7$EN)
      uart_vrRecvBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_7$D_IN;
    if (uart_vrXmitBuffer_0$EN)
      uart_vrXmitBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_0$D_IN;
    if (uart_vrXmitBuffer_1$EN)
      uart_vrXmitBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_1$D_IN;
    if (uart_vrXmitBuffer_2$EN)
      uart_vrXmitBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_2$D_IN;
    if (uart_vrXmitBuffer_3$EN)
      uart_vrXmitBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_3$D_IN;
    if (uart_vrXmitBuffer_4$EN)
      uart_vrXmitBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_4$D_IN;
    if (uart_vrXmitBuffer_5$EN)
      uart_vrXmitBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_5$D_IN;
    if (uart_vrXmitBuffer_6$EN)
      uart_vrXmitBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_6$D_IN;
    if (uart_vrXmitBuffer_7$EN)
      uart_vrXmitBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_7$D_IN;
  end

  always@(posedge CLK or `BSV_RESET_EDGE RST_N)
  if (RST_N == `BSV_RESET_VALUE)
    begin
      uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
      uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
      uart_rRecvState <= `BSV_ASSIGNMENT_DELAY 3'd0;
      uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
      uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
      uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY 1'd1;
      uart_rXmitState <= `BSV_ASSIGNMENT_DELAY 3'd0;
    end
  else
    begin
      if (uart_rRecvBitCount$EN)
	uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvBitCount$D_IN;
      if (uart_rRecvCellCount$EN)
	uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvCellCount$D_IN;
      if (uart_rRecvState$EN)
	uart_rRecvState <= `BSV_ASSIGNMENT_DELAY uart_rRecvState$D_IN;
      if (uart_rXmitBitCount$EN)
	uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitBitCount$D_IN;
      if (uart_rXmitCellCount$EN)
	uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitCellCount$D_IN;
      if (uart_rXmitDataOut$EN)
	uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY uart_rXmitDataOut$D_IN;
      if (uart_rXmitState$EN)
	uart_rXmitState <= `BSV_ASSIGNMENT_DELAY uart_rXmitState$D_IN;
    end


  // handling of system tasks

endmodule  // mkRule30Driver



//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:51 EDT 2024
//
//
// Ports:
// Name                         I/O  size props
// RDY_start                      O     1
// getResult                      O     8 reg
// RDY_getResult                  O     1
// CLK                            I     1 clock
// RST_N                          I     1 reset
// start_a                        I     8
// EN_start                       I     1
// EN_getResult                   I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkRule30(CLK,
		RST_N,

		start_a,
		EN_start,
		RDY_start,

		EN_getResult,
		getResult,
		RDY_getResult);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule

  // mkRule30




`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif


`ifdef BSV_ASYNC_RESET
 `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
 `define BSV_ARESET_EDGE_META
`endif


// N -bit counter with load, set and 2 increment
module Counter(CLK,
               RST,
               Q_OUT,
               DATA_A, ADDA,
               DATA_B, ADDB,
               DATA_C, SETC,
               DATA_F, SETF);

   parameter width = 1;
   parameter init = 0;

   input                 CLK;
   input                 RST;
   input [width - 1 : 0] DATA_A;
   input                 ADDA;
   input [width - 1 : 0] DATA_B;
   input                 ADDB;
   input [width - 1 : 0] DATA_C;
   input                 SETC;
   input [width - 1 : 0] DATA_F;
   input                 SETF;

   output [width - 1 : 0] Q_OUT;



   reg [width - 1 : 0]    q_state ;

   assign                 Q_OUT = q_state ;

   always@(posedge CLK `BSV_ARESET_EDGE_META) begin
    if (RST == `BSV_RESET_VALUE)
      q_state  <= `BSV_ASSIGNMENT_DELAY init;
    else
      begin
         if ( SETF )
           q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
         else
           q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
      end // else: !if(RST == `BSV_RESET_VALUE)
   end // always@ (posedge CLK)

`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
   // synopsys translate_off
   initial begin
      q_state = {((width + 1)/2){2'b10}} ;
   end
   // synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS

endmodule



`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

`ifdef BSV_ASYNC_RESET
 `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
 `define BSV_ARESET_EDGE_META
`endif

`ifdef BSV_RESET_FIFO_HEAD
 `define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
 `define BSV_ARESET_EDGE_HEAD
`endif

`ifdef BSV_RESET_FIFO_ARRAY
 `define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
 `define BSV_ARESET_EDGE_ARRAY
`endif


// Sized fifo.  Model has output register which improves timing
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
   parameter               p1width = 1; // data width
   parameter               p2depth = 3;
   parameter               p3cntr_width = 1; // log(p2depth-1)
   // The -1 is allowed since this model has a fast output register
   parameter               guarded = 1'b1;
   localparam              p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;

   input                   CLK;
   input                   RST;
   input                   CLR;
   input [p1width - 1 : 0] D_IN;
   input                   ENQ;
   input                   DEQ;

   output                  FULL_N;
   output                  EMPTY_N;
   output [p1width - 1 : 0] D_OUT;

   reg                      not_ring_full;
   reg                      ring_empty;

   reg [p3cntr_width-1 : 0] head;
   wire [p3cntr_width-1 : 0] next_head;

   reg [p3cntr_width-1 : 0]  tail;
   wire [p3cntr_width-1 : 0] next_tail;

   // if the depth is too small, don't create an ill-sized array;
   // instead, make a 1-sized array and let the initial block report an error
   reg [p1width - 1 : 0]     arr[0: p2depth2];

   reg [p1width - 1 : 0]     D_OUT;
   reg                       hasodata;

   wire [p3cntr_width-1:0]   depthLess2 = p2depth2[p3cntr_width-1:0] ;

   wire [p3cntr_width-1 : 0] incr_tail;
   wire [p3cntr_width-1 : 0] incr_head;

   assign                    incr_tail = tail + 1'b1 ;
   assign                    incr_head = head + 1'b1 ;

   assign    next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
   assign    next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;

   assign    EMPTY_N = hasodata;
   assign    FULL_N  = not_ring_full;

`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
   // synopsys translate_off
   initial
     begin : initial_block
        integer   i;
        D_OUT         = {((p1width + 1)/2){2'b10}} ;

        ring_empty    = 1'b1;
        not_ring_full = 1'b1;
        hasodata      = 1'b0;
        head          = {p3cntr_width {1'b0}} ;
        tail          = {p3cntr_width {1'b0}} ;

        for (i = 0; i <= p2depth2; i = i + 1)
          begin
             arr[i]   = D_OUT ;
          end
     end
   // synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS


   always @(posedge CLK `BSV_ARESET_EDGE_META)
     begin
        if (RST == `BSV_RESET_VALUE)
          begin
             head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
             tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
             ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
             not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
             hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
          end // if (RST == `BSV_RESET_VALUE)
        else
         begin

             casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
               // Clear operation
               5'b1????: begin
                  head          <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
                  tail          <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
                  ring_empty    <= `BSV_ASSIGNMENT_DELAY 1'b1;
                  not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
                  hasodata      <= `BSV_ASSIGNMENT_DELAY 1'b0;
               end
               // -----------------------
               // DEQ && ENQ case -- change head and tail if added to ring
               5'b011?0: begin
                  tail          <= `BSV_ASSIGNMENT_DELAY next_tail;
                  head          <= `BSV_ASSIGNMENT_DELAY next_head;
               end
               // -----------------------
               // DEQ only and NO data is in ring
               5'b010?1: begin
                  hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
               end
               // DEQ only and data is in ring (move the head pointer)
               5'b010?0: begin
                  head          <= `BSV_ASSIGNMENT_DELAY next_head;
                  not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
                  ring_empty    <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
               end
               // -----------------------
               // ENQ only when empty
               5'b0010?: begin
                  hasodata      <= `BSV_ASSIGNMENT_DELAY 1'b1;
                  end
               // ENQ only when not empty
               5'b0011?: begin
                  if ( not_ring_full ) // Drop this test to save redundant test
                    // but be warnned that with test fifo overflow causes loss of new data
                    // while without test fifo drops all but head entry! (pointer overflow)
                   begin
                      tail          <= `BSV_ASSIGNMENT_DELAY next_tail;
                      ring_empty    <= `BSV_ASSIGNMENT_DELAY 1'b0;
                      not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
                   end
               end
             endcase
         end // else: !if(RST == `BSV_RESET_VALUE)
     end // always @ (posedge CLK)

   // Update the fast data out register
   always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
     begin
`ifdef  BSV_RESET_FIFO_HEAD
        if (RST == `BSV_RESET_VALUE)
          begin
             D_OUT    <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
          end // if (RST == `BSV_RESET_VALUE)
        else
`endif
        begin
             casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
               // DEQ && ENQ cases
               5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
               5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
               // DEQ only and data is in ring
               5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
               // ENQ only when empty
               5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
             endcase
          end // else: !if(RST == `BSV_RESET_VALUE)
     end // always @ (posedge CLK)

   // Update the memory array  reset is OFF
   always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
     begin: array
`ifdef BSV_RESET_FIFO_ARRAY
        if (RST == `BSV_RESET_VALUE)
          begin: rst_array
             integer i;
             for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
               begin
                   arr[i]  <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
               end
          end // if (RST == `BSV_RESET_VALUE)
        else
`endif
         begin
            if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
              begin
                 arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
              end
         end // else: !if(RST == `BSV_RESET_VALUE)
     end // always @ (posedge CLK)

   // synopsys translate_off
   always@(posedge CLK)
     begin: error_checks
        reg deqerror, enqerror ;

        deqerror =  0;
        enqerror = 0;
        if (RST == ! `BSV_RESET_VALUE)
           begin
              if ( ! EMPTY_N && DEQ )
                begin
                   deqerror = 1 ;
                   $display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
                end
              if ( ! FULL_N && ENQ && (!DEQ || guarded) )
                begin
                   enqerror =  1 ;
                   $display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
                end
           end
     end // block: error_checks
   // synopsys translate_on

   // synopsys translate_off
   // Some assertions about parameter values
   initial
     begin : parameter_assertions
        integer ok ;
        ok = 1 ;

        if ( p2depth <= 1)
          begin
             ok = 0;
             $display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
          end

        if ( p3cntr_width <= 0 )
          begin
             ok = 0;
             $display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
          end

        if ( ok == 0 ) $finish ;

      end // initial begin
   // synopsys translate_on

endmodule



`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

`ifdef BSV_ASYNC_RESET
 `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
 `define BSV_ARESET_EDGE_META
`endif

`ifdef BSV_RESET_FIFO_HEAD
 `define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
 `define BSV_ARESET_EDGE_HEAD
`endif

// Depth 1 FIFO
module FIFO1(CLK,
             RST,
             D_IN,
             ENQ,
             FULL_N,
             D_OUT,
             DEQ,
             EMPTY_N,
             CLR
             );

   parameter width = 1;
   parameter guarded = 1'b1;
   input                  CLK;
   input                  RST;
   input [width - 1 : 0]  D_IN;
   input                  ENQ;
   input                  DEQ;
   input                  CLR ;

   output                 FULL_N;
   output [width - 1 : 0] D_OUT;
   output                 EMPTY_N;

   reg [width - 1 : 0]    D_OUT;
   reg                    empty_reg ;


   assign                 EMPTY_N = empty_reg ;


`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
   // synopsys translate_off
   initial
     begin
        D_OUT   = {((width + 1)/2) {2'b10}} ;
        empty_reg = 1'b0 ;
     end // initial begin
   // synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS


   assign FULL_N = !empty_reg;

   always@(posedge CLK `BSV_ARESET_EDGE_META)
     begin
        if (RST == `BSV_RESET_VALUE)
          begin
             empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
          end // if (RST == `BSV_RESET_VALUE)
        else
           begin
              if (CLR)
                begin
                   empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
                end // if (CLR)
              else if (ENQ)
                begin
                   empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
                end // if (ENQ)
              else if (DEQ)
                begin
                   empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
                end // if (DEQ)
           end // else: !if(RST == `BSV_RESET_VALUE)
     end // always@ (posedge CLK or `BSV_RESET_EDGE RST)

   always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
     begin
`ifdef BSV_RESET_FIFO_HEAD
        if (RST == `BSV_RESET_VALUE)
          begin
             D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
          end
        else
`endif
           begin
              if (ENQ)
                D_OUT     <= `BSV_ASSIGNMENT_DELAY D_IN;
           end // else: !if(RST == `BSV_RESET_VALUE)
     end // always@ (posedge CLK or `BSV_RESET_EDGE RST)

   // synopsys translate_off
   always@(posedge CLK)
     begin: error_checks
        reg deqerror, enqerror ;

        deqerror =  0;
        enqerror = 0;
        if (RST == ! `BSV_RESET_VALUE)
           begin
              if ( ! empty_reg && DEQ )
                begin
                   deqerror = 1 ;
                   $display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
                end
              if ( ! FULL_N && ENQ && (!DEQ || guarded) )
                begin
                   enqerror =  1 ;
                   $display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
                end
           end // if (RST == ! `BSV_RESET_VALUE)
     end
   // synopsys translate_on

endmodule



Reference solution:
rtl/generated.v:   input  CLK;
  input  RST_N;

  // action method start
  input  [7 : 0] start_a;
  input  EN_start;
  output RDY_start;

  // actionvalue method getResult
  input  EN_getResult;
  output [7 : 0] getResult;
  output RDY_getResult;

  // signals for module outputs
  wire [7 : 0] getResult;
  wire RDY_getResult, RDY_start;

  // register busy_flag
  reg busy_flag;
  wire busy_flag$D_IN, busy_flag$EN;

  // register r30
  reg [7 : 0] r30;
  wire [7 : 0] r30$D_IN;
  wire r30$EN;

  // register step_complete
  reg step_complete;
  wire step_complete$D_IN, step_complete$EN;

  // register x
  reg [55 : 0] x;
  wire [55 : 0] x$D_IN;
  wire x$EN;

  // rule scheduling signals
  wire CAN_FIRE_RL_stepper,
       CAN_FIRE_getResult,
       CAN_FIRE_start,
       WILL_FIRE_RL_stepper,
       WILL_FIRE_getResult,
       WILL_FIRE_start;

  // inputs to muxes for submodule ports
  wire [55 : 0] MUX_x$write_1__VAL_1, MUX_x$write_1__VAL_2;

  // remaining internal signals
  wire [51 : 0] r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146;
  wire [47 : 0] r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144;
  wire [43 : 0] r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142;
  wire [39 : 0] r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140;
  wire [35 : 0] r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138;
  wire [31 : 0] r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136;
  wire [27 : 0] r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134;
  wire [23 : 0] r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132;
  wire [19 : 0] r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130;
  wire [15 : 0] r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128;
  wire [11 : 0] r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126;
  wire [7 : 0] r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124;
  wire [3 : 0] r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122;
  wire [2 : 0] b0__h167, b55__h222;

  // action method start
  assign RDY_start = !busy_flag ;
  assign CAN_FIRE_start = !busy_flag ;
  assign WILL_FIRE_start = EN_start ;

  // actionvalue method getResult
  assign getResult = x[31:24] ;
  assign RDY_getResult = busy_flag && step_complete ;
  assign CAN_FIRE_getResult = busy_flag && step_complete ;
  assign WILL_FIRE_getResult = EN_getResult ;

  // rule RL_stepper
  assign CAN_FIRE_RL_stepper = busy_flag && !step_complete ;
  assign WILL_FIRE_RL_stepper = CAN_FIRE_RL_stepper ;

  // inputs to muxes for submodule ports
  assign MUX_x$write_1__VAL_1 =
	     { r30[b55__h222],
	       r30[x[55:53]],
	       r30[x[54:52]],
	       r30[x[53:51]],
	       r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 } ;
  assign MUX_x$write_1__VAL_2 = { x[55:32], start_a, x[23:0] } ;

  // register busy_flag
  assign busy_flag$D_IN = !EN_getResult ;
  assign busy_flag$EN = EN_getResult || EN_start ;

  // register r30
  assign r30$D_IN = 8'h0 ;
  assign r30$EN = 1'b0 ;

  // register step_complete
  assign step_complete$D_IN = !EN_start ;
  assign step_complete$EN = EN_start || WILL_FIRE_RL_stepper ;

  // register x
  assign x$D_IN =
	     WILL_FIRE_RL_stepper ?
	       MUX_x$write_1__VAL_1 :
	       MUX_x$write_1__VAL_2 ;
  assign x$EN = WILL_FIRE_RL_stepper || EN_start ;

  // remaining internal signals
  assign b0__h167 = { x[1:0], 1'b0 } ;
  assign b55__h222 = { 1'b0, x[55:54] } ;
  assign r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 =
	     { r30[x[12:10]],
	       r30[x[11:9]],
	       r30[x[10:8]],
	       r30[x[9:7]],
	       r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 } ;
  assign r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 =
	     { r30[x[16:14]],
	       r30[x[15:13]],
	       r30[x[14:12]],
	       r30[x[13:11]],
	       r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 } ;
  assign r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 =
	     { r30[x[20:18]],
	       r30[x[19:17]],
	       r30[x[18:16]],
	       r30[x[17:15]],
	       r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 } ;
  assign r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 =
	     { r30[x[24:22]],
	       r30[x[23:21]],
	       r30[x[22:20]],
	       r30[x[21:19]],
	       r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 } ;
  assign r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 =
	     { r30[x[28:26]],
	       r30[x[27:25]],
	       r30[x[26:24]],
	       r30[x[25:23]],
	       r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 } ;
  assign r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 =
	     { r30[x[32:30]],
	       r30[x[31:29]],
	       r30[x[30:28]],
	       r30[x[29:27]],
	       r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 } ;
  assign r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 =
	     { r30[x[36:34]],
	       r30[x[35:33]],
	       r30[x[34:32]],
	       r30[x[33:31]],
	       r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 } ;
  assign r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 =
	     { r30[x[40:38]],
	       r30[x[39:37]],
	       r30[x[38:36]],
	       r30[x[37:35]],
	       r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 } ;
  assign r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 =
	     { r30[x[44:42]],
	       r30[x[43:41]],
	       r30[x[42:40]],
	       r30[x[41:39]],
	       r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 } ;
  assign r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 =
	     { r30[x[48:46]],
	       r30[x[47:45]],
	       r30[x[46:44]],
	       r30[x[45:43]],
	       r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 } ;
  assign r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 =
	     { r30[x[4:2]], r30[x[3:1]], r30[x[2:0]], r30[b0__h167] } ;
  assign r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 =
	     { r30[x[52:50]],
	       r30[x[51:49]],
	       r30[x[50:48]],
	       r30[x[49:47]],
	       r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 } ;
  assign r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 =
	     { r30[x[8:6]],
	       r30[x[7:5]],
	       r30[x[6:4]],
	       r30[x[5:3]],
	       r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 } ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        busy_flag <= `BSV_ASSIGNMENT_DELAY 1'd0;
	r30 <= `BSV_ASSIGNMENT_DELAY 8'd30;
	step_complete <= `BSV_ASSIGNMENT_DELAY 1'd0;
	x <= `BSV_ASSIGNMENT_DELAY 56'd0;
      end
    else
      begin
        if (busy_flag$EN) busy_flag <= `BSV_ASSIGNMENT_DELAY busy_flag$D_IN;
	if (r30$EN) r30 <= `BSV_ASSIGNMENT_DELAY r30$D_IN;
	if (step_complete$EN)
	  step_complete <= `BSV_ASSIGNMENT_DELAY step_complete$D_IN;
	if (x$EN) x <= `BSV_ASSIGNMENT_DELAY x$D_IN;
      end
  end