You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Your Name
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_javibajocero_top (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

    // --- UART Baud Generators ---
    wire baud_tick_tx;
    wire baud_tick_rx;

    baud_generator #(.BAUD_DIV(5208)) baud_gen_tx ( // 50MHz / 9600
        .clk(clk),
        .rst_n(rst_n),
        .baud_tick(baud_tick_tx)
    );

    baud_generator #(.BAUD_DIV(651)) baud_gen_rx ( // 50MHz / (9600 * 8)
        .clk(clk),
        .rst_n(rst_n),
        .baud_tick(baud_tick_rx)
    );

    // --- UART RX ---
    wire [7:0] rx_data; //one byte just received via uart
    wire       rx_valid;//flag triggering when succesfull byte is received


    uart_rx uart_rx_inst (
        .clk(clk),
        .rst_n(rst_n),
        .baud_tick(baud_tick_rx),
        .rx(ui_in[0]),
        .data(rx_data),
        .byte_received(rx_valid)
    );

    // --- Buffer Comparator (detect "MARCO") ---
    wire trigger_send;

    buffer_comparator comp (
        .clk(clk),
        .rst_n(rst_n),
        .new_byte(rx_valid),
        .the_byte(rx_data),
        .match(trigger_send)
    );

    // --- UART TX ---
    wire tx_serial;

    uart_tx uart_tx_inst (
        .clk(clk),
        .rst_n(rst_n),
        .baud_tick(baud_tick_tx),
        .send(trigger_send),
        .tx(tx_serial),
        .busy(uo_out[4])
    );

    // --- ADDRESSABLE LED ---
    // (WS2812 uses GRB format)
    reg [23:0] color0 = 24'h00FF00; // Green (G=FF)
    reg [23:0] color1 = 24'hFF0000; // Red   (R=FF)

    single_addresable_led led_driver_inst (
        .clk(clk),
        .rst_n(rst_n),
        .color_select(trigger_send),
        .color0(color0),
        .color1(color1),
        .led_data_out(uo_out[5])
    );


    // --- Output Connections ---
    assign uo_out[0] = tx_serial;
    assign uo_out[1] = baud_tick_rx;
    assign uo_out[2] = baud_tick_tx;
    assign uo_out[3] = trigger_send;

    assign uo_out[6] = 1'b0;
    assign uo_out[7] = 1'b0;

    // --- All IOs unused ---
    assign uio_out    = 8'b0;
    assign uio_oe     = 8'b0;

    // Unused signal suppression
    wire _unused = ena | &uio_in | &ui_in[7:1];


endmodule



`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company: DAKKA POWER ELECTRONICS S.L
// Engineer: Javier MS
// 
// Create Date: 06/16/2025 02:40:30 PM
// Module Name: baud_generator
// Target Devices: spartan7 fpga and tiny tapeout ASIC
// Tool Versions: 
// Description: BAUD_DIV is jsut a simple prescaler for clk signal
//              as long as it fits in the counter register it will scale down clk and output to baud_tick
// 
// Dependencies: none
// 
// Revision 0.01 - File Created
// Additional Comments: not really
// 
//////////////////////////////////////////////////////////////////////////////////


module baud_generator(
    input wire clk,
    input wire rst_n,
    output reg baud_tick
    );
    parameter BAUD_DIV = 1250;  // (12_000_000) / 9600

    reg [12:0] counter;  // Enough bits to hold values up to 65535
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            counter   <= 0;
            baud_tick <= 0;
        end else begin
            if (counter == BAUD_DIV - 1) begin
                counter   <= 0;
                baud_tick <= 1;
            end else begin
                counter   <= counter + 1;
                baud_tick <= 0;
            end
        end
    end

endmodule


`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company: DAKKA POWER ELECTRONICS S.L
// Engineer: Javier MS
// 
// Create Date: 06/31/2025 12:20:25 AM
// Module Name: uart_tx
// Target Devices: spartan7 fpga and tiny tapeout ASIC
// Tool Versions: 
// Description: simple state machine, this is barely a uart, the transmission buffer is hardcoded and the baudrate is controled with baud_tick
//              when the signal send is received, this module spits out the hardcoded message serialiced to tx.
//              busy signal is kept high during the whole transmission , in case we need some flow control or debuging purposes
// Dependencies: none
// 
// Revision 0.01 - File Created
// Additional Comments: not really
// 
//////////////////////////////////////////////////////////////////////////////////

module uart_tx (
    input  wire clk,         // system clock
    input  wire rst_n,       // active-low reset
    input  wire baud_tick,   // 9600 baud tick (1 cycle per bit)
    input  wire send,        // trigger to start sending "POLO\n"
    output wire tx,          // UART transmit line
    output wire busy         // high when sending
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule





`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company: DAKKA POWER ELECTRONICS S.L
// Engineer: Javier MS
// 
// Create Date: 06/30/2025 12:20:25 AM
// Module Name: uart_rx
// Target Devices: spartan7 fpga and tiny tapeout ASIC
// Tool Versions: 
// Description: simple state machine, uart_rx uses an oversampled 8x baud_tick to detect and deserialice rx signal.
//              the baudrate is controled with baud_tick, being the actuall serial baudrate baud_tick/8.
//              if new byte is received it triggers byte_received and paralelices the byte out to data.
// 
// Dependencies: none
// 
// Revision 0.01 - File Created
// Additional Comments: not really
// 
//////////////////////////////////////////////////////////////////////////////////


module uart_rx (
    input  wire clk,
    input  wire rst_n,
    input  wire baud_tick,   // oversampled (e.g. 8x)
    input  wire rx,          // serial input line
    output reg  [7:0] data,
    output reg  byte_received
);

    localparam [2:0]
        IDLE     = 3'd0,
        START    = 3'd1,
        DATA     = 3'd2,
        STOP     = 3'd3;

    reg [2:0] state;
    reg [2:0] bit_index;
    reg [3:0] baud_ctr;
    reg [7:0] rx_shift;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state      <= IDLE;
            bit_index  <= 0;
            baud_ctr   <= 0;
            rx_shift   <= 0;
            data       <= 0;
            byte_received <= 0;
        end else begin
            byte_received <= 0;

            if (baud_tick) begin
                case (state)
                    IDLE: begin
                        if (!rx) begin // start bit detected
                            state <= START;
                            baud_ctr <= 0;
                        end
                    end
                    START: begin
                        if (baud_ctr == 4) begin  // sample at center of bit
                            if (!rx) begin
                                state <= DATA;
                                bit_index <= 0;
                            end else begin
                                state <= IDLE;
                            end
                        end else
                            baud_ctr <= baud_ctr + 1;
                    end
                    DATA: begin
                        if (baud_ctr == 7) begin
                            rx_shift <= {rx, rx_shift[7:1]};
                            baud_ctr <= 0;
                            if (bit_index == 7)
                                state <= STOP;
                            else
                                bit_index <= bit_index + 1;
                        end else
                            baud_ctr <= baud_ctr + 1;
                    end
                    STOP: begin
                        if (baud_ctr == 7) begin
                            if (rx) begin // stop bit OK
                                data <= rx_shift;
                                byte_received <= 1;
                            end
                            state <= IDLE;
                            baud_ctr <= 0;
                        end else
                            baud_ctr <= baud_ctr + 1;
                    end
                    default: begin
                        // fallback to safe state
                        state <= IDLE;
                        baud_ctr <= 0;
                        bit_index <= 0;
                        rx_shift <= 0;
                    end
                endcase
            end
        end
    end

endmodule


`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company: DAKKA POWER ELECTRONICS S.L
// Engineer: Javier MS
// 
// Create Date: 06/30/2025 12:24:27 AM
// Module Name: buffer_comparator
// Target Devices: spartan7 fpga and tiny tapeout ASIC
// Tool Versions: 
// Description: when received a new_byte signal, the comparator stores the_byte in a fifo buffer
//              then checks if the buffer matches the harcoded message 'MARCO', if the buffer is equal to the message it triggers match.
// 
// Dependencies: none
// 
// Revision 0.01 - File Created
// Additional Comments: not really
// 
//////////////////////////////////////////////////////////////////////////////////

module buffer_comparator (
    input  wire        clk,
    input  wire        rst_n,
    input  wire        new_byte,       // From uart_rx
    input  wire [7:0]  the_byte,       // New received UART byte
    output reg         match           // Goes high for 1 cycle when "MARCO" is matched
);

    // Shift register buffer (last 5 characters)
    reg [7:0] buffer [0:4];  // buffer[4] = newest

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            buffer[0] <= 8'd0;
            buffer[1] <= 8'd0;
            buffer[2] <= 8'd0;
            buffer[3] <= 8'd0;
            buffer[4] <= 8'd0;
            match     <= 1'b0;
        end else begin
            match <= 1'b0;

            if (new_byte) begin
                // Shift left, insert newest byte at end
                buffer[0] <= buffer[1];
                buffer[1] <= buffer[2];
                buffer[2] <= buffer[3];
                buffer[3] <= buffer[4];
                buffer[4] <= the_byte;

                // Check for "MARCO"
                if (buffer[1] == "M" &&
                    buffer[2] == "A" &&
                    buffer[3] == "R" &&
                    buffer[4] == "C" &&
                    the_byte  == "O") begin
                    match <= 1'b1;
                end
            end
        end
    end

endmodule



`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company: DAKKA POWER ELECTRONICS S.L
// Engineer: Javier MS
// 
// Create Date: 06/30/2025 12:20:25 AM
// Module Name: single_addresable_led
// Target Devices: spartan7 fpga and tiny tapeout ASIC
// Tool Versions: 
// Description: drives a single addressable 800Khz WS2812  led, the depending of color_select it will output color0 or color1 
// 
// Dependencies: none
// 
// Revision 0.01 - File Created
// Additional Comments: not really
// 
//////////////////////////////////////////////////////////////////////////////////

module single_addresable_led (
    input  wire clk,
    input  wire rst_n,
    input  wire color_select,   
    input  wire [23:0] color0,
    input  wire [23:0] color1,
    output reg  led_data_out
);

    // Timing constants (50 MHz clock)
    localparam T1H         = 40;          // 800 ns
    localparam T0H         = 20;          // 400 ns
    localparam TOTAL       = 62;          // 1.24 us total bit time
    localparam RESET_TIME  = 10000;       // 50+150 us reset time
    localparam COLOR1_TIME = 2_500_000;   // 50 ms (50 MHz clock)

    // FSM states
    localparam IDLE  = 0,
               LOAD  = 1,
               SEND  = 2,
               RESET = 3;

    reg [2:0]  state;
    reg [5:0]  clk_cnt;
    reg [4:0]  bit_index;
    reg [11:0] reset_cnt;
    reg [23:0] shift_reg;
    reg        bit_val;

    // Timer for 100ms color1
    reg [22:0] color1_timer;
    wire use_color1 = (color1_timer != 0);

    // Color selection logic
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            color1_timer <= 0;
        else if (color_select)
            color1_timer <= COLOR1_TIME;
        else if (color1_timer != 0)
            color1_timer <= color1_timer - 1;
    end

    // WS2812 FSM
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            led_data_out <= 0;
            clk_cnt      <= 0;
            bit_index    <= 0;
            reset_cnt    <= 0;
            shift_reg    <= 0;
            bit_val      <= 0;
            state        <= IDLE;
        end else begin
            case (state)
                IDLE: begin
                    shift_reg <= use_color1 ? color1 : color0;
                    bit_index <= 0;
                    clk_cnt   <= 0;
                    state     <= LOAD;
                end

                LOAD: begin
                    bit_val   <= shift_reg[23];                    // latch MSB
                    shift_reg <= {shift_reg[22:0], 1'b0};          // shift left
                    led_data_out <= 1;                             // always start high
                    clk_cnt   <= 0;
                    state     <= SEND;
                end

                SEND: begin
                    clk_cnt <= clk_cnt + 1;

                    if ((bit_val && clk_cnt == T1H) || (!bit_val && clk_cnt == T0H))
                        led_data_out <= 0;

                    if (clk_cnt == TOTAL) begin
                        if (bit_index == 23) begin
                            state     <= RESET;
                            reset_cnt <= 0;
                            led_data_out <= 0;
                        end else begin
                            bit_index <= bit_index + 1;
                            state     <= LOAD;
                        end
                    end
                end

                RESET: begin
                    led_data_out <= 0;
                    reset_cnt <= reset_cnt + 1;
                    if (reset_cnt >= RESET_TIME)
                        state <= IDLE;
                end

                default: state <= IDLE;
            endcase
        end
    end

endmodule



Reference solution:
rtl/generated.v: 
    localparam [2:0]
        IDLE       = 3'd0,
        START_BIT  = 3'd1,
        DATA_BITS  = 3'd2,
        STOP_BIT   = 3'd3,
        NEXT_BYTE  = 3'd4,
        DONE       = 3'd5;

    reg [2:0] state;
    reg [2:0] bit_index;
    reg [3:0] byte_index;  // extended to fit up to 9 bytes
    reg [7:0] shift_reg;
    reg tx_reg;
    reg sending;

    assign tx = tx_reg;
    assign busy = sending;

    // ROM-like function to return byte from "POLO!\n\r"
    function automatic [7:0] get_message_byte(input [3:0] index);
        case (index)
            4'd0: get_message_byte = 8'h0A; // '\n'
            4'd1: get_message_byte = 8'h0D; // '\r'
            4'd2: get_message_byte = 8'h50; // 'P'
            4'd3: get_message_byte = 8'h4F; // 'O'
            4'd4: get_message_byte = 8'h4C; // 'L'
            4'd5: get_message_byte = 8'h4F; // 'O'
            4'd6: get_message_byte = 8'h21; // '!'
            4'd7: get_message_byte = 8'h0A; // '\n'
            4'd8: get_message_byte = 8'h0D; // '\r'
            default: get_message_byte = 8'h00;
        endcase
    endfunction

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state       <= IDLE;
            bit_index   <= 0;
            byte_index  <= 0;
            shift_reg   <= 8'h00;
            tx_reg      <= 1'b1;
            sending     <= 1'b0;
        end else begin
            case (state)
                IDLE: begin
                    tx_reg <= 1'b1;
                    sending <= 1'b0;
                    if (send) begin
                        byte_index <= 0;
                        shift_reg <= get_message_byte(0);  // preload first byte
                        state <= START_BIT;
                        sending <= 1'b1;
                    end
                end

                START_BIT: begin
                    if (baud_tick) begin
                        tx_reg <= 1'b0;  // start bit
                        bit_index <= 0;
                        state <= DATA_BITS;
                    end
                end

                DATA_BITS: begin
                    if (baud_tick) begin
                        tx_reg <= shift_reg[0];
                        shift_reg <= {1'b0, shift_reg[7:1]};
                        if (bit_index == 3'd7)
                            state <= STOP_BIT;
                        else
                            bit_index <= bit_index + 1;
                    end
                end

                STOP_BIT: begin
                    if (baud_tick) begin
                        tx_reg <= 1'b1; // stop bit
                        state <= NEXT_BYTE;
                    end
                end

                NEXT_BYTE: begin
                    if (baud_tick) begin
                        if (byte_index == 4'd8) begin
                            state <= DONE;
                        end else begin
                            byte_index <= byte_index + 1;
                            shift_reg <= get_message_byte(byte_index + 1);
                            state <= START_BIT;
                        end
                    end
                end

                DONE: begin
                    sending <= 1'b0;
                    state <= IDLE;
                end

                default: begin
                    // recover to safe state
                    state <= IDLE;
                    sending <= 1'b0;
                    tx_reg <= 1'b1;
                end
            endcase
        end
    end