You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Aakash Apoorv
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none
`timescale 1ns / 1ps

module tt_um_atomNPU (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
    // Declare internal wires
    wire start;
    wire done;
    wire npu_done;
    wire [3:0] npu_output; // Corrected width to match output_data[3:0]

    // Assign 'start' to uio_in[4]
    assign start = uio_in[4];

    // Instantiate the Tiny NPU Core
    atom_npu_core npu (
        .clk(clk),
        .rst_n(rst_n),
        .start(start),
        .input_data(ui_in[3:0]),   // Using lower 4 bits of ui_in
        .weight(uio_in[3:0]),      // Using lower 4 bits of uio_in
        .output_data(npu_output),
        .done(npu_done)
    );

    // Assign 'done' signal from NPU core to internal 'done' wire
    assign done = npu_done;

    // Assign the lower 4 bits of uo_out to the NPU output and set specific bits
    assign uo_out = {2'b00, done, 1'b0, npu_output}; // uo_out[5] = done, others as needed

    // Assign unused outputs to 0
    assign uio_out = {2'b00, done, 1'b0, npu_output};
    assign uio_oe  = 8'd0;

    // List all unused inputs to prevent warnings
    wire unused = &{ena, clk, rst_n, 1'b0, ui_in[7:4], uio_in[7:4]};
endmodule


module atom_npu_core (
    input  wire       clk,
    input  wire       rst_n,
    input  wire       start,
    input  wire [3:0] input_data,
    input  wire [3:0] weight,
    output reg  [3:0] output_data,
    output reg        done
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




Reference solution:
rtl/generated.v: 
    localparam IDLE = 2'b00;
    localparam CALC = 2'b01;
    localparam DONE = 2'b10;

    reg [1:0] state;
    reg [2:0] bit_count;
    reg [3:0] multiplier;
    reg [7:0] accumulator;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state        <= IDLE;
            bit_count    <= 0;
            multiplier   <= 0;
            accumulator  <= 0;
            output_data  <= 0;
            done         <= 0;
        end else begin
            case (state)
                IDLE: begin
                    if (start) begin
                        state       <= CALC;
                        bit_count   <= 0;
                        multiplier  <= weight;
                        accumulator <= 0;
                        done        <= 0;
                    end
                end

                CALC: begin
                    if (bit_count < 4) begin
                        if (multiplier[0])
                            accumulator <= accumulator + ({4'b0000, input_data} << bit_count);
                        multiplier    <= multiplier >> 1;
                        bit_count     <= bit_count + 1;
                    end else begin
                        state <= DONE;
                        if (accumulator > 8'd15)
                            output_data <= 4'd15;
                        else
                            output_data <= accumulator[3:0];
                    end
                end

                DONE: begin
                    done    <= 1;
                    state   <= IDLE;
                end

                default: state <= IDLE;
            endcase
        end
    end