You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.14-2022/10/10-beta-Pro
//_\source top.tlv 36

//_\SV
   // Include Tiny Tapeout Lab.
   // Included URL: "https://raw.githubusercontent.com/os-fpga/Virtual-FPGA-Lab/35e36bd144fddd75495d4cbc01c4fc50ac5bde6f/tlv_lib/tiny_tapeout_lib.tlv"// Included URL: "https://raw.githubusercontent.com/os-fpga/Virtual-FPGA-Lab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlv_lib/fpga_includes.tlv"
//_\source top.tlv 79
//_\SV

// ================================================
// A simple Makerchip Verilog test bench driving random stimulus.
// Modify the module contents to your needs.
// ================================================


// Provide a wrapper module to debounce input signals if requested.

//_\SV



// =======================
// The Tiny Tapeout module
// =======================

module tt_um_ajstein_stopwatch (
    input  wire [7:0] ui_in,    // Dedicated inputs - connected to the input switches
    output wire [7:0] uo_out,   // Dedicated outputs - connected to the 7 segment display
       // The FPGA is based on TinyTapeout 3 which has no bidirectional I/Os (vs. TT6 for the ASIC).
    input  wire [7:0] uio_in,   // IOs: Bidirectional Input path
    output wire [7:0] uio_out,  // IOs: Bidirectional Output path
    output wire [7:0] uio_oe,   // IOs: Bidirectional Enable path (active high: 0=input, 1=output)
    
    input  wire       ena,      // will go high when the design is enabled
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




// Undefine macros defined by SandPiper.
`undef BOGUS_USE


Reference solution:
rtl/generated.v:    wire reset = ! rst_n;

// ---------- Generated Code Inlined Here (before 1st \TLV) ----------
// Generated by SandPiper(TM) 1.14-2022/10/10-beta-Pro from Redwood EDA, LLC.
// (Installed here: /usr/local/mono/sandpiper/distro.)
// Redwood EDA, LLC does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality.


// For silencing unused signal messages.
`define BOGUS_USE(ignore)


genvar digit, input_label, leds, switch;


//
// Signals declared top-level.
//

// For $slideswitch.
wire [7:0] L0_slideswitch_a0;

// For $sseg_decimal_point_n.
wire L0_sseg_decimal_point_n_a0;

// For $sseg_digit_n.
wire [7:0] L0_sseg_digit_n_a0;

// For $sseg_segment_n.
wire [6:0] L0_sseg_segment_n_a0;

// For /fpga_pins/fpga$cycle_counter.
wire [31:0] FpgaPins_Fpga_cycle_counter_a0;
reg  [31:0] FpgaPins_Fpga_cycle_counter_a1;

// For /fpga_pins/fpga$display_counter.
wire [3:0] FpgaPins_Fpga_display_counter_a0;
reg  [3:0] FpgaPins_Fpga_display_counter_a1;

// For /fpga_pins/fpga$reset.
wire FpgaPins_Fpga_reset_a0;

// For /fpga_pins/fpga$segments.
wire [6:0] FpgaPins_Fpga_segments_a0;




   //
   // Scope: /fpga_pins
   //


      //
      // Scope: /fpga
      //

         // Staging of $cycle_counter.
         always @(posedge clk) FpgaPins_Fpga_cycle_counter_a1[31:0] <= FpgaPins_Fpga_cycle_counter_a0[31:0];

         // Staging of $display_counter.
         always @(posedge clk) FpgaPins_Fpga_display_counter_a1[3:0] <= FpgaPins_Fpga_display_counter_a0[3:0];







//
// Debug Signals
//

generate

   if (1) begin : DEBUG_SIGS_GTKWAVE

      (* keep *) wire [7:0] \@0$slideswitch ;
      assign \@0$slideswitch = L0_slideswitch_a0;
      (* keep *) wire  \@0$sseg_decimal_point_n ;
      assign \@0$sseg_decimal_point_n = L0_sseg_decimal_point_n_a0;
      (* keep *) wire [7:0] \@0$sseg_digit_n ;
      assign \@0$sseg_digit_n = L0_sseg_digit_n_a0;
      (* keep *) wire [6:0] \@0$sseg_segment_n ;
      assign \@0$sseg_segment_n = L0_sseg_segment_n_a0;

      //
      // Scope: /digit[0:0]
      //
      for (digit = 0; digit <= 0; digit=digit+1) begin : \/digit 

         //
         // Scope: /leds[7:0]
         //
         for (leds = 0; leds <= 7; leds=leds+1) begin : \/leds 
            (* keep *) wire  \//@0$viz_lit ;
            assign \//@0$viz_lit = L1_Digit[digit].L2_Leds[leds].L2_viz_lit_a0;
         end
      end

      //
      // Scope: /fpga_pins
      //
      if (1) begin : \/fpga_pins 

         //
         // Scope: /fpga
         //
         if (1) begin : \/fpga 
            (* keep *) wire [31:0] \//@0$cycle_counter ;
            assign \//@0$cycle_counter = FpgaPins_Fpga_cycle_counter_a0;
            (* keep *) wire [3:0] \//@0$display_counter ;
            assign \//@0$display_counter = FpgaPins_Fpga_display_counter_a0;
            (* keep *) wire  \//@0$reset ;
            assign \//@0$reset = FpgaPins_Fpga_reset_a0;
            (* keep *) wire [6:0] \//@0$segments ;
            assign \//@0$segments = FpgaPins_Fpga_segments_a0;
         end
      end

      //
      // Scope: /switch[7:0]
      //
      for (switch = 0; switch <= 7; switch=switch+1) begin : \/switch 
         (* keep *) wire  \/@0$viz_switch ;
         assign \/@0$viz_switch = L1_Switch[switch].L1_viz_switch_a0;
      end


   end

endgenerate

// ---------- Generated Code Ends ----------
//_\TLV
   /* verilator lint_off UNOPTFLAT */
   //_\source top.tlv 72   // Instantiated from top.tlv, 146 as: m5+tt_lab.
      // Connect Tiny Tapeout I/Os to Virtual FPGA Lab.
      //_\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/35e36bd144fddd75495d4cbc01c4fc50ac5bde6f/tlvlib/tinytapeoutlib.tlv 76   // Instantiated from top.tlv, 74 as: m5+tt_connections()
         assign L0_slideswitch_a0[7:0] = ui_in;
         assign L0_sseg_segment_n_a0[6:0] = ~ uo_out[6:0];
         assign L0_sseg_decimal_point_n_a0 = ~ uo_out[7];
         assign L0_sseg_digit_n_a0[7:0] = 8'b11111110;
      //_\end_source
      // Instantiate the Virtual FPGA Lab.
      //_\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv 307   // Instantiated from top.tlv, 76 as: m5+board(/top, /fpga, 7, $, , stopwatch)
         
         //_\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv 355   // Instantiated from /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv, 309 as: m4+thanks(m5__l(309)m5_eval(m5_get(BOARD_THANKS_ARGS)))
            //_/thanks
               
         //_\end_source
         
      
         // Board VIZ.
      
         // Board Image.
         
         //_/fpga_pins
            
            //_/fpga
               //_\source top.tlv 43   // Instantiated from /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv, 340 as: m4+stopwatch.
               
                  assign FpgaPins_Fpga_reset_a0 = reset;
                  assign FpgaPins_Fpga_cycle_counter_a0[31:0] = FpgaPins_Fpga_reset_a0 ? 1 :
                      FpgaPins_Fpga_cycle_counter_a1 == 20000000 ? 1 :
                      FpgaPins_Fpga_cycle_counter_a1 + 1;
                  assign FpgaPins_Fpga_display_counter_a0[3:0] =
                     FpgaPins_Fpga_reset_a0 ? 4'd0 :
                     FpgaPins_Fpga_cycle_counter_a0 == 20000000
                         ? FpgaPins_Fpga_display_counter_a1 == 9 ? 0 :
                           FpgaPins_Fpga_display_counter_a1 + 1 :
                     //default
                           FpgaPins_Fpga_display_counter_a1;
                  assign FpgaPins_Fpga_segments_a0[6:0] =
                     (FpgaPins_Fpga_display_counter_a0 == 0) ? 7'b1000000 :
                     (FpgaPins_Fpga_display_counter_a0 == 1) ? 7'b1111001 :
                     (FpgaPins_Fpga_display_counter_a0 == 2) ? 7'b0100100 :
                     (FpgaPins_Fpga_display_counter_a0 == 3) ? 7'b0110000 :
                     (FpgaPins_Fpga_display_counter_a0 == 4) ? 7'b0011001 :
                     (FpgaPins_Fpga_display_counter_a0 == 5) ? 7'b0010010 :
                     (FpgaPins_Fpga_display_counter_a0 == 6) ? 7'b0000010 :
                     (FpgaPins_Fpga_display_counter_a0 == 7) ? 7'b1111000 :
                     (FpgaPins_Fpga_display_counter_a0 == 8) ? 7'b0000000 :
                     7'b0010000 ; // '9'
                  assign uo_out = {1'b0, ~FpgaPins_Fpga_segments_a0};
                  assign uio_out = 8'b0;
                  assign uio_oe = 8'b0;
               //_\end_source
      
         // LEDs.
         
      
         // 7-Segment
         //_\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv 395   // Instantiated from /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv, 346 as: m4+fpga_sseg.
            generate for (digit = 0; digit <= 0; digit=digit+1) begin : L1_Digit //_/digit
               
               for (leds = 0; leds <= 7; leds=leds+1) begin : L2_Leds //_/leds

                  // For $viz_lit.
                  wire L2_viz_lit_a0;

                  assign L2_viz_lit_a0 = (! L0_sseg_digit_n_a0[digit]) && ! ((leds == 7) ? L0_sseg_decimal_point_n_a0 : L0_sseg_segment_n_a0[leds % 7]);
                  
               end
            end endgenerate
         //_\end_source
      
         // slideswitches
         //_\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv 454   // Instantiated from /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv, 349 as: m4+fpga_switch.
            generate for (switch = 0; switch <= 7; switch=switch+1) begin : L1_Switch //_/switch

               // For $viz_switch.
               wire L1_viz_switch_a0;

               assign L1_viz_switch_a0 = L0_slideswitch_a0[switch];
               
            end endgenerate
         //_\end_source
      
         // pushbuttons
         
      //_\end_source
      // Label the switch inputs [0..7] (1..8 on the physical switch panel) (top-to-bottom).
      //_\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/35e36bd144fddd75495d4cbc01c4fc50ac5bde6f/tlvlib/tinytapeoutlib.tlv 82   // Instantiated from top.tlv, 78 as: m5+tt_input_labels_viz(⌈"UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED"⌉)
         generate for (input_label = 0; input_label <= 7; input_label=input_label+1) begin : L1_InputLabel //_/input_label
            
         end endgenerate
      //_\end_source
   
   //_\end_source

/*SV_plus*/

   // ==========================================
   // If you are using Verilog for your design,
   // your Verilog logic goes here.
   // Note, output assignments are in my_design.
   // ==========================================

//_\SV