You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Your Name
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_gmejiamtz (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




module LUT3(
    input clk_i,
    input resetn,
    input new_seed_i,
    input [2:0] args_i,
    input [7:0] seed_i,
    output out_o);

  reg [7:0] lookup_table_r;
  reg out_r;
  always @(posedge clk_i) begin
    if(!resetn) begin
      lookup_table_r <= '0;
    end
    else if (new_seed_i) begin
      lookup_table_r <= seed_i; 
    end
  end
  always @(*) begin
    case (args_i)
    3'b000:
      out_r = lookup_table_r[0];
    3'b001:
      out_r = lookup_table_r[1];
    3'b010:
      out_r = lookup_table_r[2];
    3'b011:
      out_r = lookup_table_r[3];
    3'b100:
      out_r = lookup_table_r[4];
    3'b101:
      out_r = lookup_table_r[5];
    3'b110:
      out_r = lookup_table_r[6];
    3'b111:
      out_r = lookup_table_r[7];
    endcase
  end
  assign out_o = out_r;
endmodule

Reference solution:
rtl/generated.v:   wire comb_out;
  reg is_sync_r,comb_out_r, out_r;

  //make a lut 3
  LUT3 lut (.clk_i(clk),.resetn(rst_n),.new_seed_i(ui_in[3]),.args_i(ui_in[2:0]),.seed_i(uio_in),.out_o(comb_out));
  //setting the lut to me "synchronous" eg a 2 cycle read instead of 1
  always @(posedge clk) begin
    if(!rst_n) begin
      is_sync_r <= 1'b0;
    end else if(ui_in[3]) begin 
      is_sync_r <= ui_in[4];
    end
  end

  //ff for a sync clk - will be a 2 cycle delay with this LUT design
  always @(posedge clk) begin
    if(!rst_n) begin
      comb_out_r <= '0;
    end else begin
      comb_out_r <= comb_out;
    end
  end

  always @(*) begin
    if (is_sync_r) begin
      out_r = comb_out_r;
    end else begin
      out_r = comb_out;
    end
  end
  assign uo_out = {7'b0,out_r};
  assign uio_oe = '0;
  wire _unused = &{ena, ui_in[7:5],1'b0};
  assign uio_out = '0;