You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2025 Sean Patrick O'Brien
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none
`timescale 1ns / 1ps

module boundary_scan_register(
  input  wire        tck_i,
  input  wire        reset_i,

  input  wire        ir_sample_preload_i,
  input  wire        ir_extest_i,
  input  wire        ir_intest_i,
  input  wire        ir_clamp_i,

  output wire [25:0] capture_data_o,
  input  wire [25:0] update_data_i,
  input  wire        update_i,

  output wire  [7:0] sys_ui_in_o,
  inout  wire  [7:0] sys_uo_out_i,
  output wire  [3:0] sys_uio_in_o,
  input  wire  [3:0] sys_uio_out_i,
  input  wire  [3:0] sys_uio_oe_i,

  input  wire  [7:0] pin_ui_in_i,
  output wire  [7:0] pin_uo_out_o,
  input  wire  [3:0] pin_uio_in_i,
  output wire  [3:0] pin_uio_out_o,
  output wire  [3:0] pin_uio_oe_o
);

  reg [25:0] values;


  // use negative edge-triggered flops
  // 8.8.1 Rule D.2: "[output pins] shall change only on the falling edge of TCK in the Update-DR controller state"
  always @(negedge tck_i or posedge reset_i) begin
    if (reset_i)
      values <= 26'b0;
    else if (update_i && (ir_sample_preload_i || ir_extest_i || ir_intest_i))
      values <= update_data_i;
  end

  wire control_output = ir_extest_i || ir_intest_i || ir_clamp_i;
  wire control_input  = ir_intest_i;

  assign capture_data_o = {
    ir_extest_i ? 8'b0         : sys_uo_out_i,
    ir_extest_i ? pin_uio_in_i : sys_uio_out_i,
    ir_extest_i ? 4'b0         : sys_uio_oe_i,
    ir_intest_i ? 8'b0         : pin_ui_in_i,
    2'b11 // FIXME: rst_n and clk
  };

  assign pin_uo_out_o  = control_output ? values[25:18] : sys_uo_out_i;
  assign pin_uio_out_o = control_output ? values[17:14] : sys_uio_out_i;
  assign pin_uio_oe_o  = control_output ? values[13:10] : sys_uio_oe_i;

  assign sys_ui_in_o  = control_input ? values[9:2]   : pin_ui_in_i;
  assign sys_uio_in_o = control_input ? values[17:14] : pin_uio_in_i;

endmodule


/*
 * Copyright (c) 2025 Sean Patrick O'Brien
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none
`timescale 1ns / 1ps

module inner_project (
  input  wire [7:0] ui_in,    // Dedicated inputs
  output wire [7:0] uo_out,   // Dedicated outputs
  input  wire [3:0] uio_in,   // IOs: Input path
  output wire [3:0] uio_out,  // IOs: Output path
  output wire [3:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
  input  wire       ena,      // always 1 when the design is powered, so you can ignore it
  input  wire       clk,      // clock
  input  wire       rst_n     // reset_n - low to reset
);
  reg [3:0] counter;
  always @(posedge clk or negedge rst_n) begin
    if (~rst_n)
      counter <= 4'b0;
    else
      counter <= counter + 1;
  end

  wire output_mode = ui_in[0];
  wire [3:0] input_value = ui_in[4:1];
  wire [3:0] display_value = output_mode ? input_value : counter;

  seven_segment seg(
    .value(display_value),
    .segments(uo_out[6:0])
  );

  assign uo_out[7] = 1'b0;
  assign uio_out = 0;
  assign uio_oe  = 0;

  // List all unused inputs to prevent warnings
  wire _unused = &{ena, uio_in, 1'b0};

endmodule


`default_nettype none

module jtag_tap_sm #(
  parameter IR_LENGTH = 4,
  parameter INIT_IR = {IR_LENGTH{1'b0}}
)(
  input  wire       tck_i,
  input  wire       trst_ni,
  input  wire       tms_i,
  input  wire       tdi_i,
  output wire       tdo_o,
  output wire       tdo_oe_o,

  output wire       tck_o,
  output wire       reset_o,
  output wire [3:0] ir_o,     // contents of the IR
  input  wire       bypass_i, // high if ir_o is not handled by client
  output wire       tdi_o,    // TDI to client
  input  wire       tdo_i,    // TDO from client,
  output wire       runtest_o,
  output wire       capture_o,
  output wire       shift_o,
  output wire       update_o
);

  // State machine
  localparam STATE_RESET      = 0,
             STATE_IDLE       = 1,
             STATE_SELECT_DR  = 2,
             STATE_CAPTURE_DR = 3,
             STATE_SHIFT_DR   = 4,
             STATE_EXIT1_DR   = 5,
             STATE_PAUSE_DR   = 6,
             STATE_EXIT2_DR   = 7,
             STATE_UPDATE_DR  = 8,
             STATE_SELECT_IR  = 9,
             STATE_CAPTURE_IR = 10,
             STATE_SHIFT_IR   = 11,
             STATE_EXIT1_IR   = 12,
             STATE_PAUSE_IR   = 13,
             STATE_EXIT2_IR   = 14,
             STATE_UPDATE_IR  = 15;

  reg [3:0] state_q;
  reg [3:0] state_d;

  always @(posedge tck_i or negedge trst_ni) begin
    if (~trst_ni)
      state_q <= STATE_RESET;
    else
      state_q <= state_d;
  end

  always @(*) begin
    case (state_q)
      STATE_RESET: state_d      = tms_i ? STATE_RESET     : STATE_IDLE;
      STATE_IDLE:       state_d = tms_i ? STATE_SELECT_DR : STATE_IDLE;
      STATE_SELECT_DR:  state_d = tms_i ? STATE_SELECT_IR : STATE_CAPTURE_DR;
      STATE_CAPTURE_DR: state_d = tms_i ? STATE_EXIT1_DR  : STATE_SHIFT_DR;
      STATE_SHIFT_DR:   state_d = tms_i ? STATE_EXIT1_DR  : STATE_SHIFT_DR;
      STATE_EXIT1_DR:   state_d = tms_i ? STATE_UPDATE_DR : STATE_PAUSE_DR;
      STATE_PAUSE_DR:   state_d = tms_i ? STATE_EXIT2_DR  : STATE_PAUSE_DR;
      STATE_EXIT2_DR:   state_d = tms_i ? STATE_UPDATE_DR : STATE_SHIFT_DR;
      STATE_UPDATE_DR:  state_d = tms_i ? STATE_SELECT_DR : STATE_IDLE;
      STATE_SELECT_IR:  state_d = tms_i ? STATE_RESET     : STATE_CAPTURE_IR;
      STATE_CAPTURE_IR: state_d = tms_i ? STATE_EXIT1_IR  : STATE_SHIFT_IR;
      STATE_SHIFT_IR:   state_d = tms_i ? STATE_EXIT1_IR  : STATE_SHIFT_IR;
      STATE_EXIT1_IR:   state_d = tms_i ? STATE_UPDATE_IR : STATE_PAUSE_IR;
      STATE_PAUSE_IR:   state_d = tms_i ? STATE_EXIT2_IR  : STATE_PAUSE_IR;
      STATE_EXIT2_IR:   state_d = tms_i ? STATE_UPDATE_IR : STATE_SHIFT_IR;
      STATE_UPDATE_IR:  state_d = tms_i ? STATE_SELECT_DR : STATE_IDLE;
    endcase
  end

  // Instruction Register
  localparam INSTR_BYPASS = {IR_LENGTH{1'b1}};

  reg [3:0] ir_q;
  reg [3:0] ir_shift_q;
  always @(posedge tck_i or negedge trst_ni) begin
    if (~trst_ni)
      ir_q <= INIT_IR;
    else if (state_q == STATE_RESET)
      ir_q <= INIT_IR;
    else if (state_q == STATE_UPDATE_IR)
      ir_q <= ir_shift_q;
  end

  always @(posedge tck_i or negedge trst_ni) begin
    if (~trst_ni)
      ir_shift_q <= 4'b0;
    else if (state_q == STATE_RESET)
      ir_shift_q <= 4'b0;
    else if (state_q == STATE_CAPTURE_IR)
      ir_shift_q <= {ir_q[3:2], 2'b01};
    else if (state_q == STATE_SHIFT_IR)
      ir_shift_q <= {tdi_i, ir_shift_q[3:1]};
  end

  // BYPASS Register
  wire should_bypass = ir_q == INSTR_BYPASS || bypass_i;
  reg bypass_shift_q;
  always @(posedge tck_i or negedge trst_ni) begin
    if (~trst_ni)
      bypass_shift_q <= 1'b0;
    else if (state_q == STATE_RESET)
      bypass_shift_q <= 1'b0;
    else if (state_q == STATE_CAPTURE_DR && should_bypass)
      bypass_shift_q <= 1'b0;
    else if (state_q == STATE_SHIFT_DR && should_bypass)
      bypass_shift_q <= tdi_i;
  end

  // TDO Mux and Timing
  reg tdo_q;
  reg tdo_d;

  // tdo is updated on the falling edge of TCK
  always @(negedge tck_i or negedge trst_ni) begin
    if (~trst_ni)
      tdo_q <= 1'b0;
    else if (state_q == STATE_RESET)
      tdo_q <= 1'b0;
    else
      tdo_q <= tdo_d;
  end

  always @(*) begin
    if (state_q == STATE_SHIFT_IR)
      tdo_d = ir_shift_q[0];
    else if (state_q == STATE_SHIFT_DR)
      tdo_d = should_bypass ? bypass_shift_q : tdo_i;
    else
      tdo_d = 1'b0;
  end

  // register the reset output to prevent glitches
  reg reset_q;
  always @(posedge tck_i or negedge trst_ni) begin
    if (~trst_ni)
      reset_q <= 1'b1;
    else if (state_d == STATE_RESET)
      reset_q <= 1'b1;
    else
      reset_q <= 1'b0;
  end

  assign tdo_o     = tdo_q;
  assign tdo_oe_o  = state_q == STATE_SHIFT_IR || state_q == STATE_SHIFT_DR;

  assign tck_o     = tck_i;
  assign ir_o      = ir_q;
  assign tdi_o     = tdi_i;
  assign reset_o   = reset_q;
  assign runtest_o = state_q == STATE_IDLE;
  assign capture_o = state_q == STATE_CAPTURE_DR;
  assign shift_o   = state_q == STATE_SHIFT_DR;
  assign update_o  = state_q == STATE_UPDATE_DR;
endmodule


/*
 * Copyright (c) 2025 Sean Patrick O'Brien
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none
`timescale 1ns / 1ps

module seven_segment(
  input  wire [3:0] value,
  output wire [6:0] segments
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




/*
 * Copyright (c) 2025 Sean Patrick O'Brien
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none
`timescale 1ns / 1ps

module tt_um_obriensp_jtag (
  input  wire [7:0] ui_in,    // Dedicated inputs
  output wire [7:0] uo_out,   // Dedicated outputs
  input  wire [7:0] uio_in,   // IOs: Input path
  output wire [7:0] uio_out,  // IOs: Output path
  output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
  input  wire       ena,      // always 1 when the design is powered, so you can ignore it
  input  wire       clk,      // clock
  input  wire       rst_n     // reset_n - low to reset
);

  localparam INSTR_IDCODE = 4'd0,
             INSTR_SAMPLE = 4'd1,
             INSTR_EXTEST = 4'd2,
             INSTR_INTEST = 4'd3,
             INSTR_CLAMP  = 4'd4;

  localparam W_IR     = 4,
             W_IDCODE = 32,
             W_BSR    = 26,
             W_MAX    = 32;

  wire tdo_oe;
  wire tck;
  wire reset;
  wire [W_IR-1:0] ir;
  reg bypass;
  wire tdi;
  wire tdo;
  wire runtest;
  wire capture;
  wire shift;
  wire update;
  jtag_tap_sm #(
    .IR_LENGTH(W_IR),
    .INIT_IR(INSTR_IDCODE)
  ) tap_sm(
    .tck_i(uio_in[4]),
    .trst_ni(rst_n),
    .tms_i(uio_in[5]),
    .tdi_i(uio_in[6]),
    .tdo_o(uio_out[7]),
    .tdo_oe_o(uio_oe[7]),

    .tck_o(tck),
    .reset_o(reset),
    .ir_o(ir),
    .bypass_i(bypass),
    .tdi_o(tdi),
    .tdo_i(tdo),
    .runtest_o(runtest),
    .capture_o(capture),
    .shift_o(shift),
    .update_o(update)
  );

  assign uio_out[6:4] = 3'b0;
  assign uio_oe[6:4]  = 3'b0;

  // bypass
  always @(*) begin
    case (ir)
      INSTR_IDCODE: bypass = 1'b0;
      INSTR_SAMPLE: bypass = 1'b0;
      INSTR_EXTEST: bypass = 1'b0;
      INSTR_INTEST: bypass = 1'b0;
      INSTR_CLAMP:  bypass = 1'b1;
      default:      bypass = 1'b1;
    endcase
  end

  // data register capture
  reg [W_MAX-1:0] capture_value;
  always @(*) begin
    case (ir)
      INSTR_IDCODE: capture_value = {{W_MAX-W_IDCODE{1'b0}}, 4'd3, 16'd42, 11'h77E, 1'b1};
      INSTR_SAMPLE: capture_value = {{W_MAX-W_BSR{1'b0}}, bsr_capture_value};
      INSTR_EXTEST: capture_value = {{W_MAX-W_BSR{1'b0}}, bsr_capture_value};
      INSTR_INTEST: capture_value = {{W_MAX-W_BSR{1'b0}}, bsr_capture_value};
      default:      capture_value = {W_MAX{1'b0}};
    endcase
  end

  // shift register
  reg [W_MAX-1:0] shift_q;
  always @(posedge tck or posedge reset) begin
    if (reset)
      shift_q <= {W_MAX{1'b0}};
    else if (capture)
      shift_q <= capture_value;
    else if (shift) begin
      case (ir)
        INSTR_IDCODE: shift_q <= {{W_MAX-W_IDCODE{1'b0}}, tdi, shift_q[W_IDCODE-1:1]};
        INSTR_SAMPLE: shift_q <= {   {W_MAX-W_BSR{1'b0}}, tdi, shift_q[W_BSR-1:1]};
        INSTR_EXTEST: shift_q <= {   {W_MAX-W_BSR{1'b0}}, tdi, shift_q[W_BSR-1:1]};
        INSTR_INTEST: shift_q <= {   {W_MAX-W_BSR{1'b0}}, tdi, shift_q[W_BSR-1:1]};
        default:      shift_q <= {       {W_MAX-2{1'b0}}, tdi, shift_q[1]};
      endcase
    end
  end

  assign tdo = shift_q[0];

  // Boundary Scan Register
  wire [W_BSR-1:0] bsr_capture_value;
  wire  [4:0] sys_leds;
  wire  [2:0] sys_buttons;
  wire  [7:0] sys_p1b;

  wire [7:0] sys_ui_in;
  wire [7:0] sys_uo_out;
  wire [3:0] sys_uio_in;
  wire [3:0] sys_uio_out;
  wire [3:0] sys_uio_oe;
  boundary_scan_register bsr(
    .tck_i(tck),
    .reset_i(reset),
    .ir_sample_preload_i(ir == INSTR_SAMPLE),
    .ir_extest_i(ir == INSTR_EXTEST),
    .ir_intest_i(ir == INSTR_INTEST),
    .ir_clamp_i(ir == INSTR_CLAMP),
    .capture_data_o(bsr_capture_value),
    .update_data_i(shift_q[W_BSR-1:0]),
    .update_i(update),
    .sys_ui_in_o(sys_ui_in),
    .sys_uo_out_i(sys_uo_out),
    .sys_uio_in_o(sys_uio_in),
    .sys_uio_out_i(sys_uio_out),
    .sys_uio_oe_i(sys_uio_oe),
    .pin_ui_in_i(ui_in),
    .pin_uo_out_o(uo_out),
    .pin_uio_in_i(uio_in[3:0]),
    .pin_uio_out_o(uio_out[3:0]),
    .pin_uio_oe_o(uio_oe[3:0])
  );
  
  inner_project inner(
    .ui_in(sys_ui_in),
    .uo_out(sys_uo_out),
    .uio_in(sys_uio_in),
    .uio_out(sys_uio_out),
    .uio_oe(sys_uio_oe),
    .ena(ena),
    .clk(clk),
    .rst_n(rst_n)
  );

endmodule


Reference solution:
rtl/generated.v: 
  reg [6:0] seg;
  always @(*) begin
    case (value)
    4'h0: seg = 7'b0111111;
    4'h1: seg = 7'b0000110;
    4'h2: seg = 7'b1011011;
    4'h3: seg = 7'b1001111;
    4'h4: seg = 7'b1100110;
    4'h5: seg = 7'b1101101;
    4'h6: seg = 7'b1111101;
    4'h7: seg = 7'b0000111;
    4'h8: seg = 7'b1111111;
    4'h9: seg = 7'b1101111;
    4'hA: seg = 7'b1110111;
    4'hB: seg = 7'b1111100;
    4'hC: seg = 7'b0111001;
    4'hD: seg = 7'b1011110;
    4'hE: seg = 7'b1111001;
    4'hF: seg = 7'b1110001;
    endcase
  end

  assign segments = seg;