You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

module tt_um_DelosReyesJordan_HDL (
    input  wire [7:0] ui_in,
    output wire [7:0] uo_out,
    input  wire [7:0] uio_in,
    output wire [7:0] uio_out,
    output wire [7:0] uio_oe,
    input  wire       ena,
    input  wire       clk,
    input  wire       rst_n
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




module reaction_time_top (
    input  wire [7:0] ui_in,      // general inputs (buttons)
    output wire [7:0] uo_out,     // segments + LED
    output wire [3:0] uio_out,    // 7-segment anode control
    output wire [3:0] uio_oe,     // anode output enable
    input  wire       clk,        // system clock
    input  wire       rst_n       // active-low reset
);

    // Active-high reset
    wire reset = ~rst_n;

    // Map UI buttons
    wire start_btn = ui_in[0];
    wire react_btn = ui_in[1];

    // FSM control signals
    wire start_timer;
    wire stop_timer;
    wire show_error;
    wire done;
    wire [2:0] state_out;

    // Timer signals
    wire [13:0] elapsed_time;

    // 7-segment display signals
    wire [6:0] seg;
    wire [3:0] an;
    wire [13:0] value_to_display;
    wire [1:0] current_digit;

    // Instantiate reaction FSM
    reaction_fsm fsm (
        .clk(clk),
        .reset(reset),
        .start_btn(start_btn),
        .react_btn(react_btn),
        .delay_done(done),           // we use 'done' from timer as delay_done
        .elapsed_time(elapsed_time),
        .led(uo_out[0]),             // connect LED output
        .start_timer(start_timer),
        .stop_timer(stop_timer),
        .show_error(show_error),
        .done(done),
        .state_out(state_out)
    );

    // Instantiate timer
    timer tmr (
        .clk(clk),
        .reset(reset),
        .start(start_timer),
        .stop(stop_timer),
        .ms_time(elapsed_time)
    );

    // Instantiate 7-segment display driver
    seg7_driver display (
        .clk(clk),
        .reset(reset),
        .show_error(show_error),
        .value(elapsed_time),
        .seg(seg),
        .an(an),
        .digit_select(current_digit)
    );

    // Output assignments
    assign uo_out[7:1] = seg;    // 7-segment segments
    assign uio_out = an;          // anode signals
    assign uio_oe  = 4'b1111;    // enable all anodes

endmodule


module reaction_fsm(
    input clk, reset, start_btn, react_btn,
    input delay_done, 
    input [13:0] elapsed_time, // max 9999
    output reg led,
    output reg start_timer, stop_timer, show_error, done,
    output reg [2:0] state_out  // new output for current FSM state
);

    // State encoding
    parameter IDLE  = 3'b000,
              WAIT  = 3'b001,
              READY = 3'b010,
              TIMING= 3'b011,
              DONE  = 3'b100,
              ERROR = 3'b101;

    reg [2:0] state, next;

    // State register with synchronous reset
    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else
            state <= next;

        state_out <= state;
    end

    // Next state logic and outputs
    always @(*) begin
        next = state;
        led = 0;
        start_timer = 0;
        stop_timer = 0;
        show_error = 0;
        done = 0;

        case (state)
            IDLE: begin
                if (start_btn)
                    next = WAIT;
            end

            WAIT: begin
                if (react_btn)
                    next = ERROR;
                else if (delay_done)
                    next = READY;
            end

            READY: begin
                led = 1;
                start_timer = 1;
                next = TIMING;
            end

            TIMING: begin
                led = 1;
                if (react_btn) begin
                    stop_timer = 1;
                    next = DONE;
                end
            end

            DONE: begin
                done = 1;
                if (start_btn)
                    next = IDLE;
            end

            ERROR: begin
                show_error = 1;
                if (start_btn)
                    next = IDLE;
            end

            default: next = IDLE;
        endcase
    end

endmodule


module random_delay(
    input clk, reset, start,
    output reg done
);
    reg [28:0] counter;
    reg [28:0] target;

    // Simple LFSR for pseudo-random number generation
    reg [15:0] lfsr;
    wire feedback = lfsr[15] ^ lfsr[13] ^ lfsr[12] ^ lfsr[10];

    always @(posedge clk) begin
        if (reset) begin
            counter <= 0;
            done <= 0;
            lfsr <= 16'hACE1; // seed
        end else begin
            
            lfsr <= {lfsr[14:0], feedback};

            if (!start) begin
                counter <= 0;
                done <= 0;
                // Create pseudo-random delay between ~1s and ~5s
                target <= 29'd25_000_000 + (lfsr * 29'd100_000);
            end else if (start && !done) begin
                counter <= counter + 1;
                if (counter >= target)
                    done <= 1;
            end
        end
    end
endmodule


module timer(
    input clk, reset, start, stop,
    output reg [13:0] ms_time
);
    reg [14:0] cycle_count;
    reg counting;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            cycle_count <= 0;
            ms_time <= 0;
            counting <= 0;
        end else begin
            if (start)
                counting <= 1;
            if (stop)
                counting <= 0;

            if (counting) begin
                cycle_count <= cycle_count + 1;
                if (cycle_count == 25000) begin
                    cycle_count <= 0;
                    ms_time <= ms_time + 1;
                end
            end
        end
    end
endmodule


module seg7_driver (
    input  wire       clk,
    input  wire       reset,
    input  wire       show_error,
    input  wire [13:0] value,   // 0–9999 decimal value
    output reg  [6:0] seg,      // segments a–g
    output reg  [3:0] an,       // digit select (active low)
    output wire [1:0] digit_select  // expose current digit for top module
);

    // Separate registers for each digit (no arrays in Verilog-2001)
    reg [3:0] digit0, digit1, digit2, digit3;
    reg [1:0] current_digit;
    reg [3:0] curr_digit_val;

    assign digit_select = current_digit; // expose current digit

    // Digit extraction
    always @(*) begin
        if (show_error) begin
            // Show "Err" on display: digit3 = E, others = r
            digit3 = 4'hE;   
            digit2 = 4'hF;   
            digit1 = 4'hF;
            digit0 = 4'hF;
        end else begin
            digit3 = (value / 1000) % 10;
            digit2 = (value / 100) % 10;
            digit1 = (value / 10) % 10;
            digit0 = value % 10;
        end
    end

    // Digit multiplexing
    always @(posedge clk or posedge reset) begin
        if (reset)
            current_digit <= 2'b00;
        else
            current_digit <= current_digit + 1;
    end

    always @(*) begin
        case (current_digit)
            2'b00: begin an = 4'b1110; curr_digit_val = digit0; end
            2'b01: begin an = 4'b1101; curr_digit_val = digit1; end
            2'b10: begin an = 4'b1011; curr_digit_val = digit2; end
            2'b11: begin an = 4'b0111; curr_digit_val = digit3; end
        endcase
    end

    // Segment decoder (common cathode, active low)
    always @(*) begin
        case (curr_digit_val)
            4'h0: seg = 7'b1000000;
            4'h1: seg = 7'b1111001;
            4'h2: seg = 7'b0100100;
            4'h3: seg = 7'b0110000;
            4'h4: seg = 7'b0011001;
            4'h5: seg = 7'b0010010;
            4'h6: seg = 7'b0000010;
            4'h7: seg = 7'b1111000;
            4'h8: seg = 7'b0000000;
            4'h9: seg = 7'b0010000;
            4'hA: seg = 7'b0001000;
            4'hB: seg = 7'b0000011;
            4'hC: seg = 7'b1000110;
            4'hD: seg = 7'b0100001;
            4'hE: seg = 7'b0000110; // 'E'
            4'hF: seg = 7'b0110111; // 'r'
            default: seg = 7'b1111111;
        endcase
    end

endmodule



Reference solution:
rtl/generated.v: 
    wire reset = ~rst_n;

    wire [3:0] an;
    wire [3:0] oe;

    reaction_time_top top (
        .ui_in(ui_in),
        .uo_out(uo_out),
        .uio_out(an),
        .uio_oe(oe),
        .clk(clk),
        .rst_n(rst_n)
    );

    assign uio_out[3:0] = an;
    assign uio_out[7:4] = 4'b0000;
    assign uio_oe[3:0]  = oe;
    assign uio_oe[7:4]  = 4'b0000;

    wire unused = (&uio_in) & ena;