You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

module pwm4bit (input wire clock, input wire reset, input wire ena, input wire [3:0] sample, output wire pwm);

    reg [3:0] cntr;
    assign pwm = cntr < sample;

    always @(posedge clock or posedge reset) begin
        if (reset) begin
            cntr <= 4'b0;
        end else if (ena) begin
            cntr <= cntr + 4'b1;
        end
    end
endmodule


module sndgen #(parameter SAMPLE_RATE=16384) (input wire clock, input wire sample_ena, input wire reset, output wire [3:0] sample,
                                             output wire s1_o, output wire s2_o, output wire s3_o, output wire s4_o);

    reg [5:0] sample_int;
    
    localparam TIMESLOT  = SAMPLE_RATE/8;
    localparam BARSLOT   = 16;
    localparam LFSRTIME  = SAMPLE_RATE-14'd1024;
    
    reg [$clog2(SAMPLE_RATE)-1:0]      phacc1;
    reg [$clog2(SAMPLE_RATE)-1:0]      phacc2;
    reg [$clog2(SAMPLE_RATE)-1:0]      phacc3;
    reg [$clog2(SAMPLE_RATE)-1:0]      phacc4;
    reg [$clog2(TIMESLOT)+$clog2(BARSLOT)-1:0] slot_counter;
    reg [3:0]                          mask_1;
    reg                                mask_2;
    
    reg [3:0]                          s1;
    reg [3:0]                          s2;
    reg [3:0]                          s3;
    reg [3:0]                          s4;
    
    reg [1:0]                          c1;
    reg [3:0]                          c2;
    reg [3:0]                          c3;
    reg [3:0]                          c4;
    
    reg [7:0] lfsr;
   
   
    localparam D=1;
    localparam DIS=2;
    localparam E=3;
    localparam F=4;
    localparam FIS=5;
    localparam G=6;
    localparam GIS=7;
    localparam A=8;
    localparam AIS=9;
    localparam H=10;
    localparam C=11;
   
    
    assign sample = sample_int[5:2];
    
    always @(posedge clock or posedge reset) begin
        if (reset) begin
            lfsr <= 8'h01;
        end else if (sample_ena) begin
            lfsr <= lfsr[7] ? {lfsr[6:0],1'b1} ^ 8'b01110000 : {lfsr[6:0],1'b0};
        end
    end
        
    reg [$clog2(SAMPLE_RATE)-1:0] rom_out;
    reg [3:0]                     rom_addr;
        
    always @(*) begin
        case (rom_addr)
            D   : rom_out = SAMPLE_RATE-14'd277;
            //DIS : rom_out = 294;
            E   : rom_out = SAMPLE_RATE-14'd311;
            F   : rom_out = SAMPLE_RATE-14'd330;
            FIS : rom_out = SAMPLE_RATE-14'd369;
            G   : rom_out = SAMPLE_RATE-14'd392;
            GIS : rom_out = SAMPLE_RATE-14'd415;
            //A   : rom_out = 440;
            AIS : rom_out = SAMPLE_RATE-14'd466;
            //H   : rom_out = 494;
            C   : rom_out = SAMPLE_RATE-14'd261;
            default: rom_out = 0;
        endcase
    end
    
    reg [3:0]  llsr;
    reg [3:0]  sample_ena_delay;
    reg [$clog2(SAMPLE_RATE)-1:0] p_c2;
    reg [$clog2(SAMPLE_RATE)-1:0] p_c3;
    reg [$clog2(SAMPLE_RATE)-1:0] p_c4;
    

    always @(posedge clock or posedge reset)
        if (reset) begin
            sample_ena_delay = 4'b0;
            p_c2 <= 0;
            p_c3 <= 0;
            p_c4 <= 0;
            rom_addr <= 0;
        end else begin
            sample_ena_delay = {sample_ena_delay[2:0],sample_ena};
            if (sample_ena_delay[0]) begin
                rom_addr <= c2;
            end
            if (sample_ena_delay[1]) begin
                p_c2 <= rom_out;
                rom_addr <= c3;
            end
            if (sample_ena_delay[2]) begin
                p_c3 <= rom_out;
                rom_addr <= c4;
            end
            if (sample_ena_delay[3]) begin
                p_c4 <= rom_out;
            end
        end
        
    wire [$clog2(BARSLOT)-1:0] bar_counter = slot_counter[$clog2(TIMESLOT)+:$clog2(BARSLOT)];
    
    always @(posedge clock or posedge reset) begin
        if (reset) begin
            slot_counter   <= 0;
            c1             <= 2;
            c2             <= 0;
            c3             <= 0;
            c4             <= 0;
            mask_1         <= 4'h0;
            mask_2         <= 1'b1;
            phacc2         <= 0;
            phacc3         <= 0;
            phacc4         <= 0;
        end else if (sample_ena) begin
            slot_counter <= slot_counter + 1;
            
            /* generate masks at start of new bar */
            if (& slot_counter) begin
                mask_1 <=  lfsr[1+:4];
                mask_2 <=  | (lfsr[1+:3]) ? 1'b0 : 1'b1; /* prevent silence */
            end
            
            if (& slot_counter[$clog2(TIMESLOT)-1:0]) begin
                
                /* generate perc note */
                case (bar_counter[2:0])
                    0 : c1 <= 2'd2;
                    1 : c1 <= 2'd0;
                    2 : c1 <= 2'd1;
                    3 : c1 <= 2'd0;
                    4 : c1 <= 2'd2;
                    5 : c1 <= 2'd1;
                    6 : c1 <= 2'd1;
                    7 : c1 <= 2'd0;
                endcase
                
                /* generate bass note */
                if (bar_counter[1:0] == 2'b11) begin
                    case (bar_counter[3:2])
                        2'b00 : c2 <= D;
                        2'b01 : c2 <= E;
                        2'b10 : c2 <= GIS;
                        2'b11 : c2 <= FIS;
                    endcase
                end
                
                /* generate melody note */
                case ({lfsr[7],lfsr[5],lfsr[3]})
                    3'b100  : begin c3 <= D;   c4 <= FIS;   end
                    3'b101  : begin c3 <= E;   c4 <= GIS;   end
                    3'b110  : begin c3 <= FIS; c4 <= AIS;   end
                    3'b111  : begin c3 <= GIS; c4 <= C;     end
                    default : begin c3 <= 0;   c4 <= 0;     end
                endcase
            end
            
            /* generate tones */
            if (&slot_counter[1:0]) begin
                phacc2 <= (phacc2 + p_c2);
            end
            phacc3 <= (phacc3 + p_c3);
            phacc4 <= (phacc4 + p_c4);

        end
    end
        
    wire three_quarters = (slot_counter[$clog2(TIMESLOT)-1:0] > ((TIMESLOT*3)/4));
        
    always @(*) begin
        /* generate samples */
        if (three_quarters || ({mask_1[0],mask_2} == 2'b0) || (c1 == 2'b0)) begin
            s1 = 4'b1000;
        end else begin
            s1 = (c1 == 2'b1) ? {1'b0,{lfsr[7],lfsr[5],lfsr[3]}} : {lfsr[7],lfsr[5],lfsr[3],lfsr[1]};
        end
        
        s2     = (mask_1[1] & ~three_quarters) ? phacc2[$clog2(SAMPLE_RATE)-1] ? 4'b1100 : 4'b0100 : 4'b1000;
        s3     = mask_1[2]                     ? phacc3[$clog2(SAMPLE_RATE)-1] ? 4'b1100 : 4'b0100 : 4'b1000;
        s4     = mask_1[3]                     ? phacc4[$clog2(SAMPLE_RATE)-1] ? 4'b1100 : 4'b0100 : 4'b1000;
    
        /* mix samples */
        sample_int = s1 + s2 + s3 + s4;
    end

    assign s1_o = {!(({mask_1[0],mask_2} == 2'b0) || (c1 == 2'b0))};
    assign s2_o = {mask_1[1]           ? c2 != 0 : 1'b0};
    assign s3_o = {mask_1[2]           ? c3 != 0 : 1'b0};
    assign s4_o = {mask_1[3]           ? c4 != 0 : 1'b0};

endmodule


module vga(input wire clock,   input wire reset,  input wire ena, 
           input wire [3:0] sample,
           input wire s1, input wire s2, input wire s3, input wire s4,
           output reg hsync,   output reg vsync, 
           output wire hline,
           output reg [1:0] r, output reg [1:0] g, output reg [1:0] b);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




module top(input wire clock, input wire reset, output wire hsync, output wire vsync,
                                               output wire [1:0] r, output wire [1:0] g, output wire [1:0] b,
                                               output wire pwm);
                                                     

    /* prescaler unit */
    /* assume 50 MHz clock */
    localparam CLOCK_FREQUENCY = 50000000;
    localparam SAMPLE_RATE     = 15'd16384;
    
    reg [4:0]  sys_presc;
    
    wire [3:0] sample;
    wire s1, s2, s3, s4;
    
    wire vga_ena = sys_presc[0];
    wire pwm_ena = sys_presc == 5'b0;
    
    
    always @(posedge clock or posedge reset) begin
        if (reset) begin
            sys_presc    <= 5'b0;
        end else begin
            sys_presc    <= sys_presc + 5'b1;
        end
    end
    

    
    wire sample_ena;
    sndgen #(.SAMPLE_RATE(SAMPLE_RATE)) sndgen_inst (.clock(clock), .sample_ena(sample_ena), .reset(reset), .sample(sample), .s1_o(s1), .s2_o(s2), .s3_o(s3), .s4_o(s4));
    pwm4bit    pwm_inst (.clock(clock),.reset(reset),.ena(pwm_ena),.sample(sample),.pwm(pwm));
    vga        vga_inst (.clock(clock),.reset(reset),.ena(vga_ena),.sample(sample),.hline(sample_ena),.hsync(hsync),.vsync(vsync),.r(r),.g(g),.b(b),.s1(s1),.s2(s2),.s3(s3),.s4(s4));

endmodule


`default_nettype none
module tt_um_cfib_demo (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

    wire hsync, vsync, pwm;
    wire [1:0] r, g, b;
    
    assign uo_out[0] = r[1];
    assign uo_out[1] = g[1];
    assign uo_out[2] = b[1];
    assign uo_out[3] = vsync;
    assign uo_out[4] = r[0];
    assign uo_out[5] = g[0];
    assign uo_out[6] = b[0];
    assign uo_out[7] = hsync;
    
    assign uio_oe  = 8'b10000000;
    assign uio_out = {pwm, 7'b0};
    
    wire _used = &{ena, uio_in[7:0], 1'b0};
    wire reset = ~rst_n;

    top top_inst(.clock(clk), .reset(reset),  .hsync(hsync), .vsync(vsync),
                                              .r(r), .g(g), .b(b),
                                              .pwm(pwm));

endmodule


Reference solution:
rtl/generated.v:            

    reg [9:0] x;
    reg [9:0] y;
    
    always @(posedge clock or posedge reset) begin
        if (reset) begin
            x <= 10'b0;
            y <= 10'b0;
        end else if (ena) begin
            x <= x + 10'b1;
            if (x == 10'd799) begin
                x <= 10'b0;
                y <= y + 10'b1;
                if (y == 10'd524) begin
                    y <= 10'b0;
                end
            end
        end
    end 
    
    localparam HVIS=10'd640;
    localparam VVIS=10'd480;
    localparam HFP=10'd16;
    localparam HSYNC=10'd96;
    localparam VFP=10'd10;
    localparam VSYNC=10'd2;
    
    localparam SPACE=10'd26;
    localparam CHANNEL=10'd128;
    
    localparam O=4'd3;
    
    reg  [3:0] sx1, sr1;
    reg  [7:0] x1;
    wire [5:0] bg  = {y[O+2+:2],2'b0,y[O+:2]};
    wire [5:0] nbg = 6'h0;
    reg  [3:0] xmin;
    reg  [3:0] xmax;
    
    localparam START1 = 320-128;
    localparam START2 = 320-128+16;
    localparam END1   = 320+128;
    localparam END2   = 320+128+16;

    assign hline = (x == HVIS & y[0]) & ena;
    
    always @(posedge clock or posedge reset) begin
        if (reset) begin
            x1    <= 8'b0;
            sr1   <= 4'b0;
            sx1   <= 4'b0;
            xmin  <= 4'b0;
            xmax  <= 4'b0;
        end else if (ena) begin

            if (hline) begin
                {sr1, sx1} <= {sx1, sample};
            end

            if (x < START2) begin
                x1           <= 8'b0;
                {xmin, xmax} <= (sx1 < sr1) ? {sx1, sr1} : {sr1, sx1};
            end else begin
                x1           <= x1 + 1'b1;
            end
                
        end
    end
    
    
    localparam DSTART  = 9'd16;
    localparam DDIFF   = 9'd16;
    localparam STARTY  = DSTART;
    localparam STARTY2 = STARTY+DDIFF;
    localparam ENDY    = 9'd480-DSTART;
    localparam ENDY2   = ENDY+DDIFF;
    
    always @(*) begin
        hsync = !(x >= HVIS+HFP && x < HVIS+HFP+HSYNC);
        vsync = !(y >= VVIS+VFP && y < VVIS+VFP+VSYNC);
        {r, g, b} = 6'b0;
        if (x < HVIS && y < VVIS) begin
            {r, g, b} = bg;
        end
        
        if (y >= STARTY && y <= ENDY && x >= START1 && x <= END1) begin
        
            {r, g, b} = (x1[7:4] >= xmin  && x1 <= {xmax,4'b0011})   ? 6'b001100 :
                        (x[3:0] == 4'b0000 || y[3:0] == 4'b0000)     ? 6'b001000 : 6'b000100;
                        
            if (y > STARTY && y < STARTY+16) begin
                if (x >  START1    && x < START1+16) begin
                    g[1] = s1;
                end
                if (x >  START1+16  && x < START1+32) begin
                    g[1] = s2;
                end
                if (x >  START1+32 && x < START1+48) begin
                    g[1] = s3;
                end
                if (x >  START1+48 && x < START1+64) begin
                    g[1] = s4;
                end
            end
                        
        end else if (y >= STARTY2 && y < ENDY2 && x >= START2 && x < END2) begin
            {r, g, b} = {1'b0,bg[5],1'b0,bg[3],1'b0,bg[1]};
        end
    end