You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Alexander Krassovsky
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

// Github username is save-buffer
module tt_um_save_buffer_hash_table (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




/*
 * Copyright (c) 2024 Alexander Krassovsky
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module probing_mem (
    input wire 	      clk,
    input wire [2:0]  hash,
    input wire [3:0]  key,
    input wire [3:0]  val,
    input wire [1:0]  cmd,
    input wire 	      go,
    input wire 	      rst_n,
    output reg [1:0]  status,
    output reg [3:0]  out
);
   reg [8:0]   mem[0:7];
   reg [3:0]   cursor;
   reg 	       state;

   reg 	       go_ok; // To make sure user brings `go` low between requests
   reg [3:0]   key_saved;
   reg [3:0]   val_saved;
   reg [2:0]   hash_saved;

   integer     i;

   localparam CMD_LOOKUP = 0;
   localparam CMD_INSERT = 1;
   localparam CMD_DELETE = 2;

   localparam STATE_IDLE = 0;
   localparam STATE_PROBING = 1;

   localparam STATUS_OK = 0;
   localparam STATUS_FULL = 1;
   localparam STATUS_NOTFOUND = 2;
   localparam STATUS_BUSY = 3;

   always @(posedge clk) begin
       if (!rst_n) begin
	   for (i = 0; i < 8; i = i + 1) begin
	       mem[i] <= 0;
	   end
	   key_saved <= 0;
	   val_saved <= 0;
	   hash_saved <= 0;
	   cursor <= 0;
	   go_ok <= 1;
	   state <= STATE_IDLE;
	   status <= STATUS_OK;
	   out <= 0;
       end
       else begin
	   case (state)
	       STATE_IDLE: begin
		   if (!go && !go_ok) begin
		       go_ok <= 1;
		   end
		   else if (go && go_ok) begin
		       key_saved <= key;
		       val_saved <= val;
		       hash_saved <= hash;
		       cursor <= {1'b0, hash[2:0]};
		       state <= STATE_PROBING;
		       status <= STATUS_BUSY;
		       go_ok <= 0;
		   end
	       end
	       STATE_PROBING: begin
		   if (cursor[3] && cursor[2:0] == hash_saved[2:0]) begin // Did a full loop
		       status <= cmd == CMD_INSERT ? STATUS_FULL : STATUS_NOTFOUND;
		       state <= STATE_IDLE;
		   end
		   else if ((cmd == CMD_LOOKUP || cmd == CMD_DELETE) && mem[cursor[2:0]][8] && mem[cursor[2:0]][7:4] == key_saved) begin // Found the key!
		       out <= mem[cursor[2:0]][3:0];
		       if (cmd == CMD_DELETE)
			 mem[cursor[2:0]][8] <= 0;
		       state <= STATE_IDLE;
		       status <= STATUS_OK;
		   end
		   else if (cmd == CMD_INSERT && (!mem[cursor[2:0]][8] || mem[cursor[2:0]][7:4] == key_saved)) begin // Found an empty slot
		       mem[cursor[2:0]][8] <= 1;
		       mem[cursor[2:0]][7:4] <= key_saved;
		       mem[cursor[2:0]][3:0] <= val_saved;
		       out <= mem[cursor[2:0]][3:0];
		       state <= STATE_IDLE;
		       status <= STATUS_OK;
		   end
		   else begin
		       cursor <= cursor + 1;
		   end
	       end
	   endcase
       end
   end
endmodule


Reference solution:
rtl/generated.v:    assign uio_oe[0] = 0;
   assign uio_oe[1] = 0;
   assign uio_oe[2] = 0;
   assign uio_oe[5:3] = 0;
   assign uio_oe[6] = 1;
   assign uio_oe[7] = 1;

   wire [1:0] 	      cmd = uio_in[1:0];
   wire 	      go = uio_in[2];

   reg [1:0] 	      status;
   assign uio_out[7:6] = status;
   assign uio_out[5:0] = 0;

   wire [3:0] 	      key = ui_in[7:4];
   wire [3:0] 	      val = ui_in[3:0];
   wire [2:0] 	      hash = key[3:1] ^ (key[2:0] & {key[3], key[3], key[3]});

   reg [3:0] 	      out;
   assign uo_out[3:0] = out[3:0];
   assign uo_out[7:4] = 0;

   probing_mem tb (
       .clk(clk),
       .hash(hash),
       .key(key),
       .val(val),
       .cmd(cmd),
       .go(go),
       .rst_n(rst_n),
       .status(status),
       .out(out)
   );

   // List all unused inputs to prevent warnings
   wire _unused = &{ena, 1'b0};