You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2025 Zedulo.com
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none


module tt_um_zedulo_spitest1 (
    input  wire [7:0] ui_in /*verilator public*/,    // Dedicated inputs
    output wire [7:0] uo_out /*verilator public*/,   // Dedicated outputs
    input  wire [7:0] uio_in /*verilator public*/,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk /*verilator public*/,      // clock
    input  wire       rst_n /*verilator public*/     // reset_n - low to reset
);

	// Assign / list all unused inputs to prevent warnings
	assign uio_out = 0;
	assign uio_oe  = 0;
	wire _unused = &{ena, uio_in, ui_in[7:3], 1'b0};

	reg [3:0] sub_clk; //clk=100MHz, sub_clk[0]=50MHz, sub_clk[1]=25MHz, sub_clk[2]=12.5MHz sub_clk[3]=6.25MHz


	//assign uo_out[0] =  //miso
	//assign uo_out[1] =  //debug
	assign uo_out[2] = clk; //clock mirror
	assign uo_out[5:3] = 3'h0; //unused
	//assign uo_out[6] = //status
	//assign uo_out[7] = //reset status

	wire spi_mosi, spi_clk, spi_cs;
	assign spi_mosi = ui_in[0];
	assign spi_clk  = ui_in[1];
	assign spi_cs   = ui_in[2];

/*      input  wire clk
        input  wire rst_n
        input  wire spi_mosi
        input  wire wspi_clk
        input  wire wspi_cs
        output wire wspi_miso
        output wire wled_status
        output wire wled_reset
        output wire wdebug */
	//                    clk  reset  mosi      spi clk   spi cs    miso       status     reset      debug
	nanospi_top spidevice(clk, rst_n, spi_mosi, spi_clk, spi_cs, uo_out[0], uo_out[6], uo_out[7], uo_out[1]);

endmodule


/*
 * Copyright (c) 2025 Zedulo.com
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 Nano SPI controller, all SPI commands are 4 bit long, arg is 4 bits
 Returns top bits as command with bit 7 inverted.
	CMD:	ARG:		Definition:
	STATUS	field		Returns status for the specific field
	SET	IO pin		Sets the specified output pin
	CLEAR	IO pin		Clears the specified output pin
	TARGET	reg/addr/io	Specify the target for read/write operations
	WRITE	data		Writes to the set target
	READ	n/a		Reads from the set target

*/


`define CMD_STATUS 4'h0
`define CMD_SET 4'h1
`define CMD_CLEAR 4'h2
`define CMD_TARGET 4'h3
`define CMD_WRITE 4'h4
`define CMD_READ 4'h5

`default_nettype none


module nanospi_top (
	input  wire clk /*verilator public*/,	// clock
	input  wire rst_n /*verilator public*/,	// reset_n - low to reset

	input  wire spi_mosi /*verilator public*/,    	//
	input  wire wspi_clk /*verilator public*/,    	//
	input  wire wspi_cs /*verilator public*/,    	//
	output wire wspi_miso /*verilator public*/,   	//	

	output wire wled_status /*verilator public*/,   	//optional
	output wire wled_reset /*verilator public*/,   	//optional
	output wire wdebug /*verilator public*/   	//optional
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule



 


Reference solution:
rtl/generated.v: 
	reg spi_clk_buff[1:0];
	wire spi_clk;
	assign spi_clk = spi_clk_buff[0];
	wire spi_clk_stabile;
	assign spi_clk_stabile = spi_clk_buff[1] == spi_clk_buff[0];

	reg spi_miso;
	assign wspi_miso = spi_miso;	
	
	reg led_status;
	assign wled_status = led_status;
	reg led_reset;
	assign wled_reset = led_reset;
	reg debug;
	assign wdebug = debug;

////////////////////////// TT definitions above, don't change!


	reg data_ready; //data is ready for use
	reg arm_tx; //put out first tx bit on miso
	reg spi_completed; //tranmission completed flag, rx data in data_reg
	reg prev_spi_clk; //last state of cpi_clk, to detect edges
	reg [7:0] main_reg; //main shiftreg
	reg [2:0] spi_count;
	
	reg target; //set by TARGET, decides what bits should be written by WRITE
	reg [7:0] storage; //let us save a byte for READ/WRITE access, high/low bits set by TARGET
	

	always @ (posedge clk)
	begin
		//$strobe("spi_clk %d", spi_clk);
		
		//reset sequence
		if(rst_n == 0)begin //0 == reset
			//$display("Reset");
			//SPI regs
			main_reg <= 8'h59;  //no need to clear other regs
			led_reset <= 1'h1; //LED2 on
			led_status <= 1'h1;			
			debug <= 0;
		end
		else if(wspi_cs == 1'b1) begin
			prev_spi_clk <= 1;
			spi_completed <= 0;
			arm_tx <= 1;
			spi_clk_buff[0] <= wspi_clk;
			spi_clk_buff[1] <= wspi_clk;
			data_ready <= 0;
			spi_count <= 0;
		end
		//normal operation
		else begin
			spi_clk_buff[0] <= wspi_clk;
			spi_clk_buff[1] <= spi_clk_buff[0];
			
			led_reset <= 1'h0; //LED2 off			
			
			if(data_ready == 1)begin 
			
				`ifdef _VERILATOR
				$display("->Target exec. reg %h", main_reg[7:0]);
				//$display("Exec CMD %h with arg %h", main_reg[7:4], main_reg[3:0]);
				`endif

				data_ready <= 0;				
				//main_reg[7:0] <= 8'h99;
				arm_tx <= 1;
				debug <= 1'b0;

				case (main_reg[7:4])
					`CMD_STATUS : begin
						main_reg[0] <= 1'h0; //input_pin;
						main_reg[3:1] <= 3'h0;
						//$display("STATUS arg %h", data_reg[3:0]);
					end

					`CMD_SET : begin
						main_reg[3:0] <= 4'h1;
						//output_pin <= 1;
						led_status <= 1'h0; //LED1 on
						//$display("SET arg %h", data_reg[3:0]);
					end

					`CMD_CLEAR : begin
						main_reg[3:0] <= 4'h1;
						//output_pin <= 0;
						led_status <= 1'h1; //LED1 off
						//$display("CLEAR arg %h", data_reg[3:0]);
					end

					`CMD_TARGET : begin
						main_reg[3:0] <= 4'h1;
						target <= main_reg[0];
						//$display("TARGET arg %h", data_reg[3:0]);
					end

					`CMD_READ : begin
						if(target == 0)main_reg[3:0] <= storage[3:0];
						else main_reg[3:0] <= storage[7:4];
						//$display("READ arg %h", data_reg[3:0]);
					end

					`CMD_WRITE : begin
						main_reg[3:0] <= 4'h1;
						if(target == 0)storage[3:0] <= main_reg[3:0];
						else storage[7:4] <= main_reg[3:0];
						//$display("WRITE arg %h", data_reg[3:0]);
					end
					
					default : begin //do nothing
						//$display("UNKNOWN CMD, arg %h", data_reg[3:0]);
						main_reg[3:0] <= 4'hf;
					end
				endcase
			end //
			else if(spi_completed == 1)begin 
				//spi_count <= 0;
				spi_completed <= 0;
				data_ready <= 1;
			end
			else if(arm_tx == 1)begin
				spi_miso <= main_reg[7];
				arm_tx <= 0;
			end
			else if(spi_clk_stabile == 1 & spi_clk == 1 & prev_spi_clk == 0)begin
				prev_spi_clk <= 1;

				main_reg[7] <= main_reg[6];
				main_reg[6] <= main_reg[5];
				main_reg[5] <= main_reg[4];
				main_reg[4] <= main_reg[3];
				main_reg[3] <= main_reg[2];
				main_reg[2] <= main_reg[1];
				main_reg[1] <= main_reg[0];
				main_reg[0] <= spi_mosi;

				if(spi_count == 7)begin 
					led_status <= 1'h0; //LED1 off
					spi_completed <= 1;
					debug <= 1'b1;
					//spi_count <= 3'h0;
				end
				
				spi_count <= spi_count + 3'h1;
			end
			// SPI Clock low, put out new data
			else if(spi_clk_stabile == 1 & spi_clk == 0 & prev_spi_clk == 1)begin
				spi_miso <= main_reg[7];
				prev_spi_clk <= 0;
			end
			else begin				
				spi_completed <= spi_completed;
				prev_spi_clk <= prev_spi_clk;
				spi_count <= spi_count;
				spi_miso <= spi_miso;
				arm_tx <= arm_tx;
				debug <= debug;
			end
			
		end

	end