You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.


`default_nettype none

module tt_um_otp_encryptor (    
    input  [7:0] ui_in,    // Dedicated inputs
    output [7:0] uo_out,   // Dedicated outputs
/* verilator lint_off UNUSEDSIGNAL */
    input  [7:0] uio_in,   // IOs: Input path
/* verilator lint_on UNUSEDSIGNAL */
    output [7:0] uio_out,  // IOs: Output path
    output [7:0] uio_oe,
    input        ena,      // will go high when the design is enabled
    input        clk,      // clock
    input        rst_n     // reset_n - low to reset
        );

wire [7:0] data;
wire [7:0] pad_gen;
wire [2:0] r_num;
reg[2:0] count;
wire decrypt;
wire reset;

reg [7:0] out;
reg [2:0] index_out;


// io
assign data = ui_in[7:0];
assign decrypt = uio_in[0];
assign r_num = uio_in[3:1];
assign reset = ~rst_n;

assign uo_out[7:0] = out[7:0];
assign uio_out[6:4] = index_out[2:0];
	
assign uio_out[7] = 1'b0;
assign uio_out[3:0] = 4'h0;
assign uio_oe = 8'b11110000;

// registers	
reg[7:0] mem[0:7];
integer i;

LFSR_PRNG rng(
    .clk(clk),
    .rst(reset),
    .prn(pad_gen));

//assign out = ena ? (decrypt ? (pad_read ^ data) : (pad_gen ^ data)) : 8'h00;
	 
always @ (posedge clk, posedge reset) begin
	if (reset) begin
		count <= 3'h0;
		out <= 8'h00;
		index_out <= 3'h0;
		
		for(i = 0; i < 8; i = i + 1) begin
			mem[i] <= 8'h00;
		end
		
	end
	else if (ena) begin
		if (decrypt) begin
			index_out <= 3'h0;
			out <= mem[r_num] ^ data;
		end
		else begin // encrypt
			if(count == 3'b111) begin
				count <= 3'b000;
			end
			else begin
				count <= count + 3'h1;
			end
			out <= pad_gen ^ data;
			mem[count] <= pad_gen;
			index_out <= count;
		end
	end
	else out <= 8'h00;
end
    
endmodule


module LFSR_PRNG (
    clk,
    rst,
    prn);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




Reference solution:
rtl/generated.v: 
    input clk;
    input rst;
    output [7:0] prn;

    reg [31:0] D32 = 32'hbdca2c92; //NEVER 000000

    assign prn[0] = D32[23];
    assign prn[1] = D32[17];
    assign prn[2] = D32[13];
	 assign prn[3] = D32[11];
	 assign prn[4] = D32[7];
	 assign prn[5] = D32[5];
	 assign prn[6] = D32[3];
	 assign prn[7] = D32[2];

    always @ (posedge rst or posedge clk)
    if (rst)
        begin
            D32 <= 32'hbdca2c92;
        end
    else
        begin
            D32[1] <= D32[0];
            D32[2] <= D32[1];
            D32[3] <= D32[2];
            D32[4] <= D32[3];
            D32[5] <= D32[4];
				D32[6] <= D32[5];
				D32[7] <= D32[6];
				D32[8] <= D32[7];
				D32[9] <= D32[8];
				D32[10] <= D32[9];
				D32[11] <= D32[10];
				D32[12] <= D32[11];
				D32[13] <= D32[12];
				D32[14] <= D32[13];
				D32[15] <= D32[14];
            D32[16] <= D32[15];
				D32[17] <= D32[16];
            D32[18] <= D32[17];
            D32[19] <= D32[18];
            D32[20] <= D32[19];
            D32[21] <= D32[20];
				D32[22] <= D32[21];
				D32[23] <= D32[22];
				D32[24] <= D32[23];
				D32[25] <= D32[24];
				D32[26] <= D32[25];
				D32[27] <= D32[26];
				D32[28] <= D32[27];
				D32[29] <= D32[28];
				D32[30] <= D32[29];
				D32[31] <= D32[30];
				D32[0] <= ~(~(~(D32[31] ^ D32[21]) ^ D32[1]) ^ D32[0]);
        end