You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Your Name
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_ccu_goatgate (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

  // All output pins must be assigned. If not used, assign to 0.
    assign uo_out[3:0] = dout;
    assign uo_out[7:4] = 0;
    assign uio_out = 0;
    assign uio_oe  = 0;
    
    // I/O definitions
    wire [3:0] din = ui_in[3:0];
    wire [3:0] kin = ui_in[7:4];
    wire [3:0] dout;
    
  // List all unused inputs to prevent warnings
  wire _unused = &{ena, 1'b0};
  ccu ccu_inst (
                          .clk(clk),
                          .reset(rst_n),
                          .data_in(din),
                          .key(kin),
                          .data_out1(dout)
                          
                       );
endmodule


module ccu(
    input wire [3:0] data_in,   // 4-bit input data (plaintext)
    input wire [3:0] key,       // 4-bit key for encryption
    input wire clk,             // Clock signal
    input wire reset,           // Reset signal
    output wire [3:0] data_out1 // 4-bit output data (ciphertext with key1)
    
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule





Reference solution:
rtl/generated.v: 
    reg [3:0] key1, key2, key3;
    reg [3:0] ciphered_data;

    // Function to derive keys from the original key using simple XOR and rotations
    // Key derivation example: Rotate key and XOR with constants
    always @(*) begin
        key1 = key;                // First key is the original key
        key2 = {key[2:0], key[3]}; // Rotate left by 1 bit
        key3 = key ^ 4'b1010;      // XOR with a constant value (for example, 1010)
    end

    // Process the input data on the rising edge of the clock
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            ciphered_data <= 4'b0000;  // Reset to 0 when reset signal is high
            
        end else begin
            // Encrypt the data using the derived keys
          	ciphered_data <= ((data_in ^ key1)^ key2)^ key3;  // XOR with key1
            
        end
    end

    // Output the ciphered data
    assign data_out1 = ciphered_data;