You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

module tt_um_CKPope_top 
(
    input  wire [7:0] ui_in,    // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
    output wire [7:0] uo_out,   // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
    input  wire [7:0] uio_in,   // IOs: Input path for FSM Control MOTION control input plus spares
    output wire [7:0] uio_out,  // IOs: Output path (not used)
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output) - TIED For UIO BEING INPUTS ONLY
    input  wire       ena,      // will go high when the design is enabled
    input  wire       clk,      // clock
// ---------------------------------------------------------------
//outputs for simulation diagnostics
//	output wire	init_regs_out,
//	output wire load_xy_out,
//	output wire [3:0] x_target_reg_out,
//	output wire [3:0] y_target_reg_out,
//	output wire x_comp_eq_out, x_comp_gt_out, x_comp_lt_out,
//	output wire x_counten_out, x_count_up1_dwn0_out,
//	output wire y_comp_eq_out, y_comp_gt_out, y_comp_lt_out,
//	output wire y_counten_out, y_count_up1_dwn0_out,
//	output wire reset_n_out, reset_out, motion_out,
//-- --------------------------------------------------------------
   input  wire rst_n     // reset_n - low to reset
);// Quartus Prime Verilog Template

//----------------------------------------------------------------
//Local tile signal Inputs
wire clock, sync_reset, reset_n;

//FSM Initialization of external registers
wire init_regs;

//FSM control inputs;
wire motion_inp,sync_motion;

// x-y target data inputs
wire [3:0] x_target;
wire [3:0] y_target;

// x-y target_register signals
wire [3:0] x_target_reg;
wire [3:0] y_target_reg;
wire load_xy;

// x-y counter signals
wire x_counten, x_count_up1_dwn0, y_counten, y_count_up1_dwn0;
wire [3:0] x_pos;
wire [3:0] y_pos;

// X-Y Counter comparator signals
wire x_comp_eq, x_comp_gt, x_comp_lt;
wire y_comp_eq, y_comp_gt, y_comp_lt;

//----------------------------------------------------------------
// make Connections to infrastructure signals. clock can only run when the module is enabled (selected)
assign clock 	= clk;
assign reset_n =  rst_n;

//----------------------------------------------------------------
// make Connections to uio, ui, uo ports
assign motion_inp = (uio_in[0]);
assign x_target = ui_in[7:4];
assign y_target = ui_in[3:0];
assign uo_out[7:4] = x_pos[3:0];
assign uo_out[3:0] = y_pos[3:0];

// TIE OFF Unused uio ports
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
//----------------------------------------------------------------
// module instantiation

// Input Synchronizer
input_synch buttons
(.clk (clock), .reset(!reset_n), .sync_reset(sync_reset), .sync_in(motion_inp),  .sync_out (sync_motion));

//FSM:
Mealy_SM xycontroller 
(.clk(clock), .reset(!reset_n | sync_reset), .motion(sync_motion), .init(init_regs),
.x_comp_eq(x_comp_eq), .x_comp_gt(x_comp_gt), .x_comp_lt(x_comp_lt), .x_count_en(x_counten), .x_up1_dwn0(x_count_up1_dwn0),
.y_comp_eq(y_comp_eq), .y_comp_gt(y_comp_gt), .y_comp_lt(y_comp_lt), .y_count_en(y_counten), .y_up1_dwn0(y_count_up1_dwn0), 
.capt_enbl(load_xy));

//X, Y Target Capture Registers
target_reg x_treg (.clk (clock), .load (load_xy), .data (x_target), .reset ((sync_reset | init_regs)), .target_reg (x_target_reg));
target_reg y_treg (.clk (clock), .load (load_xy), .data (y_target), .reset ((sync_reset | init_regs)), .target_reg (y_target_reg));	 	

//X, Y Counters:
ud_counter x_counter (.clk (clock), .count_en (x_counten), .count_up1_dwn0 (x_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (x_pos[3:0]));
ud_counter y_counter (.clk (clock), .count_en (y_counten), .count_up1_dwn0 (y_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (y_pos[3:0]));	 	

// X, Y Comparators
Compx4 x_comp (.a_hex(x_pos), .b_hex(x_target_reg), .a_eq_b(x_comp_eq), .a_gt_b(x_comp_gt), .a_lt_b(x_comp_lt)); 
Compx4 y_comp (.a_hex(y_pos), .b_hex(y_target_reg), .a_eq_b(y_comp_eq), .a_gt_b(y_comp_gt), .a_lt_b(y_comp_lt)); 

//----------------------------------------------------------------
// temporary connections for diagnostics outputs
//assign x_target_reg_out = 	x_target_reg;
//assign y_target_reg_out = 	y_target_reg;
//assign load_xy_out = load_xy;
//assign x_counten_out = x_counten; 
//assign x_comp_eq_out = x_comp_eq; 
//assign x_comp_gt_out = x_comp_gt; 
//assign x_comp_lt_out = x_comp_lt;
//assign x_count_up1_dwn0_out = x_count_up1_dwn0;
//assign y_counten_out = y_counten; 
//assign y_comp_eq_out = y_comp_eq; 
//assign y_comp_gt_out = y_comp_gt; 
//assign y_comp_lt_out = y_comp_lt;
//assign y_count_up1_dwn0_out = y_count_up1_dwn0;
//assign reset_out = sync_reset;
//assign reset_n_out = reset_n;
//assign init_regs_out = init_regs;
//assign motion_out= sync_motion;

endmodule





module Compx1
(
   input a,
	input b,
 	output reg aeqb,		
	output reg agtb,		
	output reg altb		
	
); 

always @(*)
begin
	aeqb = (a & b) | ((!(a)) & (!(b)));
	
	agtb = a & (!(b));
		
	altb = (!(a)) & b ;
end		
endmodule



module Compx4
(
   input [3:0] a_hex,
	input [3:0] b_hex,
 	output reg a_eq_b,		
	output reg a_gt_b,		
	output reg a_lt_b	
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




module Mealy_SM
(
  input  clk,
  input  reset,	 
  input  motion,
  input  x_comp_eq,
  input	x_comp_gt,
  input  x_comp_lt,
  			 
  input  y_comp_eq,
  input	y_comp_gt,
  input  y_comp_lt,
  
  output reg init,
  output reg x_count_en,
  output reg x_up1_dwn0,
  output reg y_count_en,
  output reg y_up1_dwn0,
  output reg capt_enbl		 
);

  parameter INITIALIZE1 =3'b000,
				INITIALIZE2 =3'b001,
				AT_REST		=3'b010,
				CAPTURE_XY	=3'b011,
				IN_MOTION	=3'b100,
				XY_REACHED	=3'b101;

 // RANGE of STATE VALUES (INITIALIZE, AT_REST, CAPTURE_XY, IN_MOTION, XY_REACHED);

   reg [2:0] current_state, next_state;		// current_state, next_state registers of type STATES


// STATE MACHINE: MEALY Type

//REGISTER SECTION OF STATE MACHINE

always @(posedge clk, posedge reset) 	// sequential logic to latch the FSM state (FSM REGISTER SECTION)
   begin
		if (reset==1) 
	      current_state <= INITIALIZE1;
		else   
         current_state <= next_state; 	// on the rising edge of clock the current state is updated with next state value
   end	

	//TRANSITION SECTION OF STATE MACHINE
always @(*) 		 							// logic to determine next state. (FSM TRANSITION SECTION)
begin
     case (current_state)	  
				INITIALIZE1: 
				begin		
               next_state = INITIALIZE2;
            end
				
				INITIALIZE2: 
				begin		
               next_state = AT_REST;
            end
				
				AT_REST: 
				begin		
					if (motion) 
               next_state = CAPTURE_XY;
					else 
               next_state = AT_REST;
            end
				
				CAPTURE_XY: 
				begin		
					if (motion) 
               next_state = CAPTURE_XY; // stay here until MOTION goes off. Then go to IN_MOTION
					else
               next_state = IN_MOTION;
            end
				
				IN_MOTION:
				begin
					if ((x_comp_eq) & (y_comp_eq))
               next_state = XY_REACHED;
					else
					next_state = IN_MOTION;
            end

           XY_REACHED:
			  begin
					next_state = AT_REST;
				end
							 
			  default:
               next_state = AT_REST;
 		endcase
 end

 
//DECODER SECTION OF STATE MACHINE
 always @(*)			  							// logic to drive MEALY FSM outputs (FSM DECODER SECTION)
 begin
	if (current_state == INITIALIZE1)		// force outside counters to be initialized to zero for first state
			begin
				init			= 1'b1;
				x_count_en 	= 1'b0;
				x_up1_dwn0  = 1'b0;				
				y_count_en 	= 1'b0;
				y_up1_dwn0  = 1'b0;				
				capt_enbl 	= 1'b0;
			end	

	else if (current_state == INITIALIZE2) // keep outside counters initialized to zero for another state
			begin
				init			= 1'b0;
				x_count_en 	= 1'b0;
				x_up1_dwn0  = 1'b0;				
				y_count_en 	= 1'b0;
				y_up1_dwn0  = 1'b0;				
				capt_enbl 	= 1'b0;
			end	

	else if (current_state == CAPTURE_XY) // motion button has been pressed. activate outside x/y register capture enables
			begin
				init			= 1'b0;
				x_count_en 	= 1'b0;
				x_up1_dwn0  = 1'b0;				
				y_count_en 	= 1'b0; 
				y_up1_dwn0  = 1'b0;				
				capt_enbl 	= 1'b1;
			end	
	else if (current_state == IN_MOTION) // motion input button release. x/Y motion is now enabled
			begin
				init			= 1'b0;
				x_count_en 	= ((x_comp_gt) | (x_comp_lt));
				x_up1_dwn0  = x_comp_lt;				
				y_count_en 	= ((y_comp_gt) | (y_comp_lt));
				y_up1_dwn0  = y_comp_lt;
				capt_enbl 	= 1'b0;
			end
	else											// default case (used in AT_REST and XY_REACHED states), is to deactivate all FSM outputs.
			begin
				init			= 1'b0;
				x_count_en 	= 1'b0;
				x_up1_dwn0  = 1'b0;				
				y_count_en 	= 1'b0;
				y_up1_dwn0  = 1'b0;				
				capt_enbl 	= 1'b0;
			end
end
endmodule


module input_synch
(
	input wire clk,
	input wire reset,
	output wire sync_reset,
	input wire sync_in,
	output wire sync_out
);
	reg [1:0] chain0, chain1;
	
	always @ (posedge clk)
	begin
		chain0[1:0] <= {chain0[0], reset};
		chain1[1:0] <= {chain1[0], sync_in};
	end	

	assign sync_reset = (chain0[1]);
	assign sync_out	= (chain1[1]);
	
endmodule


module target_reg
(
	input wire clk, 
	input wire load, 
	input wire [3:0] data,
	input wire reset,
	output reg [3:0] target_reg
);

	// Reset if needed, increment or decrement if counter is not saturated
	always @ (posedge clk)
	begin
		if (reset)
			target_reg <= 4'b0000;
		else if (load)
		   target_reg <= data ;
	end

endmodule


module ud_counter
(
	input wire clk, 
	input wire count_en, 
	input wire count_up1_dwn0, 
	input wire reset,
	output reg [3:0] count
);

	// Reset if needed, increment or decrement if counter is not saturated
	always @ (posedge clk)
	begin
		if (reset)
			count <= 4'b0000;
		else if ((count_en & count_up1_dwn0) & (count!= 4'b1111))
			count <= count + 4'd0001;
		else if ((count_en & (!count_up1_dwn0)) & (count!= 4'b0000))
			count <= count - 4'd0001;
	end

endmodule


Reference solution:
rtl/generated.v:  
	
	wire [3:0] aeqb;	
	wire [3:0] agtb;	
	wire [3:0] altb;	

// connections to single bit comparators
	Compx1	Bit3_COMP(.a(a_hex[3]), .b(b_hex[3]), .aeqb(aeqb[3]), .agtb(agtb[3]), .altb(altb[3]));
	Compx1	Bit2_COMP(.a(a_hex[2]), .b(b_hex[2]), .aeqb(aeqb[2]), .agtb(agtb[2]), .altb(altb[2]));
	Compx1	Bit1_COMP(.a(a_hex[1]), .b(b_hex[1]), .aeqb(aeqb[1]), .agtb(agtb[1]), .altb(altb[1]));
	Compx1	Bit0_COMP(.a(a_hex[0]), .b(b_hex[0]), .aeqb(aeqb[0]), .agtb(agtb[0]), .altb(altb[0]));

		always @(*)
		begin
			a_eq_b = aeqb[3] & aeqb[2] & aeqb[1] & aeqb[0];
	
			a_gt_b = agtb[3] | (aeqb[3] & agtb[2]) | (aeqb[3] & aeqb[2] & agtb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & agtb[0]);
	
			a_lt_b = altb[3] | (aeqb[3] & altb[2]) | (aeqb[3] & aeqb[2] & altb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & altb[0]);
		end