You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Your Name
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_chrishtet_LIF (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




`timescale 1ns / 1ps
// Leaky Integrate-and-Fire with post-spike max, refractory down to -THRESH
// Fixed-point: Q4.4 on signed 8-bit: [-128, +127]; 1.0 = 16
// Range ≈ [-8.0, +7.9375]

module lif_core #(
    parameter signed [7:0] THRESH_Q4_4     = 8'sd64,   // +4.0
    parameter integer      LSH             = 3,        // leak shift: leak = V >>> LSH
    parameter signed [7:0] V_MAX_Q4_4      = 8'sd127,  // set V to max on spike
    parameter signed [7:0] NEG_DRIVE_Q4_4  = 8'sd16    // extra negative drive during refractory (1.0)
)(
    input  wire                 clk, rst_n, en,
    input  wire signed  [7:0]   I_q4_4,     // input increment (Q4.4)
    output reg                  spike,      // 1-cycle pulse on spike
    output reg                  refractory, // high while in refractory
    output reg  signed  [7:0]   V_q4_4,     // membrane potential (Q4.4)
    output wire         [3:0]   V_dbg       // MSBs for quick probing
);
    // ---- helpers ----
    wire signed [7:0] leak = V_q4_4 >>> LSH;

    // normal path (integrate + leak)
    wire signed [8:0] V_norm_wide = V_q4_4 + I_q4_4 - leak;

    // refractory path (ignore input, push down)
    wire signed [8:0] V_refr_wide = V_q4_4 - leak - NEG_DRIVE_Q4_4;

    // saturate to signed 8-bit
    function signed [7:0] sat8;
        input signed [8:0] x;
        begin
            if      (x >  9'sd127)  sat8 = 8'sd127;
            else if (x < -9'sd128)  sat8 = -8'sd128;
            else                    sat8 = x[7:0];
        end
    endfunction

    wire signed [7:0] V_norm_next  = sat8(V_norm_wide);
    wire signed [7:0] V_refr_next  = sat8(V_refr_wide);

    // Spike detection only when not refractory
    wire will_spike = (!refractory) && (V_norm_next >= THRESH_Q4_4);

    assign V_dbg = V_q4_4[7:4];

    // ---- sequential ----
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            V_q4_4     <= 8'sd0;
            spike      <= 1'b0;
            refractory <= 1'b0;
        end else begin
            spike <= 1'b0; // default

            if (en) begin
                if (refractory) begin
                    V_q4_4 <= V_refr_next;
                    if (V_refr_next <= -THRESH_Q4_4)// Exit refr IF V <= -THRESH
                        refractory <= 1'b0;
                end else if (will_spike) begin  // Spike and set V to max, then enter refractory
                    spike      <= 1'b1;
                    V_q4_4     <= V_MAX_Q4_4;
                    refractory <= 1'b1;
                end else begin                  // Normal integrate+leak
                    V_q4_4     <= V_norm_next;
                    refractory <= 1'b0;
                end
            end
        end
    end

endmodule


Reference solution:
rtl/generated.v: 
  // All output pins must be assigned. If not used, assign to 0.

    wire signed [7:0] I_q4_4 = ui_in;   // use all 8 ui_in bits as signed Q4.4 input
    wire              lif_en = ena;     // TT 'ena' is always 1 when powered

    // Wires from core
    wire        spike;
    wire        refractory;
    wire signed [7:0] V_q4_4;
    wire [3:0]  V_dbg;

    // Instantiate the neuron core
    lif_core #(
        .THRESH_Q4_4(8'sd64),       // +4.0 (Q4.4)
        .LSH(3),
        .V_MAX_Q4_4(8'sd127),
        .NEG_DRIVE_Q4_4(8'sd16)
    ) u_core (
        .clk(clk),
        .rst_n(rst_n),
        .en(lif_en),
        .I_q4_4(I_q4_4),
        .spike(spike),
        .refractory(refractory),
        .V_q4_4(V_q4_4),
        .V_dbg(V_dbg)
    );

    // Driving all required outputs (no undriven pins!)
    assign uo_out[0]   = spike;
    assign uo_out[1]   = refractory;
    assign uo_out[5:2] = V_dbg;         // 4-bit scope view of V[7:4]
    assign uo_out[7:6] = 2'b00;
    // Bidir IOs not used
  assign uio_out = 0;
  assign uio_oe  = 0;

  // List all unused inputs to prevent warnings
  wire _unused = &{uio_in, 1'b0};