You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

module tt_um_stopwatchtop (
    input  wire [7:0] ui_in,    // user inputs
    output wire [7:0] uo_out,   // user outputs
    input  wire [7:0] uio_in,   // bidir inputs
    output wire [7:0] uio_out,  // bidir outputs
    output wire [7:0] uio_oe,   // bidir enables
    input  wire       ena,      // always 1 when enabled
    input  wire       clk,      // global TT clock (~12 MHz)
    input  wire       rst_n     // global reset (active low)
);

    // Control signals
    wire start = ui_in[0]&ena;
    wire stop  = ui_in[1]&ena;

    // Stopwatch outputs
    wire [5:0] sec;
    wire [5:0] min;

    // Stopwatch instance (active-high reset inside)
    stopwatch sw (
        .clk (clk),
        .rst_n (rst_n),   // convert active-low → active-high
        .start(start),
        .stop(stop),
        .sec(sec),
        .min(min)
    );

    // Convert sec/min into BCD
    reg [15:0] bcd;
    reg [5:0] sec_tmp, min_tmp;
    wire rst=~rst_n;
    
    always @(*) begin
        // --- seconds ---
        sec_tmp = sec;
        if (sec_tmp >= 50) begin bcd[7:4] = 5; sec_tmp = sec_tmp - 50; end
        else if (sec_tmp >= 40) begin bcd[7:4] = 4; sec_tmp = sec_tmp - 40; end
        else if (sec_tmp >= 30) begin bcd[7:4] = 3; sec_tmp = sec_tmp - 30; end
        else if (sec_tmp >= 20) begin bcd[7:4] = 2; sec_tmp = sec_tmp - 20; end
        else if (sec_tmp >= 10) begin bcd[7:4] = 1; sec_tmp = sec_tmp - 10; end
        else bcd[7:4] = 0;
        bcd[3:0] = sec_tmp[3:0];

        // --- minutes ---
        min_tmp = min;
        if (min_tmp >= 50) begin bcd[15:12] = 5; min_tmp = min_tmp - 50; end
        else if (min_tmp >= 40) begin bcd[15:12] = 4; min_tmp = min_tmp - 40; end
        else if (min_tmp >= 30) begin bcd[15:12] = 3; min_tmp = min_tmp - 30; end
        else if (min_tmp >= 20) begin bcd[15:12] = 2; min_tmp = min_tmp - 20; end
        else if (min_tmp >= 10) begin bcd[15:12] = 1; min_tmp = min_tmp - 10; end
        else bcd[15:12] = 0;
        bcd[11:8] = min_tmp[3:0];
    end

    // 7-seg driver outputs
    wire [6:0] seg;
    wire       dp;
    wire [3:0] an;

    seven_seg_driver ssd (
        .clk (clk),
        .rst_n (rst_n),
        .bcd (bcd),
        .seg (seg),
        .dp  (dp),
        .an  (an)
    );

    // Map outputs → TinyTapeout pins
    assign uo_out[6:0] = seg;
    assign uo_out[7]   = dp;
    assign uio_out[3:0] = an;
    assign uio_out[7:4] = 4'b0000;
    assign uio_oe = 8'h0F; // lower 4 are outputs

    // Prevent unused warnings
    wire _unused = &{ui_in[7:2], uio_in};
endmodule


module seven_seg_driver(
    input  wire clk,
    input  wire rst_n,        // active-low reset
    input  wire [15:0] bcd,
    output reg [6:0] seg,
    output reg        dp,
    output reg [3:0]  an
);

    // internal active-high reset
    wire rst = ~rst_n;

    reg [1:0]  digit_select;    // which digit active
    reg [3:0]  digit_value;
    reg [15:0] refresh_counter;

    // Refresh rate divider (digit multiplexing)
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            refresh_counter <= 0;
            digit_select    <= 0;
        end else begin
            if (refresh_counter == 16'd49_999) begin
                refresh_counter <= 0;
                digit_select <= digit_select + 1;
            end else begin
                refresh_counter <= refresh_counter + 1;
            end
        end
    end

    // Select which digit to display
    always @(*) begin
        case(digit_select)
            2'b00: begin digit_value = bcd[3:0];   an = 4'b1110; end
            2'b01: begin digit_value = bcd[7:4];   an = 4'b1101; end
            2'b10: begin digit_value = bcd[11:8];  an = 4'b1011; end
            2'b11: begin digit_value = bcd[15:12]; an = 4'b0111; end
            default: begin digit_value = 4'd0;     an = 4'b1111; end
        endcase
        dp = 1'b1; // decimal point off
    end

    // 7-seg decoder (active-high segments)
    always @(*) begin
        case(digit_value)
            4'd0: seg = 7'b1111110;
            4'd1: seg = 7'b0110000;
            4'd2: seg = 7'b1101101;
            4'd3: seg = 7'b1111001;
            4'd4: seg = 7'b0110011;
            4'd5: seg = 7'b1011011;
            4'd6: seg = 7'b1011111;
            4'd7: seg = 7'b1110000;
            4'd8: seg = 7'b1111111;
            4'd9: seg = 7'b1111011;
            default: seg = 7'b0000001; // dash
        endcase
    end
endmodule


module stopwatch(
    input  wire clk,       // 50 MHz input clock
    input  wire rst_n,     // active low reset
    input  wire start,
    input  wire stop,
    output reg [5:0] sec,
    output reg [5:0] min
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




Reference solution:
rtl/generated.v: 
    // Active-high reset
    wire rst = ~rst_n;

    // Run/stop state
    reg running;

    always @(posedge clk or posedge rst) begin
        if (rst)
            running <= 1'b0;
        else if (start)
            running <= 1'b1;
        else if (stop)
            running <= 1'b0;
    end

    // Divider for ~1 Hz (assuming 50 MHz input clock)
    reg [25:0] div_counter;
    wire one_sec_enable = (div_counter == 26'd49_999_999);

    always @(posedge clk or posedge rst) begin
        if (rst)
            div_counter <= 26'd0;
        else if (one_sec_enable)
            div_counter <= 26'd0;
        else
            div_counter <= div_counter + 1'b1;
    end

    // Time counters
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            sec <= 6'd0;
            min <= 6'd0;
        end
        else if (running && one_sec_enable) begin
            if (sec == 6'd59) begin
                sec <= 6'd0;
                if (min == 6'd59)
                    min <= 6'd0;
                else
                    min <= min + 1'b1;
            end else begin
                sec <= sec + 1'b1;
            end
        end
    end