You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Your Name
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_td4 (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
  );

  // 未使用端子の接続（使わない入力ビットを潰す）
  wire _unused = &{ena, ui_in[5:4], 1'b0};

  // memory in
  wire [3:0] mem_address; // メモリのアクセス先アドレス
  wire [3:0] opcode_in; // メモリへのオペコード入力
  wire [3:0] immediate_in; // メモリへの即値入力
  wire mem_write; // メモリへの書き込み信号（反転）

  // memory out
  wire [3:0] opcode_out;// メモリからのオペコード出力
  wire [3:0] immediate_out; // メモリからの即値出力

  // 出力を内部信号に接続（最適化で消されないように可視化）
  // RegA を下位 4bit、RegB を上位 4bit に出力
  // 双方向ポートは uio[7] のみ Carry を出す例。その他は入力のまま。
  wire [3:0] io_input;
  wire [3:0] register_A;
  wire [3:0] register_B;
  wire [3:0] register_out;
  wire [3:0] pc;
  wire       carry;

  // モード関連（連続代入で扱う）
  wire is_read_mode = ui_in[6];
  wire is_exec_mode = ui_in[7];
  assign mem_write = ~is_read_mode & ~is_exec_mode;

  // 各モジュールへの入力
  assign opcode_in = ui_in[3:0];
  assign io_input = ui_in[3:0];
  assign immediate_in = uio_in[3:0];
  // メモリアドレスは Load/Read 時は外部入力 Exec 時は PCより指定
  assign mem_address = is_exec_mode ? pc : uio_in[7:4];

  CPU cpu(
        .opcode(opcode_out),
        .immediate(immediate_out),
        .io_input(io_input),
        .exec_mode(is_exec_mode),
        .register_A(register_A),
        .register_B(register_B),
        .pc(pc),
        .register_OUT(register_out),
        .register_carry(carry),
        .clk(clk),
        .rst_n(rst_n)
      );

  Memory memory(
           .address(mem_address),
           .opcode_in(opcode_in),
           .immediate_in(immediate_in),
           .opcode_out(opcode_out),
           .immediate_out(immediate_out),
           .write(mem_write),
           .clk(clk),
           .rst_n(rst_n)
         );

  // 各モードでの接続
  // Read モード: uo_out にメモリ内容を表示
  // Exec モード: uo_out にレジスタ、uio_out に出力/キャリーフラグ、uio_oe を出力有効
  assign uo_out   = (!is_exec_mode & is_read_mode)
         ? {immediate_out, opcode_out}
         : {register_B, register_A};
  assign uio_out  = (is_exec_mode)
         ? {carry, 3'b000, register_out}
         : 8'b0;
  assign uio_oe   = (is_exec_mode) ? 8'hFF : 8'h00;

endmodule


`default_nettype none


module Memory (
    input wire [3:0] address,
    input wire [3:0] opcode_in,
    input wire [3:0] immediate_in,
    output wire [3:0] opcode_out,
    output wire [3:0] immediate_out,
    input wire write,
    input wire clk,
    input wire rst_n
  );
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule





`default_nettype none

module CPU (
    input wire [3:0] opcode,
    input wire [3:0] immediate,
    input wire [3:0] io_input,
    input wire exec_mode,
    output reg  [3:0] register_A,
    output reg  [3:0] register_B,
    output reg  [3:0] pc,
    output reg  [3:0] register_OUT,
    input wire clk,
    input wire rst_n,
    output reg register_carry
  );

  // opcode definitions (4-bit)
  localparam ADD_A    = 4'b0000; // ADD A, Im
  localparam ADD_B    = 4'b1010; // ADD B, Im
  localparam MOV_A_IM = 4'b1100; // MOV A, Im
  localparam MOV_B_IM = 4'b1110; // MOV B, Im
  localparam MOV_A_B  = 4'b1000; // MOV A, B
  localparam MOV_B_A  = 4'b0010; // MOV B, A
  localparam JMP      = 4'b1111; // JMP Im
  localparam JNC      = 4'b0111; // JNC Im
  localparam IN_A     = 4'b0100; // IN A
  localparam IN_B     = 4'b0110; // IN B
  localparam OUT_B    = 4'b1001; // OUT B
  localparam OUT_IM   = 4'b1101; // OUT Im

  always @(posedge clk or negedge rst_n)
  begin
    if (!rst_n)
    begin
      register_A <= 4'b0;
      register_B <= 4'b0;
      pc <= 4'b0;
      register_OUT <= 4'b0;
      register_carry <= 1'b0;
    end
    else
    begin
      if (exec_mode)
      begin
        case (opcode)
          ADD_A:
            {register_carry, register_A} <= register_A + immediate;
          ADD_B:
            {register_carry, register_B} <= register_B + immediate;
          MOV_A_IM:
            register_A <= immediate;
          MOV_B_IM:
            register_B <= immediate;
          MOV_A_B:
            register_A <= register_B;
          MOV_B_A:
            register_B <= register_A;
          JMP:
            pc <= immediate;
          JNC:
            if (!register_carry)
            begin
              pc <= immediate;
            end
          IN_A:
            register_A <= io_input;
          IN_B:
            register_B <= io_input;
          OUT_B:
            register_OUT <= register_B;
          OUT_IM:
            register_OUT <= immediate;
          default:
            ;
        endcase

        // increment PC for non-jump/branch instructions
        if (opcode != JMP && opcode != JNC)
          pc <= pc + 1;

        // clear carry on non-add instructions
        if (opcode != ADD_A && opcode != ADD_B)
          register_carry <= 1'b0;

      end
    end
  end
endmodule


Reference solution:
rtl/generated.v: 
  reg [7:0] data[0:15]; // 8bit 16wordメモリ

  always @(posedge clk or negedge rst_n)
  begin
    if (!rst_n)
    begin
      // リセット(0クリア)
      data[0] <= 8'b0;
      data[1] <= 8'b0;
      data[2] <= 8'b0;
      data[3] <= 8'b0;
      data[4] <= 8'b0;
      data[5] <= 8'b0;
      data[6] <= 8'b0;
      data[7] <= 8'b0;
      data[8] <= 8'b0;
      data[9] <= 8'b0;
      data[10] <= 8'b0;
      data[11] <= 8'b0;
      data[12] <= 8'b0;
      data[13] <= 8'b0;
      data[14] <= 8'b0;
      data[15] <= 8'b0;
    end
    else if (write)
    begin
      // 書き込み
      data[address] <= {immediate_in, opcode_in};
    end
  end

  assign {immediate_out, opcode_out} = data[address];