You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

module tt_um_fifo #(parameter DSIZE=8, parameter ASIZE=4)
(
    input  wire [7:0] ui_in,
    output wire [7:0] uo_out,
    input  wire [7:0] uio_in,
    output wire [7:0] uio_out,
    output wire [7:0] uio_oe,
    input  wire   ena,
    input  wire   clk,
    input  wire   rst_n  
  
);
  assign uo_out = rdata;
  wire [DSIZE-1:0] rdata;
  wire  wfull, rempty;
  assign uio_oe = 8'b00100111;
  assign uio_out[0] = rempty;
  assign uio_out[1] = wfull;
  
  wire  [DSIZE-1:0] wdata = ui_in;
  wire winc = uio_in[7];
  wire rinc = uio_in[6];
  wire rrst_n = uio_in[3];
  wire wrst_n = uio_in[4];
    assign uio_out[7:6] = 0;
    assign uio_out[4:3] = 0;
    
    assign uio_out[5] = wclk;
    assign uio_out[2] = rclk;
  // Internal divided clocks
  wire wclk, rclk;

  // Clock divider instance
  clk_div clk_div_inst (
    .clk   (clk),
    .r_rst (rrst_n),   // active-high reset for divider
    .w_rst (wrst_n),
    .wclk  (wclk),
    .rclk  (rclk)
  );

  // Address & pointers
  wire [ASIZE-1:0] waddr, raddr;
  wire [ASIZE:0]   rptr, wptr, WSR2_ptr, RSW2_ptr;
  wire             wclken = (winc && !wfull);
  wire             rclken = (rinc && !rempty);

  // Synchronizers
  sync_R2W sync_r2w (
    .RSW2_ptr(RSW2_ptr), .rptr(rptr),
    .wclk(wclk), .wrst_n(wrst_n)
  );

  sync_W2R sync_w2r (
    .WSR2_ptr(WSR2_ptr), .wptr(wptr),
    .rclk(rclk), .rrst_n(rrst_n)
  );

  // FIFO memory
  fifomem #(DSIZE, ASIZE) fifomem_inst (
    .rdata(rdata),
    .wdata(wdata),
    .raddr(raddr),
    .waddr(waddr),
    .wclken(wclken),
    .wclk(wclk),
    .rclken(rclken),  
    .rclk(rclk)        
  );

  // Empty / full logic
  rptr_empty #(.ASIZE(ASIZE)) rptr_empty_inst (
    .rempty(rempty), .raddr(raddr), .rptr(rptr),
    .WSR2_ptr(WSR2_ptr), .rinc(rinc),
    .rclk(rclk), .rrst_n(rrst_n)
  );

  wptr_full #(.ASIZE(ASIZE)) wptr_full_inst (
    .wfull(wfull), .waddr(waddr), .wptr(wptr),
    .RSW2_ptr(RSW2_ptr), .winc(winc),
    .wclk(wclk), .wrst_n(wrst_n)
  );
    wire _unused = &{ena,uio_in[5],uio_in[2:0],rst_n};
endmodule



module wptr_full #(parameter ASIZE = 4)(
  output reg [ASIZE:0] wptr,
  output     [ASIZE-1:0] waddr,
  output reg wfull,
  input  [ASIZE:0] RSW2_ptr,
  input  wclk,
  input  wrst_n,
  input  winc
  
);

  reg  [ASIZE:0] wbin;
  wire [ASIZE:0] wgraynext, wbinnext;
  wire wfull_val;

  // Binary and Gray pointer update
  always @(posedge wclk or negedge wrst_n)
    if (!wrst_n)
      {wbin, wptr} <= 0;
    else
      {wbin, wptr} <= {wbinnext, wgraynext};

  // Write address for memory access
  assign waddr     = wbin[ASIZE-1:0];
  assign wbinnext  = wbin + {4'h0,(winc & ~wfull)};
  assign wgraynext = (wbinnext >> 1) ^ wbinnext;

  // Full condition (Cummings method)
  assign wfull_val = (wgraynext == {~RSW2_ptr[ASIZE:ASIZE-1], RSW2_ptr[ASIZE-2:0]});

  // wfull update
  always @(posedge wclk or negedge wrst_n)
    if (!wrst_n)
      wfull <= 1'b0;
    else
      wfull <= wfull_val;

endmodule



module sync_W2R #(parameter ASIZE = 4)(
  output reg [ASIZE:0] WSR2_ptr,
  input  [ASIZE:0]     wptr,
  input                rclk,
  input                rrst_n
);

  reg [ASIZE:0] WSR1_ptr;

  always @(posedge rclk or negedge rrst_n)
    if (!rrst_n)
      {WSR2_ptr, WSR1_ptr} <= 0;
    else
      {WSR2_ptr, WSR1_ptr} <= {WSR1_ptr, wptr};

endmodule




module sync_R2W #(parameter ASIZE = 4)(
  output reg [ASIZE:0] RSW2_ptr,
  input  [ASIZE:0]     rptr,
  input                wclk,
  input                wrst_n
);

  reg [ASIZE:0] RSW1_ptr;

  always @(posedge wclk or negedge wrst_n)
    if (!wrst_n)
      {RSW2_ptr, RSW1_ptr} <= 0;
    else
      {RSW2_ptr, RSW1_ptr} <= {RSW1_ptr, rptr};

endmodule



module rptr_empty #(parameter ASIZE = 4)(
  output reg [ASIZE:0] rptr,
  output     [ASIZE-1:0] raddr,
  output reg rempty,
  input  [ASIZE:0] WSR2_ptr,
  input  rclk,
  input  rrst_n,
  input  rinc
);

  reg  [ASIZE:0] rbin;
  wire [ASIZE:0] rgraynext, rbinnext;
  wire rempty_val;

  // Binary and Gray pointer update
  always @(posedge rclk or negedge rrst_n)
    if (!rrst_n)
      {rbin, rptr} <= 0;
    else
      {rbin, rptr} <= {rbinnext, rgraynext};

//memory 
  assign raddr     = rbin[ASIZE-1:0];
  assign rbinnext  = rbin + {4'h0,(rinc & ~rempty)};
  assign rgraynext = (rbinnext >> 1) ^ rbinnext;

//empty cond
  assign rempty_val = (rgraynext == WSR2_ptr);

  // rempty update
  always @(posedge rclk or negedge rrst_n)
    if (!rrst_n)
      rempty <= 1'b1;  // FIFO is empty after reset
    else
      rempty <= rempty_val;

endmodule




module fifomem  #(parameter DSIZE = 8,parameter ASIZE =4)
(output reg [DSIZE-1:0] rdata,
 input [DSIZE-1:0] wdata,
 input [ASIZE-1:0] raddr,waddr,
 input wclken,wclk,rclken,rclk
 );
 
 localparam DEPTH = 1<<ASIZE;
 reg [DSIZE-1:0] mem [0:DEPTH-1];
 
 always@(posedge wclk)
 if(wclken)
    mem[waddr]<=wdata;
  
 always@(posedge rclk)
   if(rclken)
     rdata <= mem[raddr];
 
 endmodule



module clk_div(
    input  wire clk,     // 100 MHz input clock
    input  wire r_rst,   // active-high reset for rclk
    input  wire w_rst,   // active-high reset for wclk
    output reg  wclk,    // 50 MHz (÷2)
    output reg  rclk     // ~33.3 MHz (÷3)
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




Reference solution:
rtl/generated.v: 
    
    
    // Divide-by-2 for 50 MHz
    always @(posedge clk or negedge w_rst) begin
        if (!w_rst)
            wclk <= 1'b0;
        else
            wclk <= ~wclk;
    end

    // Divide-by-3 for ~33.3 MHz
    reg [1:0] rcount;
    always @(posedge clk or negedge r_rst) begin
        if (!r_rst) begin
            rcount <= 0;
            rclk   <= 1'b0;
        end else begin
            rcount <= (rcount == 2) ? 0 : rcount + 1;
            rclk   <= (rcount < 1);  // high for 1 cycle, low for 2 cycles
        end
    end