You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

/*
 * Copyright (c) 2024 Your Name
 * SPDX-License-Identifier: Apache-2.0
 */

`define default_netname none

module tt_um_i_tree_batzolislefteris(
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // will go high when the design is enabled
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule




module i_tree(
    input wire clk,
    input wire reset,
    input wire sensor_data, // Incoming sensor data bit
    output wire anomaly_detected // Output indicating if an anomaly was detected
);

// Internal signal declarations
wire [7:0] data_from_buffer;
wire data_ready;
wire data_processed;

// Instantiate the InputBuffer module
  InputBuffer #(.DATA_WIDTH(8)) input_buffer_inst (
    .clk(clk),
    .reset(reset),
    .sensor_data(sensor_data),
    .data_processed(data_processed),
    .data_output(data_from_buffer),
    .data_ready(data_ready)
);

// Instantiate the IsolationTreeStateMachine module
IsolationTreeStateMachine isolation_tree_state_machine_inst (
    .clk(clk),
    .reset(reset),
    .data_input(data_from_buffer),
    .data_valid(data_ready),
    .anomaly_detected(anomaly_detected),
    .data_processed(data_processed)
);

endmodule

module IsolationTreeStateMachine(
    input wire clk,
    input wire reset,
    input wire [7:0] data_input,
    input wire data_valid,
    output reg anomaly_detected,
    output reg data_processed
);

// Define state constants
localparam [1:0] IDLE = 2'b00,
                 CHECK_ANOMALY = 2'b01,
                 PROCESS_DONE = 2'b10;

// State variables
reg [1:0] current_state = IDLE;
reg [1:0] next_state = IDLE;
reg [7:0] anomaly_pattern; // Internal register to hold the anomaly pattern

always @(posedge clk or negedge reset) begin
    if (!reset) begin
        // Reset logic
        anomaly_detected <= 0;
        data_processed <= 0;
        current_state <= IDLE;
        next_state <= IDLE;
        anomaly_pattern <= 8'h00; // Reset anomaly pattern register
    end else begin
        current_state <= next_state; // Transition to the next state

        case (current_state)
            IDLE: begin
                anomaly_detected <= 0; // Reset anomaly_detected each cycle
                if (data_valid) begin
                    next_state <= CHECK_ANOMALY; // Transition to check anomaly if data is valid
                    anomaly_pattern <= data_input; // Store the first 8-bit value as the anomaly pattern
                end
            end
            CHECK_ANOMALY: begin
                // Perform anomaly check
                anomaly_detected <= (data_input == anomaly_pattern); // Check if data matches anomaly pattern
                next_state <= PROCESS_DONE; // Move to process done state
            end
            PROCESS_DONE: begin
                // Indicate processing is done
                data_processed <= 1;
                next_state <= IDLE; // Return to IDLE state
            end
            default: begin
                next_state <= IDLE; // Default fallback to IDLE
            end
        endcase
    end
end

endmodule


module InputBuffer #(
    parameter DATA_WIDTH = 8  // Default parameter for data width
)(
    input wire clk,
    input wire reset,
    input wire sensor_data,
    input wire data_processed,  // Signal from state machine indicating data has been processed
    output reg [DATA_WIDTH-1:0] data_output,
    output reg data_ready
);

// Internal signals and registers
reg [DATA_WIDTH-1:0] buffer;
reg [DATA_WIDTH-1:0] data_temp;
reg [DATA_WIDTH-1:0] bit_count = 0; // Bit count for data collection

// Always block for handling the shift register and outputting data
always @(posedge clk or posedge reset) begin
    if (reset) begin
        // Reset all outputs and internal registers
        buffer <= 0;
        data_temp <= 0;
        data_output <= 0;
        data_ready <= 0;
        bit_count <= 0;
    end else begin
        // Handle data collection and output
        if (bit_count < DATA_WIDTH) begin
            buffer <= (buffer << 1) | sensor_data;
            bit_count <= bit_count + 1;
        end

        // Check if data has been processed and ready to be output
        if (data_processed && (bit_count == DATA_WIDTH)) begin
            data_temp <= buffer; // Save data temporarily
            data_ready <= 1;
        end

        // Output data after ensuring it has been processed and ready
        if (data_ready) begin
            data_output <= data_temp;
            data_ready <= 0;
            buffer <= 0; // Reset buffer for new data collection
            bit_count <= 0; // Reset bit count
        end
    end
end

endmodule


Reference solution:
rtl/generated.v: 
	assign uio_oe  = 8'b0000_0000;
	assign uio_out = 8'b0000_0000;
	assign uo_out[7:1] = 7'b0000_000;
	

	i_tree i_tree_inst(
	    .clk(clk),
	    .reset(rst_n),
	    .sensor_data(ui_in[0]),
	    .anomaly_detected(uo_out[0])
	);