You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

`default_nettype none

module izh (
    input wire [7:0] current,    // Input current (8-bit)
    input wire clk,
    input wire reset_n,

    output wire spike,         // Spike output (1-bit)
    output reg [7:0] v        // State output (voltage)
);

    // Internal Constants (scaled values for fixed-point arithmetic)
    reg [15:0] a = 16'b000000000_0000010;  // 0.02 * 128 = 2.56
    reg [15:0] b = 16'b000000000_0011000;  // 0.15 * 128 = 19.2
    reg [15:0] c = 16'b111110000_1110000;  // -65 * 128 = -8320
    reg [15:0] d = 16'b000010100_0000000;  // 10 * 128 = 1280
    reg [15:0] thr = 16'b000000001_1100000;  // 30 * 128 = 3840

    // Internal Variables
    reg [15:0] u = 16'b0;                
    reg [15:0] u_next = 16'b0;
    reg [15:0] v_next = 16'b0;

    // Sequential logic (on clock)
    always @(posedge clk) begin

        // If reset is active, reset the state
        if (!reset_n) begin
            v <= 8'b0;       // Reset voltage
            u <= 16'b0;      // Reset recovery variable

        // Otherwise, update the state
        end else begin
            v <= v_next[7:0];  // Update voltage state
            u <= u_next;        // Update recovery state
        end
    end

    // Combinational logic (no clock)
    always @(*) begin
        v_next = {8'b0, v}; // Keep lower 8 bits for voltage
        u_next = u;

        // Check for spike condition
        if ({8'b0, v} >= thr) begin  
            v_next = c;          // Reset voltage to c
            u_next = u + d;      // Reset recovery variable

        // Update Izhikevich equation
        end else begin

            // Update voltage
            v_next = (({8'b0, v} * {8'b0, v} * 16'd2) >> 7) + 
                     (({8'b0, v} * 16'd5) >> 7) - u + ({8'b0, current} << 4);
            
            // Update recovery variable (decay of u)
            u_next = u + ((a * (b * {8'b0, v} - u)) >> 7);
        end
    end
    
    // Assign spike output 
    assign spike = ({8'b0, v} >= thr) ? 1'b1 : 1'b0;

endmodule

/*
 * Copyright (c) 2024 Noah Williams
 * SPDX-License-Identifier: Apache-2.0
 */

`default_nettype none

module tt_um_nomuwill (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule



Reference solution:
rtl/generated.v: 
  // All output pins must be assigned. `If not used, assign to 0.
  assign uio_out [5:0] = 0;

  // List all unused inputs to prevent warnings
  wire _unused = &{ena, 1'b0, uio_in};

  // Internal signal
  wire [7:0] v1; 
  wire spike1;
  wire [7:0] v2; 
  wire spike2;

  // Instantiate the Izhikevich neuron
  izh izh_1(
    .current(ui_in),  // current input from parent module, concatenated to 16 bits
    .clk(clk),        // clock driven by clock in parent module
    .reset_n(rst_n),  // reset driven by reset in parent module
    .spike(spike1),    // most significant bit of state output to parent module
    .v(v1)   // Use lower 8 bits of v for state output
  );

  // Instantiate the Izhikevich neuron again!
  izh izh_2(
    .current(v1),   // Route the output of the first neuron to the second neuron
    .clk(clk),        
    .reset_n(rst_n),  
    .spike(spike2),    
    .v(v2)  
  );

  assign uo_out = v1; 
  assign uio_oe = v2;
  assign uio_out[7] = spike1;
  assign uio_out[6] = spike2;