You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:

// >>> Module Implementation Begin

// <<< Module Implementation End

Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.

Follow these rules:

1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.

Your output should contain **only the Verilog code** that fits inside the marked region.

`default_nettype none

module tt_um_lif_tk (
    input  wire [7:0] ui_in,    // Inputs: [2:0] pattern_select, [7:3] base_current
    input  wire [7:0] uio_in,   // IOs: Coupling strength
    output wire [7:0] uo_out,   // Outputs: Spikes
    output wire [7:0] uio_out,  // IOs: First neuron state
    output wire [7:0] uio_oe,   // IOs: Enable path
    input  wire       ena,
    input  wire       clk,
    input  wire       rst_n
);
// >>> Module Implementation Begin

// <<< Module Implementation End
endmodule



`default_nettype none

module lif (
    input wire clk,
    input wire rst_n,
    input wire ena,
    input wire [4:0] base_current,
    input wire [7:0] coupling_in,
    input wire [2:0] pattern_select,
    input wire [7:0] phase_offset,
    output reg [7:0] membrane_potential,
    output reg spike
);

    // Parameters
    localparam THRESHOLD = 8'd200;
    localparam RESET_POTENTIAL = 8'd50;
    localparam LEAK_RATE = 8'd5;
    localparam REFRACTORY_PERIOD = 4'd10;

    // Internal signals
    reg [7:0] next_potential;
    reg [3:0] refractory_counter;
    reg [7:0] phase_counter;
    wire [7:0] total_current;
    wire in_refractory;
    wire in_phase;
    
    assign in_refractory = (refractory_counter != 0);
    assign in_phase = (phase_counter >= phase_offset);
    
    // Calculate total current based on pattern
    wire [7:0] excitation, inhibition;
    assign excitation = coupling_in << 1; // 2x stronger excitation
    assign inhibition = coupling_in << 2; // 4x stronger inhibition
    
    // Pattern select:
    // 000: Independent firing
    // 001: Synchronized firing (strong excitation)
    // 010: Opposed firing (strong inhibition)
    // 011: Weak coupling
    assign total_current = 
        (pattern_select == 3'b000) ? {3'b0, base_current} :
        (pattern_select == 3'b001) ? {3'b0, base_current} + excitation :
        (pattern_select == 3'b010) ? (in_phase ? {3'b0, base_current} : 8'd0) - inhibition :
        (pattern_select == 3'b011) ? {3'b0, base_current} + {1'b0, coupling_in[7:1]} : // Half strength coupling
        {3'b0, base_current};

    // Membrane potential update logic
    always @(*) begin
        if (membrane_potential >= THRESHOLD) begin
            next_potential = RESET_POTENTIAL;
        end else if (in_refractory) begin
            next_potential = RESET_POTENTIAL;
        end else begin
            // Add current, subtract leak
            if (membrane_potential > LEAK_RATE) begin
                next_potential = membrane_potential + total_current - LEAK_RATE;
            end else begin
                next_potential = membrane_potential + total_current;
            end
        end
    end

    // Sequential logic
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            membrane_potential <= RESET_POTENTIAL;
            spike <= 1'b0;
            refractory_counter <= 4'd0;
            phase_counter <= 8'd0;
        end else if (ena) begin
            membrane_potential <= next_potential;
            phase_counter <= phase_counter + 1;
            
            // Spike and refractory period logic
            if (membrane_potential >= THRESHOLD) begin
                spike <= 1'b1;
                refractory_counter <= REFRACTORY_PERIOD;
            end else begin
                spike <= 1'b0;
                refractory_counter <= (refractory_counter > 0) ? refractory_counter - 1 : 0;
            end
        end
    end

endmodule

Reference solution:
rtl/generated.v: 
    // Internal signals
    wire [7:0] neuron1_state, neuron2_state;
    wire neuron1_spike, neuron2_spike;
    wire [4:0] base_current;
    wire [2:0] pattern_select;
    wire [7:0] coupling_strength;

    // Assign inputs
    assign base_current = ui_in[7:3];
    assign pattern_select = ui_in[2:0];
    assign coupling_strength = uio_in;

    // Phase offsets for the neurons
    localparam PHASE1 = 8'd0;
    localparam PHASE2 = 8'd100;  // Half period offset

    // Instantiate two LIF neurons
    lif neuron1 (
        .clk(clk),
        .rst_n(rst_n),
        .ena(ena),
        .base_current(base_current),
        .coupling_in(neuron2_spike ? coupling_strength : 8'b0),
        .pattern_select(pattern_select),
        .phase_offset(PHASE1),
        .membrane_potential(neuron1_state),
        .spike(neuron1_spike)
    );

    lif neuron2 (
        .clk(clk),
        .rst_n(rst_n),
        .ena(ena),
        .base_current(base_current),
        .coupling_in(neuron1_spike ? coupling_strength : 8'b0),
        .pattern_select(pattern_select),
        .phase_offset(PHASE2),
        .membrane_potential(neuron2_state),
        .spike(neuron2_spike)
    );

    // Assign outputs
    assign uo_out = {6'b0, neuron2_spike, neuron1_spike};
    assign uio_out = neuron1_state;
    assign uio_oe = 8'b0;  // Set as inputs