HDTenEightyP/NetNews huggingface dataset:
From: bvs@nastar.uucp (Bill Versteeg)
Subject: seeking info on UDLC, P1024 and Uniscope
Organization: Digital Transmission Systems, Duluth, GA.
Date: Mon, 11 Jan 1993 17:20:08 GMT


I am looking for some information on some Unisys
specific protocols.

I am told that UDLC is Unisys' flavor of HDLC, and it has
some different reject codes.

I am told that Uniscope and P1024 are some other synchronous
Unisys protocols.

I need some hard protocol specs for these protocols. Any 
pointers, antecdotes, rumors, or idle gossip would be appreciated.
A reference to a document describing these protocols would
be GREATLY appreciated.

Bill VerSteeg
bvs@ver.com
From: ed@titipu.resun.com (Edward Reid)
Newsgroups: comp.sys.unisys
Subject: Re: unisys internal mapper email
Date: Thu, 7 Jan 93 18:31:49 EST(-0500)
Organization: Accuracy, Ltd.
Reply-To: ed@titipu.resun.com (Edward Reid)
X-Mailer: uAccess - Macintosh Release: 1.6v0

luis@worldbank.org (Luis Herrera W3/TI5LHM) writes:
> 	why do I get:
> 
>       ----- Transcript of session follows -----
> 421 Host unislc.slc.unisys.com not found for mailer ddn.
> 550 <postmstr@unislc.slc.unisys.com>... Host unknown

Sorry about that.  I didn't check the instructions I posted very carefully. 
One set didn't mention the host name for the gateway, and the other gave it
wrong.  The correct address for the gateway is postmstr@unislc.uucp.  If that
fails, try sun!unislc!postmstr or att!unislc!postmstr.  I also claimed I never
made the gateway work -- not true; I did verify that the gateway worked, though
I was never able to establish contact with my intended contactee.  Here's my
own summary of how to use the gateway:

Outside world to Ofislink/Mappermail:

  Send a message to postmstr@unislc.uucp  (that's postmstr, not postmaster)
  In the BODY of the message, give the address in a #To: line.  The number/
    host address is inverted and the slash replaced by a period.  For example,
    if the user's address is 4331/EMMK, the line in the body is

    #To: EMMK.4331

Ofislink/Mappermail to outside world:

  Send a message to postmstr/un49.
  In the body of the message, include a #To: line giving the outside address,
    for example

    #To: ed@titipu.resun.com

  All formatting (underline, bold, etc) will be stripped off by the gateway.

In both directions you can have multiple addresses, either on a single #To:
line separated by spaces or on multiple #To: lines.  Be aware that messages
headers will not survive the gateway in either direction.

Edward Reid  (8*}>
  eel:   ed@titipu.resun.com  or  nosc.mil!titipu.resun.com!ed
  snail: PO Box 378/Greensboro FL 32330
From: silla@prophecy.West.Sun.Com (Lito Silla)
Newsgroups: comp.sys.unisys
Subject: Re: unisys internal mapper email
Date: 8 Jan 1993 01:31:21 GMT
Organization: Sun Microsystems, Inc.
Distribution: world
Reply-To: silla@prophecy.West.Sun.Com
NNTP-Posting-Host: prophecy.west.sun.com

Gateway is not working. I'm getting the same session messages as that of Luis Herrera.
Any help out there?

Thanks and regards,

Lito Silla
From: silla@prophecy.West.Sun.Com (Lito Silla)
Newsgroups: comp.sys.unisys
Subject: unisys internal mapper email
Date: 5 Jan 93 20:45:26 GMT
Reply-To: silla@prophecy.West.Sun.Com
Organization: Sun Microsystems, Inc.
NNTP-Posting-Host: prophecy.west.sun.com

Keywords: 

I need information on how I could send internet email to unisys internal mapper email
system. Any reply would be very much appreciated. Somebody told me that this question
had been replied to before in this newsgroup, but I donot know where the previous
articles are archived and for how long. 

Lito Silla, Sun Microsystems Inc.
lito.silla@West.Sun.Com
From: bob@hobbes.dtcc.edu (Bob Rahe)
Newsgroups: comp.sys.unisys
Subject: NEC CDROM on an A6
Date: 11 Jan 1993 21:04:36 GMT
Organization: Delaware Technical & Community College
Distribution: world
NNTP-Posting-Host: hobbes.dtcc.edu
Keywords: CDROM A6 NEC73M


Hi,

  I'm trying to get a NEC CDR73M connected to my A6HS running 3.9.1.  I'm
adding it to a DLP chain that has 4 internal SCSI disks and an Exabyte
8mm drive.  I've tried all kinds of things with terminators in and out,
tape drive in and out etc. etc.  The best I've been able to do is get the
bus hung 8-(  The disks are units 0-3 (PK54-57), the tape is unit 5 (MT59)
and I set the CDROM to unit 6 (CD60?).  Never sees it; if I RY it it blinks
and then goes off on a tangent with unknown errors, hangs the bus, IOs don't
complete etc. etc.

  Maintlog seems to show (for SCSI 60) an LRD of 0000000000023,
and a DLP Result of 0231 0000 0000 0000. DLP command was
8E600000000000000FE0000.

  This thing is a single ended device (as is the tape drive which works)
since I can hook both up to the scsi port on a Mac Plus and poke around the
varios scsi-ish stuff.

  Any theories/thngs to try? This guy is supposed to be ISO compliant, is
there some other spec Unisys wants on A series???

   Bob

-- 
-------------------------------------------------------------------------
|Bob Rahe, Delaware Tech&Comm College | AIDS, Drugs, Abortion: -        |
|Internet: bob@hobbes.dtcc.edu        |  - Don't liberals just kill you?|
|CI$: 72406,525 Genie:BOB.RAHE        |Save whales; and kill babies?    |
-------------------------------------------------------------------------
Newsgroups: comp.sys.unisys
From: luis@worldbank.org (Luis Herrera W3/TI5LHM)
Subject: Re: unisys internal mapper email
Reply-To: luis@worldbank.org
Organization: The World Bank, Washington, DC, USA
Date: Fri, 8 Jan 1993 15:53:09 GMT

In article n49sla@titipu.resun.com, ed@titipu.resun.com (Edward Reid) writes:
 
> Sorry about that.  I didn't check the instructions I posted very carefully. 
> One set didn't mention the host name for the gateway, and the other gave it
> wrong.  The correct address for the gateway is postmstr@unislc.uucp.  If that
> fails, try sun!unislc!postmstr or att!unislc!postmstr.  I also claimed I never
> made the gateway work -- not true; I did verify that the gateway worked, though
> I was never able to establish contact with my intended contactee.  Here's my
> own summary of how to use the gateway:
> 

	Thanks Edward it works just fine !! I'm still waiting for the
reply to get back to me, but at least my email got to them !!!!!!

		Luis



---

| Internet : luis@worldbank.org 	| Voice: (202) 473-6981       |
| UUNET    : uunet!nimbus!luis		| fax:   (202) 676-1634	      |
|                                     	| W3/TI5LHM                   |

Newsgroups: comp.sys.unisys
From: wwkiii@well.sf.ca.us (Walt Kemmerer)
Subject: Re: unisys internal mapper email
Organization: Whole Earth 'Lectronic Link
Date: Wed, 6 Jan 1993 03:33:59 GMT


If by "internal mapper email" you mean the OFISLink stuff, then there is a
way... Unisys now has an X.400 interface, and OFISLink users can call their
OFISLink coordinator and get registered into it.  This allows two-way coms
into and out of OFISLink to those folks that have access to X.400.  As this
includes SprintMail, ATTMail, MCIMail, and CompuServe (among others), this
is light-years better than before.  I can assure you it works, because I've
used it and it's both fast and dependable.  More information available on
request, but best bet is to have your Unisys contact call his/her OFISLink
coordinator and get registered.

Cheers, Walt.

---------------------------------------------------------------------------
I/O Specialists, Inc.    713.858.0997     kemmerer@ioscc.neosoft.com
3906 Green Fields                         wwkiii@well.sf.ca.us
Sugar Land, TX  77479    Network & Comm   wkemmerer@attmail.com
---------------------------------------------------------------------------
From: silla@prophecy.West.Sun.Com (Lito Silla)
Newsgroups: comp.sys.unisys
Subject: Re: unisys internal mapper email
Date: 11 Jan 1993 21:34:36 GMT
Organization: Sun Microsystems, Inc.
Distribution: world
Reply-To: silla@prophecy.West.Sun.Com
NNTP-Posting-Host: prophecy.west.sun.com

I had just found out that the gateway is indeed working. I used sun!unislc!postmstr.
Thanks to everybody who contributed to this particular subject.

Regards,

Lito Silla

Newsgroups: comp.sys.intel,comp.sys.mac.hardware,comp.sys.ibm.pc.hardware
From: fisher@ncselxsi.uucp (Chuck Fisher)
Subject: Re: 486 vs. Mac Benchmarks
Organization: National Computer Systems, San Jose, CA  95131
Date: Tue, 5 Jan 1993 19:03:31 GMT

In article <C0Co0s.1C6@usenet.ucs.indiana.edu> ntaib@silver.ucs.indiana.edu (Iskandar Taib) writes:
>In article <1992Dec23.144535.11341@crd.ge.com> davidsen@crd.ge.com (bill davidsen) writes:
>
>>  The truth is that Mac applications are 32 bit, and DOS applications
>>are 16 bit. A comparison of UNIX 32 bit applications would be more
>>correct, if they were just comparing the processors.
>
>Well, if this is so, how do the apps run on Mac Pluses? And why is 
>32 bit adressing an option under System 7? 

*Most* Mac applications are "32-bit clean" which means that they will
run in 32-bit addressing mode.  Some older Mac applications are not
32-bit clean and will not run in 32-bit mode.  32-bit addressing is
necessary for using Macs with more than 8 MB of RAM.  For example, in
my PowerBook 160 I have 14 MB of RAM installed.  I use 6 MB as a RAM
disk and 8 MB for memory.  I turn off 32-bit addressing mode with this
configuration.  If I need to use more or less RAM as main memory or
RAM disk, I just use the Memory control panel and reconfigure the RAM
and the addressing mode.

The "32-bit dirty" applications typically used one of the address
bytes for other information which is now a "no-no" according to Apple.

32-bit clean applications will run on any Mac, including a Mac Plus.
32-bit dirty applications will only run on System with 32-bit adressing
mode turned off (the default.)  In this mode you can only use 8 MB of
RAM as main memory.
-- 
Chuck Fisher                                        (800) 359-7997 Work
ncselxsi system administrator                       (415) 964-2819 Home
uucp:  ...!netcom!ncselxsi!fisher
From: tdbear@dvorak.amd.com (Thomas D. Barrett)
Newsgroups: comp.sys.intel
Subject: Re: Pentium to be Scrapped?!
Date: 8 Jan 93 19:34:24 GMT
Organization: Advanced Micro Devices, Inc.; Austin, Texas

In article <1iimlfINN7b1@hpscit.sc.hp.com> matthias@nsr.hp.com (Matthias Kamm) writes:
>Intel would RUIN it's relations with it's
>customers to cancel the chip now. 

Well... let's suppose that this chip was burning holes in PC Boards
and melting plastic ZIF sockets.  If so, then those customers are
probably already a little nipped.  Let's suppose that the only way out
of the situation is to delay the project for whatever reason and then
suggest that they wait just a little while longer for something
totally awesome and cool-running.  The customers are still a little
nipped, but if they are told that they won't have to do any
redesigning and that they get a little while longer to work out all of
their chipset bugs, then they might not be so nipped come introduction.

(Don't read anything in to any of this... I know absolutely nothing)

-- 
|Tom Barrett (TDBear), Sr. Engineer|tom.barrett@amd.com|v:512-462-6856 |
|AMD PCD MS-520 | 5900 E. Ben White|Austin, TX  78741  |f:512-462-5155 |
|"No is yes, And we're all free" ---Tracy Chapman, "Why?"              |
|My views are my own and may not be the same as the company of origin  |
From: doconnor@sedona.intel.com (Dennis O'Connor)
Newsgroups: comp.sys.intel
Subject: Re: 960 XA/MX Questions
Date: 9 Jan 93 13:32:20
Organization: Intel i960(tm) Architecture
	<1993Jan8.215944.10065@gandalf.ca>
	<DOCONNOR.93Jan8234804@potato.sedona.intel.com>
	<16313@auspex-gw.auspex.com>
NNTP-Posting-Host: potato.intel.com
In-reply-to: guy@Auspex.COM's message of 9 Jan 93 19:31:11 GMT


guy@Auspex.COM (Guy Harris) writes:
]
] >	MC : core + FPU + MMU, mil-spec
] >	XA : MC	+ object-oriented tagged architecture, mil-spec
]
] I.e., the BiiN machines all used mil-spec chips? :-)

The chips the BiiN machine used ( past tense ) are currently
only available as mil-spec parts.

] >Note that none of the commercial parts are the same die as 
] >any of the military parts : that would cost too much.
]
] I seem to remember Steve McGeady implying that, at least in some sense,
] the KA, KB, MC, and XA all used the same die, even though the dies on
] the mil-spec versions might be more rigorously tested.  The XA may have
] an extra pin or so for the tag bit.

This was true in the past. I'm pretty sure it is no longer true.

--
Dennis O'Connor			doconnor@sedona.intel.com
From: joker@diku.dk (Morten Christian Holmgreen)
Newsgroups: comp.sys.intel
Subject: Re: Pentium to be Scrapped?!
Date: 9 Jan 93 17:40:30 GMT
Organization: Department of Computer Science, U of Copenhagen

dbarber@crash.cts.com (David C. Barber) writes:

>Maybe they'll wait and try to get a clock-doubling Pentium running.

>That would be a nice surprise.

I was under the impression, that the Pentium to be released _was_ clock-
doubled from the start - does anybody know?

Christian
-- 
M. Christian Holmgreen / joker@diku.dk / mochmch@uts.uni-c.dk
M.Sc. student, University of Copenhagen, Dept. of Computer Science
"Human errors can only be avoided if one can avoid the use of humans"
Newsgroups: comp.sys.intel
From: feustel@netcom.com (David Feustel)
Subject: 960 XA/MX Questions
Organization: DAFCO: OS/2 Software Support & Consulting
Date: Wed, 6 Jan 1993 02:37:33 GMT

I just received a copy of the Intel 960 XA/MX Programmer's Reference
and my interest in these chips continues to rise. 

Are these chips available yet?
How much do they cost?
Are there evaluation boards and software available?
Is anyone working with these chips for commercial products?
Has the Mach microkernel been ported to this architecture?
Thanks.


-- 
Dave Feustel N9MYI <feustel@netcom.com>
 
                        Happy Holidays to ALL!!!
Xref: sparky comp.sys.intel:2882 comp.sys.mac.hardware:25314 comp.sys.ibm.pc.hardware:34836
From: gwangung@carson.u.washington.edu (Roger Tang)
Newsgroups: comp.sys.intel,comp.sys.mac.hardware,comp.sys.ibm.pc.hardware
Subject: Re: 486 vs. Mac Benchmarks
Date: 5 Jan 1993 18:00:57 GMT
Organization: University of Washington, Seattle
NNTP-Posting-Host: carson.u.washington.edu

In article <1993Jan5.161422.10231@lth.se> f88hv@efd.lth.se (Henrik Vallgren) writes:
>In article <1992Dec17.224200.22219@noose.ecn.purdue.edu> merrifie@cidmac.ecn.purdue.edu (Michael C Merrifield) writes:
>>        "Recent Studies Reveal 25MHz Is Now Faster Than 50MHz"
>>"Ingram Benchmark Results, March 1992 - 25 and 33 MHz 040 Macintosh Quadra
>>Outruns the 486 at 33 and 50 MHz."
>>"This revelation is brought to you by the Apple Macintosh and the Motorola
>>68040."  The add goes on to say that Ingram Labs (an independent PC testing
>>firm) compared the newest 040 Macs (Quadra 950 and 700) to several of the
>
>First, about the "independent" firm: they we're hired by Apple right ?

	So?

	As a sometimes player in testing, if you allow your client to cook
the results or you do that yourself, you get a reputation.

	And with a reputation like that, you don't get jobs in the future.
-- 
Roger Tang, gwangung@u.washington.edu
Producer Emeritus, Asian Theatre at the UW, Uncle Bonsai Memorial Fan Club
	"The definition of balls is for a non-singer to go karaoke singing
with the cast of a musical revue."
From: doconnor@sedona.intel.com (Dennis O'Connor)
Newsgroups: comp.sys.intel
Subject: Re: P6 Specs/features
Date: 10 Jan 93 16:41:35 GMT
Article-I.D.: potato.DOCONNOR.93Jan10084135
Organization: Intel i960(tm) Architecture
NNTP-Posting-Host: potato.intel.com
In-reply-to: gregg@bss1.umd.edu's message of 10 Jan 93 02:59:21 GMT


gregg@bss1.umd.edu (Gregg Piermarini) writes:
] While we are on the subject of the next processor after the Pentium, could 
] anybody give me some info on exactly what capabilities the P6 will have. 

The only people allowed to talk about next-generation Intel processors
are those who don't really know anything about them. Until the "next"
becomes "current" of course.

I think it's been publicly stated that the Pentium processor's successor 
will have about 6 million transistors, execute x86 code, and be faster. 
That's about all that's solidly public, the rest is speculation.
--
Dennis O'Connor			doconnor@sedona.intel.com
From: doconnor@sedona.intel.com (Dennis O'Connor)
Newsgroups: comp.sys.intel
Subject: Re: Pentium to be Scrapped?!
Date: 8 Jan 93 23:35:31
Organization: Intel i960(tm) Architecture
	<DOCONNOR.93Jan7094831@potato.sedona.intel.com>
	<1993Jan8.192720.20393@dvorak.amd.com>
NNTP-Posting-Host: potato.intel.com
In-reply-to: tdbear@dvorak.amd.com's message of Fri, 8 Jan 93 19:27:20 GMT

tdbear@dvorak.amd.com (Thomas D. Barrett) writes:


] In article <DOCONNOR.93Jan7094831@potato.sedona.intel.com> doconnor@sedona.intel.com (Dennis O'Connor) writes:
] >This is an idiotic rumor. No part in the 960 architecture will EVER
] >replace the x86 line. Where did you hear such lunacy ? 
]
] There was talk about a year ago that the MP# pin wouldn't be static in
] a 960-like part which would allow a 486 to co-exist with this part
] which installed in the OverDrive(tm) socket.

Well, I don't hear everything that's said everywhere, but I do work
in the i960(tm) processor Architecture group here at Intel, and I 
never heard anyone plan to do anything of the kind.

I won't, however, comment on what we do plan to do. That's not my job.
--
Dennis O'Connor			doconnor@sedona.intel.com
From: mas@aero.org (Marcus A.Shaw)
Newsgroups: comp.sys.intel
Subject: Intel's Latest Party Line
Date: 11 Jan 1993 21:30:49 GMT
Organization: The Aerospace Corporation, El Segundo, CA
NNTP-Posting-Host: aerospace.aero.org

I just got back from a briefing given by a guy named Augustine
who was identified as an "intel architect from the last 15 years".
He said that he had been involved with the design and rollout of 
every x86 chip since the stone age.  He had the usual intel fluff info,
but was very helpful in describing a lot of topics.  He discussed the
"environmental computer" projects, the Overdrive chip, the entire
intel architecture and the future of intel projects.  He introduced 
the iComp average and showed the performance numbers that were posted
here a couple of notes ago.  Here were some high (and low) lights of
his briefing (all on his words... not guarantees):

* the Pentium(tm) will be released in this quarter of 1993.  He has seen
  a working Pentium system with DOS/Windows/Lotus Display software running
  last year (in July).  Systems with a Pentium/PCI architecture will be
  available by mid-year.  The cheapest Pentium systems will be around 
  $5000.

* the Pentium will have a 64-bit path.  The chip design is as follows:
     
  20% for FPU (a significant increase to put the Pentium on the same
      math level as workstations.  Much faster FPU)
  15% for Superscalar pipelines/architecture
  10% for x86 compatibility
  20% for on board cache
  10% for connecting to the system
  15% for other stuff.

* iComp was designed to stomp out the 386 chips (my opinion) and their
  clones.  The 486SX20 shows up worse than the 386DX by this standard. 

* The pentium can execute 2 instructions simultaneously (code willing)
  and two pentium processors can work concurrently for something he
  called "non-stop" computing which will include error trapping between
  the two.  

* Compilers for the Pentium were written 1-1.5 years ago and will be   
  available.  The optimization done on these compilers will improve
  i486 performance by about 8%.  The were written to take full advantage
  of the superscalar architecture of the Pentium and the compilers were
  given away to software vendors.

* i486/66DX2 systems with the P24 socket (Pentium upgradeable) will be
  available in the next month (should beat the Pentium systems out, 
  but not necessarily).  Intel is now dedicated to fixing the pin    
  structure of the next generation architecture when the current generation
  chip is released.  Therefore, the pin set of the P6 will be set when the
  Pentium comes out.

There were a lot of other questions and answers, and if anyone has any
that may have been asked, I will try to answer them.  The guy would not
release any speed or Mflops info, but did say that it was 5-7 times faster
than the current architecture.  Literature that he passed out indicated that
Intel wants to have 100 million transistor chips by the year 2000 with full
x86 compatibility.

later

*ice*
  have been released to all the software companies.  Th
  
  delay
Newsgroups: comp.sys.intel
Subject: Re: Pentium to be Scrapped?!
From: Spartacus/CUNY LC NY <LENBC@CUNYVM.BITNET>
Date: Sunday, 10 Jan 1993 21:41:05 EST
Organization: City University of New York/ University Computer Center

In article <1993Jan6.235812.18764@netcom.com>, feustel@netcom.com (David
Feustel) says:
>
>I heard a rumor today that Intel is seriously thinking about
>scrapping the Pentium for another chip architecture (the 960mx?). Can
>anyone confirm/deny/amplify this rumor?
>--
>Dave Feustel N9MYI <feustel@netcom.com>

If Intel scraps the Pentium, then what about all those people
who have bought new 486 based systems during the price wars
this fall with the intent to upgrade to the p24t?

-------
------------------------------+             All The Best,
Reply To:                     |
     LenBC@CunyVM.Cuny.Edu    |             Edward Galarza
     LenBC@CunyVM.BitNet      |             Brooklyn College Of The
     IRC: Spartacus           |             City University Of New York
------------------------------+             "Que viva el OS/2! v2.1"
Newsgroups: comp.sys.intel
From: daya@ncb.gov.sg (Thayalam Chinnayya)
Subject: Scrapping i386DX ?
Keywords: intel chips 386DX
Organization: National Computer Board, Singapore
Date: Fri, 8 Jan 1993 06:19:03 GMT

I heard this other rumour that Intel would be dropping / scrapping the 
386 DX line of processors. Would anybody like to amplify / deny / respond
to this comment ? With this rumour, would the entry-level be 486SX instead ?


Email : daya@ncb.gov.sg

Newsgroups: comp.sys.intel
From: wbeebe@bilver.uucp (Bill Beebe)
Subject: Re: Pentium to be Scrapped?!
Organization: W. J. Vermillion - Winter Park, FL
Date: Sun, 10 Jan 1993 03:34:12 GMT

In article <DOCONNOR.93Jan8142700@potato.sedona.intel.com> doconnor@sedona.intel.com (Dennis O'Connor) writes:
>
>wbeebe@bilver.uucp (Bill Beebe) writes:
>] the P6 (which is derivative of the P5, I'm sure),
>
>Sorry, you're completely incorrect. Both are/will be members of
>X86 architecture family, but P6 is no more a derivative of
>the Pentium(R) CPU than Pentium was derivative of the Intel486(R).

You know best, I'm sure. But the only things that the Intel486(R) shares
with the Pentium is the instruction set and the fact they're both made of
silicon. Beyond that, the similarties seem to get real fuzzy. I was trying
to speak of design and process similarities. After all, don't your design
methods become more advanced with each new generation? And I was reading
somewhere that the P5 and P6 development where occuring in this parallel
mode because of a lot of heavy borrowing from the P5.

-- 
William H. Beebe, Jr. - wbeebe@bilver.UUCP
                 UUCP - {ucf-cs,peora,uunet}!tarpit!bilver!wbeebe
                      - bilver Public Access Unix, Orlando FL
                      - (407)644-8327  2400/9600  24 hours  8N1
Newsgroups: comp.sys.intel