HDTenEightyP/NetNews huggingface dataset:
From: bevan@cs.man.ac.uk (Stephen J Bevan)
Newsgroups: comp.specification
Subject: Re: Semantic definition style
Date: 7 Nov 92 14:01:34 GMT
Organization: Department of Computer Science, University of Manchester
In-reply-to: dmason@uwaterloo.ca's message of 5 Nov 92 17:15:27 GMT

In article <DMASON.92Nov5131527@plg.uwaterloo.ca> dmason@uwaterloo.ca (Dave Mason) writes:
   In article <720801988.16035@minster.york.ac.uk> song@minster.york.ac.uk writes:
   > I am aware that there are four different styles to define semantics.
   > 	operational
   > 	denotational
   > 	algebraic 
   > 	axiomatic

   There is also action semantics, as describes by Mosses.  In many ways,
   action semantics is better than the others, but it's also newer.

I don't want to start a "my spec. system better than your spec.
system" but would you (or anybody else) care to expand on the above?

My only exposure to action semantics is via a couple of tech reports
and David Watt's book [1].  From this I get the impression that great
emphasis is put on the readability aspect of the definition.  However,
I'm at a loss to see the difference between the action semantic
definitions given and an equivalent denotational/operational
definition that uses equally well chosen English words instead of
Greek symbols[2].  There must be more to it than just notation, so
could somebody please enlighten me?

bevan

[1] 
@book
{ Watt91
, author=    {David A. Watt}
, title=     {Programming Language Syntax and Semantics}
, publisher= {Prentice Hall International}
, year=      {1991}
}

[2] Use monads if you want to hide "state" and/or "enviroments" in a
    similar fashion to the facets in an action semantic definition :-

@inproceedings
{ Moggi89
, author=    {E. Moggi}
, title=     {Computational lambda-calculus and monads}
, booktitle= {IEEE International Symposium on Logic In Computer Science}
, year=      {1989}
}

@techreport
{ Wadler92
, author=      {Philip Wadler}
, title=       {Comprehending Monads}
, institution= {Department of Computing Science, University of Glasgow}
, address=     {Glasgow, UK, G12 8QQ}
, year=        {1992}
}
Newsgroups: comp.parallel
From: azhao@cs.arizona.edu (Qiang Alex Zhao)
Subject: Q: Express references
Followup-To: comp.parallel
Keywords: express
Organization: Computer Science Dept, Univ of Arizona, Tucson
Date: 13 Nov 92 20:58:50 GMT


Hi there,

Does anybody know where I can find some reference about "Express"? I
know it's commercial -- but I just want to see what it is and what it
supports (especially I'm interested in its "parallel graphics"
stuff)... Thanks a million!

 ---
= Qiang Alex Zhao                 ___       .             ______
  Computer Science Dept          /   )     /|   )          __//  )
  University of Arizona         /   /     /_|  /  _       //    /_   _. ._
  azhao@cs.arizona.edu         (__)(_o   /  (_/(_%__)(   ((____/  )_(_(_(_)

Newsgroups: comp.parallel
From: Dr. C.P. Ravikumar <rkumar@ee.iitd.ernet.in>
Subject: Call for papers
X-Organisation: Indian Institute of Technology, New Delhi.
Organization: Clemson University
Date: Thu, 5 Nov 92 14:15:10 ist

			      CALL FOR PAPERS

	                        VLSI DESIGN : 
                   International Journal of Custom Chip Design,
	                  Simulation, and Testing.


	                        SPECIAL ISSUE ON 
                   PARALLEL SOLUTIONS FOR VLSI DESIGN AUTOMATION


	VLSI DESIGN is a new international journal which will be
	published by Gordon and Breach Publishers starting 1993.
	A special issue on "Parallel Solutions for VLSI Design 
        Automation" is being planned for late 1993.  The guest
	editors for the special issue are Dr. C.P. Ravikumar and
	Prof. L.M. Patnaik.  Papers are sought for the special issue, 
        on topics that are related to parallel architectures and/or 
        parallel algorithms for VLSI design automation applications.

        BACKGROUND

	Algorithms for VLSI/CAD can be highly compute-intensive
	due to large problem sizes involved.  As a result, 
	a number of attempts have been made in the recent past
	to accelerate CAD tasks through the use of parallel
	and distributed processing.  Some of the design tasks for
	which higher speeds are required are -- VLSI Placement
	and Routing, Circuit Simulation, Logic Simulation, High-level
	Synthesis, Test Generation, and Fault Simulation.
	The special issue will focus on parallel implementations
	of design automation.


        INSTRUCTIONS FOR AUTHORS

	Submit 5 copies of the manuscript, not exceeding 35 
        double-spaced typed pages including figures and tables, 
        to Dr. C.P. Ravikumar (address given below).  The topics 
        of interest for the special issue are 

	. Hardware Accelerators for Design Automation Applications
	. Parallel Architectures for Design Automation Applications
	. Parallel Implementations of CAD software on 
		General-Purpose Parallel Computers
	. Hardware/Software Tradeoffs in Designing Accelerators
	. Parallel Algorithms for Combinatorial Optimization


	SUBMISSION DEADLINE

		The papers must be received by the guest editors
	by March 31, 1993.

	GUEST EDITORS


	   Dr. C.P. Ravikumar			    Prof. L.M. Patnaik
        Department of Electrical 		Department of Computer Science
    	     Engineering				and Automation
        Indian Institute of Technology	        Indian Institute of Science
           New Delhi 110016	                     Bangalore 560012
	       INDIA                                        INDIA

     email : rkumar@ee.iitd.ernet.in	         lalit@micro.iisc.ernet.in
     Phone : 653561    Ext. 2224                    344411 Ext. 2520 
                                                    342451 Direct
       Fax : 91-11-6862037			    Fax : 91-812-341683

Newsgroups: comp.parallel
From: pedersen@seas.smu.edu (Ted Pedersen)
Subject: parallel parsing of natural language
Organization: SMU School Of Engineering and Applied Science
Date: Thu, 5 Nov 1992 22:21:06 GMT


I am interested in finding out if anyone knows of work being done in
parallel parsing of natural language. I haven't been able to unearth
much in our library here so I thought I would make a very general
inquiry. If you have seen a journal article, know of someone working
in the area, or have some personal experience in the field I'd like to
hear from you.


* Ted Pedersen                                  pedersen@seas.smu.edu * 
* Department of Computer Science and Engineering,                     *
* Southern Methodist University, Dallas, TX 75275      (214) 692-2126 *




Newsgroups: comp.parallel
From: simons@Think.COM (Joshua Simons)
Subject: Re: a question on C* (Connection Machine) syntax
Organization: Thinking Machines Corporation, Cambridge MA, USA
Distribution: usa
Date: 10 Nov 92 17:39:08

In article <1992Nov9.221103.17282@husc3.harvard.edu> mlevin@husc8.harvard.edu (Michael Levin) writes:


This has been answered privately, but if anyone else cares, C* is complaining
for the same reason an ANSI-compatible compiler would complain: incompatible
types.

-josh simons


   From: mlevin@husc8.harvard.edu (Michael Levin)
   Sender: fpst@hubcap.clemson.edu (Steve Stevenson)

       The following short C* code does not compile. The  error given by
   cs is:

   "x.cs", line 12: bad operand combination for =

      the only difference between lines 12 and 10 is that the
   pre-declaration of b() has a float as an argument, and  the one for
   a() does not. If I change b to take int:plane, it compiles. Why is
   this so? The regular C compiler has no problem with it (without the
   :plane). If anyone knows what the problem is, please let me know at
   mlevin@presto.cs.tufts.edu. 

   shape [128][128]plane;

   int:plane a(int:plane p); 
   int:plane b(float:plane p);

   int:plane (*which_funct(s))()
   char *s;
   {
     if (!stricmp(s,"A"))
       return(a);
     if (!stricmp(s,"B"))
       return(b);
   }

--
simons@think.com
thinking machines corporation
245 first street					tel: 617.234.2844
cambridge, ma  02142-1264				fax: 617.234.4444

Newsgroups: comp.parallel
From: gupta@nmsu.edu (Gopal Gupta)
Subject: Overview paper on Connection Machine/Data Parallel Lisp
Apparently-To: comp-parallel@uu.net
Organization: NMSU Computer Science
Date: Tue, 3 Nov 1992 20:22:58 GMT


I am looking for a reference paper that gives a good overview
of a data-parallel lisp (such as for the Connection Machine).
(Something suitable for a student-presentation in a seminar 
course on Parallel Processing, so manuels are out).

Best Regards


Gopal Gupta
---------------------------------------------------------------------
Department of Computer Science	   email: gupta@nmsu.edu
Box 30001, Dept. 3CS		      	  gupta@compsci.bristol.ac.uk
New Mexico State University	   Ph: +1 (505) 646 6236 
Las Cruces, NM 88003-0001	   Fax: +1 (505) 646 6218
USA
---------------------------------------------------------------------

	 
 

Newsgroups: comp.parallel
From: ccechk@nuscc.nus.sg (Heng Kek)
Subject: RFI: EXPRESS software
Apparently-To: uunet!comp-parallel
Organization: National University of Singapore
X-Newsreader: Tin 1.1 PL4
Date: Sat, 7 Nov 1992 07:28:34 GMT

Hello all,

I've been told that there's a similar software to PVM called
EXPRESS by Parasoft.  Can anyone tell me if I may obtain any
information on EXPRESS in the public domain?  e.g. papers, comments,
reference guides, etc.

Thanks in advance
Heng Kek
National University of Singapore

Newsgroups: comp.parallel
From: dbader@eng.umd.edu (David Bader)
Subject: Re: scalability analysis
Keywords: scalability analysis
Organization: Professional Student, University of Maryland, College Park
Date: Sat, 07 Nov 92 14:33:46 GMT

In article <1992Nov6.195037.19983@hubcap.clemson.edu> chunghsu@pepper.rutgers.edu (Chung-Hsing Hsu) writes:
>
>Can anyone suggest me a good introduction(or survey) for
>scalability analysis of parallel algorithms and architectures?
>I'm especially interested in the metrics which can take both
>into account.

Refer to the following textbook.  It uses the PRAM model to focus on
parallel algorithmic issues, and also uses a Work-Time framework to
analyse parallel algorithms.

JaJa, Joseph.  Introduction to Parallel Algorithms.  Addison-Wesley,
	New York, 1992.


-d

Maryland Address:                Permanent Address:
David A. Bader                   David A. Bader
48 Avonshire Court               1402 Lorain Avenue
Silver Spring, MD 20904          Bethlehem, Pa  18018
(301) 680-3616                   (215) 868-1311

Internet: dbader@eng.umd.edu

Newsgroups: comp.parallel
From: carson@cs.umd.edu (Mark Carson)
Subject: Re: Any parallel algs. for ring topology?
Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742
Date: 11 Nov 92 13:41:49 GMT


Many matrix algorithms work well on rings (and even meshes and tori).
In fact, they're probably the best examples, since generally their
data movement requirements are fairly limited and quite regular.  For
an introduction, see Golub and van Loan, Matrix Computations (the
second edition (1989), not the first).

Mark
-- 
Mark Carson	carson@cs.umd.edu	301-240-7348
Department of Computer Science   University of Maryland, College Park -or-
IBM 182/3F42   800 N. Frederick Ave.   Gaithersburg MD 20879

Newsgroups: comp.parallel
From: stathis@dcs.warwick.ac.uk (Efstathios Papaefstathiou)
Subject: T800/SPARC Benchmarks
Organization: Department of Computer Science, Warwick University, England
Date: Sun, 8 Nov 1992 19:55:40 GMT

Hello,

I am working on a parallel benchmark for image processing. I need
to compare the results of the sequential version of the benchmark,
running on a SUN4 workstation and the results of the parallel
version of the benchmark running on a Parsytec SuperCluster.
In order to analyze the results I need a comparative study of
the T800 and the SPARC. Has anyone heard about an article about
this subject?

Thanks

Stathis Papaefstathiou
University of Warwick
From: tve%crackle.CS.Berkeley.EDU@ucbvax.Berkeley.EDU (Thorsten von Eicken)
Newsgroups: comp.parallel
Subject: Re: Multi-computers, what are they
Keywords: multi-computers, references
Date: 12 Nov 92 05:34:02 GMT
Article-I.D.: hubcap.1992Nov12.130959.1984
Organization: University of California, Berkeley

In article <1992Nov11.130949.12723@hubcap.clemson.edu> mtayler@pilot.njin.net (Mark Tayler) writes:
>
>I am posting this for a friend
>He needs to find information on "multi-computers"
>
>What is the definition of a multi-computer
Some people differentiate between "multiprocessors" and "multicomputers": a
"multiprocessor" has N processors connected via some network to M memories,
a "multicomputer" has N processor+memory modules connected with each other
via some network. The idea is that the former is multiple processors connected
to memory and the latter is mutiple "complete" computers connect with each
other. Since I strongly believe that the latter is taking over the world and
that the former sounds nerdy, I use "multiprocessor" for both.  (Ha! flame!)

>Are there any machines out there that are "multi-computers"
Lots: CM-5, IPSC/*, nCUBE/*, all the transputer thingies, etc...
You have to hunt for multiprocessors (unless you're happy with a handful
of processors).

>What are other names for "multi-computers"
>Are there any decent general referces to "multi-computer" systems.
Hum, I don't have a favorite book, any one volunteer a reference?

	Thorsten von Eicken
From: psk%magus@uunet.UU.NET (Kumaran Punnaippakam)
Newsgroups: comp.parallel
Subject: Re: 3rd conference on hypercube concurrent computers
Date: 11 Nov 92 15:21:16 GMT
Article-I.D.: hubcap.1992Nov12.131009.2117
Organization: Pencom Software


In article <1992Nov10.182202.1346@hubcap.clemson.edu> rmunk@cs.uni-sb.de  
(Ralf-Werner Munkes) writes:
> 
> who can tell me where i can find (via ftp) articles from the
> 
> 3rd conference on hypercube concurrent computers  ?
> 
> 
> i'm interested in everything concerning intel's ipcs-systems
> 
> 
> Ralf-Werner Munkes                email : rmunk@sol.cs.uni-sb.de
> Department of Computer Science
> Universitas saraviensis
> Saarbruecken, GERMANY


I think the 3rd conference and the ones after that were renamed as
Distributed Computing ..........(I don't remember the exact name).
I remember, not too long ago, that I was searching for some articles
in the 3rd and 4th conference on hypercube concurrent computers
and later discovered that it underwent a change in name and also
it was no longer under SIAM.

So, search under Distributed da da da in your library.
Good luck,
--Kumaran.
Newsgroups: comp.parallel,comp.theory
From: parallel@netcom.com (B. Mitchell Loebel)
Subject: The PARALLEL Processing Connection - Meeting notice
Apparently-To: comp-parallel@ames.arc.nasa.gov
Organization: Netcom - Online Communication Services  (408 241-9760 guest) 
Distribution: usa
Date: Sun, 8 Nov 1992 18:49:48 GMT

November 9th - Massively Parallel Processing in Japan --
               Striking Win - Win Partnerships Through Joint 
               Development!

Japan's Fifth Generation Project  involved Artificial Intelligence and 
Massively Parallel Processing; the Real World Computing Initiative 
is the follow-on program. Their Intelligent Manufacturing Systems 
program would create "flexible factories using computers and robots 
to instantly modify assembly operations at plants around the world". 
And the Japanese have offered to share research, development, and 
funding with U. S. and European enterprises to bring these 
endeavors to fruition. Professor Robert Burmeister, director of the 
U.S. - Japan Technology Management Center at Stanford 
University will present a detailed view of these two important 
programs, the concomitant ground floor joint venture/entrepreneurial 
opportunities, and the political obstacles that have stalled them.

The meeting will take place at 7:30 PM at Sun Microsystems at 901 
South San Antonio Road in Mountain View, California. 
Southbound travelers exit 101 at San Antonio; northbound attendees 
also exit at San Antonio and take the overpass to the other side of 
101. There is an $8 visitor fee for non-members and members ($40 
per year) will be admitted free.

Please be prompt; we expect a capacity attendance; don't be left out 
or left standing.

For further information contact:

-- 
B. Mitchell Loebel                                      parallel@netcom.COM
PARALLEL Processing Connection                                 408-732-9869

Newsgroups: comp.parallel
From: Dr. C.P. Ravikumar <rkumar@ee.iitd.ernet.in>
Subject: Special Issue (Call For Papers)
X-Organisation: Indian Institute of Technology, New Delhi.
Organization: Clemson University
Date: Tue, 10 Nov 92 23:57:59 ist


			      CALL FOR PAPERS

	                        VLSI DESIGN : 
                   International Journal of Custom Chip Design,
	                  Simulation, and Testing.


	                        SPECIAL ISSUE ON 
                   PARALLEL SOLUTIONS FOR VLSI DESIGN AUTOMATION


	VLSI DESIGN is a new international journal which will be
	published by Gordon and Breach Publishers starting 1993.
	A special issue on "Parallel Solutions for VLSI Design 
        Automation" is being planned for late 1993.  The guest
	editors for the special issue are Dr. C.P. Ravikumar and
	Prof. L.M. Patnaik.  Papers are sought for the special issue, 
        on topics that are related to parallel architectures and/or 
        parallel algorithms for VLSI design automation applications.

        BACKGROUND

	Algorithms for VLSI/CAD can be highly compute-intensive
	due to large problem sizes involved.  As a result, 
	a number of attempts have been made in the recent past
	to accelerate CAD tasks through the use of parallel
	and distributed processing.  Some of the design tasks for
	which higher speeds are required are -- VLSI Placement
	and Routing, Circuit Simulation, Logic Simulation, High-level
	Synthesis, Test Generation, and Fault Simulation.
	The special issue will focus on parallel implementations
	of design automation.


        INSTRUCTIONS FOR AUTHORS

	Submit 5 copies of the manuscript, not exceeding 35 
        double-spaced typed pages including figures and tables, 
        to Dr. C.P. Ravikumar (address given below).  The topics 
        of interest for the special issue are 

	. Hardware Accelerators for Design Automation Applications
	. Parallel Architectures for Design Automation Applications
	. Parallel Implementations of CAD software on 
		General-Purpose Parallel Computers
	. Hardware/Software Tradeoffs in Designing Accelerators
	. Parallel Algorithms for Combinatorial Optimization


	SUBMISSION DEADLINE

		The papers must be received by the guest editors
	by March 31, 1993.

	GUEST EDITORS


	   Dr. C.P. Ravikumar			    Prof. L.M. Patnaik
        Department of Electrical 		Department of Computer Science
    	     Engineering				and Automation
        Indian Institute of Technology	        Indian Institute of Science
           New Delhi 110016	                     Bangalore 560012
	       INDIA                                        INDIA

     email : rkumar@ee.iitd.ernet.in	         lalit@micro.iisc.ernet.in
     Phone : 653561    Ext. 2224                    344411 Ext. 2520 
                                                    342451 Direct
       Fax : 91-11-6862037			    Fax : 91-812-341683
From: kumar@moose.cs.umn.edu (Vipin Kumar)
Newsgroups: comp.parallel
Subject: JPDC Special Issue on Scalability
Keywords: scalability, large-scale parallel computers, analysis
Date: 12 Nov 92 02:32:34 GMT
Article-I.D.: hubcap.1992Nov12.130946.1814
Organization: University of Minnesota
Apparently-To: comp-parallel@uunet.uu.net


			CALL  FOR  PAPERS

Special Issue of the Journal of Parallel and Distributed Computing (JPDC) on 

        Scalability of Parallel Algorithms and Architectures 


Papers are solicited for a special issue of the Journal of Parallel and
Distributed Computing on scalability of parallel algorithms and architectures
planned for April 1994.
The issue will publish about eight regular papers (about 35 double-spaced
manuscript pages) and upto four research notes (about 15 double-spaced
manuscript pages).

The objective of this special issue is to bring together the research
done by theoreticians,  architecture designers and application developers
on scalability analysis of large-scale parallel systems. 
Topics of interest include but are not limited to  
Scalability metrics, Scalable parallel algorithms, Scalability analysis
of selected parallel algorithm-architecture combinations, Cost effectiveness
of scaling parallel architectures in terms of performance, Methods of scaling
up applications, etc.

Authors should follow the JPDC manuscript format
as described at the end of each JPDC issue. Five copies of complete 
manuscript should be sent to the guest editor by April 5, 1993. The authors
will be notified of the decision by September 1, 1993 and the final manuscript
ready for publication will be due by October 1, 1993.


				Guest Editor:

				Prof. Vipin Kumar
				Department of Computer Science
				200 Union Street S.E., EE/CSci 4-192
				University of Minnesota
				Minneapolis  MN 55455

				Tel:   (612) 624-8023
				Fax:   (612) 625-0572
				Email: kumar@cs.umn.edu
From: cnews@umr.edu (UMR Usenet News Post)
Subject: Any parallel algs. for ring topology?
Apparently-To: uunet!comp-parallel@uunet.uu.net
Originator: junlin@mcs213k.cs.umr.edu
Organization: University of Missouri - Rolla
Date: Mon, 9 Nov 1992 22:47:14 GMT

Some parallel algorithms are desinged for some specific kinds of 
interconnection networks among processors, like mesh or hypercube. 
Is there any parallel algotiths or applications that are suitable for 
"ring" type of topology among processors?  Someones refer me that 
molecular dynamics can be simulated using ring topology in parallel 
computers.  Any other application for ring? 

Does parallel string matching problem uses ring topology?  Any comments? 


Thanks, 

Junlin Liu

-- 
+-------------------------------------------------------------------+
|    Junlin Liu     | Computer Science Dept.   | (O) (314) 341-6434 |
|    -----------    | Univ. of Missouri, Rolla |     ----------     |
| junlin@cs.umr.edu | Rolla, MO 65401          | (H) (314) 341-3166 |


Newsgroups: comp.parallel
From: karhinen@cc.helsinki.fi (Anssi Karhinen)
Subject: KSR coherency
Apparently-To: comp-parallel@mcsun.EU.net
Organization: University of Helsinki
X-Newsreader: TIN [version 1.1 PL6]
Date: Thu, 5 Nov 1992 07:13:17 GMT


There have been some postings in this group that describe
the function of the ALLCACHE-memory on the KSR 1 in detail.
I have missed one detail or it hasn't been mentioned.

The machine has 256 KB first level I- and D-caches. How are these
caches kept coherent with the 32 MB ALLCACHE memory in each PE?

Many thanks, Anssi


Newsgroups: comp.parallel
From: laisietl@iscs.nus.sg
Subject: Info. on constraint-based object-oriented concurrent language
Apparently-To: uunet!comp-parallel
Reply-To: LAISIETL%NUSDISCS.BITNET@nusvm.nus.sg
Organization: Dept. of Information Systems and Computer Science, National University of Singapore
Date: Thu, 5 Nov 1992 09:01:41 GMT

Dear Netters,
  Does anyone of you have experience or info on constraint-based 
object-oriented concurrent language ?? If so, pls mail it to me ...
If there is enough response , I may post a summary ...

Thank you !!

Regards,
  S L Lai
From: ccechk@nuscc.nus.sg (Heng Kek)
Newsgroups: comp.parallel
Subject: Q: PVM vs EXPRESS
Date: 12 Nov 92 01:52:59 GMT
Article-I.D.: hubcap.1992Nov12.130941.1744
Organization: National University of Singapore
Apparently-To: uunet!comp-parallel
X-Newsreader: Tin 1.1 PL4

Dear Parallelites

I have a need to evaluate 2 parallelizing softwares: PVM and
EXPRESS.  I'm aware that EXPRESS is commercial.

Can anyone give a critique on the relative merits of the 2 packages?
Experiences based on both will be most welcome.  However, if this
has been asked before, did someone by any chance archive the
discussion and make it retrievable in the public domain?

Thanks for listening, and hope to hear from some of you.

Yours truly
Heng Kek
Computer Centre
National University of Singapore
Newsgroups: comp.parallel