HDTenEightyP/NetNews huggingface dataset:
From: byron@sfsuvax1.sfsu.edu (Byron Chun)
Subject: Re: help on AMD
Organization: California State University, Sacramento
Date: Wed, 2 Sep 1992 20:00:31 GMT

odysee@kobra.DoCS.UU.SE (Tobias Thomson) writes:
: I need a lot of help. In april this year I bought a 386-33 motherboard.
: The life was wonderful (upgrading from 286-6) but then there was
: bootingproblems, the system hangd and the frequence of the problems
: increced (?). I opened the computer and saw the 386 was an Am386. 
: 
: My problem is to convince the seller that Am386 is not good and I have
: read some artikels in news about the same problems (with the board not
: the seller) and now they a gone. Can anyone send me these and some other
: info about it?
: 
: odysee@csd.uu.se
: 
:

There is nothing wrong with my AMD processor.  Are you sure you did  
not put some old 6MHz boards into your new system?  It sure sounds   
like your "upgrade" did not include all of the peripheral equipment.

If your old boards are too slow for the new system board, try changing
the bus clock speed on your system board to accomodate the slowest
board you have (probably your video board or an MFM disk controller)
  
-- 
byron@sfsuvax1.sfsu.edu           =====================================
                                  | My employer will allow me to have |
"It's not in my job description,  | an opinion.  They just won't back |
 but I'll do it anyway."          | me if things go sour.             |
Newsgroups: comp.sys.intel
From: aswin@nimbus.worldbank.org (aswin kokilananda)
Subject: Re: X Windows
Organization: WORLD BANK
Date: Fri, 28 Aug 1992 15:38:45 GMT

In article <8eawNJy00VpcIX9VBR@andrew.cmu.edu>, Brian Patrick Dunphy <bd29+@andrew.cmu.edu> writes:
> 
> I'm trying to run X windows on a 386-40 connected to an internet network
> using a 10-BaseT network card.  What is the best approach?  
> I've seen the new Desqview/x and it seems to have the options that I
> want but is a little more expensive than I would like.  I'm currently
> running windows 3.1 and would prefer something that runs under it.
> 
> Thanks, 
> Brian 
> 
> BD29@ANDREW.CMU.EDU
> 
> 
>  I'm using HCL-eXceed/W, an X Window Server implementation for PCs running Windows.
 It's working great for me. You may want to give it a try, 
	VENDOR: 2900 John Street, Unit4, Markham, Ontario, Canada L3R 5GS
									Phone (416) 470-1203

aswin@nimbus.worldbank.org
 			

Newsgroups: comp.sys.intel
From: wbeebe@bilver.uucp (Bill Beebe)
Subject: Re: Future of i860 line
Organization: W. J. Vermillion - Winter Park, FL
Date: Sat, 29 Aug 1992 03:01:15 GMT

In article <BtM3Mn.2BC@pgroup.com> lfm@pgroup.com (Larry Meadows) writes:
>
>It is my personal opinion that Intel's failure to properly market and
>position the i860 resulted in its lack of mainstream acceptance.  Intel
>started out marketing the i860 as the workstation chip, then switched
>to the graphics chip, then to the supercomputing chip, even before
>vendors such as OKI had shipped any non-beta workstations.

Nope. Before it became a mainstream CPU it was meant to be marketed as
a special support chip for the i486. The story I got was that when Intel
went around and showed the i860 to it's biggest clients that those
clients wanted the i860 marketed as a separate CPU. I had heard rumours
for some time that a new chip was coming out that would take the place
of the 82786 and compete against the TI34020. Whether the i860 was
that chip, I suppose no one will ever know.

-- 
William H. Beebe, Jr. - wbeebe@bilver.UUCP
                 UUCP - {ucf-cs,peora,uunet}!tarpit!bilver!wbeebe
                      - bilver Public Access Unix, Orlando FL
                      - (407)644-8327  2400/9600  24 hours  8N1
Newsgroups: comp.sys.intel
From: fredch@phx.mcd.mot.com (Fred Christiansen)
Subject: Re: p24t
Organization: Motorola Computer Group, Technical Systems Operations
Date: Wed, 2 Sep 1992 15:38:09 GMT

In article <6107@gumby.Altos.COM> rcollins@altos.COM (Robert Collins) writes:
>In article <b_lya#b@rpi.edu> gilem@aix02.ecs.rpi.edu (Michael R. Gile) writes:
>>Could someone please tell me what the p24t is/will be?
>
>Yes, it's the 486 DX2 that you've heard about, but with a twist.
>If memory serves me correctly, it will not be a clock-doubler for
>the '486DX (as the DX2 is), but for the '486SX.

An Intel promo sheet that some dealers are handing out promotes the
OverDrive technology.  There was a separate page for each of these:
    OverDrive upgrade for 486SX ("vacancy" area; evidently distinct from 487SX)
    OverDrive upgrade for 486DX (and not a DX2)
    OverDrive upgrade for 486DX2 (in the future)

Could someone from Intel comment on this, as to whether I understood correctly.
Man, things are getting complicated with all these chip variations (e.g.,
also things like RapidCAD).
-- 
Fred Christiansen, Motorola, 2900 S Diablo Way, Tempe, AZ 85282  "Canajun, eh?"
fredch@phx.mcd.mot.com  ||  uunet!phx.mcd.mot.com!fredch  ||  +1 602-438-3464
  On Attitude & the Immune System:  A sound heart is the life of the flesh:
    but envy the rottenness of the bones.  Prov 14:30
Newsgroups: comp.sys.intel
From: gweil@ichips.intel.com (Garry A. Weil)
Subject: Re: PLM programming query
Keywords: PLM 8051
Organization: MultiMedia Software Tools Group, Intel Corp.
Date: Wed, 26 Aug 1992 16:58:51 GMT

In article <1992Aug26.093356.6125@canon.co.uk> chudley@canon.co.uk (Martin Chudley) writes:
>Path: intelhf!ichips!iWarp.intel.com|uunet!pipex!unipalm!uknet!canon.co.uk!chudley
>From: chudley@canon.co.uk (Martin Chudley)
>Newsgroups: comp.sys.intel
>Subject: PLM programming query
>Keywords: PLM 8051
>Message-ID: <1992Aug26.093356.6125@canon.co.uk>
>Date: 26 Aug 92 09:33:56 GMT
>Organization: Canon Research Centre Europe Ltd
>Lines: 16

>Apologies for this, it shouldn't be necessary but the PLM manual isn't very
>helpful on this subject.

>All I want to do is pass a string to a procedure. At present I'm using the
>dot operator to pass a string constant in the function call and a based variable
>to access it inside the procedure, and I get garbage. Can anyone send a few
>lines of code showing how to do this - maybe I should just fork out for
>something sensible like a C compiler.

>Thanks

>-- 
>Martin Chudley (Postmaster)

>ARPA : chudley@canon.co.uk                              Voice : +44 483 574325
>UUCP : ...seismo!mcsun!uknet!canon!chudley              Fax   : +44 483 574360
I am not sure about this for the 8051, but PLM for x86 the . operator 
returns just a 16-bit pointer. The @ operator returns a 32-bit pointer.
----------
Garry Weil

gweil@ichips.intel.com		After August 30th:gweil@ibeam.intel.com
gweil@garry.intel.com				  gweil@garry.ht.intel.com
garry_weil@ccm.hf.intel.com			  garry_weil@htccm2.ht.intel.com
uunet!intelhf!ichips!gweil                        uunet!intelhf!ht!ibeam!gweil
From: davidsen@ariel.crd.GE.COM (william E Davidsen)
Newsgroups: comp.sys.intel
Subject: Re: 486 / 586(P5) Upgrade
Date: 26 Aug 92 13:32:24 GMT
Reply-To: davidsen@crd.ge.com (bill davidsen)
Organization: GE Corporate R&D Center, Schenectady NY

In article <1992Aug24.013528.55@wsuhub.uc.twsu.edu>, zxnoueih@wsuhub.uc.twsu.edu (...VALENCIA...) writes:
| A question concerning 486 to 586 upgradability after reading
| some of the replies: Are upgrades possible only on EISA based systems?
| If yes, why? If no, then I guess it was a stupid question...:-)

  There's nothing inherent in the P5 (or any CPU) which needs EISA.
Since the memory is on the motherboard on all modern systems, the bus
handles i/o only. Now, as far as being plug-in replacements (pin
compatible), I doubt it. There may be technical reasons, but the main
reason is that Intel loves to use new pinouts, as they did on the 486SX.

  By doing this they require new board design, which raises the price,
increases inventory, and ups the price to the consumer while delivering
no added functionality. Did I mention that they don't really seem to
care about public relations? If the 486SX had been pin compatible they
could have claimed it was a more cost effective solution for those who
don't need the FPU, and people would have had a good feeling toward them.

  I wonder if anyone at Intel sees a connection between the move to
other vendors when possible and their packaging, pricing, and slipped
delivery policies.

-- 
bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
    I admit that when I was in school I wrote COBOL. But I didn't compile.
From: davidsen@ariel.crd.GE.COM (william E Davidsen)
Newsgroups: comp.sys.intel
Subject: Re: p24t
Date: 26 Aug 92 13:51:57 GMT
Reply-To: davidsen@crd.ge.com (bill davidsen)
Organization: GE Corporate R&D Center, Schenectady NY

In article <0105010F.bsia3c@mprnews.mpr.com>, mslater@mpr.com (Michael Slater) writes:

| for the write-back cache. Intel has defined a new OverDrive
| socket, which it recommends for DX2 systems, that has an extra
| row of pins surrounding the standard OverDrive socket. Most of
| these pins are power and ground; six of them are being
| documented only for customers who sign non-disclosure
| agreements (these are the write-back cache support pins).

  Just a note, I was unable to get Intel to send me such an agreement,
or even get them to admit they would do such a thing. They appear to be
claiming that this is only done for customers who make systems for
retail resale, and is not available to customers who want to embed x86
systems in commercial products, or use them inhouse. The sales 'droid
had been trained to ask "Do you manufacture motherboards for resale to
other vendors or end users?" and if the answer was no to say "that
information is not available to end users at this time."

  Since the P5 is not currently deliverable, it turned out that
performance was not in any way an issue after all.

-- 
bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
    I admit that when I was in school I wrote COBOL. But I didn't compile.
Newsgroups: comp.sys.intel
From: odysee@kobra.DoCS.UU.SE (Tobias Thomson)
Subject: help on AMD
Organization: Dept, of Computer Systems, Uppsala University, Sweden.
Date: Wed, 2 Sep 1992 17:50:11 GMT

I need a lot of help. In april this year I bought a 386-33 motherboard.
The life was wonderful (upgrading from 286-6) but then there was
bootingproblems, the system hangd and the frequence of the problems
increced (?). I opened the computer and saw the 386 was an Am386. 

My problem is to convince the seller that Am386 is not good and I have
read some artikels in news about the same problems (with the board not
the seller) and now they a gone. Can anyone send me these and some other
info about it?

odysee@csd.uu.se

 
Newsgroups: comp.sys.intel
From: peter@citr.uq.oz.au (Peter Klavins)
Subject: Re: 8051 C compilier
Keywords: 8051
Organization: Prentice Centre, University of Queensland
Date: Thu, 3 Sep 1992 07:18:18 GMT

hoffberg@phebos.aps.anl.gov (Mike G. Hoffberg) writes:

>Does anyone know of a US distributer for Keil Electronics?  Or of any
>other compiliers on the market?

Give these people a go.  They have an 8051 C Compiler and Assembler ...
And cheap, from what I remember ...

Hi-Tech Software     Contact:  Clyde Smith-Stubbs
PO Box 103                     clyde@hitech.com.au
Alderley QLD 4051              Phone:  +61 7 300 5011
Australia                      Fax:    +61 7 300 5246
--
------------------------------------------------------------------------
 Peter Klavins    Internet: peter@citr.uq.oz.au   Fidonet:    3:640/821
 Centre for Information Technology Research       Phone: +61 7 365 4321
 University of Queensland QLD 4072 Australia      Fax:   +61 7 365 4399
Newsgroups: comp.sys.intel
From: ross@kaos.ingr.com (Ross Erickson)
Subject: White paper for P5, P24T, P54C, and P6
Reply-To: ross@kaos.b11.ingr.com
Organization: Intergraph Corporation
Date: Mon, 31 Aug 1992 15:13:18 GMT

--
Where can I get some good summary information ala a "white paper" of
sorts for the above listed chips?  I'd like to do some studying of
what these different CPUs provide (plan to provide).  Thanks.

|------------------------------------------------------------------|
|  Ross Erickson             |                                     |
|  ross@kaos.b11.ingr.com    | "No individual raindrop considers   |
|  205-730-4019 - voice      |  itself responsible for the flood." |
|  205-730-6445 - fax        |                                     |
|  Internet: 129.135.252.87  |                                     |
|------------------------------------------------------------------|
From: t9214309@phillip.edu.au
Newsgroups: comp.sys.intel.ipsc310
Subject: ipsc simulator ??
Date: 25 Aug 92 20:15:31 GMT
Organization: RMIT (Bundoora Campus)

Dear Netters:
I would like to know if there is any public domain version of the ipsc
simulator. I am looking for one to run on the SUN SPARC or the SONY W/S.
I remember that UIUC had a simulator that works on the SUN W/S. Could 
someone out there send me instructions of how to get one?
Thanx in advance
Madhav
e-mail : t9214573@phillip.edu.au
From: rcollins@gumby.Altos.COM (Robert Collins)
Newsgroups: comp.sys.intel
Subject: Re: p24t
Date: 28 Aug 92 22:40:45 GMT
Reply-To: rcollins@altos.COM (Robert Collins)
Organization: Altos Computer Systems, San Jose, CA

In article <b_lya#b@rpi.edu> gilem@aix02.ecs.rpi.edu (Michael R. Gile) writes:
>Could someone please tell me what the p24t is/will be?
>I have heard several vendors (including zeos) claim 
>they have a slot for it, and would like to know what
>good it does.  
>
>mike (gilem@rpi.edu)

Yes, it's the 486 DX2 that you've heard about, but with a twist.
If memory serves me correctly, it will not be a clock-doubler for
the '486DX (as the DX2 is), but for the '486SX.



-- 
"Worship the Lord your God, and serve Him only."  Mat. 4:10
Robert Collins		UUCP:  ...sun!altos86!rcollins
Home:  (408) 225-8002             rcollins@altos.COM
Work:  (408) 428-3642
Newsgroups: comp.sys.intel
From: friedman@col.hp.com (John Friedman)
Subject: Re: Future of i860 line
Date: Wed, 2 Sep 1992 16:30:31 GMT
Organization: HP Colorado Springs Division

mneideng@thidwick.acs.calpoly.edu (Mark Neidengard) writes:
> Wait up.  You speak as if the i860 is not superscalar; it sure as heck IS!
> 
> It has MULTIPLE pipelines, which can be used concurrently.  That's the
> textbook definition of superscalar microprocessing.

Actually, superscalar means that the processor can START executing
instructions concurrently, in the same clock cycle, that is.  The 860's
cannot do this, but they can be processing multiple instructions at the same
time that started at different times.

John Friedman
friedman@col.hp.com

Newsgroups: comp.sys.intel,comp.sys.palmtops
From: payner@netcom.com (Rich Payne)
Subject: Re: Flash Cards
Date: Thu, 27 Aug 92 21:38:44 GMT
Organization: Netcom - Online Communication Services (408 241-9760 guest)

In article <1992Aug27.171032.14617@uwm.edu> anthony@csd4.csd.uwm.edu (Anthony J Stieber) writes:
>In article <fr-n==q.payner@netcom.com> payner@netcom.com (Rich Payne) writes:
>
>>This? Flash EPROM sounds interesting, but it still seems to me that
>>the voltage and power requirements to -write- to it are far above the
>>power requirements for a small drive. It would not seem that the present
>>FLASH EPROM would be a replacement for current small HD's. But I think
>>it still would be usefull. 
>
>Voltage isn't the same as power.  

Agreed, but voltages above that provided by the batteries requires
a DC-DC converted, which sucks power as well. So for portable devices,
power delivered will not equal power consumed for voltages above the
battery voltage. 

>                                      The 4MB card consumes 0.15 watts
>active, and 0.04 watts standby.  

By active, do you mean reading, writing, or both?

>                                  The main problems with Flash EPROM are
>that it takes on the average 2 seconds to erase a 256KB zone.  

Can several zones be erased simultaneously? Does this increase power
consumption? And how does the file system do small writes without
erasing other files? Does it require 256K of cache, and if so will
this not increase write times by the amount needed to load/read the
cache?

>                                                                    The
>entire zone must be erased.  Once erased, writes take 10us per byte and
>reads are 200ns maximum, data transfer at 8MB/s.  The card can be shut
>down between accesses so it takes no power, then be instantly powered
>back up.  A disk drive will take a few seconds just to spin up.  Disk
>drives also have head and rotational latency.  Note that all the figures
>I have are for 4MB cards, 20MB cards may differ significantly.

Hopefully by being improved. :^)
 
>I could certainly see a 20MB Flash card replacing a Kittyhawk or
>similar drive in at least some applications.  Simply by size and power
>consumption, two or more 20MB cards would fit where only one hard drive
>would.  They may end up more complementary that competitive however.
>Even a drive as small as the Kittyhawk could probably have a few
>megabytes of Flash memory for use as cache.  This could give the low
>power and speed of Flash with the low cost of disk.
>
>--
><-:(= Anthony Stieber	anthony@csd4.csd.uwm.edu   uwm!uwmcsd4!anthony
>

Rich

payner@netcom.com


Newsgroups: comp.sys.intel
From: fredch@phx.mcd.mot.com (Fred Christiansen)
Subject: Re: Upgradability question for INTEL staff
Organization: Motorola Computer Group, Technical Systems Operations
Date: Tue, 25 Aug 1992 15:32:35 GMT

In article <183203@pyramid.pyramid.com> atam@pyrps5.eng.pyramid.com (Alexander Tam) writes:
>One of the main reason I purchased a DECpc is because you, Intel, help
>them make the inside and I assume a DECpc will have the *GREATEST* compatibility
>and upgradability to 586/P5 over any other pc clones.

Generally motherboards are quite replaceable, but you ought to ask.
Note that DEC has just announced that they will start making their
own PC's, as opposed to buying them from Intel, Tandy, and Olivetti.
-- 
Fred Christiansen, Motorola, 2900 S Diablo Way, Tempe, AZ 85282  "Canajun, eh?"
fredch@phx.mcd.mot.com  ||  uunet!phx.mcd.mot.com!fredch  ||  +1 602-438-3464
  On Attitude & the Immune System:  A sound heart is the life of the flesh:
    but envy the rottenness of the bones.  Prov 14:30
Newsgroups: comp.sys.intel
From: gideony@microsoft.com (Gideon Yuval)
Subject: Re: PLM programming query
Date: 27 Aug 92 14:30:42 GMT
Organization: Microsoft Corporation
Keywords: PLM 8051

PL/M-51 pointers get dereferenced in RAM, unless the ROM
keyword is used in the BASED declaration. Add ROM to the BASED
declaration, & try again.
-- 
Gideon Yuval, gideony@microsoft.com, 206-882-8080 (fax:-883-8101;TWX:160520)
Newsgroups: comp.sys.intel
From: gideony@microsoft.com (Gideon Yuval)
Subject: Re: Future of i860 line
Date: 28 Aug 92 02:17:12 GMT
Organization: Microsoft Corporation

In article <BtM3Mn.2BC@pgroup.com> lfm@pgroup.com (Larry Meadows) writes:
...
>RISC chip.  In fact, at equivalent clock rate with a proper memory system
>design, I'd happily put the i860-XP as-is up against Alpha, HP, or RS6000,
>and it would clearly beat the Sparc.

In integer SPECmarks per MHz, the 860 is _slower_ than the 486.
I'd be really surprised if DEC and IBM, without all the X86 dead wood
on their backs, cannot to a bit better still.
-- 
Gideon Yuval, gideony@microsoft.com, 206-882-8080 (fax:-883-8101;TWX:160520)
Newsgroups: comp.sys.intel
From: izahi@bsc.no (Raul Izahi Lopez Hernandez)
Subject: Re: Intel 486 on-chip cache in a multiprocessor config ?
Organization: Bergen Scientific Centre, Bergen, NORWAY
Date: Tue, 1 Sep 1992 08:23:58 GMT

In article <1992Aug31.170710.7898@jpradley.jpr.com> adykes@jpradley.jpr.com (Al Dykes) writes:
>Can the 486  on-chip cache maintain cache coherency in 
>a shared memory MP configuration ? 
>
>Al Dykes
>---------
>adykes@jpr.com

   Yes, it has bidirectional address lines.
   I don't recall, however, if it can implement Exclusive/Shared/Dirty/Invalid
status on the cache and source its data to other caches, or will only flush
the cache or a single line when an address in its cache is given to the chip
from an outside system. 
-- 
         -----> All opinions expressed here are my own, not IBM's <-----
Raul Izahi Lopez	Izahi Engineering
izahi@bsc.no		IBM Bergen Environmental Sciences and Solutions Centre
			Thormoehlensgate 55, 5008 Bergen, NORWAY (47-5)54-4653
From: v078p6g8@ubvmsd.cc.buffalo.edu (Richard M Wasserman)
Newsgroups: comp.sys.intel
Subject: 196/8096 development question.
Date: 26 Aug 92 03:00:00 GMT
Organization: University at Buffalo
News-Software: VAX/VMS VNEWS 1.41


	I was wondering if there were any assemblers/compilers available
in the public domain for the above microcontrollers.  If not any info
on available software for an IBM platform would be greatly appreciated.
I don't often read this group so direct E-Mail would be helpful.  I'll post
a summary of any responses I get.  Thanks in advance.
		Rich Wasserman
Newsgroups: comp.sys.intel
From: denny@view (Denny Page)
Subject: 860: set_elt in locore.o
Organization: Views.
Distribution: comp
Date: Thu, 3 Sep 1992 19:57:47 GMT

Does anyone have usage knowledge of set_elt()?

I am trying to work with a replacement for the asy driver and it is
panicing ("no as allocated") on the first access to low memory.

The only extern function that I am able to find in the asy that looks
like a candidate is set_elt(), but I am quite open to suggestion.

Thanks,
	Denny
Newsgroups: comp.sys.intel
From: lfm@pgroup.com (Larry Meadows)
Subject: Re: Future of i860 line
Date: Wed, 26 Aug 1992 22:25:35 GMT
Organization: The Portland Group, Portland, OR

In article <TMH.92Aug26230950@doppel.first.gmd.de> tmh@doppel.first.gmd.de (Thomas Hoberg) writes:
>In article <BtLGIG.3q2@pgroup.com> I write:
>   Actually, the announcement was that Intel had admitted the failure of
>   the i860 as a general-purpose CPU.  They still intend to support it in
>   graphics and embedded applications; speculation is that they will also
>   support it for the iPSC MPP systems.  No followon has been announced,
>   but one would obviously be needed if they do indeed plan to continue to
>   use i860-like chips in the iPSC.
>
>Why did it fail, though? While there might be better CPUs today, I
>thought it pretty good when it came out. Was there anything seriously
>wrong with it (except that it'd do virtual caching)? Was it just that
>the various vendors were too busy promoting their own designs or
>tuning their old architectures? Is it just bad luck that nobody
>decided to pick it up or is there something about the i860 that I
>missed?

Well, I could probably go on all day, and Intel may shoot me, but...

It is my personal opinion that Intel's failure to properly market and
position the i860 resulted in its lack of mainstream acceptance.  Intel
started out marketing the i860 as the workstation chip, then switched
to the graphics chip, then to the supercomputing chip, even before
vendors such as OKI had shipped any non-beta workstations.

As for why Intel did this, it seems clear that they decided that the
resources spent on the i860 were better spent on the x86 line.  Whether
or not they decide that the i860 is worth a follow on is a separate
decision.

As for the chip itself, it was fine when it came out, and a few minor
architectural enhancements would have made it as good as any existing
RISC chip.  In fact, at equivalent clock rate with a proper memory system
design, I'd happily put the i860-XP as-is up against Alpha, HP, or RS6000,
and it would clearly beat the Sparc.

My opinions only, of course.
-- 
Larry Meadows		The Portland Group
lfm@pgroup.com
Newsgroups: comp.sys.intel