From: pmamtora@uceng.UC.EDU (Padmanabh D. Mamtora )
Newsgroups: misc.jobs.resumes
Subject: MSEE, VLSI Design/VLSI CAD/VLSI Testing/Comp. Design
Keywords: MSEE, VLSI Design/VLSI CAD/VLSI Testing/Comp. Design
Date: 13 Apr 92 15:13:31 GMT
Article-I.D.: uceng.1992Apr13.151331.23677
Organization: College of Engineering, University of Cincinnati

Dear Prospective Employer:

I am a Masters student in the Department of Electrical & Computer
Engineering, at the University of Cincinnati. I plan to graduate by
June 1992. I am interested in the areas of VLSI Design, VLSI CAD and
VLSI Testing, with their applications to Component Design and 
Development.

I have had extensive experience in the areas of VLSI Design, Testing 
and CAD Tools Development. My design experience, coupled with knowledge 
of VLSI CAD Tools and Hardware Description Languages, have enabled me 
to get a firm grasp of the various aspects of High Level Synthesis 
Systems. My thesis topic, involves verification of synthesis using 
simulation, with behavior extraction for timing. I have been exposed to 
elaborate design procedures and group effort in my Floating Point 
Processor Design project. In an individual capacity, I have implemented 
a synthesized model of a Traffic Light Controller, in silicon with 
complete simulation of the behavioral and the layout models, within a 
real fabrication deadline. 

Enclosed is my resume, which lists my work and programming experience
in the various project works.

I will appreciate  the  opportunity to meet with you to discuss my
qualifications and employment prospects with your company. Please feel 
free to contact me by phone or e-mail. I look forward to hearing from
you.

Thank you,

Sincerely,



Paddy Mamtora


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			   PADDY D. MAMTORA


2930 Scioto St # 210			Office: (513) 556--3025
Cincinnati, OH 45219.			email: pmamtora@pumpkin.ece.uc.edu
Home: (513) 556--7404			Fax: (513) 556--7326

OBJECTIVE
---------
Seek entry level position in the areas of VLSI CAD Tools Development, VLSI 
Design and VLSI Testing. 

EDUCATION
---------
M.S. Electrical Engineering			University of Cincinnati
Major: Computer Systems Design		Expected graduation date - June 92
GPA: 3.5/4.0
Master's Thesis : TestBench Compiler
Working on verification of High Level VHDL Synthesis Systems. 
To translate the VHDL behavioral and structural description test patterns  
to low level layout switch-level simulator test files.  

B.E. Electronics Engineering				University of Bombay
GPA: 1st Class (Honors)						June 1988

PROJECTS
--------
 * Designed, generated layout and simulated a Floating Point Processor using 
   Mentor Graphics GDT Tools - inception to final layout.	
 * Implemented a Space-craft Environment Monitoring System in Ada - Software 
   Engineering techniques. 
 * Designed, coded and simulated VHDL and GDT libraries to generate paramete-
   rized components - part of the VHDL Synthesis system, developed at Digital 
   Design Environments Lab. 
 * Tested VHDL Synthesis System of a Doctoral student - Simulated and 
   generated layout of the synthesized model of a Traffic Light Controller,
   using Magic and GDT Tools.
 * Emulated a UNIX File system in C as a hierarchical layered structure and 
   simulated various Disk Scheduling strategies using Simpas, as part of the 
   Operating Systems Design course.
 * Implemented the D algorithm in C for testing circuits with stuck-at faults.
 * Wrote a term-paper on Characterization & Testing of Physical Failures in 
   MOS LSI circuits - part of the Fault Tolerant Computing course.
 * Wrote a term-paper on Analysis of Multiple-bus Interconnection Networks - 
   part of the course on Parallel Processing.
 * Designed and generated artwork for a Microprocessor-based Universal
   Slave System - speech synthesis applications.
 * Developed an English Text-to-Speech Translator I/O Card for the IBM PC - 
   phoneme-based translation software implemented in Pascal.

COURSES
-------
VLSI System Design, VLSI Design Lab, MOS/LSI Integrated Circuits, Software 
Engineering, Operating Systems Design, Introduction to Computer Architecture,
Introduction to Parallel Processing, Fault Tolerant Computing, 
Switching and Automata Theory.

SKILLS
------
VLSI CAD Tools: GDT (Mentor Graphics), Magic (UC Berkeley), SPICE, IRSIM, 
		Esim, Crystal, Meg, Peg, Expresso.
Languages: C, VHDL, C++,  Unix Shell, LEX, YACC, Pascal, ADA, ISPS, Simpas, 
	   Fortran, Basic, Assembly (8085,8086). 
Operating Systems: Unix, MS-DOS, VMS, IBM-AIX.
Packages:} 
	- Document preparation systems:- PTF and LaTeX.  
	- Word Processing systems:- Wordstar, Word Perfect, MacWrite.
	- Graphic Packages:- IDraw, XFig, MacDraw.
Computers: Sun Sparcstations (Unix), VAX-11/750(Ultrix), HP-840(Unix)
VAX-11/785(VMS), Macintosh SE, IBM PC.

REPORTS
-------
 * "VSS: VHDL Synthesis System - Its Organization and Structure", TM-ECE-
   DDE-91-15, June 1991.
 * "Register Level Component Generators", TM-ECE-DDE-91-13, June 1991.
 * "Benchmarks for High Level Synthesis", TM-ECE-DDE-91-11, June 1991.

EXPERIENCE
----------
Teaching Assistant		     University of Cincinnati, Cincinnati.
Sept 90 - Dec 90
 * Graded papers and quizzes for a course on Fortran in Mechanical 
   Engineering Department.
Computer Consultant                       UC Computing Center, Cincinnati.
Sept 90 - Dec 90
 * Assisted Engineering students to use the IBM-RT machines.
Research Assistant		        Watumull Institute, Bombay, India.
June 88 - May 89
 * Interacted with Graduate students in their research projects.
Teaching Staff			      Wondersoft Computers, Bombay, India.
June 88 - May 89
 *  Taught introductory course on Pascal for Software Education.

AWARDS
------
 * Merit scholarship throughout the undergraduate program.
 * University Graduate Scholarship (1989-92).
 * University Teaching Assistantship (1990).

REFERENCES
----------
Excellent references will be furnished upon request.


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-- 
Padmanabh Mamtora 'Paddy'
Elx : pmamtora@pumpkin.ece.uc.edu
Voice : (513) 556-8433 (H)
	(513) 556-3025 (O)