From: mshute@cs.man.ac.uk (Malcolm Shute)
Newsgroups: bionet.info-theory
Subject: Re: The Dualism in info theory
Date: 12 Oct 92 11:42:52 GMT
Organization: Dept Computer Science, University of Manchester, U.K.

In article <1992Oct11.072935.9685@ncsu.edu> samodena@csemail.cropsci.ncsu.edu (S. A. Modena) writes:
>In article <1992Oct10.171852.27566@wixer.cactus.org> sparky@wixer.cactus.org (Timothy Sheridan) writes:
>>I hope i can get this right..
>Well, I can't be sure exactly what you're up to: maybe you have a special
>way of looking at things.....

>>There several reasons for why this seems important. since a computer program
>>that performs a mapping always requires a a 'computer to run it the question
>>arises-"how much of the complexity of the mapping is hidden in the physical
>>structure of the computer?". And, can we minimize the functional part of
>>the systen so as to perhaps equate the form with the process..?
Maybe I'm wrong... but what I understand Timothy to be asking, is not unrelated
to a question which Tom put up some time ago... and which I tried to latch
onto without any success.

Take the program, P1, to perform quick-sort on N numbers,
written for assembler language, or rather instruction-set, S1.
It consists of M1 bits of op-codes+data.

Take the program, P2, to perform quick-sort on N numbers,
written for assembler language, or rather instruction-set, S2.
It consists of M2 bits of op-codes+data.

Obviously P1 and P2 contain the same amount of information (obviously?),
since they are in fact one and the same program.
So why is there a difference between M1 and M2?
Some of it (not all of it) is due to the different powers of expression
of the two programming languages, S1 and S2.

If S1 and S2 happen to both be 'perfect' instruction sets (i.e. no
wasted op-codes, non-orthogonal instructions, etc), then maybe
we could conclude that M1+E(S1) = M2+E(S2) [where E(S1) is the entropy
tied up in the instruction set... how much complexity there is tied
up in the knowledge that 0001000000000000 is the MOV instruction,
and 0110000000000000 is the ADD instruction, etc).

This, to me, seems very much like Tom's question, how much information do you
need to deliver a letter, or to wander down to stores?  How much information
needs to be on the envelope, and how much is 'encoded' by the maze (by the
road network, or the corridor layout).

I've tried a couple of times to provoke response, with a picture of an H-tree
layout, and asked how much information is contained in the layout itself.
No one has ever responded, either positively, or negatively.  Was I really
way off course, and into the realms of irrelevence with my suggestion?
You can tell me... I can take it :-)


>[...] I posted that notice about the VLSI seminar, which I hope
>to attend, for it's very Shannonesque flavor.  Reread it (you'll
>have to fixup your .newsrc file).  The problem stated that VLSI
>design methods have become inefficient at high transistor density
>because, until now, only the STATIC parameters of the logic gates
>have been considered in the silicon compilers.  Now however, submicron,
>high density VSLI has become DOMINATED by the COMMUNICATION processes
>BETWEEN the gates.  He is saying that the switching transient
>characteristics used to be a problem, but now gates can be manufactured
>that can run at very high clocks indeed.  It is the interconnections
>that are important....the dynamics of signal propagation, signal 
>degradation, and, of course, the effect of NOISE.  

It looks jolly interesting stuff.  I wish I could have gone.

Could I ask you, and whoever else attends this event, a favour?
Could you post a summary of any interesting bits from this seminar to this
group, and argue them out in front of the rest of us?

Thanks in advance, if you can do this.
--

Malcolm SHUTE.         (The AM Mollusc:   v_@_ )        Disclaimer: all