Newsgroups: misc.jobs.resumes
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From: iyengar%ppl.utah.edu@cs.utah.edu (Satish Iyengar)
Organization: Odyssey Ultraware, Inc
Date: Thu, 31 Dec 1992 04:03:51 CDT
Subject: M.S.E.E. looking for a position in VLSI Design/CAD Development

Dear Prospective Employer:

I am a graduate student at the  University  of  Utah,  Salt  Lake
City.   I  will be graduating with a Masters degree in Electrical
Engineering later this month.  My area of specialization has been
VLSI Design and I would like to pursue a career in that field.

Included below is a copy of my resume for your reference.  I have
taken a number of courses that augment my skills and knowledge in
the field of VLSI Design/CAD.   During  my  course  work  I  have
designed  a  variety  of chips prominent among which are an 8-bit
RISC chip, a Pipeline Cache Memory chip,  a  Self-Timed  Pipeline
Adder chip, an Asynchronous FIR Filter chip, a Traffic Controller
chip and a Data Queue chip.  My thesis research, titled "FIRAIDE:
A  Computer Aided Design Tool for the Automatic Layout Generation
of High-Performance FIR Filters", involves extensive  programming
in  C++  in the UNIX environment.  This tool runs under X-Windows
on a Sun platform.  The front end of this  tool  is  a  graphical
user interface developed using InterViews, a GUI package built on
top of X-Windows.

I am looking for a growth oriented position  as  an  Entry  Level
Design/CAD  Engineer  with  a  leading  edge firm in the field of
VLSI.  I am a highly motivated individual and  am  compentent  to
embark  on  a  project all by myself and traverse from conceptual
design through final design within the given time constraints.  I
possess  strong  written  and  oral communication skills and am a
motivated team player.

If you think that I meet your requirements feel free to  call  me
at  any  of the phone numbers listed below.  I am looking forward
to working with you.

Sincerely,

Satish S. Iyengar.

******************************  M Y   R E S U M E 
*******************************
__________________________________________________________________________________

                          SATISH S. IYENGAR

Dept of Electrical Engg                       Home  : (801) 581-1424
University of Utah			      Work  : (801) 581-5618
						      (801) 585-3676
Residential Address:			      Address in the Bay Area:
1159 East 400 South			      1901 Hartford Avenue, #166
Salt Lake City, UT 84102.		      Santa Clara, CA 95051.
					      Phone : (408) 983-1334
__________________________________________________________________________________

OBJECTIVE :
Seeking a challenging position as a VLSI Design/CAD Engineer with a leading
edge firm.

EDUCATION :
Master of Science in Electrical Engineering
Specialization : Computer Engineering
University of Utah, Salt Lake City, UT 84112.
Thesis Research:  FIRAIDE: A Computer Aided Design Tool for the automatic
		  layout generation of high-performance of FIR Filters.
Graduation Date : December, 1992.

Bachelor of Engineering
Major : Electronics and Communication Engineering
Osmania University, Hyderabad, India.
Senior Thesis:  A Study of Global Positioning Systems and Performance
simulation
		of the alpha-beta tracker.
G.P.A. : 3.8/4.0	Graduation Date : April, 1989.


COURSEWORK :
		*Logic and Switching Theory	  *Computer Architecture
		*Parallel Computer Architecture   *Microprocessor Theory and
		*IC Applications		   Applications
		*Modelling of Integrated Circuits *Introduction to Integrated
		*Asynchronous IC Design		   Circuit Design
		*Structural Design of LSI Circuits
		*Digital Signal Processing	  *Adaptive Signal Processing

COMPUTERS :
Languages :	C, C++, Pascal, FORTRAN, Intel 8085/8086 Assembly

Packages  :	X Windows, SunView, Matlab, 
		VTI Tools, VLSISPICE, HSPICE, PPL, MAGIC,
		VIEWLOGIC, InterViews.

Systems   :	Sun(Sun OS), HP350(BSD UNIX 4.3), IBM PCs(MS DOS),
		Macintoshes(Mac OS).


PROFESSIONAL EXPERIENCE :
Research Assistant : (6/01/90 - Present)
Center for Excellence in VLSI Design, State of Utah.
University of Utah, Salt Lake City, UT 84112.
Responsibilities : Development of a Computer Aided Design Tool for the
automatic
		   layout generation of High-Performance FIR Filters in VLSI.
	   	   This design tool has been written entirely in C++ in the UNIX
		   and X-Window programming environment.  The front-end of this
		   tool is a Graphical User Interface developed using InterViews,
		   a window based system developed on top of X-Windows.

Software Engineer : (4/89 - 8/89)
CMC Ltd., Secunderabad, India.
Responsibilities  : Development of a Relational Database Management System for
		    in-house inventory control and personnel records.

PROJECTS :

Pipeline Cache Memory Design :   Developed a Pipeline Cache Memory System using
			         Associative Mapping Techniques.

Computer Design :                Designed a RISC based computer along with its
				 instruction set.

Finite Impulse Response Filter : Developed an Asynchronous Finite Impulse Response
				 Filter using Viewlogic.

Traffic Controller Chip:         Developed a Traffic Controller Chip which
				 regulates the traffic at the intersection of a
				 highway and a narrow lane using a sensor to 
	        		 detect flow of traffic on the narrow lane.

Pipeline Asynchronous Adder :    Designed a Self-Timed Pipeline Adder 8-bits
in
				 length with dual-rail bundled data and 4 phase
				 clocking technique.

Data Queue Chip :		 Designed a Data Queue chip which coordinates and
				 assigns priority as to which of two data buses
				 can write into a register file.

ACTIVITIES:

Basketball, Reading, Sports, Music.


References can be furnished on request.


WILLING TO
RELOCATE.

__________________________________________________________________________________

**********************************************************************************
-- 
Satish S. Iyengar                             Phone:(Home) (801) 581-1424
Dept. of Electrical Engg.                           (Work) (801) 581-5618
University of Utah,                                        (801) 585-3676
Salt Lake City, UT 84112.                            



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