Newsgroups: alt.folklore.computers
Subject: Re: ASSEMBLY LANGUAGE IBM
From: ljw@nacjack.gen.nz (lawrence wilkinson)
Date: 24 Nov 92 7:29:42 GMT
Distribution: world
Organization: Malleus Maleficarum - Nil Mortifi Since Lucre


ALAN@VM1.McGill.CA (Alan Greenberg) writes:
 
> On the model 360/30, they used things that looked like punch cards,
> and were in fact programmed on card-punches.  I don't remember the
> exact technology, but the cards were complex sandwiches and perhaps
> punching a whole actually severed a connection inside.
 
The following may also be a bit hazy:
 
That technique was known as CCROS for card-capacitor-ROS.  The cards
were fairly simple - a plastic card with a conductive ink printed on it,
a small pad at each chad and a shorting bar between rows.  The microcode
was about 56 bits wide; I think the remaining columns were used to
identify the card's position in the unit (some columns were also taken
up by the row drive contacts).
 
The cards were fitted into racks against PCBs which had traces running
down the rows.  At a guess, the /30 had about 40 cards wide by 6 cards
high by 10 words per card ~ 2400 words to do the basic and decimal
instruction sets, as well as the multiplexor channel and console device
- actually I think it was closer to 4k. For scientific instructions or
1401 emulation an additional CCROS unit was added.  Each unit would be
400Wx600Hx300D or so.
 
To hold the cards against the PCBs, there were thin card-sized air bags
which were inflated by a not-so-small compressor at the rear of the
unit.  This starts up occasionally, readily heard above the din of
cooling fans and 2311 drives.  I'm sure there was a thin plastic sheet
which prevented the cards from actually shorting the PCBs, card reading
was performed by driving a card row and picking up the pulses coupled
into the column sense lines by the un-punched pads.
 
CPU cycle time was 1.5us, I'm not too sure what the CCROS access time
was.  Each microcode word specified the next microcode address, with the
two LS bits determined by condition codes.  For this reason, I'm sure
the CCROS read 4 words in parallel and selected the appropriate one late
in the cycle, so the access time was probably 1us or so.  There was a
special 'address mode' for instruction decode.  This prefetch technique
impressed me enough (compared with the prevailing AMD bit slices!) that
I used it in a UCSD p-machine design c. 1983 - I should try and finish
it someday.
 
Cards could be produced or duplicated in a conventional punch.  Some of
my cards are paper rather than plastic, I assume these are changes. When
I first fired it up after a long shutdown (10 years?) many microcode
words generated parity errors, necessitating careful repairs with a
bottle of conductive ink.  There were nice diagnostics to cycle through
all microcode addresses etc. and multiple parity bits per word. By
pulling off the air line I could remove/replace a card with the whole
system running - who needs a WCS?  I think there are still a few flaky
bits - the multiplexor channel would fall over every hour or so with
some untraceable check.
 
The 2841 DASD controller and the 2314 used TROS, which is not as
amenable to quick changes.  I'm sure it's faster, say 750ns cycle.
 
Lawrence Wilkinson

============== ljw@nacjack.gen.nz ============== CI$ 72070,3440 ==============
There's nothing so simple that works so well that it can't    --o--      F-Atl
be made to work better by making it more complicated.       []=(_)=[]   TTAGGG