From: jain@cs.utah.edu (Prabhat Jain)
Subject: MS, MPhil CS; VLSI Verification/Simulation/Synthesis/Architecture
Date: 13 Aug 92 22:32:47 MDT
Followup-To: jain@cs.utah.edu
Originator: jain@cs.utah.edu
Keywords: MS, Aug 92; MPhil=(PhD requirements except dissertation)+more courses
Organization: University of Utah CS Dept
Distribution: usa


Dear Prospective Employer:

I am a graduate student in the Department of Computer Science at the
University of Utah, Salt Lake City, and I will complete my MS degree
in the end of August 1992. I have finished all the requirements for PhD
except the part of the dissertation research work; I intend to complete
my PhD some time in the future.

For my MS thesis, I am working on ``A Symbolic Simulation-based
Verification System for Synchronous Circuits.'' This verification
system takes the transition assertions derived from the high-level
specification of the design, generates the vectors for symbolic
simulation using the parametric form of Boolean expressions, and
verifies the design using the switch-level COSMOS symbolic simulator.
This verification technique will be integrated with the high-level
synthesis and verification tools.

I have done extensive course-work and I have good theory and programming
background. I also have experience in the design of large synchronous and
asynchronous circuits. Recently, I designed a self-timed Execution Unit
for the NSR(Non-Synchronous RISC) Processor using the VIEWlogic tools and
Actel macros. The NSR Processor is implemented in Actel FPGA and is fully
operational.

I am enclosing a copy of my resume for your perusal. I hope that you will
find my background matching with a suitable position in your organization.

Hoping to hear from you,

Sincerely,

Prabhat Jain
jain@cs.utah.edu


*********************  R  E  S  U  M  E  ***********************************

			 PRABHAT JAIN

		#4560 MEB, Dept. of Computer Science,
		University of Utah, Salt Lake City,
		UT 84112   e-mail: jain@cs.utah.edu
		Office: (801)-581-8354 Home: (801)-355-4802
	
OBJECTIVE

A position for the research and development of VLSI Systems and Architectures.
The areas I have worked on are: Hardware Simulation and Verification,
Application Specific Architectures, Computer Architecture, Automated
Synthesis of VLSI, and CAD tools for VLSI design.

EDUCATION

** M.S. (Computer Science), August 1992, Computer Science Dept.,
   University of Utah, Salt Lake City; completed Ph.D. requirements except
   part of the dissertation research work.
   GPA : 4.0/4.0
** M.Phil. (Computer Science), finished requirements[^], Computer Science
   Dept., University of Utah, Salt Lake City.
   GPA : 4.0/4.0
** M.Tech. (Computer Science), Indian Institute of Technology, Kharagpur,
   India, January 1988.
** B.E. (Computer Science and Engineering), Devi Ahilya University, Indore,
   India, June 1986.
** Industrial Management Course (Diploma), Devi Ahilya University, Indore,
   India, June 1986.

[^]M.Phil. requires 81 course credit hours and Ph.D. preliminary and advanced
   comprehensive examinations.

RESEARCH PROJECTS

** Symbolic Simulation-based Verification of Synchronous Circuits
   (M.S. thesis work).
** Self-timed Execution Unit for NSR(Non-Synchronous RISC) Processor
   (VLSI Architecture; implemented in Actel FPGA).
** Some Recent Asynchronous Circuit Design Methodologies (A survey report).
** hgrep: A Hardware Regular Expression Processor (Synchronous IC Design).
** VLSI Simulation using Object-oriented Approach (M.Tech. thesis).
** Design and Implementation of Intel 8051 Micro-computer Trainer
   (B.E. thesis).

EXPERIENCE

** Research Assistant (June 1990 - Present), Computer Science Dept.,
   University of Utah, Salt Lake City. Research areas worked on:
   Application Specific Architectures, Automated Synthesis of VLSI,
   Hardware Simulation and Verification, Asynchronous System Design,
   and CAD tools for VLSI design.
** Teaching Assistant (Sept 1988 - May 1990), Computer Science Dept.,
   University of Utah, Salt Lake City.
   Courses assisted: Structured Design of ICs, Hardware Laboratory,
   Advanced Computer Organization, Software Engineering, Formal Languages,
   Algorithms and Data Structures, Programming Language Structure,
   and Fortran 77.
** Lecturer (March 1988 - Sept 1988)}, Dept. of Computer Science
   and Engineering, S.G.S. Institute of Tech. and Science, Indore, India.
   Courses taught: Computer Networks, Discrete Structures,
   and Theory of Computation.

LANGUAGES AND PROGRAMMING ENVIRONMENTS

** Viewlogic tools, Actel FPGA, COSMOS, SPICE, MAGIC, and 
   PPL(Path Programmable Logic) tools for semi-custom designs;
   Net and Verilog.
** C, C++, Common Lisp, Prolog, Pascal, Fortran 77, SML, and COBOL.
** MIPS R2000, MC68000, Intel 8085, Z80; UNIX, MS-Dos, and X-Windows.

SELECTED LIST OF COMPUTER PROJECTS

** Self-time Execution Unit of the NSR(Non-Synchronous RISC) Processor
   (VLSI Architecture; implemented in Actel FPGA).
** High-level Synthesis of the Self-timed Execution Unit of the NSR(Non-
   Synchronous RISC) Processor from Functional Specifications
   (High Level Synthesis; target circuit was Actel FPGA).
** Custom Layout and Simulation of A Testable Asynchronous Counter
   (Modeling of ICs).
** hgrep: A Hardware Regular Expression Processor (Synchronous IC Design).
** Ethernet Simulation using C++ Process Package (Discrete Event Simulation).
** Implementation and Comparison of Garbage Collection Methods in LISP
   (LISP and AI Programming).
** Implementation of A PL/0 Compiler (Compiler Design).
** Query Interpreter for A Library Database System using
   QBE(Query By Example) Approach.
** Cross Macro Assembler for Intel 8085 on a UNIX machine
   with facility to download the code to a microprocessor kit.
** Preprocessor to convert Fortran 77 programs to Fortran IV programs.

HONORS AND AWARDS

** The University of Utah Graduate Research Fellowship
   (Sept 1991 - May 1992).
** Graduate Scholarship for M.Tech. Program (Sept 1986 - Jan 1988).
** Nominated member of the Board of Studies of Computer Engineering,
   Devi Ahilya University, Indore, India (1986 - 1987).
** Awarded Gold medal for securing first rank in the faculty of
   Engineering, Devi Ahilya University, for B.E. degree (1986).
** National Merit Scholarship for B.E. degree program (1981 - 1986).

ACTIVITIES

** Student member of the Association of Computing Machinery (1988 - ).
** Nominated member of the Board of Studies of Computer Engineering,
   Devi Ahilya University, Indore, India (1986 - 1987).
** Member of the Board of Directors of Co-operative society,
   S.G.S. Institute of Tech. and Science, Indore, India (1983 - 1986).

REFERENCES

Available upon request.
---------------------------------------------------------------------------

PUBLICATIONS

Prabhat Jain and Ganesh Gopalakrishnan.
``Some Techniques for Efficient Symbolic Simulation-based Verification''.
To appear in the International Conference on Computer Design, Boston,
Oct 11-14, 1992.

Prabhat Jain, Prabhakar Kudva, and Ganesh Gopalakrishnan.
``Towards A Verification Technique for Large Synchronous Circuits''.
In the Fourth Workshop on Computer-Aided Verification, Montreal,
Quebec, Canada, June 29 - July 1, 1992.

Prabhat Jain and Ganesh Gopalakrishnan.
``Efficient Symbolic Simulation-based Verification Using the
  Parametric form of Boolean Expressions''.
Technical Report, Department of Computer Science, 
University of Utah, No. UU-CS-TR-91-0023 (Submitted to IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems).

Prabhat Jain, Ganesh Gopalakrishnan, and Prabhakar Kudva.
``Verification of Regular Arrays by Symbolic Simulation''.
Technical Report, Department of Computer Science, 
University of Utah, No. UU-CS-TR-91-0022.
(Submitted to the Sixth International Conference on VLSI Design, Bombay,
 India, January 3-6, 1993).

Ganesh Gopalakrishnan and Prabhat Jain.
``Some Recent Asynchronous Circuit Design Methodologies''.
Technical Report, Department of Computer Science, 
University of Utah, No. UU-CS-TR-90-0016
(Submitted to ACM Computing Surveys). 

Ganesh Gopalakrishnan, Prabhat Jain, et. al.
``Combining Verification and Simulation''.
In Advanced Research in VLSI, International Conference,
Santacruz, March 1991.

Ganesh Gopalakrishnan and Prabhat Jain.
``A Practical Approach to Synchronous Hardware Verification''.
In 4th CSI/IEEE International Symposium on VLSI Design, New Delhi,
India, January 1991. 

*****************************************************************************

thanks,
Prabhat Jain