From: takao@tsl.cl.nec.co.jp (Takao Nishitani)
Subject: VLSI Signal Processing
Date: Thu, 27 Aug 1992 04:21:34 GMT
Distribution: fj
Organization: Terminal Systems Res. Lab., C&C Systems Res. Labs., NEC, Kawasaki, JP

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1992 IEEE Workshop on VLSI Signal Processing Program

The Inn at Napa Valley, Napa, California
October 28-30, 1992
Sponsored by
The IEEE ASSP Society's Technical Committee on VLSI

Supported by the National Science Foundation and
Hughes Aircraft Company

GENERAL CHAIR        TECHNICAL PROGRAM CHAIR
Kung Yao             Wojtek Przytula

GENERAL CO-CHAIR     TECHNICAL PROGRAM CO-CHAIR
Rajeev Jain          Jan Rabaey

PROGRAM COMMITTEE

Jonathon Allen      Konstant Konstantinides     Robert Owen
Magdy Bayoumi       Jit Kumar                   Robert Owens
Robert Broderson    Sun-Yuan Kung               Keshab  K. Parhi
Peter Cappello      K.J. Ray Liu                Viktor Prasanna
Francky Catthoor    Edward Lee                  John G. Proakis
Paul Chau           Richard F. Lyon             G. Robert Redinbo
Ed Deprettere       Miroslaw Malek              Henry Samueli
Jon Eldon           John McWhirter              David A. Schwartz
Wanda Gass          Teresa H.Y. Meng            Bing Sheu
Manfred Glesner     Howard Moscowitz            Gerald Sobelman
Yu Hen Hu           J. Greg Nash                Earl E. Swartzlander, Jr.
Jeng N. Hwang       Yrjo Neuvo                  Takao Yamazaki
Leah H. Jamieson    Takao Nishitani

The 1992 Workshop on VLSI Signal Processing is structured for formal
presentations and informal interactions in new theoretical and applied VLSI
signal processing areas of: integrated circuit technology, digital signal
processing theory, CAD, design methodologies, and applications.  The program
includes a keynote address, invited speakers, contributed papers, and a panel
discussion.

TUESDAY, OCTOBER 27

8:00 pm to 10:00 pm Registration

WEDNESDAY, OCTOBER 28

8:00 am to 8:45 am Registration

8:45 am to 9:00 am Introductory Comments

9:00 am to 9:45 am Keynote Address

"Low Power Signal Processing Systems," Robert Brodersen, University of
California, USA

9:45 am to 10:00 am Coffee Break

10:00 am to 12:00 am Session 1 - Architectures and Circuits 1
Chair:  Earl Swartzlander, University of Texas,USA

"An Approach for Power Minimization Using Transformations," Anantha P.
Chandrakasan, Miodrag Potkonjak, Jan Rabaey, and Robert Brodersen,
University of California at Berkeley, USA

"Ultra-Low Power Digital CMOS Circuits," Menahem Lowy and Jerome J.
Tiemann, General Electric Company, USA

"A Design Strategy for High-Throughput Applications," J. Van Meerbergen,
P. Lippens, B. McSweeny, W. Verhaegh, A. van der Werf, Philips Research
Labs, THE NETHERLANDS

"VLSI Implementation of Real-Time Parallel DCT/DST Lattice Structures for
Video Communications," C. T. Chiu, R. K. Kolagotla, K.J.R. Liu, and J.JF.JJaJa,
University of Maryland, USA

"Self-Test for F.I.R. Filters," C. Counil, M. Renovell, and G. Cambon,
Universite de Montpelier II:  Sciences et Techniques du Languedoc, FRANCE



12:00 am to 1:30 pm Lunch

1:30 pm to 3:30 pm Session 2 - Applications
Chair: Keshab Parhi, University of Minnesota, USA

"An Architecture for Lossy Signal Compression," Konstantinos
Konstantinides and Balas K. Natarajan, Hewlett-Packard Laboratories, USA

"VLSI Architectures and Implementation of Predictive Tree-Searched Vector
Quantizers for Real-Time Video Compression," Shu-Sun Yu,
RaviJK.JKolagotla, and Joseph F. JaJa, University of Maryland, USA

XCLONER:  An Interactive Multi-Platform Parallel Imaige Processing
Development Environment," Chao-Chun Wang and Leah H. Jamieson, Purdue
University, USA

"VLSI Opto-Electronic Array Processor for Morphological Image
Processing," Wai-Chi Fang, Tim Shaw, and Juffery Yu, California Institute of
Technology, USA

"Architectures for Integration of Real-Time Image Processing Systems," M.
Robert, M. Paindavoine, and P. Gorria, Universite Montpellier II, Sciences
Institut des Sciences de '.Ingenieur, FRANCE


3:30 pm to 3:45 pm Coffee Break

3:45 pm to 4:45 pm Session 3 - Short Presentations 1
Chair: Konstant Konstantinides, Hewlett Packard, USA

"A SIMD DSP for Real-Time MPEG Video Encoding/Decoding," Ichiro
Tamitani, Akio Yoshida, Yasushi Ooi, and Takao Nishitani, C&C Systems
Research Laboratories, NEC Corporation, JAPAN

"A Concurrent Lossless Coder for Video Compression," Keshab K. Parhi
and Gireesh Shrimali, University of Minnesota, Minneapolis, USA

"High-Speed VLSI Pipelined Processor Design for Lossless Image Data
Compression," Wai-Chi Fang and Bing J. Sheu, California Institute of
Technology, USA

"A Ring-Structured Topology of Programmable Digital Filter Processors on
a Single Chip," Alan Kwentus, Michael Werter, and Alan N. Willson, Jr.,
University of California, Los Angeles, USA

"Scaling and Folding the Viterbi Algorithm Trellis," Paul M. Chau, University
of California, San Diego, USA

"A Tri-Array for the Real-Time Computation of Higher Order Moments
Estimates," Haris M. Stellakis and Elias S. Manolakos, Northeastern University,
USA

"VLSI Performance/Precision Tradeoffs of Approximate Rank-Order Filters,"
J. David Narkiewicz and Wayne P. Burleson, University of Massachusetts, USA

"A New Algorithm for Order Statistic and Sorting," Barun K. Kar, and Dhiraj
K. Pradhan, University of Massachusetts, USA

"High Sample Rate Architectures for Median Filters," Chaitali Chakrabarti,
Arizona State University, USA

"Improved Bit-Level Systolic Two-Port Wave Filter Adaptor," S.S. Scarlatos,
Princeton University, USA

"An Algorithmic Approach to Concurrent Error Detection in Artificial Neural
Networks," Vincenzo Piuri, Department of Electronics, Politecnico di Milano,
ITALY


4:45 pm to 6 pm - Poster Session 1

6:00 pm to 7:00 pm - Reception

8:00 pm to 10 pm - Panel Session

Panel Leader - Henry Samueli, University of California, USA
"Handheld Multimedia Terminals -- An Achievable Goal This Century?"


THURSDAY, OCTOBER 29


8:30 am to 9:15 am Invited Talk
"Applications of Multimedia," Shane Robison, Apple Computer, USA

9:15 am to 10:05 am Session 4 - Multimedia
Chair: Bing Sheu, University of Southern California, USA

"Computer Graphics -- As Seen on TV," John A. Eldon, TRW LSI Products,
Inc., USA

"Design and Implementation of a Linear-Phase Equalizer in Digital Audio
Signal Processing," C.H. Slump, C.G.M. van Asma, J.K.P. Barels, W.J.A.
Brunink, F.B. Drenth, J.V. Pol, D. Schouten, M.M. Samson, and O.E. Herrmann,
University of Twente, THE NETHERLANDS



10:05 am to 10:20 am Coffee Break

10:20 am to 12:00 am Session 5 - Architectures and Circuits 2
Chair: Paul Chau, University of California

"A Reconfigurable Data-driven Multiprocessor Architecture for Rapid
Prototyping of High Performance DSP Algorithms," A. Yeung, and J. Rabaey,
University of California, Berkeley, USA

"An Efficient Systolic Architecture for QMF Filter Bank Trees," Mohan
Vishwanath, Robert Owens, and Mary Jane Irwin, The Pennsylvania State
University, USA

"VLSI Implementation of the Real-Time Image Processing Parallel
Architecture GFLOPS," Dominique Houzet, and Jean-Luc Basille, IRIT, FRANCE

"An Adaptive High-Speed Vector Quantization," Oscal T.-C. Chen, Zhen
Zhang, and Bing J. Sheu, University of Southern California, USA


12:00 am to 1:30 pm Lunch

1:30 pm to 3:30 pm Session 6 - CAD
Chair: Wanda Gass, Texas Instruments, USA

"SISim:  A System-Level Interactive Simulator for Array Processor System,"
Wei-Hsin Chou and Sun-Yuan Kung, Princeton University, USA

"Automating High Level Control Flow Transformations for DSP Memory
Management," Michael F.X.B. van Swaaifj Frank H.M. Franssen, Francky V.M.
Catthoor, and Hugo J. De Man, IMEC, BELGIUM

"The Exploitation of Global Operations in Affine Space-Time Mapping," Jan
Rosseel, Francky Catthoor, and Hugo De Man, IMEC, BELGIUM

"Cellular Broadcast in Regular Processor Arrays," Delft University of
Technology, THE NETHERLANDS

"Algebraic Recurrence Transformations for Massive Parallelism," Gerhard
Fettweis, and Lothar Thiele, Teknekron Communications Systems, Inc., USA



3:30 pm to 3:45 pm  Coffee Break

3:45 pm to 4:45 pm - Session 7 - Short Presentations 2
Chair: Peter Cappello, University of California, USA

"Orthogonal Faddeev:  from Algorithm to VLSI Parallel Implementation,"
Guido R. den Heijer, Remco de Zwart, Mark Bloemendaal and Ed. F. Deprettere,
Delft University of Technology, THE NETHERLANDS

"Optimal Scheduling Scheme for Systolic Array Partitioning Problem," Yin-
Tsung Hwang and Yu Hen Hu, University of Wisconsin, Madison, USA

"Clustering Approach for Mapping Recursive DSP Algorithms to
Multiprocessor with Fixed Interprocessor Communication Delays," Yu Hen Hu
and Duen-Jeng Wang, University of Wisconsin-Madison, USA

"Piecewise Linear Schedules for Recurrence Equations:  Extended
Summary," Lap Mui, Sanjay Rajopadhye, and Sayfe Kiaei, Oregon State
University, USA

"A Design Methodology for the High-Level Synthesis of Fault-Tolerant
ASICs," Alex, Oraloglu, Ramesh Karri, University of California, San Diego, USA

"Design Techniques for ASIC Oversampling A/D Converters," Monte F. Mar
and Robert W. Brodersen, University of California, Berkeley, USA

"Systolic Implementation of the Regularized Parameter Estimator," J.
Kadlec, F.M.F. Gaston, and G.W. Irwin, The Queen's University of Belfast,
NORTHERN IRELAND

"A Systematic Folding Design Procedure for a 1-D RLS Systolic Array,"
Flavio Lorenzelli and Kung Yao, University of California, Los Angeles, USA

"A High Performance Algorithm, Architecture and ASIC for Multiplication,
Division and Square Root," S.E. McQuillan, J.V. McCanny, R.F. Woods, and J.
Dowling, The Institute of Advanced Microelectronics, The Queen's University of
Belfast, NORTHERN IRELAND

"Column Compression Multipliers for Signal Processing Applications,"
Zhongde Wang, G.A. Jullien, and W.C. Miller, VLSI Research Group, University
of Windsor, CANADA

"A Chip-Set for the Generalized Hough Transform," M. Albanesi, A. Antola,
M. Ferretti, and R. Negrini, Dip. Informatica e Sistemistica, Univ. PAVIA, ITALY

"VLSI Systolic Array Implementation of a Staged Decoder from BCM
Signals," G. Caire, J. Ventura-Traveset, J. Murphy, and S.Y. Kung, Princeton
University, USA



4:45 pm to 6:00 pm Poster Session 2

6:00 pm to 8:00 pm  Visit to the Winery


FRIDAY,  OCTOBER 30


8:30 am to 9:15 am Invited Talk
"Fast Arithmetic for Recursive Computations," Milos Ercegovac, University of
California, Los Angeles, USA

9:15 am to 10:05 am Session 8 - Arithmetic
Chair: John Eldon, TRW, USA

"Optimizing Arithmetic Elements for Signal Processing," Thomas  K.
Callaway and Earl E. Swartzlander, Jr., The University of Texas at Austin, USA

"Conventional and On-Line Arithmetic Designs for High-Speed Recursive
Digital Filters," John S. Fernando and Milos D. Ercegovac, University of
California, Los Angeles, USA


10:05 am to 10:20 am Coffee Break

10:20 am to 12:00 am Session 9 - Algorithms
Chair: David Schwartz, Hughes Aircraft, USA

"Fast Convergent Jacobi Algorithms using High Dimensional Rotations for
VLSI Signal Processing," John Angell and Kung Yao, University of California,
Los Angeles, USA

"A VLSI Algorithm for SVD Tracking," Eric M. Dowling, Larry P. Ammann,
and Ronald D. DeGroat, The University of Texas at Dallas, Texas, USA

"Real-time, Least-Squares Adaptive Acoustic Beamforming:  A Design
Study," I. K. Proudler, DRA Electronics Division, RSRE, UNITED KINGDOM

"QRD-Based Square Root Free Algorithms and Architectures," Ray Liu and
E. Frantzeskakis, University of Maryland, USA



WORKSHOP LOCATION

The 1992 IEEE Workshop on VLSI Signal Processing locale is situated in the
heart of the Napa Valley (Valley of the Moon), one of Northern Califonia's
most spectacular natural highlights.

Touched with bay fog at the valley's southern tip which borders the San Pablo
Bay and continuing 30 miles north to the base of Mt. St. Helena, the valley
ranges from one to five miles wide and is protected by oak tree clad, low
mountains on the east and west.

Both hills and valley floor are dotted with acre after acre of world renowned
vineyards, chateau-like wineries and homes of local stone built before the
turn of the century.

An hour's drive from the bustling metropolitan Bay Area, Napa Valley provides
a unique country setting conducive to retreats and outdoor activities.

TRANSPORTATION

Shuttle from Airports

The Bay Area is served by two international airports;  Oakland and San
Francisco (approximately 60 and 75 miles from the Napa conference site,
respectively).  Efficient, reliable, daily shuttle services link the town of
Napa to these transportation centers.

Shuttle fares (subject to change) are currently \$15.00 per person per
direction.  All shuttles  require reservations.

From/To San Francisco International Airport
Evans Airport Service, Inc. (Napa, CA)
(707)255-1559, (707)944-2025 or (707)643-8432.

From/To Oakland International Airport
Grapevine Airport Service, (Napa, CA)
(707)253-9093

Rent a Car
You may rent a car at either airport for this convenient and pleasant one hour
drive.  Maps and directions available at car rental agencies.

The Workshop Hotel

The workshop hotel is INN AT NAPA VALLEY (CROWN STERLING SUITES), Napa,
California.  A block of rooms has been reserved for IEEE VLSI Signal
Processing attendees at a special rate of Single -- $99.00 per night
(Saturday rate -- $109.00) and double:  $114.00 per night (Saturday rate --
$124.00).  Local and state taxes will add approximately 10.5%.  Hotel
reservations should be made directly with the hotel.  Reservation deadline is
October 1, 1992.

ATTTN:  Sales Department
Inn at Napa Valley/Crown Sterling Suite
1075 California Boulevard
Napa, CA  94559
(707)253-9540 or (800)433-4600

WORKSHOP REGISTRATION INFORMATION:

Fees:                                IEEE Member             Non-Member
If received by Oct. 10, 1992         US  $200             US $220
If received after Oct. 10,1992       US  $220             US $240

The registration fee includes hard-bound workshop proceedings, coffee breaks,
three lunches, a Wednesday evening reception, and a Thursday evening reception
at a local winery for wine tasting.

Please send the form below to reserve a space at the workshop.

Check or money order payable to ``92 Workshop on VLSI SP.''  Send to:
Ms. Cathleen Swiggert
University of California
Electrical Engineering Department
Engr. IV 56-125B
Los Angeles, CA  90024-1594
(310)206-8495 (FAX)
cathleen@ee.ucla.edu

Amount enclosed _________________


Name ____________________________________________________________________

Affiliation_____________________________________________________________

Address: ______________________________________________________________

______________________________________________________________________

_______________________________________________________________________

_______________________________________________________________________

Telephone: ____________________________________________________________

FAX:____________________________________________________________________

IEEE Member No: _______________________________________________________

Attendance Grants

Limited funds derived from a National Science Foundation grant are available
to partially cover expenses incurred by recent graduate researchers and
graduate students from US institutions attending the workshop.  For
information and an application, please contact Ms. Cathy Swiggert.

-- 
Takao Nishitani		takao@TSL.CL.nec.co.jp
Manager			C&C Systems Research Labs., NEC Corporation
			Phone: +81 44 856 2118	 Fax: +81 44 856 2232
Newsgroups: fj.meetings,fj.comp.parallel