HDTenEightyP/NetNews huggingface dataset:
From: guy@Auspex.COM (Guy Harris)
Newsgroups: comp.sys.intel
Subject: Re: i860 vs. i960
Date: 18 Nov 92 19:23:09 GMT
Organization: Auspex Systems, Santa Clara

>i960 .... These are intended for "embedded computing"
>applications, like Postscript interpretation, smart bridges/routers,
>and avionics.

Well, they are *now*.

Somebody from Intel once indicated that the i960 was *originally*
intended to be *the* 32-bit microprocessor architecture from Intel, for
everything from toasters through UNIX boxes to BiiN boxes. 
(Unfortunately, I guess the 386 came along too soon, or the first 960
came out too late....)

From e.g. statements in Myers and Budde's book on the 960 architecture,
I can easily believe that was the case.  Was it?  (No spin-doctoring,
please; if it was the case, but Intel doesn't want you to say it was the
case, just don't say anything.)
Newsgroups: comp.sys.intel
From: cs123052@cs.brown.edu (Michael Lee)
Subject: Re: 486 vs. Mac Benchmarks
Organization: Brown Computer Science Dept.
Date: Mon, 23 Nov 1992 18:58:49 GMT

|> Fascinating.  I am finding it very hard to locate *any* published
|> cross-platform benchmarks that compare 486's to Macintosh's in
|> meaningfully comparable applications, such as wordprocessing.  So far
|> I've only located two.  Does anyone know about any others?
|> 
|> The first one I found is in PC Magazine for May 12, 1992, which
|> compares a $7,000 Quadra 700 to a $9,275 Dell PowerLine 450DE
|> (80486-50 cpu).  The latter has a 4MB cache in its EISA controller!
|> (The article says the Dell is running Windows, but the article is not
|> at all clear whether the applications are Windows applications or DOS
|> applications>.

[stuff deleted]

|> in the Oct. PCWorld.  The price/performance ratios of the 24
|> platforms, not counting the PS/2, but counting the Mac, have a 2:1
|> range, whereas the prices have a 3:1 range. (If you plot price vs.
|> performance you see very little correlation.) 21 of the 486's have a
|> worse p-p-ratio than the Mac, and it is only 12% worse than the best.
|> (The only 486 in the 24 faster than the Mac was only 5% faster but 30%
|> more expensive; nearly half of them were more expensive than the Mac)

[ditto]
|> 
|> Ted Lee <tmplee@TIS.COM>


I would like to note, however, one may purchase a Dell 450DE w/ 32bit
SCSI controller & 230MB HD for about $4200 now...

- mike
cs123052@cs.brown.edu
Newsgroups: comp.sys.intel
From: rbhardin@undergrad.math.waterloo.edu (Ron Harding)
Subject: Request for OverDrive technical details
Organization: University of Waterloo
Date: Thu, 19 Nov 1992 18:33:23 GMT

A co-worker has informed me that there was some discussion here a while ago
about the OverDrive chip.  As I understand it, an OverDrive is really a
fully functional CPU which just shuts off the original CPU, but requires
that the original be left in place.

I'm particularly interested in a description of how an OverDrive chip knows
that the original is in place.  Is it just a matter of a couple pins shorted,
or is there some complex handshake between the two chips?

If anyone remembers the gist of that thread, I'd appreciate hearing about
it.

=============================================================================
From a local computer call-in show:	|  Ron Harding
Q: I hear all this talk about base      |  rbharding@descartes.uwaterloo.ca
   memory, expanded memory, and         +------------------------------------
   extended memory.  What is the difference, and why don't I have them on
   my Amiga?
A: Well, the Amiga doesn't offer you that kind of flexibility...
=============================================================================
Newsgroups: comp.sys.intel
From: feustel@netcom.com (David Feustel)
Subject: 960 xa/mm/mx - What are the differences from the mc?
Organization: DAFCO: OS/2 Software Support & Consulting
Date: Sat, 21 Nov 1992 00:12:53 GMT

I just got a copy of the 4th edition 960 Solutions book today and
discovered the xa/mm/mx versions of the 960. What are the software
differences between these chips and the original 960 mc (for which I
have documentation)?


-- 
Dave Feustel N9MYI <feustel@netcom.com>
 
GE knew there was lots of money to be made in the diagnostic medical
machine field since it was only a matter of time before people started
getting sick from the effects of all of GE's toxic and radioactive
waste dumping. I expect GE to get into the Mortuary business next.
Newsgroups: comp.sys.intel
From: plim@diana.cair.du.edu (PATRICK M LIM)
Subject: Floating point performance of 486 vs 386/387?
Organization: University of Denver, Denver, Colorado
Distribution: usa
Date: Thu, 19 Nov 92 04:18:56 GMT

Is the floating point performance better for a 386/33 387
combination or a 486/33?
Thanks in advance
From: solworth@newyork.eecs.uic.edu (Jon Solworth)
Newsgroups: comp.sys.intel
Subject: Intel 486SL
Date: 18 Nov 92 17:55:00 GMT
Article-I.D.: newyork.SOLWORTH.92Nov18115500
Distribution: comp
Organization: Dept. of EECS, University of Illinois at Chicago


Compaq and others have announced a machine with this chip, which is essentially
a 486DX which runs on 3.3 volts.

Are there any other differences?  Is the interface a 32-bit one?

thanks
Jon
______________________________________________________________________________
Jon A. Solworth                 	internet:  solworth@parsys.eecs.uic.edu
Dept. of EECS (M/C 154)         	telephone: (312) 996-0955
University of Illinois at Chicago       FAX:       (312) 413-0024
851 S. Morgan Rm 1120 SEO
Chicago, IL 60607-7053
--
______________________________________________________________________________
Jon A. Solworth                 	internet:  solworth@parsys.eecs.uic.edu
Dept. of EECS (M/C 154)         	telephone: (312) 996-0955
University of Illinois at Chicago       FAX:       (312) 413-0024
851 S. Morgan Rm 1120 SEO
Chicago, IL 60607-7053
From: tapvalli@sara.cc.utu.fi
Newsgroups: comp.sys.intel
Subject: Re: howdy
Date: 23 Nov 92 11:30:52 GMT
Distribution: comp
Organization: University of Turku, Finland


In article <1992Nov23.4528.2689@dosgate>, "darryl sladden" 
<darryl.sladden@canrem.com> writes:
> Hello there Claire,
> 
> How's it going?  I've never used this kind of thing before, so please
> again this week after I get my own account.

  If you did receive this
> send a reply to Darryl Sladden on USENET and let us know, so I'll know
> that I did something right for a change.

	No Darryl, I think you messed it up again. I am terrified about the
thought of you having an own account:):)

		Take care, (and right addresses) Tapsa:)

p.s Many greetings to Claire too:):)
From: davidsen@ariel.crd.GE.COM (william E Davidsen)
Newsgroups: comp.sys.intel
Subject: Re: Idea for the P5!
Date: 19 Nov 92 13:58:30 GMT
Reply-To: davidsen@crd.ge.com (bill davidsen)
Distribution: usa
Organization: GE Corporate R&D Center, Schenectady NY

In article <1992Nov18.222927.20422@nas.nasa.gov>, fineberg@win31.nas.nasa.gov (Samuel A. Fineberg) writes:

| I think the main problem is that its done.  The P5 is no longer under development
| (though they may still be debugging it).  Also, there is no P5 any more, it is
| called the Pentium CPU.  Sure the name is stupid, but its too late to change
| that either.  Maybe you should concentrate on the P6?

  The correct name for the P5 is "Godot."

  I find it interesting that Intel implied that the reason the P5 is
late is because they have all their fab lines tied up with the 486
demand, and yet they have just announced the 486DX2-80. If this sells
well it will tie up more fab lines.

  I predict that the P5 will ship in volume as soon as AMD starts
shipping their 486, just as the 486 suddenly because more available when
other 386 chips were shipping.

-- 
bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
    "We will ship no chip before its time..."
Newsgroups: comp.sys.intel
From: nv89-pla@nada.kth.se (Peter Laan)
Subject: Intel 8051 .
Originator: nv89-pla@hemul.nada.kth.se
Reply-To: nv89-pla@nada.kth.se (Peter Laan)
Organization: Royal Institute of Technology, Stockholm, Sweden
Date: Wed, 18 Nov 1992 20:56:24 GMT

Does anybody know if there is any PD/SW c-compiler for
the 8051 processor. 

Im quite desperate so please i you know anything abt
a compiler, please send me a note...

//
From: tmcconne@sedona.intel.com (Tom McConnell~)
Newsgroups: comp.sys.intel
Subject: RISC vs. CISC (Was: Re: P5 or Pentium)
Date: 20 Nov 1992 18:37:09 GMT
Organization: Intel Corporation
Distribution: world
NNTP-Posting-Host: thunder.intel.com
Originator: tmcconne@sedona


In article <DOCONNOR.92Nov20100231@potato.sedona.intel.com>, doconnor@sedona.intel.com (Dennis O'Connor) writes:
> 
> mu@terapin.com (Mu Hong Lin) writes:
> ] Will someone explain ( technially ) why RISC chips are so much faster
> ] than CISC chips??
> 
> RISC chips don't need to support obsolete mis-features from 10 years ago.
> CISC chips generally do, because they are all old architectures.
> --
> Dennis O'Connor			doconnor@sedona.intel.com

  To be fair, that answer may fit a particular part, but has nothing to do with
the RISC/CISC question.

  The most simplistic answer is that RISC, being relatively simpler to build,
can be made to clock faster. That way it may take five RISC instructions to
duplicate one CISC instruction that takes five cycles, but it will finish first
because it is running faster. For example, as I recall the first HP-PA
(Precision Architecture) chip set was actually bonded to large copper
"Finstrates" to dissapate heat because it ran so fast.

  In a more general sense, there is no clear winner in the RISC/CISC wars,
although RISC seems to be gaining the edge, based on announcements from the last
couple of years.

    Cheers,

    Tom McConnell

 Tom McConnell          |     Internet: tmcconne@sedona.intel.com
 Intel, Corp. C3-91     |     Phone: (602)-554-8229
 5000 W. Chandler Blvd. | The opinions expressed are my own. No one in 
 Chandler, AZ  85226    | their right mind would claim them.
-- 
 Tom McConnell          |     Internet: tmcconne@sedona.intel.com
 Intel, Corp. C3-91     |     Phone: (602)-554-8229
 5000 W. Chandler Blvd. | The opinions expressed are my own. No one in 
 Chandler, AZ  85226    | their right mind would claim them.
Newsgroups: comp.sys.intel
From: fineberg@win31.nas.nasa.gov (Samuel A. Fineberg)
Subject: Re: Idea for the P5!
Organization: CSC, NASA Ames Research Center, NAS Division
Date: Wed, 18 Nov 92 22:29:27 GMT
Reply-To: fineberg@nas.nasa.gov
Distribution: usa

In article <1992Nov18.203321.18612@msuinfo.cl.msu.edu>, sundaram@eecae.msu.edu writes:
|> 
|> Hi y'all,
|> 
|> I had a couple of ideas for how Intel could keep backward compatibility with
|> its 80x86 line of processors without having to dedicate a small part of the 
|> P5 to emulating 80[3|4]86 code. 
|> 
|> Instead of devoting part of the die to emulate 80x86 code, why not include some
|> instructions that will allow the P5 to act as a master processor to a true 
|> (or slightly modified) 80x86 chip.
|> 
|> 
|> 	So, if you run a program run for the 386 on the P5, it will "make" the 
|> 	386 execute them instead and can handle other tasks. The idea is similar
|> 	to the DOS VDM's in IBM's OS/2. These VDM's can run most DOS 5.0 apps,
|> 	but the "OS" they run is not DOS 5.0. Similarly, this chip will not 
|> 	quite be a true 486 but one slightly hacked to allow it to co-operate
|> 	with the P5 and work with it as a slave processor. This MAY include 
|> 	some incompatibilities with existing software, but these can be 
|> 	virtually eliminated by intelligent design etc. Moreover, this will 
|> 	allow users to keep their old 80x86 based software while allowing them
|> 	to step up to the P5 (or the P6, P7 .... ) and its advanced features 
|> 	and superior performance. The P5 could be sold independently, so that
|> 	users who need x86 compsatibility can "upgrade" to it when necessary.
|> 	Also, motherboards for the P5 could have a built in socket for the 
|> 	486 compatible (intel) micro-(co)-processor. 
|> 
|> 	OK, This mirror's OS/2 2.0 's setup quite closely, where DOS/Windows
|> 	support is optional and some programs (like WPWIN 5.1) need to be 
|> 	"fixed" before being able to run under a WINOS2 session. However, the
|> 	setup does provide for compatibility with over 95% of the DOS software
|> 	out there. Could this be done for the P5?
|> 
|> 
|> Voila!
|> 
|> Now, don't flame me. This is just an idea. I do not know how feasible this is
|> going to be. I will let you decide.
|> 
|> Later y'all
|> 
|> Divya
|> (sundaram@egr.msu.edu)
I think the main problem is that its done.  The P5 is no longer under development
(though they may still be debugging it).  Also, there is no P5 any more, it is
called the Pentium CPU.  Sure the name is stupid, but its too late to change
that either.  Maybe you should concentrate on the P6?

Sam
Newsgroups: comp.sys.intel
From: ken@mri.com (Ken Greenberg)
Subject: Re: Microcontroller
Organization: Microtec Research Inc., Santa Clara, CA
Date: Mon, 16 Nov 1992 19:34:39 GMT

ps02@ns1.cc.lehigh.edu (PENELOPE E. SMITH) writes:

>In article <1992Nov11.052400.28073@nuscc.nus.sg>, eletanjm@nuscc.nus.sg (Tan Jin
> Meng) writes:
>>Does INTEL have a microcontroller (ie UART, A/D IO ports etc) that comes
>....
>>1) I have a requirement for a microcontroller (small board space).

>In a not too recent (several months) EE TIMES I saw an IBM PC on a 2X2 board.
>Small enough?


This is probably Ampro Computers' CoreModule line. They come in various
flavors from a PC up to a 386SX and (I believe) even a 486. There are a 
few other vendors of this kind of system, but Ampro tends to be the
industry leader. They have a whole line of CoreModules that stack up
to make any kind of system you want. The footprint stays the same but
the system becomes more "cubic" as you stack them up. There is an
organization that is standardizing the bus used as PC104.

They are at (408) 522-2100 in the US. They have international distributors
if you are located outside the US.
-- 
Ken Greenberg (ken@mri.com)        |      "Never let judgment get in
Director, Technical Marketing      |      the way of procedure."
Microtec Research, Inc.            |       - Nick Tredennick, discussing USAF practice.
Newsgroups: comp.sys.intel
From: pauls@truevision.com (Paul Scherf)
Subject: Question about i386/i486 protected mode far jumps
Summary: Why does it clear the NT flag of the destination
Keywords: protected mode, far jumps
Organization: Truevision Inc., Indianapolis, IN
Date: Wed, 18 Nov 1992 22:27:22 GMT

In an attempt to better understand protected mode, I'm trying to figure out far
CALL, far IRET and far JMP. Let me call them simply CALL, IRET and JMP.

When a CALL, IRET or JMP causes a task switch (e.g. by referencing a TSS or a
task gate), it appears that the important things to understand are what happens
to the busy bits, NT flags and link fields of the old and new tasks.

The busy bit seems straight forward. It keeps track of whether the TSS is in
the middle of execution. JMP and IRET clear the busy bit of the old TSS (the
old TSS is becoming inactive), while CALL leaves the busy bit of the old TSS
(it will be on) alone. JMP and CALL ensure the busy bit of the new TSS was off
and turn on the busy bit of the new TSS (the new TSS is becoming active), while
IRET leaves the busy bit of the new TSS (it better already be on) alone.

The link field of a TSS is used to keep a stack of TSS's (implemented as a
linked list). CALL pushes a TSS onto the stack. That is, CALL points the link
field of the new TSS at the old TSS, and sets the NT flag. IRET pops a TSS from
the stack. That is, IRET uses the link field of the old TSS to find the new
TSS, and clears the NT flag of the old TSS.

JMP, well, I'm a bit confused about JMP. The book (i486 Programmer's Reference
Manual) says that JMP clears the NT flag of the new TSS. If JMP left the NT
flag of the new TSS alone, it would make more sense to me.

I can think of several possible scenarios where a system might have several TSS
stacks. I can imagine the currently executing task (at the top of a TSS stack)
wanting to switch to a particular other task (e.g. at the top of one of the
other TSS stacks).

JMP seems to do the right thing with the busy bits. The new TSS becomes busy.
The old TSS becomes not busy. JMP seems to do the right thing with the link
fields of the old and new tasks, it leaves them alone. That seems reasonable,
they should return to whatever CALL'd them. JMP doesn't seem to do quite the
right thing with the NT flags. It does leave the NT flag alone on the old TSS,
but it clears the NT flag on the new TSS. This invalidates the return chain of
the new TSS.

I can see a work-around for this situation. CALL a "task switcher" TSS, that
IRET's to the desired new TSS. This still leaves me wondering what JMP is good
for.

Why does JMP clear the NT flag of the new TSS? JMP clearly doesn't do the right
thing for my example. What are some correct uses of JMP? Am I missing something
about CALL and IRET? Is there a good book that gets to at least this level of
detail about the i486?

Paul Scherf
pauls@truevision.com
Truevision Inc., Indianapolis, IN
From: doconnor@sedona.intel.com (Dennis O'Connor)
Newsgroups: comp.sys.intel
Subject: Re: P5 or Pentium
Date: 20 Nov 92 10:02:31
Organization: Intel i960(tm) Architecture
NNTP-Posting-Host: potato.intel.com
In-reply-to: mu@terapin.com's message of 19 Nov 92 19:53:09 PST


mu@terapin.com (Mu Hong Lin) writes:
] I wonder how Motorola is doing with '050.

They're not. Motorola is jumping straight to the 68060. Due out in '94 I THINK.

] I guess Intel's profit is too great, I mean, Intel makes more money,
] and will have more money to spend in R&D.

Actually, I'm pretty sure Motorola is actually bigger than Intel, in gross
revenues. But Motorola is also more diversified : they make cellular phone,
pagers, police radios, and other things, as well as chips.

] Will someone explain ( technially ) why RISC chips are so much faster
] than CISC chips??

RISC chips don't need to support obsolete mis-features from 10 years ago.
CISC chips generally do, because they are all old architectures.
--
Dennis O'Connor			doconnor@sedona.intel.com
From: doconnor@sedona.intel.com (Dennis O'Connor)
Newsgroups: comp.sys.intel
Subject: Re: i860 vs. i960
Date: 18 Nov 92 08:10:27
Organization: Intel i960(tm) Architecture
NNTP-Posting-Host: potato.intel.com
In-reply-to: esky@marathon.cs.ucla.edu's message of Tue, 17 Nov 92 23:39:54 GMT


the Intel i860(tm) and i960(R) processor families are not related
to each other. The i860 processors are intended for "scientific"
applications ( i.e. those with tons of FPU work ). The i960 family
of processors, ranges from the low-cost i960 SA microprocessor,
to the world's first commercially-available superscalar microprocessor
( the i960 CA and the follow-on CF ), to the military-standard
i960 XA and MX processors. These are intended for "embedded computing"
applications, like Postscript interpretation, smart bridges/routers,
and avionics.

Given the vast difference in the intended markets for the products,
you can imagine the architectures are very different, and they are.
Both are "RISCy", and both are 32-bit, and both are from Intel :
other than that, they don't have a lot in common.
--
Dennis O'Connor			doconnor@sedona.intel.com
Newsgroups: comp.sys.intel
From: feustel@netcom.com (David Feustel)
Subject: 960 mc Simulator (in software)?
Organization: DAFCO: OS/2 Software Support & Consulting
Date: Wed, 18 Nov 1992 23:47:27 GMT

Does anyone know whether there exists a program that simulates
instruction execution of the Intel 960 mc processor? I called Intel
development tools today and the answer is "no" as far as Intel is
concerned.
-- 
Dave Feustel N9MYI <feustel@netcom.com>
 
GE knew there was lots of money to be made in the diagnostic medical
machine field since it was only a matter of time before people started
getting sick from the effects of all of GE's toxic and radioactive
waste dumping. I expect GE to get into the Mortuary business next.
From: rpb@psy.ox.ac.uk (Ray Bellis)
Newsgroups: comp.graphics
Subject: Working anti-aliased line drawing routine needed
Date: 18 Nov 92 15:33:54 GMT
Organization: Dept. of Experimental Psychology, Oxford, England.


I've been trying to use the algorithms in Burger & Gillies
(Interactive Computer Graphics) for 8 octant anti-aliased
line drawing but I can't get them to work.  Does anyone
please have a *working* function (preferably in C) that
I could have.

The main problem I have is that the algorithm I have expects
to plot two pixels for each iteration of the loop, and I can't
figure out for the 8 octant version where to place the second
pixel relative to the primary pixel.

Thanks,

p.s. I know about the code in graphics gems, and that's
     definite overkill.


--
------------------------------------------------------------------------------
R. P. Bellis				E-Mail:	<rpb@psy.ox.ac.uk>
Dept. of Experimental Psychology	Whois:	(RB83)
University of Oxford			Tel:	+44 865 271419
South Parks Road			Fax:	+44 865 310447
Oxford OX1 3UD
------------------------------------------------------------------------------
From: spl@ivem.ucsd.edu (Steve Lamont)
Newsgroups: comp.graphics
Subject: Re: CGM Public Domain
Date: 21 Nov 1992 02:44:17 GMT
Organization: University of Calif., San Diego/Microscopy and Imaging Resource
NNTP-Posting-Host: ivem.ucsd.edu

In article <1992Nov21.001220.12459@netcom.com> ampac@netcom.com (Marc Kulla) writes:
>2 questions:

Two answers.

>1.  Are there _any_ public domain CGM readers around?  I know that it would
>    not be a beautiful or robust app, but something to get started with.

Yes.  Get ahold of GPLOT from the Pittsburg Supercomputer Center.
calpe.psc.edu (128.182.62.148).

>2.  I know you can get the specs from American National Standards Inst,
>    but do any services on the internet provide access to it?

Probably not, since it is, to the best of my knowledge, copyrighted
material.

							spl
-- 
Steve Lamont, SciViGuy -- (619) 534-7968 -- spl@szechuan.ucsd.edu
UCSD Microscopy and Imaging Resource/UCSD Med School/La Jolla, CA 92093-0608
"Morgenstund hat Gold im Mund..."
"... wer laenger schlaeft, bleibt auch gesund!" - email private communication
Newsgroups: comp.graphics
From: mazzucch@ghost.dsi.unimi.it (massimo mazzucchi)
Subject: dtp program
Organization: Computer Science Dep. - Milan University
Date: Wed, 18 Nov 1992 13:18:49 GMT


HI 

i am Max from Milan Italy

i will know if exist a PD program (not windows) or commercial

like publisher/page maker that:

- there aren't the difficultes to use it

- max 1 Mb di program

- and it can write A4 (21x29) ruotate (29x21) in which way 

 i can write on 2 page (15x21) but that left page must be

 an object and right page another object.

 ---------
 |        |                    ____________________
 |        |                    |        |         |
 |        |                    |        |         |
 |        |    --->            |        |         |
 |        |                    |        |         |
 |        |                    --------------------
 ----------
 Thanks for your help

 Bye


--------------------------------------------------------------------------------
!  Massimo Mazzucchi                         address    e-mail                !
!  University of State                       mazzucch@ghost.dsi.unimi.it      !
!  Departement of Computer Science            149.132.2.1                     ! 
!  Via Comelico, 41 -  20133 MILAN ITALY                                      !
 -------------------------------------------------------------------------------
Newsgroups: comp.graphics