From: siraisi@hcrlgw.crl.hitachi.co.jp (Yoichi Shiraishi)
Newsgroups: fj.meetings
Subject: 4th Physical Design Workshp (text)
Date: 1 Oct 92 02:08:50 GMT
Distribution: fj
Organization: Central Research Lab., Hitachi Ltd.

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                         CALL FOR PAPERS

             The 4th ACM/SIGDA Physical Design Workshop
Layout Synthesis for the New Generation of VLSI ASIC Technologies
                        April 19-21, 1993
               Lake Arrowhead, California, U.S.A.

OBJECTIVE

The rapid advances in VLSI ASIC technologies have led to many new
challenges  in  the  physical  design automation of VLSI systems:
The increasing emphasis on  system  performance  requires  timing
constraints  to  be considered at every stage of physical design;
the constantly decreasing  feature  size  leads  to  much  denser
circuits  (close  to  one million gates on a single chip) and the
interconnection delay becomes the  dominating  factor  in  system
performance;  the  widespread  use  of  automatic logic synthesis
tools complicates many  layout  problems;  the  strong  need  for
shorter design cycles and lower design costs have resulted in the
fast development of field-programmable  gate-arrays  (FPGAs)  and
field-programmable  interconnects  (FPICs). The objective of this
workshop is to provide a forum to discuss and  investigate  these
emerging  problems  in  physical  design  automation  for the new
generation of VLSI ASIC technologies.

SCOPE

The workshop welcomes papers on recent developments in all  areas
of   physical   design  automation  of  VLSI  systems,  including
partitioning, floorplanning and placement,  global  and  detailed
routing,  module  generation,  and  compaction for ICs, MCMs, and
FPGAs.  In particular, the workshop encourages submissions on the
following topics:
   + Partitioning  and  placement  techniques  for  very   large
     circuits.
   + Performance optimization in layout designs.
   + Design and evaluation of high-speed interconnects in IC  and
     MCM designs.
   + Integration of logic synthesis and layout design.
   + Layout design for field-programmable gate arrays (FPGAs) and
     field-programmable interconnects (FPICs).
   + Layout design for multiple-chip modules (MCMs).

SUBMISSION

Authors should submit 8 copies of a manuscript, not exceeding  15
pages  (including  abstract, figures, tables, and references), to
the program chair by Dec. 15, 1992. Authors should state  clearly
the  originality of their contributions, with adequate comparison
with  existing  methods.   An  informal   proceedings   will   be
distributed  at the workshop, where authors can contribute either
the full paper (up to 12 pages)  or  a  summary  of  results  (an
extended abstract of 2-4 pages or a copy of the view-graphs of up
to 12 pages).

ORGANIZING COMMITTEE

Workshop Chair	        	Workshop Co-Chair	
Prof. Jason Cong		Dr. Bryan Preas	
Computer Science Dept. 		Xerox PARC	
Univ. of California		3333 Coyote Hill Road	
Los Angeles, CA 90024		Palo Alto, CA 94304 	
Tel: 310-206-2775		Tel: 415-812-4845	
Fax: 310-825-2273		Fax: 415-812-4471	
cong@cs.ucla.edu		preas.pa@xerox.com	

Program Chair			Publication Chair  
Prof. Carl Sechen		Prof. Mary Jane Irwin
Electrical Engineering Dept.	Computer Science Dept.
Univ. of Washington, FT-10	Penn State University
Seattle, WA 98195		University Park, PA 16802
Tel: 206-685-8756		Tel: 814 865-9505
Fax: 206-543-3842		Fax: 814 865-3176
sechen@ee.washington.edu	mji@cs.psu.edu


PROGRAM COMMITTEE

Jeff Burns (IBM Watson, USA)
Wayne Dai (UC Santa Cruz, USA)
Patrick Groeneveld (TU of Delft, The Netherlands)
Andrew Kahng (UCLA, USA)
Youn-Long Lin (Tsing Hua Univ., Taiwan)
C. Y. Lo (AT&T Bell Lab, USA)
Massoud Pedram (USC, USA)
Rob Rutenbar (CMU, USA)
Lou Scheffer (Cadence, USA)
Yoichi Shiraishi (Hitachi Ltd., Japan)
Martin Wong (UT Austin, USA)
Gerhard Zimmermann (Univ. of Kaiserslautern, Germany)


BENCHMARKS

	Benchmark Chair
	Dr. Krzysztof Kozminski
	MCNC, P.O. Box 12889
	RTP, NC 27709
	Tel: 919-248-1969
	kk@mcnc.org

In addition to the existing layout design benchmarks  established
by the previous physical design workshops, this workshop is going
to release a set of new benchmarks of 100,000 - 300,000 cells for
testing  partitioning  and  placement  techniques  for very large
designs.  Moreover,  a set of MCM routing benchmarks of  2,500  -
15,000 pins will be released for testing multi-layer general area
routing algorithms in MCM designs.

Benchmarks will be available via anonymous ftp from  mcnc.org  or
on  magnetic tape.  Send e-mail to benchmarks@mcnc.org to receive
more information.  Benchmark session participants are invited  to
send   in   their  results  to  the  benchmark  chair  by  e-mail
(kk@mcnc.org) by April 5, 1993.  Further  instructions  regarding
the benchmark session will be given in the advance program of the
workshop.

IMPORTANT DATE

   Dec. 15, 1992:  Deadline of submission.
   Feb. 15, 1993:  Notification of acceptance.
   Mar. 25, 1993:  Camera-ready copy is due.

*****************************************************************


--
 ----------------------------- Yoichi Shiraishi -----------------------------
   Function-Device Research Office, Central Research Laboraty, Hitachi, Ltd.
         1-280  Higashi-Koigakubo Kokubunji Tokyo, 185 Japan
 --- siraisi@crl.hitachi.co.jp Tel:0423-23-1111 Ext:4122 Fax:0423-27-7779 ---