HDTenEightyP/NetNews huggingface dataset:
From: ellen@opua.Berkeley.EDU (Ellen M. Sentovich)
Newsgroups: comp.lsi.cad
Subject: Re: SIS (latest MIS version)
Date: 24 Jan 1993 00:05:24 GMT
Organization: UC Berkeley
Distribution: na
Reply-To: ellen@opua.Berkeley.EDU (Ellen M. Sentovich)
NNTP-Posting-Host: opua.berkeley.edu

The following is the latest release message for SIS:

*****

The second release of SIS, SIS-1.1,  is available via anonymous ftp
or by ordering a tape from the UCB EECS ILP office.

Instructions for anonymous ftp:

ftp ic.berkeley.edu (the net address for ic is 128.32.132.1)
Name: anonymous
Password: anything
binary
cd pub/sis
get sis-1.1.tar.Z
get sis-1.1.patch1
quit

Note that the file sis-1.1.tar.Z is 5.9 Mbytes.  Benchmark examples
take up a significant amount of memory.  A version without the
examples is in the file sis-1.1.noex.tar.Z (it is 3 Mbytes).

To uncompress and extract the SIS files:

uncompress sis-1.1.tar.Z
tar xf sis-1.1.tar

Instructions for obtaining a tape:

Contact Cindy Manly-Fields in the ILP office (cost is $150):

Cindy Manly-Fields
Software Distribution Office
EECS/ERL Industrial Liaison Program
479 Cory Hall
University of California at Berkeley
Berkeley, CA  94720

(510) 643-6687
cindy@hera.berkeley.edu

After the tape has been obtained, uncompress and extract the
SIS files as described above.  Within the top level directory:

The file README contains information about compiling and running SIS,
getting help, and sending comments/bugs/suggestions to the authors.

The file RELEASE-NOTES-1.1 contains information about this release of
SIS, including updates and new packages.

The file SIS-paper.ps is a paper describing all the sequential
optimization and synthesis techniques in SIS, as well as updates to
the combinational techniques.  For a full description of combinational
algorithms, see the combinational references in this paper.  SIS-paper.ps
also has examples for synchronous and asynchronous design, and descriptions
of the BLIF (Berkeley Logic Interchange Format for netlists) and GENLIB
(format for library gates) formats.

All comments/questions/bugs should be sent to sis@ic.berkeley.edu.

-- 
Ellen M. Sentovich
Dept of EECS
UC Berkeley
ellen@ic.Berkeley.EDU
Newsgroups: comp.lsi.cad
From: bender@renfield.uucp (Craig Bender)
Subject: Re: Pin assignment
Keywords: pin assignment, algorithm, program
Organization: Seattle Silicon Corporation, Bellevue, WA
Date: Mon, 25 Jan 1993 22:08:18 GMT

I don't know of a software tool that can handle your Pin Assignment
problem, but I'll comment on your overall plan.

You're over simplifying by assumming an "in-house design" provides
"full control over the process" (of assigning pin locations) since
who manufactures the ICs and who within your company approves spending
(money) are going to limit `your control'.  For example:

1]  All Gate-Array ASIC suppliers have a limited number of package
    options available and many packages have limitations on power
    and ground locations.  This is very true of high pin count
    ceramic packages.

2]  If you're generating the packaged units in-house then your purchasing
    folks will want `open-tooled' packages selected instead of custom
    designs that can cost $45K+ to design and tool.

3]  Even if all the ICs are in PQFPs with no PQFP Vendor restrictions
    on pin assignments you'll still have pin placement restrictions due
    to the actual IC functions.

    IC -a- could be designed on a FAB process and set of design rules that
    requires one power/ground pair per every eight output pads while IC
   -b- needs one pair per four outputs.  If both devices have the same
    footprint and drive the same bus you're going to be hard pressed to
    find a single solution.

These are real world issues and very dependant on the IC functions,
design rules, and process performance while they have less to do with
`in-house design and control' of the ICs themselves.  ASIC package selection
is still treated as a low-tech no brainer that causes endless confusion
for IC designers and ASIC suppliers (like me) late in a design cycle.

Good Luck.
            Craig Bender
            Product Engineer
----------------------------------------
From: arrigo@cube.sublink.org (Arrigo Benedetti)
Newsgroups: comp.lsi.cad
Subject: Looking for hard to simulate MOS circuit(s)
Date: 21 Jan 93 16:12:37 GMT
Reply-To: arrigo@cube.sublink.org
Organization: Arrigo Benedetti

I am looking for some simple MOS circuits that are difficult to simulate
with SPICE-like circuit simulators. I need this because I'm implementing
the infamous gmin stepping algorithm in a multilevel circuit simulator
that I'm developing for my thesis. In particular, I'm interested in MOS
circuits that will not achieve convergence with Newton-Raphson, but that
will converge with the gmin stepping algorithm. Our simulator at present
can only do .OP and .DC sweep analyses and handle SPICE LEVEL 1 mosfets,
so please submit only circuits exhibiting convergence problem with these
type of analyses and device model.
What I'm looking for is a simple circuit (<= 10 devices) for which it is 
known that it will get to convergence ONLY with gmin steppping.
I'm aware that circuits with positive feedbacks (e.g. static MOS SR
flip-flops) are hard to simulate with existing techniques.

Descriptions files in SPICE format are welcome.

I will summarize any reply to the Net.

Thanks,

-Arrigo Benedetti
-- 
Arrigo Benedetti             e-mail: arrigo@cube.sublink.org (preferred)
University of Bologna                benedett@deis01.cineca.it
undergraduate student (EECS)         
Via S. Agata, 11               Tel:  (home)   +39 59 224929
41100 Modena - Italy                 (office) +39 59 216688 (fax) +39 59 220727
Xref: sparky comp.lsi.cad:1347 comp.lsi:805 alt.cad:503
From: glenn@sm.luth.se (Glenn Jennings)
Newsgroups: comp.lsi.cad,comp.lsi,alt.cad
Subject: Help with BDNET please
Keywords: BDNET, BDSYN, Octtools, Berkeley Tools, Netlisting
Date: 26 Jan 93 15:10:15 GMT
Followup-To: comp.lsi.cad
Organization: University of Lulea, Sweden

For you OCTTOOLS experts, from a beginner:  BDNET questions please !

1) is there something like BDSYN's "SYNONYM" function in BDNET to create new
   named (and local) bundles by picking and choosing bits from other
   bundles (bit vectors), for example:

      NEW_INTERNAL_SIGNAL<4:0> = IN_A<2> & IN_B<2> & IN_B<2> & LOCAL<3:2>;

  ...or something like this ?  I hope the answer is not:
   
    a) I have to keep track of all individual bits myself in terms of their
       ultimate source or destination names:
         (in that case the problem still occurs if I want to tie a primary
          input directly to a primary output, doesn't it ?)

       or

    b) actually wire them through a dummy bdsyn module that does the
       bit-gathering for me and passes out my new bit vector...

2) does more complete BDNET documentation exist (more than the man pages
   distributed with OCTTOOLS) ?

3) using the scmos standard cells:  anything resembling a gated transparent
   latch, or do I have to wire my own together ??

PS I couldn't get BDSYN's "SYNONYM" (sic) function to work either...

Thanks! Glenn J.
    Glenn Jennings,       Tekn.Dr.       Email:  glenn@sm.luth.se
    Div.  of  Computer Engineering       Tel:     (+46) 920 91763
    Lulea University of Technology       Alt:     (+46) 920 91000
    S-951 87 Lulea,         SWEDEN       Fax:     (+46) 920 97288
From: aimane@pike.ee.mcgill.ca (Aiman El-Maleh)
Newsgroups: comp.lsi.cad
Subject: SIS (latest MIS version)
Date: 23 Jan 93 21:02:28 GMT
Distribution: na
Organization: McGill University - VLSI Laboratory, Montreal, CANADA.

Hi,
  We are looking for the ftp site of SIS, or the latest version of
MIS (multilevel interactive system) which includes the concurrent 
decomposition and factorization algorithm. If you have any information
how we can get, we will appreciate your immediate response.
Thanks,

Aiman
From: glenn@sm.luth.se (Glenn Jennings)
Newsgroups: comp.lsi.cad
Subject: Help with BDNET please
Date: 26 Jan 93 15:18:02 GMT
Reply-To: Glenn Jennings <glenn@my.sm.luth.se>
Organization: University of Lulea, Sweden

For you OCTTOOLS experts, from a beginner:  BDNET questions please !

1) is there something like BDSYN's "SYNONYM" function in BDNET to create new
   named (and local) bundles by picking and choosing bits from other
   bundles (bit vectors), for example:

      NEW_INTERNAL_SIGNAL<4:0> = IN_A<2> & IN_B<2> & IN_B<2> & LOCAL<3:2>;

  ...or something like this ?  I hope the answer is not:
   
    a) I have to keep track of all individual bits myself in terms of their
       ultimate source or destination names:
         (in that case the problem still occurs if I want to tie a primary
          input directly to a primary output, doesn't it ?)

       or

    b) actually wire them through a dummy bdsyn module that does the
       bit-gathering for me and passes out my new bit vector...

2) does more complete BDNET documentation exist (more than the man pages
   distributed with OCTTOOLS) ?

3) using the scmos standard cells:  anything resembling a gated transparent
   latch, or do I have to wire my own together ??

PS I couldn't get BDSYN's "SYNONYM" (sic) function to work either...

Thanks! Glenn J.
    Glenn Jennings                       Email:  glenn@sm.luth.se
    Div.  of  Computer Engineering       Tel:     (+46) 920 91763
    Lulea University of Technology       Alt:     (+46) 920 91000
    S-951 87 Lulea,         SWEDEN       Fax:     (+46) 920 97288
Newsgroups: comp.lsi.cad
From: jcooley@world.std.com (John Cooley)
Subject: Joining ESNUG
Organization: The E-mail Synopsys Users Group (ESNUG)
Date: Thu, 21 Jan 1993 05:46:28 GMT


  If you're using the Synopsys Design Compiler and/or their ATPG product, you 
  might be interested in joining the E-Mail Synopsys Users Group (ESNUG).

  What we are is a group of hardware designers from all over the world who
  wish to trade experiences, bug reports and the techniques that we've
  found that work best in getting a design from a behavioral description
  to a final fully tested product.  This is a grassroots forum independent
  of Synopsys, Inc.

  A Sample of What We Discuss:

	- Known Synopsys Compiler Bugs    - Implementing Boundry Scan

	- Mentor related issues    - EDIF related issues

	- Hierarchical Compliations   - design_analyzer   - JTAG

	- How Various ASIC Vendors Model Their Macros.   - Clock Constraints

	- Using ATPG Tools   - The Best Way To Write State Machines in Verilog

	- Using VHDL   - System Simulation vs. Synopsys Friendly Code

	- Clever Workarounds to Known Pitfalls   - Testing Strategies

  In order to insure an open discussion, but yet keep our respective managers
  happy in having our company's projects remain SECRET, submissions to be 
  posted to the ESNUG mailing list can be stripped of identifying engineers 
  and company names if so requested.

  In addition, to further secure privacy and to avoid e-mail headers that
  are hundreds of names long, each mailing is a batch of singlely addressed 
  e-mail letters.

  If you want to join ESNUG, please send me e-mail to "jcooley@world.std.com"
  saying you wish to join and why.  (Please don't send a copy of this letter
  back to me, I know what you're refering to when you're writing.)

					- John Cooley
					  ESNUG Moderator

 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
     /o o\  /  it's a FEATURE!"   |    Backup Address: jcooley@miracle.com
    (  >  )                       |              (508) 429-4357
     \ - /       |   Snail Mail: P.O. Box 6222, Holliston, MA 01746-6222
     _] [_       |     "This here ain't no one's opinion 'cept my own."


Xref: sparky comp.lsi:815 comp.lsi.cad:1355
From: jcooley@world.std.com (John Cooley)
Subject: Joining ESNUG
Organization: The E-mail Synopsys Users Group (ESNUG)
Date: Thu, 21 Jan 1993 05:45:40 GMT


  If you're using the Synopsys Design Compiler and/or their ATPG product, you 
  might be interested in joining the E-Mail Synopsys Users Group (ESNUG).

  What we are is a group of hardware designers from all over the world who
  wish to trade experiences, bug reports and the techniques that we've
  found that work best in getting a design from a behavioral description
  to a final fully tested product.  This is a grassroots forum independent
  of Synopsys, Inc.

  A Sample of What We Discuss:

	- Known Synopsys Compiler Bugs    - Implementing Boundry Scan

	- Mentor related issues    - EDIF related issues

	- Hierarchical Compliations   - design_analyzer   - JTAG

	- How Various ASIC Vendors Model Their Macros.   - Clock Constraints

	- Using ATPG Tools   - The Best Way To Write State Machines in Verilog

	- Using VHDL   - System Simulation vs. Synopsys Friendly Code

	- Clever Workarounds to Known Pitfalls   - Testing Strategies

  In order to insure an open discussion, but yet keep our respective managers
  happy in having our company's projects remain SECRET, submissions to be 
  posted to the ESNUG mailing list can be stripped of identifying engineers 
  and company names if so requested.

  In addition, to further secure privacy and to avoid e-mail headers that
  are hundreds of names long, each mailing is a batch of singlely addressed 
  e-mail letters.

  If you want to join ESNUG, please send me e-mail to "jcooley@world.std.com"
  saying you wish to join and why.  (Please don't send a copy of this letter
  back to me, I know what you're refering to when you're writing.)

					- John Cooley
					  ESNUG Moderator

 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
     /o o\  /  it's a FEATURE!"   |    Backup Address: jcooley@miracle.com
    (  >  )                       |              (508) 429-4357
     \ - /       |   Snail Mail: P.O. Box 6222, Holliston, MA 01746-6222
     _] [_       |     "This here ain't no one's opinion 'cept my own."


Xref: sparky comp.lsi:793 comp.lsi.cad:1326
From: schuster@shpptl.edag.ptdg.sharp.co.jp (Bernd SCHUSTER)
Newsgroups: comp.lsi,comp.lsi.cad
Subject: Scheduling/Allocation for High Level Synthesis
Date: 22 Jan 93 02:03:58 GMT
Followup-To: comp.lsi
Organization: Production Technology Lab., SHARP Corp., Tenri, Nara, Japan

Hello!

I am interested in the following paper of ICCAD '91:
An Algorithm for Component Selection in Performance
Optimized Scheduling, by L. Ramachandran and D. Gajski
of the University of California, Irvine. Especially if
there is a more detailled description of this work or
an implementation. I am comparing different scheduling
and allocation strategies for High Level Synthesis.

If anyone on the net can help me to get further information,
or how to contact the authors, email or mail is appreciated.

Thank you in advance.

Bernd Schuster               schuster@edag.ptdg.sharp.co.jp

"Rapport"-Tenri #249,
2613-1, Ichinomoto-cho,
Tenri-shi, Nara 632,
From: ronald@cs.tu-berlin.de (Ronald Hindmarsh)
Newsgroups: comp.lsi
Subject: Impact of minimal transistor width 3 or 4 instead of 2?
Date: 25 Jan 1993 19:54:43 GMT
Organization: Technical University of Berlin, Germany
NNTP-Posting-Host: harry.cs.tu-berlin.de
Keywords: CMOS VLSI


I am working on a CMOS-VLSI layout generator for digital circuits. 

For topological reasons I would like to limit the MINIMUM w/l
of a MOS transistor to 3 or 4 (in some physical design rules
of a process I have seen a minimal transistor width of 2).

Do you think, from your experience, this would have a strong
impact on the performance or the power consumption of a circuit?


----------------------------------------------------------------------
 Ronald Hindmarsh                      e-mail: ronald@cs.tu-berlin.de
 Institut fuer Technische Informatik
 TU Berlin FR 3-9
 Franklinstr. 29                            Phone: (+49) 30 314-73432
 W-1000 Berlin 10                             Fax: (+49) 30 314-21103
----------------------------------------------------------------------
Newsgroups: comp.lsi,comp.lsi.cad
From: volker@vlsivie.tuwien.ac.at (Volker Hamann)
Subject: Availability of waveform visualizer for simulation
Keywords: simulation,waveform
Reply-To: volker@vlsivie.tuwien.ac.at (Volker Hamann)
Organization: Technical University of Vienna
Date: Mon, 25 Jan 1993 11:12:12 GMT

Hello!

We have obtained a software product for system level design (well, uh, it's
more like a finite state machine designer capable of generating VHDL code).
This product incorporates a simulator which unfortunately is only text-based
which means it writes signal values, state changes etc. onto standard output
but does not provide any other means of visualisation.

What we would like to have is a kind of X11 based waveform visualizer which
takes the textual simulation output as input and displays it as waveforms
in an X11 window.

Does anybody know if there is such a product available which is easily
configurable to our needs and possibly free of charges?

Thank you for any info,

	Volker

--
|   /| ! Volker Hamann              ! Email: volker@vlsivie.tuwien.ac.at
|  / | ! Department for VLSI Design ! Phone: (++43 1) 58801-8142
|-/--| ! University of Technology   ! Fax:   (++43 1) 569697
|/   | ! Vienna, Austria              "IS THERE ANYBODY OUT THERE?"
From: glenn@sm.luth.se (Glenn Jennings)
Newsgroups: comp.lsi
Subject: Help with BDNET please
Date: 26 Jan 93 15:20:17 GMT
Reply-To: Glenn Jennings <glenn@my.sm.luth.se>
Organization: University of Lulea, Sweden

For you OCTTOOLS experts, from a beginner:  BDNET questions please !

1) is there something like BDSYN's "SYNONYM" function in BDNET to create new
   named (and local) bundles by picking and choosing bits from other
   bundles (bit vectors), for example:

      NEW_INTERNAL_SIGNAL<4:0> = IN_A<2> & IN_B<2> & IN_B<2> & LOCAL<3:2>;

  ...or something like this ?  I hope the answer is not:
   
    a) I have to keep track of all individual bits myself in terms of their
       ultimate source or destination names:
         (in that case the problem still occurs if I want to tie a primary
          input directly to a primary output, doesn't it ?)

       or

    b) actually wire them through a dummy bdsyn module that does the
       bit-gathering for me and passes out my new bit vector...

2) does more complete BDNET documentation exist (more than the man pages
   distributed with OCTTOOLS) ?

3) using the scmos standard cells:  anything resembling a gated transparent
   latch, or do I have to wire my own together ??

PS I couldn't get BDSYN's "SYNONYM" (sic) function to work either...

Thanks! Glenn J.
    Glenn Jennings                       Email:  glenn@sm.luth.se
    Div.  of  Computer Engineering       Tel:     (+46) 920 91763
    Lulea University of Technology       Alt:     (+46) 920 91000
    S-951 87 Lulea,         SWEDEN       Fax:     (+46) 920 97288



-- 
    Glenn Jennings                       Email:  glenn@sm.luth.se
    Div.  of  Computer Engineering       Tel:     (+46) 920 91763
    Lulea University of Technology       Alt:     (+46) 920 91000
    S-951 87 Lulea,         SWEDEN       Fax:     (+46) 920 97288
From: paul@canuck.Berkeley.EDU (Paul Cohen)
Newsgroups: comp.lsi
Subject: Re: Impact of minimal transistor width 3 or 4 instead of 2?
Date: 28 Jan 1993 02:23:37 GMT
Organization: University of California at Berkeley
NNTP-Posting-Host: canuck.berkeley.edu
Keywords: CMOS VLSI

In article <1k1gi3INNbgs@news.cs.tu-berlin.de> ronald@cs.tu-berlin.de (Ronald Hindmarsh) writes:
>
>I am working on a CMOS-VLSI layout generator for digital circuits. 
>
>For topological reasons I would like to limit the MINIMUM w/l
>of a MOS transistor to 3 or 4 (in some physical design rules
>of a process I have seen a minimal transistor width of 2).
>
>Do you think, from your experience, this would have a strong
>impact on the performance or the power consumption of a circuit?
>

Depends mostly on the Delta W for the target process or processes.
I've seen  2 micron processes with Delta W > 2, so if the transistor
was drawn 2 microns wide, you'd have nothing left! Also, as W
approaches Delta W, the characteristics really degrade.


-- 
Paul B. Cohen				| paul@aha.com
Advanced Hardware Architectures, Inc.	| paul@ic.berkeley.edu
P.O Box 9669				| (208) 883-8000 (v)
Moscow, ID 83843			| (208) 883-8001 (f)
Xref: sparky comp.lsi:813 comp.lsi.cad:1352 news.answers:5481
From: al@rbc.uucp (Al Davis)
Newsgroups: comp.lsi,comp.lsi.cad
Subject: ACS  circuit simulator  posted to alt.sources
Date: 28 Jan 93 05:18:54 GMT
Reply-To: davis@ee.rochester.edu
Organization: Huh?

"ACS" (Al's circuit simulator) has been posted to alt.sources.

ACS is a general purpose mixed analog and digital circuit simulator.  It  
performs nonlinear dc and transient analyses, fourier analysis, and ac  
analysis linearized at an operating point.  It is fully interactive and  
command driven.  It can also be run in batch mode.  The output is produced  
as it simulates.  Spice compatible models for the MOSFET (level 2) and  
diode are included in this release.  Other models (MOSFET levels 1 and 3  
and BJT) are in the testing phase.

Since it is fully interactive, it is possible to make changes and  
re-simulate quickly.  The traditional batch approach of repeat(edit,  
simulate, wait) is a thing of the past.  This makes ACS ideal for  
experimenting with circuits as you might do in an iterative design or  
testing design principles as you might do in a course on circuits.

In batch mode it is mostly Spice compatible, so it is often possible to  
use the same file for both ACS and Spice.

The analog simulation is based on traditional nodal analysis with  
iteration by Newton's method and LU decomposition.  An event queue and  
incremental matrix update speed up the solution considerably for large  
circuits and provide most of the benefits of relaxation methods but  
without the drawbacks.

It also has digital devices, so it is a gate level logic simulator.  The  
digital devices may be implemented as either analog subcircuits or as true  
digital models.  The simulator will automatically determine which to use.  
Networks of digital devices are simulated as digital, with no conversions  
to analog between gates.  This results in digital circuits being simulated  
faster than on a typical analog simulator, even with behavioral models.

ACS also has a simple behavioral modeling language that allows simple  
behavioral descriptions of most components including capacitors and  
inductors.

ACS is an ongoing research project.  It is being released in a preliminary  
phase in hopes that it will be useful and that others will use it as a  
thrust or base for their research.  It may be copied as per the GNU  
General Public License.

ACS is available from a dial-up 716-272-1645.  Login as "guest".  Type  
"help" for a list of commands.

I plan to put it on an anon ftp site soon.  Details!.

al.
Newsgroups: comp.lsi