HDTenEightyP/NetNews huggingface dataset:
From: ajayshah@almaak.usc.edu (Ajay Shah)
Newsgroups: comp.arch
Subject: Re: Sales figures on workstation vendors?
Date: 24 Jan 1993 19:31:33 -0800
Organization: University of Southern California, Los Angeles, CA
NNTP-Posting-Host: almaak.usc.edu

rsrodger@wam.umd.edu (Yamanari) writes:

>	Can anyone give me (or tell me where I might find) the figures
>	on workstations sold for Sun, HP, IBM, NeXT, Dec and Data General?

Sorry, does not quite address your question, but this is one of the
few bits of data I have:

From Unix World, Jan 1993

World computer market share (%)
-------------------------------

                                1991            1996

DOS, Windows, Netware           37.0            40.0
Unix                            11.6            21.0
IBM Mainframe                   17.4            14.4
VAX/VMS                          3.7             2.6
IBM minis                        4.1             4.0
Macintosh                        3.6             4.6
Other                           22.6            13.4

Totally                         $155e9

1996 projections are by IDC


1993 Unix hardware sales
------------------------

                        Units           $billion        installed-base

Workstations            876k            14.1            2.755e6
Midrange                583k             7.4            0.931e6
Large-scale             223              1.8            673
PC Unix                 425k             0.6            1.813e6

Total                   1.46e6          23.9e9          6.535e6

Source: ITG
(Interesting to note $24 billion is sortof consistent with the previous
table).
-- 
Ajay Shah, (213)749-8133, ajayshah@rcf.usc.edu
Newsgroups: comp.arch
From: preston@dawn.cs.rice.edu (Preston Briggs)
Subject: Re: Control TO Data Dependence
Keywords: Control Dependence, Data Dependence, High-Level Synthesis
Organization: Rice University, Houston
Date: Sat, 23 Jan 1993 01:23:06 GMT

lka@lems17lems.brown.edu (Lalit K. Agarwal) writes:
>Has anyone played with converting CONTROL-DEPENDENCE to
>DATA-DEPENDENCE in High-Level-Synthesis or come across any algorithm
>for doing it in the literature.?  All suggestions are highly welcome.

I'm not sure what you mean by "high-level synthesis."
In vectorizing compilers, lots of people use "if conversion".
A paper is

  title="Conversion of Control Dependence to Data Dependence",
  author="J. R. Allen and Ken Kennedy and Carrie Porterfield and Joe Warren",
  pages="177--189",
  booktitle=popl10,
  year=1983,
  month=jan

where popl10 is proceedings of the Principles of Programming Languages
conference.

Preston Briggs
Newsgroups: comp.arch
From: pas@jupitercmc.ca (Peter Stokes)
Subject: Re: Want Sun 2000 info
Reply-To: pas@jupiter.ic.cmc.ca
Organization: Canadian Microelectronics Corporation
Date: Fri, 22 Jan 1993 20:02:22 GMT

In article <LIMES.93Jan21170255@straylight.eng.sun.com>, limes@straylight.eng.sun.com (Greg Limes) writes:
|> In article <1993Jan19.212026.11480@venus.ic.cmc.ca> pas@jupitercmc.ca (Peter Stokes) writes:
|> 
|> |   Hi.  I'm looking for technical (read non-sales) info
|> |   on the Sun 2000 machine.   I'm looking for a description
|> |   of the architecture, including processor and memory 
|> |   organization, the new Sun bus (whatever its called) and
|> |   the like. 
|> 
|> Wander over to ftp.uu.net:/systems/sun/papers/SunPerfOv+references
|> via anonymous ftp, lots of good stuff there. In particular, the
|> directory "SPARCcenter2000_Arch.Z-split" probably has what you want.
|> 
|> I'm just starting to read it myself, but so far it looks like it
|> has quite a bit of good solid detail.
|> --
|>    Greg Limes						

Thanks to all for the pointers.   I yanked the stuff and
printed it.   Not a bad start.  Good solid detail is pushing
it though.   I would still like some pointers to more in-
depth info.   Something in between a Sun white paper and 
a research paper.   An example is the IBM paperback book:

   RISC System/6000 Technology

This kind of material but for the Sun 2000 would be ideal.

Cheers,
Peter

Peter A. Stokes ___________________________________ Voice: (613) 545-2923
Engineering Applications Support                      Fax: (613) 548-8104
Canadian Microelectronics Corporation        Email: pas@jupiter.ic.cmc.ca
Kingston, Ontario, Canada _______________________________________________
From: gss@ilx018.intel.com (Shavit Amir)
Newsgroups: comp.arch
Subject: Re: Machines with cond. assignment instruction?
Date: 25 Jan 93 08:24:32 GMT
Organization: Intel Israel (74) Ltd.
NNTP-Posting-Host: ilx061.intel.com
X-Newsreader: TIN [version 1.1 PL8]

Pradeep Dubey (pradeep@watson.ibm.com) wrote:
: Hello Everyone,
: Are there announced machines (specially micros) with
: some conditional assignment instruction.  I mean
: instruction such as the following:

: MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */

: where, c1 refers to some result of some previous compare.

: Any pointers to such machines or any quantitative evaluation
: of usefulness of this instruction in the specific context
: of some machine would be appreciated.

: Thanks,
: Pradeep

The above instruction is a 4 operand instruction, as the condition code is
another implicit source operand. The best way to perform a conditional move
is to have compares set or clear all the bits in a register.
Once that is done, conditional moves are simple.

AND R1, R2 -> R4    /* R1 containes the condition code */
ANDNOT R1,R3 -> R4


Gad
From: aro@aber.ac.uk (Andrew Ormsby)
Newsgroups: comp.arch
Subject: Re: ANDF bogosity
Date: 25 Jan 93 12:18:04 GMT
	<1378@taniwha.UUCP> <1993Jan20.120919.14235@infodev.cam.ac.uk>
Reply-To: aro@aber.ac.uk (Andrew Ormsby)
Organization: CS Dept, University of Wales, Aberystwyth

In article <1993Jan20.120919.14235@infodev.cam.ac.uk> rf@cl.cam.ac.uk (Robin Fairbairns) writes:

   In article <1378@taniwha.UUCP>, paul@taniwha.UUCP (Paul Campbell) writes:
   |> In article <1993Jan15.101326.27072@infodev.cam.ac.uk> rf@cl.cam.ac.uk (Robin Fairbairns) writes:
   |>  
   |> >|> Heck, maybe we could throw in calls to encrypt and decrypt...
   |> 
   |> >(which is only currently legally available within the USA, or from
   |> >free, formally unmaintained, sources outside)
   |> 
   |> Name one country where calling encrypt or decrypt is illegal, or where
   |> it's against the law to sell code containing them .... :-)

   ... and so on

   The fact of the matter is that US computer manufacturers don't make
   their implementations of crypt and decrypt available to the likes of
   us here in the UK. 

And you can get a better idea of the picture by FTP-ing to
gatekeeper.pa.dec.com, where you will find the following informative
message:

Script started on Mon Jan 25 12:13:44 1993

ftp> open gatekeeper.pa.dec.com
Connected to gatekeeper.dec.com.
220- *** /etc/motd.ftp ***
     Gatekeeper.DEC.COM is an unsupported service of DEC Corporate Research.
     Use entirely at your own risk - no warranty is expressed or implied.
     Complaints and questions should be sent to <gw-archives@pa.dec.com>.
     
     EXPORT CONTROL NOTE: Non-U.S. ftp users are required by law to follow U.S.
     export control restrictions, which means that if you see some DES or
     otherwise controlled software here, you should not grab it.  Look at
     00README.export-control (in every directory, more or less) to learn more.
     (If your the treaty between your country and the United States did not
     require you to respect U.S. export control restrictions, then you would
     not have Internet connectivity to this host.  Check with your U.S. embassy
     if you want to verify this.)
     
etc...

--
Andrew Ormsby	 AI & Robotics Research Group, Department of Computer Science,
aro@aber.ac.uk   University of Wales, Aberystwyth, SY23 3DB, UK.
Newsgroups: comp.arch
From: eoahmad@ntuix.ntu.ac.sg (Othman Ahmad)
Subject: PCs need ZERO space
Organization: Nanyang Technological University - Singapore
X-Newsreader: TIN [version 1.1 PL8]
Date: Thu, 28 Jan 1993 04:13:15 GMT

This is in response to the Amdhal mainframe debate.
Please note that the mainframes need terminals which can be huge. The PCs do
not take up much space and can be positioned such that it does not take up
any more desktop space so if we were to take out the terminal consideration
from the mainframes, then PCs need no room space at all.
	I thought this is obvious and could be the reason for the demise of
mainframes. Customers know best.


--
Othman bin Ahmad, School of EEE,
Nanyang Technological University, Singapore 2263.
Internet Email: eoahmad@ntuix.ntu.ac.sg
Bitnet Email: eoahmad@ntuvax.bitnet
From: pnevmati@milhouse.cs.wisc.edu (Dionisios N. Pnevmatikatos)
Newsgroups: comp.arch
Subject: Re: ANDF bogosity
Date: 21 Jan 93 20:27:14 GMT
Organization: U of Wisconsin Madison - Computer Sciences

barnett@convex.com (Paul Barnett) writes:

>In <1993Jan20.120919.14235@infodev.cam.ac.uk> rf@cl.cam.ac.uk (Robin Fairbairns) writes:

>DES and almost every other commercial encryption/description software
>that is worth anything is on the US's list of "controlled export
>items".  In other words, DEC, IBM, Microsoft, etc. can't (legally)
>sell these products outside the US.

OK, but I can (have actually) get DES from Australia (or anywhere in
Europe), and then I can give/sell it whereever I want. What keeps all
these companies from doing exactly that? (either here in the US or in
their abroad offices?)

>--
>Paul Barnett
>MPP OS Development     (214)-497-4846
>Convex Computer Corp.  Richardson, TX

Dionisis
-- 
  -- Dionisis
%
% Dionisios N. Pnevmatikatos      Email: pnevmati@cs.wisc.edu
% Computer Sciences Department    Phone: (1) 608/262 1721,(1) 608/255 0840
% University of Wisconsin-Madison Fax  : (1) 608/262 9777
%
/M{moveto 0 rlineto}def(PAAPACKFGMDEMDICAECAFCAHCAICDFCDHJPUUAAB){65 sub}
forall setrgbcolor scale translate M M M M M M M M M M M stroke showpage
-- 
  -- Dionisis
%
% Dionisios N. Pnevmatikatos      Email: pnevmati@cs.wisc.edu
% Computer Sciences Department    Phone: (1) 608/262 1721,(1) 608/255 0840
% University of Wisconsin-Madison Fax  : (1) 608/262 9777
%
/M{moveto 0 rlineto}def(PAAPACKFGMDEMDICAECAFCAHCAICDFCDHJPUUAAB){65 sub}
forall setrgbcolor scale translate M M M M M M M M M M M stroke showpage
From: vamsee@abgen.tamu.edu (Vamsee Lakamsani)
Newsgroups: comp.arch
Subject: SPEC
Date: 21 Jan 1993 06:46:09 GMT
Organization: Center for Macromolecular Design, Texas A&M University.
Distribution: world
NNTP-Posting-Host: abgen.tamu.edu

Cybenko and Kuck in their article "Revolution or evolution?"
in Spectrum Sept.'92 pp:41 co:3 expand SPEC as Simulation
of Propulsion Engine cycle. Whereas David Patterson and 
J. Hennesey in their book "Computer Arch. - A Quantitative
Survey" index I23 expand it as System Performace Evaluation
Cooperative. What does SPEC stand for ? 

Thanks


Newsgroups: comp.arch,comp.sys.hp
From: sieler@shell.portal.com (Stan Sieler)
Subject: Re: HP-PA softw. virtual addr. translation HOW ?
Followup-To: comp.arch,comp.sys.hp
Organization: Portal Communications Company
X-Newsreader: TIN [version 1.1 PL7]
Date: Thu, 28 Jan 1993 07:05:31 GMT

Andre' Zehl (crusoe@cs.tu-berlin.de) wrote:
: I'm working on a preparation on the HP-PA RISC Architecture.I'm desparately
: trying to figure out, how you administer the virtual to physical address
: translation. 
... 
: The physical page number (ppn) is identical with the index from the
:hashtable. But this only makes sense, if it's not the virtual page number (vpn)
: which is hashed, but the physical page number, coming out of the
: hardware translation? IS THIS SO ? Is the PDIR Index of the hashtable vpn 
the VPN is hashed.
: the hashed ppn or the hashed ?

Each entry in the hash table points to the FIRST PPN in a linked list of all
physical pages whose VPN hash to the same value.  Thus, you walk
the linked list in the PDIR, examining each entry to see if its VPN matches
the one you are looking for (presumably, the one you got a TLB miss on).
If a match is found, you found it! (And the physical address is
the PPN (which is based on the PDIR index as you noticed) plus the original
bottom 11 or so bits (i.e.: virtual pages are aligned on physical page
boundaries).

(I emailed a little more to him)

--
Stan Sieler
sieler@allegro.com
Newsgroups: comp.arch
From: veijalai@klaava.Helsinki.FI (Tony Veijalainen)
Subject: Idea on super fast memory system
Organization: University of Helsinki
X-Newsreader: TIN [version 1.1 PL6]
Date: Wed, 27 Jan 1993 09:52:49 GMT

Conventionally memory has been implemented in one hole block of address
decoded ramchips and bus. The continuous bandwidth of memory chip is
however limited and can't supply memory fast enough for fast processor
without expensive cache systems.

Nowadays we are reading the news of 64 Mbit RAM chip implementations
etc. The memory bandwidth is however still very limited. So how could it
be speeded up.

1) direct mapped cache on memory chip itself and very wide or multiple
paths from memory cells to output pins.

COMMENT: This is quite obvious way, but I have not info about the
economics of this kind of thing. So please give info: how costly is say
256 bit wide buss inside chip in number of memory cells? How about
having four segments each with 64 bit path of access (possibly no sense
because there mayby is no advantage otherwise than lower chip count
compared to using four chips) ? How about massively parallel arrangement
with say 1024 parts of chip with each having its very small direct
mapped cache?

2) Having multiple memory segments with own memory buss mapping
consecutive memory addresses in interleave scheme to different memory
systems.  So with n segments we have refense to same segment only every
nth cycle in typicall case. Say we have 200 MHz processor and 50 memory
systems, then we have typical address frequency of 4 MHz per block, like
in my Acorn Archimedes A310 which uses 4 MHz clock, but uses burst mode
in 8 MHz. If we offsett the memorysystems to operate in different 200
Mhz cycles (1st block cycles 0,50,100,150, 2nd 1,51,101,151 or any fifty
spaced partition of cycle numbers which ever allocation seemed
sensible) and combine them in processor we get agregate bandwidth 200
MHz practically allway. As long as we keep signals from memory systems
short enough i.e. 1/200MHZ long, it would seem to me that there should
be no problem in having memory system match or eaven exceed any given
clock frequency. Where has these kind of memory system implemented and
why have I not heared of them? Actually massively parallel computer is
quite similar to this kind of memory architecture.
-- 
Tony Veijalainen	e-Mail: Tony.Veijalainen@helsinki.fi (preferred)
 		(finger veijalai@cc.helsinki.fi for more information)

Newsgroups: comp.arch,comp.lsi,comp.lsi.cad,sci.electronics
From: tonyb@sequoia.btv.ibm.com (Anthony R. Bonaccio/557822)
Subject: Re: Good and Recent VLSI books
Date: Thu, 28 Jan 93 13:52:39 GMT
Reply-To: U7410@BTVLABVM.VNET.IBM.COM
Organization: IBM Technology Products, Burlington, VT.

In article <1993Jan27.232024.2494@hplabsz.hpl.hp.com>, kjchang@hplabsz.hpl.hp.com (K. J. Chang) writes:
|> Looking for good and up-to-date books on VLSI Designs.
|> 
  ... 

|> I do not think the material in them are up-to-date,
|> especially BiCMOS. Furthermore, I do not think any
|> of the first three have 2nd edition. Am I right?
|> 

A must have for anyone doing any kind of circuit design has JUST been
updated:  Analysis and Design of ANALOG INTEGRATED CIRCUITS, by Gray and 
Meyer.  ISBN is 0-471-57495-3.  They've improved the integration of BiCMOS
design and included a fair amount of real-world SPICE exercises.  This one 
continues to be a bible as far as I'm concerned. 

Drs. Gray and Meyer - if you're watching, thanks for a great piece of work.

-- 
Tony Bonaccio 				IBM Technology Products 
Analog IC Design			Burlington, VT.
Newsgroups: comp.arch
From: steved@lion.inmos.co.uk (Stephen Doyle)
Subject: Re: faster internal clocks
Organization: INMOS Limited, Bristol, UK
Date: Wed, 27 Jan 1993 09:33:47 GMT

In article <1993Jan26.091719.17577@irisa.fr> mcconnel@irisa.fr (Roderick McConnell) writes:
>
>  How are faster internal clocks for CPU's typically generated?  I am
>wondering about processors such as the transputer, where the internal
>clock is a significant multiple of the external clock.  The external
>clock speed can not be varied (for the transputer at least), so my
>first guess is that there is a PLL inside - but wouldn't that require
>analog circuitry?
>-- 
>					- Roderick

You're quite right about the transputer using PLL's to increase clock speed,
these are implemented in CMOS and internally increase frequency to support
up to 30MHz clock cycle and 5x oversampling of the 20Mbit/sec links -
the clock input supplied to the transputer must be 5MHz.

Steve

Steve Doyle, Software Marketing, INMOS Ltd   | Tel +44 454 616616
1000 Aztec West                              | 
Almondsbury                                  | UK: steved@inmos.co.uk
Bristol BS12 4SQ, UK                         | US: steved@inmos.com
From: tal@plts.uucp (Tom Limoncelli)
Newsgroups: comp.arch
Subject: Re: Want Sun 2000 info
Date: 23 Jan 1993 14:05:18 -0500
Organization: P.L.T.S., North Plainfield, New Jersey, USA
NNTP-Posting-Host: plts.uucp

In <1993Jan19.212026.11480@venus.ic.cmc.ca> pas@jupitercmc.ca (Peter Stokes) writes:

>Hi.  I'm looking for technical (read non-sales) info
>on the Sun 2000 machine.   I'm looking for a description
>of the architecture, including processor and memory 
>organization, the new Sun bus (whatever its called) and
>the like.    Info on the implementation of Unix for this
>architecture might also be of interest.   Does anyone 
>know where I can get this info?    Some papers from a 
>conference or similar would be ideal.    

I'm still taking bets on (1) if it ships in Q2 1993, and (2)
if they drop the Vikings out of it by Q1 1994.

Tom
-- 
Tom Limoncelli -- tal@plts.uucp (home) -- tal@warren.mentorg.com (work)
Moderator of ne-social-motss and the Drew University Alumni/ae mailing lists.
"There is nothing wrong with America that cannot be cured by what is
right with America." --Bill Clinton's inaugural address, 1/20/93
Newsgroups: comp.arch
From: preston@dawn.cs.rice.edu (Preston Briggs)
Subject: Re: SPEC
Organization: Rice University, Houston
Date: Thu, 21 Jan 1993 16:56:36 GMT

vamsee@abgen.tamu.edu (Vamsee Lakamsani) writes:

>Cybenko and Kuck in their article "Revolution or evolution?"
>in Spectrum Sept.'92 pp:41 co:3 expand SPEC as Simulation
>of Propulsion Engine cycle. Whereas David Patterson and 
>J. Hennesey in their book "Computer Arch. - A Quantitative
>Survey" index I23 expand it as System Performace Evaluation
>Cooperative.

Different beasts.  The SPEC program is part of the Perfect Club
benchmark suite.  The SPEC benchmark suite is a collection of Fortran
and C applications.

Preston Briggs
From: andrey@cco.caltech.edu (Andre T. Yew)
Newsgroups: comp.arch
Subject: How is TFP so fast?
Date: 28 Jan 1993 03:04:51 GMT
Organization: California Institute of Technology, Pasadena
NNTP-Posting-Host: punisher.caltech.edu


	Can someone say how SGI achieved its 300 MFLOPS/chip
rate in the TFP?  Is it too much to hope that it's
asynchronous (ala micropipelines)?

--Andre

-- 
             Andre Yew andrey@cco.caltech.edu (131.215.139.2)
Newsgroups: comp.arch,comp.compilers,comp.misc,comp.programming
From: horst@techfak.uni-bielefeld.de (Horst Hogenkamp)
Subject: Re: Machines with cond. assignment instruction?
Date: Fri, 22 Jan 1993 08:28:12 GMT
Organization: Universitaet Bielefeld, Technische Fakultaet.

In article <1993Jan21.163607.31684@watson.ibm.com>, pradeep@watson.ibm.com (Pradeep Dubey) writes:
> Are there announced machines (specially micros) with
> some conditional assignment instruction.  I mean
> instruction such as the following:
> 
> MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */
> 
> where, c1 refers to some result of some previous compare.


As far as I know the definition of the SPARC architecture
includes conditional moves from version 9 on.
                                ---------

Horst Hogenkamp
.
Newsgroups: comp.arch
From: lka@lems17lems.brown.edu (Lalit K. Agarwal)
Subject: Control TO Data Dependence
Keywords: Control Dependence, Data Dependence, High-Level Synthesis
Organization: Laboratory for Engineering Man/Machine Systems
Date: Sat, 23 Jan 1993 00:35:31 GMT

Has anyone played with converting CONTROL-DEPENDENCE to DATA-DEPENDENCE in
High-Level-Synthesis or come across any algorithm for doing it in the literature.?
All suggestions are highly welcome.

thanks,

Lalit K. Agarwal (lka@lems.brown.edu)
Dept. of Computer Engg.
Brown University,
Providence, RI-02912



Newsgroups: comp.arch
From: tdbear@dvorak.amd.com (Thomas D. Barrett)
Subject: Power OPEN Computing Organization: Contact?
Organization: Advanced Micro Devices, Inc.; Austin, Texas
Distribution: usa
Date: Thu, 21 Jan 93 16:37:56 GMT

Can someone give me contact information for joining the Power Open
Computing Organization (schedule for April)?

Also, a source for the PowerPC 61 specs?

Please email and I will repost the info.

Thanks,
Tom
-- 
|Tom Barrett (TDBear), Sr. Engineer|tom.barrett@amd.com|v:512-462-6856 |
|AMD PCD MS-520 | 5900 E. Ben White|Austin, TX  78741  |f:512-462-5155 |
|"No is yes, And we're all free" ---Tracy Chapman, "Why?"              |
|My views are my own and may not be the same as the company of origin  |
Newsgroups: comp.arch,comp.parallel
From: ugurdag@ces.cwru.edu (Fatih Ugurdag)
Subject: ASPLOS conference
Organization: Computer Engineering and Science, Case Western Reserve University
Date: 26 Jan 1993 07:02:16 GMT



Does anybody out there have any info about the ASPLOS Conference?

If possible, can you post its notice in this newsgroup?

Thanx in advance.
-- 
Fatih Ugurdag
Case Western Reserve University
From: jrexford@adirondacks.eecs.umich.edu (Jennifer Lynn Rexford)
Newsgroups: comp.arch
Subject: Non-uniform traffic in message-passing systems
Date: 27 Jan 93 20:46:25 GMT
Organization: University of Michigan EECS Dept., Ann Arbor, MI


   Does anyone know of any papers that characterize realistic
communication patterns in message-passing systems? In particular,
how often are various communication constructs (such as many-to-one,
one-to-many, and others) used over a wide range of applications?
 
   I am looking at non-uniform traffic patterns on point-to-point,
message-passing networks (such as k-ary n-cubes).  The shared-memory
community has models of non-uniform traffic in terms of a ``hot-spot''
memory, that can cause congestion trees in multistage interconnection
networks.  It seems that a ``hot'' node (or set of nodes) in a message
passing environment (or a distributed shared memory environment) would
be analogous.
 
   Any thoughts/references?
 
   I do have one reference ("Hot-Spot Contention in Binary Hypercube
Networks," by Dandamudi and Eager, IEEE TOC, Feb. 1992, pp. 239-244).
 
   Thanks.
 
-- Jennifer
   jrexford@eecs.umich.edu
Newsgroups: comp.arch,comp.lsi,comp.lsi.cad,sci.electronics
From: kjchang@hplabsz.hpl.hp.com (K. J. Chang)
Subject: Good and Recent VLSI books
Date: Wed, 27 Jan 1993 23:20:24 GMT
Organization: Hewlett-Packard Laboratories Palo Alto,CA

Looking for good and up-to-date books on VLSI Designs.

I have the following four books on VLSI designs:
1. Mead and Conway (1980)
2. Weste and Dobberpuhl (1985)
3. Glasser and Eshraghian (1985)
4. Pucknell and Eshraghian (1988) 2nd edition

I do not think the material in them are up-to-date,
especially BiCMOS. Furthermore, I do not think any
of the first three have 2nd edition. Am I right?

Thanks for your attention,

-- 
K J Chang, Hewlett-Packard ICBD R & D,                      (())_-_(())
Palo Alto, CA 94304                                          | (* *) | 
Internet: kjchang@hpl.hp.com           a UCLA Bruin  -->    {  \_@_/  }
voice mail: (415)857-4604                                     `-----'