HDTenEightyP/NetNews huggingface dataset:
From: jmueller@fzi.DE (Jens Mueller)
Subject: Re: Subset of VHDL for synthesis.
Reply-To: fzi.de
Organization: Forschungszentrum Informatik (FZI), Karlsruhe, Germany
Date: Tue, 10 Nov 1992 13:16:38 GMT

|> 
|> Dear all,
|> 
|> I would like to know the present state regarding a formal definition
|> for a subset of VHDL aiming at synthesis.
|> 
|> I believe there is a group (VHDL Synthesis Working Group in Europe???) that
|> is trying to specify this subset.
|>
|> Does anybody know how I can get info on this subject?
|> 
|> Thanks a lot,
|> 
|> Meyer.
|> 



Indeed, there is a VHDL Synthesis Working Group in Europe.
The group, supported by an ESPRIT project ECIP92, is chaired
by Wolfgang Ecker.
You can get information about this group in the proceedings
of the EuroDAC/EuroVHDL 92 or you can contact Wolfgang Ecker
(fax ++49-89 636 44950, E-mail: ecker@nixe.zfe.siemens.de).

I hope this helps.

Jens

+------------------------------------+-----------------------------------+
| Jens Mueller                       |                                   |
| Automation of Circuit Design       |                                   |
| Forschungszentrum Informatik (FZI) |     o                             |
| Haid-und-Neu-Str. 10-14            |   --<(-----                       |
| W-7500 Karlsruhe, Germany          |     [\                            |
| Tel.: (++49)|(0)-(721)-9654-452    |        ...sitting at synthi's bar |
| Fax.: (++49)|(0)-(721)-9654-459    |                                   |
| email: jmueller@fzi.de             |                                   |
| IRC: synthi  channel #tuebingen    |                                   |
+------------------------------------+-----------------------------------+
From: M.Nigri@cs.ucl.ac.uk (Meyer E. Nigri)
Newsgroups: comp.lang.vhdl
Subject: Subset of VHDL for synthesis.
Date: 9 Nov 92 12:27:16 GMT


Dear all,

I would like to know the present state regarding a formal definition
for a subset of VHDL aiming at synthesis.

I believe there is a group (VHDL Synthesis Working Group in Europe???) that
is trying to specify this subset.

Does anybody know how I can get info on this subject?

Thanks a lot,

Meyer.

PS: I will summarise to the group the responses I get on this
+--------------------------+-----------------------------------------------+
|Meyer Elias Nigri         |   JANET:mnigri@uk.ac.ucl.cs                   |
|Dept. of Computer Science |  BITNET:mnigri%uk.ac.ucl.cs@UKACRL            |
|University College London |Internet:mnigri%cs.ucl.ac.uk@nsfnet-relay.ac.uk|
|Gower Street              | ARPANet:mnigri@cs.ucl.ac.uk                   |
|London WC1E 6BT           |    UUCP:...!mcvax!ukc!ucl-cs!mnigri           |
+--------------------------+-------------------------+---------------------+
|Tel: +44 71 387-7050      | Fax: +44 71 387-1397    |    Telex: 28722     |
|                 ext. 3708|                         |                     |
+--------------------------+-------------------------+---------------------+
From: rimen@ce.chalmers.se (Marcus Rimen)
Newsgroups: comp.lang.vhdl
Subject: VHDL grammar ?
Keywords: VHDL grammar
Date: 12 Nov 92 11:35:21 GMT
Organization: Chalmers Univ. of Technology, Dept. of Comp. Eng., Gothenburg, Sweden

Does anybody out there know of a public-domain VHDL grammar (input for yacc or bison)?

The grammar does not have to be complete. I want to use it to extract a list of
every signal and their types in a VHDL description. I also want to extract a list
of all component instances.

Any pointers are welcome! Please send email to rimen@ce.chalmers.se

Thanks.
From: jdsb@egr.duke.edu (J. D. S. Babcock)
Newsgroups: comp.lang.vhdl
Subject: VHDL modules wanted/available for system reusability research.
Summary: Rapid System Prototyping Through Increased Subsystem Reusability
Keywords: vhdl VHDL subsystems system
Date: 12 Nov 92 22:01:33 GMT
Distribution: na
Organization: Duke University EE Dept.; Durham, NC

Brief Overview:
* Duke University is looking for well documented VHDL module designs for
  inclusion in a database of VHDL modules for subsystem reusability.
* We welcome request lists from users who would like to use our
  libraries.
* A module library will be made available around May, 1993, for new system
  development.

     Rapid System Prototyping Through Increased Subsystem Reusability

   In a research project at Duke University we are studying the development,
collection, and distribution in machine form of subsystem designs. The intent
is to facilitate rapid system prototyping through reuse of existing subsystems.
We are largely using the Viewlogic tools, but all our work aims at vendor 
independent, maintainable, usable libraries. Currently we are using VHDL toward
that end, with additional representations and formats for different levels of
abstraction (netlist, physical design, etc.).  The project is more than a 
library development and aims at the usage methodology, CAD tools, as well as
the actual existence of subsystem libraries.

   Therefore, we welcome contributions of VHDL modules for subsystems which
meet the following criteria:
   1. They are characterized and are known to work,
   2. They are non-proprietary and can be distributed free of charge to all
      interested parties, and,
   3. Are properly documented.

   We are working on standardized formats for contributions and distribution,
but at this stage we want to interact with as many sites as possible, towards
the end of establishing some contacts.

   We also welcome request lists from users who would like to use our
libraries.  In the spring of 1993 the existing libraries will be used and
augmented by students in a rapid system prototyping course at Duke, and
we hope that a reasonably robust (but still small) library will be available
for distribution by May, 1993.

   All inquiries/suggestions/comments are welcome. 

Please respond to: J. D. Sterling Babcock (jdsb@ee.egr.duke.edu)

Principal Investigator: Apostolos Dollas
Graduate Research Asst: J. D. Sterling Babcock
-------------------------------------------------------------------------
J. D. Sterling Babcock             Duke University Electrical Engineering
jdsb@ee.egr.duke.edu
Newsgroups: comp.lang.vhdl
From: emmel@pslu1.psl.wisc.edu (Grant Emmel)
Subject: Re: Are there pub-domain VHDL compilers?
Organization: Physical Sciences Lab, University of Wisconsin
Distribution: comp
Date: Thu, 12 Nov 92 18:15:35 GMT

In article <DAVE.92Nov11174608@gctgw.gctech.co.jp> dave@gctech.co.jp (Dave) writes:
>Are there public domain VHDL compilers?
>
>When I'm hacking out a new bus protocol, I usually use a tiny C package I
>wrote that inputs and outputs activities on nodes in a "Logio" format that
>looks something like this:
>

text based timing diagram deleted...

>... and so on.  This format is easy to display and debug with a simple
>text-based display program.  Thus I can throw together stuff no matter
>where I am, without resorting to a pencil (which I don't remember how to
>use) and in spite of the fact that I'm too poor to buy a CAD tool.  But I
>do wish that I could use VHDL instead of C.
>
>Does anything like this exist?
>
>Dave
>
>

Ditto.  I'd like to know also.

-- 

------------------------------------------------------------------------
Grant Emmel,  Physical Sciences Laboratory University of Wisconsin
Internet:emmel@psl.wisc.edu.                              608-873-6651
Newsgroups: comp.lang.vhdl,comp.lang.verilog,comp.sys.super
From: dank@blacks.jpl.nasa.gov (Daniel R. Kegel)
Subject: HDL models or driver chips for HIPPI, anyone?
Organization: Image Analysis Systems Group, JPL
Date: Thu, 5 Nov 1992 20:09:44 GMT

Hi,
we're considering using HIPPI to connect several custom-built
signal processing boards together.  Has anyone out there written
functional models in Verilog or VHDL for the HIPPI physical layer?

Also, does anyone know of good line driver/receiver chips for HIPPI?
I'd be interested in hex or octal chips; the only chips I remember offhand 
are the 10116 triple line receivers etc., which aren't very dense.
It would be especially nice if the drivers/receivers also included
level shifters to translate from HIPPI's ECL levels to CMOS levels that
can be used with FPGA's.

Please respond to dank@blacks.jpl.nasa.gov.
I will summarize any replies.
Thanks!
   Dan Kegel
Newsgroups: comp.lang.vhdl
From: dave@gctech.co.jp (Dave)
Subject: Are there pub-domain VHDL compilers?
Organization: GC Technology
Distribution: comp
Date: Wed, 11 Nov 1992 08:46:08 GMT

Are there public domain VHDL compilers?

When I'm hacking out a new bus protocol, I usually use a tiny C package I
wrote that inputs and outputs activities on nodes in a "Logio" format that
looks something like this:

Sequence: D Flip Flop
Time:	0.0
D:	0
!RST:	1
CLK:	0
Time:	1.0
CLK:	1
Time:	1.1
Q:	0
!Q:	1
Time:	2.0
CLK:	0
D:	1
Time:	3.0
CLK:	1
Time:	3.1
Q:	1
!Q:	0

... and so on.  This format is easy to display and debug with a simple
text-based display program.  Thus I can throw together stuff no matter
where I am, without resorting to a pencil (which I don't remember how to
use) and in spite of the fact that I'm too poor to buy a CAD tool.  But I
do wish that I could use VHDL instead of C.

Does anything like this exist?

Dave


Newsgroups: comp.lang.vhdl
From: bygate@ncrcol.ColumbiaSC.NCR.COM (Terrence A. Bygate)
Subject: Re: Subset of VHDL for synthesis.
X-Newsreader: Tin 1.1 PL5
Date: Tue, 10 Nov 92 20:38:04 GMT

Meyer E. Nigri (M.Nigri@cs.ucl.ac.uk) wrote:
: 
: I would like to know the present state regarding a formal definition
: for a subset of VHDL aiming at synthesis.
: 
: Meyer.
: 
: |University College London |Internet:mnigri%cs.ucl.ac.uk@nsfnet-relay.ac.uk|

The primary problem with defining a subset is that the target is
always moving.  At best, the subset would be valid six months, depending
on which synthesis tool you were using.  I have been using Synopsys for 
about 1.5 years, and with each release (and I have been through 3-4 
releases), the synthesis tool is able to read in more and more VHDL 
constructs.

Also, some synthesis tools are starting to be able to do true high level
synthesis.  Albeit very expensive, Silcon1076 from LSI (~ US$256 K per seat),
will read a high level description (ie, a behavioral description without
any implied clocks) and then generate RTL VHDL, which is then fed into
Synopsys.

I am sure it is only a matter of time before other tool vendors will 
offer the same functionality.

Terry.
--
     Terrence A. Bygate    803-791-6492      |   "A problem is nothing but an
    Multiprocessor Systems Business Unit     |   opportunity dressed in work
  NCR Corporation - 3500 Module Development  |   clothes" -borrowed
---------------------------------------------+----------------------------------
  Terrence.Bygate@ColumbiaSC.NCR.COM   ...uunet!ncrlnk!ncrcae!terrence.bygate
Newsgroups: comp.lang.vhdl
From: allison@hal.COM (Dennis Allison)
Newsgroups: comp.lang.verilog
Subject: Verilog lex/yacc grammar
Date: 5 Nov 92 16:45:27 GMT
Organization: HaL Computer Systems, Inc.
NNTP-Posting-Host: sumeru.hal.com

Is there a public domain lex/yacc grammar for the verilog language
available on the net?  
Newsgroups: comp.lang.verilog
From: leung@DSG.Tandem.COM (Steven Leung)
Subject: Re: Avoiding inertial delay in delay lines
Originator: leung@bittemple
Organization: Tandem Computers
Date: Thu, 12 Nov 1992 16:31:16 GMT


smb@afterlife.ncsc.mil (Steve M. Burinsky) writes:

>I need to simulate delay lines in order to model a bus interface.  The
>solution seems obvious --  use a net delay.  However, the signal I need
>to delay has pulse widths (w) which are shorter than the delay time (d);
>that is w < d.  The problem is that inertial delay causes the short pulse
>to disappear within the delay. ...

I think Verilog's stated delay model is inertia, but I found out from my
experiments (with 1.6a) that the non_blocking assignment _plus_ delay 
control after the assignment operator has the same effect of transport delay.
Since I don't know whether either Cadence or OVI has formally stated support
for transport delay model, so I don't know whether this is a (happy) coincident
or there may be some limitations I didn't know or they may change in the
future version or it may not work with another Verilog simulator or ... But 
you can try this:

	a <= #10 b;	/* transport delay */

Steven
-- 
328. Seek opportunity, not security. ...
        - Life's Little Instruction Book by H. J. Brown, Jr.

Newsgroups: comp.lang.verilog
From: smb@afterlife.ncsc.mil (Steve M. Burinsky)
Subject: Avoiding inertial delay in delay lines
Organization: The Great Beyond
Date: Thu, 12 Nov 1992 05:33:06 GMT

I need to simulate delay lines in order to model a bus interface.  The
solution seems obvious --  use a net delay.  However, the signal I need
to delay has pulse widths (w) which are shorter than the delay time (d);
that is w < d.  The problem is that inertial delay causes the short pulse
to disappear within the delay.

So, how should this be implemented?  I have two options, neither of which
I like:
1.  Implement the delay line as a string of (for example) 10 buffers, each
with 10% of the total required delay.  This has drawbacks, as it requires
that the user know the number of internal sub-delay units in order to
guarantee acurate delay generation.  Also, (given that 10 buffers are used)
10w > d is required.
2.  Implement a PLI routine which calls (for example) tf_strdelputp, which
allows me to specify transport (versus inertial) delay.

Is there anyway I can choose transport delay using a standard language
construct?  Is there another (easy, portable, general) way of implementing
delay lines I'm missing?

Thanks,
Steve Burinsky
smb@afterlife.ncsc.mil

-- 

Steve M. Burinsky
smb@afterlife.ncsc.mil
Newsgroups: comp.lang.verilog
From: rajesh@chdasic.sps.mot.com (Rajesh Patil)
Subject: Re: Avoiding inertial delay in delay lines
Reply-To: rajesh@chdasic.sps.mot.com
Organization: Motorola SPS ASIC, Chandler, AZ
Date: Fri, 13 Nov 1992 18:28:38 GMT

smb@afterlife.ncsc.mil (Steve M. Burinsky) writes:

> I need to simulate delay lines in order to model a bus interface.  The
> solution seems obvious --  use a net delay.  However, the signal I need
> to delay has pulse widths (w) which are shorter than the delay time (d);
> that is w < d.  The problem is that inertial delay causes the short pulse
> to disappear within the delay.

If you do not expect to have more than a single pulse (2 edges) every delay time
d units, then you could use the pulse rejection ratio command line switches
to Verilog. I do not have a manual in front of me now to give you the details, 
but it is something like +pulse_r. This will however, change the pulse swallowing
ratio for all delays in the design. If you want control on one specific delay, 
then look into using the specparam based control on pin-to-pin delays. The section
on specify blocks in the manual talks about this.
But the problem we ran into was we needed to run multiple pulses into the
delay line such that n*w < d, where n was the number of pulses. So we should
have seen all the n pulses come out of the delay line after a delay of d.
The switches mentioned above will let you control the width of a pulse that 
will get thru but not the number of pulses. Verilog-Xl will only let you 
schedule at the most 2 events (I believe) on any node. Each new event after the
second one will cause an earlier scheduled event to get overwritten/dropped.
As a result Verilog will show you only the last pulse in the pulse train 
come out of the delay line. For this problem, I believe there is no solution
other than using a string of elements to build the delay line.

---
Rajesh Patil
----------------------------------------------------------------------
Advanced Product Operations                 rajesh@chdasic.sps.mot.com
Motorola ASIC				     ----------------------------------------------------------------------
From: tsai@hal.com (Finnegan T. Tsai)
Newsgroups: comp.lang.verilog
Subject: Wanted: Informations on parallel VHDL/Verilog Simulators
Keywords: parallel processing, VHDL, Verilog, Logic Simulator
Date: 12 Nov 92 23:41:10 GMT
Organization: HaL Computer Systems
NNTP-Posting-Host: molly.hal.com


Hi, Experts


I am trying to gather any informations related to event-driven 
parallel VHDL or Verilog simulators. Would you please help me?
Any clues to papers or academic researches are highly appreciated.



Desperately Finney
From: J.Dzikowski@cs.ucl.ac.uk (Jens-Uwe Dzikowski)
Newsgroups: comp.lang.verilog
Subject: Tasks & Libraries
Date: 5 Nov 92 15:28:22 GMT

Hi verilog experts,

I've got a question:

Is there any possibility to store tasks in libraries?
There seems to bee no related information in the manuals. They only 
talk about modules and UDPs.

Has anyone got another(better) idea how to include large blocks of 
frequent assignments in a modular way without having to pass hundreds
of parameters ?

Thanks

Jens

--------------------------------------------------------------------
Jens-Uwe Dzikowski			
Dept. of Computer Science
University College London	tel. : +44-71-3877050 ext.3701
Gower Street			fax  : +44-71-3871397
London WC1E 6BT 		email: dziko@uk.ac.ucl.cs
--------------------------------------------------------------------
Newsgroups: comp.lang.verilog
From: tsai@hal.com (Finnegan T. Tsai)
Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.parallel
Subject: Wanted: Informations on parallel VHDL/Verilog Simulators
Keywords: parallel processing, VHDL, Verilog, Logic Simulator
Date: 12 Nov 92 19:58:54 GMT
Article-I.D.: hubcap.1992Nov12.200836.8991
Organization: HaL Computer Systems



Hi, Experts


I am trying to gather any informations related to event-driven 
parallel VHDL or Verilog simulators. Would you please help me?
Any clues to papers or academic researches are highly appreciated.



Desperately Finney
From: bjdunlop@shamash.cdc.com (Bruce Dunlop)
Newsgroups: comp.lang.verilog
Subject: 3rd Party Verilog Compilers
Date: 12 Nov 92 21:11:16 GMT
Distribution: usa
Organization: Control Data Systems Inc., Arden Hills, MN


A company called Chronologic Simulation was mentioned as having a fast
verilog compiler, in a previous post here.  Can someone give me their
phone number?

Also, does anyone have any good/bad experiences with it?

********************************************************************
*   Jim Dahlberg		 Computing Devices International   *
*   bjdunlop@shamash.cdc.com		A Ceridian Company         *
********************************************************************
Newsgroups: comp.lang.scheme
From: Alan@lcs.mit.EDU (Alan Bawden)
Subject: case sensitivity
Organization: The Internet
Date: Thu, 12 Nov 1992 21:10:41 GMT

   Date: Fri, 6 Nov 1992 06:23:57 GMT
   From: Daniel Kobler <kobler@informatik.tu-muenchen.de>

       'Wall is claimed to be the same as 'WALL,

   whereas

       (string->symbol "Wall") and (string->symbol "WALL") are different.

   And again my question: why these differences?...

Perhaps it has something to do with the fact that

  'foo;comment

is the same as

  'foo

whereas

  (string->symbol "foo;comment")

and

  (string->symbol "foo")

are different.

`string->symbol' isn't the reader (the thing that constructs Scheme objects
given their printed representations).  The thing you are looking for might
perhaps be called `string->object', but standard scheme doesn't have it.
Perhaps it should.

				- Alan
From: pk@cs.tut.fi (Kellom{ki Pertti)
Newsgroups: comp.lang.scheme
Subject: Re: Code is not portable across case folding methods
Date: 5 Nov 92 14:20:38 GMT
Organization: Tampere Univ. of Technology, Finland.
NNTP-Posting-Host: talitiainen.cs.tut.fi
In-reply-to: gjc@mitech.com's message of 4 Nov 92 18:19:55 GMT

In article <3432@mitech.com> gjc@mitech.com (George J. Carrette) writes:
   I hate to say it guys, but this is already enough
   freedom to blow away code portability, as long
   as a program can call READ at runtime.

I have run into this, but in a different way: I have a Scheme reader
that reads Scheme expressions, and returns a data structure that is
basically the s-expression with information about where in the source
file the expression was. The reader uses string->symbol to make a
symbol out of the string it has read, but for example in sci I get

  (string->symbol "define") => \d\e\f\i\n\e

So, I must prepare for different preferred cases with a kludge (IMHO):

;;;
;;; Are symbols converted to upper case, lower case or not converted?
;;; 

(define *psd-preferred-case*
  (cond ((string=? (symbol->string 'Foo) "foo")
	 'lowercase)
	((string=? (symbol->string 'Foo) "FOO")
	 'uppercase)
	(else 'original-case)))

--
Pertti Kellom\"aki (TeX format)  #       These opinions are mine, 
  Tampere Univ. of TeXnology     #              ALL MINE !
      Software Systems Lab       #  (but go ahead and use them, if you like)
From: pk@cs.tut.fi (Kellom{ki Pertti)
Newsgroups: comp.lang.scheme
Subject: Re: Code is not portable across case folding methods
Date: 6 Nov 92 10:02:16
Organization: Tampere Univ. of Technology, Finland.
Distribution: world
	<1dbqagINN7a2@early-bird.think.com>
NNTP-Posting-Host: talitiainen.cs.tut.fi
In-reply-to: barmar@think.com's message of 5 Nov 92 18:48:48 GMT

In article <1dbqagINN7a2@early-bird.think.com> barmar@think.com (Barry Margolin) writes:
   Unless you're prepared to emulate all the
   features of the reader prior to calling string->symbol, you can lose
   lose.  This is why Common Lisp has READ-FROM-STRING.

In my case, I have to be prepared to do that, because that's what I'm
doing: writing a reader. It would be nice to have read-from-string in
Scheme, though. I can not use plain read, because I want to keep track
of the position (line and column) in the input stream.


--
Pertti Kellom\"aki (TeX format)  #       These opinions are mine, 
  Tampere Univ. of TeXnology     #              ALL MINE !
      Software Systems Lab       #  (but go ahead and use them, if you like)
From: jwkim@ece.arizona.edu (Jinwoo Kim)
Newsgroups: comp.lang.scheme
Subject: Looking for person's email address
Date: 13 Nov 92 16:59:07 GMT
Distribution: usa,local
Organization: U of Arizona Electrical and Computer Engineering

Dear Netters,

Does anyone know the email address of these persons ;

     Sam M. Daniel   or  John B. Zuckerman

     Government Electronics Group
     Artificial Intelligence Laboratory
     Motorola INC.

I appreciate your help in advance.

   
Jinwoo Kim    (Email : jwkim@helios.ece.arizona.edu)
From: mfausett@bbn.com (Mark Fausett)
Newsgroups: comp.lang.scheme
Subject: Re: Scheme for Macintosh & System 7
Date: 6 Nov 92 19:52:53 GMT
NNTP-Posting-Host: kirin.bbn.com

kjdriese@vnet3.vub.ac.be writes:

>If you are looking for a cheaper implementation, Marc Feeley's Gambit
>Scheme 1.9 is for free, if you can FTP and only want an interpreter
>(anonymous ftp to acorn.cs.brandeis.edu   in /pub/gambit )

I just looked; the unix version is there, but the mac version was removed.

mf
Newsgroups: comp.lang.scheme
From: thinman@netcom.com (Technically Sweet)
Subject: Continuations via stack-switching
Organization: International Foundation for Internal Freedom
Date: Fri, 6 Nov 1992 07:08:58 GMT

Has anyone implemented continuations via remapping the
stack address space?  The features implemented in BSD & SunOS
for threads should be useable for continuations also.
The mmap() system call changes the memory underneath
a virtual address, and I think there's a provision for a
separate signal stack?

-- 

Lance Norskog

Data is not information is not knowledge is not wisdom.
Newsgroups: comp.lang.scheme
From: ryan@ux1.cso.uiuc.edu (amy)
Subject: Re: What are good references on learning Scheme
Organization: University of Illinois at Urbana
Date: Fri, 13 Nov 1992 16:09:44 GMT

pmathis@utdallas.edu (Paul J. Mathis) writes:
>What are some good books on Scheme?  I currently have only PC Scheme's
>User's Guide and Reference Manual.  Thanks!

ohoh our professor thinks "Structure and Interpretation of Computer
Programs" by Ablesun (sp?) and Sussman is the scheme equivalent of the 
bible...it's published by MIT Press through McGraw HIll (I think)

anyway...it seems pretty decent...you may want to take a look at it..

   --amy
(ryan@ux1.cso.uiuc.edu)
Newsgroups: comp.lang.scheme