HDTenEightyP/NetNews huggingface dataset:
From: boudjit@rhone.imag.fr (Mokhtar BOUDJIT)
Newsgroups: comp.lsi,comp.lsi.testing
Subject: Information needed
Date: 29 Sep 92 15:07:06 GMT
Organization: IMAG-TIM3/INPG, Grenoble, France



	I would highly appreciate if someone could furnish me with the 
following information:


	- Is there any tool to translate a BLIF or SLIF multi-level
	sequential or combinational formats of the ISCAS benchmark
	circuits in the two-level description in order to use 
	Espresso as this one accepts as input only a two-level 
	description of a boolean function..

	My email address is:

		boudjit@archi.imag.fr
		

	Thank you for your time and help.
From: cindy@zoran.hellnet.org (Cindy Eisner)
Newsgroups: comp.lsi
Subject: zycad logic simulation strange behavior
Keywords: zycad
Date: 5 Oct 92 08:15:08 GMT
Organization: Zoran Microelectronics LTD. Haifa, Israel.

i have the following strange behavior on a full chip simulation:  some of
the ff's (which are modeled using the zycad primitive dffq) go to x (unknown)
in the middle of the clock and then recover before they are needed - i.e.,
the test runs fine, but you have x's all over the waves.  i have not been 
able to recreate this behavior on a small test case.  so:  before i go 
plunging in to debug this - maybe someone has seen this before, or has some
ideas.  what could cause this behavior from the dffq primitive.  btw, the
prebar and clrbar inputs are constant at 1 throughout the simulation.

thanks,

cindy.
-- 

    Cindy Eisner,                     Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: cindy@Zoran.HellNet.Org
    Advanced Technology Center
    Haifa 31204, Israel               Could be my employer doesn't agree.
Xref: sparky comp.lsi:618 comp.lsi.cad:993
From: jgealow@mtl.mit.edu (Jeffrey C. Gealow)
Newsgroups: comp.lsi,comp.lsi.cad
Subject: Calma GDSII Stream format
Date: 4 Oct 92 23:12:53 GMT
Article-I.D.: athena.1992Oct4.231253.4273
Organization: MIT Microsystems Technology Laboratories

I would like to obtain a specification of the Calma GDSII Stream
format.  This format may be used to submit designs to MOSIS.  How may
a specification be obtained?

Jeff Gealow
jgealow@mtl.mit.edu
From: frankp@blade.stack.urc.tue.nl (Frank van de Pol)
Newsgroups: comp.lsi
Subject: Where to get SPICE models ?
Date: 5 Oct 92 13:01:09 GMT
Organization: MCGV Stack, Eindhoven University of Technology, the Netherlands.
X-Newsreader: TIN [version 1.1 PL6]

Hello,

	I'm looking for a mailserver (or ftp-site) to get my SPICE models
and subcircuits from. I guess there should be such a site at some
university. 

I have no access to ftp, so if anybody knows a ftp site, please specify the
directory and filenames. I can then use the ftpmail service.

As I'm not the only one looking for SPICE models, please respond trough the
net.

					Thanks, Frank

========================------------------> 
#define NAME    "Frank van de Pol"     /| :  a typical PC boot sequence: :-(
#define ADDRESS "mgr. Nelislaan 10"   / | :  tick, tick, tick, .(etc)., tick
#define CITY    "4741 AB Hoeven"     /--| :  bhuurrrrrr, bruzzzzzz, pieereep
#define COUNTRY "The Netherlands"   /   | :  doggadoggadoggadoggadogga brrrr
#define EMAIL   "frankp@stack.urc.tue.nl" :  530 kB free memory (of 8MEG???)


Xref: sparky comp.lsi:616 comp.lsi.cad:987 comp.lsi.testing:236 sci.electronics:16474
From: cwagner@ee.ualberta.ca (Chad Wagner)
Subject: Spice Models
Summary: Spice Models
Organization: University Of Alberta, Edmonton Canada
Date: Sat, 3 Oct 1992 00:54:06 GMT


I am looking for models of several devices for Spice.

I am running Spice3c1 but have access to Spice3e2.

What I need is:

	Op-Amps 324,741
	Comparators 339,311
	Transistors 2N4401,2N3904,MPQ2222,2N4403,2N3906,MPQ2907,MPF102
	Diodes 1N914,1N4148,1N4005, 10V and 6V Zener
	Timers 555,556

Any ones help would be greatly appreciated.
Thanks in advance!

Chad G. Wagner
EE Student
University of Alberta, Canada
cwagner@bode.ee.ualberta.ca



Newsgroups: comp.lsi,comp.lsi.cad,comp.lsi.testing,sci.electronics
From: wkt@csadfa.cs.adfa.oz.au (Warren Toomey)
Subject: Wanted: SPICE models for transistors/diodes
Organization: Australian Defence Force Academy, Canberra, Australia
Date: Fri, 2 Oct 1992 04:33:22 GMT

[ Pardon the crosspost - my last post to comp.lsi only got other people
  asking for the same information ]

Does anybody know if there is freely available PSPICE or SPICE 3e2 models
for all types of diodes and transistors, especially ones via anonymous ftp.
I've found some op-amp models available ftp-wise, but no transistors etc.

Any answers very much appreciated. Seeing as though there are other people
wanting this information, please reply in this (or a more relevant)
newsgroup.

Cheers,
	Warren Toomey


Xref: sparky comp.lsi:621 comp.lsi.cad:996
From: goldberg@isi.edu (Joel Goldberg)
Newsgroups: comp.lsi,comp.lsi.cad
Subject: Re: Calma GDSII Stream format
Date: 5 Oct 92 18:10:00 GMT
Reply-To: goldberg@isi.edu (Joel Goldberg)
Organization: USC-Information Sciences Institute
Keywords: GDSII

jgealow@mtl.mit.edu (Jeffrey C. Gealow) writes:
>I would like to obtain a specification of the Calma GDSII Stream
>format.  This format may be used to submit designs to MOSIS.  How may
>a specification be obtained?

The official GDSII document is published by Calma, as you might have
suspected.  It is titled "GDSII (tm) Stream Format Manual."  My latest
version is for Release 6.0, is dated February, 1987, and is document No
B97E060.  Unfortunately, this document covers only the syntax of Stream
Format.  To the best of my knowledge, there is *no* document that describes
the semantics of Stream Format; you need a Calma guru to enlighten you.
Even more unfortunately, attempts to divine the semantics from the names of
the syntactic record types will run across some lovely booby traps.  Do not
try this without professional assistance!

-- Joel Goldberg (for the above-mentioned Ms. Mosis)



Newsgroups: comp.lsi,comp.lsi.testing
From: luciano@athos.Berkeley.EDU (Luciano Lavagno)
Subject: Re: Information needed
Reply-To: luciano@athos.Berkeley.EDU (Luciano Lavagno)
Organization: UC Berkeley IC CAD Group
Date: Wed, 30 Sep 1992 17:15:14 GMT

In article <1992Sep30.093057.25933@peanuts.informatik.uni-tuebingen.de>,
es@peanuts.informatik.uni-tuebingen.de (Endric Schubert) writes:
>In article <1992Sep29.150706.29931@imag.fr>, boudjit@rhone.imag.fr (Mokhtar
>BOUDJIT) writes:
[...]
>|> 	- Is there any tool to translate a BLIF or SLIF multi-level
>|> 	sequential or combinational formats of the ISCAS benchmark
>|> 	circuits in the two-level description in order to use 
>|> 	Espresso as this one accepts as input only a two-level 
>|> 	description of a boolean function..
[...]
>yup, there is:
>
>use misII or sis (the newer one) from UC Berkeley:
>``misII -t blif -T pla -o <outfile>.pla <infile>.blif''

But be ready to wait for a while if '<infile>.blif' does not have a reasonable
sized two-level representation (apparently only C17 does :-) ).
Luciano

-- 
Luciano Lavagno            luciano@ic.Berkeley.EDU            +1-510-642-5012
Dept. of EECS, 207-69 Cory Hall, Univ. of California, Berkeley, CA 94720, USA
From: homi@ece.wvu.wvnet.edu
Newsgroups: comp.lsi
Subject: Graduate Research Assistantship Avalilable Spring 1993
Keywords: Research Assistantship
Date: 28 Sep 92 15:40:44 GMT
Organization: Microelectronic Systems Research Center

GRADUATE RESEARCH ASSISTANTSHIP AVAILABLE SPRING 1993
                September 25, 1992

                MICROELECTRONIC SYSTEMS RESEARCH CENTER 
                       WEST VIRGINIA UNIVERSITY
                        COLLEGE OF ENGINEERING

The recently established Microelectronic Systems Research Center
explores the application of advanced and emerging technologies in
high performance microelectronic systems, with an emphasis on new
system level technologies such as multi-chip modules, 3D systems,
intelligent systems, optical interconnections, and  cryoelectronics.
Current research projects are funded by DARPA and NSF and include 
collaborations with AT&T Bell Laboratories and with research 
consortia.

A graduate research assistantship in the area of high performance 
microelectronic systems will be filled at the begining of the 
spring semester 1993.  This is a highly competitive position, with 
applicants solicited both from WVU and from other universities. 
It is expected that this position will be filled by a PhD candidate,
though exceptional Masters level candidates will be considered.  
The following summarizes the research area.

Intelligent Networks for Highly Parallel, High Performance 
Computing:  Silicon Wafer Area Networks (SWANS)  
This program seeks to design an intelligent mesh-connected network 
of switches with dynamic adaptation to traffic in order to provide 
automatic load balancing through activity potentials evolving at a rate 
consistent with the size of the network and local state-machine 
decisions.  The overall network is to be implemented on a silicon 
wafer.  Project includes analysis of percolation and chaotic 
effects along with VLSI design and area/speed tradeoffs.  It is 
expected that the student will develop network simulations on a 
SUN workstation.  VLSI design will be based either on OctTools or 
on VALID tools.

Salary for this position is at a base of $2,000 per month,  at 
100% time during the summer and 50% time during the academic year.

For further information, contact either Dr. Stuart Tewksbury or 
Dr. Larry Hornak at the following address.     

        Microelectronic Systems Research Center 
        Engineering Sciences Building # 827     
        Evansdale Campus        
        West Virginia University        
        Morgantown, WV 26506-6101

        Tel: (304)293-6371        
        Fax: (304)293-5024        
        e-mail:  ee_skt@a.coe.wvu.wvnet.edu
        e-mail:  ee_hornak@a.coe.wvu.wvnet.edu

West Virginia University is an equal opportunity employer.
Newsgroups: comp.lsi,comp.lsi.testing
From: es@peanuts.informatik.uni-tuebingen.de (Endric Schubert)
Subject: Re: Information needed
Organization: "Lehrstuhl fuer Technische Informatik, Uni Tuebingen"
Date: Wed, 30 Sep 92 09:30:57 GMT

In article <1992Sep29.150706.29931@imag.fr>, boudjit@rhone.imag.fr (Mokhtar BOUDJIT) writes:
|> 
|> 
|> 	I would highly appreciate if someone could furnish me with the 
|> following information:
|> 
|> 
|> 	- Is there any tool to translate a BLIF or SLIF multi-level
|> 	sequential or combinational formats of the ISCAS benchmark
|> 	circuits in the two-level description in order to use 
|> 	Espresso as this one accepts as input only a two-level 
|> 	description of a boolean function..
|> 
|> 	My email address is:
|> 
|> 		boudjit@archi.imag.fr
|> 		
|> 
|> 	Thank you for your time and help.

yup, there is:

use misII or sis (the newer one) from UC Berkeley:
``misII -t blif -T pla -o <outfile>.pla <infile>.blif''

-- 

                     Endric Schubert
                  Universitaet Tuebingen
           Lehrstuhl fuer Technische Informatik
                        Sand 13
                 7400 Tuebingen, Germany
Newsgroups: comp.lsi.testing
From: yooho@ursula.ic.cmc.ca (Yoo Ho Cho)
Subject: Monthly Posting of the comp.lsi.testing charter
Organization: Canadian Microelectronics Corporation
Date: Fri, 2 Oct 1992 21:34:34 GMT

This is the monthly posting of the comp.lsi.testing charter.


NAME/GROUP: 
    comp.lsi.testing

STATUS:
    unmoderated 

CHARTER:
    This newsgroup is intended to cover all aspects of the testing of
    electronic circuits such as (but not restricted to)
      *  Testing of Digital and Analog Devices
      *  Automatic Test Pattern Generation
      *  Fault Modeling and Fault Simulation
      *  Design for Testability
      *  Scan Design and Built-in Self Test
      *  PCB-Test and Boundary Scan
      *  Design Verification
      *  ATE

    Important topics are (again not restricted to)
      * Announcements (conferences, workshops, special issues)
      * Books on testing
      * Standards
      * Benchmarks
      * Questions and answers
      * Discussions concerning technical or algorithmic problems
      * Available commercial and public domain tools

    PLEASE: DO NOT USE THIS GROUP FOR "test" POSTINGS TO CHECK YOUR
    MAILER OR NEWS SYSTEM. THERE ARE OTHER SPECIAL GROUPS FOR THIS
    PURPOSE, such as "alt.test", "news.test", "local.test" ETC.

WHY THIS GROUP:
    The ever increasing number of publications on testing shows a
    vivid and growing interest in that subject. A newsgroup on 
    testing will stimulate and accelerate the exchange of related 
    information among interested network users. It makes it easier 
    to recognize current trends in testing, especially for novices. 
    
    The discussion period showed a general agreement on the theme.
    Our first proposal for the name of the group was comp.lsi.cat,
    which is similiar to comp.lsi.cad. A number of contributors 
    remarked that this name is not generally understandable or 
    misleading. Among the proposed alternatives were:
    comp.lsi.test, comp.lsi.testing, comp.lsi.ate, comp.lsi.ft (fault 
    tolerance). Taking into account that ".test" may sound like
    "alt.test", "news.test" which have a specific function within the
    USENET hierarchy, the proposed name "comp.lsi.testing" should be
    the most understandable and general one. 

    Some authors commented that there are existing groups like comp.lsi
    which do not have an extreme news flow to date. Splitting therefore
    should not be necessary. We have never intended to split any group
    due to "net bandwidth", comp.lsi.testing is a new thread. A closer
    look at comp.lsi[.cad] shows that these groups are mostly design oriented,
    and this probably raises the level for participation of non-designers.

Newsgroups: comp.lsi.testing
From: yooho@ursula.ic.cmc.ca (Yoo Ho Cho)
Subject: VXI, IEEE488 and controlling software
Organization: Canadian Microelectronics Corporation
Date: Tue, 29 Sep 1992 19:31:28 GMT

Netters,

Two questions for instrumentation expert

1) I am about to look into a couple of lab instrument control programs. The two
   I have in mind are HP's VEE and National's LabView. Does anyone have
   any experience with either of these packages ? I'm thinking of controlling
   instrumentation on both VXI and IEEE 488 and I'd like to get an idea on 
   how easy they are to use and install.

2) VXI vs IEEE488. I'd like to get some information on your 
   experiences with either of these two instrument control busses.

Thanks 

Yoo Ho Cho
Canadian Microelectronics Corporation
yooho@scorpio.ic.cmc.ca
Newsgroups: comp.lsi.testing
From: yooho@ursula.ic.cmc.ca (Yoo Ho Cho)
Subject: Digital Testers
Organization: Canadian Microelectronics Corporation
Date: Wed, 30 Sep 1992 14:16:48 GMT


I'd like to ask the netters involved in IC testing, especially
educational institutions, if they have constructed/assembled digital
functional testers that would match the following specifications. We
are very interested in a low lost / low end solution for digital
functional testing in an educational environment.  If you have the best
solution, we would like to talk to you about licensing it for use in
Canadian Universities. 

Please e-mail to me. I will summarize to the net if there is sufficient 
interest.


Yoo Ho Cho

======================Specs==========================================

Specifications for a Low-End Digital Tester


1	# of pins ( I/O )		48/64 Splittable bi-directional
					I/O

2	standard DUT card		48 pin used for 68 pin PGA
					( to be customized )

3	maximum data rate		min. 1 MHz and maximum 5MHz

4	memory				16K per channel

5	per pin waveform formatting	6-8 clock phases,
					timing generator, common timing,
					resource selectable on per pin 
					basis

6	waveform formatting		delayed NRZ and NZ

7	hooks for mixed signal		sync out or trigger pulse

8	timing precision		edge resolution 2ns

9	timing accuracy			edge placement +- 5ns

10	dead time			=< 10% of period

11	minimum pulse width		=< 10% of period

12	voltage range			0-5 volts programmable per
					pin basis

13	slew rate			0.5V/ns

14	driver impedance		50 ohms

15	driver current sourcing		5mA ( four SLTTL )

16	driver current sinking		5mA

17	comparator			dual threshold

18	PMU				nice to have, not neccessary

19	dynamic Idq			Idq vs time, same resolution as
					timing generator

20	memory reload time		must be reloadable

21	voltage accuracy		
	 a. driver			+/- 50 mV
	 b. power supply		+/- 50 mV
	 c. compare threshold		+/- 50 mV

22	interface			Sun workstation prefered
					Other UNIX Workstations/IBM PC
					(IEEE 488 interface would be nice)

Newsgroups: comp.lsi.testing
From: cp79038@csie.nctu.edu.tw (Liu Hung-Bin)
Subject: Bin test!
Organization: National Chiao Tung University
Date: Mon, 5 Oct 1992 11:25:06 GMT

  This is a test !
From: 8809787l@levels.unisa.edu.au
Newsgroups: comp.lsi.testing
Subject: Help with PhD Topic
Date: 1 Oct 92 00:52:32 GMT
Organization: University of South Australia
NNTP-Posting-Host: sirius.itd.adelaide.edu.au
Originator: daemon@sirius.ucs.adelaide.edu.au

Dear readers

I am presently undertaking a PhD progarm at the University of South Australia
( Adelaide ). The topic that I am looking at presently is "Automated Design and
Diagnostics for Electronic Systems" specialy concentrating on digital systems.
I would be greatfull to you if you could provide me with any information on
this topic and also recent work which is going on in this direction.

I also would be greatfull if any one could provide me with some advice on the
possible directions which one might find more fruitfull in this area.
As a small note I would like to say at present I am looking at using the
functionality of the system blocks ( ie Boolean expresion ) to extract both
design and testing data, by using ideas drived from minimization. Would like to
comment on this ?

Any way for now I think I have taken your time enough, but would be greatfull
for response from you.

Thank you for your time, and hope to hear from you,

Yours faithfully 

Peyam Pourbeik
University Of South Australia
School of Electronic Engineering
Adelaide, South Australia, Australia

e-mail address : 8809787L@LV.LEVELS.UNISA.EDU.AU


#! rnews 445
From: mamjpc@levels.unisa.edu.au
Newsgroups: unisa.cis.dslss
Subject: IMPORTANT!!!!! assignment2
Date: 1 Oct 92 12:05:47 +0930
Organization: University of South Australia

For assignment 2

write the relative information out to a dummy file (as it states in the specs!)

not to the scrren

(though it is permissible to write it out to the screen as well)

Michael.

#! rnews 10674
From: etwz@levels.unisa.edu.au
Newsgroups: soc.culture.china
Subject: Convertor between GB and BIG5 wanted
Date: 1 Oct 92 16:24:17 +0930
Organization: University of South Australia

IS there a conversion package between the PRC Chinese standard code and 
the Taiwan Chinese code, ie. GB to or from BIG5 ? Thanks for inform me.

W. Zhang
University of South Australia
From: kernel@nextwork.rose-hulman.edu (Kernel Account)
Subject: lex and yacc for ML wanted
Reply-To: kernel@nextwork.rose-hulman.edu (Kernel Account)
Organization: Rose-Hulman Institute of Technology
Date: Sat, 26 Sep 1992 20:59:49 GMT
Keywords: lex, yacc, functional, question, ML

I've heard rumors on the existence of mllex and mlyacc (lex and yacc that
generate ML code).  The only version I could locate (through an ARCHIE
search) was written for CAML-Light.  I need a version that works with SML
of New Jersey.

o Does anybody know where I could find mllex or mlyacc for SML-NJ?
o Does anybody know of any other compiler tools for use with SML-NJ?

Email replies to kleinjf@cs.rose-hulman.edu

Joel F. Klein
The Happy Pascal Project,
Rose-Hulman Institute of Technology
-- 
Send compilers articles to compilers@iecc.cambridge.ma.us or
{ima | spdcc | world}!iecc!compilers.  Meta-mail to compilers-request.
From: Bruce.Hoult@bbs.actrix.gen.nz
Newsgroups: comp.compilers,comp.human-factors
Subject: Re: Syntax of Comments (was: language design tradeoffs)
Keywords: design
Date: 5 Oct 92 15:25:03 GMT
Article-I.D.: comp.92-10-014
Reply-To: Bruce.Hoult@bbs.actrix.gen.nz
Organization: Actrix Information Exchange

de19@umail.umd.edu (Dana S Emery) writes:
> I'm surprised no one has suggested coloration or styleing to reflect
> semantics.
> 
> It would be simple enough for a pretty printer to use
> font/italics/color/background shadeing for comments, and that would
> delineate commented out code in an emphatic way.  Of course, one has to
> allow the programmer to spec the styling.

The code browsing and editing environment I use on the Mac, "Object
Master" does just that.  (It does a lot more besides, but this isn't the
time to go into it all...  I'll just say that it provides a smalltalk-like
browser and controls Apple's MPW compilers via AppleEvents)

It understands the syntax of Object Pascal, C++ and (Object) Modula-2 and
lets the user assign a different colour and style to each syntatic
element.  You can create some extremely ugly things, and I don't find the
choice of syntatic elements entirely ideal (at least in C++ -- it seems to
be better in Pascal), but it do find that I like to make keywords bolded
and a medium gray (for about the same overall optical impact, but a
different "feel") and comments red.
-- 
Bruce.Hoult@bbs.actrix.gen.nz   Twisted pair: +64 4 477 2116
BIX: brucehoult                 Last Resort:  PO Box 4145 Wellington, NZ
-- 
Send compilers articles to compilers@iecc.cambridge.ma.us or
{ima | spdcc | world}!iecc!compilers.  Meta-mail to compilers-request.
Newsgroups: comp.compilers
From: Pat Terry  <CSPT@giraffe.ru.ac.za>
Subject: Grosch Toolkit For DOS
Reply-To: Pat Terry  <CSPT@giraffe.ru.ac.za>
Organization: Compilers Central
Date: Tue, 6 Oct 1992 16:26:30 GMT
Keywords: tools, question, MSDOS

Has anybody ported the Modula-2 versions of the GMD toolkit to work
under MS-DOS Modula-2 compilers?

Pat Terry, Computer Science, Rhodes University, GRAHAMSTOWN 6140, RSA
cspt@alpha.ru.ac.za  or  cspt@giraffe.ru.ac.za  or pdterry@psg.com
-- 
Send compilers articles to compilers@iecc.cambridge.ma.us or
{ima | spdcc | world}!iecc!compilers.  Meta-mail to compilers-request.
Newsgroups: comp.compilers
From: andrewd@cs.adelaide.edu.au (Andrew Dunstan)
Subject: Re: language design tradeoffs [macro mayhem]
Reply-To: andrewd@cs.adelaide.edu.au (Andrew Dunstan)
Organization: The University of Adelaide
Date: Sat, 26 Sep 1992 02:01:44 GMT
Keywords: C, macros, syntax, comment

tgl+@cs.cmu.edu (Tom Lane) writes:
|> The real reason that this is such a pain is not macros, it's C's
|> misbegotten syntax.  If semicolons were statement separators (a la Pascal)
|> instead of statement terminators, things would work a lot more smoothly.

I can't agree less. The semicolon as statement separator in Pascal can get
to be a real bug sometimes. It also leads to syntactic nonsense.  This
compound statement:

	begin
	   x := y;;;;
	end

is composed of 5 statements: the assignement plus a null statement after
each semicolon. Let's please have a semicolon terminator and an explicit
null statement as in Ada.
-- 
#  Andrew Dunstan                  
#  Department of Computer Science  
#  University of Adelaide          
#  South Australia                 
#  net: andrewd@cs.adelaide.edu.au 
[The semicolon as separator (Algol60) vs. as terminator (PL/I) is an old
argument that we're not going to resolve here.  My impression is that the
Algol approach is more elegant and makes source transformations, including
macro expansion, easier, while the PL/I approach is easier for humans to
write.  Neither is unambiguously better; one's preference usually depends on
what one learned first.  Personally, I think that the obvious and intuitive
way to indicate continuations is to put a digit after the initial tab. -John]
-- 
Send compilers articles to compilers@iecc.cambridge.ma.us or
{ima | spdcc | world}!iecc!compilers.  Meta-mail to compilers-request.
Xref: sparky comp.compilers:1683 comp.theory:2103