From: tbills@cse.unl.edu (Trent Bills)
Newsgroups: comp.sys.amiga.programmer,comp.sys.amiga.hardware
Subject: Re: CISC and RISC
Date: 16 Dec 1992 16:20:38 GMT
Organization: University of Nebraska--Lincoln	
Distribution: world
NNTP-Posting-Host: cse.unl.edu

|> Another Advantage of RISC is the abundance of Register memory.  CISC
|> commonly contains few registers (The 68000 has 8 data registers and 8
|> address registers) while RISC processors contain anywhere from 32 registers
|> to a few hundred registers (It is not uncommon to have RISC processors that
|> have 512 registers).  Since Register memory is about 10 times faster than
|> main memory, most of the instructions are register to register, therefore
|> increasing efficiency.

Since most microprocessor computers have either on chip or external caches,
register access really isn't much if any faster than memory access.  The
real speedup comes from the fact that register to register operations
can be coded in a short and easy to decode instruction word (usually 32
bits).
It is important to note that RISC processors that have > 32 registers do
not have the use of all of these registers simultaneously.  The processor
only has access to a few (24-32) at a time.  A compiler can then place
parameters for function calls in the last few registers.  When the
function call is executed, the CPW (current window pointer) is changed
so that the registers that were previously the last few are now the first
few.  This parameter passing technique avoids using the stack (slow memory)
and thereby drastically reduces the cost (time) of a function call.

|> There is also a significant amount of parallellism and pipelining in RISC
|> chips.  As soon as an instruction is started another instruction may be
|> started even before the completion of the previous instruction.  Output of
|> one instructions is passed on to another Unit in the chip for further
|> processing while the current unit executing the instruction fetches a new
|> instruction to process.  On many RISC chips as many as 4 instructions can be
|> completed in one clock cylce as a result of this.

Most RISC chips are NOT capable of completing 4 instructions in one clock
cycle.  Most RISC chips use a simple 4 or 5 stage pipeline which means that
one instruction is started every clock cycle and one instruction finishes
every clock cycle, only the instruction that is completed in a given
cycle was actually started 4 or 5 cycles before.  This results in a net
throughput of 1 instruction per clock cycle.

|> >I was under the impression that CISC meant complicated instruction set
|> >and RISC meant reduced instruction set. So wouldn't that mean larger
|> >code size on a RISC machine compared to CISC.
|> >
|> >What are the advantages of CISC and RISC?
|> 
|> CISC I think is easier to program.  RISC is difficult as you have to worry
|> about timing your instructions properly.  If you issued a memory write and
|> do a read from the same location immediately after the write instruction,
|> the data you may have wanted to read may not be there yet!  So you may have
|> to issue the write a few steps earlier than you would normally on a CISC
|> chip.

RISC is based on several observations made by looking at compiler generated
code.  The first is that compiler writers have great difficulty in trying
to find situations under which a complicated assembly code instruction
can be used.  It has been observed that compilers for CISC machines do not
typically make use of "nifty" instructions.  Second, it has been observed
that compilers for CISC machines ussually only use one or two addressing
modes.  Therefore, in the RISC processor, only one or two addressing modes
are implemented.  These simplifications and the register to register only
operations allow RISC designers to fit their instructions into a fixed
size instruction word (32 or 64 bits).  The fixed size instruction word
greatly reduces the complexity of the instruction decode portion of the
CPU.  All of these simplifications add up to a great savings in space
on the chip.  This extra space can be used for a cache, large register
file, or on chip coprocessors.

Since RISC is actually based on observations of existing compiler generated
CISC code, compilers have no problem generating code for RISC processors.
While the pipeline in the RISC processor does introduce some restrictions
on what instructions can be executed after others, compilers usually have
no problems getting around these restrictions.

 - Trent Bills