HDTenEightyP/NetNews huggingface dataset:
Newsgroups: comp.lang.vhdl
From: des@frogland.inmos.co.uk ()
Subject: vhdl array catenation etc
Reply-To: des@frogland.inmos.co.uk ()
Organization: INMOS Architecture Group
Date: Wed, 26 Aug 92 13:06:02 BST


can anyone help with a vhdl/synopsys problem we've been having recently
... at the moment we seem to be chasing the problem round a circle
as we've now shifted it back to its original point.

we have a general mulitplexor function "muxi" defined in a library
which takes as arguments an array of selectors and an array of
bits (which represent the catenation of same length words with
one word per selector) and it returns the subword from the array
of bits for which the selector is true (its assumed that only
one is true). however i think the behaviour is not relevant to
the problem.

we have a piece of vhdl which says something like

X(3 DOWNTO 0) := muxi((sig_vector_t'(<exp1>,<exp2>,<exp3>)),
                      (sig_vector12_t(Y(13 DOWNTO 10) &
                                      (sig_vector4_t'(low,high,high,low)) &
                                      (sig_vector4_t'(low,high,high,low)))));

where <expn> are various expressions and

TYPE     sig_vector_t        IS ARRAY (natural RANGE <>) OF sig_t;
SUBTYPE  sig_vector4_t       IS sig_vector_t(3 DOWNTO 0);
SUBTYPE  sig_vector12_t      IS sig_vector_t(11 DOWNTO 0);

using this we get an error

    Type conversion operand and result type must have matching elements in each
       dimension.

flagged on the second & catenation operator.

however if we try declaring temp as a sig_vector_t(11 DOWNTO 0) and
write

temp := (Y(13 DOWNTO 10) &
         (sig_vector4_t'(low,high,high,low)) &
         (sig_vector4_t'(low,high,high,low)));
X(3 DOWNTO 0) := muxi((sig_vector_t'(<exp1>,<exp2>,<exp3>)),temp)l

we don't get the error. anyone tell me what's going on .... doesn't VHDL
have substitionaly semantics?

also as a side issue ... is there any benefit from the way VHDL treats
array types as being the start and end indices rather than just a width?
from my recent experience it just buys you a heap of type conversions
all over the place to ensure that array bounds are what you expect.

--
--------------------------------------------------------------------------
david shepherd: des@inmos.co.uk or des@inmos.com    tel: 0454-616616 x 625
                inmos ltd, 1000 aztec west, almondsbury, bristol, bs12 4sq
                "i don't consider myself to be narcissistic ... if i had a
From: rmarshall@v2.cgu.mcc.ac.uk (Robert Marshall)
Newsgroups: comp.lang.vhdl
Subject: Would an archive site for this group be useful?
Keywords: VHDL anonymous ftp
Date: 3 Sep 92 08:50:00 GMT
Reply-To: rmarshall@cs.man.ac.uk
Organization: Manchester Computing Centre CGU

Some time ago, I posted a message asking if there were any archive sites for
this news group. I received no response other than a similar request posted at 
about the same time.

Let me phrase a different question: If an archive site for this group were to 
become available would there be any interest?

Robert
Newsgroups: comp.lang.vhdl
From: euaamt@eua.ericsson.se (Amir.Taheri)
Subject: VHDL Packages
Organization: Ellemtel Telecom Systems Labs, Stockholm, Sweden
Date: Wed, 2 Sep 1992 12:04:00 GMT

Hi all VHDL GURUs!
  If I am not totaly wrong there was some ftp-cite containing VHDL-libraries
and packages for public use. If there is any one out there who know about 
this please post the details to the group. 
I greatly appriciate this in advance.


                         Amir Taheri. 

Newsgroups: comp.lang.vhdl
From: kelley@rapnet.sanders.lockheed.com (Sean Kelley)
Subject: Re: Would an archive site for this group be useful?
Keywords: VHDL anonymous ftp
Organization: Lockheed Sanders, Inc., Nashua, NH
Date: Fri, 4 Sep 92 16:14:27 GMT

In article <1992Sep3.085000.1@v2.cgu.mcc.ac.uk>, rmarshall@v2.cgu.mcc.ac.uk (Robert Marshall) writes:
|> Let me phrase a different question: If an archive site for this group were to 
|> become available would there be any interest?
|> 
|> Robert

	What would the archive site consist of?

	Do you mean sample code?

	Or just Mail?

							Sean

-- 
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Lockheed-Sanders, Inc    
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Nashua, NH               
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Rock-Chalk JayHawk KU!!!!!!!!!!
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Xref: sparky comp.lang.vhdl:421 comp.arch:9044
From: jcooley@seqp4.sequoia.com (John Cooley)
Newsgroups: comp.lang.vhdl,comp.arch
Subject: Re: Synopsys Training
Date: 25 Aug 92 15:18:28 GMT
Organization: Sequoia Systems Inc., Marlboro, Mass.

> From: Vidur.Kapoor@bbs.oit.unc.edu (Vidur Kapoor)
> 
> Dear users,
>                 Could someone supply me some information on gdt software 
> from mentor graphics or synopsys synthesis software and inform me if there 
> are any courses in any university in the Boston area in this subject
>  
> Thanks in advance.
>  
> vidur

As far as I heard, the only place I've seen give classes in how to use
the Synopsys synthesis software has been Synopsys themselves.  I know
of quite a few univerisity graduate school types using the software,
but none of them have ever spoken about formal credited classes teaching
how to use Synopsys.  (Typically, they're using the tool in some sort of
sponsored project or thesis developement.)

The phone number for the Boston Synopsys office is (617) 890-0077; they
have regularly scheduled classes in which you can enroll.

					- John Cooley
					  ESNUG Moderator

===========================================================================
Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
===========================================================================
     !!!     "It's not a BUG,    |           jcooley@sequoia.com
    /o o\  /  it's a FEATURE!"   |         jcooley@sds.sequoia.com
   (  >  )                       |        "Yes, We make trees here!"
    \ - /       |
    _] [_       |        "This here ain't no one's opinion 'cept my own."
Newsgroups: comp.lang.vhdl
From: jab3@cec2.wustl.edu (John Alonzo Breen)
Subject: Re: VHDL Problem - Procedures & Processes
Organization: Washington University, St. Louis Mo.
Distribution: usa
Date: Thu, 27 Aug 1992 12:56:36 GMT

In article <1992Aug25.172750.11830@babbage.ece.uc.edu> pmamtora@pumpkin.ece.uc.edu (Paddy Mamtora) writes:
>1.Can you call a procedure from two different processes ? If not,
>then, is there any way to getting around it ?

I know for a fact that procedures without signal assignments can be
called from more than one process, and I'm pretty sure that procedures
with signal assignments can also (but see below).

>2. In a procedure, can you assign to signals that are declared
>to be ports of the entity ? ( without declaring any 
>formal parameters for the signals in the procedure declaration) 

As I recall, there were some problems with this; something about the
analyzer/simulator not being able to tell which process (and
accompanying driver) to associate with the assignment.  Maybe one of
the "language police" will elaborate.
--
John A. Breen                   |
jab3@cec1.wustl.edu             | This space unintentionally left blank
Newsgroups: comp.lang.vhdl
From: cclrl@csdws2.trentu.ca (Larry Laframboise)
Subject: Printing on HP Deskjet 500c
Organization: Trent University
Date: Fri, 4 Sep 1992 17:35:39 GMT

I want to output colour images on a Deskjet 500c printer from IDL.
PCL device type appears not to deal with colour.
HJ device type doesn't work on an Ultrix workstation.

Anyone got a solution.

Larry

LLaframboise@TrentU.ca
Newsgroups: comp.lang.verilog
From: eversole@acae037.cadence.com (Richard Eversole; x6239)
Subject: Re: Verilog models for 74xxx?
Reply-To: eversole@acae037.cadence.com (Richard Eversole; x6239)
Organization: Cadence Design Systems, Inc.
Date: Tue, 1 Sep 1992 10:38:27 GMT

As part of the Standard Release of Verilog from Cadence you should
be able to find a directory called examples/libraries.
Here you will find two important files:

   CDS_GEN_LIBS.v  and CDS_GEN_UDPS.v

These two files contain the "generic" library that Cadence uses as
the basis for all the models it produces. While this library will not
show you how to select the timing for devices you know it does show 
you the way to model various devices typically found in an ASIC
library. 

These same files should be present in the release for the version
of Verilog integrated with Design Framework II.

Cadence has been shipping these example models since it's 1.6 release.

Additionally, Cadence does provide(at a charge of course) a library of
standard "TTL", "CMOS" and "ECL" parts for use in board and system 
level design. These models are Verilog HDL and provide a good source
of how to model these types of devices.

-- 
  
  =====================================================================

    eversole@cadence.com
  
    Live long and prosper !

    |Standard disclaimers apply: I speak for myself and not Cadence|


Newsgroups: comp.lang.verilog
From: hutton@eucad.co.uk (Peter Hutton)
Subject: NDL => Verilog Translator
Keywords: NDL Verilog
Reply-To: hutton@eucad.co.uk
Organization: EuCAD
Date: Wed, 26 Aug 1992 11:15:39 GMT

Has anyone heard of (or even better got) a translator from LSI Logic's NDL
format to Verilog? Sources, names, contacts, hints ... all welcome.

	Thanks,
		- pete

Newsgroups: comp.lang.verilog
From: eekhfung@uxmail.ust.hk (Fung Ka Hing)
Subject: Analogue modeling by Verilog
Summary: Enquiry for information
Organization: Hong Kong University of Science and Technology
Date: Thu, 3 Sep 1992 07:15:52 GMT

I am a new learner of verilog.  I want to find some information about the
ability of modelling analog circuit by verilog.  

Would someone help me please?
From: fields@acuson.com (Julian Fields)
Newsgroups: comp.lang.verilog
Subject: Re: NDL => Verilog Translator
Keywords: NDL Verilog
Date: 29 Aug 92 00:13:34 GMT
Organization: Acuson; Mountain View, California

hutton@eucad.co.uk (Peter Hutton) writes:
>Has anyone heard of (or even better got) a translator from LSI Logic's NDL
>format to Verilog? Sources, names, contacts, hints ... all welcome.

Synopsys can do this if you want all the gates instantiated.

-- 
Julian Fields, Jr        fields@acuson.com  
VLSI Design Engineering Consultant 
415-929-9112x2408 work,408-773-8197h
This is from ~/.tail 
Newsgroups: comp.lang.verilog
From: eversole@acae037.cadence.com (Richard Eversole; x6239)
Subject: Re: readmem
Reply-To: eversole@acae037.cadence.com (Richard Eversole; x6239)
Organization: Cadence Design Systems, Inc.
Date: Mon, 31 Aug 1992 13:35:12 GMT

In article <ovs5imk@fido.asd.sgi.com>, williams@agomoda.asd.sgi.com (Eric Williams) writes:
|> In <4006@rbiffm.informatik.uni-frankfurt.de> justin@rbiffm.informatik.uni-frankfurt.de (Justin Strohschneider) writes:
|> 
|> >For the simulation of a computer architecture it is necessary for me to
|> >define a RAM as a module and to have several incarnations of this RAM with
|> >different contents.
|> >The $readmem system task can be used to fill a memory array with data.
|> >The problem I have is to realize different filenames in the $readmem task.
|> >I would be very glad if anybody could give me some information concerning
|> >this problem.
|> 
|> Two ways you could do this.  The first method simply does the readmemh from
|> the module that instantiates the memories.  It sounds like you're trying to
|> put the readmem in the module that contains the memory.  In this case try
|> method 2 which passes this filename into the module as an input.
|> 
|> -Eric Williams


Another alternative (and prefered over second option shown by Eric is
to use the parameter construct. There are two ways to use this:
override with defparam and module parameter value assignment.
Both are shown in the following simple example. Note I only use
a $display but it could be $readmemh or whatever.


module test;

wire A;

memmod #("FILEA") U1(A); // Parameter Value Assignment

defparam U2.FOO = "BAR";
memmod U2(A);

endmodule

module memmod(A);
input A;

parameter FOO = "";

initial
 $display("%s",FOO);
endmodule


-- 
  
  =====================================================================

    eversole@cadence.com
  
    Live long and prosper !

Newsgroups: comp.lang.verilog
From: hampton@ecadsr.enet.dec.com (Jonathan D. Hampton)
Subject: Verilog models for 74xxx?
Organization: Digital Equipment Corporation
Date: Thu, 27 Aug 1992 15:01:33 GMT

Hi.

I beginning to delve into the Verilog world.  Can someone send to me
a few verilog models to study?  Maybe something in the 74xxx
series?

Thanks.

Hamp 


-----

Jonathan "Hamp" Hampton		hampton@ecadsr.dec.com


	"Zipperphobia?  *BUTTON* your fly!"

-----
From: hitesh@duddley.tamu.edu
Newsgroups: comp.lang.verilog
Subject: Verilog models for M68000 M68020 M68030 etc.
Date: 1 Sep 92 18:45:53 GMT
Reply-To: hitesh@duddley.tamu.edu ()
Organization: Texas A&M University
Originator: hitesh@duddley.tamu.edu

Hi,

I wanted to know if I could get the functional models of any processor like 
the M68k family or the Intel family or any other experimental processor model.
I am doing some work in evaluation of architectures using Verilog and it would
be great if someone could tell me if anything like this is available.
Thanks.


Hitesh.
From: kandappan@asic.dec.com (K. Parthiban)
Newsgroups: comp.lang.verilog
Subject: Re: NDL to Verilog translator
Date: 1 Sep 92 00:51:12 GMT
Organization: Digital Equipment Corporation

Apropos the query for an NDL to Verilog translator, I presume you are
looking for a gate level netlist translator.

Perhaps you know this already or perhaps this is irrelevant. FWIW,
do you have access to Synopsys? If so, you could read in Verilog and output
NDL or vice-versa!

ciao 
K.Parthiban
From: alzien@palmyra.eng.hou.compaq.com (Khaldoun Alzien)
Newsgroups: comp.lang.verilog
Subject: Incremental Pattern File tasks
Date: 31 Aug 92 21:20:26 GMT
Organization: Compaq Computer Corp.

--------------------------------------------------------------------------------
Hi,

Has anybody used the Incremental Pattern File tasks with vectors?
    ( $incpattern_write, $incpattern_read, $compare )

    According to Verilog-XL 1.6a Release Notes, the Incremental Pattern File
    tasks support both scaler and vectors, but that was not what I
    experienced.

I did not have any problems using the tasks when all my signals were scaler.
On the other hand every thing fell apart once at least one of my signals was
a vector.

	- $incpattern_write: Verilog did not report the signal name in
	    the Declarations for Incremental Stimulus File "file_name"

	- $incpattern_read: Did not read in the vectors properly which leads
			    me to believe that it was not saved properly,
			    or better yet not saved at all.

	- $compare: reports FALSE errors.

Your feedback is appreciated.

--------------------------------------+-----------------------------------------
        Khaldoun Alzien		      | Experience is what causes a person to 
	(713)374-4114                 | make new mistakes instead of old ones.
	alzien@twisto.compaq.com      | -- author unknown --
--------------------------------------+-----------------------------------------
Xref: sparky comp.lang.verilog:334 comp.lang.vhdl:436
From: jcooley@seqp4.sequoia.com (John Cooley)
Newsgroups: comp.lang.verilog,comp.lang.vhdl
Subject: ESNUG goes on Vacation!
Date: 4 Sep 92 15:44:09 GMT
Organization: Sequoia Systems Inc., Marlboro, Mass.



  This message is directed to the subscribers of the E-mail Synopsys Users
  Group (ESNUG) who may have missed the latest mailing:

  E-mail at my company is going to be messed up for the next two weeks because 
  we're moving to another building.  As a consequence, ESNUG will be down for 
  9 days from Monday, Sept. 7 to Wednesday, Sept. 16.

						- John Cooley

 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    |           jcooley@sequoia.com
     /o o\  /  it's a FEATURE!"   |         jcooley@sds.sequoia.com
    (  >  )                       |        "Yes, We make trees here!"
     \ - /       |
     _] [_       |        "This here ain't no one's opinion 'cept my own."
Newsgroups: comp.lang.sigplan
From: bh@anarres.CS.Berkeley.EDU (Brian Harvey)
Newsgroups: comp.lang.scheme
Subject: Re: wots going on here!?
Date: 31 Aug 1992 05:02:56 GMT
Organization: University of California at Berkeley
NNTP-Posting-Host: anarres.cs.berkeley.edu

jinx@zurich.ai.mit.edu writes:
>Your answer of having to tweak a flag or whatever is analogous to
>saying "recompile and run it under the debugger".
>
>Please remember that there are programs that modify global state, and
>thus re-running is not an option since they may not fail in the same
>way or at all.

As an experienced C programmer, I always put CFLAGS = -g in my makefile.
I'm thinking about what's best for a beginner.  Beginners mostly make
trivial mistakes -- missing or extra parentheses, for example -- and it's
not clear that a debugger would do them much good.  And when the core
language is still pretty mysterious, I don't think they should have to
deal with the extra mysteries of a debugger.

So, indeed, when I'm teaching C, I tell my *beginning* students nothing
about gdb; if they can't find their bugs by inspection I tell them to
put in debugging printf's and recompile.  After a month or so of that,
that's when I teach them about gdb.

I think it should be the same in Scheme.  For the example I gave, which
was saying (+ 2 a) when there's no variable a, the message I proposed
says it all.  A debugger wouldn't help much anyway.  If the problem is
about something returning wrong values, trace some procedures and run
it again.

(If it modifies global state and therefore can't be run again, you are
up to chapter 3 and therefore halfway through the semester.  By then
you can have complicated debuggers if you want.)
From: jinx@zurich.ai.mit.edu (Guillermo J. Rozas)
Newsgroups: comp.lang.scheme
Subject: Re: wots going on here!?
Date: 29 Aug 92 14:19:08 GMT
Reply-To: jinx@zurich.ai.mit.edu
Organization: M.I.T. Artificial Intelligence Lab.
In-reply-to: 9241593t@lux.latrobe.edu.au's message of 29 Aug 92 09:21:13 GMT

In article <1992Aug29.092113.12007@lugb.latrobe.edu.au> 9241593t@lux.latrobe.edu.au (B. Leach) writes:

|   This is the sort of error I keep getting:
|
|   Application of inapplicable object #[undefined-value]
|
|   There is no environment available;
|   using the current REPL environment
|   ;Package: (user)
|
|   Now I have NO idea what that means!!  Is my program fubar or is the
|   installation?!
|

What this means is that your program (or the system on behalf of your
program) tried to apply (i.e. invoke, call) the object whose printed
representation is `#[undefined-value]' as a procedure.

Of course, that object is not a procedure, and the system didn't let
you do it.

Since the error occurred at apply time, not at eval time, there is no
environment defined, and the system is telling you that.

Since there is no environment associated with the error, the system
must choose one to give you in the new read-eval-print loop (REPL)
that it will create (the one with the error prompt).  The system is
telling you that it is using the environment of the "surrounding" REPL.

It is also telling you that this environment is the environment
corresponding to the `(USER)' package, i.e. the default user
interaction environment (where all your definitions are likely to
reside).

Although there is no proper environment associated with the error, you
can go into the debugger (Type `(debug)') to examine the stack and the
history, where you may find some useful information.
From: bh@anarres.CS.Berkeley.EDU (Brian Harvey)
Newsgroups: comp.lang.scheme
Subject: Re: wots going on here!?
Date: 30 Aug 92 04:28:33 GMT
Organization: University of California at Berkeley
NNTP-Posting-Host: anarres.cs.berkeley.edu

jinx@zurich.ai.mit.edu writes:
>There is a large tension in a system
>aimed both at experienced users and stark novices between being overly
>verbose and "nice" and being useful.
  [...]
>The system distributed by MIT is not the system that is used directly
>by students in 6.001 or 6.003 at MIT.  The system given to students is
>typically built on top and often is "nicer" to novices at the expense
>of being cumbersome to experienced users.

The behavior I want would be *less* verbose:

	> (+ 2 a)
	Unbound variable: a

	>

Short and sweet.  It should be possible for an advanced user to ask
for pause-on-error behavior in which Scheme would attempt to preserve
the environment in which the error occurred, but you should have to
ask for it.  (This is how Logo does things.  Errors give a message
and return to toplevel, unless you have asked in advance for pause
on error.  In that case you get a special prompt and (because of good
old dynamic scope -- but that's another argument) *all* of the possibly
relevant variables are immediately accessible in the usual way without
you having to know anything about environments.)
From: kend@data.rain.com (Ken Dickey)
Newsgroups: comp.lang.scheme
Subject: Re^2: wots going on here!?
Date: 2 Sep 92 23:44:49 GMT
Organization: Microtek DSD, Hillsboro, OR

>bh@anarres.CS.Berkeley.EDU (Brian Harvey) writes:

>%%The behavior I want would be *less* verbose:
>%%        > (+ 2 a)
>%%        Unbound variable: a
>%%        >

Well, as long as you are not asking for standards (!), here is Gambit:


: (+ 2 a)
*** ERROR -- Unbound variable: a

1: ,r		;; return a value for a
Value: 3
5

: (define x 1)
x

: (define z (set! x 2))  ;; to get undefined value
z

: z
#[undefined]

: (z 37)
*** ERROR -- Operator is not a PROCEDURE
(z 37)

1: ,?
,?        : Summary of commands
,+ and ,- : Move to next or previous frame of continuation
,<n>      : Move to particular frame (<n> <= 0)
,b        : Display frames of continuation (i.e. backtrace)
,p        : Display procedure attached to current frame
,e        : Display subproblem of current frame
,l        : Display list of local variables accessible in current frame
,t        : Transfer to top-level REP loop
,d        : Transfer to previous REP loop
,r        : Return from REP loop
,q        : Quit

1: ,q
From: jinx@zurich.ai.mit.edu (Guillermo J. Rozas)
Newsgroups: comp.lang.scheme
Subject: Re: MIT C-Scheme for DOS
Date: 23 Aug 92 17:32:46 GMT
Reply-To: jinx@zurich.ai.mit.edu
Organization: M.I.T. Artificial Intelligence Lab.
In-reply-to: dorai@tone.cs.rice.edu's message of 23 Aug 92 00:14:48 GMT

In article <BtEu0o.9BK@rice.edu> dorai@tone.cs.rice.edu (Dorai Sitaram) writes:

|   @ Is there ftpable documentation on the different ways of defining
|   macros in MIT C Scheme?  The scheme.dvi appears to document only
|   procedures.

You may find what you need in altdorf:archive/scheme-7.1/macros.txt

It is not complete, but it may be adequate.

At some point MIT Scheme will change to agree with R[45]RS in this
respect, which is why the old system has not really been documented.

|   @ Has there been any advance on command-line options beyond that
|   mentioned in user.dvi?  Specifically, can users now get at the command
|   line once they have been whisked into the repl?  Right now, I'm doing
|   something ugly like having batch files that prefix calls to Scheme
|   with changes to scheme.ini to mimic this kind of action. 
|

Not conveniently in the version that is being distributed.  This has
been changed for the next version, which should be out in a few weeks.

|   @ Is there a way to exit Scheme without going through the confirmation
|   dialog?

(%exit)

instead of 

(exit)