HDTenEightyP/NetNews huggingface dataset:
From: declrckd@rtsg.mot.com (Dan J. Declerck)
Subject: Re: What's in a name?
Organization: Motorola Inc., Cellular Infrastructure Group
Date: Fri, 24 Jul 1992 14:48:12 GMT

In article <DOCONNOR.92Jul23085513@potato.sedona.intel.com> doconnor@sedona.intel.com (Dennis O'Connor) writes:
>
>vhs@darkcube.radig.de (Volker Herminghaus-Shirai) writes:
>] In article <> davidsen@ariel.crd.GE.COM  (william E Davidsen) writes:
>] > In article <1992Jul20.092822.7666@spool.cs.wisc.edu>,  
>] mfrank@wilma.cs.wisc.edu (Matt Frank) writes:
>] > 
>] > |> 1)  Backwards compatability is a waste of everyones time.
>] > 
>] >   Fortunately for the vendors, consumers disagree with that statement.
>] > In millions.
>]
>] You're right. Fortunately *for the vendors*.
>
>Give me a break. Intel's employees would love to take off with a bold new
>architecture that would be the pinnacle of microprocessor performance,
>completely free of the baggage of the past.

Isn't this what the 860 and 960 series is all about??


>

-- 
=> Dan DeClerck                      |  EMAIL: dand@isdgsm.motgate.mot.com<=
=> Motorola Intl Subscriber Group    |                                    <=
=>                                   |  Phone: (708) 632-4486             <=
----------------------------------------------------------------------------
Xref: sparky comp.arch:8334 comp.lang.misc:2702
From: hrubin@pop.stat.purdue.edu (Herman Rubin)
Newsgroups: comp.arch,comp.lang.misc
Subject: Re: MVC and MVCL (was Re: RISC Mainframe)
Date: 26 Jul 92 18:17:41 GMT
Followup-To: comp.arch
Organization: Purdue University Statistics Department

In article <1992Jul20.154604.12548@bcars64a.bnr.ca> schow@bqneh3.bnr.ca (Stanley T.H. Chow) writes:
>In article <GLEW.92Jul20084651@pdx007.intel.com> glew@pdx007.intel.com (Andy Glew) writes:

>>    >[Henry Spencer]
>>    >Of course, a RISC bigot like me :-) would say that this means your machine
>>    >is unbalanced:  the hardware has useful capabilities that the software is
>>    >unable to exploit in a general-purpose way.  A straight byte-for-byte copy
>>    >is not the only thing one might want to do at top speed...

>>    [Stanley Chow]
>>    Ah, I see you belong to the rewrite-code-for-each-new-machine school
>>    of programming. Otherwise, how do you write optimal loops that depend
>>    on the cache line transfer size?

>>Playing both sides, it is rather easy to create programs to find
>>and generate the optimal loops automatically.

>Clearly then, you belong to the compile-code-for-each-different-machine
>school of administration. I think I will start a disk drive company to
>supply your disk requirements :-)

Until there is a language which is powerful enough that the compiler 
can look at all the manifold ways to do what should be done, it is 
necessary to even write code for each different machine.  Certainly,
a compiler should make a different translation of HLL code into 
machine instructions for each different machine.  

Now how should the code be written?  If the language can say, copy
this block of memory to there, one can hope that the compiler can
do things in a reasonably optimal manner.  If the language cannot,
then not only should the code be compiled separately, but it should
be written separately.

None of the common current HLLs is anywhere near powerful enough to do
this, and other even essentially machine independent constructs, in
such a way that reasonable optimizing can be done.  That is, unless
you allow the compiler to do such rash things as to say that "this is
what the user MEANT to do."  And if the user does something slightly
different in between, the resulting code does not even accomplish the
design goals, however inefficiently.
-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907-1399
Phone: (317)494-6054
hrubin@pop.stat.purdue.edu (Internet, bitnet)  
{purdue,pur-ee}!pop.stat!hrubin(UUCP)
From: ivie@cc.usu.edu (CP/M lives!)
Newsgroups: comp.arch
Subject: Re: What's in a name?
Date: 23 Jul 92 20:14:38 GMT
Organization: Utah State University

In article <kitchel.711899554@moray> kitchel@moray.dpsi.com (Sidney W. Kitchel) writes:
(Mitch Kahn) writes:
>>
>>Intel boxes will still be the cheapest MIPs on the planet. 
>
>	WRONGO!!!! As of now, the cheapest MIPS on the planet come
>from MasPar Computer Corp. The MasPar MP-1 offers them at $50 / MIPS.
>You should ask Intel when you are going to get a 200 MIPS box for
>$10,000.

Actually, the _cheapest_ MIPS on the planet are the old used ones that
no one wants anymore. I picked up a 4MHz NorthStar for $5, making $5/peak MIPS.
Then there's the 11/23+ that mysteriously showed up on my porch the other
day for free...

Roger Ivie
ivie@cc.usu.edu
From: henry@zoo.toronto.edu (Henry Spencer)
Newsgroups: comp.arch
Subject: interrupt overhead
Date: 23 Jul 92 21:08:31 GMT
Organization: U of Toronto Zoology

I wrote:
>Pretty much the inescapable minimum is two pipeline breaks plus a cycle for
>the "return from interrupt" instruction...

John Carr has pointed out to me, in private mail, that a clever CPU
doesn't actually need to flush its pipelines, if the things in the
pipeline are guaranteed not to incur exceptions.  So it's potentially
not much worse than a couple of taken branches.
-- 
There is nothing wrong with making      | Henry Spencer @ U of Toronto Zoology
mistakes, but... make *new* ones. -D.Sim|  henry@zoo.toronto.edu  utzoo!henry
Newsgroups: comp.arch
From: eoahmad@ntuix.ntu.ac.sg (Othman Ahmad)
Subject: Re: Request Info Re Bus Trends & Intel 486s
Organization: Nanyang Technological University - Singapore
Date: Sun, 26 Jul 1992 04:35:11 GMT

In article <TOMW.92Jul25174038@orac.esd.sgi.com> tomw@orac.esd.sgi.com (Tom Weinstein) writes:

: I think the important word here isn't "better", it's "cheaper."  With
: motherboard, it's easier to put your system in a smaller box, use less
: board space, and fewer connectors.  All that adds up to lower production
: costs.
It is also faster because of direct connections to high speed devices such as
RAM. I am hoping that they put VIDEO on board since 8514 is establishing itself
as a standard, but it must be on zero wait state display refresh, and
can be switched on/off.

--
Othman bin Ahmad, School of EEE,
Nanyang Technological University, Singapore 2263.
Internet Email: eoahmad@ntuix.ntu.ac.sg
Bitnet Email: eoahmad@ntuvax.bitnet

Newsgroups: comp.arch,alt.folklore.computers,comp.benchmarks
From: kludge@grissom.larc.nasa.gov ( Scott Dorsey)
Subject: Re: dinosaur horsepower
Organization: NASA Langley Research Center and Reptile Farm
Date: Wed, 29 Jul 1992 14:18:08 GMT

In article <Bs5L03.3tH@exnet.co.uk> dhd@exnet.co.uk (Damon) writes:
>In article <1992Jul28.155852.23608@sctc.com> smith@sctc.com (Rick Smith) writes:
>>I was a fan of papertape myself. (5 points: can you spot the pun?)
>
>No, but I'm sure I'll burst out laughing when you list out the hole joke.

What an uncultured chad.
--scott
Newsgroups: comp.arch
From: sef@kithrup.COM (Sean Eric Fagan)
Subject: Re: What's in a name?
Organization: Kithrup Enterprises, Ltd.
Date: Mon, 27 Jul 1992 21:40:15 GMT

In article <1992Jul27.165807.29014@adobe.com> zstern@adobe.com (Zalman Stern) writes:
>1) The 486 still supports an incredibly baroque segmentation scheme that no  
>interesting piece of 32 bit software uses. (I.e. Segmentation should have  
>been left out of the 32 bit architecture and the gates and other resources  
>used to do something productive.)

The segmentation scheme is crucial to the chip; you can, for example, have a
task with 16-bit and 32-bit segments.  I.e., there isn't a "32-bit mode,"
instead, there are 32-bit *segments*.

The chip would have been far worse had they come up with two seperate modes
for the '386.

-- 
Sean Eric Fagan  | "My psychiatrist says I have a messiah
sef@kithrup.COM  |  complex.  But I forgive him."
-----------------+              -- Jim Carrey
Any opinions expressed are my own, and generally unpopular with others.
From: lindsay+@cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: 64-bit CPU vs 2 x 32-bit CPUs
Summary: not so it matters
Keywords: pins
Date: 26 Jul 92 03:26:36 GMT
Article-I.D.: cs.1992Jul26.032636.244142
Organization: School of Computer Science, Carnegie Mellon


eoahmad@ntuix.ntu.ac.sg (Othman Ahmad) writes:
>Which die area are you measuring? Have you taken into account the area taken
>by the pads? The pads are huge and require large drivers and protection 
>circuits.

Since the DEC 21064 Alpha chip only supports 43-bit effective virtual
addresses, the cost is approximately 43-32=11 pins.

Since the package has 431 pins, I don't think that 11 pins was some
sort of horrendous burden that changed everything.
-- 
Don		D.C.Lindsay 	Carnegie Mellon Computer Science
Newsgroups: comp.arch
From: glew@pdx007.intel.com (Andy Glew)
Subject: Re: CISC Microcode (was Re: RISC Mainframe)
Organization: Intel Corp., Hillsboro, Oregon
	<BrE09F.4JK@metaflow.com> <1992Jul15.163217.434@urbana.mcd.mot.com>
	<BrM813.Du5@zoo.toronto.edu> <GLEW.92Jul23184629@pdx007.intel.com>
	<JCALLEN.92Jul24132152@marley.think.com>
Date: Mon, 27 Jul 1992 03:44:14 GMT

       By the way: creating virtual address aliases with different cache
       properties is a recipe for a complicated, expensive, and lower
       performance than it should be multilevel cache system.

    How so? Since the R4000 uses a completely separate bus for the
    secondary cache, I don't see the complication. Uncached access
    go straight to the main memory bus; otherwise the usual cache
    lookup takes place. What am I missing?

If the access is determined to be uncached based on a bit in the TLB
entry, you have to send it to both the main memory bus and the
backside cache, because it might have been placed in the cache based
on a virtual address alias.

Unless, that is, you have required users to have the same cacheability
in all virtual address aliases.

I call this "cacheability type aliasing".  What machines do this?


--

Andy Glew, glew@ichips.intel.com
Intel Corp., M/S JF1-19, 5200 NE Elam Young Pkwy, 
Hillsboro, Oregon 97124-6497

This is a private posting; it does not indicate opinions or positions
of Intel Corp.

Intel Inside (tm)
From: mash@mips.com (John Mashey)
Newsgroups: comp.arch
Subject: Re: What's in a name? (cross-posted to SGI since mentioned)
Date: 22 Jul 1992 23:56:37 GMT
Organization: MIPS Computer Systems, Inc.
NNTP-Posting-Host: winchester.mips.com

In article <MKAHN.92Jul22092527@hopi.sedona.intel.com> mkahn@hopi.sedona.intel.com (Mitch Kahn) writes:
>] 1)  Backwards compatability is a waste of everyones time.
>
>Better tell that to DEC, IBM, MIPs, Motorola etc. as well as all the users
>in the world who do not want to buy new software every time they get a
>faster box. What color is the sky in your world?

Although I hate to agree with somebody from Intel :-) I do this time.
In this business, you get one chance to start from scratch, then
you have to be at least upward-compatible for a very long time...

>Intel boxes will still be the cheapest MIPs on the planet. Who cares if
>a Crimson (or a Chartreuse) can run Windows. I'll get my P5 box for
>$5k which is about $10K cheaper than anyone else.

P5? When?
It will be interesting to read between the lines of tomorrow's
press reports.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
UUCP: 	 mash@mips.com [soon to be mash@sgi.com, but not quite moved yet].
DDD:  	408-524-7015,  or 524-8253
USPS:	(soon) Silicon Graphics, 2011 N. Shoreline Blvd, Mountain View, CA 94043
From: cullip@pooh.cs.unc.edu (Timothy Cullip)
Newsgroups: comp.arch
Subject: Re: What's in a name?
Date: 23 Jul 92 18:16:19 GMT
Organization: University of North Carolina, Chapel Hill

In article <kitchel.711899554@moray> kitchel@moray.dpsi.com (Sidney W. Kitchel) writes:
>mkahn@hopi.sedona.intel.com (Mitch Kahn) writes:
>
>>Intel boxes will still be the cheapest MIPs on the planet. 
>
>	WRONGO!!!! As of now, the cheapest MIPS on the planet come
>from MasPar Computer Corp. The MasPar MP-1 offers them at $50 / MIPS.
>You should ask Intel when you are going to get a 200 MIPS box for
>$10,000.

200 MPIS for $10,000, no not yet (in one box), but Intel based PC clones
are closing in on 20 Mips for $1000 (a cheap stripped down 486 no name clone).

Not that I like Intel (or the ubiquitous PC), but they are real close to
the $50/MIP level.


-- 

   Tim Cullip
   cullip@cs.unc.edu
Xref: sparky comp.sys.apple:14 comp.sys.apple2:17667
Organization: Bar-Ilan University Computing Center, Israel
Date: Tue, 21 Jul 1992 08:50:32 IST
From: Noam G. Nudelman <P88038@BARILVM.BITNET>
Newsgroups: comp.sys.apple,comp.sys.apple2
Subject: Apple visydex files -> macintosh

Hi,
  I am interested in converting visydex files that where
created on an Apple computer to files that I can use
on the Macintosh.  Any help / information will be appreciated.

                               Noam G. Nudelman



internet: noam@erez.cc.biu.ac.il

bitnet:   p88038@barilvm.bitnet
From: massaro@cats.ucsc.edu (Dominic W Massaro)
Newsgroups: comp.sys.sgi
Subject: Re: VGXT vs. Reality Engine
Date: 29 Jul 92 01:13:05 GMT
Organization: University of California; Santa Cruz
NNTP-Posting-Host: si.ucsc.edu


Any VGX trade-in program envisioned?
-- 

======================================================================
=                                                                    = 
=   Dr. Michael M. Cohen                   mmcohen@dewi.ucsc.edu     = 
=   Program in Experimental Psychology     mmcohen@fuzzy.ucsc.edu    =
=   433 Clark Kerr Hall                    408-459-2655 LAB          = 
=   University of California - Santa Cruz  408-459-2700 MSGS         = 
=   Santa Cruz, CA 95064                   408-459-3519 FAX          =
From: joel@jellotrees.esd.sgi.com (Joel Tesler)
Newsgroups: comp.sys.sgi,psu.comp.sgi
Subject: Re: Toolchest
Date: 24 Jul 92 23:31:03 GMT
Organization: Silicon Graphics, Inc.  Mountain View, CA


Toolchest is based on mwm.  Both execute all commands in the shell
specified by $SHELL.  csh always executes .cshrc when starting, even
when running a non-interactive script.  Your .cshrc should probably
contain the lines

if ($?prompt) then
	...whatever should only be done in interactive shell...
endif

Joel Tesler
joel@sgi.com
415-390-3048
From: HERBER@fnalf.fnal.gov (Randolph J. Herber, CD/DCD/USS, x2966)
Newsgroups: comp.sys.sgi
Subject: Re: Simple Graph Generation Tool -- gnuplot is suggested
Date: 27 Jul 92 17:04:29 GMT

Some possible sources for gnuplot near-current sources:

Host ames.arc.nasa.gov

    Location: /pub
      DIRECTORY drwxr-xr-x        512  Jul 12 18:03  gnuplot
    Location: /pub/gnuplot
           FILE -rw-r--r--     714141  Jul 12 18:03  gnuplot3_38p1p8.tar.Z
           FILE -rw-r--r--    1166289  May 29 06:56  gnuplot3p38.tar.Z

Host iraun1.ira.uka.de

    Location: /gnu
           FILE -rw-r--r--    1166289  Jun 10 13:37  gnuplot3p38.tar.Z

Host monu1.cc.monash.edu.au

    Location: /pub
           FILE -rw-r--r--        397  Jun  9 11:56  gnuplot.README
           FILE -rw-r--r--    1166289  Jun  9 11:54  gnuplot3p38.tar.Z

Host adder.maths.su.oz.au

    Location: /misc
           FILE -r--r--rwx    1166289  Jun  5 12:10  gnuplot3p38.tar.Z

Randolph J. Herber, herber@fnalf.fnal.gov, +1 708 840 2966
(Speaking for myself and not for US, US DOE, FNAL nor URA.)
(Product, trade, or service marks herein belong to their respective owners.)
From: fred@poly2.nist.gov (Frederick R. Phelan Jr.)
Newsgroups: comp.sys.sgi
Subject: Re: Status of OpenGL?
Date: 24 Jul 92 12:37:23 GMT



Kipp Hickman <kipp@warp.asd.sgi.com> writes:

>Eventually on future machines there will be no IrisGL.

Is this correct?  I thought that IrisGL was still going
to be supported along side of OpenGL.

---
Fred Phelan
fred@poly2.nist.gov
/*___________________________________________________
   ____ __  ___  __    ___       ___        ___ 
  /__  /_/ /__  / /   /__/ /__/ /__   /    /__/ /\  /  
 /    / ( /__  /_/   /    /  / /___  /___ /  / /  \/
___________________________________________________*/
From: cliff@cs.arizona.edu (Cliff Hathaway)
Newsgroups: comp.sys.sgi
Subject: whither rpc.rstatd in 4.0.1?
Date: 29 Jul 92 23:10:53 GMT
Organization: U of Arizona, CS Dept, Tucson

There's a man page for rstatd which came with 4.0.1 (according to the creation
date on the file), but /usr/etc/rpc.rstatd isn't there.  One of our users claims
to have used rstatd in the past (before we upgraded to 4.0.1) on our 4D/340VGX.

If rpc.rstatd wasn't distributed with 4.0.1, is there something else which
performs the same functions?


-- 

    Cliff Hathaway
    Dept. of Computer Science (602)621-4291
    University of Arizona     cliff@cs.arizona.edu 	        (internet) 
    Tucson, Ariz. 85721	      {cmcl2,noao,uunet}!arizona!cliff	(uucp)
From: bergman@proline.cs.unc.edu (Larry Bergman)
Newsgroups: comp.sys.sgi
Subject: two cursor questions
Date: 22 Jul 92 02:55:37 GMT

I'm hoping that someone can help with a couple of questions about
graphics cursors.

  1) I want to use either the "hourglass" or the "watch" cursor
     in my code.  Are definitions of either available?

  2) I'm defining a non-default cursor in my program.  For some
     reason, the new cursor is only displayed in the window that's
     active when the cursor is defined.  Anywhere outside that
     window, I get the default cursor (arrow).  This doesn't
     seem to agree with the documentation.  Has anyone experienced
     this kind of behavior?  If so, how do I get a non-default
     cursor definition in other windows (or against the background).



Thanks for any help you can give me.

Larry Bergman
--------------------------------------------------------------------
-- 
Larry Bergman
bergman@cs.unc.edu
From: et11hkh@sbusol.rz.uni-sb.de (Rainer Zewe)
Newsgroups: comp.sys.sgi
Subject: Thomas Winter
Keywords: Indigo Question about feedback
Date: 21 Jul 92 09:12:14 GMT

By using Feedback on the Indigo, data appears in groups of six
floating point values. Is it possible to get the z-coordinate
in screen-coordinates, or is there an other possibility to get 
z-information (in screen-coordinates) of a pixel.

Thanks for answer !
From: bryan@pi.eai.iastate.edu (Bryan Manske)
Subject: Audio Questions
Originator: bryan@IRIX
Reply-To: bryan@pi.eai.iastate.edu (Bryan Manske)
Organization: EAI, Iowa State University, Ames, IA
Distribution: na
Date: Sat, 25 Jul 1992 16:38:27 GMT


Two quick questions about audio for one of our programmers.

1.  How do you set the default audio gain level in hardware on
    a 35 or indigo?  (nvram parameter?)


2.  Exactly how do the gain slots (0-255) map to real world db values?
    (linear relationship?)


And, I guess, a question from me.  I'm assuming 8-bit samples.
Is this correct?

Thanks in Advance.

Bryan



-- 
Bryan Manske  (515) 296-9908        . Images of sorrow,
Engineering Animation, Inc.         . pictures of delight,
bryan@pi.eai.iastate.edu            . things that go to make up a life...
#include <caveat_opinion.h>         . 
#include <standard_disclaimer.h>    . 	         Home by the Sea, Genesis
From: rdlankes@rodan.acs.syr.edu (Virtual Dave)
Newsgroups: comp.sys.sgi
Subject: SGO and Flip
Date: 23 Jul 92 16:02:16 GMT
Organization: Syracuse University, Syracuse, NY


I'm starting to work on the Iris and Showcase specifically. There is
a function that allows you to import SGO and Flip 3D models. My
question is, are there any utilities for converting other 3D formats
to these. i.e. dxf to SGO or flip.

This would be a great help.

Thanks in advance,


-------------------------------------------------------------------------------
|R.David Lankes (Virtual Dave)| Virtual Realities/Synaesthatic Communication  |
|  rdlankes@rodan.acs.syr.edu |     "We'll solve VIRTUALLY any problem"       |
-------------------------------------------------------------------------------
From: grege@chopin.asd.sgi.com (Greg Estes)
Newsgroups: comp.sys.sgi
Subject: Re: VGXT vs. Reality Engine
Date: 23 Jul 92 17:02:58 GMT
Organization: Silicon Graphics, Inc.

In article <jboyle.711872066@godzilla.cgl.citri.edu.au>, jboyle@cgl.citri.edu.au (James Boyle) writes:
|> I was just reading about the new graphics hardware for SGI called the 
|> Reality Engine. What are the differences (ie. capabilities & speed) between
|> that and the VGXT? Also when will this new hardware be available?
|> Just curious.
|> 
|> - James
|> jboyle@godzilla.cgl.citri.edu.au

RealityEngine was designed to provide an increase in performance
over VGXT, but more importantly, an increase that users would
really be able to take advantage of, as opposed to just faster
raw polygon numbers that you could only duplicate in a benchmark
situation.

So...

Most code will see an immediate 2-4x speed improvement due
to the MIMD architecture and extensive use of FIFOs

Flat-shaded t-meshes run about the same speed as a VGX/VGXT

Textured, anti-aliased polygons run *a lot* faster

For example,


T-meshes		VGXT	RealityEngine

Flat-shaded, unlighted
Z-Buffered, Texture
mapped Anti-aliased	35K	600K

Flat-shaded, lighted
Z-buffered		780K	820K

Flat-shaded, unlighted
no Z-buffer		1.1M	1.1M


Pixel Fill

Texture mapped, tri-
linear interp, Mip-
mapped anti-aliased	44M	320M
---

In addition, RealityEngine features
 
12-bit per channel color RGBA (96-bit double-buffered)
Real-time multi-sample anti-aliasing with no performance penalty
1600 x 1200 and HDTV resolutions
21" multi-sync monitors
New texture mapping modes, including bicubic interpolation and
	3D textures
4MB of dedicated texture memory (VGXT- 512K)
Stereo in a window
NTSC/PAL/S-Video output
etc.

Shipping September.
Any SGI salesperson could get you more specs.

G. Estes
Product Manager
Advanced Graphics & Video
Silicon Graphics
From: jack@cwi.nl (Jack Jansen)
Newsgroups: comp.sys.sgi
Subject: New version of dynamic loader available
Date: 31 Jul 92 09:31:29 GMT
Organization: CWI, Amsterdam

I've made a new version of dl, my dynamic loader for Irix, available.
It contains a few bug fixes and some extensions that people asked for.
Most importantly, incremental loading now works (i.e. if you load two
modules dynamically the second module will see the externals defined
by the first one).

Also, there is a new interface if you need the address of more than
one routine from the newly loaded object file.

dl is available for FTP access on ftp.cwi.nl, file /pub/dl-1.4.tar.Z.
If you don't have ftp access I can mail it to you.
-- 
--
Jack Jansen        | If I can't dance I don't want to be part of
Jack.Jansen@cwi.nl | your revolution             -- Emma Goldman
uunet!cwi.nl!jack    G=Jack;S=Jansen;O=cwi;PRMD=surf;ADMD=400net;C=nl
Newsgroups: comp.sys.sgi
From: root@sanger.chem.nd.edu (Doctor Math)
Subject: Re: sendmail and timed problems. [2nd bug FIXED]
Keywords: sendmail-lost mail-timed-machine not responding
Organization: University of Notre Dame
Date: Mon, 27 Jul 1992 17:50:45 GMT

In article <nqbqoig@sgi.sgi.com> roberts@nimrod.wpd.sgi.com (roberts) writes:
>Whoever this "Doctor Math" is he's no sendmail.cf programmer.  (This
>statement is not intended as a slight.  Most normal humans would, rightly,
>take it as a compliment.)  I repeat, the above change should NOT be made
>to your sendmail.cf file.  "Doctor Math" would you PLEASE STOP telling
>people to do this.

I'll take that as a compliment. I did pass it on to Pat Hurt because he
had the exact symptoms that I did when I installed 4.0.1 and sendmail
didn't work (yes, I tried rebuilding the frozen configuration file).
I've been using a sendmail.cf from a Sun Sparcstation for the last few
months, and it works fine; I gave up on the SGI-supplied sendmail.cf when
I couldn't get it to work for me. Various people have told me that it's
infinitely easier to modify a working sendmail.cf...
I am now testing the stock 4.0.1 sendmail.cf. It isn't working. It is
failing to deliver mail to another user on THIS machine. I've been waiting
five minutes. Now, I'll reset sendmail with the Sun-derived sendmail.cf...
Mail to another user on this machine happens instantly (using Mail -v to
watch in both cases). The SGI-supplied sendmail.cf from 4.0.1 is stock,
the only changes being those where my local domain information gets plugged
in. If SGI's sendmail.cf doesn't have problems, I'd like to know what
those problems aren't so I can be sure not to fix them.

Newsgroups: comp.sys.sgi