From: ed_heinrich@npd.novell.com
Newsgroups: vmsnet.internals
Subject: Re: ALPHA MB instruction
Date: 15 Apr 92 14:54:59 GMT
Organization: Macro32<==>Vmsnet.Internals Gateway
X-Gateway-Source-Info: Mailing List


In article <1992Apr15.202204.1669@zl2tnm.gen.nz>. don@zl2tnm.gen.nz writes:

>In article <1992Apr14.112350.860@beckman.com>, dsroberts@beckman.com writes:
>> What this sounds like to me is that the MB command (and associated spin loop)
>> gives you is the same type of control as a VAX spinlock but for shared data
>> regions of your own creation, and without the annoyance of going into kernel
>> mode.
>
>MB is a primitive that makes spinlocks work in multiprocessor Alphas.  It
>also has applications when talking to device registers etc.  Basically,
>without MB, the operations (my Alpha book has been borrowed, so I can't
>quote the assembler mnemonics):
>
>        move a to x
>        move b to y

>might get re-ordered by the hardware to do the b->y write *before* the
>a->x write.  If x and y are device registers, this would be a Bad Thing.
>If x were a spinlock and y some shared data, that would also be a Bad
>Thing.  On the other hand, if the x & y were in different memory banks
>and the bank which contained x was still being written to, writing to y
>while x was busy might just help performance a little.
>
>So, you change the sequence to:
>
>        move a to x
>        MB
>        move b to y
>
>and everybody's happy, since we now know that the a->x move will happen
>before the b->y move.
>

Many RISC architectures, including ALPHA, obtain part of their performace
gains by optimizing access to memory.  This optimization often means that,
as Don stated above, Y may be updated prior to X, even though the instruction
to update X was issued first.  In the VAX architecture, reads and writes to
memory CAN be reordered with respect to each other, but two reads or two writes
MUST execute in the order they are issued.  (This read/write disordering is
the reason for VAX INTERLOCKED instructions, which guarantee the order of the
accesses.)

On Alpha, reads can be disordered with respect to other reads, as can writes
to other writes.  One example of how data could be moved not in the issuance
order, (using the above example) is when the value of A is not in cache while
the contents of B are in cache.  Because A is not in cache, it must first be
read into cache before it is copied to X.  In the meantime, B has been copied
to Y.

>> I was hoping some of the internals guru's who have reviewed ALPHA might
>> elaborate on how this concept is similar or different from the VAX spinlock.
>
>Spinlocks are a higher level construct to what the MB instruction deals
>with.  You can use it to implement spinlocks, but the issues about who
>can create one where and when are going to be just as OS dependent as
>they are with the VAX.
>
>

MB instructions will allow spinlocks to be correctly implemented by allowing
"test and set" algorithms that perform similiar functions as the VAX
interlocked hardware instructions to be done in serveral Alpha instructions.
Spinlocks will STILL, in SMP versions, be the mechanism for synchronization
to OS data structures.  The MB instruction will NOT act as a spinlock by
preventing access to a field, rather it will insure that other processors in
a SMP Alpha system are presented with a view of memory consistent with the
instruction sequences issued.


>Don Stokes, ZL2TNM (DS555)                       don@zl2tnm.gen.nz (home)
>Network Manager, Computing Services Centre           don@vuw.ac.nz (work)
>Victoria University of Wellington, New Zealand             +64-4-495-5052

-------------------------------------------------------------------------------
Ed Heinrich, Novell, Inc.       Sandy, Utah
ed_heinrich@npd.Novell.COM

                "it's NOT the kill, it's the thrill of the chase"
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