From: dmw@taurus.ece.cmu.edu (Hank Walker)
Subject: Defect and Fault Tolerance Workshop
Originator: dmw@taurus.ece.cmu.edu
Keywords: defect, fault tolerance
Reply-To: dmw@ece.cmu.edu
Organization: Electrical and Computer Engineering, Carnegie Mellon
Date: Tue, 18 Aug 1992 20:40:59 GMT


                      1992 IEEE International Workshop on
                  Defect and Fault Tolerance in VLSI Systems
                               sponsored by the
            IEEE Computer Society, TC on Fault Tolerant Computing
                      in cooperation with the TC on VLSI

                              November 4-6, 1992
                         Fairmont Hotel, Dallas, Texas

                                FINAL PROGRAM

The goal of the workshop is to provide a discussion forum for researchers
and  practitioners dealing with digital, analog, and mixed  VLSI integrated
circuits.  All aspects of design, manufacturing, test,  reliability, and
availability which are  affected by defects during manufacturing and by
faults during system operation  are of interesst.  Presentations  will focus
on the areas of fault and yield models, fault tolerance, test and and
reconfiguration.

        General Chair                   Technical Program Chair

        D.M.H. Walker                   F. Lombardi
        Department of ECE               Department of C.S.
        Carnegie Mellon University      Texas A&M University
        USA                             USA
        Phone : (412) 268-8522          Phone:  (409) 845-5465
        Email:  dmw@ece.cmu.edu         Email:  lombardi@cs.tamu.edu

Program Committee

D. Blough, UC Irvine, USA              M. Rivier, IBM, France
H. Ito, Chiba University, Japan        G. Saucier, INPG, France
A.V. Ferris-Prabhu, IBM, USA           Y. Savaria, Ecole Poly., Canada
W.K. Fuchs, Univ. Illinois, USA        K. Somani, Univ. Washington, USA
V.K. Jain, Univ. South Florida, USA    C.H. Stapper, IBM, USA
I. Koren, Univ. Massachussetts, USA    R. Stefanelli, Pol. Milano, Italy
R.M. Lea, Brunel Univ., UK             E. Swartzlander, Univ. Texas, USA
R. Melhem, Univ. Pittsburgh, USA       I.P. Teixeira, INESC, Portugal
J. Pineda de Gyvez, Texas A&M, USA     S. Tewksbury, West Virginia Univ., USA
J. Trihle, SGS-Thomson, France

Industrial Subcommittee

R. Collins, DEC, USA                   J. Hammond, Intel, USA
D. Dance, Sematech, USA                C.H. Stapper, IBM, USA
C.M. Drum, AT&T Bell Labs, USA


LOCAL INFORMATION

The workshop will be held at the Dallas Fairmont Hotel, 1717 N. Akard St.,
Dallas, Texas 75201, Tel.(214) 720-2020, FAX (214) 720-4015.  The Dallas
Fairmont Hotel is located in the Arts District in the heart of downtown
Dallas.  The Fairmont is within five minutes of the Convention Center and
Market Complex, and close to the Dallas Museum of Art, and the Morton H.
Meyerson Symphony Center.

Dallas has an average temperature of 67-46 Fahrenheit (19-8 Celsius), and an
average  rainfall of 2.2 inches in the month of November.  Getting around in
Dallas is very easy, transportation services include auto rentals, taxis
($1.50 base rate + $1.2 for each additional mile), limousines, handicapped
transportation, "Dallas Area Rapid Transit (DART) and even horse-drawn
surreys.  Dallas is a major transportation hub in the U.S.  The city is
located, via air, less than three hours from any major city in the
continental U.S., and is  easily accessible from destinations in Europe and
Asia via its international airport.  Not to be overlooked is the area's
comprehensive system of groud transportation.  Four interstate highways and
many more national and state highways make Dallas a leading hub for
automoblie transportation.  The city is also also served by Amtrak and
Greyhound.  Dallas has two airports:  Love Field pand a major airport
located within the city limits and Dallas/Fort Worth International Airport.
Dallas/Fort Worth International is the nation's largest airport (bigger than
Manhattan Island).  It is currently the second busiest airport in the world
-and one of the most modern.  In addition to flights within the U.S., every
day there are non-stop flights to and from  all major international
destinations.  Some carriers are: American Airlines, Continental Airlines,
Delta Airlines, British Airways, and TWA.

The Fairmont is only minutes away from North Dallas, Fort Worth, and both
Love Field and Dallas/Fort Worth airports.  Buses are available to the
Fairmont from both airports.

REGISTRATION

Workshop registration includes admission to all sessions, breaks and
panels and a copy of the proceedings. 

IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems
Workshop Registration

First Name___________________Last Name_______________________________________

Company/Institution__________________________________________________________

Address______________________________________________________________________

City___________________ State/Province_____ Postal Code_____ Country_________

Email____________________ Phone____________________ Fax______________________

Circle Fee              Before October 16, 1992    After October 16, 1992

IEEE Member                    US $250                     US $325
Non-Member                     US $300                     US $375
IEEE Student Member            US $100                     US $100
IEEE Member No.                                

Payable by check or money order in U.S. dollars.
Make check payable to "IEEE Int'l Workshop on Defect and Fault Tolerance 
in VLSI Systems"

Send above information and check, by October 16, 1992, to:

        Dr. H. Y. Youn, DFT92 Registration Chair
	University of Texas at Arlington
	CSE Department
	Arlington, TX  76019-10013				
	Phone:  (817) 273-3602
	FAX:    (817) 273-2548				
	Email:  youn@cse.uta.edu

A limited number of rooms have been reserved at the Fairmont Hotel at
a group rate of $85 per night (single or double).  To reserve a room 
contact directly the Fairmont Hotel at 1-800-527-4727 (mention IEEE 
Computer for the special rate).

TECHNICAL PROGRAM

WEDNESDAY, NOVEMBER 4, 1992

7:30 REGISTRATION

8:00-8:30 a.m. 

Welcome - Plenary Session

Welcome
D.M.H. Walker, Carnegie Mellon University

Opening Remarks
F. Lombardi, Texas A&M University

Opening Session

8:30 - 9:30 a.m.
Invited Speaker:  M. Lea
Brunel University, United Kingdom

9:30 - 10:00 a.m.  BREAK

10:00 - 12:00 a.m.
Session 1:  Defect and Yield Modeling
Chair:  C.H. Stapper, IBM, Essex Junction

1.1L  Defect Density Assessment in an Integrated Circuits Fabrication L
R.E. Harris, Rockwell International, USA

1.2L  Optical Inspection of Wafers Using Large Area Defect Detection and
Sampling
Stuart L. Riley, IBM, USA

1.3L  Comparing Results from Defect Tolerant Yield Models
C. Thibeault and Y. Savaria
Universite du Quebec a Montreal, Ecole Polytechnique de Montreal, Canada

1.4L  Defect Level Estimation for Digital ICs
J.J.T. Sousa and J.P. Teixeira, INESC, Portugal

12:00 - 1:30 a.m.  LUNCH

1:30 - 3:00 p.m.
Session 2:  Fault Tolerant Arrays
Chair:  J.H. Kim, University of S.W. Louisiana

2.1L  Efficient Bi-Level Reconfiguration Algorithms for Fault Tolerant Arrays
R. Libeskind-Hadas, N. Shrivastava, R.G. Melhem, and C.L. Liu
University of Illinois at Urbana-Champaign,
University of Pittsburgh, USA

2.2L  A Real-Time Reconfiguration Algorithm for Fault-Tolerant VLSI and
WSI Arrays
H. Al-Assad and M. Vai
Northeastern University, USA

2.3S Fault Spectrum Analysis of Fast Spare Allocation in Reconfigurable Arrays
W. Che and I. Koren
University of Massachusetts, USA

2.4S  Recognition of Catastrophic Faults
A. Nayak, L. Pagli and N. Santoro
Carleton University, University of Pisa, Canada and Italy

3:00 - 3:30 p.m.  BREAK

3:30-4:30 p.m.
Session 3:  Testing
Chair:  J. Muzio, University of Victoria

3.1L  Bridging Faults Modeling and Detection in CMOS Combinational Gates
G. Buonanno and D. Sciuto
Politecnico di Milano and Universita di Brescia, Italy

3.2S Scan-Based Testability for Fault-Tolerant Architectures
A. Dehon
MIT AI Lab, USA

3.3S  Time Complexity of Systolic Array Testing
N. Faroughi
California State University, USA

4:30-5:30 p.m.
Session 4:  Concurrent Error Detection
Chair:  W. Shi, University of North Texas

4.1S  Concurrent Error Detection in ALU's by Recomputing with Rotating
Operands
J. Li and E. Swartzlander
University of Texas at Austin, USA

4.2S PLA Decomposition to Reduce the Cost of Concurrent Checking 
D. Wessels and J.C. Muzio
University of Victoria, Canada

4.3L  Concurrent Error Detection in Artificial Neural Networks:  The Use of
AN+B Codes
V. Piuri, M. Sami and R. Stefanelli
Politecnico di Milano, Italy

8:00 - 9:00 p.m.  PANEL DISCUSSION

THURSDAY, NOVEMBER 5, 1992

8:30 - 9:30 a.m.
Invited Speaker:  G. Saucier
INPG/CSI, France

9:30 - 10:00 a.m.  BREAK

10:00 - 12:00 a.m.
Session 5:  System Fault Diagnosis
Chair:  R. Melhem, University of Pittsburgh

5.1L  Probabilistic Diagnosis in Wafer-Scale System
J. Wang and A.K. Somani
University of Washington, USA

5.2S  Probabilistic Analysis of Memory
Reconfiguration in the Presence of Coupling Faults
C.P. Low and H.W. Leong
National University of Singapore, Singapore

5.3S  On Fault Probabilities and Yield Models for Analog VLSI Neural Networks
P.M. Furth and A.G. Andreou
The John Hopkins University, USA

5.4L  Nondeterministic Adaptive Routing Techniques for WSI Processor Arrays
D.C. Blight and R.D. McLeod
University of Manitoba, Canada

12:00 - 1:30 p.m.  LUNCH

1:30 - 3:00 p.m.
Session 6:  Defect and Fault Modeling
Chair:  E. Swartzlander, University of Texas, USA

6.1L  Special Fault Simulation and the Saturation Effect
C.H. Stapper
IBM Technology Products, USA

6.2L  Modeling of 3-dimensional Defects in Integrated Circuits
J. Pineda de Gyvez and S. Dani
Texas A&M University, USA

6.3L  Tolerance of Delay Faults
D.M.H. Walker
Carnegie Mellon University, USA

3:00 - 3:30 p.m.  BREAK

3:30 - 5:30 p.m.
Session 7:  Fault Tolerant Systems
Chair:  S. Horiguchi, JAIST

7.1L  Design Rule Centering for Row-Redundant Content Addressable Memories
W.B. Noghani and I.P. Jalowiecki
Brunel University, United Kingdom

7.2L  A WSI Hypercube Design Using Shift Channels
H. Ito and E. Hosoya
Chiba University, Japan

7.3L  An Efficient Algorithm-Based Fault Tolerance Design with Extended
Rearranged Hamming Checksum
C.G. Oh, H.Y. Youn and V.K. Raj
University of Texas at Arlington, USA

7.4L  Time Redundant Adders and Multipliers
Y.M. Hsu and E. Swartzlander
University of Texas at Arlington, USA

8:00 - 9:00 p.m.  GROUP DISCUSSION

FRIDAY, NOVEMBER 6, 1992

8:00 - 9:00 a.m.
Session 8:  Defect Tolerance
Chair:  J. Pineda, Texas A&M University

8.1L Application of Yield Models for Semiconductor Yield Improvement
Daren Dance and Richard Jarvis
SEMATECH, AT&T, USA

8.2L Analysis of Defect Maps of Large Area VLSI IC
I. Koren, Z. Koren and C.H. Stapper
University of Massachusetts and IBM, USA

9:00 - 10:00 a.m.
Session 9:  Fault Tolerant Arithmetics
Chair:  T.R. Rao, University of S.W. Louisiana

9.1L A Fast Pipelined Complex Multiplier:  The Fault-Tolerance Issues
L. Breveglieri, V. Piuri and D. Sciuto
Politecnico di Milano and Universita di Brescia, Italy

9.2L High Speed Parallel Input-Output Bit-Sliced Fault-Tolerant Convolvers
L. Dadda and M. Sami
Politecnico di Milano, Italy

10:00 - 10:30 a.m.  BREAK

11:00 - 12:00 a.m.
Session 10:  System Testing
Chair:  D. Sciuto, Universita di Brescia

10.1L Practical Application of Automated Fault Diagnosis at the Chip and
Board Levels
M. Maccanelli, A. Halliday, B. Bell, D. Steiss and K.M. Butler
Texas Instruments, USA

10.2L A Universal Self-Test Design for Chip, Card and System 
D.M. Wu and R. Doney
IBM, Austin, USA

12:00 - 12:45 a.m.
Session 11:  Routing for Defect Tolerance
Chair:  H.Y. Youn, University of Texas at Arlington

11.1S Improved Layer Assignment for Packaging Multichip Modules
Cheng-Hsi Chen, M.H. Heydari, I.G. Tollis, and C. Xia
The University of Texas at Dallas, USA

11.2L New Routing and Compaction Strategies for Yield Enhancement
V.K.R. Chiluvuri and I. Koren
University of Massachusetts, USA

1:00 p.m. STEERING COMMITTEE MEETING

L = Long Presentation
S = Short Presentation

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