From: stein@decsim.enet.dec.com
Newsgroups: misc.jobs.offered
Subject: Full-Custom VLSI CAD Engineering, Boston area
Keywords: CAD, VLSI, DESIGN
Date: 28 Jan 93 15:02:23 GMT
Reply-To: JGIROUARD@OBSESS.ENET.DEC.COM
Distribution: na
Organization: Digital Equipment Corporation




                       DIGITAL EQUIPMENT CORPORATION

                          HUDSON, MASSACHUSETTS


                         SEMICONDUCTOR OPERATIONS

SEMICONDUCTOR OPERATIONS, LOCATED IN HUDSON, MA., HAS SEVERAL OPENINGS
IN THE SEMICONDUCTOR ENGINEERING GROUP (SEG).  SEG PROVIDES MOST OF THE
MOS (CMOS) CUSTOM SILICON DESIGN EXPERTISE WITHIN DIGITAL.  OUR CHIPS
ARE VIRTUALLY IN EVERY DIGITAL PRODUCT, AND OUR SOFTWARE IS USED
THROUGHOUT DIGITAL.

WE HAVE SEVERAL OPENINGS IN THE COMPUTER AIDED DESIGN GROUP. (CAD)

IF YOU ARE INTERESTED IN THE FOLLOWING OPENINGS, PLEASE SEND YOUR 
RESUME VIA EMAIL OR FAX TO:

                  MS. JAYE GIROUARD  HL2-2/K13
                  DIGITAL EQUIPMENT CORPORATION
                  77 REED ROAD
                  HUDSON, MA. 01749
                  FAX (508)568-4681 OR EMAIL JGIROUARD@OBSESS.ENET.DEC.COM

***PLEASE BE ADVISED THAT WE ARE ACCEPTING ONLY U.S.CITIZEN'S OR PERMANENT
RESIDENT'S****  PLEASE INDICATE INTEREST BY MENTIONING POSITION CODE.

POSITION CODE (WP) (3)  SIGNAL INTEGRITY 

 1)  Applicant will work as part of a module design team in SEG and will
     be responsible for integrating signal integrity tools into their
     CAD environment and providing support for these tools.   Also be
     responsible for understanding module design and signal integrity
     problems, developing new programs, debugging code, and supporting
     CAD tools.

     MS in EE or Physics.  Experience in module-level signal integrity
     analysis.  Good knowledge of "C" programming and good communication
     skills.

2)   Hardware engineer responsible for developing and supporting Signal
     Integrity CAD tools (AWEsim, INSEIN, MODULEX, AND MODCrotic) for
     simulation and electrical analysis.  Responsibilities will include
     developing new algorithms, coding, testing, and supporting the tool.

     MS in EE or Physics with experience in "C" programming, and a strong
     background in circuit simulation, numerical/math analysis.

3)   Person will be responsible for supporting and improving circuit
     simulation tools, including SPICE.  Will be working as part of a
     project team and independently, to meet specific project goals,
     including supporting the tool, developing new algorithms, coding,
     and testing.

     MS in EE, CS or Physics with experience in FORTRAN and "C".  Strong
     background in circuit simulation, numerical analysis, device
     physics and mathematical analysis.


POSITION CODE (AD) (2)  AUTOMATIC LAYOUT TOOLS

 1)  Position involves development of tools for automatic layout of
     integrated circuits in the CMOS technology.  Candidate will work
     in the CAD group as part of a software development team that 
     interacts heavily with circuit and layout designers.  The work
     done by the group involves creation of totally new tools, 
     enhancements to existing tools, and direct support to our users.
     The key goal of our automatic layout tools is to shorten the 
     layout schedules for chips critical to Digital hardware products.

     Applicant should have a solid base in software development,
     (knowledge of a high level language, preferably "C", operating
     systems, debuggers, testing, etc). Knowledge of one or more
     areas of automatic layout such as channel routers, global
     routing algorithms, placement algorithms such as min-cut or
     simulated annealing, arrayed structures such as RAM/ROM/PLA
     generators) is necessary.  Experience doing actual chip layout
     with tools such as Berkeley's MAGIC would be a plus.

     BS or MS degree in EE or CS

2)   LOGIC SYNTHESIS TOOLS

     This position involves development of tools for logic synthesis,
     that is, generating logic schematics starting from high level
     behavior descriptions.  Candidate will work in the CAD group as
     part of a software development team that interacts heavily with
     architects and circuit designers.  Work done in this group involves
     creation of new tools, enhancements to existing tools, adapting
     university produced software, and direct support to our user base.

     Applicant should have a solid base in software development.  
     Knowledge of one or more areas of logic design and synthesis, (logic
     minimization algorithms, rule-based logic transformations, translation
     of behavior to boolean equations, mapping of boolean equations to
     technology libraries, PLA minimization techniques, finite state
     machine encoding techniques, timing analysis) is necessary.
     Familiarity with a university system, such as Berkeley's MISII/SIS
     or Colorado's BOLD would be a plus.