From: Mark Kovarski <kovarski@zooid.guild.org>
Subject: Re: What's wrong with this?
Organization: ZOOiD BBS
Date: Tue, 22 Dec 1992 16:30:53 GMT

markh@csd4.csd.uwm.edu (Mark) writes:
>In article <1992Dec15.205835.643@zooid.guild.org> Mark Kovarski <kovarski@zooid.guild.org> writes:
>>ON BOARD PARITY ERROR                                                          
>>ADDR (HEX) = (xxxx:xxxx)                                                       
>>SYSTEM HALTED.                                                                 
>>                                                                               
>>This apparently appears when the following is run:                             
>>                                                                               
>>mov al,74                                                                      
>>out 43,al                                                                      
>>mov al,ff                                                                      
>>out 41,al                                                                      
>>mov al,ff                                                                      
>>out 41,al                                                                      
>>ret                                                                            
>
>or...
>
>mov al,74   ;;; Timer control <- 74 =
>out 43,al   ;;;  Channel 1(40) + 16 bit load (30) + Mode2 (04) + Binary (00)
>
>mov al,ff
>out 41,al
>mov al,ff
>out 41,al   ;;; Timer1 <- 2^16 - 1 (1/18 second)
>
>ret
>
>oops.  You just set the memory refresh timer to 50,000 microseconds.


Let me see if I get it right this time...

The 8284 supplies the 8253 a 1.19 MHz pulse. Each Interrupt occurs 18.2 times
per second. This comes to 54.92 ms for each Interrupt. This is for a count of
65,536. If this is the default value that is used, this would mean that it
still wouldn't work. Like some people pointed out, most DRAMS have to be
refreshed every 15 ms, there are some that go up to 160 ms but 15 ms are more
common. So if the 18.2 per second is true and is used as the default, how
does the DRAM in the PC keeps working? Or is there a different value that is
used? Also, according the Intel data book, the largest possible value is not
0FFh but 00 (2^16) for binary count. For BCD it's 2^14.
Here is an example, please correct if I am wrong:

I will take the 1M*1 Motorola DRAM. The array is 1024 rows by 1024 columns,
but electrically it operates like half array of 512 rows by 1024 columns.
During the refresh, every row is treated as if it runs through both halfs of
the array, refreshing 2048 columns (bit cells) per row. The refresh time is
specified as following:

512 Cycles Refresh  MCM511000A = 8 ms
                    MCM51L1000A = 64 ms

According to Motorola, the design will allow to refresh the entire array since
only 512 rows need to be accessed instead of 1024. They also specify that the
refresh can occur as a single burst, refreshing the entire array in one "shot"
or the refresh can occur distributed. Hence, if we take this particular DRAM,
512 rows* 165 ns to refresh each row=84.48 microseconds. Someone pointed out
that when the value 0xFFFF is loaded into 41h, it would take 20 seconds to
refresh one DRAM, could this person (Christian, I believe)  please ellaborate
on this matter? Christian assumed that there were 512 rows, and since there
refresh rate is set at 18.2, did he simply devide 512/18.2=28.13?

If someone can provide a fully explained example, I would greatly appreciate
it. Thanks.

Mark K.