HDTenEightyP/NetNews huggingface dataset:
From: bb11807@medtronic.COM (Brian A. Blow)
Subject: Re: Impact of minimal transistor width 3 or 4 instead of 2?
Organization: Medtronic, Inc.
X-Newsreader: TIN [version 1.1 PL8]
Date: Tue, 26 Jan 1993 14:33:17 GMT

Ronald Hindmarsh (ronald@cs.tu-berlin.de) wrote:

: I am working on a CMOS-VLSI layout generator for digital circuits. 

: For topological reasons I would like to limit the MINIMUM w/l
: of a MOS transistor to 3 or 4 (in some physical design rules
: of a process I have seen a minimal transistor width of 2).

: Do you think, from your experience, this would have a strong
: impact on the performance or the power consumption of a circuit?

Using wider transistors will mean that you will have to drive larger
gate capacitances.  This will lead to a slightly increased power consumption.

If you use wider transistors to drive these gates, you will have a
greater charging/discharging current to do this, so circuit speed should 
not significantly change.


Brian Blow                         brian.blow@medtronic.com
Medtronic, Inc.                    (612) 574-4030
Minneapolis, MN
Newsgroups: comp.lsi,comp.lsi.cad
From: ssave@ole.cdac.com (The Devil Reincarnate)
Subject: Re: Silicon Compiler chip-sets
Organization: CDAC, WA
Date: Thu, 28 Jan 1993 21:10:03 GMT

  Can someone give me some leads into companies offering
Silicon Compiler chip-sets, ie: accelerator chips/cards/boxes
which you can plug into your system to increase performance
of placement/routing algorithms/software?
  Leads to papers/journal articles appreciated as well.

  Similar to what Zycad (?) did with DRC/LVS etc accelerator
boxes.


Thanks,
-S
ssave@ole.cdac.com
From: paul@canuck.Berkeley.EDU (Paul Cohen)
Newsgroups: comp.lsi
Subject: Re: OCTTOOLS QUESTION
Date: 28 Jan 1993 02:19:47 GMT
Organization: University of California at Berkeley
Distribution: world
NNTP-Posting-Host: canuck.berkeley.edu
Keywords: OCTTOOLS, Musa, Magic.

In article <1k2t9tINNd81@coral.bucknell.edu> lokanthn@bucknell.edu (arumugamangalam lokanathan GR) writes:
>I have had the following problem with OCTTOOLS for a while now :
>
>I CANNOT SIMULATE PHYSICAL OCT FACETS USING MUSA.
>

The problem is that musa is a simulator, not an extractor. The
physical viewtype does not contain information for musa to use to do
the logic simulation. The database includes layer information, polygon
(or rectangle) information, etc. Musa does not know that the fact that
poly crosses active is a transistor.

If you want to use the nand gate in a desing, and simulate that higer
level design, you will need to add simulation properties. Please see
the VEM physical editing tutorial shipped with release 5.1 ffor
information on how to do this.


-- 
Paul B. Cohen				| paul@aha.com
Advanced Hardware Architectures, Inc.	| paul@ic.berkeley.edu
P.O Box 9669				| (208) 883-8000 (v)
Moscow, ID 83843			| (208) 883-8001 (f)
Xref: sparky comp.lsi:814 comp.lsi.cad:1353 news.answers:5482
From: robert@koko.csustan.edu (Robert Zeff)
Newsgroups: comp.lsi,comp.lsi.cad
Subject: New version of Spice for WIndows NT / Windows 3.1 uploaded
Date: 22 Jan 93 17:38:13 GMT
Organization: CSU, Stanislaus

I uploaded a bug fix of my spice circuit simulator for 
Windows NT / Windows 3.1

If your target system is Windows NT, get the spice41.txt, spice41.zip,
& spice42.zip

If your target system is Windows 3.1, also get spice43.zip, which contains
the Win32s components necessary for running Windows NT binaries on a
Windows 3.1 system.

You can get it at wuarchive.wustl.edu.

It's in the /pub directory.  Don't get the spice4.zip, which is old.


-- 
Robert Zeff
    (209) 521-1448
FAX (209) 522-5866
C$ERVE: 70323,1251
From: lokanthn@bucknell.edu (arumugamangalam lokanathan GR)
Newsgroups: comp.lsi
Subject: OCTTOOLS QUESTION
Date: 26 Jan 1993 08:38:21 GMT
Organization: Bucknell University, Lewisburg, PA
Distribution: world
NNTP-Posting-Host: acrux.cs.bucknell.edu
Keywords: OCTTOOLS, Musa, Magic.

I have had the following problem with OCTTOOLS for a while now :

I CANNOT SIMULATE PHYSICAL OCT FACETS USING MUSA.

For example :

I laid out a simple nand gate in  "Magic" and using "mag2oct" I got a physical

octfacet called "nand:physical". 

nand:physical has inputs "a" and "b" and output "O".

The properties of the cell as shown by the command "bdnet -n nand:physical" are

________________________________________________________________
 
MODEL "nand":physical;

TECHNOLOGY scmos;
VIEWTYPE PHYSICAL;
EDITSTYLE PHYSICAL;
INPUT "a";
INPUT "b";
OUTPUT "O";
GROUND "GND!";
SUPPLY "Vdd!";

ENDMODEL;

___________________________________________________________________

When I simulate this cell with musa, "O" is "unknown" regardless of "a" and "b".

Further I can assign a value to "O", which means musa is treating "O" as any other

input. 



ARE THERE ANY OCTTOOLS EXPERTS WHO KNOW OF A SOLUTION TO THIS PROBLEM ?

I would appreciate any help you have to offer.

You are welcome to email your suggestions directly to me at

lokanthn@pleiades.cs.bucknell.edu

Loki 



Newsgroups: comp.lsi.testing
From: npaizis@frx177.intel.com (Nick Paizis - EPG ~)
Newsgroups: comp.lsi.testing
Subject: readership
Date: 26 Jan 93 20:58:09 GMT
Organization: Intel Corporation

Count me in.

Nick Paizis
Developement Engineering
Intel Corp

Folsom Ca
Newsgroups: comp.lsi.testing
From: arj@quince (Andy Jackson)
Subject: JTAG
Organization: Olivetti Research Ltd, Cambridge, England.
X-Newsreader: TIN [version 1.1 PL6]
Date: Thu, 21 Jan 1993 08:51:13 GMT


I am just starting to investigate JTAG and would be interested to hear
any comments/information related to this, particularly:

	1)	Sources of JTAG compatible parts

	2)	Experiences of using JTAG

	3)	Example source code for driving JTAG ports.

	Thanks,

			Andy..

--------------------------------------------------------------------------
  Andy Jackson - arj@cam-orl.co.uk - phone 0223-343308 - fax 0223-323542
    Olivetti Research, 24a Trumpington Street, Cambridge, UK, CB2 1QA
        My brothers stoned - move the bar and he'll fall over
      Doesn't like to fight, just drinks to kill - Clive Wraight
--------------------------------------------------------------------------
Newsgroups: comp.lsi.testing
From: brad@titan.austin.ibm.com (Brad Garton)
Subject: RE: JTAG 
Date: Thu, 21 Jan 1993 22:49:17 GMT
Reply-To: brad@titan.austin.ibm.com  (Brad Garton)
Organization: IBM Advanced Workstation Division
Keywords: JTAG

I am using JTAG parts from TI, Xilinx and Motorola in a system 
test application.

Don't yet have a lot of experience with JTAG except that 
the costs are still a little hard to justify in extremely 
1.  you are able to do away with somephase of testing ( ICT - 
    or some functional) 
2. I'ts use in the field can be demonstrated to save maintenance costs.

It is still a kind of chicken and egg problem in that without it 
being implemented you are not going to prove 1 or 2.
       
Can't give out source code, sorry.

Brad  
___________________________________________________________
| Brad Garton  (512) 838-1333 | brad@titan.austin.ibm.com |
| I speak for myself not IBM  | VNET: GARTON AT AUSTIN    |
+---------------------------------------------------------+
From: kumar@cleaver.mti.sgi.com (Kumar Venkat)
Newsgroups: comp.lsi.testing
Subject: Re: Boundary Scan
Date: 26 Jan 93 20:16:56 GMT
Organization: Silicon Graphics, Inc.

In article <1993Jan26.180613.4943@cbis.ece.drexel.edu>,
dspstu18@cbis.ece.drexel.edu (Anthony Sama) writes:
|> Has anyone utilized JTAG boundary scan to perform tests of system
|> logic?
|> Specifically, I would like to do the following:
|> 1) Scan in test data along the boundary scan register.
|> 2) Allow the system to run for one clock cycle using data from the
|> boundary
|> scan register as input to the system logic.
|> 3) Record the system outputs in the boundary scan register.
|> 4) Scan out the results.
|> 
|> My problem is with steps 2) and 3) above.
|> If I use the Internal test, how do I allow the sytem to run for one
|> clock
|> cycle? Since the system clock is an input, it is unavailable. Do I
|> simply
|> let the system run for one cycle of TCK in the Run-test/Idle state of
|> the
|> TAP controller. Is there another way to do this without using the
|> Internal
|> test? Perhaps using the Sample test in conjunction with external system
|> clock controls?
|> 
|> Any help/pointers/suggestions would be greatly appreciated!
|> 
|> Anthony Sama
|> Drexel University


In INTEST, you can use a boundary-scan register to supply the clock
instead of either system clock or test clock. This register will have
to be multiplexed in at the source of the on-chip clock network. This
means you would have to scan once for each phase of the clock, and 
scan the input signal values separately to provide enough setup and
hold with respect to the scanned clock.


-Kumar Venkat
Silicon Grpahics
kumar@mti.sgi.com
Newsgroups: comp.lsi.testing,comp.lsi,comp.lsi.cad
From: sdh@uicc.com (sheldon haynie)
Subject: Re: IC Defect Statistics
Summary: IC defects and yields
Keywords: yield, defects, models
Organization: Unitrode Integrated Circuits Corp., Merrimack, NH, USA
Date: Tue, 26 Jan 1993 13:18:30 GMT

in previous post Gerald M. Spiegel says:
	>Anyone who deals with product quality and yield 
	>of integrated circuits probably has the same problem:
	>Where can I get realistic data about defect densities
	>and defect size distributions concerning a certain
	>manufacturing process? Well, so do I.

	>For my opinion, we should stick together and share 
	>the little information we have.
	>So here is my call: Please email ANY information 
	>you have about defect statistics, if you think it
	>might be usable. 
	>No, you are not asked to let out any internal 
	>company affairs, because the information shall 
	>be summarized and posted.

	>Any help is greatly appreciated.

Here's some info from previous processes that I have known well. These
data are 3-15 years old and *should* be therefore pessimisitic estimates. 
Don't ask which fabs, because it doesn't matter. These were all reproducible 
manufacturing numbers, in companys from Fortune 500 to start-ups. Obviously,
*Yield* must be separated from *defect density* by a coherent strategy
that eliminates testing, parametric and design issues. With SRAM or DRAM 
cells, or by arbitrarily grouping adjacent linear die you can synthesize enough
yield vs area information to develop a curve. Take *lots* of data
(> 10,000 wafers) before you decide what your D and Alpha are.


In 1988 I was priviliged to attend a Defect reduction course at RPI
with a presentation by Dr. Stapper... he put up sanitized data that
showed the IBM General Tech. Divisions Historical Defect reduction on a 
log scale. The units were arbitrary, but the slope was near constant from 
'69 to '86...

Model parameters are for a "Stapper" gamma function defect distribution
which fit my data better than exponential, Murphy/Moore or Seeds. Your milage 
will vary. Note: defects do cluster, the distributions are not simple.

Stapper's eqn: Yield = (1 + AD/alpha)^-alpha
where alpha is the parameter for wafer to wafer variations

 
Technology	Design	Feature	Wafer 	D(/cm^2)	Alpha	Tooling
________________________________________________________________________
Bipolar slm 	Linear	5 um 	100mm 	2.5		1.3	PE 341
Bicmos	dlm	Linear	3	100	1.02		.8	PE 341
CMOS	slm	digital	5	100	10		3	Canon Prox.	
CMOS	dlm	digital	2	100	5		3	PE 341	
CMOS	dlm	digital	1	100	3		2	5:1 DSW
Bicmos	dlm	linear	2	100	10		3	5:1 DSW
DMOS	slm	disc.	4	100	8		2	Canon Prox.
DMOS	dlm	disc.	5	75	7		2.5	Canon Prox
JFET	slm	disc.	2	50	20		.3	K&S contact
Bipolar	slm	disc.	10	75	50		.5	K&S contact

Notes: 	slm = single metal
	dlm = double metal
	The tooling and possible redundancy of the circuits will dramatically
	affect yields... Note that the contact printers (ca 1978) with 
	emulsion masks gave very consistent (small alpha) results.
	
Sheldon Haynie		|
Unitrode IC Corp	| 
7 Continental Blvd.	|
Merrimack, NH 03054	|
FAX:603-424-3460	|voice:603-424-2410 (EST)|	sdh@.uicc.com
*********************************************************************
From: matthias@nsr.hp.com (Matthias Kamm)
Newsgroups: comp.lsi.testing
Subject: Re: IC test quality references (was Re: Stuck-At model dead?)
Date: 21 Jan 1993 21:32:18 GMT
Organization: Hewlett Packard Santa Clara Site
NNTP-Posting-Host: hpmvd069.nsr.hp.com
X-Newsreader: TIN [version 1.1.2 PL7]

Good stuff.
Thanks,

-------------------------------------------------------------------
| Matthias Kamm              Hewlett Packard     ...  __o         |
|                            MTV, CA           ...  =-\<_>        |
|                                              ....(_)/(_)..      |
| matthias@hpmvd069.nsr.hp.com                                    |
| The opinions expressed above are mine, not HP's.                |
-------------------------------------------------------------------
From: cindy@Zoran.Hellnet.Org (Cindy Eisner)
Newsgroups: comp.lsi.testing
Subject: Re: Readership
Date: 26 Jan 93 06:44:19 GMT
Organization: Zoran Microelectronics LTD. Haifa, Israel.


-- 

    Cindy Eisner,                     Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: cindy@Zoran.HellNet.Org
    Advanced Technology Center
    Haifa 31204, Israel               Could be my employer doesn't agree.
Newsgroups: comp.lsi.testing,misc.wanted,comp.misc
From: cs000rdw@selway.umt.edu (Richard D Warner)
Subject: NEED AN INEXPENSIVE GAL (or PAL, or other PLD) programmer
Followup-To: poster
Organization: University of Montana
Date: Wed, 27 Jan 1993 13:22:37 GMT

Hi there -
	We're putting together a circuit and need to be able to decode port
addresses on a PC.  Do you have a PAL or GAL programmer sitting around not
being used?  We can't afford much, but would like hearing from you.  Send
email with the details.  Thanks in advance.

Rich
Newsgroups: comp.lsi.testing
From: obnoid@netcom.com (Michael Kirschner)
Subject: Re: IDDQ Testing?
Organization: Netcom - Online Communication Services  (408 241-9760 guest) 
X-Newsreader: TIN [version 1.1 PL6]
Date: Fri, 22 Jan 1993 16:00:47 GMT

Terry Manley (manley@optilink.COM) wrote:
: In article <1993Jan19.231338.29821@newsgate.sps.mot.com> saari@chdasic.sps.mot.com writes:
: 
: >IDDQ testing is also necessary for the latent defects and catching faults in
: >redundant logic...
: 
: I'm unfamiliar with the term IDDQ testing. Would someone simply state the
: method of this test and it history?

Iddq is the the current drawn from Vdd while the device is in a static, or
"quiescent" state, hence "Iddq". It's only useful, to my knowledge, for
CMOS devices which are designed such that there are no intended resistive
paths from Vdd to ground while in some known state, e.g. immediately after
reset, with clock, if there is any, at a DC level.

: 
: Thanks,
: 
: dave
: manley@optilink.com

Mike

-- 
----------------
Michael Kirschner
2224 Larkin St.                                 (415)292-3674 (voice)
San Francisco, CA 94109    Preferred E-Mail address: obnoid@netcom.COM
[GEnie: M.KIRSCHNER1; well: obnoid]
From: clarkw@utdallas.edu (WILLIAM D CLARK)
Newsgroups: comp.lsi.testing
Subject: Re: Readership
Date: 27 Jan 93 21:48:03 GMT
Organization: Univ. of Texas at Dallas


Bill Clark
SGS-Thomson Microelectronics
Carrollton, Texas
clarkw@sun100.isnet.inmos.com
Newsgroups: comp.lsi.testing
From: menaf00@DMI.USherb.CA (FRANCOIS MENARD)
Subject: Readership
Organization: Universite de Sherbrooke -- Dept. d'Informatique
Date: Wed, 27 Jan 1993 06:03:22 GMT

Count me in !

-=Frank=-





-- 
--- 
Francois Menard ! Menaf00@DMI.USherb.CA ! Universite de Sherbrooke, Canada !
Groupe des Utilisateurs OS/2 de l'Estrie ! CP 142, Sherbrooke, QC  J1H 5H8 !
(819) 565-3666 voice, (819) 821-2137 FMMHOST/2 OS/2 BBS 300-19200ZyX Bps   !
Xref: sparky comp.lsi.testing:475 comp.lsi:794 comp.lsi.cad:1329
From: gerald@i80s20.ira.uka.de (Gerald M. Spiegel)
Newsgroups: comp.lsi.testing,comp.lsi,comp.lsi.cad
Subject: IC Defect Statistics
Date: 22 Jan 1993 14:41:43 GMT
Organization: University of Karlsruhe, FRG
Distribution: world
NNTP-Posting-Host: i80s20.ira.uka.de

Anyone who deals with product quality and yield 
of integrated circuits probably has the same problem:
Where can I get realistic data about defect densities
and defect size distributions concerning a certain
manufacturing process? Well, so do I.

For my opinion, we should stick together and share 
the little information we have.
So here is my call: Please email ANY information 
you have about defect statistics, if you think it
might be usable. 
No, you are not asked to let out any internal 
company affairs, because the information shall 
be summarized and posted.

Any help is greatly appreciated.

Gerald M. Spiegel

--------------------------------------------------------------------
UNIVERSITY of KARLSRUHE (Germany)         
Department of Computer Science            
Institute of Computer Design 
and Fault Tolerance                       Phone (+49) (721) 608 4227
P.O. Box 69 80                            FAX   (+49) (721) 370  455  
W-7500 Karlsruhe 1                        email: gerald@ira.uka.de 
--------------------------------------------------------------------

 
Newsgroups: comp.lsi.testing
From: danr@ais.org (Daniel Romanchik)
Subject: Test Programming in Top-Down Design
Organization: UMCC
Date: Wed, 27 Jan 1993 23:38:39 GMT

You folks were so helpful the last time I tried this (I was writing a
product survey on boundary scan at the time), I thought I'd do
it again.  I hope I'm not wearing out my welcome.  :)

I am beginning to research an article for the May 1993 issue of Test &
Measurement World.  The working title is "Test Development in a
Top-Down Design Environment."  My idea is to describe what a top-down
design environment is, show where test development fits into this
process, and talk about some of the tools and how to use them.

If any of you have experience with type of development or the
test-development tools and would be willing to talk about it, please
contact me.

Thanks, Dan
=====================================================================
        Dan Romanchik              |        danr@umcc.ais.org
       Technical Editor            |         (313) 930-6564
    Test & Measurement World       |     MCI Mail: tmwromanchik
=====================================================================
  For a copy of Test & Measurement World, the magazine for test and
     inspection in electronics, send me your U.S. Mail address.
=====================================================================
From: manley@optilink.COM (Terry Manley)
Newsgroups: comp.lsi.testing
Subject: IDDQ Testing?
Date: 20 Jan 93 06:22:34 GMT
Organization: DSC/Optilink Access Products

In article <1993Jan19.231338.29821@newsgate.sps.mot.com> saari@chdasic.sps.mot.com writes:

>IDDQ testing is also necessary for the latent defects and catching faults in
>redundant logic...

I'm unfamiliar with the term IDDQ testing. Would someone simply state the
method of this test and it history?

Thanks,

dave
manley@optilink.com
Newsgroups: comp.lsi.testing
From: philp@bcrka449.bnr.ca (Phil Pownall 1342476)
Subject: Re: IDDQ Testing?
Reply-To: philp@bcrka449.bnr.ca (Phil Pownall 1342476)
Organization: Bell-Northern Research, Ottawa, Canada
Date: Mon, 25 Jan 1993 14:36:48 GMT

Iddq is a current-measurement technique for detecting defects.  Iddq, or
quiescent Idd, is the (leakage) current which remains after a transition.
In CMOS circuits, the quiescent current is very small (on the order of
micro or nano amperes), and so Iddq is a particularly effective method
for detecting defects such as gate-oxide shorts, which can raise the
Iddq into the milliampere range.  There is also widespread belief (with
some evidence to back it up) that the kinds of defects that Iddq detects
will often lead to infant mortality failures, and so Iddq could also be
considered to be a reliability test.

Iddq was first investigated and used (I Believe) by Ford Microelectronics in
the early 80's.  Other notable locations which have published results include
Sandia Labs, Phillips Research, CMU and National Semiconductor.  There are
lots of papers on Iddq in the proceedings of the International Test Conference,
for example.

In essence, Iddq testing could be considered to be essentially the same as
scan-based testing, except it uses the power & ground lines to observe the
defect mechanism rather than scanning out a voltage value using the scan
shift register; both techniques rely on having a high-coverage pattern to
sensitise the defect.  In addition, Iddq also requires that other sources
of leakage current are controlled (e.g. dynamic memories, pullup resistors
on input pads, etc) so that the Iddq value is as small as possible.  Iddq
values generally follow a normal distribution centred around a very small
value, and so the test method basically involves deriving a margined test
value similar to any other parametric test.  Scan-based patterns have
frequently been used for Iddq because they obtain high internal node
coverage, and they are quite predictable in their timing behaviour.  Many
vendors of scan & design-for-test tools have the capability to generate a
scan-based pattern for Iddq.
  
The main difficulty with the test method has been the measurement speed.
Since the values are so small, a certain amount of settling time has to
be allowed.  Some proponents have designed their own low-current measuring
instruments, others have used the tester parametric measurement unit, and
others have used the power supplies.

Regards,
Phil Pownall

philp@bnr.CA 
Newsgroups: comp.lsi.testing
From: makki@uncc.edu (Rafic Z Makki)
Subject: Re: IDDQ testing, how reliable is it?
Reply-To: makki@uncc.edu
Organization: University of NC at Charlotte
Date: Thu, 21 Jan 1993 15:53:14 GMT

Bjorn, the points that you make are indeed valid. However, it is still
early to disgard IDDQ for a number of reasons. First, a number of researchers
such as Maly and Hawkins have shown IDDQ to be effective when used as an additional screen
and a good way to augment stuck-at and functional testing. Second, one cannot look at
any one test method in isolation for all levels of the maufacturing process from
die level to chip level to card level. There are many different test activities and, if used
properly, IDDQ can be effective in helping to assure higher quality levels. Finally, 
IDDQ is still far from being a mature test method and much research remains to be done
in areas such as designing current-testable circuits, combining IDDQ with boundary scan, etc...

Bjorn, thanks for your comments. I enjoyed thinking about the questions that you posed.



-Rafic Makki
Newsgroups: comp.lsi.testing
From: menaf00@DMI.USherb.CA (FRANCOIS MENARD)
Subject: test
Organization: Universite de Sherbrooke -- Dept. d'Informatique
Date: Wed, 27 Jan 1993 06:06:19 GMT

Count me in !

-=Francois=-
---


-- 
Francois Menard ! Menaf00@DMI.USherb.CA ! Universite de Sherbrooke, Canada !
Groupe des Utilisateurs OS/2 de l'Estrie ! CP 142, Sherbrooke, QC  J1H 5H8 !
(819) 565-3666 voice, (819) 821-2137 FMMHOST/2 OS/2 BBS 300-19200ZyX Bps   !
In '92 IBM USA was 5 billions under, IBM Canada was 800k over, Eh ! :-)    !
Newsgroups: comp.lsi.testing