From: rec@aim.com (Bob Cousins)
Newsgroups: comp.arch
Subject: Re: BUSES
Date: 29 Jul 92 18:42:14 GMT
Organization: /usr/lib/news/organization

In article <33751@cbmvax.commodore.com> jesup@cbmvax.commodore.com (Randell Jesup) writes:
>keith@ksmith.uucp (Keith Smith) writes:
>>Someone please correct me if I'm wrong, but I think the inherent problem
>>with a 'bus' of any description is the delay while the electrons take a
>>torturous route across the copper foiling, and thru the connectors and
>>buffers from the CPU to whatever card.  As clock speeds of CPU chips
>>go up, it just takes too long for the information to run accross the
>>conductors.
>	Well, that and the fact that skew between different signals becomes
>more of a problem at high speeds.

There are a number of well-known solutions to these problems. Technologies
such as FutureBUS+ deal with them in a very systematic fashion. However,
the problems always break down to two catagories: bandwidth and latency.
(Ok, cost and analog considerations held constant.) Bandwidth is easy
to buy if you are willing to keep widening the backplane. Latency,
however, is now often limited by a combination of problems:
	How long until the current master gives up the bus?
		This is function of bus cycle time.
			This is a function of signal prop time.
		This is also a function of the burst length.
		And of the speed of the bus slave involved.
	How long until I can get the bus?
		Function of arbitration scheme.
			often limited by prop time
		Function of number of contending masters.

Anyway, there are techniques available to reduce backplane prop time
to *VERY* low times. My favorite is the "wagon wheel" backplane.
In this design, the backplane is no longer a flat board but is 
instead a small cylindrical object at most a couple of inches in
diameter. Boards are connected radially outwards. Connections between
boards are made though connectors which mate directly with conductors
in the middle. 

Backplanes of this form can have worst case prop delays measured in
1-2 ns, with very low capacitance. Furthermore, signal termination is 
often not required which allows lower power interface circuitry. In 
some cases, the interface circuitry is not required at all. In fact,
some *VERY* compact implementations have found that they didn't need
*ANY* special bus circuitry due to the similarity in electrical 
characterstics between the PCB and backplane. I once read of a company
which had a connector scheme based upon this (have forgotten the name)
which allowed 100 connections per inch and was able to extend more than
15 inches. They were claiming under 1 pf capacitance and under 1 ns
for worst case prop delay with standard FCT series logic on both sides.

This is an easy way to buy both latency and bandwidth. I once was
given the job of architecting a 64 CPU shared memory multiprocessor.
This was the technique which I chose. I still had to use extreme
bus technologies (split transactions, dual paths, replicated memory, 
etc.) However, on paper it worked cleanly. Shame I didn't get a chance
to build it. ;-)



-- 
________________________________________________________________________________
Robert Cousins                    rec@aim.com                  (408)748-8649x212
Consultant to Aim Technology                          Speaking for myself alone.
Newsgroups: comp.arch