From: tmc@spartan.ac.BrockU.CA (Tim Ciceran)
Subject: Re: WOC Toronto: Amiga's Future
Organization: Brock University, St. Catharines Ontario
Date: Wed, 16 Dec 1992 05:46:27 GMT

In article <1992Dec15.173535.24953@oracle.us.oracle.com> dnavas@oracle.uucp
(David Navas) writes:

>Is it public what was covered in the Sat. night seminar -- I didn't see any
>specific mention of it?  If you compiled both seminars into these posts,
>nice job!  Of course, I like my news -raw- rather than well-done :)

The information conveyed in both the private and public seminars was
virtually the same, with the exception of a few additional details given
by Mr. Eggebrecht following the developer/dealer/exhibitor meeting.
Nothing revealed was therefore subject to the NDA.

>Anyway, that's a 17ns pixel -- which is what we need for 1024x768x60, right?
>Any mention of such a mode?

Not explicitly, although one could perhaps infer this capability. The
resolution of the low-end chipset is generally tagged at 800x600 NI.

>Yeah, for free.  This, along with the 100% backwards compatible makes it
>yet-again a 16bit blitter.  Sigh....

My impression was that downward compatibility was an objective, but he
intimated that this would not necessarily be thorough.

>As Ty pointed out to me in email, this sounds rather the funny thing to say.
>I mean, they asked for a 16bit TC mode and it came back from the designers
>with an extra 8bits layed out or something?  ;)

This is subject to interpretation as well. 24-bit true colour was evidently
mentioned in the context of 'television' resolutions, so it would seem
safe to assume that this would be limited.

>All in all, pretty reasonable for, say, six months in the future.
>My guess is that it's going to be longer than that, in which case a DRAM
>backwards compatible chipset seems kinda silly.

By all accounts, the high-end chipset is apparently further along in the
development process, with a second run to be issued in March. Estimated
delivery times were mentioned to be in the area of 1 year.

>>High End:
>>	- 4 Chips ( 750k transistors each )

>Each or total?  I seem to remember these being -totals- in the WOC Pasadena
>address?

Total.

>Hmm, 1280x1280x60 pretty easily there....  That seems very reasonable for
>future chipsets.

Yes, in fact the high-end version will supposedly offer 1280x1024 as the
default configuration.

>>	- 1280 x 1024 24 bit color 72 Hz Refresh Rate
>
>Okay, BIG quesiton here.  This is REALLY THE QUESTION I'm posting this
>whole message because of!

>Is this really 1280x1024x24?  Or is it simply a note that says -- hey,
>we have a 24bit palette in our hi-res mode?  The former is impressive, the
>latter is marketing ;)

Tough call.

>What I really want to know is -- what are the max. screen modes -- what
>resolutions, what "bitplane" depth?

Don't we all? Stay tuned for the WOC NYC :).

>>	- Video Upgrade module ( You can add more chips for parallel processing
>>	 chip set i.e. multiple blitters, and Higher Resolution Display Modes )
>
>Like I really am going to believe this?
>Really, I'd prefer a wider CHIPbus....  What is more than one blitter going
>to do for me?  I've only -got- one bloody bus (or do I?).

An improved bus design was also alluded to, but details were vague.

>>	- Hardware Graphics Decompression Modes
>
>GDM == HAM/DYUV/MPEG?  This is a great way to market HAM, is that what they're
>doing or are we getting real-time JPEG or something like that....

Software and hardware solutions, the former of which is supposedly scheduled
to be demoed at the CES. That's about it.

>If something as basic as a CPU hasn't been decided on, then I can only
>conclude that this is a pipe-dream.  An interesting one, to be sure, but
>one that hasn't been sold to the people that say "OK, go do it".

I believe that this was only mentioned in the context of RISC.

>Let's try and keep this one in a position to make a difference, shall we?

Ditto.