From: michael@Canada.lsil.com (Michael Smith)
Subject: Information on Headland's SHASTA Chipset
Keywords: chipset, headland, lsi-logic, shasta
Reply-To: michael@Canada.lsil.com
Organization: LSI Logic Corporation of Canada, Inc.
Date: Tue, 22 Dec 1992 22:17:30 GMT

Since I have received an absolutely *ENORMOUS* number of queries concerning
the Headland HTK340 (i.e. "Shasta") chipset, to save my own sanity (and
mail spooler) I'll just post the response to some of the questions I have
received.

Summary of Information
----------------------

Composed of two required chips (HT321 ISA Controller and HT342 MCU) and 
one optional chip (HT44 Cache Controller).


Features:

	GENERAL

		Support for 486 SX/DX/DX2
		2 184 pin PQFP devices
		Local bus interface
		16, 20, 25, and 33 MHz local bus speeds
		Full static operation
		Weitek 4167 supported
		System and Video BIOS on single ROM
		Uses 0.7 Micron HCMOS process

	ISA Controller

		AT Compatible
		Sync 8MHz ISA bus
		Posted backplane memory writes
		10 or 16 bit I/O mapping
		Integrated 8237s, 8259s and 8254 functionality
		Fast gate A20/Fast reset

	Write Buffer

		4 deep on-chip buffer
		Byte gathering
		Out of order operation
		Full or partial write buffer hits

	DRAM COntroller

		Line burst capability from DRAM to 80486
		256k/1M/4M/16M DRAMs
		Mixed memory types
		EMS 4.0
		Hidden refresh operation
		256MB Maximum system memory
		Staggered refresh
		Shadowing in 16KB increments between 640K and 1MB
		Remapping
		Fast paging
		2 or 4 way interleaving

	Cache Configuration

		32K, 64K, 128K, 256K, 512K or 1MB cache sizes
		25ns SRAMs required at 33MHz
		Asynchronous and Synchronous SRAMs supported
		Programmable write-protected and non-cacheable regions are
		  supported through the chip set

	Cache Architecture

		Look-Aside cache
		Write Through
		Direct Mapped
		Intergrated Tag Comparator
		Zero wait state cache hits
		Simultaneous 486 and L2 update on read miss
		486 line burst cycle support


Benefits of this chipset:

	In the basic configuration, without the K2 cache (i.e. HT44) 
	controller, due to the write-buffering and write gathering, this
	chipset performs in a manner almost identical to all other chipsets
	with a cache!  With a 486DX2, the basic configuration performs even
	better under Windows and Unix applications.  Although the 486 does
	have a write buffer, is does not gather writes together.  Unix and
	Windows applications perform a lot more writes than typical DOS
	apps., and this results in the 486's write buffer filling up much
	faster than other chipsets can offload them.  By doubling the write
	buffer size to 8 DWORDs (i.e. 8 by 32 bits) and by gathering together
	writes, this additional write traffic will not kill the system.

	Recall that the 486 has a write-through cache, not a write-back cache.
	For read traffic, the internal 4-way set associative 486 cache will
	take care of 90%+ of all read traffic.  All write traffic, though, will
	get propogated through to the local bus.  For a DX2 chip, optimizing
	this 10-20% of all memory traffic that are writes (off-the-cuff 
	number, so no flames please) will significantly increase performance.

	Out of order operation on the write buffer implies that a read will
	propogate around the write buffer, even if the write buffer is full.
	Thus, the CPU does not have to stall while it waits for the write
	buffers to offload if its performing a read.

	Posted writes means that writes to the backplane (i.e. ISA bus) are
	terminated on the local bus before they are terminated on the ISA
	bus.  Thus, the CPU does not have to wait for a slow ISA device to
	respond before it can continue.  Only memory writes are posted,
	posting I/O writes is a good way to crash your system.


Where is it built/designed:

	This chipset is entirely designed in the LSI-Logic office in Toronto,
	Canada.  Fabrication is done through LSI-Logic Corp. in Miliptas, CA.


Companies using this chipset:

	Sidus
	Dell
	Siemanns
	IBM
	any many more....

	Note that not all of the boards manufacturers use this chipset, if
	you want a SHASTA chipset board, make sure that the board does use
	this chipset.


Pricing:

	I dunno, I'm just an engineer, not a sales-droid.

**********************************************************************

I hope this answers the majority of peoples questions.  All of the above
technical information is available through the chipset specifications.  Any
opinions, comments, or mistakes are my own, are not those of LSI Logic
or my boss.


---
     Michael Smith - Chipset Design Engineer

Phone: (416) 620-7400         michael@canada.lsil.com
Fax:   (416) 694-5005

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