HDTenEightyP/NetNews huggingface dataset:
From: arnief@sail.LABS.TEK.COM (Arnie Frisch)
Newsgroups: comp.lsi.testing
Subject: Re: Boundary Scan JTAG 1149.1 Experience?
Keywords: help
Date: 9 Nov 92 17:29:35 GMT
Organization: Tektronix, Inc., Beaverton,  OR.

In article <BxD9CM.C1@scd.hp.com> vinoski@ch.apollo.hp.com (Stephen Vinoski) writes:
>
>One issue with 1149.1 is that every chip has its own scan controller.
>This is fine for chip test, but for board test it would better if
>there were only one controller for all the chips on the board.  See
>
>	Dervisoglu, B.I., "Scan Path Architecture For Pseudorandom
>	Testing", IEEE Design & Test of Computers, 6(4): pp. 32-48,
>	1989.
>
>	Dervisoglu, B.I., "Features of a Scan and Clock Resource Chip
>	For Providing Access to Board-Level Test Functions", Journal
>	of Electronic Testing: Theory and Applications, 2: pp.
>	107-115, 1991.

There is not one scan controller per chip.  There is one TAP controller
for each chip that has boundary scan implemented.  All chips do not
need to implement boundary scan, and seldom - if ever - do you find a
board where they all do.  Depending upon the implementation, there may
be a scan controller on the board, but usually not.  Scan control is
implemented in a computer that has a scan control chip (usually -
though this can be done in SW), and SW used for testing and diagnosis.

NOW...  I WANT TO TAKE EXTREME ISSUE WITH YOUR INFERENCE THAT THE
APOLLO 10K ARCHITECTURE FOR SCAN IS SOMEHOW BETTER THAN BOUNDARY SCAN.

The P1149.1 standard is the engine that is driving the future of
built-in test.  Departures from this standard slow the process of
progress.  The issue is not whether something is better (and I doubt
that your example qualifies) but whether the standard is "good
enough".  If it is good enough, it should be used, and if it is used
people will find that it has much more capability than is visible on
the surface.  For example, did you know that ATT uses boundary scan as
the basis for communication of internal BIST results from chips to
boundary scan controllers in production test applications?  Did you
know that this use, and extensions of this methodology, are in
development at many major sites in the US and elsewhere?

Did you know that a substantial infrastructure - involving HW and SW is
being created around P1149.1 and its extensions, an infrastructure that
will not support other architectures and scan methodologies?  Do you
think it is smart and cost effective and productive to depart from the
standard under these conditions?

Arnold Frisch
Tektronix Laboratories
Newsgroups: comp.lsi.testing
From: vinoski@ch.apollo.hp.com (Stephen Vinoski)
Subject: Re: Boundary Scan JTAG 1149.1 Experience?
Organization: Hewlett-Packard Corporation, Chelmsford, MA
Date: Tue, 10 Nov 1992 22:45:57 GMT

In article <12867@sail.LABS.TEK.COM> arnief@sail.LABS.TEK.COM (Arnie Frisch) writes:
>>Do you realize that the DN10000 scan architecture was developed before
>>1149.1?  How can you accuse us of "departing from the standard" when
>>the standard wasn't even around when we did this work?
>
>Do you realize that JTAG (the Joint Test Action Group) had been working
>on this for about 8 years, and that they were well ahead of the DN10000
>architecture when they started writing the basis for the P1149.1
>standard?

The DN10000 architecture work began in 1985, and we had a working
system in 1987.  This included power-up self tests that utilized
pseudorandom scan test techniques, an offline scan test program that
tested the system with automatically-generated scan patterns, and a
remote debugger that allowed access to the system under test from any
other workstation on the net.  We never would have finished any of
this if we had waited for 1149.1; the market window for the DN10k
would have closed by then.

What do you mean when you say that the 1149.1 folks were "well ahead"
of us?  Especially given the fact that we completed our work before
they published the standard?  Just because they were working on 1149.1
for a portion of the time that we were working on the DN10k doesn't
mean that their work was anywhere near being ready to be put to use in
a real system.  Be practical, Arnie.

>As I understand it, consultants were hired to do the major part of the
>IC design for the 10K - including the scan design.  They subsequently
>came out with a product for testing scan designs and tried to sell it -
>unsuccessfully - under the banner "Gillytronics".  Seems like something
>was lacking in their methodology.

Sorry, Arnie.  You're talking to a member of the DN10k development
team, so please get your facts straight.  We did our own ICs using
gate arrays from Integrated CMOS Systems (ICS).  The scan architecture
was largely the brainchild of Bulent Dervisoglu.  His many papers and
articles contain a lot of good information related to scan
architectures and scan testing.  (Judging from the content of your
postings, you should read them sometime.)  Gillytronics was somehow
related to ICS, but that is their only (weak) link to the DN10k work.
Remember, Arnie, they set out to do chip testing with a specialized
test system, and we were doing system testing using a built-in service
processor.  Very different beasties altogether.

Why are you so bent out of shape about this, Arnie?  Seems like you
need to broaden your horizons a bit.

-steve
Newsgroups: comp.lsi.testing
From: ncl@philabs.philips.com (Nai-Chi Lee)
Subject: Re: Boundary Scan JTAG 1149.1 Experience?
Organization: Philips Laboratories, Briarcliff Manor, NY.
Date: Thu, 12 Nov 1992 13:58:41 GMT

In article <12871@sail.LABS.TEK.COM> arnief@sail.LABS.TEK.COM (Arnie Frisch) writes:
>In article <1992Nov10.215505.7919@philabs.philips.com> ncl@philabs.philips.com (Nai-Chi Lee) writes:
>>	[ JTAG Version 0 ]
>>	  The initial JTAG proposal was created by Frans Beenker (Philips
>>	Research Labs, The Netherlands), Chantal Vivier (Bull Systems,
>>	France) and Colin Maunder (British Telecom Research Labs, UK) in
>>	June 1986
>
>Yes, the initial document was completed in 1986, but work started on
>this several years before.  I said they had been working on this for
      ^^^^^^^^^^^^^^^^^^^^
>about 8 years, and I think this checks out.

(*sigh* doesn't this guy ever give up?)

To quote from the same book, same page again:

	JTAC was set up following a paper by Frans Beenker of Philips
	Research Labs in 1985 [IEEE International Test Conference].

Now, don't argue with me that Frans must have been working on this for
years before 1985.  Of course he has --- for PHILIPS.  JTAG doesn't even
exist back then.

--
Nai-Chi Lee
Philips Research Labs, Briarcliff
Newsgroups: comp.lsi.testing
From: ncl@philabs.philips.com (Nai-Chi Lee)
Subject: Re: Boundary Scan JTAG 1149.1 Experience?
Organization: Philips Laboratories, Briarcliff Manor, NY.
Date: Tue, 10 Nov 1992 21:55:05 GMT

In article <12867@sail.LABS.TEK.COM> arnief@sail.LABS.TEK.COM (Arnie Frisch)
writes:
>Do you realize that JTAG (the Joint Test Action Group) had been working
>on this for about 8 years, and that they were well ahead of the DN10000
                   ^^^^^^^
>architecture when they started writing the basis for the P1149.1
>standard?

Quoted from "The Test Access Port And Boundary Scan Architecture", page 23:

	[ JTAG Version 0 ]
	  The initial JTAG proposal was created by Frans Beenker (Philips
	Research Labs, The Netherlands), Chantal Vivier (Bull Systems,
	France) and Colin Maunder (British Telecom Research Labs, UK) in
	June 1986

(I have no intention to get into this dog-fight. This is just to set the
 record straight)
--
Nai-Chi Lee
Philips Research Labs, Briarcliff
From: alvin@cse.ucsc.edu (Alvin Jee)
Newsgroups: comp.lsi.testing
Subject: Re: Boundary Scan JTAG 1149.1 Experience?
Date: 10 Nov 1992 22:24:39 GMT
Organization: University of California, Santa Cruz (CE/CIS Boards)
NNTP-Posting-Host: arapaho.ucsc.edu

In article <12867@sail.LABS.TEK.COM> arnief@sail.LABS.TEK.COM (Arnie Frisch) writes:
>As I understand it, consultants were hired to do the major part of the
>IC design for the 10K - including the scan design.  They subsequently
>came out with a product for testing scan designs and tried to sell it -
>unsuccessfully - under the banner "Gillytronics".  Seems like something
>was lacking in their methodology.
>
>Arnold Frisch
>Tektronix Laboratories

  Actually, as I understand it :), the 10K was not designed by
  consultants; rather, the design was given to a company to implement
  using their scan and gate array technology. The company was called
  Integrated CMOS Systems, but is now called Vertex. Gillytron was the
  ATE vendor that they bought some equipment from. Vertex had their own
  scan stuff working before the 1149 standard was approved and have
  since modifed their stuff to become JTAG compliant (I think). Anyways,
  I believe that Vertex is still around as a subsidiary of Toshiba.

Alvin Jee
alvin@cse.ucsc.edu
From: ekearns@bbn.com (Edward Joseph Kearns)
Newsgroups: comp.lsi.testing
Subject: Re: JTAG 1149.1 && LSSD
Date: 10 Nov 1992 01:30:32 GMT
Distribution: usa
NNTP-Posting-Host: bbn.com
Keywords: help

takla@r1w4.pub.utk.edu (Mourad B. Takla) writes:

>Hi All,
>	
>	I am looking for the JTAG 1149.1 standard. Any information about
>how to get those standards is appreciated. 

>Thanks
>Takla

Write to:

IEEE Service Center
P.O. Box 1331
445 Hoes Lane
Piscataway, N.J. 08855

or call:

1-800-678-4333

Ed Kearns
BBNASD
Bellevue,Washington
From: ekearns@bbn.com (Edward Joseph Kearns)
Newsgroups: comp.lsi.testing
Subject: Re: Tons of 1149.1 experience...
Date: 10 Nov 1992 00:59:14 GMT
NNTP-Posting-Host: bbn.com
Keywords: help

vinoski@ch.apollo.hp.com (Stephen Vinoski) writes:

>This is fine for chip test, but for board test it would better if
>there were only one controller for all the chips on the board.  See

A good time for me to clarify our present test philosophy...

Actually, that is what we hope to accomplish.  By placing a Micro-
processor and one Test Bus Controller with multiple scan path linkers
on the board, we can apply stimuli vectors, saved in an EPROM, to the 
"boundary" of one functional block of the board, then observe the 
response by collecting the resultant vector on other scan paths in 
other functional blocks.  

This "embedded test" will be used for connectivity testing between 
ASIC's where the number of functional ASIC stimuli vectors would be 
too high to apply in a timely fashion after power-up and before the 
system ready state.

In case folks where wondering, yes there are plenty of non-scan parts
on this board that I also have to write tests for.  That's the part 
I've done before.  And yes we will have approximately 6K scanable ASIC 
pins, plus some scanable registers and fifo's on the board as others 
have questioned. Sounds exciting I know!

My final goal with the embedded test at power-up is only to achive a 
level of funtionality confidence, and not complete ASIC functionality.  
Thus the 1149.1 architecture features that we install will contain the 
"hooks" to perform more thorough testing on the manufacturing floor using
a non-resident test processor in a PC for instance, as a diagnostic tool
in module test or burn-in.  Prior to this step, the ASIC's will have been
tested at the foundary before pc board assembly and at the ATE station 
after pc board assembly.

>In a previous life I wrote a lot of scan software.  I found that the
>use of object-oriented software development techniques greatly reduces
>the chances for errors while allowing relatively powerful tools to be
>developed quickly and reused for different applications.

Others have mentioned the Object Oriented approach as a wise choice.
Thank you for the advice and the references.

Actually!, Thank you all for the many responses.  Between all the phone 
calls with new vendor product leads, and all the new reading material,
a a couple of well deserved vacation days, I've not had enough time to
respond to everyone.  

Let's keep this discussion going.  I still have a ton of questions...

Ed Kearns
BBNASD
Bellevue,Washington


Newsgroups: comp.lsi.testing
From: vrkaramc@mtu.edu (Karamchedu)
Subject: Current-mode Subthreshold Analog VLSI
Organization: Michigan Technological University
Date: Sat, 7 Nov 1992 23:10:42 GMT


Are there any forthcoming conferences/conventions allowing for presentations
or discussions of Current-mode Subthreshold Circuits (perhaps with some 
applications or demonstrations of neural circuits) ? 


Any feelers and hints on probable dates, locations would be greatly 
appreciated.

PLEASE E-MAIL ME DIRECT.

Thank you

Karamchedu Raj

Dept of EE

 
-- 

Instruments and moods are two facets of Being.
From: pjd@ecs.soton.ac.uk (PJ Dickinson)
Newsgroups: comp.lsi.testing
Subject: BSDL descriptions
Summary: Looking for BSDL descriptions
Keywords: BSDL
Date: 9 Nov 92 11:37:53 GMT

Hi.

	I am currently working with the BSDL parser from HP. 
Does anyone have any BSDL descriptions of chips custom/production
which they could let me have?

	Does anyone know of any anon-ftp sites where BSDL
descriptions have been collected?

	I still have version 0.0 of the parser from HP. Has this
been superseded yet?

Thanks.

Paul.

--
Paul John Dickinson                                  pjd@uk.ac.soton.ecs
Department of Electronics & Computer Science, University of Southampton,
England,  SO9 5NH                                     Tel: (0703) 593127
Newsgroups: comp.lsi.testing
From: storm@binkley.cs.mcgill.ca (Marc WANDSCHNEIDER)
Newsgroups: comp.compilers
Subject: Tools for Measuring Pointer Usage
Keywords: code, question
Date: 5 Nov 92 12:44:16 GMT
Article-I.D.: comp.92-11-024
Reply-To: storm@binkley.cs.mcgill.ca (Marc WANDSCHNEIDER)
Organization: Compilers Central


	We are about to undertake on a project to study pointer usage in
computer programs, and were wondering if anybody has written a tool that
will tell you what percentage of loads are, in fact, just getting addresses
for pointer dereferences...

	If such a tool has been written, we would like to save ourselves the
time of writing it.  If not, we would appreciate any suggestions on how we'd
go about doing this.

	Toodlepip!
	Marc 'em.
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From: 0005507197@mcimail.com (Lee Leitner)
Newsgroups: comp.compilers
Subject: Two Level Grammars
Keywords: parse, question
Date: 9 Nov 92 15:46:00 GMT
Article-I.D.: comp.92-11-037
Reply-To: Lee Leitner <0005507197@mcimail.com>
Organization: Compilers Central

I am looking for some reference sources for "two level Grammars" and "Van
Wijngaarden form" grammars. I am aware of the "Revised report on the
algorithmic language Algol 68" (Acta Informatica 5, 1-236 Van Wijngaarden, et.
al.) Can anyone point me to other references which describe these grammars? 
Thank you.

--------------------------------------------------------
Lee Leitner                            leitnerl@mcimail.com
Infocus, Inc.                           or ljl@world.std.com
37 S. Main St.
Yardley, PA 19067
(215) 321-2200                   fax: (215) 321-2205
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From: cse264ce@cs.ucsd.edu (What Is)
Newsgroups: comp.compilers
Subject: Code optimization questions
Keywords: optimize, question, comment
Date: 4 Nov 92 06:14:28 GMT
Article-I.D.: comp.92-11-015
Reply-To: cse264ce@cs.ucsd.edu (What Is)
Organization: U.C. San Diego -- 1991 'Wannabe A Real College' finalist

[1] Is there any info on optimizers that take advantage of profiler
    information?  That is, the compiler creates some code that generates
    profiler information, then the code is run, then the compiler is
    run again, and it used the generated profiler information to
    generate better code.

[2] Is there any info on optimizers that take advantage of runtime
    assertions?  This can help with anti dependencies, but it may have
    other advantages; for instance, if an integer is guaranteed to be
    within a certain range, then some operations on it may be cheaper,
    etc. etc.

[3] If statement A has a def-use chain to statement B, does it follow
    that statement B has a use-def chain to statement A?  Is this an
    "if and only if" relation?  I've checked the Dragon book, but it
    seems to have no opinion on this.

Thanks for any help,

Steve Boswell
whatis@ucsd.edu
[Multiflow had a profiler-based optimizer and I'm sure that others do, too.
-John]
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From: zou@flora.ccs.northeastern.edu (Chendong Zou)
Newsgroups: comp.compilers
Subject: LALR grammar hints
Keywords: LALR, question
Date: 5 Nov 92 15:45:56 GMT
Article-I.D.: comp.92-11-026
Reply-To: zou@flora.ccs.northeastern.edu (Chendong Zou)
Organization: College of CS, Northeastern U

Hi:

I am now try to design a grammar to preprocess some technical papers using a
LALR parser.

I wonder if there is a general rule to design a grammar to guarantee it to be
a LALR(1). For sometimes, if you do some tricky changes, a non-LALR(1) grammar
will become a LALR(1).

Any suggestions? or can you recommend some books to read?

Please email me directly.
Thank you!

-- Zou
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From: dk%farm.cs.kiev.ua@ussr.eu.net
Newsgroups: comp.compilers
Subject: Need: ANSI C to p-code compiler
Keywords: C, question
Date: 4 Nov 92 12:21:20 GMT
Article-I.D.: comp.92-11-022
Reply-To: dk%farm.cs.kiev.ua@ussr.eu.net
Organization: Compilers Central

Are there any free ANSI C compiler implementation (source) which generates
some explicit intermediate code for simple stack machine?  (or can be
easily tailored to do that).

No code generation besides that is required, nor _any_ optimizations
(besides may be simple constant pasting in expression trees).

the compiler is about to be used for embedding into applications (so size
is much more important than speed).

thanks in advance.
please reply by e-mail.
--- 
: sender ." dk%farm.cs.kiev.ua@ussr.eu.net" ; ' sender CONSTANT [cs:dk]
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From: henry@zoo.toronto.edu (Henry Spencer)
Newsgroups: comp.compilers
Subject: Re: Constant divisions, remainders
Keywords: arithmetic, comment
Date: 8 Nov 92 04:39:53 GMT
Article-I.D.: comp.92-11-033
Reply-To: henry@zoo.toronto.edu (Henry Spencer)
Organization: U of Toronto Zoology

torbenm@diku.dk (Torben AEgidius Mogensen) writes:
>I think the round-to-zero rule for div and signed mod are relics from ones
>complement computers, and should be laid to rest.

Actually, I seem to recall that it is specifically a relic of FORTRAN,
which made a fairly arbitrary decision for the sake of well-defined
behavior, and has been too influential for machine designers to ignore
ever since.
-- 
Henry Spencer @ U of Toronto Zoology, henry@zoo.toronto.edu  utzoo!henry
[Probably was based on the instruction set of the IBM 704. -John]
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From: byron@netapp.com (Byron Rakitzis)
Newsgroups: comp.compilers
Subject: Re: Is this a new idea?
Keywords: parse, performance
Date: 4 Nov 92 08:57:30 GMT
Article-I.D.: comp.92-11-017
Reply-To: Byron Rakitzis <byron@netapp.com>
Organization: Netcom - Online Communication Services  (408 241-9760 guest)

>[Scanning and parsing can be as much as half of the total time that a
>compiler takes (so says Ken Thompson of his Plan 9 C compiler) and that is
>quite amenable to incremental precalculation. -John]

Well, that's Ken's compiler, which doesn't do hairy optimizations, leaves
a lot of work for the loader, and has a fast in-core implementation of
tree passes to boot. ("Turbo C for Unix")

I think the %-age for gcc (and I am assuming that most commercial
multi-pass, aggressively optimizing compilers show similar performance) is
considerably lower, around 20%. I am not sure of the figure, it is from
memory from around the time that gcc2 was being released. This would have
been with the optimizer turned on, of course.

Sorry I can't be more specific right now.
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From: scheek@RUGRCX.RUG.NL (Frans van hoesel)
Newsgroups: comp.compilers
Subject: error recovery with yacc
Keywords: yacc, errors
Date: 10 Nov 92 16:14:41 GMT
Article-I.D.: comp.92-11-038
Reply-To: scheek@RUGRCX.RUG.NL (Frans van hoesel)
Organization: Compilers Central

Hi
  
   I have a problem understanding/using the error recovery mechanisme
   with yacc. Part of my syntax is:

  	%start compilation_chunk
	%%

	procedure:
		: PROC proc_header proc_body ENDPROC
		;
	proc_body
		: statement_list
		;
	statement_list
		: /* empty */
		| statement
		| statement_list separator
		| statement_list separator statement
		;
	seperator
		: ';'
		| NEWLINE
		;
	one_liner
		: /* empty */
		| statement
		| one_liner ';'
		| one_liner ';' statement
		;
	compilation_chunk
		: one_liner NEWLINE
			{ YYACCEPT ; }
		| procedure
			{ YYACCEPT ; }
		;
   	%%
	
   If some statement is in error then I just want to skip over the 
   next separator (which is a ';' or NEWLINE) and continue the
   parsing of the proc_body with the rest of the statements.
   I added the following rule to the statement_list definition:
		| error separator statement_list
   ( no yyerrok here!) 
   This seems ok, but causes the error to be reduce only just before
   the ENDPROC.
   Somehow it just doesn't feel right to me. Is there a better way?
   
   It sounds to me I'm reinventing the wheel, so maybe there is a
   kind person who wants to explain to me how a wheel should look like?

-- frans van hoesel

scheek@rugrcx.rug.nl or
hoesel@igc.ethz.ch
(both are me)
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From: ttk@ucscb.UCSC.EDU (the troglodyte killer)
Newsgroups: comp.compilers
Subject: Re: Is this a new idea?
Keywords: performance
Date: 4 Nov 92 17:48:51 GMT
Article-I.D.: comp.92-11-019
Reply-To: ttk@ucscb.UCSC.EDU (the troglodyte killer)
Organization: University of California; Santa Cruz

M.J.Landzaat@fel.tno.nl (Maarten Landzaat) writes:
: [a compiler] that during my editing, reads the program text I typed in so
: far, and tries to compile and link it as much as it can in the background,
: with low priority so nobody gets bad response.
 
     I seem to remember Rational using a compiler that did 
something similar..  It would color-tag the lines of code as they 
appeared on your screen, so that if you finish a block and it's 
still tagged red, you know you made an error somewhere.
 
ttk@ucscb.UCSC.EDU
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