From: bouldin@cs.utk.edu (Don Bouldin)
Newsgroups: comp.lsi,comp.lsi.cad
Subject: Tuition-Free Short Courses for Faculty
Date: 27 Jan 1993 11:38:43 -0500
Organization: CS Department, University of Tennessee, Knoxville
Distribution: world
NNTP-Posting-Host: duncan.cs.utk.edu

      DESIGNING MICROELECTRONIC SYSTEMS
     USING FIELD-PROGRAMMABLE GATE ARRAYS

  5-Day, Tuition-Free Short Courses for Faculty Enhancement
      Sponsored by the National Science Foundation

   June 21-25, 1993          and      August 16-20, 1993
   Sacramento, CA                     Knoxville, TN
   California State University        University of Tennessee


Course Description:

Two five-day short courses are  being  offered  to  introduce  to
faculty new techniques for designing microelectronic systems that
can be rapidly prototyped using  field-programmable  gate  arrays
(FPGAs).   Thus,  an  FPGA-based system can be taken from initial
specification to a working implementation involving all the steps
in the design, simulation and testing cycle.

Laboratory exercises will permit each participant to  complete  a
project  that can be taken home.  Also, each participant will re-
ceive a "starter kit" containing class  notes,  reprints,  sample
completed  projects  and instructions on how to obtain discounted
or donated vendor hardware and software.

These courses are sponsored by the  National  Science  Foundation
(NSF)  for U.S. faculty only.  No tuition will be charged and all
meals and lodging expenses will be borne by  the  NSF.   Partici-
pants will be responsible for their own transportation.  Applica-
tions must be received by March 15, 1993.

Course Participation:

These courses are intended for  those faculty whose  primary  du-
ties lie in undergraduate teaching.  Most participants should or-
dinarily have a minimum of three years of undergraduate  teaching
experience,  preferably  in  electrical engineering, computer en-
gineering or computer science. However, it is expected that there
will  be  a small number of participants from community colleges,
high schools, or allied disciplines. Participants  having  taught
relevant  courses  in  the  recent past and planning to introduce
FPGA topics to either existing  or  new  courses  will  be  given
priority for the limited number of seats in the course.

These courses differ from those offered by FPGA and CAD tool ven-
dors  for  industrial  customers  since these faculty enhancement
courses emphasize the educational possibilities of using FPGAs to
design microelectronic systems.

Prospective participants must submit an  application  to  attend.
Deadline for receipt of applications is March 15, 1993.  Partici-
pants will be notified of acceptance by April 15, 1993, and  pro-
vided  with  details on how to obtain evaluation copies of vendor
software. Thus, prior to the course, each participant  will  have
the opportunity to become familiar with the software installation
and some of the introductory laboratory exercises.

A user group of the participants will be formed  following  these
courses.   Communication will be conducted on a regular basis us-
ing electronic mail. During 1994, a special session will  be  or-
ganized  at  a  professional  conference  for the participants to
present  results  of  their  experiences  and  to  share  lessons
learned.



Course Objectives:

Upon completion of this course, the participant will be able  to:
(1)  understand  the  most  educationally  significant options in
designing  microelectronic  systems  using  FPGAs,  (2)   acquire
public-domain and commercial CAD software and educational materi-
als, (3) understand the design  process  including  architectural
partitioning,   logic  design  and  synthesis  using  a  hardware
description  language  and   schematics,   simulation,   physical
placement/routing,  functional  testing using a rapid-prototyping
breadboard, and (4) subsequently develop or refine curricula  and
materials for other FPGA-related courses.

Different Laboratory Environments:

The lecture sessions at both sites will be almost identical since
the  same  instructors  will  present the material in both cases.
Both sites will use SPARCs running UNIX, X-Windows, and Viewlogic
VHDL.   In  Knoxville,  the  SPARCs  will  be  used for Viewlogic
schematic capture, followed by the options of Xilinx FPGA,  Actel
FPGA,  or  MOSIS  standard-cell  implementations.  In Sacramento,
486/386-based DOS systems will be used  for  Viewlogic  schematic
capture  and  XABLE logic equation entry, followed by only Xilinx
implementation and experimentation.

Instructors:

Dr.  Don Bouldin is an IBM Professor of Electrical  and  Computer
Engineering at the University of Tennessee, Knoxville.  He served
as an instructor for three faculty enhancement workshops on  VLSI
design  held  at  the  Massachussets  Microelectronics  Center in
1990-92. He is special Section Editor of  the  ``VLSI  Designer's
Interface'' column for IEEE Circuits & Devices Magazine.

Dr. Jerry Dillion is a Professor Emeritus of Computer Science  at
California State University, Sacramento (CSUS).  He retired after
teaching 14 years at Cal Poly, San Luis Obispo in Electronic  En-
gineering, and 17 years at CSUS.  He served for 16 months as Pro-
gram Director of Systems Prototyping and Fabrication for the  NSF
and organized the 1990 NSF FPGA Workshop.

Other Course Offerings:

For computer science faculty whose primary interest is  in  logic
synthesis  or  CAD tools, the NSF is sponsoring two other courses
that will be held in June 1993 in Starkville,  MS.  For  details,
contact  Prof.  Bob  Reese  by telephone at (601)-325-3670 or via
email at reese@erc.msstate.edu.



Course Outline:

Monday, Day 1

Microelectronic Systems
Technology Choices
Fabrication of ICs
FPGA Applications           
Design Flow
Schematics Lab

Tuesday, Day 2

System Partitioning
Logic-based Design
Clocking
Simulation
Simulation Lab

Wednesday, Day 3

Hardware Description Languages             
Specifying Behavioral Control             
Specifying  Structural Components
Synthesis Lab/Demo

Thursday, Day 4

Physical Design
Identifying Critical Paths
Design for Testability
Xilinx Rep. Presentation
Placement and Routing Lab

Friday, Day 5

Retargeting
Actel Rep. Presentation
Acquiring CAD Software
Future of FPGAs
Rapid Prototyping Lab



==================================================

           EMAIL APPLICATION FORM
  Submit to:  bouldin@sun1.engr.utk.edu
              by March 15, 1993

"DESIGNING MICROELECTRONIC SYSTEMS USING FPGAS"

  5-Day Short Courses for Faculty Enhancement
  Sponsored by the National Science Foundation

Site Preference:    CA ____  TN ____   Either ____

Name: ____________________________________________

University: ______________________________________

Institution Type: 4-yr ____  2-yr ____  Other ____

Department: ______________________________________

City, State & Zip:  ______________________________

TEL: _____________________________________________

FAX: _____________________________________________

EMAIL: ___________________________________________

Highest Degree: ______  Major: ______  Year: _____

Minority Status: _________________________________

Years Teaching Experience: _______________________

Planning FPGA Course(s):     Yes ______  No ______

Univ. Will Pay Transportation Costs: Yes ______  No ______

Univ. Will Pay Participant's Salary: Yes ______  No ______

Univ. Will Support FPGA Course: Yes ______  No ______

Your Dept. Head Must Approve This EMAIL Application 
     Prior to Submission.

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Newsgroups: comp.lsi