HDTenEightyP/NetNews huggingface dataset:
From: bic@cj2.ICS.UCI.EDU
Newsgroups: fj.mail-lists.parallel
Subject: Workshops at ISCA'92 -- Australia
Date: 7 Apr 92 11:43:08 GMT
Distribution: fj

A series of Workshops will be held at the Architecture Symposium
(ISCA'92) this May. If you would like to attend, please contact me to
receive travel and other information.

Lubomir Bic, Workshops Chair
University of California, Irvine
bic@ics.uci.edu
(714) 856-5248


                          ISCA'92

            INFORMATION ON ARCHITECTURE WORKSHOPS

DATES

There will be three 2-day workshops and 1 one day workshop. The
dates are May 24-25, 1992.

LOCATION

All Workshops will be held on Hamilton Island (a part of the
Whitsunday Island group), which is a very popular vacation resort on
the Great Barrier Reef.


LIST OF WORKSHOPS AND ORGANIZERS

1. Dataflow Computing

Guang Gao
McGill University
514-398-4446
gao@andy.cs.mcgill.ca

Jean-Luc Gaudiot
Univeristy of Southern California
(213) 740-4484
gaudiot@usc.edu

Lubomir Bic, University of California, Irvine
(714) 856-5248
bic@ics.uci.edu


2. Future Multicomputers: Beyond Minimalist Multiprocessors?

Andrew A. Chien
University of Illinois
(217) 333-6844
achien@cs.uiuc.edu

Daniel Reed
University of Illinois
(217) 333-3807
reed@cs.uiuc.edu

Justin Rattner
Intel


3. Graphics Architectures & Algorithms

David Mizell
Boeing Computer Services
Research & Technology
(206) 865-2705
mizell@espresso.boeing.com

Fred Kitson
c/o Carmen Ramos
Hewlett Packard Labs
(415) 857-3604
ramos@hplabs.hp.com


4. Optical Computing Systems: Architectures and Algorithms

THIS WORKSHOP HAS BEEN CANCELED


5. High Performance Special-Purpose Architectures

Heiko Schroder, Univeristy of Newcastle, AUS
heiko@venus.newcastle.edu.au

David Abramson, Commonwealth Scientific and Research Organisation, AUS
davida@mel.dit.csiro.au
61 3 282 2666
From: rminnich@super.super.org (Ronald G Minnich)
Newsgroups: fj.mail-lists.parallel
Subject: Re: Atomic read/writes to memory in SMMs
Date: 7 Apr 92 11:38:37 GMT
Distribution: fj

In article <1992Apr6.230404.4322@hubcap.clemson.edu> kweber@Snake.mcs.kent.edu (Ken Weber) writes:
>What I am referring to is the ability for a 32-bit value to be either written
>or read atomically from a memory location.  I could envision the situation
>where a read/write may work with only 16 bits of a value at a time.  This
>could lead to the following situation:

oh, i see now. Well, if anyone out there can think of a multiprocessor, 
BUILT AFTER 1980 (see, i get out of having to worry about C.mmp and CM*)
that was not a true 32-bitter, I would be interested in hearing about 
it. To further restrict things, I won't count (e.g.) 
8086 cards in a multibus rack, as lots of these were done for industrial 
control, but they hardly count as multiprocessors in the same sense as
a Sequent. 

But, for your case Ken, I think it safe to assume that 32-bit
writes are atomic. 

someone want to show me wrong?
ron
From: MXD120@psuvm.psu.edu
Newsgroups: fj.mail-lists.parallel
Subject: Raytracing on a CM
Date: 6 Apr 92 15:22:59 GMT
Article-I.D.: nttlab.283113
Distribution: fj

I have a friend who has access to a Connection Machine and we were
thinking of compiling a raytracer on it (DKB or Rayshade) to create
frames for animation.  I know that the code has to be optimized to
run on a parallel machine, but I'm not sure how to do this.  Has
anybody out there done this?  The most logical way, to me at least,
of accomplishing this would be to send each line to a different
processor.  Any ideas?

Matthew "Beaker" Donadio      / INCLUDE "disclaimer.dat"
Penn State                   /
mxd120@psuvm.psu.edu        /   OBJECT
donadio@wilbur.psu.edu     /      Disclaimer
From: tjebelea@risc.uni-linz.ac.at (Tudor Jebelean)
Newsgroups: fj.mail-lists.parallel
Subject: systolic hardware?
Date: 12 Apr 92 23:11:51 GMT
Distribution: fj

My institute (RISC - Linz) is planning to buy some hardware based
on the cellular automata and/or systolic approach.

Can somebody help me with some hints on how to find information
about such devices available on the market?

Are there people which have already used such devices and who would
help me with a [short] description of their experience?

Thank you very much,

Tudor Jebelean            Phone: Austria-7236-3231-20
RISC - Linz,              Fax:   Austria-7236-3338-30
A-4040 Linz, Austria      E-mail: tjebelea@risc.uni-linz.ac.at
From: overeind@fwi.uva.nl (Benno Overeinder)
Newsgroups: fj.mail-lists.parallel
Subject: Asynchronous communication with use of synchronous primitives
Date: 6 Apr 92 15:24:47 GMT
Article-I.D.: nttlab.283129
Distribution: fj

Good day!

I am interested in references to articles or on-going work (or whatever)
which touch upon the implementation of a buffered asynchronous communication
layer with use of synchronous primitives.

In particular, I am interested in the implementation of such an asynchronous
layer on a transputer network. I don't want to use the CSN primitives of 
CSTools, which provides asynchronous communication primitives, because the
communication setup time is much to large for the small messages I have to 
send.

Summary: I like to receive any response or critique considering the 
	 asynchronous communication layer.


Thanks in advance,

  Benno
-- 
===========================================================================
 Benno Overeinder			 Computer Systems Department	     
 					 University of Amsterdam	    
 e-mail: overeind@fwi.uva.nl		 The Netherlands
From: yariva@gemini.math.tau.ac.il (Aridor Yariv )
Newsgroups: fj.mail-lists.parallel
Subject: hardware support for fine-grained comp.
Date: 14 Apr 92 18:01:10 GMT
Distribution: fj

I am working on a parallel language which combines functional and object 
oriented subsets. In general the implementation is based on light-weight tasks
which as usual, causes overhead (in every processor) due to their
allocation/scheduling/context-switch.

I am looking for references on SPECIAL HARDWARE FEATURES which helps to overcome
this local overhead like : 

1. co-processors/hardware which prepare (IN PARALLEL) the next task(process) in the 
   queue for work (Make ready the relevant data in registers). 

2. Special machine instructions. 

Are there any articles on this subject ? 

Thanx for the cooperation.

	- Yariv Aridor
	  E-mail:yariva@math.tau.ac.il

paper address:

Yariv Aridor
Computer Science Dept.
Tel-Aviv university
Ramat-Aviv
Tel-Aviv 69978
ISRAEL
From: tardif@outaouais.ulaval.ca (Pierre-Martin Tardif)
Newsgroups: fj.mail-lists.parallel
Subject: Portable compiler
Date: 15 Apr 92 20:25:20 GMT
Distribution: fj

I just like to know where and how people are doing research about
a portable compiler for the parallel computers (independant of
the architecture) ?
-- 
Pierre-Martin Tardif, etudiant gradue  (email: tardif@gel.ulaval.ca)
Laboratoire de Vision et Systemes Numeriques
Universite Laval, Pavillon Adrien-Pouliot, local 00100-I, Ste-Foy, Quebec,
Canada, G1K 7P4         (418-656-2131, ext 4848)
From: leech@cs.unc.edu (Jon Leech)
Newsgroups: fj.mail-lists.parallel
Subject: Re: parallel fast multipole method
Date: 12 Apr 92 23:10:59 GMT
Distribution: fj

In article <1992Apr6.152353.21846@hubcap.clemson.edu>, banshee@cats.UCSC.EDU (Wailer at the Gates of Dawn) writes:
>	I've seen very little actual use of the FMM, most of the above is
> benchmarking and algorithm proofs.

    Is this due to a large constant factor, because people haven't yet
spent the effort to work it into their codes, or some other cause?
--
    Jon Leech (leech@cs.unc.edu)    __@/
    "Student Activism 1968-69 Oct 23: 15 students picket the Circus
     Room to protest the poor quality of UNC sandwiches."
	_The Daily Tar Heel_, 11/15/89
From: kcollins@convex.com (Kirby L. Collins)
Newsgroups: fj.mail-lists.parallel
Subject: Has anyone read Green Parallel Processing for Computer Graphics?
Date: 14 Apr 92 18:00:57 GMT
Distribution: fj

I just got the latest MIT Press flyer, and it describes a book by
Stuart Green titled "Parallel Processing for Computer Graphics".
According to the blurb it "provides background information on both
computer graphics and parallel computers and then goes on to 
describe how a distributed memory multiprocessor can be used to
effectively implement the ray tracing algorithm."

Anyone read a copy of this book yet?
From: oudelutt@cs.utwente.nl (Paul Oude-Luttighuis)
Newsgroups: fj.mail-lists.parallel
Subject: Looking for recent papers on parallel lexing/parsing
Date: 6 Apr 92 15:24:24 GMT
Article-I.D.: nttlab.283124
Distribution: fj


   Dear readers of this newsgroup,

  I am looking for the text of two papers presented at the 6th 
  International Parallel Processing Symposium (Berverly Hills, CA, 
  USA, March 23--26, 1992).  The proceedings have, of course, not 
  appeared yet at our library.  Still, I would like to read them 
  quickly in order to be able to include them in a soon to appear 
  annotated bibliography on parallel parsing.  Is there any way to 
  get the text of the following two papers quickly (maybe via the 
  authors themselves)?

    C.R. Asthagiri & J.L. Potter
    Associative parallel lexing

    W. Deng & S. Sitharama Iyengar
    Parallel algorithms for arithmetic expression parsing

  Thanks!

  Paul Oude Luttighuis
  Dept. of Computer Science
  University of Twente
  P.O. Box 217
  NL-7500 AE  Enschede
  The Netherlands
From: ewilts@mr.gov.bc.ca (Ed Wilts)
Newsgroups: fj.mail-lists.parallel
Subject: DECmpp and Vax 9000 chargeback
Date: 14 Apr 92 12:32:48 GMT
Distribution: fj

I'm looking for some typical commercial billing rates for the following systems:
	Vax 9000-420 with 2 vector processors
	MasPar MP-1 1200 with 8192 processors (aka DECmpp 12000)
We're in the process of setting up a research center and are interested in
hearing what other people charge.  How much do you charge per CPU hour?  Does
this include disk space or network access charges?  For background information,
this setup is based on a rather sizable donation from Digital.  Our rates will
take into account the fact that we don't have to recover capital costs, but I
need to know just how attractive we're going to be sitting.

On a side note, this research center is being set up for limited production
starting in May.  For the first 6 months or so, we'll be offering EXTREMELY
attractive rates until we ramp up our BC-based customer base.  If you have a
task that you're stating is research and are looking for cheap cycles, please
contact me.

Any billing will be greatly appreciated.

-- 
Ed Wilts, BC Systems Corp., 4000 Seymour Place, Victoria, B.C., Canada, V8X 4S8
EWilts@MR.Gov.BC.CA   |   Ed.Wilts@BCSystems.Gov.BC.CA   |   (604) 389-3430
From: tj@alliant.com (Tom Jaskiewicz)
Newsgroups: fj.mail-lists.parallel
Subject: Re: Atomic read/writes to memory in SMMs
Date: 12 Apr 92 23:11:24 GMT
Distribution: fj

In article <1992Apr6.230404.4322@hubcap.clemson.edu> kweber@Snake.mcs.kent.edu (Ken Weber) writes:
>What I am referring to is the ability for a 32-bit value to be either written
>or read atomically from a memory location.  I could envision the situation
>where a read/write may work with only 16 bits of a value at a time.  This
>could lead to the following situation:
>
>Process 1 writes to low 16 bits of location A
>Process 2 writes to low 16 bits of location A
>Process 2 writes to high 16 bits of location A
>Process 1 writes to high 16 bits of location A

This exact problem could occur in the Alliant FX/8.  An FX/8 could
contain up to 8 CE processors and up to 12 IP processors.  The CE's
could do atomic reads and writes of 64 bits at a time.  The IP's were
powered by Motorola 68012's and could only do atomic reads and writes of
16 bits.

User code rarely had a problem with this.  Most multiprocessing with
shared memory by user code was done only on CE's.  However, the
CONCENTRIX kernel had nearly all of its data structures in memory shared
by all the CE's and IP's.  The situation you describe above not only
could occur, it DID occur.  (It caused some very strange bugs).

In article <1992Apr7.113842.26166@hubcap.clemson.edu> rminnich@super.super.org (Ronald G Minnich) writes:
]oh, i see now. Well, if anyone out there can think of a multiprocessor, 
]BUILT AFTER 1980 ...

]But, for your case Ken, I think it safe to assume that 32-bit
]writes are atomic. 
]
]someone want to show me wrong?

The FX/8 was announced in 1985.
-- 
##########################################################################
# The doctrine of nonresistance against arbitrary power, and oppression is
# absurd, slavish, and destructive of the good and happiness of mankind.
#   -- Article 10, Part First, Constitution of New Hampshire
From: jabf@festival.edinburgh.ac.uk
Newsgroups: fj.mail-lists.parallel
Subject: BCS PPSG AGM Lecture
Date: 12 Apr 92 23:09:41 GMT
Distribution: fj


                 The  British  Computer  Society
             Parallel  Processing  Specialist  Group

                           (BCS PPSG)

                    The 1992 A.G.M. Lecture :


             Should the U.K. have a High Performance
                    Computing & Communications
                     co-ordinated programme ?

                               by

                    Dr. Geoff Manning C.B.E.

               Chairman, Active Memory Technology

                       Tuesday May 5 1992

                            6.30 p.m.
                 Ambrose Fleming Lecture Theatre
                    University College London
                  Torrington Place,  London WC1
          (entrance directly opposite Dillons bookshop)

  (Attendance is free and open to all, members and non-members.
   No prior booking required. Refreshments will be available !)

Gone are the days when using a computer was an isolated localised
activity.   Networks  already enable the sharing of databases and
processor power spread across continents.  They are here to stay.
 So what are the integrated needs of computing and communications
going to be in the next millennium ?  Must supercomputers contin-
ue to be the preserve of a select few or should  they  accessible
by  all.   Must the highways of the future be capable of carrying
gigabits of data per second ?  Is  the  required  investment  too
large  for  the UK to take on single-handedly ?  How can Industry
and Government best collaborate ?


Dr Geoff Manning is the Chairman  of  Active  Memory  Technology,
manufacturers  of  the  massively parallel Distributed Array Pro-
cessor (DAP) and is Chairman (designate) and acting CEO of the UK
Education and Research Networking Association (UKERNA) that is to
be established to operate the UK academic  network.   He  is  em-
inently  qualified to speak on this  subject his past accomplish-
ments including heading the High Energy Physics  Division  &  the
Atlas  Computing Division at the Rutherford Laboratory and becom-
ing Director of the Rutherford Appleton Laboratory.  His  experi-
ence  includes the purchase and management of central and distri-
buted systems and 35 years use of a wide range of machines.

         PPSG members are further invited to attend the
      Committee Meeting (from 3 p.m. in Room 110) and the
                 A.G.M. which starts at 6 p.m.
            (in the Ambrose Fleming Lecture Theatre)
From: bourne-linda@CS.YALE.EDU (Linda Bourne)
Newsgroups: fj.mail-lists.parallel
Subject: Alan J. Perlis Symposium
Date: 12 Apr 92 23:10:24 GMT
Distribution: fj

ALAN J. PERLIS SYMPOSIUM:  Parallel Computers of the Future

Sponsored by the Department of Computer Science, Yale University

April 23, 1992

Sheffield-Sterling-Strathcona Hall
Room 114
Corner Grove and Prospect Streets
New Haven, Connecticut


Morning Session (9:30-11:00)

	Opening Remarks
		Drew McDermott
		Chairman, Yale CS

	"Dataflow Architectures:  From Monsoon to *T"
		Arvind
		Massachusetts Institute of Technology


Afternoon Session (1:30-4:30)

	"PRAMs:  Theory, Physical Design, and Application"
		Wolfgang Paul
		University of Saarbrucken

	"Will Parallel Architectures Converge?"
		H.T. Kung
		Carnegie-Mellon University



Following the last talk a public reception will be held at the
Department of Computer Science, Arthur K. Watson Hall.

All talks are free and open to the public.

For further information please call (203) 432-1246.
-------
From: freeman-elisabeth@CS.YALE.EDU (Elisabeth Freeman)
Newsgroups: fj.mail-lists.parallel
Subject: CM5 studies
Date: 12 Apr 92 23:12:09 GMT
Distribution: fj

I am doing an architecture project this semester on the CM5.  I would like
to find out if anyone has run any benchmarks or done any kind of performance 
studies on the CM5.

Please send email to: freeman-elisabeth@cs.yale.edu

Thanks,

Beth Freeman
From: kweber@Snake.mcs.kent.edu (Ken Weber)
Newsgroups: fj.mail-lists.parallel
Subject: Re: Atomic read/writes to memory in SMMs
Date: 6 Apr 92 23:03:55 GMT
Distribution: fj

In article <1992Apr6.152327.21611@hubcap.clemson.edu> rminnich@super.super.org (Ronald G Minnich) writes:
>
>I assume you mean atomic read-modify-write (RMW)?
>

What I am referring to is the ability for a 32-bit value to be either written
or read atomically from a memory location.  I could envision the situation
where a read/write may work with only 16 bits of a value at a time.  This
could lead to the following situation:

Process 1 writes to low 16 bits of location A
Process 2 writes to low 16 bits of location A
Process 2 writes to high 16 bits of location A
Process 1 writes to high 16 bits of location A

Thus in location A we have the low bits from process 2 and the high bits
from process 1.  

I am wondering on how many machines I need to lock the memory (using atomic
test-and-set) when I do a 32-bit read/write?  Further, is even a 16-bit
read/write always safe?  (I assume without proof that a 1-byte read/write is
safe.)

Ken Weber Dept. of Math & Comp. Sci. KSU, Kent, OH 44242

P.S.  Thanks for your input, Ron
From: vu0208@bingvaxu.cc.binghamton.edu (!)
Newsgroups: fj.mail-lists.parallel
Subject: Re: Fast window summation on a SIMD machine
Date: 16 Apr 92 12:20:55 GMT
Distribution: fj

In article <1992Apr14.180225.182521@cs.cmu.edu> you write:
>    I am looking for an idea for a high-performance algorithm for
>    the following problem:
>
>	I have a large SIMD machine (maspar) with an image distributed
>	across the 2-dimensional array of processors.  Each processor has
>	a small (8*8), square piece of the image.  I want to produce a new
>	image in which the new pixels represent the sum, in the original
>	image, of a large (64*64) window around that pixel.  
>
>	Currently, I copy the large window of pixels onto each processor from
>	the surrounding processors and then perform an efficient window
>	summation algorithm without having to do any further communication.
>	This is very inefficient because each processor is duplicating many
>	of the additions of its neighbors.
>
>	Any ideas?  Pointers to published references?
>
>    Thanks!
>    Bill Ross
>    br@cs.cmu.edu 
>

correct me if i am wrong in understanding your problem!

if each square below represents a 8*8 pixel contained in a processor,



       (a)
-------------------------------
| | | |8|8|8| | | | | | | | | |
-------------------------------
| | | |8|x|8| | | | | | | | | |
-------------------------------
| | | |8|8|8| | | | | | | | | |
-------------------------------
| | | | | | | |8|8|8|8|8|8|8|8| 
------------------------------- 
| | | | | | | |8|8|8|8|8|8|8|8| 
-------------------------------
| | | | | | | |8|8|8|8|8|8|8|8|
-------------------------------  (b)
| | | | | | | |8|8|8|8|8|8|8|8|
-------------------------------
| | | | | | | |8|8|8|8|8|8|8|8|
-------------------------------
| | | | | | | |8|8|8|8|8|8|8|8|
-------------------------------
| | | | | | | |8|8|8|8|8|8|8|8|
-------------------------------
| | | | | | | |8|8|8|8|8|8|8|8|
-------------------------------


what you want to do is generate a new image pixel 'x', which is sum of
pixels labeles '8' above...in (a) is that right? i don't understand 64*64
size, which means 8x8 squares in the above diagram (b)! Are you condesing
the image that big into a 8x8 pixel ?

The replication in additions can be avoided if you partition the large
windows such that they don't overlap, and then finding the sum of a
window will generate a new image completely independent of the cells
outside the large window (assuming large window = 64x64 sq.pixels).

If you need algorithm on that i can work on it....

Please let me know if my understanding of the problem is correct, is
it (a) or (b) that you are doing?
From: gtoal@robobar.co.uk
Newsgroups: fj.mail-lists.parallel
Subject: Re: Transputer dead?
Date: 6 Apr 92 23:05:27 GMT
Article-I.D.: nttlab.283284
Distribution: fj

In article <1992Apr1.165109.12132@hubcap.clemson.edu> thompson@inmos.co.uk (Peter Thompson) writes:
:I'm happy to say that time will prove you wrong.  We have plenty of customers
:eagerly awaiting the T9000 whom we do not intend to disappoint.  In any case
:it would hardly be "good business sense" for the corporation to can the
:project now after so much has been invested in it.

Can't comment on the transputer-wars, but I've seen enough companies go
down through throwing good money after bad because some MD had a personal
hobbyhore he wanted ridden than I can confidently disagree with your
'hardly be "good ..."' comment.

Graham (who is thinking of applying the dsame logic to his London flat...)
--
From: bic@cj2.ICS.UCI.EDU
Newsgroups: fj.mail-lists.parallel
Subject: Workshops at ISCA'92 -- Australia
Date: 6 Apr 92 15:23:38 GMT
Article-I.D.: nttlab.283115
Distribution: fj

A series of Workshops will be held at the Architecture Symposium
(ISCA'92) this May. If you would like to attend, please contact me to
receive travel and other information.

Lubomir Bic, Workshops Chair
University of California, Irvine
bic@ics.uci.edu
(714) 856-5248


                          ISCA'92

            INFORMATION ON ARCHITECTURE WORKSHOPS

DATES

There will be three 2-day workshops and 1 one day workshop. The
dates are May 24-25, 1992.

LOCATION

All Workshops will be held on Hamilton Island (a part of the
Whitsunday Island group), which is a very popular vacation resort on
the Great Barrier Reef.


LIST OF WORKSHOPS AND ORGANIZERS

1. Dataflow Computing

Guang Gao
McGill University
514-398-4446
gao@andy.cs.mcgill.ca

Jean-Luc Gaudiot
Univeristy of Southern California
(213) 740-4484
gaudiot@usc.edu

Lubomir Bic, University of California, Irvine
(714) 856-5248
bic@ics.uci.edu


2. Future Multicomputers: Beyond Minimalist Multiprocessors?

Andrew A. Chien
University of Illinois
(217) 333-6844
achien@cs.uiuc.edu

Daniel Reed
University of Illinois
(217) 333-3807
reed@cs.uiuc.edu

Justin Rattner
Intel


3. Graphics Architectures & Algorithms

David Mizell
Boeing Computer Services
Research & Technology
(206) 865-2705
mizell@espresso.boeing.com

Fred Kitson
c/o Carmen Ramos
Hewlett Packard Labs
(415) 857-3604
ramos@hplabs.hp.com


4. Optical Computing Systems: Architectures and Algorithms

THIS WORKSHOP HAS BEEN CANCELED


5. High Performance Special-Purpose Architectures

Heiko Schroder, Univeristy of Newcastle, AUS
heiko@venus.newcastle.edu.au

David Abramson, Commonwealth Scientific and Research Organisation, AUS
davida@mel.dit.csiro.au
61 3 282 2666

---------------------------------END------------------------------------
From: fineberg@eng.uiowa.edu (Sam Fineberg)
Newsgroups: fj.mail-lists.parallel
Subject: PARAFRASE
Date: 15 Apr 92 20:24:38 GMT
Distribution: fj

I would like some information on a package called PARAFRASE.  My
understanding is that it does some static code analysis for automatic
parallelization,  What I am most interested in is what information does it
gather that could be used for further code restructuring.  For example,
dopes it provide a data-dependence graph.  Also, how does one obtain the
package, i.e., is it available via anonymous FTP or is it only available 
commercially from Kuck and Associates.


Thanks,
Sam Fineberg
-- 
Samuel A. Fineberg                 Department of Elect. and Comp. Engr.
fineberg@eng.uiowa.edu             University of Iowa
Voice: (319)335-5962               Iowa City, IA  52242, USA
FAX: (319)335-6028