HDTenEightyP/NetNews huggingface dataset:
From: nyq@jupiter.esd.ornl.gov (Jon E. Nyquist)
Subject: Autocad and PVWave
Keywords: pvwave,acad,graphical editing
Organization: ORNL-ESD Earth Sciences Modeling Center
Date: Mon, 25 Jan 1993 19:48:10 GMT

I use PV-Wave to analyze geophysical data and often wish there were
a simple way to overlay AutoCad information such as rivers, roads,
buildings, etc., on top of a PV-Wave image such as produced by
image_cont.  I have a quick-and-dirty filter that strips polylines
out of an AutoCad dxf file and writes a file I can overplot with
oplot.  Unfortunately, I lose all text information as well as more
complicated graphical objects such as symbols, ellipses, circles, etc.

Has anyone written a more sophisticated filter?  How about going the
other way: read a PV-Wave image into Acad v10?  Any public domain 
graphical editors that let me take an PV-Wave cgm or tiff file and 
and text, lines, boxes, etc., would be useful as well, but I would
still have to recreate all the information in the AutoCad drawing.

Thanks!


-- 
Jonathan E. Nyquist
nyq@ornl.gov
Geology and Geophysics Group
Environmental Sciences Division
Oak Ridge National Laboratory
P.O. Box 2008
Oak Ridge,TN  37831-6317
(615) 574-4646
(615) 574-7420 Fax
Newsgroups: comp.lang.vhdl
From: daniel@clsi.COM (Daniel S. Barclay)
Subject: Re: VHDL: arrays
Organization: CAD Language Systems Inc.
Date: 21 Jan 93 14:10:33

> I try to become conversance with VHDL, especially
> the structure architecture.
> I have the following question:
>   How can you define a multi-dimensional array of
>   components ? (for creating a design hierarchy with components)
> 
>   e.g. 
> 
>        Structural description of Counter is
> 
>            Component And2 
> 	      port(I1, I2: in BIT;
> 	           O1:     out BIT)
>             end Component;
> 
>         begin
> 	   -- array of instances of component And2 
> 	   ????
> 	   ????
> 	   -- e.g. :array with width=10 of instances 
> 	            refering to component And2
> 
> 	end Structure;
> 
> Is it possible in building Cell descriptions?

Have you tried the generate statement with a "for" iteration scheme?

E.g.,
	
	for i in 1 to 10 generate
	    C: And2 (I1 => p1(i), I2 => p2(i), O1 => p3(i));
	end generate;

Is that the type of thing you're trying to do?
--
------------------------------------------------------------------------------
Daniel S. Barclay                    --who's still searching for a good 
CAD Language Systems, Inc.           signature, not liking any of his recent
Suite 101, 5457 Twin Knolls Rd.      feeble attempts to improve on the whiny:
Columbia, MD  21045  USA             Why can't _I_ think of a good signature?
From: 8809787l@levels.unisa.edu.au
Newsgroups: comp.lang.vhdl
Subject: Need Help with VHDL, please.
Date: 29 Jan 93 15:17:46 +1030
Organization: University of South Australia

Dear readers

I am undertaking a PhD in Design and Diagnosis ( eg. design for testability,
test generation etc are involved in my work) as a result I have been asked to
get familiar with VHDL and to study it in some detail.

I am at the moment very much ignorent of hardware descriptive languages and so
I was wondering if any one out there who is experienced in this field could
provide me with some references on this topic which could get me going.
Also I have recently installed LINUX on my 486 PC which is a PD UNIX
envrionment so is there any way that I could get a PD software to help me learn
VHDL or not ?

Thank you for your time.

With Highest Regards

Peyam Pourbeik
University of South Australia
School of Electronics

Newsgroups: comp.lang.vhdl
From: daniel@clsi.COM (Daniel S. Barclay)
Subject: Re: Status of VHDL 92???
Organization: CAD Language Systems Inc.
Date: 21 Jan 93 14:14:19

> Can anybody tell me what the status is of VHDL 92?  Is there a draft
> standard?  Has it been voted on?  Has it been adopted?

The VHDL 1992 draft was voted on and passed.  However, the VASG is applying
changes from the negative ballot process, and the resulting revised LRM
must be reballoted (I think).

Check with Stan Krolikoski (VASG Chair) for more details, at my address with 
"daniel" replaced by "stank".

--
------------------------------------------------------------------------------
Daniel S. Barclay                    --who's still searching for a good 
CAD Language Systems, Inc.           signature, not liking any of his recent
Suite 101, 5457 Twin Knolls Rd.      feeble attempts to improve on the whiny:
Columbia, MD  21045  USA             Why can't _I_ think of a good signature?

Newsgroups: comp.lang.vhdl
From: jcooley@world.std.com (John Cooley)
Subject: Joining ESNUG
Organization: The E-mail Synopsys Users Group (ESNUG)
Date: Thu, 21 Jan 1993 05:44:56 GMT


  If you're using the Synopsys Design Compiler and/or their ATPG product, you 
  might be interested in joining the E-Mail Synopsys Users Group (ESNUG).

  What we are is a group of hardware designers from all over the world who
  wish to trade experiences, bug reports and the techniques that we've
  found that work best in getting a design from a behavioral description
  to a final fully tested product.  This is a grassroots forum independent
  of Synopsys, Inc.

  A Sample of What We Discuss:

	- Known Synopsys Compiler Bugs    - Implementing Boundry Scan

	- Mentor related issues    - EDIF related issues

	- Hierarchical Compliations   - design_analyzer   - JTAG

	- How Various ASIC Vendors Model Their Macros.   - Clock Constraints

	- Using ATPG Tools   - The Best Way To Write State Machines in Verilog

	- Using VHDL   - System Simulation vs. Synopsys Friendly Code

	- Clever Workarounds to Known Pitfalls   - Testing Strategies

  In order to insure an open discussion, but yet keep our respective managers
  happy in having our company's projects remain SECRET, submissions to be 
  posted to the ESNUG mailing list can be stripped of identifying engineers 
  and company names if so requested.

  In addition, to further secure privacy and to avoid e-mail headers that
  are hundreds of names long, each mailing is a batch of singlely addressed 
  e-mail letters.

  If you want to join ESNUG, please send me e-mail to "jcooley@world.std.com"
  saying you wish to join and why.  (Please don't send a copy of this letter
  back to me, I know what you're refering to when you're writing.)

					- John Cooley
					  ESNUG Moderator

 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
     /o o\  /  it's a FEATURE!"   |    Backup Address: jcooley@miracle.com
    (  >  )                       |              (508) 429-4357
     \ - /       |   Snail Mail: P.O. Box 6222, Holliston, MA 01746-6222
     _] [_       |     "This here ain't no one's opinion 'cept my own."


Newsgroups: comp.lang.vhdl
From: mitch@clsi.COM (Mitchell N. Perilstein)
Subject: Re: REQUEST: VHDL <-> C tools
Organization: CAD Language Systems, Inc.
	<1jjmvbINNo7m@srvr1.engin.umich.edu>
Date: 22 Jan 93 18:36:16

CLSI has a product called the Retargetable VHDL Code Generator.  It is
part of our integration platform and simulation system.  The code
generated is C.

Mail mitch@clsi.com if you would like more information.

---
 Mitchell N. Perilstein   CAD Language Systems, Inc.   410-992-5700 x225 
 Member, League for Programming Freedom.  Mail lpf@uunet.uu.net for info.
Newsgroups: comp.lang.vhdl
From: parviz@bcrkd10.bnr.ca (Parviz Yousefpour)
Subject: The Ottawa Region VHDL User Group meeting
Organization: Bell-Northern Research, VHDL Group
Distribution: can
Date: Thu, 21 Jan 1993 14:52:24 GMT

The second Ottawa Region VHDL User Group meeting is being held at the

                Lord Elgin Hotel
                Ottawa, Ont.
                Feb 15-16, 1993

The user meeting will include an emphasis on users' experiences with
VHDL, one day modeling techniques and synthesis course, and EDA vendor
presentation & demos.  Here is the agenda for the meeting

  Feb 15th.   Course: VHDL in Modeling and Synthesis
              Cost $100.00 
              A one-day introductory course 
                 By: Prof. E.M Aboulhamid, E. Cerny, U.of.M
     08:30       VHDL Familiarization & Modeling Technique
     15:00       VHDL Modeling for Synthesis.

  Feb 16th.   VHDL User Group Meeting and EDA Presentation
              Cost $15:00 
     09:00       Arrival and Registration
     09:15       DSP Verification and Implementation Using VHDL
                    By: Janick Bergeron, Bell-Northern Research
     10:15       Rapid Development of High-Level VHDL Models
                    By: Karim Khordoc, University of Montreal
     11:15       Case studies of using VHDL for high level design
                    By: Appl. Engineer from Synopsys
     12:00       Lunch
     01:00       Technical Presentations & Demos
                    - VIP Hardware Accelerator by ZYCAD
                    - Demonstration of high level design by Synopsys
                    - Other topics to be announced.

For further information and registration, please contact:

Parviz Yousefpour         Dennis Lenard           Azzedine Boubguira
Bell-Northern Research    Computing Devices Co.   LSI Logic Corp, Canada
P.O. Box 3511, Stat C     P.O Box 8508            Suite 400, 260 Hearst Way
Ottawa, Ontario           Ottawa, Ontario         Kanata, Ontario, K2L 3H1
Tel: (613) 763 8697       Tel: (613) 596 7744     Tel: (613) 592 1263
Fax: (613) 763 7241       Fax: (613) 596 7334     Fax: (613) 592 3253
email: parviz@bnr.ca
From: thole@peanuts.informatik.uni-tuebingen.de (Peter Thole)
Newsgroups: comp.lang.vhdl
Subject: struct. VHDL to EDIF ?
Date: 25 Jan 1993 12:23:10 GMT
Organization: "Lehrstuhl fuer Technische Informatik, Uni Tuebingen"
Distribution: world
NNTP-Posting-Host: bill.informatik.uni-tuebingen.de

I'm searching for a tool, that transfers a structural VHDL description 
(with no more information than a netlist) to EDIF or an other wide 
spread netlist format like XNF or BLIF. The tool has not to be public
domain by necessity, but that would be prefered :->.

Regards,
	Peter

-- 
***************************************************
< Peter Thole                                     >           
< Universitaet Tuebingen                          >           
< Lehrstuhl fuer technische Informatik            >           ^
< Sand 13, 7400 Tuebingen, Germany                >          _/\
< Tel.: (++49)|(0)-(7071)-29-5865                 >         C__/-
< email thole@peanuts.informatik.uni-tuebingen.de >         /\\ /\
< IRC: speiche		channel: #tuebingen       >         \/  \/ 
****************************************************************************
Newsgroups: comp.lang.vhdl
From: hofstede@cs.utwente.nl (Jaap Hofstede)
Subject: Re: YACC-grammar for VHDL wanted
Organization: University of Twente, Dept. of Computer Science
Date: Mon, 25 Jan 1993 13:08:39 GMT

fs2@irz202.inf.tu-dresden.de (Frank Stolle) writes:
> 
> I'm looking for a conflict-free YACC-grammar for VHDL. If anybody knows 
> where to get one, please tell me.
> 

I have a conflict-free grammar for VHDL. However it is not for YACC, but for LALR, the parser generator
of the GMD compiler tool box from Karlsruhe. Conversion to YACC should be quite easy.
The grammar has been announced on the net about half a year ago and it is distributed to about 40
people. If you are interested, please send me mail.

--
Jaap Hofstede (hofstede@cs.utwente.nl)

Jaap Hofstede                             Tel:   +31 53 893788
Dept. of Computer Science (INF/SPA)       Fax:   +31 53 356531
University of Twente                      Email: hofstede@cs.utwente.nl
PB 217
NL-7500 AE ENSCHEDE
The Netherlands
From: dank@blacks.jpl.nasa.gov (Daniel R. Kegel)
Newsgroups: comp.lang.vhdl
Subject: Futurenet to VHDL/Verilog converter, anyone?
Date: 22 Jan 93 18:43:55 GMT
Organization: Image Analysis Systems Group, JPL
NNTP-Posting-Host: blacks.jpl.nasa.gov

Hi,
I'm about to write a program to convert Futurenet netlist files
into VHDL or Verilog modules.  Has anyone else already done this
or a similar converter, so I can save myself some work?
- Dan Kegel (dank@blacks.jpl.nasa.gov)
Newsgroups: comp.lang.vhdl
From: daniel@clsi.COM (Daniel S. Barclay)
Subject: Re: VHDL: arrays
Organization: CAD Language Systems Inc.
Date: 21 Jan 93 14:10:05

> I try to become conversance with VHDL, especially
> the structure architecture.
> I have the following question:
>   How can you define a multi-dimensional array of
>   components ? (for creating a design hierarchy with components)
> 
>   e.g. 
> 
>        Structural description of Counter is
> 
>            Component And2 
> 	      port(I1, I2: in BIT;
> 	           O1:     out BIT)
>             end Component;
> 
>         begin
> 	   -- array of instances of component And2 
> 	   ????
> 	   ????
> 	   -- e.g. :array with width=10 of instances 
> 	            refering to component And2
> 
> 	end Structure;
> 
> Is it possible in building Cell descriptions?

Have you tried the generate statement with a "for" iteration scheme?

E.g.,
	
	for i in 1 to 10 generate
	    C: And2 (I1 => p1(i), I2 => p2(i), O1 => p3(i));
	end;

Is that the type of thing you're trying to do?
--
------------------------------------------------------------------------------
Daniel S. Barclay                    --who's still searching for a good 
CAD Language Systems, Inc.           signature, not liking any of his recent
Suite 101, 5457 Twin Knolls Rd.      feeble attempts to improve on the whiny:
Columbia, MD  21045  USA             Why can't _I_ think of a good signature?
From: sr@mp.co.umist.ac.uk (Simon Read)
Newsgroups: comp.lang.vhdl
Subject: Re: YACC-grammar for VHDL wanted
Date: 22 Jan 93 12:23:05 GMT
Organization: UMIST Sun 630, Manchester Computing Centre, UK

In article <1jjqirINN2hv@irz401.inf.tu-dresden.de> fs2@irz202.inf.tu-dresden.de (Frank Stolle) writes:

   Hi experts !

   I'm looking for a conflict-free YACC-grammar for VHDL. If anybody knows 
   where to get one, please tell me.

   Thanks in forward !

   Frank Stolle

   ------------------------------------------------------------------------------
   Frank Stolle
   Department of Computer Science
   Dresden University of Technoloy

   stolle@irzr17.inf.tu-dresden.de                        Nal komerex khesterex !
   stolle@freia.inf.tu-dresden.de
   ------------------------------------------------------------------------------

As far as I know there isn't one in the Public Domain for all of VHDL
1076-1987. I have made one available for a subset. It's available by
ftp from suna.co.umist.ac.uk [192.84.84.1] it's in pub/sr and it's
called parser.tar.Z.

I am working on a complete grammar at the moment, (in fact the window
below the news reader is an emacs of the new parser) any collaboration
would be gratefully accepted (all work is returned to the PD). This
parser will be suitable for use in bison++ and C++, conversion to C
should be fairly easy though!

More details can be obtained from ....

Simon Read
----------
Simon.Read@umist.ac.uk
Newsgroups: comp.lang.vhdl
From: dank@cco.caltech.edu (Daniel R. Kegel)
Newsgroups: comp.lang.vhdl,caltech.compsci.cartel
Subject: Writing a tool to convert digital circuit netlists to VHDL
Date: 29 Jan 1993 02:54:41 GMT
Organization: California Institute of Technology, Pasadena
NNTP-Posting-Host: punisher.caltech.edu

I'm starting to design a netlist converter in C++ which will 
read in a Futurenet netlist and produce a structural VHDL netlist.
(VHDL is the up-and-coming hardware description language for digital
electronics design & simulation, if you hadn't heard the acronym before.
Futurenet is an el cheapo schematic capture package.)

I want to handle not just simple signals, but also arrays and records
(at least as far as the Futurenet format supports them).
I'm trying to decouple the netlist reading from the netlist writing
by representing the netlist in memory.  This ought to make it easy to 
add new input or output languages, such as EDIF, without having to 
rewrite the whole thing.

Right now, I'm still designing the classes that will make up the
internal representation.  The task reminds me of compiler design at the
moment.

If anyone is interested in working with me on this, or just kibitzing, please 
write me at dank@blacks.jpl.nasa.gov.  
- Dan Kegel
Newsgroups: comp.lang.vhdl
From: edlefsen@waters.mcrc.etdesg.trw.com (Steven J. Edlefsen)
Subject: Re: Verilog Librrary for parallel system design.
Organization: TRW, Inc., Redondo Beach...
Date: 26 Jan 93 17:39:14

In article <523@idtinc.UUCP> frazer@idtinc.UUCP (Andrew Frazer) writes:

>   Path: deneva!gumby.dsd.trw.com!venice!usc!sdd.hp.com!spool.mu.edu!uunet!idtinc!frazer
>   From: frazer@idtinc.UUCP (Andrew Frazer)
>   Newsgroups: comp.lang.vhdl
>   Date: 20 Jan 93 22:47:51 GMT
>   References: <C1314B.4zG@ccu.umanitoba.ca>
>   Reply-To: frazer@dtg.nsc.com
>   Organization: Integrated Device Technology, Santa Clara
>   Lines: 14
>
>   In article <C1314B.4zG@ccu.umanitoba.ca> shome@eeserv.ee.umanitoba.ca (Tapas Shome) writes:
>   >
>   >What I need immediately is that any advice on designing microprogrammable
>   >controller and certaily a nice library of 74ls/54 series structural
>   >description.
>   >
>
>   For Verilog HDL examples you could consult "Digital Design with Verilog HDL"
>   by Sternheim, Singh and Trivedi.  It costs about $60 now and is available from
>   Automata Publishing in Cupertino, CA.
>
>   Andy Frazer
>   Integrated Device Technology

Funny, EDN has started a series of articles called "Secrets of the Lost
Architecture"  an EDN Hands on VHDL Design Project.  The author of the article is
designing a Z80 microproccesor with VHDL.  The and BBS number from which the
code can be downloaded is listed in the article.
Xref: sparky comp.lang.vhdl:698 comp.lsi.cad:1354 comp.sys.mentor:357
From: frazer@idtinc.UUCP (Andrew Frazer)
Newsgroups: comp.lang.vhdl,comp.lsi.cad,comp.sys.mentor
Subject: Re: VHDL simulators: VHDLsim vs VSS ??
Date: 26 Jan 93 20:08:21 GMT
Reply-To: frazer@dtg.nsc.com
Followup-To: comp.lang.vhdl
Organization: Integrated Device Technology, Santa Clara

In article <C16JE5.6tp@utdallas.edu> clarkw@utdallas.edu (WILLIAM D CLARK) writes:
>
>I would like to ask for suggestions or experiences from those of you
>who have used either or both of these simulators.  All comments (good
>or bad) are welcome.  
>
>BTW -- the reason we believe our choice should be between these two is
>that we will be using Synopsys' Design Compiler for synthesis and
>Mentor's GDT IC tools for layout and schematic capture (if needed).
>We believe our interfacing problems will be minimized by using one of
>these two.  


If you've already decided on Mentor's schematic editor then you would probably
do well to limit your choices to Mentor and Synopsys.  However, if you're
not limited to their schematic editor, then you might wish to look at Viewlogic's
new VHDL simulator.  The Synopsys->Viewlogic path is very good, better than
the Synopsys->Mentor.  Viewlogic also has the advantage of having just aquired
Vantage Systems, who supposedly have the best _compiled_ VHDL simulator.

Andy Frazer


From: domi@marlis.grenoble.hp.com (Dominique DUMONT)
Date: Tue, 26 Jan 1993 13:52:41 GMT
Subject: run C over VHDL ???
Organization: Hewlett-Packard, GND
Newsgroups: comp.lang.vhdl

Is there a way to run C program over VHDL ?

What I'd like to do is to run a C driver on a simulator which would have the
VHDL behavioral model of a not_yet_finished_but_we're_working_on_it hardware.

Any idea ? Do you know if one can buy simulators with that kind of 
functionality ?

Thanks


-----------------------------------------------------------------------------
                Name:          Dominique Dumont 
    ^^^^^^      Email:         Dominique_Dumont@grenoble.hp.com
   / O  O \     HP Desk:       Dominique DUMONT / HP6300/UM
  ( \____/ )    Address :      HEWLETT PACKARD, 38053 Grenoble Cedex 09 FRANCE
   \______/     Tel,Telnet:    (33) 76 62 57 24 - 7 779 5724
                Telex,Fax:     980 124 - (33) 76 62 53 20
-----------------------------------------------------------------------------
From: shoeft@hsc.usc.edu (Sebastian Hoeft)
Newsgroups: comp.lang.idl
Subject: ignore: test
Date: 21 Jan 1993 14:14:04 -0800
Organization: University of Southern California, Los Angeles, CA
Distribution: la
NNTP-Posting-Host: hsc.usc.edu


this is just a test.
From: peba1231@camillo.fb12.tu-berlin.de (Peter Bartsch)
Newsgroups: comp.lang.idl
Subject: Re: Problems using (compound) widgets
Date: 21 Jan 1993 18:18:01 GMT
Organization: TU Berlin, Inst. f. Luft- und Raumfahrt, FRG
Distribution: world
Reply-To: peba1231@camillo.fb12.tu-berlin.de
NNTP-Posting-Host: camillo.fb12.tu-berlin.de

Sorry for posting my article to the wrong newsgroup.

Of course, comp.lang.idl-pvwave would be the correct group.

:-(((((
-- 
----------------------------------------------------------------------
Peter Bartsch        |   Tel.    +49 (0)30 314 23093
TU Berlin, Sekr. F2  |   FAX:    +49 (0)30 314 22866
Marchstr. 14         |
1000 Berlin 10       |   e-mail: peba1231@camillo.fb12.tu-berlin.de
----------------------------------------------------------------------
From: peba1231@camillo.fb12.tu-berlin.de (Peter Bartsch)
Newsgroups: comp.lang.idl
Subject: Problems using (compound) widgets
Date: 21 Jan 1993 16:55:05 GMT
Organization: TU Berlin, Inst. f. Luft- und Raumfahrt, FRG
Distribution: world
Reply-To: peba1231@camillo.fb12.tu-berlin.de
NNTP-Posting-Host: camillo.fb12.tu-berlin.de

I startet to write an IDL program as a front end to my grid generator.
At the moment, there are only a few buttons (cw_pdmenu), a drawing area
(widget_draw), event handling routines and a procedure, which reads an ascii 
file.

Nevertheless, I get strange error messages:

1) % Temporary variables are still checked out - cleaning up...

2) % Variable is undefined: <UNDEFINED>.

These messages are listed in the release notes for IDL2.4.  According to
the notes, the underlying problems are solved. (Something with STOP statements
in functions, but I don't use STOP at all)

I use IDL3.0 on an IBM RS6000/320, AIX3.2.1.beta.U402045.U412057.21.8.1992

Any hints are *very* appreciated,

Peter

-- 
----------------------------------------------------------------------
Peter Bartsch        |   Tel.    +49 (0)30 314 23093
TU Berlin, Sekr. F2  |   FAX:    +49 (0)30 314 22866
Marchstr. 14         |
1000 Berlin 10       |   e-mail: peba1231@camillo.fb12.tu-berlin.de
----------------------------------------------------------------------
From: oet@maz.sma.ch (Thomas Oettli)
Newsgroups: comp.lang.idl
Subject: archives of comp.lang.idl
Date: 21 Jan 1993 17:21:41 GMT
Organization: Swiss Meteorlogical Institute
Distribution: world
Reply-To: oet@maz.sma.ch
NNTP-Posting-Host: i30.sma.ch
Keywords: idl archives

Does anybody know about ftp-sites with archives of comp.lang.idl?

I couldn't find much with archie.

Thanks for any hint!

-- 
|Thomas Oettli                    Internet: Thomas.Oettli@sma.ch               |
|Swiss Meteorological Institute   CServe:   100015.3543@compuserve.com         |
|Kraehbuehlstr. 58                X.400 (PP) :                                 |
|8044 Zuerich                     S=oet/O=sma/PRMD=SWITCH/ADMD=ARCOM/C=CH/     |
|                                 FAX: +41 1 256 92 78, Phone: +41 1 256 93 16 |