HDTenEightyP/NetNews huggingface dataset:
From: brandes@gmd.de (Thomas Brandes)
Subject: Translation of CM Fortran Programs to Message Passing Programs
Apparently-To: comp-parallel@news.Germany.EU.Net
Summary: Announcing Adaptor Version 1.0
Keywords: Data Parallelism, CM Fortran
Organization: GMD, Sankt Augustin, Germany
Date: Thu, 15 Oct 1992 13:55:57 GMT

___________________________________________________________________

         THE  A D A P T O R  DATA PARALLEL PROGRAMMING TOOL
___________________________________________________________________

             -----------------------------------
               Announcing Adaptor Version 0.1

                       October 1992
             -----------------------------------


Adaptor (Automatic DAta Parallelism TranslatOR) is a tool that transforms
data parallel programs written in Fortran with array extensions, parallel
loops, and  layout directives  to parallel programs with explicit message
passing.

Adaptor is a big package that consists of:

 o the interactive source to source transformation tool XAdaptor
 o the distributed array library (DALIB)
 o documentation files in Postscript format,
 o example programs.

The source language of ADAPTOR can be defined shortly in the following way:

 o Fortran 77 with some restrictions,
 o with many array extensions of Fortran 90 (inclusive dynamic arrays
   and intrinsic functions for arrays),
 o with some features of Connection Machine Fortran (timing, random numbers),
 o with layout directives to specify the data distribution.

ADAPTOR is not a compiler but a source to source transformation that
generates Fortran 77 host and node programs with message passing.
The new generated source codes have to be compiled by the compiler of the
parallel machine. The following parallel machines are supported:

  * Alliant FX/2800
  * iPSC/860
  * Net of SUN 4 Workstations (based on PVM)
  * Net of IBM Risc Workstations (based on PVM)
  * Parsytec GCel
  * Meiko Concerto

The software packages, documentations files in PostScript, and a number of
example programs are available via "anonymous ftp" from:

    ftp.gmd.de    (129.26.8.90)
    in subdirectory    gmd/adaptor

Read the Installation Guide (iguide.ps) carefully to install the
package on your machine.

Please send remarks and bug reports to: brandes@gmdzi.gmd.de

--
===================================================================
Thomas Brandes                         e-mail: brandes@gmdzi.gmd.de
GMD, I1.HR, Schloss Birlinghoven, D-5205 St. Augustin, West Germany
===================================================================



Newsgroups: comp.parallel
From: "Benedito A. Cruz" <CHBENE%orion.cpqd.ansp.br@UICVM.UIC.EDU>
Subject: Looking for a simulation package.
Organization: Clemson University
Date: Fri, 9 Oct 92 14:28 C


     Does anybody know a discrete-event simulation package written in
C++ and how could I get it ?


Thanks

Bene
(chbene@cpqd.ansp.br)

Newsgroups: comp.parallel
From: andreas@vuse.vanderbilt.edu (Andreas Stathopoulos)
Subject: LAPACK reference
Apparently-To: comp-parallel@news.uu.net
Originator: andreas@atoms
Organization: Vanderbilt University School of Engineering, Nashville, TN, USA
Distribution: usa
Date: Fri, 16 Oct 1992 04:40:19 GMT


I am looking for the correct bibliographic reference to the LAPACK Users 
Guide published by SIAM some months ago. I would appreciate some
information either on the news or directly to

andreas$vuse.vanderbilt.edu

Thanks a lot
Andreas Stathopoulos

Newsgroups: comp.parallel
From: smitley@super.super.org (David L. Smitley)
Subject: Re: (News Release) MasPar Announces Second Generation System
Apparently-To: uunet!comp-parallel
Keywords: MasPar,MP-2
Organization: Supercomputing Research Center (Bowie, MD)
Date: Wed, 14 Oct 1992 16:55:58 GMT

>There are separate paths (read pins) for nearest-neighbor grid communication,
>global router communication, and memory.  You are on the right track in your
>conjectures about memory access.  There are two types of access, based on
>addressing modes.  
>
>  Globally specified (direct) address - 
>    All PEs access the same address in their respective memories.  Their
>    memories are interleaved in the shared fast page mode DRAM chips, so
>    this guarantees a big block transfer with no DRAM page changes.
>
>  Locally specified (indirect) address -
>    Each PE computes its own address into its memory.  This means each
>    PE waits for a DRAM page change, and the total access takes
>    about 2.5 times as long.  Considering the flexibility this offers,
>    that's impressive performance.
>

what exactly is the time for all 16K processors to do a single direct
access?  indirect access?  Is there still some form of local fast memory ala
MP-1?

David Smitley
Supercomputing Research Center


Newsgroups: comp.parallel
From: Andrew F Stratton <Andrew.Stratton@computing-maths.cardiff.ac.uk>
Subject: Re: (News Release) MasPar Announces Second Generation System
Apparently-To: hypercube@hubcap.clemson.edu
Keywords: MasPar,MP-2
Organization: University of Wales College of Cardiff
Date: Wed, 7 Oct 1992 10:00:11 +0100

In article <1992Oct6.181556.1267@hubcap.clemson.edu> sund@MasPar.COM (Brenda Sund) writes:
>     In addition, the MP-2 sets a new level of performance on 
>another important metric, integer operations per second.  The MP-2 
>delivers 68,000 MIPS (Million Instructions Per Second), a level 
>unmatched by any other massively parallel system, regardless of 
>price.

Well - someone has to say it - firstly I will assume that this is an
un-installed system (i.e.  this system is feasible and I'm sure will work
- but no one has yet built one).

If so - then the new nCUBE 2 model will actually acheive a potential
performance of greater than 68,000 MIPS.

OK- I see you asking how - well the nCUBE 2 model 10 ran at 7.5 MIPS
at 20 MHz and upto 8192 processors = 61,440 MIPS - Not enough :-)

However, the new nCUBE 2 model (available now) runs at 25 Mhz (everywhere)
and thus achieves 76,800 MIPS.

This means that MasPar can still win - if they install a system - since no
one seems to be able to afford a 8192 processor nCUBE 2 - nCUBE did have
an installed system running at a potential of 15,360 MIPS - while testing
boards.

I now look forward to lots of flames!

Andy Stratton.

Newsgroups: comp.parallel
From: Sridhar Sundaram <sridhar@cs.cornell.EDU>
Subject: FFT on the n x n mesh of processors
Apparently-To: comp-parallel@eddie.mit.edu
Organization: Cornell University, CS Dept., Ithaca, NY
Date: Fri, 9 Oct 1992 13:49:21 GMT

What algorithm is used to compute the Fourier Transform of a signal stored
one sample per processor on an n x n mesh of processors?
Could you please give me references also?

Thanks,
sridhar

-- 
sridhar@cs.cornell.edu   Off : 607-255-5578
                         Res : 607-277-2697
-------------------------------------------

Newsgroups: comp.parallel
From: phils@manasys.co.nz (Philip Shreeve)
Subject: Parallel Genetic Algorithm refs
Organization: Clemson University
Date: Thu, 8 Oct 92 20:12:03 NZD

About 2 years ago I spent a few months working on a optimization problem 
using PGA's. I couldn't find much in the way of references at the time,
however the principles were fairly clear. I followed suggestions in 
Goldberg's book and using a farming technique which worked well. I 
programmed in parallel C and Fortran on a 8 node transputer net. 
The results gave a significant improvment however it was difficult to
guarantee an optimal solution and the results seemed sensitive to small
changes in parameters (this could have been peculiar to my application).

Basically I recommend the technique for non-critical optimization - the
parallel programming was far more dificult than the GA's!

I'd be interested to hear about what you're doing in more detail. 

Phil Shreeve. 


Newsgroups: comp.parallel
From: tuck@MasPar.COM (Russ Tuck)
Subject: Re: (News Release) MasPar Announces Second Generation System
Apparently-To: uunet!comp-parallel
Keywords: MasPar,MP-2
Reply-To: tuck@MasPar.COM (Russ Tuck)
Organization: MasPar Computer Corporation, Sunnyvale, CA
Date: Fri, 9 Oct 1992 20:04:52 GMT

Brenda Sund <sund@MasPar.COM> writes:
>... The MP-2 delivers 68,000 MIPS (Million Instructions Per Second)...

Andrew F Stratton <Andrew.Stratton@computing-maths.cardiff.ac.uk> writes:
>Well - someone has to say it - firstly I will assume that this is an
>un-installed system (i.e.  this system is feasible and I'm sure will work
>- but no one has yet built one).

MasPar does not announce "un-installed" systems.  The full range of MP-2
models, from 1K to 16K PEs, had been built, tested extensively (including 
"torture" tests at high temperature, high and low voltage limits, etc.)
and were fully ready for customer shipment before the MP-2 was announced.  
Like the MP-1, we will sell and deliver many systems of each size.  

<Step onto soapbox>

MasPar doesn't announce $100,000,000+ paper (or vapor) systems 
that no one will ever buy.  

MasPar doesn't announce systems it can't deliver.  
(Our competitors announced systems a year ago that they still can't deliver.)

MasPar sells real systems to real people to solve real problems, NOW.

<Step off soapbox>
 
Thorsten von Eicken <tve@cs.Berkeley.EDU> writes:
>The piece I found most interesting about the machine is that they pack
>32 32-bit datapaths (sorry, I don't call these things RISC processors) onto
>a single chip. How do they get data in and out? Does it work out because they
>can use burst transfers efficiently because the 32 processirs are SIMD? What
>happens for indirect addressing modes (or are they not in the MasPar
>instruction set)?
...
>	Thorsten von Eicken - tve@cs.berkeley.edu

There are separate paths (read pins) for nearest-neighbor grid communication,
global router communication, and memory.  You are on the right track in your
conjectures about memory access.  There are two types of access, based on
addressing modes.  

  Globally specified (direct) address - 
    All PEs access the same address in their respective memories.  Their
    memories are interleaved in the shared fast page mode DRAM chips, so
    this guarantees a big block transfer with no DRAM page changes.

  Locally specified (indirect) address -
    Each PE computes its own address into its memory.  This means each
    PE waits for a DRAM page change, and the total access takes
    about 2.5 times as long.  Considering the flexibility this offers,
    that's impressive performance.

--
Russ Tuck, Systems Architect
tuck@maspar.com			(408) 736-3300       FAX: (408) 736-9560
MasPar Computer Corporation	749 N. Mary Ave, Sunnyvale, CA 94086 USA

Newsgroups: comp.parallel,sci.math.num-analysis,misc.jobs.offered
From: bahendr@cs.sandia.gov (Bruce Hendrickson)
Subject: Research Fellowship at Sandia Labs
Apparently-To: comp-parallel@ucbvax.berkeley.edu
Originator: bahendr@cs.sandia.gov
Organization: Sandia National Laboratories, Albuquerque, NM
Date: Wed, 7 Oct 92 02:06:31 GMT


              Applied Mathematical Sciences Research Fellowship

       Computational Sciences, Computer Sciences and Mathematics Center

                          Sandia National Laboratories


The Computational Sciences, Computer Sciences and Mathematics Center at
Sandia National Laboratories invites outstanding candidates to apply for
the 1993 AMS Research Fellowship.  The Fellowship is supported by the
Applied  Mathematical Sciences Research Program of the U.S. Department
of Energy.  AMS Fellowships at Sandia provide an exceptional opportunity
for innovative research in scientific computing on advanced architectures
and are intended to promote the transfer of technology from the laboratory
research environment to industry and academia through the advanced training
of new computational scientists.  Candidates must be U.S. citizens, have
recently earned a Ph.D. degree or the equivalent, and have a strong interest
in advanced computing research.

The Center maintains strong programs in analytical and computational
mathematics, discrete mathematics and algorithms, computational physics
and engineering, advanced computational approaches for parallel computers,
graphics, and architectures and languages.  Sandia provides a unique
parallel computing environment, including a 1024-processor nCUBE 2, a
64-processor Intel IPSC-860, a Connection Machine-2, and several large
Cray supercomputers.

The fellowship appointment is for a period of one year and may be renewed
for a second year.  It includes a highly competitive salary, moving
expenses, and a generous professional travel allowance.  Applicants
should send a resume, a statement of research goals, and three letters
of recommendation to Robert H. Banks, Division 7531-XX, Sandia National
Laboratories, P.O. Box 5800, Albuquerque, NM 87185.  The closing date for
applications is December 31, 1992, although applications will be considered
until the fellowship is awarded.  The position will commence during 1993.

For further information contact Richard C. Allen, Jr., at (505) 845-7825
or by e-mail, rcallen@cs.sandia.gov.

Newsgroups: comp.parallel
From: cnews@umr.edu (UMR Usenet News Post)
Subject: Looking for Ostrowski's paper ....
Apparently-To: uunet!comp-parallel@uunet.uu.net
Originator: jlu@reagan.cs.umr.edu
Organization: University of Missouri - Rolla
Date: Mon, 12 Oct 1992 22:33:14 GMT


Hi,

I'm looking for English version of Ostrowski's paper if it exists.
The title is Determinanten mit uberwiegender Hauptdiagonale und
die absolute Konvergenz von linearen Iterationsprozessen, published
by Comm. Math. Helv. in 1955.  Thanks!


  --Eric
-- 
***************************************---       Grad. student          ---*
* Obviousness is always the enemy of  *   \     Jui-Lin Lu (Eric)      /   *
* correctness.  -- Bertrand Russell   *   /      jlu@cs.umr.edu        \   *
***************************************---   Univ. of Missouri-Rolla    ---*


Newsgroups: comp.parallel,comp.arch
From: hw@robots.ox.ac.uk (Han Wang)
Subject: info about C40
Follup-To: comp.parallel
Organization: Clemson University
Date: Fri, 16 Oct 92 05:13:40 BST
X-Mailer: mail-news 2.0.3

Dear friends,

I am seeking informations about the new chip C40 from TI.
Does anyone out there has any experence in using it? any
information is welcome.

thanks in advance

Han

Newsgroups: comp.parallel
From: tve%crackle.CS.Berkeley.EDU@ucbvax.Berkeley.EDU (Thorsten von Eicken)
Subject: Re: (News Release) MasPar Announces Second Generation System
Keywords: MasPar,MP-2
Organization: University of California, Berkeley
Date: 8 Oct 1992 05:04:01 GMT

In article <1992Oct7.123312.13625@hubcap.clemson.edu> Andrew F Stratton <Andrew.Stratton@computing-maths.cardiff.ac.uk> writes:
>In article <1992Oct6.181556.1267@hubcap.clemson.edu> sund@MasPar.COM (Brenda Sund) writes:
>>     In addition, the MP-2 sets a new level of performance on 
>>another important metric, integer operations per second.  The MP-2 
>>delivers 68,000 MIPS (Million Instructions Per Second), a level 
>>unmatched by any other massively parallel system, regardless of 
>>price.
>
>Well - someone has to say it - firstly I will assume that this is an
>un-installed system (i.e.  this system is feasible and I'm sure will work
>- but no one has yet built one).
>
>If so - then the new nCUBE 2 model will actually acheive a potential
>performance of greater than 68,000 MIPS.
>
>OK- I see you asking how - well the nCUBE 2 model 10 ran at 7.5 MIPS
>at 20 MHz and upto 8192 processors = 61,440 MIPS - Not enough :-)

The nCUBE/2 isn't exactly new. New are variants on it of which I don't know
very much. Several 1K node nCUBE/2 have been running for a while. I suppose
MasPar means "native" MIPS and not "VAX" equiv MIPS and the nCUBE has single
cycle instructions, sooo 1K times 25MIPS = 25000MIPS. nCUBE had a 2K machine
running internally a few years ago: 51200MIPS.

>This means that MasPar can still win - if they install a system - since no
>one seems to be able to afford a 8192 processor nCUBE 2 - nCUBE did have
>an installed system running at a potential of 15,360 MIPS - while testing
>boards.

I think the "regardless of price" claim is overdoing it: TMC installed a 1K
node CM-5: 1024 33Mhz Sparcs -> 33700 MIPS. I'm sure they would be happy to
take order for a 2K machine. Crank up the clock to 34Mhz (can be done in
software), and there you are...

The piece I found most interesting about the machine is that they pack
32 32-bit datapaths (sorry, I don't call these things RISC processors) onto
a single chip. How do they get data in and out? Does it work out because they
can use burst transfers efficiently because the 32 processirs are SIMD? What
happens for indirect addressing modes (or are they not in the MasPar
instruction set)?

>I now look forward to lots of flames!
Ha!
>
>Andy Stratton.

	Thorsten von Eicken - tve@cs.berkeley.edu

Newsgroups: comp.parallel
From: krings@cse.unl.edu (Axel Krings)
Subject: References 4 real-time workloads
Apparently-To: comp-parallel@uunet.uu.net
Organization: University of Nebraska - Lincoln
Date: Mon, 12 Oct 1992 21:20:56 GMT


Hi Everybody,

I am looking for references to "real world" applications for real-time systems 
with hard deadlines. 

Basically I need the description of workloads, and any reference to
papers that describe control applications and give some notion about how
they partitioned their programs will help.

Areas using hard real time systems include robotics, aviation, engine control, 
nuclear reactor control, chemical mixing units, satellite control,...... 

I posted this request a while back, but got only 1 response with a reference 
and lots of responses with:
              "I am interested in the responses you get"

I will appreciate any responses and will be happy to share them. Just
send a note.

Thanks 
	Axel

---------------------------------------------------------------------------
The only real things I got so far are:
---------------------------------------------------------------------------
A paper by P.Shaffer (IEEE Control Systems June 1990)
"A Multiprocessor Implementation of Real-Time Control for a Turbojet Engine",
gives the computation graph for the control program of a supersonic turbofan
with afterburner is given. This is a 64 vertex graph, and for each the 64 
procedures the max duration is indicated.


"Synthesis of a Real-Time Message Processing System with Data-Driven Timing
Constraints," Al Mok , Prasanna Amerasinghe, Moyer Chen, Supoj Suthanthavibul,
Kamtorn Tantisirivat, Proceedings of the real-time Systems Symposium, San Jose, California, Dec. 1987, 133-143.

Newsgroups: comp.parallel
From: cpr4k@holmes.acc.Virginia.EDU (Christian P. Roberts)
Subject: Re: request info - PVM
Organization: Academic Computing Center - U.Va.
Date: Thu, 15 Oct 1992 14:57:44 GMT

In addition to sending email to netlib@ornl.gov, as indicated below,
those with Internet access can ftp to research.att.com, logging in as
anonymous with user i.d. as password.  Set the mode to binary before
getting the files.

#       Papers describing PVM
#       =====================
#       This directory contains a number of items relating to pvm and
#       HeNCE systems. To obtain a short (1 page) writeup on the projects
#       send mail to netlib@ornl.gov, in the mail message type:
#       send writeup.ps from pvm

#       To receive a copy of the
#       HeNCE index send email to netlib@ornl.gov and in the message
#       type: send index from hence.

file    pvm/pvm_experiences
#       pvm_experiences :  Describes graphical PVM interface, portable
#       parallel programming on PVM, and visualization using ParaGraph.
#       Presents results and experiences with two large, real-life,
#       scientific computing applications.

# NOTE: The user interface constructs have undergone numerous small
#       changes since the papers were written. To ensure that calling
#       conventions and argument lists are consistent with the
#       software, please do not use the descriptions in the papers
#       while developing PVM applications. Use the users guide instead.

file    pvm/pvm_shar
#       pvm_shar : This is the source code for pvm.
#       Version 2.4.1/u2.4.1.
#       Last updated 5/31/92 (664716 bytes).

file    pvm/pvm_tar
#       pvm_tar : This is the source code for pvm.(tar; compress; uuencode)
#       Version 2.4.1/u2.4.1.
#       Last updated 5/31/92 (319383 bytes).

file    pvm/patch1_shar
#       This is a shar file of patches to version 2.4.1.  Highly recommended.
#       Last updated 8/13/92 (122879 bytes).

file    pvm/userguide_shar
#       userguide_shar : This is the users' guide for pvm.
#       Last updated 7/29/91 (261274 bytes).

file    pvm/refcard
#       This is a postscript file containing a quick reference card
#       which describes the C and Fortran interface to PVM.
#       Last updated 5/24/92 (79033 bytes).

-- 

Chris Roberts                     Academic Computing Center
cpr4k@virginia.edu                University of Virginia           
(804) 982-4693                    Charlottesville, Virginia 22903

Newsgroups: comp.parallel
From: Tim Gove <gove@asel.udel.edu>
Subject: request info - PVM
Organization: Clemson University
Date: Wed, 14 Oct 92 15:46:59 EDT

I am in search of any information I can get my hands on about PVM.

I have two projects involving it...a broad liturature-survey type
research paper (for which I have yet to find any literature other 
than its own on-line documentation), and an implementation project 
in which I am probably going to implement PVM using C-Linda.  

Therefore, I am looking for journal articles in particular, but any 
other citations, experiences, thoughts, etc., would be appreciated.

Please send to gove@cis.udel.edu
Thanx in advance...

Tim Gove
University of Delaware				gove@cis.udel.edu
Applied Science and Engineering Laboratories	gove@asel.udel.edu
Alfred I. duPont Institute

Newsgroups: comp.parallel
From: ian@MasPar.COM (Ian L. Kaplan)
Subject: Re: (News Release) MasPar Announces Second Generation System
Apparently-To: uunet!comp-parallel
Keywords: MasPar,MP-2
Reply-To: ian@MasPar.COM (Ian L. Kaplan)
Organization: MasPar Computer Corporation, Sunnyvale, CA
Date: Thu, 8 Oct 1992 19:25:15 GMT

In article  Andrew F Stratton
>In article  sund@MasPar.COM (Brenda Sund) writes:
>> The MP-2 
>>delivers 68,000 MIPS (Million Instructions Per Second), a level 
>>unmatched by any other massively parallel system, regardless of 
>>price.
>
>Well - someone has to say it - firstly I will assume that this is an
>un-installed system (i.e.  this system is feasible and I'm sure will work
>- but no one has yet built one).
>

  MasPar has certainly built a 16K processor MP-2 system in-house.
And it is not some huge monster machine.  It is just a MasPar Computer
cabinet with 16 MP-2 processor boards in it (i.e., 1K 32-bit
processors per board).  And it should be noted that this is not like
some parallel processors, where the maximum configuration costs more
than most people are likely to pay (e.g., $500M for one machine's
maximum configuration).  I believe that a 16K processor MP-2 is around
$1.6M.  So buy two and use one to play video games :-).

			Ian Kaplan
			ian@maspar.com

Newsgroups: comp.parallel