From: keithl@klic.rain.com (Keith Lofstrom)
Subject: Re: Fault Simulation of differential logic
Organization: Keith Lofstrom Integrated Circuits
Date: Fri, 22 Jan 1993 07:06:59 GMT

In article <1993Jan19.155846.11093@bmw.mayo.edu> buchs@mayo.edu (Kevin Buchs) writes:
> We are trying to get an idea of how effective our test vectors are
> for a differential (CML) logic design.  In considering this, however,
> it seems like differential logic is inherently untestable.  You have
> two signals and unless they are of opposite logic levels, the outputs
> are undefined.  Thus, a stuck-at fault on one would yield a unknown
> output and only a possible detect.  Since separate drive transistors
> are used for each signal, it is a lot less likely that both signals
> in the differential pair are faulty.  Can anyone shed any further
> light on this topic or show me my faults?
>
> Kevin Buchs  (buchs@mayo.edu)

First off, differential logic is poorly represented by the currently
available simulators.   The key concept is that:

*** for differential logic, two wires represent one logic signal !!! ***

That is, your logic signal is the difference between the two values.  Indeed,
all logic is differential - however, we usually are sloppy and assign one
of the logic inputs to a supply or a bias generator or - ghod help us -
a process parameter like VT or VBE.   Ewww.

Thus, what you need is an as-yet-unavailable preprocessor that goes through
your netlist and changes the pair of wires into one logic signal, while
checking loading ratios and so forth to make sure that the logic approximation
is a good one.  There are cases where it isn't - for example a differential
emitter follower off an ECL gate can generate some pretty crappy signals
if the current source pulldowns are too weak:

  +++++++++++++    *****************************************
               +++*+++++
                 *      +++++++++
                *                +++++++++
               *                          ++++++++
  *************                                   ++++++++++

... but this is the sort of thing a preprocessor should be able to find.
As a fault, it would look like excessive delay, which is why differential
logic must always be tested at speed  (meaning you have to design in some
circuitry to help your pathetically slow tester).  Performance is costly.

For multilevel current steering logic, this same preprocessor should help 
determine whether each line is biased to the proper level, the levels are
stacked properly, and the bias generators are adequate.   Since you can
swap inputs, the preprocessor must be able to incorporate zero-delay
input inversions - or select between a unit delay buffer and a unit
delay inverter at each input, if your logic simulator is too lame to
selectively invert inputs to gates and cells.

Is there a graduate student out there looking for a thesis topic?

Okay, so what you get to do is to predesign your naming conventions,
and build a crufty little preprocessor in AWK or PERL that uses and
checks them.  With that, you can boil your netlist down to logic.  As
logic, all the normal rules of fault modelling apply.  The only thing
missing is the "input driven so high that the transistor saturates and
squirts the tail current out the base" fault, but this is usually 
adequately modeled by an output-stuck-at-one for the following output.

Good luck.  ECL/CML design isn't for wimps!

Keith
-- 
Keith Lofstrom         keithl@klic.rain.com       Voice (503)-520-1993
KLIC --- Keith Lofstrom Integrated Circuits --- "Your Ideas in Silicon"
Design Contracting in Bipolar and CMOS - Analog, Digital, and Power ICs