From: shahm@vms.ucc.okstate.edu
Subject: MSEE VLSI/COMPUTER ARCHITECTURE
Organization: Oklahoma State University Computer Center
Date: Tue, 21 Jul 1992 21:23:01 GMT

                                   MANISH SHAH
				38, S.UNIV. PL.,#8
			       STILLWATER, OK-74075
	   		     PHONE NO.: (405)744-3240
                          e-mail: shahm@vms.ucc.okstate.edu

OBJECTIVE:

   To pursue a career in the field of applied Electrical engg. with emphasis
   on  VLSI Design and Computer Architecture. 


EDUCATION:

   M.S. (July 1992) ELECTRICAL ENGG. 
   OKLAHOMA STATE UNIVERSITY.
  
   GPA: 4.0/4.0


   BACHELOR OF ENGG. in Electronics and Communication Engg. 
   M.S. University of Baroda, India.
   
   GPA/CLASS: I class with Distinction (81%)
   RANK: SECOND


EXPERIENCE:

   TEACHING ASSISTANT (Since Aug 1990)
   Department of Electrical and Computer Engg., 
   Oklahoma State University.

   * Lab Instructor for the  course on Computer Based System Development.
     Teaching 'C' programming in X window environment and interfacing of
     IBM PC with external hardware. 

   PRODUCT ENGINEER (06/89 TO 05/90)
   UNITED NETWORKS PVT. LTD., INDIA.
   
   * Design, Testing and Installation of TOKEN RING FIBER OPTIC LOCAL
     AREA NETWORKS.
   * Design and Prototype Verification of 4mb/sec Token Ring Multistation
     Access Unit using active circuits.
   * Design of Line Drivers.


PROJECTS:

   * Design, Simulation and Layout of a REDUCED INSTRUCTION SET PROCESSOR
     using LAGER IV CAD Tools.
   * Design, Simulation and Layout of a CHANNEL ROUTING NETWORK in a 
     2.0 micron process and Bulk CMOS technology using MAGIC, SPICE and IRSIM. 
   * Design, Fabrication and Testing of 32-Word by 4-Bit Register File.   
   * Design of Analog Data Acquisation System using Intel's 8031 MICROCONTROLLER
   * Velocity and Position Control of Stepper Motor using IBM PC.


THESIS TOPIC:

   * VLSI Design of a Special Purpose CMOS TWIN REGISTER FILE for reducing
     the effects of Conditional Branches in Pipelined Architecture. 

     The design consists of two three-port register files which can be
     independently accessed by two independent processors. Each of the 
     two register files also has the capability of being copied into the 
     other, in a single clock phase. A 32-word by 16-bit twin register file
     was designed using 2 micron process and has a total of 12,158 transistors.
     The read access time of the twin register file is 11ns.


COURSEWORK:

   * Design and Testing of Electronic circuits * Computer Hardware 
   * Microprocessors  * Fiber Optics  * Digital Computer Design
   * Digital Data Acquisation and Control  * Advanced Computer Architecture
   * VLSI Digital System Design   * Advanced VLSI System Design 
   * CMOS Analog Circuit Design
 

COMPUTER SKILLS:

   SYSTEMS   : MS DOS, UNIX, VMS
   LANGUAGES : C, FORTRAN, Pascal, 8086/88 Assembly Language
   SOFTWARE  : MAGIC, LAGER, PSPICE, IRSIM, ORCAD.
   Experience of working on RS/6000, SUN SPARCstation, VAX 6320, IBM PC/XT/AT,
               and Macintosh.


HONORS AND ACTIVITIES:

   * Recipient of National Merit Scholarship from the Govt. of India (1982).
   * Member IEEE.
   * Member Phi Kappa Phi and Tau Beta Pi.


REFERENCES:

   Dr.James Baker (Head and Prof.) Dept. of Electrical Engg.
      Oklahoma State University.  (405) 744-5151.

   Dr.Louis Johnson (Assoc. Prof.) Dept. of Electrical Engg.
      Oklahoma State University.  (405) 744-5169.