From: Dan Johnson <danj@aue.com>
Subject: Magic/dlmV3.0 Announcement
X-Useragent: Nuntius v1.1
Organization: Advanced Microelectronics
Date: Wed, 6 Jan 1993 03:55:37 GMT
X-Posted-From: slip1.aue.com
NNTP-Posting-Host: sol.ctr.columbia.edu

********************************************************************************
MAGIC/dlmV3.0 Advisory - CIF related BUG reports                     12/21/92
********************************************************************************

AuE has developed a new version of Magic that resolves several problems found in
previous MAGIC releases. Most of the problems involve CIF processing and the MAGIC
technology files. The bug list below summarizes some of the problems that we have
encountered. To fix these problems we have implemented changes in the MAGIC source 
code and various Magic technology files. If you are using the AuE I/O pad library
please make sure that you are using the AuE technology file and the AuE version of 
Magic to process your layout databases. If you are using previous versions of MAGIC
and the MOSIS technology files you may encounter design rule violations that are
produced when databases are processed through multiple CIF read/write conversions.
You can obtain the new version of Magic and the dlmV3.0 cell family via E-mail.
Send your cell family request to cells@aue.com and your Magic request to 
magic@aue.com.

[1] PROBLEM - If the lambda=0.5(gen) CIF ostyle is used to generate CIF for 
    the AuE IO cells, the M1 to M2 vias will not be generated from the "pad" log
    and the bond pads will be floating. It does not matter that MOSIS will place 
    metal3 and via2 on the layouts before fabrication, the metal2 will still not 
    be connected to metal1!

    DETAILS - AuE used the MAGIC log "pad" as the bond pad in the 0.8um IO library. 
    Normally this log generates metal2, via, metal1, glass cut, and XP layers during 
    CIF out. The CIF output style in the initial release of 0.8u MOSIS technology 
    file DID NOT do this. The log "pad" only generates metal2 and metal1.  

    SOLUTION - AuE has obtained the latest technology file for the 0.8u design rules
    and will E-mail an updated MAGIC technology file to all registered users of the 
    cell family. DO NOT FABRICATE 0.8u DESIGNS USING THE CURRENT TECH FILE!....

[2] Problem - Via related design rule violations are produced in layouts that
    are processed through multiple CIF read/write conversions. 

    Solution - The problem is caused by the CIF reader when it attempts to merge 
    vias into via logs. The merge is unnecessary except for aesthetic reasons. 
    In the AuE technology file the merge step has been removed. Via logs are now 
    always seen as 4x4 rectangles on a metal1 and metal2 plane. The CIF reader 
    can process these planes without affecting the via shapes and locations.

[3] Problem - The AuE I/O pads contain ESD structures that can produce design rule
    errors and rail to rail shorts through the diffusion and well layers. The design 
    rule problems occur when layouts are processed through multiple CIF write/read 
    conversions. The MOSIS I/O pads also experience similiar problems. The errors 
    are produced by diffusion and well bloating that takes place during the CIF 
    conversion process.

    Solution - AuE has defined new logs called "ndop" and "pdop" that are used to
    implement the ESD structures. Using these logs, well edges can straddle
    diffusion junctions to create structures that prevent diffusion junction 
    spiking during an ESD event. The "ndop" and "pdop" logs generate active and 
    select masks but not well regions. When reading CIF back in, boolean operations 
    are performed on the n-select and p-select masks to generate the nnd, ndiff, 
    ppd, and pdiff logs. The "ndop" and "pdop" regions are added to the database 
    automatically. 

 GENERAL NOTE: MOSIS has recently updated several technology files. If you are 
               using the MOSIS service you should make sure that you obtain the 
               updated documentation.


 If you have any additional questions please contact Advanced Microelectronics via 
 E-mail using cells@aue.com. For those without E-mail access information requests 
 can be directed to:

                             Advanced Microelectronics
                             P.O. Box 55729
                             Jackson. MS 39296-5729
                             (601) 932-7620
Newsgroups: comp.lsi.cad,sci.electronics