HDTenEightyP/NetNews huggingface dataset:
From: cotrozzi@ghost.dsi.unimi.it (Massimo Cotrozzi)
Subject: Re: IBM password
Organization: Computer Science Dep. - Milan University
Date: Wed, 30 Sep 1992 16:50:38 GMT

jason@coombs.anu.edu.au (jason..) writes:

>cotrozzi@ghost.dsi.unimi.it (Massimo Cotrozzi) writes:

>>bill@chaos.cs.umn.edu ( Hari Seldon     psychohistorian ) writes:

>>>In <BvAv1r.M8C@csugrad.cs.vt.edu> rlee@csugrad.cs.vt.edu (Richard Lee) writes:

>>>>Does anyone know of a program that puts a password program in the config.sys and
>>>>the boot sector of an IBM PC?  I know of many that it's in the autoexec.bat
>>>>but that is almost laughable.

>>>drdos 6 can provide what you want

>>If you don't mind for people booting your PC with MSDOS 5.0,
>>editing the disk and changing the line in config.sys that says
>>DEVICE=C:\DRDOS\LOGIN.EXE to something like
>>REM CE=C:\DRDOS\LOGIN.EXE
>>and then boot your computer again.
>>You could put a BIOS password but then if someone takes the battery out you're done
>>again.
>>There's no way to protect a PC from use by unauthorized users ..
>>( I am not talking just for DOS, for UNIX too . Think about it !!!)
>>>bill pociengel
>>>--
>>>llbi locgeenpi " i'm a little confused right now"

>I believe you can encrypt the contents of your harddrive when you use superstor
>which is supplied with DR-DOS 6. This is as well as encrypting certain 
>directories (logical drives?) to prevent access to them. Hence, you boot
>of a bootable dos disk .. grab your copy of norton's and proceed to examine
>junk (hopefully) .. There are probably ways around it, but it seems as secure
>as you could hope to get for whatever the cost of dr-dos is ..
Yes but when you SSTOR your hard disk you have a little part of it non-compressed
because the dos will not read the compressed " partition " . So you have a 
DCONFIG.SYS which chains the original config.sys where is placed the line
DEVICE=C:\DRDOS\LOGIN.EXE. So if you just delete the chain line ....

	Massimo
-- 
--------------------------------------------------------------------------
!  /|/|  /| \ /  ! Massimo Cotrozzi  Computer Science Dept. Milan Italy  !
! /   | /-|  \   ! cotrozzi@ghost.dsi.unimi.it      			 !
!/    |/  | / \  ! massimo@cdc835.cdc.polimi.it	                         !
Newsgroups: comp.security.misc
From: janc@p.tvt.se (Jan Carlsson)
Subject: DES chips avalible in Europe
Organization: Swedish Telecom
Date:  1 Oct 92 12:32:29 GMT


I'm looking for information about hardware implementations of
DES avalible in Europe. Please answer by E-mail to the address
below and I'll post a summary.

Thanks ! 


------------------------------------------------------------------------------
      Jan Carlsson                 fax:     nat:    08-7075521
      Telia Research                        int: +46 8 7075521
      Systems Research             phone:   nat:    08-7075480
      Information Security,Sfi              int: +46 8 7075480
      S-136 80 HANINGE             e-mail:  janc@telerand.p.tvt.se
      SWEDEN
------------------------------------------------------------------------------
From: dseal@armltd.co.uk (David Seal)
Newsgroups: comp.lsi
Subject: Re: Requested: info on signed digit compare
Date: 28 Sep 92 09:37:35 GMT
Distribution: comp
Organization: A.R.M. Ltd, Swaffham Bulbeck, Cambs, UK

In article <1992Sep25.110131.17771@donau.et.tudelft.nl>
maarten@dutecaj.et.tudelft.nl (M. Hofman) writes:

>I'm doing a research on the usability of signed digit notation (and other
>redundant binary notations) in general purpose microprocessors. After checking
>the add, multiply, shift, divide and square root I finally came to the big
>question of the compare. Needed is a very fast compare (on less than zero) 
>algorithm, that can be implemented in VLSI and uses signed digit notation (in 
>specific: (0,0) for 0, (0,1) for 1 and (1,0) for -1, but I'm also interested in 
>compares using other ways of coding the redundancy). If anyone knows about papers 
>on this subject, or has developed something she/he is willing to share, please 
>mail me.
>
>I have already developed a simple method myself:
>
>In parallel check:
>  1) If the MSB is -1
>  2) If the MSB is 0 and the MSB-1 is -1
>  3) If the MSB is 0 and the MSB-1 is 0 and the MSB-2 is -1
>  4) Et cetera
>If one of the above yields true, the number is less than zero.
>
>But I don't know if this algorithm can be easily made in VLSI.

Doing this fast should be possible using techniques similar to those used in
a carry-propagate adder. I.e. at the bit level, define generate and
propagate signals for each digit position i (with the LSB being position 0)
by:

  G[i,0] = (Digit i is -1)
  P[i,0] = (Digit i is 0)

Then define similar signals on say 4-digit blocks by:

  G[4*i,1] = G[4*i+3,0]
             OR (G[4*i+2,0] AND P[4*i+3,0])
             OR (G[4*i+1,0] AND P[4*i+2,0] AND P[4*i+3,0])
             OR (G[4*i,0] AND P[4*i+1,0] AND P[4*i+2,0] AND P[4*i+3,0])

  P[4*i,1] = P[4*i,0] AND P[4*i+1,0] AND P[4*i+2,0] AND P[4*i+3,0]

This can then be repeated for 16-digit blocks, etc.

Other fast adder techniques (e.g. carry-select adders, Ling adders, etc.)
may generalise similarly.

David Seal
dseal@armltd.co.uk

All opinions are mine only...
Newsgroups: comp.lsi
From: omtzigt-theo@CS.YALE.EDU (Erwinus Theodorus Leonardus Omtzigt (Theo))
Subject: Fast implementations for level index number systems
Followup-To:  tomtzigt@pcocd2.intel.com
Keywords:     CORDIC, level-index, chip design
Organization: Intel Corporation, MPG Architecture and Planning
Date: Fri, 2 Oct 1992 17:24:23 GMT

To prospective chip designers

Parallel computation allows us to calculate more in a given time than
is possible with a single processor. Due to the large number of
calculations, the number system used is pivotal in the obtainable
accuracy of the result. The level-index and symmetric level index
number representations are two number systems that are proposed
to replace the floating point number system for calculations involving
large numbers as well as large numbers of operations. What is still
lacking in comparison with the floating point system is fast
implementations, which, most likely, will be based on CORDIC
transformations. We are looking for competitive designs for either
the level index or the symmetric level index number system.
For further information, please contact


Dr. Theodore Omtzigt
Intel Corporation, Inc.
Mail stop: FM2-08
email: tomtzigt@pcocd2.intel.com
phone: (916) 356 - 3696


Newsgroups: comp.lsi.cad
From: jds@media.mit.edu (John D. Sutter)
Subject: Octtools Questions
Organization: MIT Media Laboratory
Date: Sun, 4 Oct 1992 22:46:53 GMT

 [ Posted for a friend - jds ]

We are running Oct 5.0:

1. Is there any way to do ROM in Oct, or any PD tools for doing ROM
in SCMOS??

2. Does mizer work at all?  It doesn't work on the example in the Oct
docs.

3. Same question for octpla.  It fails in octopus (dumps core).

4. Same question for gem.  It fails in electra (error in parsing network).

5. Is there an address at Berkeley to send questions like this?


Gary Lipton
Dept. of EE
Lafayette College

glipton@lafcol.lafayette.edu


-- 
John Sutter        MIT Media Laboratory        Spatial Imaging Group 
(w)  20 Amest St E15-422, Cambridge, MA 02139, USA +1 (617) 253-0375
(h)  yet to be determined
INTERNET:   jds@media-lab.media.mit.edu                    NSS 29355
From: hossain@ee.rochester.edu (Razak Hossain)
Newsgroups: comp.lsi.cad
Subject: octpla
Summary: Help with octpla and magic
Date: 29 Sep 92 20:57:21 GMT
Distribution: usa
Organization: Univ of Rochester, College of Engineering and Applied Science

I am trying to use octtools 3.5 to generate a PLA. I am using the program
"octpla" to generate the PLA and the program "octtocif" to convert the
PLA to a format where "magic" can be used to see it. In "octpla" I have
tried using a number of scripts including to-mosis-pwell, to_magic_nwell_2u
and msu2pwell/nwell/twinwell. Unfortunately the PLA generated by all of 
the scripts are filled with design rule errors. Generally choosing an nwell
script produces errors in the pdiff while choosing a pwell process results
in ndiff problems. The magic version we are using is magic 6.1

I am wondering if anyone has used octpla to generate PLA and edited them
on magic ? If so I would appreciate some advice on the best way to go 
about generating the PLA, in terms of possible scripts and corrections
that may be used.

I would appreciate it if any replies could also be mailed to me.

Regards,
Razak (hossain@ee.rochester.edu)
 
Newsgroups: comp.lsi.cad,comp.lang.vhdl
From: rmorse@rmsun.uucp (Robert Morse)
Subject: Schematic Capture to Layout Packages Looking for Sun
Organization: NONE
X-Newsreader: TIN version 1.1 PL6
Date: Wed, 30 Sep 1992 02:49:57 GMT

Hi,
	My company is currently in the market for a set of program that
    will allow use to go from schematic capture (Including simulation) to
    the board layout.  The schematic capture package should support 
    VHDL & EDIF, plus be able to do mixed mode simulation.  I know I am
    asking a lot but that is our wish list.  We are currently evaluatin
    ViewWorks (ViewLogic) and Pads, but viewworks have some minor problems,
    and Pads (Well I won't talk about that, I haven't yet been able to
    get past the license server). 

	So we are currently looking for new packages. Does any one have
    comments on ?Something Vision?, pcad for SUN, Mentor Graphics.  We 
    are getting close to a deadline on doing a project and want to move
    fast, (I will accept literature from companies or call).

	So to some it up, please if you have any comments on CAE packages
    please email me your thoughts.  

Thanks
	Robert Morse
	Hardware Engineer.
	Medar Inc.			313-477-3900 (Work)
					313-477-8897 (FAX)

	rmorse@medar.com

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+    Robert Morse                      +          Live long and happy         +
+    ..!uunet!medar!rmsun!rmorse       +            rmorse@rmsun              +
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+    Robert Morse                      +          Live long and happy         +
+    ..!uunet!medar!rmsun!rmorse       +            rmorse@rmsun              +
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
From: paul@eros.Berkeley.EDU (Paul Cohen)
Newsgroups: comp.lsi.cad
Subject: Re: octpla problems(OCTTOOLS 5.1)
Date: 27 Sep 1992 21:47:08 GMT
Organization: University of California at Berkeley
Distribution: inet
NNTP-Posting-Host: eros.berkeley.edu

In article <1992Sep25.175906.6306@zip.eecs.umich.edu> cyc@quip.eecs.umich.edu (Yi-Chieh Chang) writes:
>
>Can any one kindly send me a public node where I could get the copy
>of OCTTOOLS 5.1 ? Thank you very much.
>

Octtools-5.1 is not available via public FTP. For information on obtaining
the tools, you should contact the Industrial Liason Program Office.
You can send e-mail to ilpsoft@janus.berkeley.edu, or call them at
(510) 643-6687. The U.S mail address is:

	    Industrial Liason Program Software Distribution
            Department of Electrical Engineering and Computer Sciences
	    457 Cory Hall
            University of California, Berkeley
	    Berkeley, CA, 94720


-- 
Paul B. Cohen				| paul@aha.com
Advanced Hardware Architectures, Inc.	| paul@ic.berkeley.edu
P.O Box 9669				| (208) 883-8000 (v)
Moscow, ID 83843			| (208) 883-8001 (f)
From: homi@ece.wvu.wvnet.edu
Newsgroups: comp.lsi.cad
Subject: Graduate Research Assistantship Available Spring 1993
Keywords: Graduate Research
Date: 28 Sep 92 15:52:30 GMT
Organization: Microelectronic Systems Research Center


GRADUATE RESEARCH ASSISTANTSHIP AVAILABLE SPRING 1993
                September 25, 1992

                MICROELECTRONIC SYSTEMS RESEARCH CENTER 
                       WEST VIRGINIA UNIVERSITY
                        COLLEGE OF ENGINEERING

The recently established Microelectronic Systems Research Center
explores the application of advanced and emerging technologies in
high performance microelectronic systems, with an emphasis on new
system level technologies such as multi-chip modules, 3D systems,
intelligent systems, optical interconnections, and  cryoelectronics.
Current research projects are funded by DARPA and NSF and include 
collaborations with AT&T Bell Laboratories and with research 
consortia.

A graduate research assistantship in the area of high performance 
microelectronic systems will be filled at the begining of the 
spring semester 1993.  This is a highly competitive position, with 
applicants solicited both from WVU and from other universities. 
It is expected that this position will be filled by a PhD candidate,
though exceptional Masters level candidates will be considered.  
The following summarizes the research area.

Intelligent Networks for Highly Parallel, High Performance 
Computing:  Silicon Wafer Area Networks (SWANS)  
This program seeks to design an intelligent mesh-connected network 
of switches with dynamic adaptation to traffic in order to provide 
automatic load balancing through activity potentials evolving at a rate 
consistent with the size of the network and local state-machine 
decisions.  The overall network is to be implemented on a silicon 
wafer.  Project includes analysis of percolation and chaotic 
effects along with VLSI design and area/speed tradeoffs.  It is 
expected that the student will develop network simulations on a 
SUN workstation.  VLSI design will be based either on OctTools or 
on VALID tools.

Salary for this position is at a base of $2,000 per month,  at 
100% time during the summer and 50% time during the academic year.

For further information, contact either Dr. Stuart Tewksbury or 
Dr. Larry Hornak at the following address.     

        Microelectronic Systems Research Center 
        Engineering Sciences Building # 827     
        Evansdale Campus        
        West Virginia University        
        Morgantown, WV 26506-6101

        Tel: (304)293-6371        
        Fax: (304)293-5024        
        e-mail:  ee_skt@a.coe.wvu.wvnet.edu
        e-mail:  ee_hornak@a.coe.wvu.wvnet.edu

West Virginia University is an equal opportunity employer.
Newsgroups: comp.lsi.cad
From: garyk@cbnewsk.cb.att.com (gerhard.karnik)
Subject: Printing MAGIC files
Organization: AT&T
Date: Wed, 30 Sep 1992 15:24:23 GMT
Keywords: magic

I am a new user of MAGIC and am having trouble with making plots of
my files.  I can print using postscript, but I need to print to either a
HP LaserJet or PaintJet printer.  Does anyone know of a way to do this
either from within the MAGIC package or some external utility?

Thanks in advance, Gary.

Xref: sparky comp.lsi.cad:995 comp.lsi:620 comp.lsi.testing:239 comp.lang.vhdl:468
From: luciano@athos.Berkeley.EDU (Luciano Lavagno)
Subject: Re: ROM in OCT; mizer
Reply-To: luciano@athos.Berkeley.EDU (Luciano Lavagno)
Organization: UC Berkeley IC CAD Group
Date: Mon, 5 Oct 1992 07:50:56 GMT

In article <1992Oct4.180822.8467@lehi3b15.CSEE.Lehigh.EDU>,
glipton@lafcol.lafayette.edu (Gary Lipton) writes:
>1. Is there any way to do ROM in OCT, or any PD tools for doing ROM
>in SCMOS??
>
>2. Does mizer work at all?  It doesn't work on the example in the OCT
>docs.
>
>3. Is there an address at Berkeley to send questions like this?

octtools@ic.berkeley.edu should be the most appropriate address.
Luciano
P.s. what version of octtools are you using ? 
-- 
Luciano Lavagno            luciano@ic.Berkeley.EDU            +1-510-642-5012
Dept. of EECS, 207-69 Cory Hall, Univ. of California, Berkeley, CA 94720, USA
Newsgroups: comp.lsi.cad
From: engp1261@nuscc.nus.sg (Teng-Kiat Lee)
Subject: Capacitance values in Magic
Reply-To: engp1261@nuscc.nus.sg
Organization: Dept. of EE, National Univ. of Singapore
Date: Wed, 30 Sep 1992 03:02:10 GMT

I have a user of Magic here who wants to implement a capacitor for
his analog design. The question is how does magic calculate the
capacitance between two metal layers. A look in the maintainer's
guide tells me what the capacitances (area, perimeter) of any layer
to substrate is, but not in between layers. Anyone has any clue
on how to get this information?

Regards,
----------------
Teng-Kiat Lee                        VLSI CAD & Design Lab
Internet: engp1261@nuscc.nus.sg      Microelectronics Div.
Bitnet:   eleleetk@nusvm.bitnet or   Dept. of Electrical Engineering
          ltk@nuseev.bitnet          National University of Singapore
Voice:    (065)-772-6319             10 Kent Ridge Crescent
          (065)-467-1518             Singapore 0511
----------------------------------------------------------------------
From: pi@sharon.isi.edu (Jen-I Pi)
Newsgroups: comp.lsi.cad
Subject: Re: Capacitance values in Magic
Date: 2 Oct 92 21:16:31 GMT
Organization: MOSIS Project, USC/ISI

In article <1992Sep30.030210.18848@nuscc.nus.sg>, engp1261@nuscc.nus.sg (Teng-Kiat Lee) writes:
|> I have a user of Magic here who wants to implement a capacitor for
|> his analog design. The question is how does magic calculate the
|> capacitance between two metal layers. A look in the maintainer's
|> guide tells me what the capacitances (area, perimeter) of any layer
|> to substrate is, but not in between layers. Anyone has any clue
|> on how to get this information?

Isn't there an "overlap" command in the extract section of Magic's
technology file do this for you?

Best Regards,

Jen-I pi@isi.edu :-)
(310)8221511 x640
From: paul@eros.Berkeley.EDU (Paul Cohen)
Newsgroups: comp.lsi.cad
Subject: Re: octpla
Date: 30 Sep 92 06:22:40 GMT
Distribution: usa
Organization: University of California at Berkeley
NNTP-Posting-Host: eros.berkeley.edu

In article <1992Sep29.205721.5851@ee.rochester.edu> hossain@ee.rochester.edu (Razak Hossain) writes:
>I am trying to use octtools 3.5 to generate a PLA. I am using the program

Octtools 3.5 has been obsolete for a number of years now. The current
release is Octtools-5.1. There is no particular hope of getting octpla
to work in Octtools 3.5. There have been a number of changes, and due
to the changes in the overall structure of the tools, the changes are
not backwards compatible to release 3.5.

>"octpla" to generate the PLA and the program "octtocif" to convert the
>PLA to a format where "magic" can be used to see it. In "octpla" I have
>tried using a number of scripts including to-mosis-pwell, to_magic_nwell_2u
>and msu2pwell/nwell/twinwell. Unfortunately the PLA generated by all of 
>the scripts are filled with design rule errors. Generally choosing an nwell
>script produces errors in the pdiff while choosing a pwell process results
>in ndiff problems. The magic version we are using is magic 6.1

The msu2nwell, pwell, and twinwell scripts have been used for some
time to generate working chips, but they will not correct the problems
associated with octpla.  In release 3.5, there were some problems with
the standard cells, which the octtocif scripts could fix. The standard
cell problems have been fixed (quite some time ago), and he scripts
have been updated to reflect this.

>I am wondering if anyone has used octpla to generate PLA and edited them
>on magic ? If so I would appreciate some advice on the best way to go 
>about generating the PLA, in terms of possible scripts and corrections
>that may be used.

I've fabricated PLAs created with octpla, and they have worked.
However, there are so many problems associated with the version of
octpla in release 3.5 that the only advice I can offer is to get the
most current release. 

-- 
Paul B. Cohen				| paul@aha.com
Advanced Hardware Architectures, Inc.	| paul@ic.berkeley.edu
P.O Box 9669				| (208) 883-8000 (v)
Moscow, ID 83843			| (208) 883-8001 (f)
Newsgroups: comp.lsi.cad,comp.cad.cadence,comp.sys.mentor,comp.specification
From: dataram@tigger.jvnc.net (Dataram Corp. PO Box 7528)
Subject: Re: Reading HP4145B disks on a PC?
Originator: dataram@tigger.jvnc.net
Organization: JvNCnet, Princeton University, NJ
Date: Thu, 1 Oct 1992 10:27:11 GMT

Along a similar track, how about reading data from an HP16500
logic analyser?
      Regards,
            Chuck 

-- 
**********************************************************
* Chuck Staatse       Dataram Corp.  609-799-0071 x 284  *
*  chuck@dataram.jvnc.net |  chuck@dataram.com           *
**********************************************************
From: glipton@lafcol.lafayette.edu (Gary Lipton)
Newsgroups: comp.lsi.cad
Subject: ROM in OCT
Keywords: rom oct
Date: 3 Oct 92 17:15:04 GMT
Organization: Lehigh University, CSEE Dept, Bethlehem, PA

Is there any way of building ROM in OCT?  Or any PD tools for building
ROM in SCMOS technology?

Gary Lipton
Lafayette College
Newsgroups: comp.lsi.cad
From: lsto@huldra.tdata.no (Lech Slawomir Tomczak)
Subject: Verilog-HDL Mode for emacs
Organization: Tandberg Data A/S, Oslo, Norway
Date: Tue, 29 Sep 1992 10:14:17 GMT
X-Newsreader: Tin 1.1 PL3

[ Article crossposted from comp.emacs ]
[ Author was Lech Slawomir Tomczak ]
[ Posted on Mon, 28 Sep 1992 13:11:25 GMT ]

Does anybody have a Verilog-HDL mode for emacs?
If so, please mail to lsto@tdata.no

Lech Tomczak, Tandberg Data A/S, Oslo, Norway
Xref: sparky comp.lsi.cad:982 comp.lsi:612
From: blackman@hodgkin.med.upenn.edu (David Blackman)
Newsgroups: comp.lsi.cad,comp.lsi
Subject: Reading HP4145B disks on a PC?
Date: 30 Sep 92 15:11:49 GMT
Followup-To: comp.lsi.cad
Organization: University of Pennsylvania

Is there software available that allows you to read data or programs
from the 3.5" floppy disks written to by a HP4145 semiconductor curve
tracer?
-- 
David Blackman
blackman@hodgkin.med.upenn.edu
(215) 898-3553
From: glipton@lafcol.lafayette.edu (Gary Lipton)
Newsgroups: comp.lsi.cad
Subject: ROM in OCT; mizer
Date: 4 Oct 92 18:08:22 GMT
Organization: Dept. of EE, Lafayette College, Easton, PA
Originator: glipton@lafcol

1. Is there any way to do ROM in OCT, or any PD tools for doing ROM
in SCMOS??

2. Does mizer work at all?  It doesn't work on the example in the OCT
docs.

3. Is there an address at Berkeley to send questions like this?


Gary Lipton
Dept. of EE
Lafayette College
Newsgroups: comp.lsi.cad
Subject: e-mail address of Dr Fraeman ?
From: mohan@jupiter.cse.utoledo.edu (Mohan Pakkurti)
Date: 26 Sep 92 20:03:57 EST
Distribution: world

Hi,

Does anyone know how I can communicate with Dr M E Fraeman ?

I heard that he works at the Applied Physics Laboratory at the
John Hopkins University.

Any e-mail address, or telephone number will be of great use to
me to contact him.

Thanks for your help. :)
--mohan
-- 
===============================================================================
+ Mohanakrishna Pakkurti            + mohan@jupiter.cse.utoledo.edu           +
+ HOME: 2917 Kendale #204, Toledo OH 43606. Phone:(419)472-6936               +
===============================================================================
Newsgroups: comp.lsi.cad
From: marek@cadence.com (Marek Ryniejski; x6259)
Subject: Public Domain Verilog Parser
Organization: Cadence Design Systems/CAE Div, Lowell MA
Distribution: comp
Date: Wed, 23 Sep 1992 10:22:30 GMT


    I'm interested in obtaining a public domain Verilog parser
(lex and yacc files). A full blown compiler would be even  better.

    Please, send email to: marek@cadence.com
--
Marek
From: glipton@lafcol.lafayette.edu (Gary Lipton)
Newsgroups: comp.lsi.cad
Subject: meg & peg
Date: 6 Oct 92 18:10:40 GMT
Organization: Lafayette College, Easton PA

Are Meg, Peg, and MPLA (the old Magic PLA tools)
available and/or supported anywhere?  

Gary Lipton
Lafayette College
From: glipton@lafcol.lafayette.edu (Gary Lipton)
Newsgroups: comp.lsi.cad
Subject: ROM in Oct; MIZER
Date: 4 Oct 92 18:05:21 GMT
Organization: Dept. of EE, Lafayette College, Easton, PA
Originator: glipton@lafcol

1. Is there any way to do ROM in OCT, or any PD tools for doing ROM
in SCMOS??

2. Does mizer work at all?  It doesn't work on the example in the OCT
docs.

3. Is there an address at Berkeley to send questions like this?


Gary Lipton
Dept. of EE
Lafayette College
Xref: sparky comp.lsi:610 comp.lsi.testing:229