HDTenEightyP/NetNews huggingface dataset:
From: doconnor@sedona.intel.com (Dennis O'Connor)
Newsgroups: comp.arch
Subject: Re: Machines with cond. assignment instruction?
Date: 26 Jan 93 18:21:51 GMT
Organization: Intel i960(tm) Architecture
NNTP-Posting-Host: potato.intel.com
In-reply-to: gss@ilx018.intel.com's message of 25 Jan 93 08:24:32 GMT


gss@ilx018.intel.com (Shavit Amir) writes:
] Pradeep Dubey (pradeep@watson.ibm.com) wrote:
] : Hello Everyone,
] : Are there announced machines (specially micros) with
] : some conditional assignment instruction.  I mean
] : instruction such as the following:
]
] : MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */
]
] : where, c1 refers to some result of some previous compare.
]
] The above instruction is a 4 operand instruction, as the condition code is
] another implicit source operand. The best way to perform a conditional move
				       ^^^^
] is to have compares set or clear all the bits in a register.
] Once that is done, conditional moves are simple.
]
] AND R1, R2 -> R4    /* R1 containes the condition code */
] ANDNOT R1,R3 -> R4

? Why is
	TEST<cc>, tsrc1, tsrc2, tdst
	AND       tdst, msrc1, mdst
	ANDNOT    tdst, msrc2, mdst

"best" compared to

	TEST        tsrc1, tsrc2
	SELECT<cc>  msrc1, msrc2, mdst

Yes, the first avoids the CC-bits bottleneck, but multiple CCs could do that
without consuming an entire register (a la RS6000). It uses three intructions
instead of two, so it seems a loss to me.

Yes, the latter uses three inputs and one output, where one input
is the CCs. However, add-with-carry does this too, and most architectures
already have it, so it can't be a big deal.
--
Dennis O'Connor			doconnor@sedona.intel.com
From: jjs40@cd.amdahl.com (John Sullivan)
Newsgroups: comp.arch
Subject: Re: How many PC's make an Amdahl mainframe
Date: 28 Jan 93 18:52:05 GMT
Organization: Amdahl Corporation, Sunnyvale CA

Our news feed missed the beginning of this thread, so I never saw the original
posting.  But, I'll toss out some numbers to kick around.

Our current high-end machine is an 8-CPU shared memory symmetric
multiprocessor.  The FCS cycle time was 6.5ns, but I don't know what we are
currently shipping them at.  The CPU pipeline is capable of issuing an 
RX-format instruction every cycle, which is equivalent to a load immediately
followed by an ALU operation.  The machine holds 2GB of 25ns main storage, 
and 8GB of 80ns extended storage.  It supports 4 I/O processors, each of
which can handle up to 128 channels.  Both high-speed fiber-optic and older
parallel 370 channels are supported.

I won't argue a lot about CPU performance, because our metrics are different
from those used by the non-IBM compatible markets. 

As far as memory and I/O are concerned, PC's in general still can't support
more than 16MB of RAM.  A SCSI controller with DMA support provides about 
the same functionality as a mainframe I/O channel.  In theory, you can put
more than one in a PC, but the bus can't really support it at that point.

So, divide 10GB by 16MB and you get something in the range of 640 PC's to
match a mainframe on memory.  If you're concerned about I/O, it'll take 
about 512 PC's to match the mainframe.  I could also dig up the numbers on
weight and power consumption, but those are too scary to think about.

On a side note, someone mentioned interrupt handling capability.  The IBM
390 architecture has complex facilities for batching up multiple interrupt
events and distributing them across multiple CPUs.  This is a major win
when it comes to running thousands of I/O devices at the same time.

-- 
John Sullivan, Engineer/CPU Development  |  "Fools!  I'll destroy them all..."
Amdahl Corporation, Sunnyvale CA         |  jjs40@cd.amdahl.com, (408)746-4688
Newsgroups: comp.arch
From: mcconnel@irisa.fr (Roderick McConnell)
Subject: faster internal clocks
Organization: IRISA, Rennes (Fr)
Date: Tue, 26 Jan 93 09:17:19 GMT

  How are faster internal clocks for CPU's typically generated?  I am
wondering about processors such as the transputer, where the internal
clock is a significant multiple of the external clock.  The external
clock speed can not be varied (for the transputer at least), so my
first guess is that there is a PLL inside - but wouldn't that require
analog circuitry?
-- 
					- Roderick
Newsgroups: comp.arch
From: thompson@inmos.co.uk (Peter Thompson)
Subject: Re: faster internal clocks
X-Newsreader: TIN [version 1.1 PL8]
Date: Wed, 27 Jan 93 09:43:22 GMT

Roderick McConnell (mcconnel@irisa.fr) wrote:

:   How are faster internal clocks for CPU's typically generated?  I am
: wondering about processors such as the transputer, where the internal
: clock is a significant multiple of the external clock.  The external
: clock speed can not be varied (for the transputer at least), so my
: first guess is that there is a PLL inside - but wouldn't that require
: analog circuitry?
: -- 
: 					- Roderick

Absolutely correct.

--
Peter Thompson              JANET:    thompson@uk.co.inmos
INMOS Ltd                   UUCP:     ukc!inmos!thompson
1000 Aztec West             INTERNET: thompson@inmos.co.uk
Bristol BS12 4SQ, U.K.      Telephone: +44 454 616616
Newsgroups: comp.arch
From: apas611@chpc.utexas.edu (David Boles)
Subject: Re: How many PC's make an Amdahl mainframe
Organization: The University of Texas System - CHPC
Date: Thu, 28 Jan 93 22:25:37 GMT

I think all of the postings on this are missing a crucial point.  Can you
currently do the following with _any_ number of PC's _or_ workstations?
Is this capability likely to be avialable in the near future?

It is Friday afternoon, 5:30 pm Central time and your system jocks notice
a problem on your central system.  This system _is_ your business (10Billion
a year, lets say) and you can tolerate essentially _no_ downtime.

Your sys jocks isolate the problem to a particular process, but don't know
whether resetting will solve the problem.  You call the company and they
set up an approximate duplicate of your setup, and using diagnostic outputs
sent back to the remote site, duplicate the problem, while your machine
continues to run and serve requests, albeit at a slowly degrading level
of performance.  The service people diagnose the problem with your/their
software, fix it, test it (on their system), and then patch yours and have
your machine back up and running with a less than 30 minute down time
at your site and in a total amount of time of less than 6 hours.

This service is available is available around the clock, from any point on
the globe, any day of the year, period.  Obviously not all problems can
be fixed so quickly, but if that happens these firms offer to take on your
processing needs on a temporary basis.

Suppose you have PC's:

you call Microsoft (not even toll-free) and get told that the next upgrade
might fix that and they'd be happy to sell it to you for half what you
originally paid sometime in the next 12-18 months, unless they decide to
abandon the product.

you call Novell and get some capable response in the 1-7 day time frame,
if the problem isn't too hard.

You have workstations:

you call your Sun support group and get told that yeah they knew about
that bug years ago, that there is a CDROM fixing it (maybe) and it is
on back-order for 1-3 months.

etc.


Newsgroups: comp.arch
From: jcooley@world.std.com (John Cooley)
Subject: Joining ESNUG
Organization: The E-mail Synopsys Users Group (ESNUG)
Date: Thu, 21 Jan 1993 05:42:06 GMT


  If you're using the Synopsys Design Compiler and/or their ATPG product, you 
  might be interested in joining the E-Mail Synopsys Users Group (ESNUG).

  What we are is a group of hardware designers from all over the world who
  wish to trade experiences, bug reports and the techniques that we've
  found that work best in getting a design from a behavioral description
  to a final fully tested product.  This is a grassroots forum independent
  of Synopsys, Inc.

  A Sample of What We Discuss:

	- Known Synopsys Compiler Bugs    - Implementing Boundry Scan

	- Mentor related issues    - EDIF related issues

	- Hierarchical Compliations   - design_analyzer   - JTAG

	- How Various ASIC Vendors Model Their Macros.   - Clock Constraints

	- Using ATPG Tools   - The Best Way To Write State Machines in Verilog

	- Using VHDL   - System Simulation vs. Synopsys Friendly Code

	- Clever Workarounds to Known Pitfalls   - Testing Strategies

  In order to insure an open discussion, but yet keep our respective managers
  happy in having our company's projects remain SECRET, submissions to be 
  posted to the ESNUG mailing list can be stripped of identifying engineers 
  and company names if so requested.

  In addition, to further secure privacy and to avoid e-mail headers that
  are hundreds of names long, each mailing is a batch of singlely addressed 
  e-mail letters.

  If you want to join ESNUG, please send me e-mail to "jcooley@world.std.com"
  saying you wish to join and why.  (Please don't send a copy of this letter
  back to me, I know what you're refering to when you're writing.)

					- John Cooley
					  ESNUG Moderator

 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
     /o o\  /  it's a FEATURE!"   |    Backup Address: jcooley@miracle.com
    (  >  )                       |              (508) 429-4357
     \ - /       |   Snail Mail: P.O. Box 6222, Holliston, MA 01746-6222
     _] [_       |     "This here ain't no one's opinion 'cept my own."


Newsgroups: comp.arch
From: stripes@pix.com (Josh Osborne)
Subject: Re: Def  of a workstation (a lark)
Organization: Pix Technologies -- The company with no adult supervision
Date: Thu, 21 Jan 1993 21:20:05 GMT

In article <1993Jan16.020011.18759@grebyn.com> richk@grebyn.com (Richard Krehbiel) writes:
>If I may add to the discussion, this is something I just thought of.
>
>See how much commercial game software you can buy for your computer.
>Free stuff, and stuff included with the OS, doesn't count.  If there's
>no entertainment software, that means it's all work, and therefore a
>"workstation".

Maxis makes Simcity for the Sun, the catch is it runs under NeWS, not X.
(yes, you can use the openwindows X/NeWS server).  So either Sun no longer
makes workstations, or you need a new definition.  (and if we want to remove
DEC's, VAXen, and others from the workstation market, send me, say, $100 and
I'll send you the correct copy of xtank....)
-- 
           stripes@pix.com              "Security for Unix is like
      Josh_Osborne@Real_World,The          Multitasking for MS-DOS"
      "The dyslexic porgramer"                  - Kevin Lockwood
We all agree on the necessity of compromise.  We just can't agree on
when it's necessary to compromise.       - Larry Wall
Newsgroups: comp.arch
From: marsh@MITL.COM (Brian Marsh)
Subject: Call for Papers: WWOS-IV
Originator: marsh@wasabi
Organization: Matsushita Information Technology Laboratory, Princeton, NJ
Date: Thu, 21 Jan 1993 16:39:35 GMT


			   CALL FOR PAPERS
      Fourth Workshop on Workstation Operating Systems (WWOS-IV)
			   Napa, California
			 October 14-15, 1993

The Fourth Workshop on Workstation Operating Systems will bring
together researchers in operating systems for a range of
computing environments, including workstations, notebooks,
and palmtop computers.  The purpose of WWOS-IV is to examine
controversial issues in operating systems for these platforms.

In contrast to previous years, we request submissions of papers that
describe ongoing or completed research, as well as position papers
that propose new directions, advocate non-traditional approaches, or
generate controversy and discussion.

As well as traditional topics, this year's workshop will pay special
attention to issues relevant to the next generation of 
personal computing, including:

	- models and implementations for ubiquitous computing	
	- mostly connected/disconnected computing
	- protocols for low-bandwidth networking
	- scalable display and window management
	- real-time and multimedia
	- system requirements for virtual reality platforms
	- global, widely accessible, storage systems	
	- OS support for small-scale embedded systems

To assure a productive workshop, attendance will be limited to 60
participants active in the field.  Each potential participant should
submit 5 copies of a 1--5 page summary paper that makes clear its
contribution to the workshop.  Submissions should be mailed to the
program chair. For registration information, contact the general
chair.

IMPORTANT DATES
	Submission deadline: 		May 31, 1993
	Notification of acceptance: 	July 30, 1993

Program chair	Brian Bershad	
		Carnegie Mellon University
		School of Computer Science
	     	Carnegie Mellon University
               	5000 Forbes Avenue
               	Pittsburgh, PA,  15213-3891 USA
                (Brian.Bershad@CS.CMU.EDU)

General chair	Fred Douglis
		Matsushita Information Technology Laboratory
	       	182 Nassau Street, Third Floor
	       	Princeton, NJ,  08542-7072
             	609 497-460, 609 497-4013 (fax)
               	(douglis@mitl.com)
-----------------------------------------------------------
Program committee
		John Carter	University of Utah
	       	David Cheriton	Stanford University
	       	Dave Cutler	Microsoft
	       	Frans Kaashoek	Massachusetts Institute of Technology
	       	Brian Marsh	Matsushita Information Technology Laboratory
	       	Mike Schwartz	University of Colorado at Boulder
	       	Margo Seltzer	Harvard
	       	Mark Weiser	Xerox PARC
-- 
Brian Marsh
Matsushita Information Technology Laboratory  | Email: marsh@mitl.com
182 Nassau Street			      | Phone: +1 609 497-4600
Princeton, NJ  08542 USA		      | Fax:   +1 609 497-4013
From: wilson@moonshine.llnl.gov (Mike Wilson )
Newsgroups: comp.arch
Subject: Re: Want Sun 2000 info
Date: 26 Jan 93 02:18:04 GMT
Organization: Magnetic Fusion Energy - LLNL

tal@plts.uucp (Tom Limoncelli) writes:

>I'm still taking bets on (1) if it ships in Q2 1993, and (2)
>if they drop the Vikings out of it by Q1 1994.

actually, I've another question.  Why doesn't sun sell an MBUS card 
with the Ross CY7C620???  Certainly that would be better than putting
off those oh-so-annoying customers for a year.

-mike
--
-------------------------------------------------------------------
wilson@moonshine.llnl.gov | Unix Sysadmin - MFE	 | 510-423-5937
Newsgroups: comp.arch
From: rbe@yrloc.ipsa.reuter.COM (Robert Bernecky)
Subject: Re: Control TO Data Dependence
Keywords: Control Dependence, Data Dependence, High-Level Synthesis
Reply-To: rbe@yrloc.ipsa.reuter.COM (Robert Bernecky)
Organization: I P Sharp Associates, Toronto
Distribution: Snake Island Research Inc
Date: Wed, 27 Jan 93 15:31:36 GMT

In article <1993Jan23.003531.21573@cs.brown.edu> lka@lems17lems.brown.edu (Lalit K. Agarwal) writes:
>Has anyone played with converting CONTROL-DEPENDENCE to DATA-DEPENDENCE in
>High-Level-Synthesis or come across any algorithm for doing it in the literature.?
>All suggestions are highly welcome.

This is common in APL and J. Both languages are array-oriented:
    1 2 3 + 8 4 2
9 6 5

so all primitives are defined on entire arrays, rather than on scalars.
Given this, programs are shorter, cleaner, more elegant, and more likely to
work if you describe algorithms in terms of array operations instead of loops.
Thus, you'll see expressions like this:

    X + 55* (X<4)     NB. Add 55 to those elements of X which are less than 4.

This involves knowledge of simple arithmetic identities, but there are
merge and selection capabilities which permit fancier stuff:
    t =. "this is my   text string'
    b =. t=' '
    b
0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0  
    NB. The above locates blanks in t.
    NB. Now replaces blanks by '*'.
    t[b/i. #b] =. '*'   NB. This is part APL, part J... 
    NB. #b is the shape of b, i.e., 24 
    NB. i. #b is the first #b integers.
    NB. b/i.#b removes from the list of #b integers those which are
        not corresponding to blanks.
    NB. t[...] =. '*' replaces the non-blank elements.   

This stuff is common in APL. Go read ACM SIGAPL Quote Quad conference 
proceedings for more examples, or come to APL93 in Toronto this August
15-19!
{I'm the Tutorials Chair...}

One last example: A model of a loom is 2.5 pages of BASIC (SEE P. Heiser,
August 1981 or so BYTE article {from memory}). This compresses into
about 12 characters of APL: Two indexing operations and one inner product.
It also runs bags faster than BASIC. Even on one processor... 8^}

Bob


Robert Bernecky      rbe@yrloc.ipsa.reuter.com  bernecky@itrchq.itrc.on.ca 
Snake Island Research Inc  (416) 368-6944   FAX: (416) 360-4694 
18 Fifth Street, Ward's Island
Toronto, Ontario M5J 2B9 
Canada
Xref: sparky comp.arch:12382 comp.arch.storage:944 comp.os.msdos.misc:7185 comp.os.msdos.programmer:12418 comp.periphs:1779 comp.sys.ibm.pc.hardware:37060
From: hhaldre@mhs.tartu.ee (Heikki Haldre)
Newsgroups: comp.arch,comp.arch.storage,comp.os.msdos.misc,comp.os.msdos.programmer,comp.periphs,comp.sys.ibm.pc.hardware
Subject: (Q) AST address, RAMPAGE info needed
Date: 25 Jan 1993 07:32:06 -0600
Organization: UTexas Mail-to-News Gateway
NNTP-Posting-Host: cs.utexas.edu




Hi folks

HELP ME!!! AST RAMPAGE/2 programming documentation needed!!!
...or AST technical support E-mail or fax/mail address needed

Anybody likes a company called AST???
This company is doomed.

I've got an AST RAMPAGE/2 ( well, it is old, really antique, but XT
holding it doesn't need better. ) memory card ( can be used to backfill
conventional memory or as expanded or extanded memory. )
And, possibly, I never will have anything from AST any more. At least
if I have to pay for AST's products.

Now this card has a wonderful(!?) setup program, so You needn't bother
setting proper switches and so on. It has a memory that holds the config
parameters.

But, a guy came, wondered: what this program's for?, and started to
study it. He set card's memory start address at 0K and somehow
made the card to think that it had only 64KB memory on board.

You think - no problem, just run the setup program again and everything
will be OK?

NO! This program is a simple .COM program. Even if it is started
by it's own BOOT program (ASTDOS,) it loads into segment higher than
0, of course. And it sets it's stack starting offset 0FFFFh - so it
can't be run on a machine that has only 64KB memory. I found one
place where it moved this value into SP register, but I couldn't find
the other - maybe there are more bugs.

Well, I need programming documentation on how to reset and write
this card's setup.

I know the following things:
 It's on board memory holds it's
 
    Base I/O address: it can be 208h, 218h, 258h, 268h, 2A8h, 2B8h, or 2E8h
    Amount of memory to backfill conventional memory.
    Memory Bank type: Bank 0 has 64K DRAMs, Bank 0 and 1 have 64KB DRAMs
                      or All banks have 256KB DRAMs
    Parity Error Checking: Enabled or Disabled
    Start Address of Expanded Memory
    
I think that the program outports something, inports something and then
writes the configuration into some area of memory ( for example at
segment 0D000h ). At least, I have no other ideas.

From the various docs, I've got, I read that Toshiba 1000 EMM Unit has
the same ports - but I have no further info about these ports. If
You happen to know these port's, maybe You can help me.


Thank You.

Please E-Mail me to Internet: hhaldre@mhs.tartu.ee

Newsgroups: comp.arch
From: colwell@pdx022.world (Robert Colwell)
Subject: Re: Machines with cond. assignment instruction?
Organization: /fs2/d/colwell/.organization
Date: Wed, 27 Jan 1993 06:42:10 GMT

In article <6346@rosie.NeXT.COM> Bob_Beckwith@NeXT.COM (Bob Beckwith) writes:
   In article <1993Jan21.163607.31684@watson.ibm.com> pradeep@watson.ibm.com  
   > Are there announced machines (specially micros) with
   > some conditional assignment instruction.  I mean
   > instruction such as the following:
   > 
   > MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */
   > 
   > where, c1 refers to some result of some previous compare.
   > 
   > Any pointers to such machines or any quantitative evaluation
   > of usefulness of this instruction in the specific context
   > of some machine would be appreciated.

   Unless I'm mistaken, the Multiflow Trace machines had conditional assignment  
   instructions. While you certainly wouldn't classify them as micros, they're  
   there (or at least were, at one point :-( ). Any ex-Multifloyd's out there  
   (DBP? PKR?) might be able to provide more information.

Hi Bob and Pradeep: Yep, the MFCI Trace VLIWs had conditional moves. Really
handy in certain tight inner loops. To quote from our ASPLOS paper: "We
also included the integer SELECT operation, which provides the semantics of
the C "?" operator without branching." This worked so well that we expanded
this to include other operations in the /500 (which was under construction
when the company croaked) such as conditional stores.

It was a tad messy trying to work SELECTs into the basic ISA, though; this
operator has more sources than normal, so figuring out how to gracefully
specify three sources in an instruction format designed for two is not
trivial. "Graceful", of course, means the compiler code generator guy likes
it.

Bob Colwell  colwell@ichips.intel.com  503-696-4550
Intel Corp.  JF1-19
5200 NE Elam Young Parkway
Hillsboro, Oregon 97124
From: gints@prophet.esd.sgi.com (Gints Klimanis)
Newsgroups: comp.arch
Subject: HOw many PC's make an Amdahl mainframe
Date: 26 Jan 93 20:22:48 GMT
Organization: Silicon Graphics, Inc.
NNTP-Posting-Host: prophet.esd.sgi.com

An Amdahl CEO in yesterday's San Jose Mercury news claimed there was no
room in the world that could how enough personal computers to match the
power of an Amdahl mainframe.  Any guesses  as to the # of PC's and disk
drives required to match this Amdahl Mount Everest of computing?
Newsgroups: comp.arch,comp.arch.storage,comp.os.msdos.misc,comp.os.msdos.programmer,comp.periphs,comp.sys.ibm.pc.hardware
From: mgolden@cwis.unomaha.edu (Brian Golden)
Subject: Re: (Q) AST address, RAMPAGE info needed
Organization: University of Nebraska at Omaha
Date: Tue, 26 Jan 1993 07:47:52 GMT

hhaldre@mhs.tartu.ee  writes:
> HELP ME!!! AST RAMPAGE/2 programming documentation needed!!!
> ...or AST technical support E-mail or fax/mail address needed

AST Research INC.
16215 Alton Parkway
Irvine, CA 92718
(714)727-4141

They have an 800 number, but I don't have it.  Call 800 info. (1-800-555-1212)
and ask for it.  You get the same help.  A Japanese to English translator
would be helpful too!  :-)

Mike Golden - mgolden@cwis.unomaha.edu