HDTenEightyP/NetNews huggingface dataset:
From: jamesd@techbook.com (James Deibele)
Subject: Re: `Envisioning Information' ? Book Reference/Review Sought.
Keywords: Envisioning Information
Organization: TECHbooks of Beaverton Oregon - Public Access Unix
Distribution: comp
Date: Thu, 16 Apr 1992 06:03:33 GMT

murray@castle.ed.ac.uk (D Laing) writes:

>Some months ago I glanced at an article referring to a book titled
>`Envisioning Information'.  I was curious about this book but at that
>time could not follow up the reference.  Of course I made a carfule note
>of the book information, and promptly lost it under an anonymous pile of
>paper. All I can recall now is the title!

I'm at home, so I don't have a copy of the book handy.  _Envisioning
Information_ was written by Edward Tufte, who's best known for his earlier
book, _The Visual Display of Quantitative Information_.  VDQI was
written up extremely favorably in a wide variety of desktop publishing
and general computer magazines for the way it describes how complex 
information could be described using charts, and how charts could also
make simple information look complex.  

I haven't really looked at EI, so I'm not going to be able to help you
much on the contents.  When I glanced at it, it seemed to pick up where
the earlier book left off.

The ISBN is 0-9613921-1-8, it's a hardcover, and it lists for $48.  The
publisher is Graphics Press.  

So you know ... you could send a message to "bip@techbook.com" and put 
#TI = "Envisioning Information" in the body.  The #TI tells the program
that you're looking for a title.  You'll get a message back telling you
everything the database has on books that match that title.  Use a
subject line of "help" to get more info.
From: hofer@urz.unibas.ch (Remo Hofer)
Newsgroups: comp.lang.idl-pvwave
Subject: Re: SGI escape sequences
Date: 6 Apr 92 14:00:11 GMT
Article-I.D.: urz.1992Apr6.150011.14110
Organization: University of Basel, Switzerland

In article <1992Apr3.150440.5531@jhunix.hcf.jhu.edu>, 
murthy_j@jhunix.hcf.jhu.edu (Jayant Murthy) writes:
> Does anyone have a list of the escape sequences for an SGI IRIS Indigo
> keyboard? I want to define the keys and the old vt200 assignments on
> my DECstation don't work.
> 
> Thanks
> Jayant Murthy
> murthy@pha.jhu.edu
> 

In the following piece of code I define some keycodes to work on a vms
vaxstation as well as on a SGI (PI 4D/35). You will find the keycodes
produced by the funtion keys of the iris keyboard in the list (SGIF1 ...
SGIF12). I do not know about other keycodes, such as Insert etc.
Hope this helps.

Remo Hofer

  ; Initialise keyboard (in VMS they are predefined)
  IF STRLOWCASE(STRTRIM(!VERSION.OS, 2)) NE 'vms' THEN BEGIN

    keys = [ $
      ['F1',	'\033[11~'], $ ; vt200 codes
      ['F2',	'\033[12~'], $
      ['F3',	'\033[13~'], $
      ['F4',	'\033[14~'], $
      ['F5',	'\033[15~'], $
      ['F6',	'\033[17~'], $
      ['F7',	'\033[18~'], $
      ['F8',	'\033[19~'], $
      ['F9',	'\033[20~'], $
      ['F10',	'\033[21~'], $
      ['F11',	'\033[23~'], $
      ['F12',	'\033[24~'], $
      ['F13',	'\033[25~'], $
      ['F14',	'\033[26~'], $
      ['HELP',	'\033[28~'], $
      ['DO',	'\033[29~'], $
      ['F17',	'\033[31~'], $
      ['F18',	'\033[32~'], $
      ['F19',	'\033[33~'], $
      ['F20',	'\033[34~'], $
      ['PF1',	'\033OP'], $
      ['PF2',	'\033OQ'], $
      ['PF3',	'\033OR'], $
      ['PF4',	'\033OS'], $
      ['SGIF1',	'\033[001q'], $ ; SGI winterm codes
      ['SGIF2',	'\033[002q'], $
      ['SGIF3',	'\033[003q'], $
      ['SGIF4',	'\033[004q'], $
      ['SGIF5',	'\033[005q'], $
      ['SGIF6',	'\033[006q'], $
      ['SGIF7',	'\033[007q'], $
      ['SGIF8',	'\033[008q'], $
      ['SGIF9',	'\033[009q'], $
      ['SGIF10','\033[010q'], $
      ['SGIF11','\033[011q'], $
      ['SGIF12','\033[012q']]
    s = SIZE(keys)
    FOR i=0, s(2)-1 DO DEFINE_KEY, keys(0, i), ESCAPE=keys(1, i)

    ; self defined keys not possible in vms
    DEFINE_KEY, 'SGIF1', 'sxm_main_menu', /TERMINATE
    DEFINE_KEY, 'SGIF2', 'sxm_help', /TERMINATE

  ENDIF

  DEFINE_KEY, 'F1', 'sxm_main_menu', /TERMINATE
  DEFINE_KEY, 'PF1', 'sxm_main_menu', /TERMINATE
  DEFINE_KEY, 'DO', 'sxm_main_menu', /TERMINATE
  DEFINE_KEY, 'F2', 'sxm_help', /TERMINATE
  DEFINE_KEY, 'PF2', 'sxm_help', /TERMINATE
  DEFINE_KEY, 'HELP', 'sxm_help', /TERMINATE

-- 
       RFC822:  <hofer@urz.unibas.ch> or <hofer%urz.unibas.ch@CERNVAX.BITNET>
        X.400:  S=hofer;OU=urz;O=unibas;P=SWITCH;A=ARCOM;C=CH
  HEPNET/SPAN:  CHGATE::YOGI::HOFER or 20579::48130::HOFER
Organization: Arizona State University
Date: Monday, 6 Apr 1992 18:15:51 MST
From: <ATPPH@ASUACAD.BITNET>
Newsgroups: comp.lang.idl-pvwave
Subject:    IDL: Printing on Tektronics Phaser

I have a relatively simple problem: For transparencies
it is sometimes useful to keep the background color
'black'. The IDL Postscript-device, however, swaps
foreground and background colors as compared to the
'X' device. How do I get around this default? I have
tried changing |p.background and |p.color or modifying
the color table. The plots are generated by 'standard'
shade_surf, plot etc. commands (no images). Screen-dumps
look OK, but the resolution is not satisfactory.

Thanks,
                                Peter.

Newsgroups: comp.lang.idl-pvwave
From: isaacman@stars.gsfc.nasa.gov (Subvert the Dominant Paradigm! (301) 513-7769)
Subject: Re:    IDL: Printing on Tektronics Phaser
News-Software: VAX/VMS VNEWS 1.4-b1  
Organization: NASA/GSFC-Laboratory for Astronomy and Solar Physics
Date: Fri, 10 Apr 1992 18:56:00 GMT

In article <92097.181551ATPPH@ASUACAD.BITNET>, <ATPPH@ASUACAD.BITNET> writes...
>I have a relatively simple problem: For transparencies
>it is sometimes useful to keep the background color
>'black'. The IDL Postscript-device, however, swaps
>foreground and background colors as compared to the
>'X' device. How do I get around this default? I have
>tried changing |p.background and |p.color or modifying
>the color table. The plots are generated by 'standard'
>shade_surf, plot etc. commands (no images). Screen-dumps
>look OK, but the resolution is not satisfactory.
> 
>Thanks,
>                                Peter.
>
Use COLOR=255 as a plotting keyword.

Rich Isaacman 
Newsgroups: comp.lang.idl-pvwave
From: gsh7w@fermi.clas.Virginia.EDU (Greg Hennessy)
Subject: PLOTS and pixmaps
Organization: University of Virginia
Date: Wed, 8 Apr 1992 21:36:50 GMT


I have a situation where I wish to display certain portions of an
image much larger than the size of my workstation screen (2048x2048
bits). I can get much of what I want by creating a pixmap window, and
then using the DEVICE,/copy=[x,y,sx,sy,wx,wy,ch] call to display the
desired subsection of my image. My problem is that I wish to use the
PLOTS routine to draw circles and arrows (and a paragraph on the back
of each) to indicate certain features on my image. However, the PLOTS
routine seem to only write to the open window, NOT to the pixmap. 

Is there a way to do what I want in IDL? (v 2.2.2)

--
-Greg Hennessy, University of Virginia
 USPS Mail:     Astronomy Department, Charlottesville, VA 22903-2475 USA
 Internet:      gsh7w@virginia.edu  
 UUCP:		...!uunet!virginia!gsh7w
From: jacek@lamartine.int-evry.fr
Newsgroups: comp.lang.vhdl
Subject: question on VHDL compilers
Date: 1 Apr 92 13:52:23 GMT
Organization: INT Evry, France


I am interested if anyone is aware of any public
domain offerings of compilers for VHDL. If this
has been the subject of previous News items could
someone send me a copy of the summary. Otherwise,
if someone has some information please forward it
directly to me.

I am looking for PLD tools which are capable to
take VHDL description as a source. It would by 
helpful if i could get any information on it.

Thanks in advance.

Jacek Wytrebowicz
SYSTEMS AND NETWORKS DEPARTMENT
FRANCE TELCOM UNIVERSITY
INSTITUT NATIONAL DES TELECOMMUNICATIONS
9, rue Charles Fourier
91011 EVRY Cedex

email:  jacek@hugo.int-evry.fr
Newsgroups: comp.lang.vhdl
From: gs4t@helga1.acc.Virginia.EDU (Gnanasekaran Swaminathan)
Subject: Re: Using records with Synopsys
Reply-To: gs4t@helga1.acc.Virginia.EDU (Gnanasekaran Swaminathan)
Organization: University of Virginia
Date: Thu, 9 Apr 1992 21:51:06 GMT

In article <9950@lupine.ncd.com>, trevor@sheridan.ncd.com (Trevor Pearman) writes:
|> I am trying to use records with the Synopsys VHDL
|> synthesis tool (v2.2) and I am having problems
|> taking the range of an element. An example:
|> 
|> TYPE T_FOO is record
|> 
|>     ELEMENT_1: bit_vector(7 downto 0);
|>     ELEMENT_2: bit_vector(3 downto 0);
|> end record;
|> 
|> 
|> ...
|> 
|> A <= T_FOO.ELEMENT_1'range;
|> B <= T_FOO.ELEMENT_2'range;

T_FOO.ELEMENT_1'range attribute returns a range of values not a
single value. There is no "range type" in the sense of an array type
in VHDL. Hence, you cannot do
	type bitRange is Integer range 7 downto 0;
	type ucRange is Integer range <>;

	function tst (A: ucRange;...) return Integer is
	begin
		for i in A loop
			...
		end loop;
		...
	end;

	variable A: ucRange := T_FOO.ELEMENT_1'range;
	
	tst(T_FOO.ELEMENT_2'range,...);
	tst(A,...);
	
So, how do I accomplish what I set out to do?

	function tst (A: Bit_Vector;...) return Integer is
	begin
		for in in A'range loop
			...
		end loop;
	end;

	variable A: Bit_Vector( T_FOO.ELEMENT_1'range );
	variable B: Bit_Vector( T_FOO.ELEMENT_2'range );

	tst(B,...);
	tst(A,...);

-Sekar
Newsgroups: comp.lang.vhdl
Subject: Re: Using records with Synopsys
From: trevor@sheridan.ncd.com (Trevor Pearman)
Date: 13 Apr 92 22:42:57 GMT
Organization: Network Computing Devices, Mt. View, CA, USA

|> I am trying to use records with the Synopsys VHDL
|> synthesis tool (v2.2) and I am having problems
|> taking the range of an element. An example:
|> 
|> TYPE T_FOO is record
|> 
|>     ELEMENT_1: bit_vector(7 downto 0);
|>     ELEMENT_2: bit_vector(3 downto 0);
|> end record;
|> 
|> 
|> ...
|> 
|> A <= T_FOO.ELEMENT_1'range;
|> B <= T_FOO.ELEMENT_2'range;


Sorry for clouding the issue but I should have
said length not range. Need to engage brain
before posting...


TYPE T_FOO is record

    ELEMENT_1: bit_vector(7 downto 0);
    ELEMENT_2: bit_vector(3 downto 0);
end record;

signal FOO: T_FOO;

...

A <= FOO.ELEMENT_1'length;
B <= FOO.ELEMENT_2'length;


I find that using the range attribute
works. For example

for n in FOO.ELEMENT_1'range loop ....


-- Trevor
From: philip@mips.com
Newsgroups: comp.lang.vhdl
Subject: Re: VHDL (lex, yacc) : request
Date: 6 Apr 92 18:32:12 GMT
Article-I.D.: spim.ku169cINNr59
Organization: MIPS Computer Systems, Inc.
NNTP-Posting-Host: galileo.mips.com


 I am also interested in obtaining any type of source code for a
VHDL grammar parser.

Thanks

- Philip Schmidt  (philip@mips.com)    (408) 524-8247
UUCP: {ames,decwrl,prls}!mips!philip
USPS: MIPS Computer Systems, 928 E. Arques Ave, Sunnyvale CA, 94086
-
Newsgroups: comp.lang.vhdl,comp.lang.verilog
From: bygate@ncrcol.ColumbiaSC.NCR.COM ()
Subject: Re: UDL/I language desription?
Organization: NCR E&M Columbia SC.
Date: Tue, 14 Apr 92 17:59:09 GMT

kinzel@ibr.cs.tu-bs.de (Jens Kinzel) writes:
: I am looking for UDL/I language description to discuss differences
: between VERILOG/VHDL and UDL/I. Is there anyone, who knows about an
: article about this subject, and where to get it?
: 
: 						Jens

The April 1990 issue of the IEEE magazine: "Design and Test of Computers"
contains the second of a two-part article on VHDL vs. UDL/I.  I am not sure 
when the first part was published.

Terry.
-- 
     Terrence A. Bygate    803-791-6492      |   "A problem is nothing but an
    Multiprocessor Systems Business Unit     |   opportunity dressed in work
  NCR Corporation - 3500 Module Development  |   clothes" -borrowed
---------------------------------------------+----------------------------------
From: martinwh@syma.sussex.ac.uk (Martin White)
Newsgroups: comp.lang.vhdl
Subject: VHDL parsers
Keywords: Public domain
Date: 8 Apr 92 12:57:45 GMT
Organization: University of Sussex

Hi,

Two people were asking for VHDL parsers, I was in the midst of
replying but my system went down and I don't know who they are.  Never
the less, last February's FAQ products and public domain had some
relevent infomation.  To save Thomas Dettmer, the originator of this
FAQ some work, I'll post this information here.

********************************************************************
This is cut from the FAQ, i.e. directly quoted from Thomas Dettmer
********************************************************************
A Public Domain VHDL Parser/Generator written in Prolog
is available via anonymous FTP from the Microelectronics
Center of North Carolina (MCNC.ORG). Look for vhdl.tar.Z in /pub
For a more up-to-date version of this software (including
bug fixes, a graphical editor and logic synthesis modules),
contact Peter Reintjes at Quintus Corporation:
NEW email adresses!!:
     pbr@quintus.com         (they are on the internet now!)
or   pbr@deerfeld.ingr.com   (I work for DASIX now!)



I don't know if the following tools are PD or not, but they are accessible
    uceng: :there is a grammar suited for lex, but no actions
associated.  There is also a validation suite.
(anonymous FTP on uceng.uc.edu)

 
dettmer@jupiter.ls1.informatik.uni-dortmund.de
phone: +49-231 755 6323, FAX: +49-231 755 6555
Thomas Dettmer, Dortmund University, Computer Science I
Post Box 50 05 00, W-4600 Dortmund 50, Germany
**********************************************************************

I include his details for completeness but would add that he has
mentioned that the FAQ details are not quaranteed complete or correct
because its a lot of work compiling the FAQ.

Regards,
-- 
Martin White
VLSI and Computer Graphics Research Group
ENGG II
University of Sussex
Newsgroups: comp.lang.vhdl
From: rkrishna@magnus.acs.ohio-state.edu (Ramesh Krishnamurthy)
Subject: Experience with VANTAGE System - Help 
Organization: The Ohio State University
Distribution: usa
Date: Fri, 10 Apr 1992 18:36:41 GMT

we were using intermetrics VLS/VHDL/VSE before we got the Vantage VSS
system in our lab.

there have been several problems we encounter when we try to analyze
and simulate models that were written and tested on the intermetrics
system. for example, Vantage gives this error message in one of the
models where we used a 'record'.

***********************************************************************
.
.
.

TYPE rec IS RECORD
   a : INTEGER;
   b : BIT;
END RECORD;

.
.
.

ENTITY tt IS PORT ( x,y : rec); END tt;            -- line 9
ARCHITECTURE t OF t IS

  
BEGIN 


    x.b <= '0';                                    -- line 33
-- NOTE THAT ONLY 'a' IS BEING ASSIGNED A VALUE HERE --


END 
*************************************************************************

The compiler out put is something like this :

    
    VHDL Compiler, v3.110.  Release 3.110
    Copyright 1991, Vantage Analysis Systems, Inc.
    ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    Compiling VHDL source file "test.vhdl" line 1.
    Compiled entity:TST in library TEST.
    ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    Compiling VHDL source file "test.vhdl" line 9.
**Error: LINE 9 *** Resolved composite signal subelement X.A not driven by process near line 33 although other subelements are driven.   (compiler/analyzer/3)
    ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    1/2 design unit(s) compiled successfully.
    Syntax summary: 1 error(s), 0 warning(s) found.


Has any other Vantage users encountered this problem? is this the way
assignments are to be done in standard VHDL? (The LRM does not say
much about it!).

In some cases, interchanging the assignment statements with the following statements or recompiling has resulted in this error message going away. 

i would appreciate any comments or suggestions on this problem.

thanks.

ramesh

--------------------------------------------------------------------
USMail: 608 Dreese Labs, 2015 Neil Av.,   |     
        The Ohio State University,        |    613, Tuscarawas Ct.
        Columbus, OH 43210                |    Columbus, OH 43210
Phone: (614)-292-2906                     |    (614)-293-0019
Email: ramesh@ee.eng.ohio-state.edu       |
       rkrishna@magnus.acs.ohio-state.edu |
--------------------------------------------------------------------
From: mickey@mogadon (Laurent ROCHETTE)
Newsgroups: comp.lang.vhdl
Subject: VHDL (lex, yacc) : request
Date: 6 Apr 92 12:28:07 GMT


I'm looking for a file containing a VHDL description grammar in lex and yacc format.
Any location or file will be welcome.
	Thanks.
	

Please answer me at :
------------------------------------------------------------------------------
Laurent ROCHETTE (ENSIMAG)                    e-mail : mickey@atarax.imag.fr
INPG/CSI, University of Grenoble              phone  : (33) 76 42 24 86
------------------------------------------------------------------------------
Newsgroups: comp.lang.vhdl
From: Alfred.Mikschl@arbi.informatik.uni-oldenburg.de (Alfred Mikschl)
Subject: looking for VHDL Compiler
Organization: University of Oldenburg, Germany
Date: Wed, 8 Apr 1992 09:11:49 GMT
Keywords: VHDL Compiler, IEEE

	Hello
We are looking for a VHDL Compiler which supports the IEEE Standard.
Are there any VHDL Compiler available (in the Puplic Domain)?
Any information, address ftp Site etc will be welcome.

	Thanks

Alfred Mikschl	email : Alfred.Mikschl@arbi.informatik.uni-oldenburg.de
University of Oldenburg, Germany; Phone +49 441 798 2368
From: wdb@vhdl (William D. Billowitch)
Newsgroups: comp.lang.vhdl
Subject: Std_Logic_1164
Date: 9 Apr 92 21:22:03 GMT
Organization: The VHDL Technology Group

*****************************************************************
* G R E A T      N E W S   !!!!!!
*****************************************************************
STD_LOGIC_1164 has successfully passed the ballot with a
whopping 95 % Positive response ! Thanks to all of you
who contributed and voted.


Sincerely,

-------------------------------------------------------------
William Billowitch                  e-mail: uunet!vhdl!wdb
The VHDL Technology Group                   vhdl!wdb@uunet.uu.net (internet)
974 Marcon Blvd, Suite 260          Phone : 215-266-9791
Allentown, PA 18103                 Fax   : 215-266-9783
From: pturner@nevin.intel.Com (Pete Turner)
Newsgroups: comp.lang.vhdl
Subject: TEST POST please ignore
Keywords: TEST
Date: 30 Mar 92 15:20:20 GMT
Originator: pturner@nevin


test post...please ignore
-- 

-- 

 ______________________________________________________________________________

 Pete Turner              | "It's a dog-eat-dog world out there, and I'm 
 Intel Corporation        |  wearing Milkbone underwear!"
 5000 W. Chandler Blvd.   |
 M/S CH3-36               |  -- Norm Peterson from "Cheers!"
 Chandler, AZ 85226       | ---------------------------------------------------
 pturner@sedona.intel.com | 
 ATT: (602) 554-8906      |  ...stay tuned for a new message...coming to an
 FAX: (602) 554-7281      |  email message near you!...
 ______________________________________________________________________________
From: trevor@sheridan.ncd.com (Trevor Pearman)
Newsgroups: comp.lang.vhdl
Subject: Using records with Synopsys
Date: 8 Apr 92 23:29:53 GMT
Organization: Network Computing Devices, Mt. View, CA, USA

I am trying to use records with the Synopsys VHDL
synthesis tool (v2.2) and I am having problems
taking the range of an element. An example:

TYPE T_FOO is record

    ELEMENT_1: bit_vector(7 downto 0);
    ELEMENT_2: bit_vector(3 downto 0);
end record;


...

A <= T_FOO.ELEMENT_1'range;
B <= T_FOO.ELEMENT_2'range;


Does anyone know if I:

a) am using illegal vhdl
b) have found a bug
c) am missing something (like paranthesis)

-- Trevor
Newsgroups: comp.lang.vhdl
From: kswatek@su19az.ess.harris.com (Ken Swatek)
Subject: Where is the VHDL Cookbook?
Followup-To: comp.lang.vhdl
Keywords: VHDL Cookbook
Reply-To: kswatek@su19az.ess.harris.com
Organization: Harris (Government Aerospace Systems)
Date: Wed, 8 Apr 1992 17:29:55 GMT

---
Does any know here the anonymous ftp site for Peter Ashenden's 
"The VHDL Cookbook" is ?

Thanks in Advance,
Ken
______________________________________________________________________________

Ken Swatek                             INTERNET: kswatek@su19az.ess.harris.com
Harris Corporation                     UUCP:     uunet!su19az!kswatek
Government Aerospace Systems Division  CCMail:   harris.kswatek
Mail Stop: 102-4827                    FAX:      407-729-3211
P.O. Box 94000                         Pager:    407-690-8548 (Digital)
Melbourne, Florida 32902               Voice:    407-727-6081
______________________________________________________________________________
From: foobar@dist.dist.unige.it (Maurizio Vitale)
Newsgroups: comp.lang.vhdl
Subject: Re: VHDL desc. of Sparc
Date: 11 Apr 92 06:08:15 GMT
Reply-To: foobar@dist.dist.unige.it (Maurizio Vitale)
Distribution: comp
Organization: DIST - Universita` di Genova

I don't know for sure, but I recall having read somewhere on the net that the 
SparcStation 1 had been simulated up to the point to be able to boot the Unix
kernel using Verilog.

	Maurizio
From: sudhir@cirrus.com (Sudhir Sharma)
Newsgroups: comp.lang.vhdl
Subject: How do you implement Global Procedures ?
Summary: I need info on how to implement global procedures in VHDL
Keywords: Procedures, VHDL
Date: 8 Apr 92 18:19:53 GMT
Organization: Cirrus Logic Inc, Fremont, CA

Hello, I am a former Verilog user and need some help in implementing a 
consistent Test Bench Method in VHDL.  Basically, what I would like to do
is to create a model of a component (a microprocessor, for example) and have
Procedures (Tasks in Verilog) like READ and WRITE inside that component which
I would like to invoke from the Test Bench.  Another layout of this may exaplainwhat I am trying to accomplish:

          entity cpu is
                 port ( .....)
          end cpu;
          architecture behavioral of cpu
          begin
               ...
               procedure READ (adr : in  mvl7_vector(15 downto 0)...

               end READ;
               procedure WRITE(adr ...
               ...
               end WRITE;
          end behavioral;

Now, if I instantiate cpu as a component in a system level schematic, how do
I invoke the tasks READ and WRITE ?  In Verilog, this was done by using the
prefix (component instance name like U1 for CPU) followed by the procedure (TASKin verilog).  For example, in Verilog you would invoke READ by using
                U1.READ (adr)

I understand that packages can be used in VHDL for creating global procedures
but I don't want to type all the signals involved in the port list.  

If you even have a clue, please let me know.  I would appreciate it.  The
fastest way to get this information to me is by my Email address.  Thanks.

Sudhir
Email: Sudhir@pixel.cirrus.com
Phone: 214-985-2354
Newsgroups: comp.lang.vhdl
From: schuppan@infotech.tu-chemnitz.de (Holger Schuppan)
Subject: ddl for Xilinx LCAs
Summary: Exchange of experience in logic design for Xilinx LCAs would be useful.
Keywords: DDL, FPGA, LCA, Xilinx
Organization: University of Technology Chemnitz, FRG
Date: Mon, 6 Apr 1992 09:01:04 GMT

I have to design a quite complex LCA for my diploma paper and I am using
some design tools developped at Chemnitz University. These are a DDL-
Compiler and Simulator, an high efficient optimizer and a netlist
generator for Xilinx Netlist Format. All these tools work on PC with
MS-DOS and produce optimized CLB equations, better than XNFOPT can do.
They put out a .MAP file, that means that the equations are already
mapped on the CLBs.
I am interested in exchange of experiences in this field. My email
address is   schuppan@infotech.tu-chemnitz.de         .
Good luck,
	   Holger