HDTenEightyP/NetNews huggingface dataset:
From: green@eniac.seas.upenn.edu (Bradley Green )
Newsgroups: comp.sys.m68k
Subject: Modular 680x0's
Date: 15 Apr 92 12:48:19 GMT
Organization: University of Pennsylvania

This is in response to the question about an integrated 680x0 with a
serial controller and MMU:

Try looking at Motorola's 683xx series.  I am only familiar with the 
68331, which include a 68000 kernal, two serial interfaces (async and sync),
a timer, various parallel I/O lines, and a really great "Systems Integration
Unit", which puts on chip much of the control logic which is usually in 
discrete logic or a PAL.

There are also the 68302 and the 68332; I'm not quite sure what is in these, 
but they one of them my have a MMU.


--
------------------------------------------------------------------------------
* Bradley S. Green				University of Pennsylvania   *
* green@eniac.seas.upenn.edu			(215) 222-7882		     *
*									     *
From: drchip@cup.portal.com (MYRON A LIEBERMAN)
Newsgroups: comp.sys.m68k
Subject: Re: Motorola in Arizona
Date: Wed, 15 Apr 92 22:03:58 PDT
Organization: The Portal System (TM)
  <1992Apr13.222106.26074@gvl.unisys.com>

Motorola has a number of facilities in Arizona. In the Phoenix area there
are semicinductor and Government Electronics facilities including sites in
Phoenix, Tempe, Mesa, Chandler, and Scottsdale. The original semicinductor
facility is located at 5005 E. McDowell Rd in Phoenix (85008, I believe). 
The addresses and descriptions of all of the other facilities should be
obtainable from there. In addition to these locations there are a number
of sales offices, etc in the Phoenix area. If you have a specific location
in mind I can try to give more precise details.
From: thad@public.BTR.COM (Thaddeus P. Floryan)
Newsgroups: comp.sys.m68k
Subject: Re: 680x0 vs 80x86
Date: 12 Apr 92 04:25:13 GMT
Organization: BTR Public Access UNIX, Mountain View CA

In article <73288@netnews.upenn.edu> green@eniac.seas.upenn.edu (Bradley Green ) writes:
>I am trying to decide between the Motorola and Intel processor series
>for a project.  I much prefer working with the Motorola systems, but 
>wonder about comparative performance.  My project involved mostly integer
>computations, so FPU performance is not very important.  Have any of you
>seen a valid-looking comparison between these processors?

From reading the above, I receive the impression you've already made up your
mind but that you'd like confirmation from others.

You clearly stated: "I much prefer working with the Motorola systems..."

Unless you're a masochist, use the good architecture!  :-)

Forget ``FUD'' (Fear, Uncertainty, and Doubt (the IBM/Intel policy)).

Remember that systems based on Intel (and VAX) computers violate even the
Internet standard Network Byte Order.  For example:

With a 680x0: a register value 0x12345678 appears in memory as 0x12345678

With a 80x86: a register (if you can find one! :-) value 0x12345678 appears
in memory as 0x78563412.

Intel is colloquially known in Silicon Valley as "First with the Worst".

Motorola chips inherently have an easy to use flat address space.

Intel chips have weird names for the modes you'd need to enable to achieve
flat addressibility ("protected" mode, and other such garbage due to their
compatibilty with the 8086 (methinks 8080, 8008 and 4004, too! :-))

Besides, as can be clearly shown with ANY test: Motorola chips consistently
whip Intel chips in performance.

Recent issues of UNIX REVIEW show 25MHz MC68040 systems over 50% faster than
33MHz i80486 systems with both integer and floating point performance.  You can
rescale those numbers for {68030 | 68020}:80386, {68020 | 68010}:80286, etc.

I design systems for a living, and had NO constraints placed on me as to what
chips to use.  After comparing what's available, Motorola consistently wins.

Of course, I have no use whatsoever for "DOS".  :-)

Be smart, use a Motorola chip; so what if it's not (ugh) "politically correct."

Thad Floryan [ thad@btr.com (OR) {decwrl, mips, fernwood}!btr!thad ]
From: ph11mlar@sbusol.rz.uni-sb.de (Arthur Recktenwald)
Newsgroups: comp.sys.m68k
Subject: How much is a 68030
Date: 16 Apr 92 09:36:37 GMT

Hello,

how much is a 68030 and a 68882 with 50 MHZ in the USA or (and) Germany.

Thanks.

Arthur

      /// Arthur Recktenwald        /// Z-Netz:  arthur@hit.zer         ///
     /// Voice:+49-(0)681-302-4217 /// Internet:arthur@lusi.uni-sb.de  ///   
    /// BTX: 0681581414-12        /// _             __    _           ///
\\\/// W-6620 V"olklingen 1   \\\/// /_\   /\/\  | | _   /_\      \\\///
 \XX/ Fed.Rep.of.Germany       \XX/ /   \ /    \ | |__| /   \ 2000 \XX/
From: jclark@sdcc3.ucsd.edu (John Clark)
Newsgroups: comp.sys.m68k
Subject: Re: RS-422 in 68000 system
Date: 9 Apr 92 18:28:36 GMT
Organization: University of California, San Diego

In article <ADAMS.92Apr8145405@PDV2.pdv2.fmr.maschinenbau.th-darmstadt.de> adams@pdv2.fmr.maschinenbau.th-darmstadt.de (Adams) writes:
+In article <73157@netnews.upenn.edu> green@eniac.seas.upenn.edu (Bradley Green ) writes:
+
+>   I'm trying to build an extremely inexpensive (to produce) single-board
+>   computer based on an 8 mHz 68000.  I need to get an RS-422 serial interface
+>   into this system, running at ~232Kbaud (AppleTalk speed, for interfacing with
+
+Fine, how about using Motorola's integrated micro controllers 683xx?
+There is at least one composed of a 68k kernel and an intelligent SCC
+(Serial Communication Controller). I would not be astonished if
+it could emulate LocalTalk (physical Layer of AppleTalk over twisted pair)
+in microcode....


On looking at the 68332 manual, several things come to mind, 1) how
to program the serial interfaces for synchronous protocols such as
SDLC and HDLC which requires the use of frame open flags, bit stuffing,
CRC generation. Another problem area is serial data encoding, LocalTalk
uses an FM mode and not 'NRZL', which is what the 68332 is
stated to support.
-- 

John Clark
jclark@ucsd.edu
Newsgroups: comp.sys.m68k
From: gudjm@uniwa.uwa.edu.au (D John McKenna)
Subject: Re: 8 Mhz. proc. at 4 MHz. ??
Organization: University of Western Australia
Date: Thu, 16 Apr 1992 04:17:31 GMT

joes@gvls2.gvl.unisys.com (Joe Schulingkamp) writes:

>Make sure of the duty cycle of your clock as well.  There are two other
>specs for clock high and clock low time.  You could have a real ugly 
>clock that violates at least one of those specs.  I don't have my 68000
>book handy right now.  Can anyone provide these numbers?

From the Good Book itself...

(listing 8MHz part specs only)
                 min    max
frequency            4      8     MHz
clock period         125   250    ns
clock low/high time  55    125    ns
clock rise/fall time       10     ns

The clock low time is from when the clock falls to below 0.8V to when it
rises above 0.8V. The clock high time is from when it rises above 2.0V
to when it falls below 2.0V. The rise/fall times are between 0.8V and
2.0V. There's a fair amount of slack in there, but still be careful with
the clock. In any case, I'm sure the chip can cope with worse specs than
this, but Motorola isn't going to guarentee it.

John West
-- 
gudjm@uniwa.uwa.edu.au  For the humour impaired: insert a :-) every 3 words
Newsgroups: comp.sys.m68k
From: joes@gvls2.gvl.unisys.com (Joe Schulingkamp)
Subject: Re: 8 Mhz. proc. at 4 MHz. ??
Organization: Unisys Defense Systems, Great Valley Labs, Paoli, Pa
Date: Wed, 15 Apr 1992 23:41:17 GMT

In article <1992Apr15.052459.12948@uniwa.uwa.edu.au> gudjm@uniwa.uwa.edu.au (D John McKenna) writes:
>>Hi, I am building a very simple 68000 based system. The design uses a 4 Mhz.
>>processor however, I have a couple of 8 MHz. chips available. To save cost :-)
>>is it possible to run the processor at 4 MHz. ? What sort of problems am I
>>likely to encounter ?
>
>I just had a look in my 68000 book, and it says that an 8MHz part will
>run perfectly happily at 4MHz (but not slower). The first 68k system I
>built ran at 4MHz, and I didn't have any problems with it. (Then I stuck
>a 16MHz into an 8MHz board, and it ran fine too. I think this is a
>general trend - you can run these beasties at half their rated speed,
>but not much slower)
>
>John West

Make sure of the duty cycle of your clock as well.  There are two other
specs for clock high and clock low time.  You could have a real ugly 
clock that violates at least one of those specs.  I don't have my 68000
book handy right now.  Can anyone provide these numbers?

Joe Schulingkamp,                | STRESS:   The confusion that is created when
joes@gvls2.GVL.Unisys.COM <-NEW! | one's mind overrides the body's basic desire
PARAMAX (UNISYS Defense Systems) | to choke the living SH-T out of some a--hole
Valley Forge Labs                | who desperately needs it.
Newsgroups: comp.sys.m68k
From: nerd@previous.rain.com (Michael Galassi)
Subject: Re: fast reversal of a bit field
Organization: Percy's mach, Portland, OR
Date: Wed, 8 Apr 1992 15:04:59 GMT

bnell@ferrari.siemens.com (Bill Nell) writes:

>Does anyone know a fast way of reversing the bits in a 16 or 32 bit
>number?  What I mean is if you start of with 011010 (for example)
>to change it to 010110.  Right know I am just doing a simple rol.l
>checking the carry flag and setting a bit in a temporary register
>with bset if the carry is set.  I'd like to know if anybody knows
>a faster way to do this (on a 68000).

The fastest way to do this is to use a lookup table,  I use this
all the time when I want to reverse 8 or 12 bit data, it gets
prohibitively large when you get to 16 or more bits.

; each element is the bit reversed patern of its index
brev_tbl:
.byte 0x00, 0x80, 0x40, 0xc0, ... ,0xaf , 0x7f, 0xff
; bit reverse 8 bit value in d0
brev8:
	move.l	a0,-(a7)
	lea	brev_tbl,a0
	move.b	(0,d0.b,a0),d0
	move.l	(a7)+,d0
	rts

If you have access to hardware you can wire up a couple of 74LS373s
back to back and get the same effect.  For more than 12 bit data this
is what I would recomend.

Sort of odd that I should tell you this since my company has to pay
yours royalty for some patents siemens holds which involve just this
code...

-michael
-- 
I won't take a stand on perl vs emacs	| Michael Galassi
'til I see /vmunix.pl or /vmunix.elc.	| nerd@percival.rain.com
From: jfw@ksr.com (John F. Woods)
Newsgroups: comp.sys.m68k
Subject: Re: Pure Segmentation on 68K's
Date: 13 Apr 92 12:15:36 EDT

icsu8209@cs.montana.edu (Glassy) writes:
>A beginner question on the 680[234]0 architecture:
>Does Motorolla make any MMU chips that do or can use pure segmentation
>for managing memory?
>I don't mean the restricted form of segmentation used in Intel's
>earlier products, nor do I mean "segmentation with paging", the common
>modern approach where a segment is made of fixed-size pages.
>I've heard of the 68451 (is that the #?) MMU, but thought it was a
>paging-oriented unit.

I'm pretty sure '451 is the number of the segmented MMU ('851 is the PMMU).
It was never too popular, and I wouldn't be surprised if Moto wasn't making
it any more (in fact, I wouldn't be too surprised if the architect hadn't been
taken out into the parking lot and machine-gunned... :-).

>What motivates the queston, is that I'd like do some fiddling with pure
>segmentation (segments of arbitrary size) and OS's...

The '451 required segments to be a power-of-two length, and you got a fairly
small number of them.

[My apologies to the architect of the '451, who almost certainly wasn't
machine-gunned and no doubt had very good reasons for why it came out the
way it did.]
Xref: sparky comp.sys.m68k:573 misc.wanted:5069
From: rflukes@ccu.umanitoba.ca (Richard F. Lukes)
Newsgroups: comp.sys.m68k,misc.wanted
Subject: WANTED: cheap source of M68332 CPUs
Date: 14 Apr 92 21:50:49 GMT
Distribution: na
Organization: University of Manitoba, Winnipeg, Canada

I am looking for a cheap source of M68332 CPU chips (quad flat packs)
for a University project.  The cheapest price locally is $75 CAN with a
two piece minimum.  If anyone knows of a cheaper source of these chips
(used chips would be OK) please e-mail me.  Depending on price,  I could
use about half-a-dozen.

Thanks in advance,
                    Rich
-- 
Richard F. Lukes                    rflukes@ccu.UManitoba.CA
Computer Science Department         (or rflukes@ccm.UManitoba.CA)
University of Manitoba
WORK: (204)-474-8696                HOME: (204)-257-6701
Newsgroups: comp.sys.m68k
From: spiff@iti.org (Jason Leigh)
Subject: Motorola in Arizona
Organization: Electronic Visualization Lab
Date: Mon, 13 Apr 1992 05:11:00 GMT

Hi,
	does anyone know where Motorola is in Arizona?  I.e. the city, and/or
county?  Or perhaps an email address to them.

Please reply to: spiff@bert.eecs.uic.edu
Thanks.

Jason Leigh

--
---------------------------------------------------------  ___
| The opinions expressed above are necessarily those of | \\     \\  | \\
| the Electronic Visualization Laboratory, NOT!         |  \\---  \\ |  \\
| Send Replies to: spiff@bert.eecs.uic.edu (Jason Leigh)|   \\____ \\|   \\____
Newsgroups: comp.sys.m68k
From: meulenbr@cst.prl.philips.nl (Frans Meulenbroeks)
Newsgroups: comp.sys.m68k
Subject: 68040 mmu problem
Date: 9 Apr 92 11:18:58 GMT

Hi!

I'm currently writing operating systems code (for MINIX) so that the
kernel can use the protection and relocation of the 68030 mmu.
Note that it is not yet my intention to do full paging, since the
current design of minix does not really support this, and I also do not
know very well how to deal with the page tables for different processes.

Therefore I decided to use early termination page descriptors with the
protection offered by that. Using 4 k pages and tia = 5, tib = 15
(tic and tid unused), I could allocate memory with early termination
without writing out the page tables. In fact if the amount of memory
needed is less than 128 MB, I can get away with only one early
termination descriptor on the tia level.

Fine. No problem yet. Everything turns fine.
Then I decided to rework my code, so that it also could be used on
68040 systems. I obtained the 68040 user manual (thanks to everyone who
told me how to get one!) and studied chapter 6.
However, it seems that the 68040 does not support early termination
page descriptors any more. 

This brings me to my question:
Is there another way to relocate a piece of memory (starting at virtual
address 0, and ending on a 4k boundary) without losing protection and
without reserving a lot of space for page tables?

If I have to go to page tables anyway, does someone have info or a
pointer to info on how to do so without wasting a lot of memory.
It is my intention to make a flexible system which would use its memory
economically even if memory is scarce (e.g. a 4 MByte system).

Thanks!


--
Frans Meulenbroeks        (meulenbr@prl.philips.nl)
	Philips Research Laboratories
From: thad@public.BTR.COM (Thaddeus P. Floryan)
Newsgroups: comp.sys.m68k
Subject: Re: MC68681 DUART help
Date: 6 Apr 92 10:43:11 GMT
Organization: BTR Public Access UNIX, Mountain View CA

In article <1992Apr6.074628.25008@cs.ubc.ca> sritchie@cs.ubc.ca (Stuart Ritchie) writes:
>I'm writing an interrupt driver for the MC68681 DUART (residing
>on a MVME188 Hypermodule).
>[...]
>[...]  Surely I don't need
>to disable the transmitter when I have nothing to transmit, do I?
>[...]

Yes, you do.

I've been using the MC68681 since 1984, and that's the way one does it.
Simply maskout the XMIT interrupt bit and (re)set the IMR (Interrupt Mask
Register).

'Tis easy to detect that state and it makes sense.

All the Moto ACIA, on-board UARTS, MC68681, etc work that way, and it IS
logical when you think about it.

If you based your statement about the MC68681 having a "problem" based on
your experiences with Intel parts, please consider:

	- Intel in known in Silicon Valley as "First with the Worst"
	- Their parts aren't all that good (ref. "brain damage architecture")
	- Intel cannot even get their Ethernet chips working at a high
	  data rate (ref. their 82586 per a recent net posting by Van
	  Jacobson).

The MC68681 is a "Damn Fine Chip" (tm) and I've used tens of thousands of them
in my commercial products.  Not one problem EVER.

In fact, and this really blew away some Motorola engineers when they saw
one of my designs, I've even used the MC68681 on MC6803- and MC6809-based
systems at bauds up to 38400 (again, with not a single problem).

Thad Floryan [ thad@btr.com (OR) {decwrl, mips, fernwood}!btr!thad ]
From: jclark@sdcc3.ucsd.edu (John Clark)
Newsgroups: comp.sys.m68k
Subject: Re: RS-422 in 68000 system
Date: 8 Apr 92 17:06:54 GMT
Organization: University of California, San Diego

In article <73157@netnews.upenn.edu> green@eniac.seas.upenn.edu (Bradley Green ) writes:
+I'm trying to build an extremely inexpensive (to produce) single-board
+computer based on an 8 mHz 68000.  I need to get an RS-422 serial interface
+into this system, running at ~232Kbaud (AppleTalk speed, for interfacing with
+Mac's).  My question is this: What hardware (UART chip) will most easily

The Apple uses the 8530 serial chip from Zilog or AMD.
It is a piece of junk, but it is ubiquitus in applications which
require both async and sync operation. (I.e. it seems to be the only
cheap solution for both problems).
-- 

John Clark
jclark@ucsd.edu
Newsgroups: comp.sys.m68k
From: sritchie@cs.ubc.ca (Stuart Ritchie)
Subject: MC68681 DUART help
Organization: Computer Science, University of B.C., Vancouver, B.C., Canada
Date: Mon, 6 Apr 92 07:46:28 GMT

I'm writing an interrupt driver for the MC68681 DUART (residing
on a MVME188 Hypermodule).

It looks like the TxRDY interrupt is constantly asserted (my
interrupt handler is being constantly invoked with this
condition).  I cannot seem to ack this interrupt and cause
it to cease.  Reading the interrupt status register does
not seem to acknowledge the interrupt.  Surely I don't need
to disable the transmitter when I have nothing to transmit,
do I?

RxRDY interrupts work fine.

I have programmed other DUART's and have never had this
problem.

Knowing my luck it's probably some bug totally unrelated
to the piece of code I'm working on....

Stuart
From: kc@dcs.ed.ac.uk (Kenneth Cameron)
Newsgroups: comp.sys.m68k
Subject: Re: fast reversal of a bit field
Date: 8 Apr 92 14:20:45 GMT
Reply-To: kc@dcs.ed.ac.uk (Kenneth Cameron)
Organization: Laboratory for the Foundations of Computer Science, Edinburgh U


Off the top of my head -

If you are prepared to trade space for speeed, use a look up table. Not a
16 or 32 bit table, just an 8 bit and some code to build up 16 and 32.
Something like:


* reverse bits in d0 16 bits into d1. d0,a0 and d1 modified.
switch16:	lea.l	lookup(pc),a0	* get address of look up table
		eor.w	d1,d1		* clear all the bits
		move.b	d0,d1		* get low 8 bits of 16 number
		move.b	(a0,d1.w),d1	* look up reversed pattern
		lsl.w	#8,d1		* shift to upper 8 bits
		lsr.w	#8,d0		* shift down inital upper bits
		or.b	(a0,d0.w),d1	* reverse them, and combine result
		rts
* reverse bits in d0 32 bits into d1 d0,d2,d3,a0, and d1 modified
switch32:	move.w	d0,d2		* save upper bits for latter
		bsr	switch16	* reverse lowet bits
		move.w	d1,d3		* save result
		swap	d3		* put in right place
		move.l	d2,d0		* get upper bits
		swap	d0		* put in lower bits (maybe use swap)
		bsr	switch16	* reverse them
		or.l	d3,d1		* combine halfs
		rts
lookup:		dc.b	* 256 (8bit)entries with bits reversed 0,128,64,etc

There are probably bugs in this (I typed it straight in, never a good idea.).
But you get the idea.
,Kenneth.

--
Kenneth@Edinburgh
From: j_wilson@csd.brispoly.ac.uk (Hi how are you)
Newsgroups: comp.sys.m68k
Subject: 8 Mhz. proc. at 4 MHz. ??
Date: 14 Apr 92 19:05:54 GMT
Organization: Bristol Polytechnic, England

Hi, I am building a very simple 68000 based system. The design uses a 4 Mhz.
processor however, I have a couple of 8 MHz. chips available. To save cost :-)
is it possible to run the processor at 4 MHz. ? What sort of problems am I
likely to encounter ?
Thanks a lot,
Jamie.

###############################################################################
#  Jamie Wilson.              E-Mail : j_wilson@csd.brispoly.ac.uk (internet) #
#  3 Lower Grove Rd,                   j_wilson@uk.ac.brispoly.csd (JANET)    #
#  Fishponds,                          j_wilson@cv.brispoly.ac.uk  (internet) #
#  Bristol.                            j_wilson@uk.ac.brispoly.cv  (JANET)    #
#  BS16 2BS.                           Voice : +44 272 651071                 #
#  England.                                                                   #
###############################################################################
From: adonkin@waikato.ac.nz
Newsgroups: comp.sys.m68k
Subject: Info on 050/060 please?
Date: 7 Apr 92 14:08:23 +1200
Organization: University of Waikato, Hamilton, New Zealand

	If anyone has any information on the new 050 or 060, please mail me as
I require as much as possible for a report on the later members of the 68000
family.  Anything from hard facts to loose rumours accepted and appreciated.

	Thanks in advance - Andrew.
From: misch@rbhp90.rbg.informatik.th-darmstadt.de (Clemens Misch)
Newsgroups: comp.sys.m68k
Subject: Re: MIPS/MFLOPS ratings
Date: 7 Apr 92 08:39:12 GMT
Reply-To: misch@rbhp90.rbg.informatik.th-darmstadt.de
Organization: Rechnerbetriebsgruppe FB20; TH Darmstadt (Germany)
Originator: misch@rbhp90.rbg.informatik.th-darmstadt.de


In article <n95H7crj6@cs.psu.edu>, melling@cs.psu.edu (Michael D Mellinger) writes:
> 
> In article <1992Apr06.082507.20807@infoserver.th-darmstadt.de> misch@rbhp90.rbg.informatik.th-darmstadt.de (Clemens Misch) writes:
> 
>    In article <Adr7iji00WB8Mn3Whx@andrew.cmu.edu>, rh2y+@andrew.cmu.edu (Russell E. Hoffman, II) writes:
>    > From several people:
>    > 
>    > Oh, and for any interested parties, I have heard tell of a 68040 OS9/68000
>    > box doing just over 26,000 dhrystones/sec.
>    > 
>    FYI, here are the ratings for a HP 9000/400t, 68040 25Mhz:
>    Dhrystone 2.1 (C-Language)
> 
> 	   cc -O -DREG=register:    ~30000	(HP's C_MIN compiler)
> 	   gcc -O -DREG=register:   ~28800	(gcc 2.1)
> 
>    The difference is due to superior loop-unrolling in the native cc. If
>    you leave out -O then the ratings drop to about 17000 dhrystones/sec.
> 
> 
> Could someone try gcc -O2 -funroll-loop?  GCC 2.0 does do loop
> unrolling but it needs to be mentioned specifically.

This does no difference. Gcc cannot unroll loops of a certain kind
e.g:

static int x;
....
proc()
{
....
for(i=x; i<x+k; ++i)
	<statement>
}

Gcc cannot unroll this loop. Proc_8 in dhrystone has this loop so
there is no speed gain with -funroll-loops
-- 
===============================================================================
Clemens Misch                                        Rechnerbetriebsgruppe FB20
                                                     Merckstrasse 25 
EMail: misch@rbhp90.rbg.informatik.th-darmstadt.de   W6100 Darmstadt (Germany)
Tel.: +49 6151 163514
===============================================================================
-- 
===============================================================================
Clemens Misch                                        Rechnerbetriebsgruppe FB20
                                                     Merckstrasse 25 
EMail: misch@rbhp90.rbg.informatik.th-darmstadt.de   W6100 Darmstadt (Germany)