From: div@nad.3com.COM (Dinesh Venkatachalam x5498)
Subject: Follow up for my bug report on BISON
Organization: GNUs Not Usenet
Distribution: gnu
Date: Thu, 27 Aug 1992 01:27:19 GMT

Version of Bison: char *version_string="GNU Bison version 1.11\n";

I had sent the "parser.y" file with lines stripped out to remove errors.
Here is the file which produces the errors

----------------------- parser.y -----------------------------------
/*
      Lex + Yacc
*/
%{
#define YYDEBUG 1
#include <string.h>
#include <ctype.h>
#include <errno.h>
#include <stdio.h>
#include <fcntl.h>

#define out(c) putc(c,yyout)
#define NCOM 300

int	bug=0, ind ;
FILE 	*fopen(), *freopen(), *fi, *ft, *fo, *fr ;
static 	int i, comment=0;
char  	*cp, *st, refd[20], part[20] ;
char	ln[80] ;

/* yydebug = 1; *//* div */

extern char 	*strsave(), *malloc();
extern int	yyleng, lexval ;

/* Use this or union below */

typedef struct YYS_TYPE {
    int i;
    char s[50];
    } yys_type ;
#define YYSTYPE     yys_type

/*
typedef union 
{
    int i;
    char s[50];
} YYSTYPE;
*/

%}

%token NL NAME NUMBER MODULE ENDMODULE WIRE INPUT OUTPUT INOUT
%token NETTYPE ASSIGN STRENGTH0 STRENGTH1 GATETYPE INIT
%token PARAMETER REG TIME INTEGER REAL EVENT DEFPARAM
%token BIN_OP UNARY_OP PRIMITIVE ENDPRIM TABLE ENDTABLE
%token OUT_SYM LEV_SYM EDGE_SYM
%token TEXT TASK ENDTASK ALWAYS CONSTANT /* div */
%token FUNCTN ENDFUNCTN BEGINS END IF ELSE CASE CASEX CASEZ FOREVER REPEAT
%token WHILE FOR WAIT POINTAT DISABLE DEASSIGN FORK JOIN 
%token DEFAULT ENDCASE LOGICAL_OP SPECIFY POSEDGE NEGEDGE /* div */

%right '='
%left BIN_OP
%nonassoc LOGICAL_OP

%start modules        /* Start Here */

%%

/* error modified */
modules 	: modules mod_prim
                | modules         error ';'
		|      	  mod_prim
		;

mod_prim	: module
		| primitive
		;

primitive	: PRIMITIVE NAME '(' list_of_vars ')' ';' prim_body ENDPRIM
		;

list_of_vars	: list_of_vars ',' NAME
		| NAME
		;

prim_body	: UDP_decl UDP_init table_def
		| UDP_decl          table_def
		;

UDP_decl	: output_decl
		| input_decl
		| reg_decl
		;

UDP_init	: INIT NAME '=' init_val
		;

init_val	: '1' '\'' 'b' '0'
		| '1' '\'' 'b' '1'
		| '1' '\'' 'b' 'x'
		| '1'
		| '0'
		;

table_def	: TABLE table_entries ENDTABLE
		;

table_entries	: table_entries combin_entry
		|               combin_entry
		| table_entries seq_entry
		|               seq_entry
		;

combin_entry	: level_in_list ':' OUT_SYM ';'
		;

seq_entry	: level_in_list ':' state ':' next_state ';'
		|  edge_in_list ':' state ':' next_state ';'
		;

/* LEX MUST PUT OUT Tokens for OUT_SYM LEV_SYM and EDGE */

level_in_list 	: LEV_SYM
		;

edge_in_list	: LEV_SYM edge LEV_SYM
		|         edge
		;

edge		: '(' LEV_SYM LEV_SYM ')'
		| EDGE_SYM
		;

state		: LEV_SYM
		;
next_state	: OUT_SYM
		;
/* div */
module		: MODULE NAME '(' list_of_ports')' ';' mod_body ENDMODULE  
                       { strcpy(modnam,$1.s); }
                | MODULE NAME ';' mod_body ENDMODULE 
                       { strcpy(modnam,$1.s); }
                ;

/* It can also be .name_of_port(port_ref) */
                
list_of_ports	: list_of_ports ',' port 
		| port
		;

port		: NAME
		| NAME '[' const_exp ']'
		| NAME '[' const_exp ':' const_exp ']'
		;

mod_body	: mod_body module_item 
		|          module_item 
		;

module_item	: param_decl
		| input_decl
		| output_decl
		| inout_decl
		| net_decl
		| reg_decl
		| time_decl
		| integer_decl
		| real_decl
		| event_decl
		| gate_decl
		| module_instant
		| defparm_decl
		| cont_assign
                | specify_blk
                | initial_blk
                | always_blk
                | statements
                | task
                | functn
                | error ';'
		;


/* -----------------  Verilog A.2 Declarations ------------------ */

input_decl	: INPUT       list_vars ';'
		| INPUT range list_vars ';'
		;

output_decl	: OUTPUT       list_vars ';'
		| OUTPUT range list_vars ';'
		;

inout_decl	: INOUT       list_vars ';'
		| INOUT range list_vars ';'
		;

/* param vars */
param_decl	: PARAMETER       param_list ';'
                | PARAMETER range param_list ';'
		;

param_list      : param_list ',' param_eq
                |                param_eq
                ;

param_eq        : NAME '=' name_or_const
                ;

name_or_const   : NAME
                | CONSTANT
                ;

reg_decl	: REG list_vars ';'
                | REG range list_vars ';'
		;

/* time vars */
time_decl	: TIME list_vars ';'
		;

/* integer vars */
integer_decl	: INTEGER list_vars ';'
		;

/* real vars */
real_decl	: REAL list_vars ';'
		;

/* event NAME -> multiple events ? */
event_decl	: EVENT NAME ';'
		;

/* ??? */
defparm_decl	: DEFPARAM
		;
/* -----------------  Verilog A.3 Primitive Instances ------------------ */

/*
   Expand LEX GATETYPE
   LEX has to pass strength info also
*/
gate_decl	: GATETYPE                   gate_instant
		| GATETYPE dr_strength       gate_instant
		| GATETYPE             delay gate_instant
		| GATETYPE dr_strength delay gate_instant
		;

delay		: '#' number
		| '#' NAME
		;

dr_strength	: '(' STRENGTH0 ',' STRENGTH1 ')'
		| '(' STRENGTH1 ',' STRENGTH0 ')'
		;

gate_instant	: NAME '(' exp ')'
		;

net_decl	: NETTYPE             list_vars ';'
		| NETTYPE range       list_vars ';'
		| NETTYPE       delay list_vars ';'
		| NETTYPE range delay list_vars ';'
		;

range		: '[' const_exp ':' const_exp ']' 
		;

list_vars	: list_vars ',' NAME '[' NUMBER ']'
                | list_vars ',' NAME 
		|               NAME '[' NUMBER ']'
    	    	|               NAME
		;

/* -----------------  Verilog A.4 Module Instantiations ------------- */

module_instant	: name_mod         mod_inst_list ';' 
              	| name_mod par_val mod_inst_list ';' 
                | name_task                      ';'
		;

name_mod	: NAME
		{ strcpy( part, yytext); }
		;

name_task       : NAME
                ;

mod_inst_list	: mod_inst_list ',' mod_inst
		|                   mod_inst
		;

/* The 3rd definition is for task calls  */

mod_inst	: reference '(' list_mod_conn ')'
        	| reference '(' list_nam_conn ')'
                |           '(' list_vars     ')'
		;

reference	: NAME
		{ strcpy( refd, yytext); }
		;

list_mod_conn	: list_mod_conn ',' exp
		|                   exp
		;
 
list_nam_conn	: list_nam_conn ',' nam_conn
		|                   nam_conn
		;
 
nam_conn	: '.' NAME '(' sig_nam ')'
		{
		    fprintf(fo,"%-18s %-22s %-10s %10s %s\n",
			 $4.s, refd, $2.s, part, modnam);
		    fprintf(fo,"Dollar Num %s %s %s %s %s\n",
			 $1, $2, $3, $4, $5);
		    fprintf(fo,"Dollar Num Dot S %s %s %s %s %s\n",
			 $1.s, $2.s, $3.s, $4.s, $5.s);
		    fprintf(fo,"Dollar Dollar %s\n",
			 $$);
                    fprintf(fo,"------------------\n");
    
		}
		;

sig_nam		: NAME
		| NAME '[' exp ']'
		{ strcpy($$.s, $1.s);
		  strcat($$.s, "[");
		  strcat($$.s, $3.s);
		  strcat($$.s, "]");
		}
		| NAME '[' exp ':' exp ']'
		{ strcpy($$.s, $1.s);
		  strcat($$.s, "[");
		  strcat($$.s, $3.s);
		  strcat($$.s, ":");
		  strcat($$.s, $5.s);
		  strcat($$.s, "]");
		}
		| concatenation
		{ strcpy($$.s, "concatenation");}
		;

par_val		: '#' '(' exp ')' 
		;

cont_assign	: ASSIGN                   list_assigns ';'
		| ASSIGN dr_strength       list_assigns ';'
		| ASSIGN             delay list_assigns ';'
		| ASSIGN dr_strength delay list_assigns ';'
		;

list_assigns	: list_assigns ',' assignment
		|                  assignment
		;

assignment	: lvalue '='     exp
		| lvalue '=' '(' exp ')'
		;

lvalue		: NAME
		| NAME '[' exp ']'
		| concatenation
		;

const_exp	: exp
		;

concatenation	: '{' exp_list '}'
		;

exp_list	: exp_list ',' exp
		|              exp
		;
	 
exp		: primary
                | UNARY_OP primary
		| UNARY_OP '(' exp ')'
		| exp BIN_OP exp
                | exp LOGICAL_OP '=' exp
                | exp LOGICAL_OP exp
		;

primary		: number
                | CONSTANT
		| NAME '[' exp ']'
		| NAME
		| concatenation
		;

number		: NUMBER
		| NUMBER '\'' 'b' NUMBER
		| NUMBER '\'' 'd' NUMBER
		| NUMBER '\'' 'o' NUMBER
		| NUMBER '\'' 'B' NUMBER
		| NUMBER '\'' 'D' NUMBER
		| NUMBER '\'' 'O' NUMBER
		;

/* Other stuff to complete and debug */

specify_blk     : SPECIFY BEGINS statements END
                ;


/* ----------------- Verilog A.5 Behavioural Statements --------------------------- */

initial_blk       : INIT statements
                  ; 

always_blk        : ALWAYS event_control statements
                  ;

event_control     : '@' '(' edge_expr ')'
	          ;

edge_expr         : edge_expr GATETYPE rest_of_edge
                  |                    rest_of_edge
                  ;

rest_of_edge      :          POSEDGE NAME
                  |          NEGEDGE NAME
                  |                  NAME
                  ;

                  | 
bool_expr         : UNARY_OP primary LOGICAL_OP bool_expr
                  |          primary LOGICAL_OP bool_expr
                  |          primary UNARY_OP '=' primary
                  |          primary '=' '=' primary
                  | UNARY_OP primary
                  | UNARY_OP                '(' bool_expr ')'
                  |          primary 
                  ;

statements        : statements single_stmt
    	          |            single_stmt
                  ;
    
single_stmt       : assignment ';'
    	    	  | if_exp
                  | else_exp
                  | case_exp
    	    	  | seq_block
    	    	  | par_block
                  | forever_stmt
                  | repeat_stmt
                  | while_stmt
                  | for_stmt
                  | delay_stmt
                  | event_control
                  | wait_stmt
                  | pointat_event
                  | system_task_stmt
                  | disable
                  | null
                  ;

null              :  ';'
                  ;

if_exp	    	  : IF '(' bool_expr ')' statements 
                  ;

/* not needed     | IF '(' bool_expr ')' ';' */
/*                | IF '(' exp ')' statements */
/*                | ELSE IF '(' bool_expr ')' statements */

else_exp          : ELSE statements
                  ;

case_exp          : CASE  '(' exp ')' case_item ENDCASE
                  | CASEZ '(' exp ')' case_item ENDCASE
                  | CASEX '(' exp ')' case_item ENDCASE
                  |                   error     ENDCASE
	          ;
    
case_item         : case_body
                  | DEFAULT ':' statements
                  ;

case_body         : exp ':' statements exp ':' statements
                  |                    exp ':' statements
                  ;

seq_block   	  : BEGINS          statements END
    	    	  | BEGINS ':' NAME statements END
                  |                 error      END
                  ;

par_block         : FORK          statements JOIN
    	    	  | FORK ':' NAME statements JOIN
                  |               error      JOIN
                  ;

forever_stmt      : FOREVER statements
                  ;
repeat_stmt       : REPEAT '(' exp ')' statements
                  ;

while_stmt        : WHILE '(' exp ')' statements
                  ;

for_stmt          : FOR '(' assignment ';' exp ';' assignment ')' statements
                  ;
delay_stmt        : '#' NUMBER NAME '=' NAME ';'
                  ;

wait_stmt         : WAIT '(' NAME ')' ';'
                  ;

pointat_event     : POINTAT NAME ';'
                  ;

system_task_stmt  : '$' NAME ';'
                  ;

disable           : DISABLE NAME ';'
                  ;

task             : TASK NAME ';' task_body ENDTASK
                 ;

task_body        : NAME NAME
                 ;



functn         : FUNCTN NAME ';' function_body ENDFUNCTN
               ;

function_body  : NAME NAME
               ;


    
%%	/* start of main */

#include "lex.yy.c"  /* extern int  yylex(); */


main(argc,argv)
int	argc;
char	*argv[];
{
    int	i,p;
    char frnam[60], fsnam[60];

    if(argc == 1) {
	fprintf(stderr,"use:hdl [-ds] file\n"); exit(1);
    }
    for(i=1; i<argc; i++)
    	if(argv[i][0] == '-'){
		bug     = ((argv[i][1] == 'd') || (argv[i][2] == 'd'));
	}
	else break;


    if(freopen( argv[i],"r",stdin) == NULL){
	fprintf(stderr,"can't open %s\n", argv[i]);exit(1);
    }	else {
	/* open output */
	for( cp=argv[i], st=fsnam ; *cp && *cp != '.' ; )*st++ = *cp++;
	*st = 0;
	strcpy( frnam, fsnam );	
	strcat( frnam, ".nam");	strcat( fsnam, ".seq");

	if((fo = fopen(fsnam, "w")) == NULL) err("can't open %s",fsnam);

	fprintf(stderr,"reading nets from %s\n", argv[i]);
    }

    yyparse() ;
	
    fclose(fo);

    fprintf(stderr,"sorting...\n");
    sprintf(ln, "sort <%s >%s", fsnam, frnam);	system(ln);
}

int     yyleng ;

char    yytext[YYLMAX];

char    yysbuf[YYLMAX];

/* char    modnam[YYLMAX]; */

char    modnam[20];

int      yylast, toklast;

extern char *yysptr;
extern int yylineno;
extern FILE *yyout;

#define YYNL 10


err(s,t)
    char *s,*t;

{

    fprintf(stderr,s,t);
    fprintf(stderr,"\n");

    exit(1);

}

yyerror(s)    char *s;

{
    fprintf(stderr,"%s error on line %d\n",s,yylineno);

}



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