HDTenEightyP/NetNews huggingface dataset:
From: cspidoug!cspidoug (Doug Johnson - CSPI Mission Viejo, CA)
Newsgroups: comp.dsp
Subject: Re: REQ: Info re: vendors for multi-  320C40 boards
Keywords: DSP, i860 Vector Processor, VME
Date: Wed, 02 Sep 92 17:13:44 PDT
Distribution: World
Organization: CSP,Inc - The Array Processors

I do not know of any vendors currently offering multi-prcessor
boards based on the 320C40. However, if you are interested in the
i860, CSP, Inc. of Billerica, MA has introduced a Quad i860, 6U
VME64 processor.  It provides 320 MFLOPS performance, and offers
four independent processors.  The programming environment is "C"
and support the Metaware High "C" i860 cross compiler.  Over
300 hand-coded library functions are available.

If you would like more information, please call at (714)-472-4301 or
send mail to Doug Johnson at Email: universal!doug@ucsd.edu

Thanks,
Newsgroups: comp.dsp
From: morrow@cns8.ucalgary.ca (Bill Morrow)
Subject: Re: Bugs in 68HC16 project - REPOST
Date: Wed, 26 Aug 92 17:07:29 GMT
Organization: cns

In article <92Aug26.161018.14929@acs.ucalgary.ca>, morrow@cns.ucalgary.ca (Bill Morrow) writes:
|> He is having problems with the IIR filter section. I seem to remember
|> some comments about there being typos in the instruction manual, or
|> bugs in the code. If so, could someone mail the corrections to me?
|> 
Sorry, the first part of my post disappeared.
The 'He' above refers to a colleague without net access. He is building the
HC16 development project 5-channel filter. His IIR filter seems to be 
saturating, so I'm wondering if there is a mistake in the instructions.

Just for interests sake, does the HC16 use the same fixed point arithmetic
as in the 56K? I have some experience using the 56K, but none with the HC16.
__________________________________________________________
Bill Morrow                    voice: (403) 220-6275
Clinical Neurosciences         fax: (403) 283-8770
University of Calgary          e-mail: morrow@cns.ucalgary.ca
3330 Hospital Drive NW
Calgary, Alberta, CANADA
T2N 4N1
From: wjs@re3sc139h.gmr.com
Newsgroups: comp.dsp
Subject: REQ: Info re: vendors for multi-  320C40 boards
Date: 1 Sep 92 17:21:23 GMT
Organization: Electronic Data Systems Corp. - Test Engineering

I apologize if this request has already been posted.

I need a list of third party vendors for the TI 320C40 chip.
Especially those that may have VME based multi-processor
configurations.

Any information on good C and Fortran compilers for this 
chip would be welcome also.

			  Thanks in advance,

			  W. Stuart   wjs@re3sc139h.gmr.com
Newsgroups: comp.dsp,comp.compression
From: enis@faline..bellcore.com (A. Enis Cetin)
Subject: LPC10e document
Summary: vocoder 
Keywords: DSP, voice coder
Reply-To: enis@faline.UUCP (xxxx)
Organization: Bellcore MRE
Date: Thu, 3 Sep 92 20:49:11 GMT

I am looking for 

D.P.Kemp, et. al., "LPC-10e Enhanced LPC-10 Voice coder, 
Phase 1 Report,"
National Security Agency, document number R163-84-01", 
March 4, 1985.

Is there an Ftp site where this document can be obtained.

Thanks in advance.
Enis
Newsgroups: comp.dsp
From: knud@enel.ucalgary.ca (Steve Knudsen)
Subject: Help sought for chirp filter.
Summary: deign references, nonlinear filters, radar
Date: Wed, 26 Aug 92 23:03:53 GMT
Distribution: na
Organization: ECE Department, U. of Calgary, Calgary, Alberta, Canada

Hello,

I'm looking at extracting a chirp-like sequence in a
very low noise situation. I have estimates of the
chirp frequency and frequency rate to base the
design on. If anyone has any useful code, notes,
references, etc., I would much appreciate them.
I have started a lit. search and have some books
that may help (mostly radar and time-varying system
books).

Please email reponses to knud@enel.ucalgary.ca
If enough interest is apparent, I'll summarize the
responses

Thanks,

Steven Knudsen

-- 
K. Steven Knudsen                     | The lasers are in the labs, the old
University of Calgary                 | man is dressed in white clothes.
Department of Electrical Engineering  | Everybody says that he's mad - 
knud@enel.ucalgary.ca                 | Nobody knows the things that he knows.
Newsgroups: comp.dsp
From: sassoj@aix.rpi.edu (John J. Sasso Jr.)
Subject: NEED WAVELET APPLICATIONS INFO. FOR...
Organization: Rensselaer Polytechnic Institute, Troy NY
Date: Fri, 28 Aug 1992 04:24:53 GMT

  Does anyone know of any articles on the applications of wavelets to sound,
such as audio compression, etc.?  Also, any articles on the applications of
wavelets to biomedical engineering, such as EKG, EEG, ECG, etc.?  Any info
is appreciated.

                     John Sasso


Newsgroups: comp.dsp
From: mlelstv@speckled.mpifr-bonn.mpg.de (Michael van Elst)
Subject: Re: Finding how much DSP56001 RAM is installed via program??
Organization: Max-Planck-Institut f"ur Radioastronomie
Date: Thu, 27 Aug 1992 12:43:24 GMT

In <1992Aug26.134637.5838@leland.Stanford.EDU> bil@cmn16.Stanford.EDU (Bill Schottstaedt) writes:
>I believe the program does not fail because the out-of-range NeXT DSP
>external memory addresses are mapped back onto lower addresses.
>For example, on an 8K dsp, an address like X:$B001 actually
>writes to X:1 (external, of course = $A001).  This makes it
>harder to figure out how much memory is actually out there.

Yep, this is hard to find. If however you know what can be at the
different addresses you can test for these shadowed RAM areas.

My favourite RAM address checker fills the memory with a series of
pseudo-random numbers and checks then against the same series. Any
addressing fault or shadowing (happens when address lines are shorted as
well) will most probably be detected. Of course you need a random
number generator with a period larger than your memory :-)

Regards,
-- 
Michael van Elst
UUCP:     universe!local-cluster!milky-way!sol!earth!uunet!unido!mpirbn!p554mve
Internet: p554mve@mpirbn.mpifr-bonn.mpg.de
                                "A potential Snark may lurk in every tree."
From: alexo+@cs.cmu.edu (Alex Orenshteyn)
Newsgroups: comp.dsp
Subject: Sliding FFTs
Date: 26 Aug 92 00:02:00 GMT
Article-I.D.: cs.BtKDFF.15u.1
Organization: School of Computer Science, Carnegie Mellon

Is anyone out there using sliding Fourier Transform for real world
problems? If so, can you give some idea about the applications are.
Also, are you using any method to keep loss of precision to the minimum?

Thanks.
From: phil@tukey.berkeley.edu (Phil Lapsley)
Newsgroups: comp.dsp
Subject: "Mwave" DSP real-time OS?
Date: 27 Aug 1992 22:17:03 GMT
Organization: U.C. Berkeley -- ERL
Distribution: world
NNTP-Posting-Host: tukey.berkeley.edu

Can anyone tell me something about "Mwave", which is alleged to be
a real-time OS for DSPs?  (Or maybe just a real-time OS for general
purpose microprocessors).  Thanks.

Phil Lapsley		phil@ohm.Berkeley.EDU		...!ucbvax!phil
From: ame@matt.ksu.ksu.edu (Abdulrahman M El-Koubysi)
Newsgroups: comp.dsp
Subject: Request for information on applications that need EMI shielding
Date: 31 Aug 1992 13:09:02 -0500
Organization: Kansas State University
NNTP-Posting-Host: matt.ksu.ksu.edu
Summary: Need to find applications that could benefit from EMI shielding
Keywords: EMI, Shielding


I am trying to put together a list of applications that could possibly use
some shield from low frequency electromagnetic interference (EMI). Dose 
anybody out there know of an application that could be improved if shielded from
EMI????


A. R. El-Koubysi          | Internet: ame@matt.ksu.ksu.edu
College of Engineering    | Bitnet  : ame@ksuvm
147, Seaton Hall, KSU     | Phone   : (913) 532-5580 
Manhattan, KS 66506       | Fax     : (913) 532-6944
From: cspidoug!cspidoug (Doug Johnson - CSPI Mission Viejo, CA)
Newsgroups: comp.dsp
Subject: 200 MFLOPS Vector Processor for Sun SPARCstations on Sbus or VME bus
Keywords: DSP, i860, Intel, Radar, Sonar, Vector Processig, Sun
Date: Mon, 24 Aug 92 15:18:29 PDT
Distribution: world
Organization: CSP,Inc - The Array Processors

 ** CSPI Announces the SuperCARD 3 VME, 200 MFLOPS Vector Processor **

     Billerica, Massachusetts -- CSPI announces the newest member of 
the popular SuperCARD vector processor family, the SuperCARD SC-3XL/VME,
a 6U VME64 board with 200 MFLOPS performance, up to 64 MBytes of memory,
and up to 200 MBytes per second I/O, using two Intel 50 MHz i860 XP Chips.
The SuperCARD SC-3XL/VME is the first VME board available that incorporates
Intel's newest i860 XP chips in a 50 MHz design: giving the SuperCARD
processor unprecedented performance, and making it CSPI's top-of-the-line
product, in the ever-growing SuperCARD family.

     The new SuperCARD processor is available with either one or 
two i860 XP chips; yielding a peak performance of 100 or 200 MFLOPS.
A Gallium Arsenide (GaAs) memory controller allows the 8, 16, 32 of 64
MBytes of DRAM memory to operate at 200 MBytes per second, and supports
cache coherency with bus snooping, and parity.  For I/O and control,
the board supports three independent I/O channels with DMA: a VME64
interface (72 MBytes/sec), a VSB interface (40 MBytes/sec), and the
CSPIO interface (200 MBytes/sec).

     As with prior SuperCARD models, the new SuperCARD 3 software
is compatible with existing models; making the transition from SC-1,
SC-2 an easy process.  Software support for platforms from Sun
Microsystems, Silicon Graphics, and many others is available.

     Due to it's industry-leading combination of speed, memory, and
I/O bandwidth, the SC-3XL/VME model is particularly well suited to 
applications such as sonar, radar, simulation, image and seismic 
processing; markets where CSPI is know as a supplier of reliable, 
high performance equipment.  The SuperCARD-3 and SC-3XL/VME will
be available in the third quarter of 1992, with prices starting at
$ 12,000.

     CSPI was founded in 1968 with specific strengths in digital
signal processing and computer technology.  Today, CSPI is recognized
as a leading manufacturer of vector processors which enhance a computer's
ability to perform high-speed arithmetic.  Markets served include science
and engineering applications in signal processing, sonar and radar 
processing, image processing, seismic processing and well logging, medical
imaging (such at CT and MRI scanning, and others.  

     For more information on CSPI and it's products, please send mail
or call the contact below.

Doug Johnson
CSPI - The Array Processors
*******************************************************************
* CSP, Inc.             	| E-Mail: universal!doug@ucsd.edu *
* 27782 Alfabia Drive    	| Or:       cspidoug@infoserv.com *
* Suite A           		| Phone:  (714) 472-4301          *
* Mission Viejo, CA  92692 	| FAX:     (714) 472-4755         *
*******************************************************************
Newsgroups: comp.dsp
From: 5140840@mcimail.com
Subject: TI DSP
Nntp-Software: PC/TCP NNTP
Organization: Texas Instruments Materials and Controls Group
Date: Fri, 4 Sep 1992 15:00:24 GMT

>  Also, what is the current state of the TI compiler .. cost
>  and availability. Is there an alternative?

The current TI C30 Compiler is now a C3x/C40 (i.e. floating point) compiler and
is on revision 4.40 (if I remember correctly the version you have is almost
three years old).  Version 4.50 is scheduled to be released in October.

The PC compiler now costs $1500 for new versions.  Since you already have a
compiler you might be able to get updated with a low registration fee
(depending on how you got the compiler).  Most universities are waived from the
registration fee, however, and a lot of universities can get free software
through the University program.  Since you're in New Zealand, however, this may
be a little difficult.

There really aren't any other C compilers for the C3x.  There is a GNU C++
Compiler which Sonitech is now marketing, but I am not sure what it's like.

Regards,
Mitch Reifel
Texas Instruments
Houston, Tx
From: pj_pycro@csd.brispoly.ac.uk (PJ Pycroft)
Newsgroups: comp.dsp
Subject: Noise Recognition
Date: 26 Aug 92 20:30:19 GMT
Organization: Bristol Polytechnic, England

Hello netters,

I'm trying to set up a project on noise recognition systems, recognize some
form of noise such as siren (police, fire etc.), alarm signal or any other
warning noise which will alert a deaf person.

I'm thinking of using Signal Processing and Neural Network for detecting
above noise and will be using parallel processing such as Transputers
and DSP (perhaps, I will be using Transputers instead of DSP).

I would be grateful if you had any ideas/info' of using Signal Processing
and Neural Network (both hardware and software) for the above project - any
hints would be grateful obtained.

Where shall I get the info'/material of Richard P. Lippmann's work on sound
alerting aid for the deaf, signal processing for hearing aids and relating
info'.

I'm a profoundly deaf postgraduate student doing M.Sc. in Parallel Computing
Systems.

Thanks for your help.

Paul

--------
pj_pycro@csd.brispoly.ac.uk
From: cspidoug!cspidoug (Doug Johnson - CSPI Mission Viejo, CA)
Newsgroups: comp.dsp
Subject: CSPI Vector Processor Users Group
Keywords: DSP, CSPI, i860, VMEbus, Signal Processing, User's Group
Date: Wed, 02 Sep 92 17:24:43 PDT
Distribution: world
Organization: CSP,Inc - The Array Processors

I represent CSP, Inc., a major manufacturer of signal and array
processing systems since 1968.  We are interested in knowing if our
users who subscribe to comp.dsp would be interested in forming a CSPI
users group on the net.  

So to all of you loyal CSPI clients, please let us know if you would
like such a group to be formed.  It would be helpful if you could 
indicate which products you have, in your response.  IE: Mini MAP,
MAP-4000, SuperCARD, VME, i860, QuickCARD etc.

Thank you for your interest.
--
Doug Johnson
CSPI - The Array Processors

********************************************************************
* CSP, Inc.			| E-Mail: universal!doug@ucsd.edu  *
* 27782 Alfabia Drive		| Or:	  cspidoug@infoserv.com    *
* Suite A			| Phone:  (714) 472-4301           *
* Mission Viejo, CA  92692	| FAX:    (714) 472-4755           *
********************************************************************
From: wjs@re3sc139h.gmr.com
Newsgroups: comp.dsp
Subject: TEST
Date: 1 Sep 92 17:13:25 GMT
Distribution: mi
Organization: Electronic Data Systems


Just a test.
Newsgroups: comp.dsp
From: mbbloom@athena.mit.edu (Matthew B Bloom)
Subject: ACCUMULATOR CHIPS
Organization: Massachusetts Institute of Technology
Distribution: comp.dsp
Date: Fri, 4 Sep 1992 16:15:50 GMT


I am having serious trouble using IC Master to find a 16 bit
Accumulator.  Does anyone know of such a part that runs < 50 ns?

Thanks...

Matt Bloom
mbbloom@athena.mit.edu


Newsgroups: comp.dsp,misc.forsale
From: vcb@irk.ugcs.caltech.edu (Vance Carl Bjorn)
Subject: Re: FORSALE: TI C30 C Complier & Assembler
Organization: California Institute of Technology, Pasadena
Date: Wed, 26 Aug 1992 15:28:28 GMT


>In article <1992Aug20.184820.3892@javelin.sim.es.com> bgeer@javelin.sim.es.com (Bob Geer) writes:

> >> vcb@irk.ugcs.caltech.edu (Vance Carl Bjorn) writes:
> >> 
> >> >I recently acquired the TI C30 C complier and assembler package
> >> >for MS-DOS based machines.  The project with which it was to be
> >> >....  I have not
> >> >sent in the registration card yet, so if there are any recent
> >> >updates, they would be sent free of charge.  
> >> 
> >> Are you sure of this?  TI is now charging an annual fee for the TMS320
> >> C compiler package update releases, at least for our Sun-based
> >> development package.
> >> 
> >> Also, what version do you have?

It is version 4.1.  I purchased it less than a year ago, so the 
upgrade policy is still in effect.  I am lowering my price
to $600, but I will not go much lower than that; I will
find some use for the package if need be.  

Vance Bjorn
vcb@ugcs.caltech.edu
Newsgroups: comp.dsp
From: sepehr@falstaff.dev.cdx.mot.com (Sepehr Mehranbanzad)
Subject: Re: mu-law encoding - definition?
Keywords: mu-law
Organization: Motorola Codex, Canton, Massachusetts
Date: Sat, 29 Aug 1992 21:27:24 GMT

In article <1992Aug22.190716.2600@athena.mit.edu> parasite@athena.mit.edu (Vince) writes:

>I have a set of data which is mu-compressed from
>12 bits to 8 bits.  I need to maniulate it in
>its 12-bit form and I'm not sure what the
>conversion process between the two is.  All of
>the books I've looked in for an explanation have
>a few graphs displaying the wonderful properties
>of mu-encoding but no direct explanation of how to
>go from one to another.
>
>Does anyone out there know the definitions of the 
>encoding algorithm and wish to tell me what it is?
>If it makes a difference, this data was taken off 
>of the audio port of a Sun Sparcstation (/dev/audio).
>


You can find a very good descriptioin of the comparsion alogrithm and how to implement
the encoder/decoder in the "TI Digital Signal Processing Applications with the TMS320
Family" pages 169 to 198.  This approach has the advantage of not requiring to do any
table look up.

=======================================================================================
Sepehr Mehrabanzad
Signal Processing Research Group		v-mail:(617) 821-7523
Motorola/Codex					e-mail:sepehr@falstaff.dev.cdx.mot.com
=======================================================================================
From: "dspse bedford" <dspse.bedford@channel1.com>
Newsgroups: comp.dsp
Subject: tms320 dps bbs help
Date: 2 Sep 92 17:55:08 EST
Reply-To: "dspse bedford" <dspse.bedford@channel1.com>
Distribution: comp
Organization: Channel 1 Communications

Quoting Jyrkkari to All on 09-01-92:

J >  I live in Finland. I read from TMS320 Family Support Guide '90 
J >about TMS320 DSP Bulletin Board Service.
J >I used SupraFAX modem v.32bis 
J >I used the highest possible speed.I dialled the number. I could 
J >hear
J >the BBS answering but the modems couldn't make the connection. J 
J >No carrier.
J >  Can someone help me out ? 

The TI TMS320 BBS is notorious for bad phone lines.  I call from 
Bedford, MA using a Gateway V.32bis modem and the only way I can 
actually connect is to force a 2400 bps connection.  Check your 
Supra manual, but the following setup string worked for me:
        AT N0 &Q0 S37=6 S10=255
Be sure to set your terminal speed to 2400.  It is a slow 
connection, but at least it works.  Supposedly the BBS is using 
V.32bis modems but I have never been able to make the connection.

Ralph Castellucci of DSP Software Engineering Inc.

--- WinQwk 2.0b#261
--
Channel 1 (R)   Cambridge, MA
From: gingell@aurs01.UUCP (Mike Gingell)
Newsgroups: comp.dsp
Subject: Re: mu-law encoding - definition?
Keywords: mu-law
Date: 26 Aug 92 17:25:10 GMT
Reply-To: gingell@aurw6b.aur.alcatel.com.UUCP (Mike Gingell)
Organization: Alcatel Network Systems, Raleigh NC

In article <1992Aug22.190716.2600@athena.mit.edu> parasite@athena.mit.edu (Vince) writes:
>
>I have a set of data which is mu-compressed from
>12 bits to 8 bits.  I need to maniulate it in
>its 12-bit form and I'm not sure what the
>conversion process between the two is.  All of
>the books I've looked in for an explanation have
>a few graphs displaying the wonderful properties
>of mu-encoding but no direct explanation of how to
>go from one to another.
>
>Does anyone out there know the definitions of the 
>encoding algorithm and wish to tell me what it is?
>If it makes a difference, this data was taken off 
>of the audio port of a Sun Sparcstation (/dev/audio).
>

mu-law is a code developed by Bell Labs about 30 years ago
for use in PCM telephony. It compresses a 13 bit dynamic
range into an 8 bit pseudo logarithmic form. The MSB is the sign
the next 3 bits are a scale factor and the least 4 are the
magnitude.  The spec is defined in various Bell & ATT documents
as well as CCITT Rec. G.711 and probably countless text books.

To paraphrase the table in CCITT G711

Segment  # of intervals     value at               code
                         segment end points
                           8159                  10000000
   8      16 * 256                               1000xxxx
                           4063                             
   7      16 * 128                               1001xxxx
                           2015
   6      16 * 64         
                            991
   5      16 * 32
                            479
   4      16 * 16
                            223
   3      16 * 8
                             95
   2      16 * 4
                             31
   1      15 * 2
           1 * 1
                              0                   11111111

This just shows the positive side - screwy isn't it?

Mike Gingell, Alcatel, Raleigh, NC USA  (919) 850-6444
UUCP:       ...!mcnc!aurgate!aurfs1!gingell
Internet:   gingell%aurfs1%aurgate@mcnc.org
Newsgroups: comp.dsp
From: iqbal@crow.eel.ufl.edu (M.Iqbal)
Subject: Manchester Encoding/Decoding
Keywords: HD6409
Organization: University of Florida
Date: Sun, 30 Aug 92 23:50:06 GMT

Hi, 

I want to pick data off the serial port(RS232C) and Manchester 
code it. I found that Harris makes a chip which does encoding and 
decoding (HD6409). I am wondering if anybody has delt with the 
chip? Is it possible to encode data off the serial port right 
away or do I have to bring the data to TTL level?

Is it good to use the chip or shall I build my own encoder?
Any suggestion as to how to build the encoder/decoder?

thanks

iqbal@sioux.eel.ufl.edu
Newsgroups: comp.dsp
From: simpson@tesla.uwaterloo.ca (Simpson KF Lam)
Subject: TMS320C30 bus problem
Originator: simpson@tesla.uwaterloo.ca
Organization: University of Waterloo
Date: Sun, 30 Aug 1992 19:05:11 GMT

Hello, world. How are everybody doing?

I've encountered a problem with the TMS320C30 bus a while
ago and I would like to discuss it with everyone.

The TMS320C30 has two buses. The primary bus and the expansion
bus. I designed my DSP board to operate the expansion bus with
MSTRB, which means the timing of the expansion bus and the primary
bus are the same. I put all my memories on the primary bus
and all the input/output on the expansion bus. 

Everything works fine until I start to test the decoded IO ports
on the expansion bus. The primary bus were running at zero wait
state at 32Mhz. The expansion bus were programmed at seven wait
states. (I have some slow IO to do so it seems the easy way to
slow down the bus. I was so wrong.) 

I first test the board with 5Mhz and every timing seems to be
fine. I put a read and a write port inside a endless loop to
verify the timing. It works fine until I put the board into
18Mhz. Then the read cycle is completely disappeared. The only
signal appears on the MSTRB and XR/W is the write cycle. I try
to put various NOP before and after the read and write since I
suspect I've got a register conflict somewhere. In several 
occusions, the bus cycles are completely gone, no MSTRB appears
on my scope.

As it turns out, I can not run the expansion bus slower than the
primary bus as long as I am running my program on the primary
bus. In 32Mhz, both bus has to operate on 1 wait state in order
for the expansion bus to operate properly. (You can have them
in zero wait state but only at 18Mhz. That is the speed I test
that works.) 

I suspect that there is intrinsic problem on the chip itself.
It is no longer cycle dependent when one bus operate faster
than another bus while the CPU has to interleave access them
both like running the program on the primary bus and doing
IO on the expansion bus.

If somebody has similar experience, I would love to hear from
you. The TMS320C30 is very powerful but not the easiest chip
to design with.

				simpson@kingcong.uwaterloo.ca
*************************************************************
-- 
+==========================================================+
+ "Be brave, and your courage will be rewarded."           +
+                                      - sisters           +
+ .........................................................+