From: pss1@kepler.unh.edu (Paul S Secinaro)
Subject: Re: Jerry "knows" 486's faster than 68040.
Organization: University of New Hampshire  -  Durham, NH
Date: Tue, 7 Apr 1992 15:54:03 GMT

In article <1992Apr7.165843.1@cc.helsinki.fi> lindblad@cc.helsinki.fi writes:

>Wrong Jerry.
>Do not belive in benchmarks so blindly. Benchmarks are too dependent on other
>things (compilers, external caches etc.).

So are your comparisons below (i.e. dependent on lots of factors).

>Why don't we look at some other things:
>
>68040 instrucions are in average perhaps 30-50% faster than equivalent 486
>instrcutions while instruction set on both is comparable.

Are you saying that you can look at any given 486 instruction, and the
comparable '040 instruction is 30-50% faster? (I don't have any 486
specs on hand, so I can't say for sure).  Most comparisons I've seen
show a fairly even split between the '040 and '486 in speed of various
integer instructions.

You can't just count instruction cycles and then average them out over
the whole instruction set, because not every instruction is used
equally often.  You have to define, in some way, what a "typical
program" looks like, and then figure how long that program takes to
execute.

>68040 has 8 general purpouse registers and 7 general purpouse data registers
>(all 32 bit). Didn't 486 have 2 *general purpouse* registers and several
>others? That means more register shuffle on 486.

Yes, this is a point in favor of the Moto architecture, IMHO.

>68040 has copyback mode on it's data cache.

I'm not sure about the 486 on this one.

>68040 can perform both floating point and integer instrcutions at the same
>time. Can 486 do the same (I don't know)?

Yes, so can the 386+387, and below (probably the '030 and '882 can also).

>68040 has separate data & instruction cache, both are 4k. 80486 only one
>unified cache of 8k.

It's going to be pretty hard to quantify the performance benefits of
different cache architectures on paper.

>FMUL on 486 takes 16 clocks, on 68040 it takes 5 clocks. FADD takes 10 on 486,
>3 on 68040, DIV takes 73 on 486, 37 on 68040. To me it seems that floating
>points seem to go 3 times faster. Also to much hated MFLOPS: Intel claims it's
>486@25 to have 1 MFLOPS while Morotola claims 3.5 MFLOPS @ 25 MHz. And floating
>point instructions are quite similar on both floating point units.

As has been mentioned before, even in FP intensive applications (which
does not include most common apps), integer instructions still make up
the most of code being executed most of the time by the user (unless
maybe you're into heavy simulation, graphics, etc.).  Consider all the
processing that must be done to handle the GUI, OS context switching,
I/O, loop overhead, etc.  And that's just while the FP intensive loop
is being run.  What about all the time the user spends entering the
data, editing, reading the newsfeed :-), etc.

I don't dispute that the '040 has faster floating point (in fact, I
think it's a really nice chip), but it's somewhat misleading to factor
that in to the overall performance figure.  The number of users who
would see little benefit from _any_ FP hardware of _any_ speed is too
large to be ignored, IMHO.  It makes more sense to evaluate floating
point and integer performance separately, IMHO.

Benchmarks aren't perfect, but neither is just looking at the
instruction set and architecture, unless you are prepared to do a
detailed statistical study of the frequency of use vs. speed of
individual instructions and produce some kind of weighted average,
taking into account architectural features, etc.  By then, you've
pretty much done what many benchmarks attempt to do anyway.

Paul



-- 
Paul Secinaro            | Synthetic Vision and Pattern Analysis Lab
pss1@kepler.unh.edu      | Dept. of Computer and Electrical Engineering
p_secinaro@unhh.unh.edu  | University of New Hampshire