From: lkoop@TIGGER.STCLOUD.MSUS.EDU (LaMonte Koop)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: Chip RAM extremely slow with GVP A530
Date: 26 Jan 93 19:02:54 GMT
Article-I.D.: msus1.1993Jan27.010254.2209
Reply-To: lkoop@TIGGER.STCLOUD.MSUS.EDU
Organization: SCS GP/Engineering Cluster

In article <93024.073149PATROL@ACI.CVUT.CS>, Pavel Troller <PATROL@ACI.CVUT.CS> writes:
>Hi netters,
>      I bought a new A530 Turbo Harddisk last week. Suddenly it is fitted
>only with a 1Meg of 32bit RAM, because my local dealer hasn't expansion SIMMS
>stock. Formerly I had GVP Series 2 Harddisk with 4Megs of expansion RAM, so
>my system has relatively expensive memory requirements. First time I booted,
>I tried SysInfo to show me the wonder, but I was surprised: 0.78 of standard
>A500, 0.30 Chip vs A3000.
>      I wrote a short program in assembler, which simply counts to zero from
>$1000000 and then returns. Its results are shown:
>      Memory Type     Inst Cache Status     Time to run
>       32bit           Enabled                3.5 s
>       Chip            Enabled                3.5 s
>       32bit           Disabled               9 s
>       Chip            Disabled               120 s   :-(
>      With motherboard CPU:
>       Chip            not available          49 s
>
>      I know that with asynchronous bus operations there is a need to syn-
>chronize bus cycles of 40Mhz '030 with 7Mhz of motherboard; but I didn't
>supposed that it will be so drastic. It also means that without the basic
>1Meg of 32bit RAM the system is unusable!

    Well, what you've run into is a charateristic of all the Motorola 680x0
series processors from the 68020 on.  The primary figure you are concerned
with above (as it seems) is the timing you received from your test when you
ran it with only CHIP memory available, with the 68030 instruction cache off.
The results you see are fairly typical given that kind of setup.  Here's why:
The 68020, 68030, and 68040 always prefetch instructions using 32-bit read
cycles.  Since the A500 motherboard bus is a 16-bit port to the 68030 on your
accelerator, essentially 2 memory read cycles must be accomplished for every
instruction prefetch done.  Right off the bat this gives you a 2x performance
hit against a 68030 doing prefetches from a full 32-bit bus port.  If you add
to this the fact that, as you indicated, the reads are done asynchronously to
a bus running a ~7.15 MHz, and the fact that you also have to deal with bus
contention from the custom chip DMA on the CHIP RAM bus, you can easily see 
where performance drops into the ground in the case with the instruction
cache disabled.  Performance figures less than a system running the stock
68000 in this situation are not unexpected.
    When the instruction cache is enabled, it tends to somewhat buffer this
effect and bring performance levels back up.  Typically, do not expect better
than a 1.5-2x performance enhancement over a stock A500 when only CHIP or
16-bit ported FAST RAM is available to the 68030 in this case.  With a 32-bit
ported RAM resource available to it, the 68030 is then not given the
restrictions above, and this is the primary reason anyone with a 68020/030/040
accelerator for an A500/600/2000 is well suited to acquire 32-bit ported memory
expansion for it as well.

                 ----------------------------------------
           LaMonte Koop -- SCSU Electrical/Computer Engineering
 Internet: lkoop@tigger.stcloud.msus.edu -OR- f00012@kanga.stcloud.msus.edu
              "You mean you want MORE lights on this thing???"
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