HDTenEightyP/NetNews huggingface dataset:
From: ptran@envmsa.eas.asu.edu (Phi-Long Tran)
Subject: Re: CIT-101e - how do i save settings?
News-Software: VAX/VMS VNEWS 1.4-b1  
Keywords: vt100 terminal CIT-101e
Reply-To: ptran@asuvax.eas.asu.edu
Organization: Arizona State University, Tempe, AZ
Date: Sun, 6 Sep 1992 22:32:00 GMT

In article <Bu6B3t.Fuo@rice.edu>, andrew@ruf.rice.edu (Andrew Mann Hung) 
writes...

> Can anyone tell me how to save the settings on a CIT-101e terminal?  I
> bought this used from someone, but i'm lacking documentation.  It's kind
> of a pain to set the transfer speed every time i reset/ reboot the
> terminal (default is 4800 baud, but my modem is only 2400 baud), and my
> only other option is to leave it on all the time.

     When you are in the setup menu, use Ctrl-S to save the setup, Ctrl-D
to reset the settings to the factory defaults, and Ctrl-R to recall a
previously-saved setup.

---
Phi-Long Tran
ptran@asuvax.eas.asu.edu
Arizona State University
Newsgroups: comp.terminals
From: ets1@cec2.wustl.edu (Eric Thomas Stuebe)
Subject: docs for Freedom100 desired
Organization: Washington University, St. Louis MO
Distribution: na
Date: Sun, 13 Sep 1992 21:00:15 GMT


I'm basically interested in anything written down (or typed to a file)
about the Freedom100 terminal.  However I don't need a termcap entry,
unless someone has one that's better than the one in "termcap.src 1.33
89/03/22 SMI; from UCB 5.28 6/7/86".

I'd like to make use of the aux port, but I don't even have a good
grasp of what ways it *can* be used (this is my "first terminal" ;-),
much less the escape codes to use.

Also, does anyone have any advice on which is the best emulation mode
to use:  hazeltine 1420, Televideo 910, Adds Regent 25, Adm 3A/5, or
Freedom 100?


If someone is willing to photocopy and mail a manual, or somesuch, I'm
willing to cover the costs.


--
Eric Stuebe, ets1@cec2.wustl.edu
CS/EE at Washington University in *St. Louis*
"I do ordinary things things for extraordinary reasons."

Newsgroups: comp.terminals
From: jain@seas.smu.edu (Rakesh Jain)
Subject: Need TERMCAP entry for IBM3163/3164 terminals.
Keywords: termcap, IBM3163/3164, vt100
Organization: School of Engineering and Applied Science
Distribution: usa
Date: Sat, 5 Sep 1992 18:18:30 GMT


hi there,

	I need termcap entry for IBM3163/3164 terminals.
	I will appreciate it very much if any one can send me one
	via E-mail. Also can any one suggest what termcap entry should
	I use to emulate the above said terminal in vt100 mode.

	Thank you very much

	rakesh

	e-mail: jain@seas.smu.edu

Newsgroups: comp.cad.cadence
From: hampton@ecadsr.enet.dec.com (Jonathan D. Hampton)
Subject: Displaying waveforms?
Organization: Digital Equipment Corporation
Date: Wed, 9 Sep 1992 15:22:33 GMT


I'm using the VERILOG-XL tool and was wondering if anyone can tell
me how to go about displaying simulation results graphically, i.e.
waveforms.  The tutorial mentions something about a graphical output
facility, but the manuals make no mention of it.

Can anyone help?

Thanks.

Hamp 


-----

Jonathan "Hamp" Hampton 	  hampton@ecadsr.enet.dec.com


	"Zipperphobia?  *BUTTON* your fly!"

-----
From: d86-emh@dront.nada.kth.se (E Magnus Hulthen)
Subject: Fonts and their sizes.
Organization: Royal Institute of Technology, Stockholm, Sweden
Distribution: comp
Date: Wed, 9 Sep 1992 13:18:36 GMT


Hello,

I'm after 6 hours of solid digging into Skill, Design Framework, and
techFile manuals still as puzzled as before I started. (If not more :-)
The question is, how do I get the size of the characters in the fonts.
The font I'm interested in is the "stick" font but I guess theres gotta
be a general way of finding this out.

So any help you can give me is greatly appreciated.

Thanks,
					/Magnus Hulthen
					d86-emh@nada.kth.se
From: arindam@cs.uwindsor.ca (Arindam Das)
Newsgroups: comp.cad.cadence
Subject: simulation problem
Keywords: STL, IL, Spice
Date: 10 Sep 1992 22:20:40 GMT

i tried to simulate an inverter schematic using spice.
The schematic had vdd, gnd, in and out nets and did
not have any capacitor hooked up from output to ground.

i used the STL for stimulus. The .stl file "inv.stl"
is as given below:

; **********  STL Source Program Template  ***************

stlinit


defpin in1      in    tr=1ns tf=1ns
defpin out1     out

deflevel  vil=0 vih=5 vol=0 voh=5
defformat in1 out1

deftiming 1ns 10ns 100ns  ;define basic time units

deftest

xv(0 1)
xv(1 0)
xv(0 1)
xv(1 0)

endtest
;*****************************************************

The simulation ran successfully. BUT in the waveform,
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
the output curve was at 0 for both 0 and 1 input.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

How to get rid of this problem ?
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

I tried simdiff("inv.stl") and got the following output:

1> simdiff("inv.stl")

<2> t
<3> t
<4> t
.
.
<7> t
<8> Preparing to read simulation output file ...
Done ...
t
<9> *Mismatch* out1  at time 9.9e-08 - expected (voh) simulated (-6.27813e-21)
t
<10> t
<11> *Mismatch* out1 at time 2.99e-07 - expected (voh) simulated (-.286818)
t
<12>t
<13> 2 simulation comparison mismatches detected (4 comparisons made)

t
<14>
 

Could somebody help me ?


Another question:

Is there any IL function so that I can redirect the output
of simdiff("inv.stl") to a file instead of standard output ?
I would be glad if someone gives an example. I had to type
the whole output above myself !@# 


Newsgroups: comp.cad.cadence
From: ruck@zeta.ee.ufl.edu (John R Ruckstuhl Jr)
Subject: Re: User Group - New Officers
Organization: EE Dept at UF
Date: Tue, 8 Sep 92 20:04:33 GMT

In article <496@idtinc.UUCP> cwp@idtg.uucp (Chuck Phillips) writes:
> We plan on sending out lots of info regarding the meeting in the
> next few weeks.

Well, what do users who missed the conference want to know?

Regarding the conference:
1.  When will printed proceedings of the conference be available?
    Who is the contact and how much will they cost?
2.  Would you post the contents of a conference program so that we have
    an idea what was presented/discussed and by whom?
3.  Was the conference videotaped, and if so, how can we get copies?
    (I had made the suggestion of videotaping the conference to a
    Cadence employee who said she'd pass it to the Right Person, but I
    don't know what the response was.)

I want to know about the current and future states of the Cadence/Valid
product line.
Did Cadence take this opportunity (the conference) to give any such 
information regarding the integration of the design systems and future 
of overlapping tools?

Regards,
ruck
-- 
John R Ruckstuhl, Jr                    ruck@alpha.ee.ufl.edu
Dept of Electrical Engineering          ruck@cis.ufl.edu, uflorida!ruck
University of Florida                   ruck%sphere@cis.ufl.edu, sphere!ruck
Newsgroups: comp.cad.cadence
From: why@bnr.ca (Graeme Boyd)
Subject: Re: Fonts and their sizes.
Originator: why@bcrks197
Reply-To: why@bnr.ca (Graeme Boyd)
Organization: Bell Northern Research, Ottawa
Distribution: comp
Date: Wed, 9 Sep 1992 13:47:44 GMT


In article <D86-EMH.92Sep9141836@dront.nada.kth.se>, d86-emh@dront.nada.kth.se (E Magnus Hulthen) writes:
> 
> Hello,
> 
> I'm after 6 hours of solid digging into Skill, Design Framework, and
> techFile manuals still as puzzled as before I started. (If not more :-)
> The question is, how do I get the size of the characters in the fonts.
> The font I'm interested in is the "stick" font but I guess theres gotta
> be a general way of finding this out.
> 
> So any help you can give me is greatly appreciated.
> 
> Thanks,
> 					/Magnus Hulthen
> 					d86-emh@nada.kth.se
In EDGE skill:
	if(inst~>shape=="label" then
	/* Case: have found a Label */
	/* then the fontSize is */
	fontSize=inst~>height
	)
See also page 4-26 of SKILL manual for a great picture of properties
for each object type.

I am not sure about OPUS skill.....
-- 
Graeme Boyd                      B.N.R. Ltd
why@bnr.ca                       Ottawa, Canada
                   Perrussel's Law
There is no job so simple that it cannot be done wrong.
==========
My thoughts, My words -- Let BNR make its own mistakes.
From: tsui@pollux.usc.edu (Chi-Ying Tsui)
Newsgroups: comp.cad.cadence
Subject: CIFIN tech file
Date: 9 Sep 1992 14:24:54 -0700
Organization: University of Southern California, Los Angeles, CA
Distribution: world
NNTP-Posting-Host: pollux.usc.edu

Hi,

	I am using the CIFIN translator in Desgin Framework II to translate some
CIF files to the Cadence database. I want the layout display  to be similar to that of 
Magic, i.e. instead of showing the CIF mask layers,the devices layers are shown.
I just wonder anyone has a default tech file for this kind of CIFIN translation.
If yes, I'll appreciate if you can send me a reply. Thanks.


Chi-ying Tsui
From: markp@vlsi-az_fw.vlsi-az.sps.mot.com (Mark Pease)
Newsgroups: comp.cad.cadence
Subject: Re: Third Party Books for Cadence
Date: 9 Sep 92 18:42:24 GMT
Organization: VLSI Design Center, Tempe AZ

In article <mn9pbdqs@csv.warwick.ac.uk> esrne@warwick.ac.uk (Mr P I Neaves) writes:
>
>A simple question.
>
>Are there any third party books (i.e. not written by Cadence) about
>how to use Cadence, SKILL etc.
>
>In other words, a decent training manual.
>
>For example, there must be hundreds if not thousands of books
>on TURBO C.
>
>What about Cadence ?
>
>Phil

How much interest would there be for a book like this? I have thought that
I might do it for my next project, but unless we could sell enough books, I
don't think that I could get a publisher to do it.

What do you think? How many installations does Cadence have? What would you
like to see in a Skill Book (How 'bout the title "Strike Up The Band:
Programing in Cadence Skill"?)


Mark Pease                             markp@vlsi-az.sps.mot.com
Motorola CODEX VLSI Design Center
2710 S Roosevelt St.                   Mail Stop: AZ28 BB106
Tempe, AZ 85282         Phone:(602)784-2725    FAX:(602)784-2759
Newsgroups: comp.cad.cadence
From: gibbons@libra.suneng (Alan Gibbons)
Subject: Re: Third Party Books for Cadence
Reply-To: gibbons@chdasic.sps.mot.com
Organization: Motorola ASIC Division
Date: Wed, 9 Sep 1992 19:56:22 GMT

> In article 24494@newsgate.sps.mot.com, markp@vlsi-az_fw.vlsi-az.sps.mot.com (Mark Pease) writes:

>Programing in Cadence Skill


Isn't Cadence Skill a contradiction in terms ?


--------------------------------------
Alan Gibbons
Motorola ASIC Division

Newsgroups: comp.cad.cadence
From: rrebello@titan.uucp (Rod Rebello -- CAD Development)
Subject: how to determine if bus/net is subnet of another bus?
Organization: Microchip Technology Inc.
Date: Tue, 15 Sep 92 04:52:11 GMT

I am porting some skill code from edge to opus. Part of the code needs to
determine if a bus definition is actually a subrange definition of another
bus.  This worked in edge but does not in opus. We were depending on the
"parent" field of the net structure to hold a pointer to the parent bus
definition (i.e., if not nil then this bus is actually a subrange
definition). However, in opus, this field does not appear to be used.
Here is a dump from ShowFileBrowser of a bus subrange, bus<1:0>, which
is a tap off of bus<3:0>. 

(db19273772 
    (cellView db18929708) 
    (objType "net") 
    (prop nil) 
    (allInstTerms nil)
    (connStatus "needToConnect") 
    (criticality 10) 
    (figs 
	(db19275604 db19275448 db19275484)
    ) 
    (groupMembers nil) 
    (instPins nil)
    (instTerms nil) 
    (name "bus<1:0>") 
    (numBits 2) 
    (parent nil) 
    (pins nil)
    (signals 
	(db19274756 db19274396)
    ) 
    (sigNames 
	("bus<1>" "bus<0>")
    ) 
    (subnet nil) 
    (subnets nil) 
    (term nil)
)

As you can see, parent is nil. Also, the subnet fields of the "parent" bus, 
bus<3:0> are also nil.  I talked to a rather inexperienced Corp. AE about
this problem who has talked to the R&D folks. So far all I've gotten is
that these fields are not supported in the same way as under edge.
I have asked to be put in direct touch with a more knowledgeable person,
but so far no response.  Can anyone enlighten me on how/when the parent
field is now used, and how I might easily check that a bus spec is 
actually a subrange of another bus?  Meanwhile, I will keep knocking
on Cadence to get me the answer (groan).  Is the answer perhaps buried
in some obscure section of one of the many skill manuals?
 
Thanks,
-- 
Rod Rebello
titan!rrebello@asuvax.eas.asu.edu
Microchip Technology Inc., Chandler, AZ
Newsgroups: comp.cad.cadence
From: toma@romulus.cray.com (Thomas Arneberg)
Subject: Re: Third Party Books for Cadence
Organization: Cray Research, Inc.
Date: 9 Sep 92 10:23:17 CDT

In article <mn9pbdqs@csv.warwick.ac.uk> esrne@warwick.ac.uk (Mr P I Neaves) writes:
>
>Are there any third party books (i.e. not written by Cadence) about
>how to use Cadence, SKILL etc.  In other words, a decent training manual.
>
>For example, there must be hundreds if not thousands of books
>on TURBO C.  What about Cadence ?
>
>Phil

There are none that I know of. However, for advanced Skill there is an
internal Cadence document called _Inside Skill_ that you should be able to
get from your Cadence applications engineer.

(BTW, I have a copyofacopyofacopy...does anyone know if _Inside Skill_ is
available in Postscript so I can print my own fresh copy?)

I wouldn't hold my breath for lots of third-party books on Cadence
software...the number of users is too low and the stuff changes too quickly
to make it profitable for a book publisher, I suspect.

  - Tom A.
---------------------------------------------+------------------------------
;-) I'd rather be ____  Thomas R. Arneberg   | Inet: toma@cray.com
:-) singing in a |____| Senior IC Design Eng.| UUCP: ...!uunet!cray!toma
:-) Barbershop  _|   _| Cray Research, Inc.  | CLAIM TO FAME: Loni Anderson 
:-) Quartet!   (_)  (_) Chippewa Falls, Wisc.|   went to my high school 
---------------------------------------------+------------------------------
From: jwalker@isi.edu (John Walker)
Newsgroups: comp.cad.cadence
Subject: Re: Summary Design Archive
Date: 15 Sep 92 19:01:04 GMT
Reply-To: jwalker@valerie.isi.edu (John Walker)
Organization: USC-Information Sciences Institute

Newsgroups: Early Posting
Subject: Problems running Edgel
Summary: 
Expires: 
Reply-To: jwalker@valerie.isi.edu (John Walker)
Followup-To: 
Distribution: 
Organization: USC-Information Sciences Institute
Keywords: 

Good Morning;
I have been trying to successfully place and route and create a GDS II file for
a large design (ruffly 5000 x 5000).  The problem that I have had is that 
when I select all of the design and "explode",  Cadence "Dies" (i.e.) I get a
"D" for the cadence process when I run "ps" and "top" shows that the process
is sleeping.

One item to note, This problem doesn't show up when working with smaller
designs.  It also doesn't happen if I only select a portion of my large design
(say a quarter of it) and then do the explode operation.

I'd appreciate it if anyone could offer suggestions.
Thanks much in advance.
John W.
Newsgroups: Early Posting
Subject: Re: Problems running edge
Summary: 
Expires: 
Reply-To: jwalker@valerie.isi.edu (John Walker)
Followup-To: 
Distribution: 
Organization: USC-Information Sciences Institute
Keywords: 

Good Morning;
I have been trying to successfully place and route and create a GDS II file for
a large design (say 5000 x 5000).  The problem that I have had is that when I
select all of the design and "explode" Cadence "Dies" (i.e. running "ps" shows
cadence in a constant "D" state, and "top" shows the cadence process to be
"sleeping" using virtually no processor time).

One item to note, This problem doesn't show up when working with smaller 
designs.   It also doesn't happen if I only select a portion of the design 
(say a quarter of it) and then do the explode operation.  So this seems to 
have to do with the size of the design and the number of cells selected.

I'd appreciate hearing from anyone who knows about this problem and how to
fix it.
Thanks much in advance.
John W.

Newsgroups: comp.cad.cadence
Subject: Re: Summary Design Archive
Summary: 
Expires: 
Reply-To: jwalker@valerie.isi.edu (John Walker)
Followup-To: 
Distribution: 
Organization: USC-Information Sciences Institute
Keywords: 

Newsgroups: comp.cad.cadence
From: toma@romulus.cray.com (Thomas Arneberg)
Subject: Pin order for HSPICE netlisting from Composer (REPOST)
Organization: Cray Research, Inc.
Date: 9 Sep 92 10:14:10 CDT

(This is a REPOST -- I have not heard a word about this from other users or
Cadence people since I first posted it in July, so I thought I'd try again
to see if any new readers may have a clue...)

Does anyone know how to change the pin order in a subcircuit call in 
hierarchical HSPICE netlist from Composer?

On page 7-95 of the Design Entry manual (October 1991), it says that you
select "Pin Order" from the "Update" menu to "define logical pin ordering
for netlisting."

Sounds simple enough, but it doesn't work for me.

I tried it in both the schematic and symbol views of a cell that is used in
a higher-level schematic, and still the pins are ordered alphabetically.

I am using version 4.2a sub-version 4.2.65.4 on a SS-2 running SunOS4.1.1.

(As an aside, the editing procedure was quite a suprise...rather than
popping up an xedit or vi window, it prompted me for editing the file in 
the unix shell in which I invoked the Cadence software! Since I had invoked 
the Cadence software in background (i.e. "cds &"), it actually stopped the 
cds job and it took me a while to figure out why the software "froze" the 
first time I tried to reorder the pin order.)

Thanks for any advice/insight,
  - Tom A.
---------------------------------------------+------------------------------
;-) I'd rather be ____  Thomas R. Arneberg   | Inet: toma@cray.com
:-) singing in a |____| Senior IC Design Eng.| UUCP: ...!uunet!cray!toma
:-) Barbershop  _|   _| Cray Research, Inc.  | CLAIM TO FAME: Loni Anderson 
:-) Quartet!   (_)  (_) Chippewa Falls, Wisc.|   went to my high school 
---------------------------------------------+------------------------------
Newsgroups: comp.cad.cadence
From: d86-emh@dront.nada.kth.se (E Magnus Hulthen)
Subject: Re: Fonts and their sizes.
Organization: Royal Institute of Technology, Stockholm, Sweden
	<1992Sep9.084019.23473@walter.cray.com>
Distribution: comp
Date: Thu, 10 Sep 1992 14:21:58 GMT

In article <1992Sep9.084019.23473@walter.cray.com> toma@romulus.cray.com (Thomas Arneberg) writes:
   In article <D86-EMH.92Sep9141836@dront.nada.kth.se> d86-emh@dront.nada.kth.se (E Magnus Hulthen) writes:
   >
   >The question is, how do I get the size of the characters in the fonts.
   >The font I'm interested in is the "stick" font but I guess theres gotta
   >be a general way of finding this out.
   >
   >So any help you can give me is greatly appreciated.
   >
	.
	.

   There are three ways that I know of:
      .
      .

   Does this answer your question, or did I misunderstand?
     - Tom A.
   ---------------------------------------------+------------------------------
   ;-) I'd rather be ____  Thomas R. Arneberg   | Inet: toma@cray.com
   :-) singing in a |____| Senior IC Design Eng.| UUCP: ...!uunet!cray!toma
   :-) Barbershop  _|   _| Cray Research, Inc.  | CLAIM TO FAME: Loni Anderson 
   :-) Quartet!   (_)  (_) Chippewa Falls, Wisc.|   went to my high school 
   ---------------------------------------------+------------------------------

No you did not misunderstand the question. But the question was a 
misconstruction. The real question I wanted to ask was how to get
the aspect ratio of each character in the "stick" font on the 
Cadence Composer system for the schematics. I need this to be able 
to calculate the width of a string given a fixed height of the string.

I apologize for my previous question.

So if anybody has some insights on this I would appreciate a hint.

				/Magnus Hulthen
				d86-emh@nada.kth.se


Xref: sparky comp.cad.cadence:302 comp.lsi.cad:950
From: cwp@idtinc.UUCP (Chuck Phillips)
Newsgroups: comp.cad.cadence
Subject: Re: Cadence Users
Date: 10 Sep 92 14:58:15 GMT
Organization: Integrated Device Technology, Santa Clara

In article <2q0pbqa4@csv.warwick.ac.uk> esrne@warwick.ac.uk (Mr P I Neaves) writes:
>Thanks for all the replys re: Cadence Books.
>
>Unfortunately - each institution can not go through Cadence to get
>literature such as an advanced guide to SKILL.
>
Cadence is working on getting thier documentation on CD-Rom. Perhaps this
may help in getting "manuals" from Cadence in the future.

>While I am *NOT* going to critisize RAL - the Cadence manuals
>we have are absoloutely *awful*.
>

If you are talking about "Edge" software then I FULLY agree. They are
very poor. The Opus manuals are improved. Many applications have both a
reference manual (states each command and its syntax) and a user guide
(more of a cookbook on how to use the application.) Also, there are
actual examples on how to use the commands - not just syntax statements!

The two documents I mentioned, Inside Skill and the Advanced Skill
Tutorial are NOT! manuals. Inside Skill is an Application Note written by
the AE staff and is not shipped with the software. You have to ask for
it. The tutorial will be available for separate purchase in the near
future. (I'll post details.) I highly recommend both of these.

You should have no problem (from Cadence) in buying the tutorial once it
is available. If you can not get Inside Skill let me know and I will look
into the matter. I do not know your individual situation but have heard
from others that Europe is a tough place to be a customer.

>Oh well - enough moaning.
>
There is NEVER enough - sometimes it's the ONLY way a vendor will listen.  :-)

>Thanks for your help boys and girls.
>
Your welcome!

>Regards
>
>Phil

===================================================
|Chuck Phillips                                   |                          
|Integrated Device Technology, Inc                |
|2670 Seeley Ave                                  |
|San Jose, CA 95134                               |
|(408)944-2052                                    |
|(408)944-2195 (FAX)                              |
|uunet.uu.net!idtg!cwp                            |
|International Cadence User Group - Co-Chair      |
|Bay Area Cadence User People, BACUP, Chair       |
===================================================
From: weedk@pogo.wv.tek.com (Kirk Weedman)
Newsgroups: comp.cad.cadence
Subject: Re: Summary Design Archive
Date: 15 Sep 92 18:46:18 GMT
Organization: Tektronix, Inc., Wilsonville,  OR.

In article <506@idtinc.UUCP> cwp@idtinc.UUCP (Chuck Phillips) writes:
>
>The only other info that I can offer is that Cadence offers a Daisy to
>Cadence translation package. I do not know how well it works.

They also offer an OrCAD to GED/CONCEPT translation package called ORTRAN
from a third party vendor - KOALAWARE 503-678-2683.
From: esrne@warwick.ac.uk (Mr P I Neaves)
Newsgroups: comp.cad.cadence
Subject: Cadence Users
Date: 10 Sep 92 07:48:08 GMT
Organization: Computing Services, Warwick University, UK

Thanks for all the replys re: Cadence Books.

As I am sure most of you are aware - there is a European wide
initiative called Eurochip.

One of its aims is to bring to Universities and Polys software like
Cadence at a reasonable price.

Unfortunately - each institution can not go through Cadence to get
literature such as an advanced guide to SKILL.

We have to go via various "service" organisations. In the UK
this is the Rutherford Appleton Laboratory.

While I am *NOT* going to critisize RAL - the Cadence manuals
we have are absoloutely *awful*.

Oh well - enough moaning.

Thanks for your help boys and girls.

Regards

Phil
Newsgroups: comp.cad.cadence
From: rjromanc@sun1.vlsi.uwaterloo.ca (Richard Romanczyk)
Subject: Re: PCB Layout              
Organization: University of Waterloo
Date: Thu, 10 Sep 1992 16:20:08 GMT

Does anyone know if CADENCE offers any CAD package for laying out Printed
Circuit Boards and generating the masks onto transparencies ? Where can I
get information about this ?


Newsgroups: comp.cad.cadence