Newsgroups: comp.sys.hp48

* * * * *     Saturn Processor Reference Update     * * * * *

stevev@miser.uoregon.edu [Steve VanDevender] posted a Saturn ML
reference which I found very well organized and a valuable addition to
the corpus of HP48 Hacker's Notes.  However, its instruction timing
data is based on the specifications of an older version of the
processor which had fewer instructions, and a few which were slower.
Also, some instructions were missing.  If you keep Saturn notes,
please update as follows.

HP's own SASM.DOC needs to be updated with this too, since it was
copied from the HP-71 IDS for the most part.

Thanks to Alonzo Gariepy and Preston Brown for most of this stuff.
Although I proofread it twice, blame any typos o me, however.
Please post additions and/or corrections to this update.  Thanx.

-jkh-

=====================================================================

The following instructions had timings of "???" in Steve's table.
BTW, none of these instructions were in the HP-71's processor.

Field & register mnemonics are as per Steve's symbol table.
Specially important: "m" stands only for A or C, and "L" stands for
the data length (the number of nibbles being handled).

AG MNEMONIC         HP MNEMONIC         CYCLES
-----------         -----------         ------
ADD.g n,r           r=r+CON g,n            5+L
BRBC h,A,PC+5+b     ?ABIT=0 n             16/9  \
BRBC h,C,PC+5+b     ?CBIT=0 n             16/9   \  yes=16
BRBS h,A,PC+5+b     ?ABIT=0 n             16/9   /   no=9
BRBS h,C,PC+5+b     ?CBIT=0 n             16/9  /
CLRB h,C            CBIT=0 n               6
JUMP.A @m           PC=(m)                16
MOVE.g m,t          m=t.F g                6+L
MOVE.g t,m          t=m.F g                6+L
MOVE.A PC,m         m=PC                   9
MOVE.Pn h,A         LAHEX nnnnn            5+L  (not 6+L)
RETBC h,A           ?ABIT=0 n             16/9
RETBC h,C           ?CBIT=0 n             16/9
RETBS h,A           ?ABIT=1 n             16/9
RETBS h,C           ?CBIT=1 n             16/9
SETB h,m            mBIT=1 n               6
SRB.g r             rSRB.F g               6+L
SUB.g n,r           r=r-CON g,n            5+L
SWAP.g m,t          mtEX.F g               6+L
SWAP.A m,PC         mPCEX                 16

=====================================================================

The following instructions are missing from Steve's main document but
are present in the disassembly summary appendix without description or
timing data.  The ones marked with an asterisk (*) were not in the
HP-71's processor.

AG MNEMONIC         HP MNEMONIC         CYCLES   OPCODE    NEW
-----------         -----------         ------   ------    ---

BUSCB               BUSCB                  7     8083       *
  Reserved.  Same as NOP (all devices ignore NSTR {Not STRobe line:
  system clock, active low} until a new command is loaded) for the
  internal peripherals.  Not issued by the CPU.

BUSCC               BUSCC                  6     80B        -
  The device currently addressed by its local data pointer performs a
  specific operation as defined by the individual device.  This
  command is not issued by the CPU.

BUSCD               BUSCD                  7     808D       *
  Reserved.  Same as NOP (all devices ignore NSTR {Not STRobe line:
  system clock, active low} until a new command is loaded) for the
  internal peripherals.  Not issued by the CPU.
  
CONFIG              CONFIG                11     805        -
  Configures an unconfigured device that has DAISYIN=1 @C.A; it then
  will no longer respond to either the CONFIGURE or ID bus commands.

INTOFF              INTOFF                 5     808F       -
  Masks maskable input register interrupts (ignore interrupts).
  Unmaskable interrupts (always available) are (1) NINTX line pulled
  low, which disables all interrupts and sets HS3 (aka MP, Module
  Pulled hardware status bit); (2) NINT2X, same as NINTX except no
  hardware status bits are set; and (3) IR15X line pulled high,
  readable via the input register commands A=IN (IN.4 A) and C=IN
  (IN.4 C).

INTON               INTON                  5     8080       -
  Unmasks maskable input register interrupts (catch interrupts) on the
  KDN line.  If KDN goes high while interrupts are off, it must remain
  high until INTON is executed to generate an interrupt.

RSI                 RSI                    6     80810 (?)  -
  ReSet Interrupts.  Causes any input register line high to be
  considered a new interrupt regardless of whether all input register
  lines have returned low.  Documents disagree on opcode; some say
  8081, most say 80810.

SHUTDN              SHUTDN                 6     807        -
  Issue the NOP bus command to clear all ops, then issue the SHUTDOWN
  bus command and enter low-power standby state; chained chips respond
  according to their own special requirements.  System clock and
  on-board oscillator are stopped.  Data in CPU resident memory is
  preserved.  However, if SHUTDN is executed when the output register
  is 000, the PC will be set to zero, causing a system halt.  The CPU
  is reawakened by either pulling an input register line high, or by
  driving the NCD line low then releasing it when NSTR (system clock)
  goes low (active).

SREQ                SREQ?                  7     80E        -
  Issue the POLL bus command and latch system bus into C.0; HS2 (aka
  SR, the Service Request hardware status bit) is set if C.0 is not
  zero (each bit representing one device's response).

UNCNFG              UNCNFG                12     804        -
  Unconfigure the configured device @C.A; it then will only respond to
  the CONFIGURE and ID bus commands.

RESET               RESET                  6     80A        -
  Issue the RESET bus command; chained chips perform a local reset.
  Unconfigures all soft-configured devices.

=====================================================================

The following instructions have wrong timing in Steve's table and in
HP's SASM.DOC.  That data was correct for the HP-71's processor, but
not for the HP48's, which is faster by one cycle for these
instructions:

AG MNEMONIC         HP MNEMONIC         CYCLES
-----------         -----------         ------
CALL.4 PC+b+6       GOSUBL                14
CLR.X ST            CLRST                  5
MOVE.X ST,C         C=ST                   5
MOVE.X C,ST         ST=C                   5
MOVE.Pn h,C         LCHEX                  2+L  **
SWAP.X C,ST         CSTEX                  5

** note: LCHEX's timing may be confusing; the opcode is 3nhh..h, where
n is *one less* than the number of hex digits to be handled, so its
timing is 3+n (using HP's documentation notation), which is the same
as 2+L (using Steve's notation).

=====================================================================

-Joseph K. Horn-   -Peripheral Vision, Ltd.-
akcs.joehorn@hpcvbbs.cv.hp.com
Disclaimer: I don't work for HP, EduCALC, or anybody else.

From: akcs.jwtrav@hpcvbbs.cv.hp.com (John Wettroth)
Date: Mon, 23 Nov 1992 09:40:06 GMT
Subject: Re: HP28 to HP48S program transfer via IR ??
Message-ID: <2b109be3.2231.1comp.sys.hp48.1@hpcvbbs.cv.hp.com>