HDTenEightyP/NetNews huggingface dataset:
From: brown@odin.ins.cwru.edu (Dan Brown)
Newsgroups: comp.terminals
Subject: Archive of Terminal Documentation??
Date: 1 Oct 1992 02:26:51 GMT
Organization: Subversive Student Publications un-inc.
NNTP-Posting-Host: odin.ins.cwru.edu


This is probably a FAQ... but... 

is there an archive someplace with documentation for various terminals?

Later.
Dan
-- 
Dan Brown	
brown@ins.cwru.edu
From: cjr@ssissi.UUCP (C. J. Rhea)
Newsgroups: comp.terminals
Subject: Wyse-60 parts/repair??
Keywords: Wyse 60
Date: 25 Sep 92 14:12:39 GMT
Distribution: usa
Organization: Supercomputer Systems, Inc. -- Eau Claire, WI

Does anybody have any info on:

1. A place that will trade/sell parts for a Wyse-60
2. Service information (schematics) on a Wyse-60.

I have a couple of Wyse-60s that have gone south. Both died in the
power supply section of the board and I am having NO luck in
figuring it out (without schematics).

A co-worker said that she once saw a place that would trade system boards
for $50. She doesn't remember where it was.

Anybody know of a place that does this???

--- Cris

Cristopher J. Rhea
Staff Engineer
Supercomputer Systems, Incorporated
...uunet!ssi!cjr
ssi!cjr@uunet.uu.net
cjr%ssi.uucp@uunet.UU.NET
From: avirmani@riches.rutgers.edu (Aashu Virmani)
Newsgroups: comp.terminals
Subject: NCR 7900
Keywords: configuration info..
Date: 30 Sep 92 05:53:39 GMT
Organization: Rutgers Univ., New Brunswick, N.J.
Cc: avirmani


I recently acquired an NCR 7900 and would appreciate any help with
setting it up with my 2400 baud modem.  It is supposed to be (so I
heard) just the same as an adds veiwpoint terminal..  Does anyone know
something about this one?  
Are there any key(s) that I could press to enter into a configuration
mode like you do on the VT100's..?  Any kind of info coul be helpful.

Thanks in advance,

- Aashu
-- 

 - Aashu Virmani (avirmani@paul.rutgers.edu)
   Hill 355,  932-3213
   Dept. of Computer Science,  
   Rutgers University, Piscataway, NJ 08855.
From: adrian@csqx.cs.rhbnc.ac.uk (A Johnstone)
Newsgroups: comp.cad.cadence
Subject: Re: How do I print out waveforms from Cadence VHDL ?
Date: 30 Sep 92 14:18:27 GMT
Reply-To: adrian@csqx.cs.rhbnc.ac.uk (A Johnstone)
Organization: Dept of Comp Sci, Royal Holloway & Bedford New College Uni London

In article <1abq6aINNb72@usenet.INS.CWRU.Edu>, bz302@cleveland.Freenet.Edu (Vince Pirat) writes:
| 
|> o The snapshot program (in OpenWindows) doesn't work with 
|> the waveform window and gives a blank frame as a result.
|> 
|> o The 'screendump' program works fine but the conversion from the
|> raster file to a postscript file gives a rather weird result
|> on the paper.
|> 
|> Does anyone have any idea on this problem ?
| 

If you can't get the built in printing functions going  I suggest you get hold
of the latest version of John Bradley's excellent xv program. As of version 2.1 
it has the ability to grab the contents of another X-window and output it in 
any of its supported formats, including Postscript. It will also let you scale
and rotate the image.

                        Adrian
From: adrian@csqx.cs.rhbnc.ac.uk (A Johnstone)
Newsgroups: comp.cad.cadence
Subject: Portrait postscript from Edge?
Date: 30 Sep 92 14:21:43 GMT
Reply-To: adrian@csqx.cs.rhbnc.ac.uk (A Johnstone)
Organization: Dept of Comp Sci, Royal Holloway & Bedford New College Uni London

This is kind of embarrassing, because there must be a simple answer but...

I'm plotting from Edge using the plotter type 'lw' which produces postscript.
By default the plots are scaled up to fit the whole page, although I can use
the scale button to keep them small. However, I now want to include some
plots in a LaTeX document and I need them to have Portrait orientation rather
than the Landscape that Edge usually puts out. How do I achieve this?

                         Adrian
Newsgroups: comp.cad.cadence
From: lsto@huldra.tdata.no (Lech Slawomir Tomczak)
Subject: Verilog-HDL Mode for emacs
Organization: Tandberg Data A/S, Oslo, Norway
Date: Tue, 29 Sep 1992 10:15:56 GMT
X-Newsreader: Tin 1.1 PL3

[ Article crossposted from comp.emacs ]
[ Author was Lech Slawomir Tomczak ]
[ Posted on Mon, 28 Sep 1992 13:11:25 GMT ]

Does anybody have a Verilog-HDL mode for emacs?
If so, please mail to lsto@tdata.no

Lech Tomczak, Tandberg Data A/S, Oslo, Norway
Newsgroups: comp.cad.cadence
From: brad@titan.austin.ibm.com (Brad Garton)
Subject: Xilinx and FPGAs ( second try )
Reply-To: brad@titan.austin.ibm.com  (Brad Garton)
Organization: IBM Advanced Workstation Division
Date: Tue, 29 Sep 92 22:07:20 GMT

Is anyone out there using Verilog to enter FPGA designs? 
Particularly I am interested in Xilinx and CLI ( Concurrent
Logic Incorporated ) Static Ram based FPGAs. What Models are 
available from third parties? 

Thanks, 
Brad  


___________________________________________________________
| Brad Garton  (512) 838-1333 | brad@titan.austin.ibm.com |
| I speak for myself not IBM  | VNET: GARTON AT AUSTIN    |
+---------------------------------------------------------+
From: cliffc@tekeda.PEN.TEK.COM (Clifford E Cummings)
Newsgroups: comp.cad.cadence
Subject: Re: Concept Package
Summary: Avoid Concept, Use Composer
Keywords: Concept, Composer, Verilog, Cadence, Simulation
Date: 29 Sep 92 17:57:30 GMT
Article-I.D.: tekig7.7120
Organization: Tektronix, Inc., Beaverton,  OR.

In article <1992Sep27.172512.29654@chpc.org> jimc@chpc.org (Jim Crocker) 
writes:
>
>Does anyone have any comments, good or bad, about the Concept
>Package from Cadence?  Our existing needs are quite simple:  We need
>a good schematic capture package that allows us to create a Verilog
>netlist for system simulations, and an Allegro netlist for PCB creation.
>
>Any comments you can offer concerning its strengths, weaknesses, etc.
>would be much appreciated.
 
Do not use Concept, use Composer.
 
Concept will gradually be phased out in favor of Composer, plus we
at Tektronix have been told that the Composer-to-Verilog design 
environment is an well-integrated(?) set of tools.

At Tektronix we currently use Concept, but intend to migrate to
Composer within the next 1-1/2 years.

Taking a schematic from Concept into Verilog requires a third-
party translator called VCMP (available from Cadence) plus some
additional scripts (not available from Cadence). 

If you intend to use simulation models from LMC and incorporate
Xilinx designs, the translation and design flow are even more
difficult.

The knowledge to setup a Concept-to-Verilog design flow does not
appear to exist at Cadence. I have worked with Cadence Applications
Engineers from Washington, Oregon, California, and have worked
with Cadence Engineers in San Jose to implement a working design
flow, without success. 

An engineering group here at Tektronix, had developed a GED
(Concept predecessor)-to-Verilog design flow which included a number 
of scripts that they had written. With minor modifications, their
scripts gave us a working solution.

If anyone else is doing Concept-to-Verilog design work, I'd like
to hear from you. The exchange of information might be beneficial
to us both.

- Regards - Cliff Cummings - cliffc@tekeda.pen.tek.com
	    Senior Hardware Design Engineer / Verilog Trainer &
	    Verilog Simulation Support
From: arindam@cs.uwindsor.ca (Arindam Das)
Newsgroups: comp.cad.cadence
Subject: graph traversal
Keywords: Graph, prolog, C
Date: 2 Oct 1992 22:14:59 GMT

Hi !

I am implementing an automated mask layout generator for dynamic CMOS
circuits.

In the first part of my implementation, i am building a two-level logic
synthesizer in prolog. The input to the synthesizer is
the on-set and don't-care-set of minterms for multi-output
functions and the output is a set of connectivity
informations and a minimized switching graph 
which is an interconnection of transistors realizing 
the given functions. 

Now, In my program i need to do complex traversal of the graph.
I being at ease in using Prolog (Quintus Prolog), am using it
comfortably and i am finding that i can develop the code pretty
quickly.

However I have to defend the use of Quintus Prolog instead of C.

Could somebody in the net give me some advice and tips and points
for defending the use of declarative prolog instead of imperative C ?

thanx in advance

-arindam

Newsgroups: comp.cad.cadence
From: shiv@cs.man.ac.uk (Shiv Sikand)
Newsgroups: comp.cad.cadence
Subject: VHDL and Cadence
Date: 29 Sep 92 11:13:26 GMT

Is it possible to use VHDL with Edge ?

I have used verilog but now need access to VHDL.

Thanks in advance.
--
---------------------------------------------------
+ Shiv Sikand                                     +
+ AMULET Research, Department of Computer Science +
+ The University, Oxford Road, Manchester M13 9PL +
+ shiv@cs.man.ac.uk, +44-61-275-6149              +
+          ! I speak only for myself !   	  +
+   ---> Power savers do it asynchronously <---   +
---------------------------------------------------
Newsgroups: comp.cad.cadence
From: lpickup@xanadu.btv.ibm.com (Lance Pickup)
Subject: EDIFOUT
Date: Tue, 29 Sep 92 22:05:33 GMT
Reply-To: lpickup@vnet.ibm.com
Organization: IBM Technology Products

Hello Cadence users,

I have a large schematic I am trying to export EDIF for.  Actually,
I have two large schematics, each one having two levels of hierarchy:
my top-level, and a bunch of underlying symbols.  What I would like
is that the EDIF I get out contains a library statement with the
reference library for all my symbols, and then each symbol also
defined in the EDIF (i.e. a hierarchical output).

  This works fine with EDIFOUT on one of my schematics which contains
about 600 underlying symbols.  I get 600 symbol defintions in the
EDIF followed by my circuit which calls out those symbols.  However,
the large circuit which contains around 1400 symbols, doesn't produce
the desired symbol definitions.  Instead, it looks like it just
didn't bother to output the reference library at all.  It didn't
even output an external library reference (that you would get if
you specified the reference library as an External Library in the
EDIFOUT form).  I didn't change any of the EDIFOUT options between
the two runs of EDIFOUT.

  Have I run into some undocumented limit in the number of reference
symbols you can output EDIF for?

  Thanks for any help anyone can provide.

--
    ...Lance

-----------------------------------------------------------------------
Lance Pickup                VNET/IBM Internet: lpickup@btv
IBM/Vendor Systems                   Internet: lpickup@vnet.ibm.com
Technology Products
Burlington, VT                          Phone: (802) 769-7104 (tie 446)
-----------------------------------------------------------------------
From: cwp@idtinc.UUCP (Chuck Phillips)
Newsgroups: comp.cad.cadence
Subject: Re: East coast users group
Date: 28 Sep 92 15:23:51 GMT
Distribution: usa
Organization: Integrated Device Technology, Santa Clara

In article <90431@netnews.upenn.edu> ekenberg@down.hep.upenn.edu (Tor L. Ekenberg) writes:
>Hi,
>
>	I have heard that there actually exists a Cadence User's Group on
>the East Coast. Is this true? If it is, I'd be interested in hearing about
>their plans for a meeting in the near future. Could anybody also tell me
>who the officers are and how I can reach them.
>
>	Thanks,
>
>				- tor
>

I've heard this rumor too. The way I understand it is that there used to
be one but the folks running/planning/coordinating it are no longer able
to do so. Cadence is looking for someone to volunteer to start it up
again. I am the Chair for BACUP (Bay Area Cadence User People) and it
really does not take that much time.

If you (or anyone!!) are interested in getting the group started again
contact:

Denise Jiminez
Cadence Design Systems
555 River Oaks Parkway
San Jose, CA 95134
MS 6A2
(408)894-3438
e-mail: djiminez@cadence.com

Denise and her staff will be happy to help get things rolling. I'm not
sure but I think you may even be able to hold the first meeting at the
local Cadence office near Boston.

===================================================
|Chuck Phillips                                   |                          
|Integrated Device Technology, Inc                |
|2670 Seeley Ave                                  |
|San Jose, CA 95134                               |
|(408)944-2052                                    |
|(408)944-2195 (FAX)                              |
|uunet.uu.net!idtg!cwp                            |
|International Cadence User Group - Co-Chair      |
|Bay Area Cadence User People, BACUP, Chair       |
===================================================
From: arindam@cs.uwindsor.ca (Arindam Das)
Newsgroups: comp.cad.cadence
Subject: defend SKILL
Keywords: SKILL, layout
Date: 4 Oct 1992 02:40:24 GMT


 hi !
 
  i am implementing a layout generator
 input to which is : minterms and don't cares for multioutput functions
 output is : the SKILL code (which when run will generate the layout)
i am developing my generator in PROLOG
 
 Q 1. In most of the industries in general, what is the language in 
     which the target code is produced ? I don't think it is SKILL.
     How can i get more info about that language ?
 
 I am asking this because I have to defend why am i producing skill code
 and why not in some other language of industry standard ? 

 Please give me some detailed tips so that i can defend successfully.
 Also I got to know How the design process goes in Cadence. Say:

1 You write the skill code 
2. Then what does the Skill interpreter output ?
..... and so on

which vol of Edge should i look into to know the details about the d
process ? 
 
 
 thanx in advance.
 
 -arindam
From: arindam@cs.uwindsor.ca (Arindam Das)
Newsgroups: comp.cad.cadence
Subject: Repost: assigning value to property in prop-list
Keywords: edge, propertylist, cmos4s, layout
Date: 29 Sep 1992 19:39:37 GMT

Hi !

I forgot to mention that I am talking regarding layout
in my previous posting.

i have few questions here:

1. for all the metal2 pins on the same metal2 drawing object(rectangle)
   i assign same value for FormalTerminal/name for all those pins.

    But is it necessary to put a value to the FormalPin/name of each of
    those pins or i should keep them blank (i.e. null strings) ?

2. in a layout,  suppose i have to input signal from the same source
   to two pins which are not connected to each other physically.
   For the purpose  of simulation will it be enough to put the same value
   to the FormalTerminal/name in each of the property list of those pins ?   Also, how should i take care of their FormalPin/name ?
From: arindam@cs.uwindsor.ca (Arindam Das)
Newsgroups: comp.cad.cadence
Subject: property list again
Keywords: layout, Edge, skill, metal pin
Date: 1 Oct 1992 18:06:17 GMT

hi !

in a layout, when i try to edit the property Net/type in the property list
of a metal (metal or dmetal) pin, i can't do it. Now I have to change
(I think i have to; I am not sure)
the value of that property to "supply" or "ground" or "clock" for power,
or gnd or clock line respectively instead of the default value "signal".

If the changing of the default value "signal" is necessary in the above case,
how can i do that ? In the long run i have to use skill function to do the same.
Could someone help me ?


another problem:

when i try to assign same value (string) to the property FormalTerminal/name
i get an error message 

"node conflict:node already labelled IN" 

at the top left corner of screen. 

However in either Place and Route  or in Design Entry of Edge, it has been
said that instead of connecting two points physically, they can be given
the same name. I don't know why am i getting the error message then.  

-arindam
From: arindam@cs.uwindsor.ca (Arindam Das)
Newsgroups: comp.cad.cadence
Subject: assigning value to property in prop-list
Keywords: edge, propertylist, cmos4s
Date: 29 Sep 1992 16:22:06 GMT

hi !

thanx to all who replied to my printing problem.


i have few questions here:

1. for all the metal2 pins on the same metal2 drawing object(rectangle)
   i assign same value for FormalTerminal/name for all those pins.

    But is it necessary to put any value to the FormalPin/name of each of those pins
    or keep them blank (i.e. null strings) ?


2. suppose i have to input signal from the same source to two pins
   which are not connected to each other physically. For the purpose
   of simulation will it be enough to put the same value to the
   FormalTerminal/name in each of the property list of those pins ?
   Also, how should i take care of their FormalPin/name ?

Xref: sparky comp.cad.cadence:370 comp.arch:9711
From: gints@roadkill.esd.sgi.com (Gints Klimanis)
Newsgroups: comp.cad.cadence,comp.arch
Subject: Re: Voice Input
Date: 29 Sep 92 19:37:18 GMT
Organization: Silicon Graphics, Inc.

In article <1587@seqp4.sequoia.com>, jcooley@seqp4.sequoia.com (John
Cooley) writes:
|> 
|> > From: gints@roadkill.esd.sgi.com (Gints Klimanis)
|> > 
|> > You get effective isolated word, speak independent recognition for
|> 1 MIPS.
|> > 
|> > How about a few hundred draftspersons talking on their telephones? 
|> In
|> > my daily experience with speech input for wordprocessing and
|> drawing,
|> > the speech input would reduce the mechanics for layout.  Another
|> > productivity bottleneck opened.
|> > 
|> > Most excellent.
|> 
|> From my very limited understanding of Voice Input systems, I would
|> think that maintainance and bug chasing would be quite complicated
|> because these systems are typically trained on one specfic person's
|> voice.  Is this true?

CHeck out first line: speak independent
From: acadams@afterlife.ncsc.mil (Arthur C. Adams)
Newsgroups: comp.cad.cadence
Subject: Skill Mode for emacs
Date: 29 Sep 92 19:12:52 GMT
Organization: The Great Beyond

In article <1992Sep29.101556.2932@huldra.tdata.no> lsto@huldra.tdata.no (Lech Slawomir Tomczak) writes:
>
>Does anybody have a Verilog-HDL mode for emacs?
>If so, please mail to lsto@tdata.no
>

For that matter, does anyone have a Skill mode?
-- 
Proud to be part of the cultural elite!
What the gamemasters wilt shall be the whole of the law.
	- Motto of the Hellfire Club, live-action roleplaying GM's
Arthur C. Adams (not the comic-book artist)                        <fnord>
Xref: sparky comp.cad.cadence:366 comp.misc:3803
From: aberno@ee.ubc.ca (Anthony Berno)
Newsgroups: comp.cad.cadence
Subject: ROMs and Adders
Date: 2 Oct 92 17:59:49 GMT
Article-I.D.: ee.1992Oct2.175949.3516
Organization: University of BC, Electrical Engineering

Hi! Does anyone know how to layout out ROMs in Edge (Cadence)?
Are there any adder blocks available?

Thank you.				Anthony Berno
Newsgroups: comp.cad.cadence
From: keiths@Cadence.COM (Keith Sabine)
Subject: Re: Cadence Users
Organization: Cadence Design Systems, Inc.
Date: Fri, 25 Sep 1992 15:12:45 GMT

In article <502@idtinc.UUCP> cwp@idtinc.UUCP (Chuck Phillips) writes:
>
>You should have no problem (from Cadence) in buying the tutorial once it
>is available. If you can not get Inside Skill let me know and I will look
>into the matter. I do not know your individual situation but have heard
>from others that Europe is a tough place to be a customer.
>

Just for the record, "Inside Skill" was written by Ian Dobinson,
James Kenney and Peter Hutton. All work for Cadence Consulting
services in Abingdon, England. There should be no problem getting
a copy in Europe, therefore... 


Keith.

*-----------------------------------------------------------------------------*
* Keith Sabine                              Phone: (44)-344-360333            *
* Cadence Design Systems UK Ltd,            Fax:   (44)-344-360324            *
* Bagshot Road,                             Email: keiths@cadence.com         *
* Bracknell,                                                                  *
* England RG12 3PH                                                            *
*-----------------------------------------------------------------------------*
From: nir@zoran.hellnet.org (Nir Sever)
Newsgroups: comp.cad.cadence
Subject: Interpreted labels on sheet symbols
Keywords: interpreted labels
Date: 30 Sep 92 10:41:38 GMT
Organization: Zoran Microelectronics LTD. Haifa, Israel.

Hi,

I'm trying to create a sheet symbol that will dynamicaly display the library and
cell name of the current cell.

I used interpreted labels on the sheet symbol, but this would't work since it
shows the properties of the instance, not those of the cell where the instance
is placed, so the label [@cellName] gives Asize, and not the true cell name.

I've tried creating an ILLable (ILL ???), but I coudn't find the pointer to the
current instance.

Has anybody done anything like this? Please note, It's important for me that
this will be an interpreted label, based on built in properties.

Thanks,
-- 

    Nir (Samburski) Sever,            Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: nir@Zoran.HellNet.Org
    Advanced Technology Center
    Haifa 31204, Israel
Newsgroups: comp.cad.cadence
From: doug@DSG.Tandem.COM (Doug Bering)
Subject: GED/Concept moving to Composer
Organization: Tandem Computers
Date: Fri, 2 Oct 1992 18:02:38 GMT

We are a customer of Cadence that currently uses GED for design capture, Verilog for simulation, and Allegro for board layout.  Cadence has told us that very shortly, GED is no longer going to be supported.  They indicate that CONCEPT is a direct replacement for GED, but support for it is also planned to be phased out (Concept will be around until sometime in 1994).  Their recommendation is that we move to COMPOSER; a capture tool migrating from their IC product line.

Well, I've spent a couple months looking at COMPOSER and the migration effort to move from GED to it, and I've got mixed emotions.  Some of the functionality of Composer looks pretty good compared to GED.  Some of the obstacles to moving seem pretty severe.

What I'd like to know is what you other GED/CONCEPT users think about this move?
What are you doing to replace GED?  Where does CONCEPT fit in your scheme of things?  What are your impressions of Composer and the migration effort?  Are you planning to move libraries from one system to another?  How?  Are you planning to move existing designs from one system to the other?  How?  Do you have any scripts or programs that access the GED ASCII files, and if so, how are you planning to provide those capabilities with COMPOSER?  What are your impressions of SKILL as a data access language?

As you can see, I'm just bubbling with questions (anxiety?) about this whole conversion process.  I'll summarize whatever people send me and let the rest of you know what we, as Cadence customers, think of this impending change.
							Doug B.