From: martin@math.rwth-aachen.de (  Martin Schoenert)
Subject: Multiplication on your favorite CPU (summary)
Organization: Rechnerbetrieb Informatik  /  RWTH Aachen
Date: 30 Sep 92 12:44:57 GMT

A while ago I asked for information about the multiplication instructions
of various CPUs.   Here is my summary.  In the following 'latency'  means
the number  of cycles from the issue of the multiplication instruction to
the first instruction that can access the result.  'pipelined' means that
several multiply instructions can  work their way through the pipeline at
once.  'independent' means that other instructions can be issued  while a
multiplication instruction is running.

Points where I still don't have the information or where I am not certain
are  marked with  '???'.  I would appreciate if someone could  fill those
holes.  Of course corrections would also be very wellcome.


DEC Alpha (21064):

  32x32 -> 64:      MULQ (is actually 64x64 -> 64)
    source:         <register> x <register or 8bit immediate>
    destitation:    <register>
    latency:        23 cycles
    pipelined:      no
    independend:    yes

  64x64 -> 128:     MULQ (lower 64 bits) & UMULH (higher 64 bits)
    source:         <register> x <register or 8 bit immediate>
    destination:    <register> & <register>
    latency:        23 (MULQ) + 23 (UMULH)
    pipelined:      no
    independent:    yes


Hewlett-Packard PA-RISC 1.0:

  32x32 -> 64:      no


Hewlett-Packard PA-RISC 1.1 (PA7[01]00):

  32x32 -> 64:      XMPYU
    source:         <fp-register> x <fp-register>
    destination:    <fp-register>
    latency:        3 (PA7000)                      2 (PA7100)
    pipelined:      every other cycle (PA7000)      fully (PA7100)
    independent:    yes                             yes (superscalar)
    comment:        one must go through main memory to get operands from
                    the <int-register>s into the <fp-register> and back.


IBM RS6000:

  32x32 -> 64:     mul
    source:        <register> x <register>
    destination:   <register> (low) & <register+1> (high) ???
    latency:       11 cycles (includes 6 cycles for sign correction)
    pipelined:     ???
    independent:   ???


Inmos Transputer T9000:

  32x32 -> 64:      LMUL
    source:         <stack-top> x <stack-top-1> ???
    destination:    <stack-top>
    latency:        3-6 cycles
    pipelined:      no
    independent:    yes (but no other arithmetic)
    comment:        LMUL also takes a carry in and generates a carry out,
                    so that it can be cascaded very easily


Intel i[34]86:

  32x32 -> 64:      MUL
    source:         EAX x <register or memory>
    destination:    EAX (low) & EDX (high)
    latency:        9-41 cycles (if second operand is in a register)
                    (<mult> == 0 ? 9 : max(<pos-leading-bit>,3) + 9) ???
                    are the timings the same for the i486 ???
    pipelined:      no ???
    independent:    no ???


Intel 960CA/CF:

  32x32 -> 64:      EMUL
    source:         <register> x <register>
    destination:    <register-i> (low) & <register-i+1> (high)
    latency:        4 cycles
    pipelined:      no ???
    independent:    yes


MIPS R[23]000:

  32x32 -> 64:      MULU
    source:         <register> x <register>
    destination:    lo-register (low) & hi-register (high)
    latency:        12 cycles
                    +2 cycles to move results from lo-hi-registers
    pipelined:      no
    independent:    yes
    comment:        the maximal bandwidth is not one product every 14 cycles
                    but one product every 16 cycles because the 2 instructions
                    after 'mflo' and 'mfhi' must not be 'mulu'.


MIPS R4000:

  ???


Motorola 680[01]0:

  32x32 -> 64:      no
  32x32 -> 32:      MULU.W
    source:         <d-register> x <d-register or memory>
    destition:      <d-register>
    latency:        ???
    pipelined:      no
    independent:    no


Motorola 680[234]0:

  32x32 -> 64:      MULU.L
    source:         <d-register> x <d-register or memory>
    destition       <d-register> (low) & <d-register> (high)
    latency:        41-44 cycles (68020)
                    (are the timings the same for the 680[34]0 ???)
    pipelined:      no
    independent:    no


Motorola 88100:

  32x32 -> 64:      no
  32x32 -> 32:      yes (name ???)
    source:         <register> x <register>
    destition:      <register>
    latency:        4 cycles
    pipelined:      yes
    independent:    yes


SPARC V7:

  32x32 -> 64:      MULSCC (multiply step)
    source:         <register> x y-register
    destination:    <register> (low) & y-register (high)
    latency:        37 cycles (includes sign correction)
                    +2 cycles to move operand to and result from y-register
    pipelined:      no
    independent:    no


SPARC V8 (SuperSPARC):

  32x32 -> 64:      UMUL[CC]
    source:         <register> x <register>
    destination:    <register> (low) & y-register (high)
    latency:        4 cycles
                    +1 cycles to move result from y-register
    pipelined:      no
    independent:    no


I would like to thank

    Anton Martin Ertl (anton@mips.complang.tuwien.ac.at)
    David Fox (davidfox@zorch.sf-bay.org)
    Torbjorn Granlund (tege@sics.se)
    Guy Harris (guy@auspex.com)
    Mitch Kahn (mkahn@hopi.intel.com)
    Thomas D. Maier (tm17@prism.gatech.edu)
    Dale Morris (morris@nsa.hp.com)
    Andrew Payne (payne@crl.dec.com)
    Guillermo J. Rozas (jinx@zurich.ai.mit.edu)
    David Shepherd (des@frogland)
    Richard Trauben (Richard.Trauben@Eng.Sun.COM)
    Shankar Unni (shankar@wpd.sgi.com)
    Jan Vorbrueggen (jan@pallas.neuroinformatik.ruhr-uni-bochum.de)
    Will Walker (wlw@hpfcso.FC.HP.COM)
    Andrew Wolfe (awolfe@moo.princeton.edu)

for their comments and explanations.

Martin.

--
Martin Sch"onert,   Martin.Schoenert@Math.RWTH-Aachen.DE,  +49 241 804551
Lehrstuhl D f"ur Mathematik, Templergraben 64, RWTH, D 51 Aachen, Germany
Newsgroups: comp.arch