HDTenEightyP/NetNews huggingface dataset:
From: magrana1!rob@uunet.UU.NET (Rob Duncan)
Subject: Potter's ASC stuff
Apparently-To: uunet!comp-parallel
Organization: Pomegranate Technology, Inc.
Date: Wed, 23 Dec 1992 05:59:25 GMT

Does anyone know whether it's possible to pick up J. L. Potter's
compilers and emulators for associative processors (known as ASC
software) via anonymous ftp or email?  I know that they're available
on cartridge for a nominal cost.

The snail-mail address is at Kent State University: any guesses as to
an email address?

Thanks,

-- 
Rob Duncan                                       Talk: +1-415-325-8780
Pomegranate Technology, Inc.                      Fax: +1-415-325-8780
235 Embarcadero Road               UUCP: ...!uunet!magrana1!rob.duncan
Palo Alto, CA 94301               Internet: rob.duncan@pomegranate.com

Newsgroups: comp.parallel
From: chaumett@labri.greco-prog.fr (Serge CHAUMETTE)
Subject: REFERENCE NEEDED, URGENT
Organization: Laboratoire Bordelais de Recherche en Informatique
Date: 18 Dec 92 07:59:54 GMT


 I'm looking for any reference regarding the Jade system.
I guess it is a debugging set of tools for distributed machines.

Especially important is the following reference:

 TOCS 1987

 I cant remember what TOCS means !!!

 Any pointer greatly apreciated.

s.c.



-- 
*----------------------------------*------------------------------------*
|         Serge CHAUMETTE          |                                    |
|              LaBRI               |                                    |
|Laboratoire Bordelais de Recherche|phone : (+33) 56 84 69 04           |
|          en Informatique         |fax   : (+33) 56 84 66 69           |
|       Universite Bordeaux I      |e-mail: chaumett@labri.greco-prog.fr|
|    351, Cours de la Liberation   |                                    |
|    33405 TALENCE Cedex, FRANCE   |                                    |
*----------------------------------*------------------------------------*

Newsgroups: comp.parallel
From: Robert Manchek <manchek@cs.utk.edu>
Subject: comp.parallel posting
Organization: Clemson University
Date: Wed, 23 Dec 92 16:43:44 EST

              PVM version 2.4.2 is now available on netlib.
              ---------------------------------------------


This distribution contains a new, rewritten, Fortran library (libfpvm)
that's easier to use than the old f2c library.  The old library will
still be included for those who don't want to switch.  It also contains
numerous fixes for minor bugs in the source and documentation and a few
new ports.

Note:

This version (2.4.2) is semi-compatible with version 2.4.1.  Pvmds of
the two versions should interoperate correctly.  Programs linked with
one version of libpvm.a will not work with a (local) pvmd of the other
however, because the libpvm-pvmd protocol has changed.  The simplest
solution is to recompile your applications with the new libraries.

How to get it:

To get an index of pvm-related files, send mail to "netlib@ornl.gov"
with the words "send index from pvm" in the subject line or message
body.  To get the source code request "send pvm_tar from pvm".


/ Robert Manchek                University of Tennessee     /
/                               Computer Science Department /
/ (615)974-8295                 Ayres Hall #104             /
/ manchek@CS.UTK.EDU.           Knoxville TN  37996-1301    /


Newsgroups: comp.parallel
From: fpst@hubcap.clemson.edu (Steve Stevenson-Moderator) 
Subject: Season's Greetings....
Organization: Clemson University
Date: Mon, 21 Dec 1992 20:51:54 GMT

Well, the students have just about all gone home for the holidays. And I've
got to admit, I'm glad for the brief respite. I'll post sporadically over
the next week.

Here's hoping wherever you live on this planet that the next 365 days are
the best possible for you and your families. Here's also hoping we have some
peace for a while and that everyone might get along, just this once.

Season's Greetings from Steve, Kathy, Kristen and Scott Stevenson.

Newsgroups: comp.parallel
From: jwang@sys.toronto.edu (Jingwen Wang)
Subject: Re: Torus vs. Hypercube
Organization: Clemson University
Date: 	Wed, 30 Dec 1992 11:46:56 -0500

maniattb@cs.rpi.edu (Bill Maniatty) writes:

>|> Is the 4^k torus isomorphic to the binary 2k-cube?
>|> 
>|> The answer and the proof (which I found quite fun) is left as an excercise
>|> to the reader.
>|> 
>|> -steve

>Is this a closely guarded corporate secret :-) ?

   The thoery is: when the dimension size (num of nodes along each dimension)
   is fixed at 4, a k-d torus is exactly a 2k-d binary hypercube.

   J. Wang at el., "On the communication structures of hyper-ring and hypercube
   multi-computers", J. of Computer Sci. and Technology, vol. 4, No. 1, 
   Jan. 1989.

jwang
--
  {}
{}(){} -----> Jingwen Wang, Univ. of Toronto       (416)-978-1675 (office)
  {}          jwang@sys.toronto.edu                1-800-ASK-wang (home)


Newsgroups: comp.parallel
From: sundaram@eng.uiowa.edu (Subbiah Sundaram)
Subject: Info requested on Parasoft Express and SR.
Apparently-To: comp-parallel@uunet.uu.net
Organization: Department of Elect. and Comp. Engr., University of Iowa, USA.
Date: Wed, 30 Dec 1992 16:01:13 GMT

[This is certainly a FAQ. If someone would collect the answers (or if you
 have the last thread) and send it to me at fpst@hubcap.clemson.edu, I'll
 put the results in a FAQ file on parlib.
 
 There is already some info on Express in parlib

]



Hi Netters:

I would like to have some info on Parasoft Express and SR. 
I think sometime back there was a discussion in this newsgroup
about Parasoft Express. If some one has collected information 
from that please send me a copy.

Thanks,
Subbiah.




Newsgroups: comp.parallel
From: raj@mcs.kent.edu (Srinivas Rajagopalan)
Subject: Info. sought about PARFORM
Apparently-To: comp-parallel@uunet.uu.net
Keywords: Parallel Computing, Distributed Environment 
Organization: Kent State University
Date: Wed, 30 Dec 1992 17:59:06 GMT

  I would like to get some info about the system, PARFORM 
  I guess it is developed at Univesity of Zurich, Switzerland

  Thanks in advance
   
   srinivas
    raj@mcs.kent.edu

Newsgroups: comp.parallel
From: landry@csgrad.cs.vt.edu (Kenneth Landry)
Subject: I need Linda programs
Organization: VPI&SU Computer Science Department, Blacksburg, VA
Date: 21 Dec 92 03:16:23 GMT




  I am currently working on my PhD in the area of programming languages.  
  More specifically, I am using instruction decomposition and code motion 
  to parallelize activities in programs (both serial and parallel).  
  I am using Linda as a basis for my optimizations and am looking for any 
  Linda programs that I can use to test out my optimizations.

  If you have ANY Linda programs (no matter how small), know where I can 
  find some Linda programs or even know someone who has written some, I 
  would appreciate any and all help.  If it is possible, I will make 
  available the programs I receive.



Kenneth D. Landry             landry@vtopus.cs.vt.edu
ISE/MSL                       (703) 231-3556
Virginia Tech
1900 Kraft Drive
Blacksburg, VA 24060

Newsgroups: comp.parallel
From: sun@elc04.icase.edu (Dr. Xian-He Sun)
Subject: IPSW'93 workshop on Scalability  of  Parallel Algorithms and Architectures
Organization: ICASE/NASA Langley
Date: 31 Dec 1992 14:20:13 GMT



                      *********************
                         CALL FOR PAPERS
                      *********************


        7th International Parallel Processing Symposium Workshop 

                               on

     Analyzing  Scalability  of  Parallel Algorithms and Architectures

                 April 1993,         Newport Beach, California




Motivation and Objective:
 
Scalability of a parallel computer system denotes the degree to which
the system can effectively use increasing number of processors.
Scalability analysis could be used to predict/analyze performance
when the parallel computer is scaled up in terms of number of
processors, processors speed and the speed of communication.
It could be used for designing better parallel algorithms and architectures.
The need for a concept of scalability both with respect to the
architecture and the algorithm (implemented on the architecture) has
been well established.
Yet, there is no consensus on how the scalability of a
parallel system should be determined.


The objective of this workshop is to critically assess the state of the art
in the theory of scalability analysis, and motivate further research. 
The workshop will bring together research
done by theoreticians, application developers, and  designers of architectures 
and system software on scalability analysis of large-scale parallel systems. 
Topics of interest include but are not limited to  
Scalability metrics, Scalability analysis of parallel algorithms, applications,
and architectures, Cost effectiveness of scaling parallel architectures
in terms of performance,  software tools for scalable parallel systems.
The workshop will consist of invited as well as contributed  presentations by 
various researchers, and discussion sessions involving presenters 
and participants.

Two copies of an extended abstract (preferably no more than 4 pages) 
should be sent to each of the workshop chair by February 1, 1993.
The authors will be notified of the decision by March 1, 1993. 

-----------------------------------------------------------------------
Workshop Cochiars


                             Vipin  Kumar
                       Computer Science Department
                Army High peformance Computing Research Center
                         University of Minnesota
                          Minneapolis,     MN    55455
            Tel: 612-624-8023,   FAX: 612-625-0572,   kumar@cs.umn.edu 

                             Xian-He Sun
                                ICASE
                        NASA Langley Research Center
                           Hampton, VA 23681-0001
             Tel: 804-864-8018,   FAX:804-864-6134,  sun@icase.edu 
-----------------------------------------------------------------------

Newsgroups: comp.parallel,comp.unix.programmer,comp.sys.intel.
From: sundaram@eng.uiowa.edu (Subbiah Sundaram)
Subject: Bus arbitrator and lock implementation
Apparently-To: comp-parallel@uunet.uu.net
Organization: Department of Elect. and Comp. Engr., University of Iowa, USA.
Date: Thu, 24 Dec 1992 16:53:48 GMT

I would like to know the way locks are implemented in systems
like the Encore. I want the hardware details and the way it works.
It would be nice if someone could point out to me a good reference 
material on this topic. I would also like to know more about 
bus arbitrator design. (In particular I would like to know about 
the bus arbitrator implementations on shared memory parallel
machines.(Books, papers, articles, etc.))

Thanks,
Subbiah.


Newsgroups: comp.parallel
From: (Stephan Gutzwiller) gutzi@ifi.unibas.ch
Subject: Re: BAKS: Basler Algorithmen Klassifikations-Schema
Organization: Clemson University
Date: Thu, 24 Dec 92 11:14:56 +0100

hi Stephen, 
	it is true, that we have such a report. currently there is
only the german version available. We are tranlating it jus now and
hope to finish early in january. If you are interested in the german
version then you can pick up a postscript file via anonymous ftp 
from 

lucy.ifi.unibas.ch

in the directory 

bacs

the file was created with a NeXT and we tested it on macintoshes with
sendps. The paper size is european standard A4 wich might be a little
problem because we have very small margins. 

I will send you a mail as soon as the report is translated. hope that
helps and merry christmas and a happy new year

Stephan


Newsgroups: comp.parallel
From: 2575brooksr@vmsf.csd.mu.edu (Ryan K. Brooks)
Subject: Re: Torus vs. Hypercube
Reply-To: 2575brooksr@vmsf.csd.mu.edu
Organization: Marquette University - Computer Services
Date: 28 Dec 1992 16:54:30 GMT

In article <1992Dec27.201910.28352@ee.eng.ohio-state.edu>, bai@rainier.eng.ohio-state.edu (Baback A. Izadi) writes:
>Couple of weeks ago, I think heard a speaker claiming that
>2-dimensional Torus and hypercube have basically the same
>topology. How could this be true? If it is, can someone
>point me to some references?

Simple.  A 2-D hypercube is a square and a 2-D torus is a ring (loop).  Each
node is only connected to the next node in both topologies. (Imagine a ring
with four evenly spaced points.) See also: Hypercube Algorithms, Ranka/Sahni,
ISBN 0-387-97322-2, 1990. Chap 1 as I recall has a pretty easy-to-read
intro.

>Baback
 ----------------------------
 Ryan K. Brooks                        "You're never dead till you're        
 2575BrooksR@vms.csd.mu.edu                  out of quarters."     
 Marquette University EECE              
 NemeSys Corporation
 "Curtains for Windows" 

Newsgroups: comp.parallel
From: anshu@bass.bu.edu (Anshu Aggarwal)
Subject: Performance Evaluation of the MasPar MP-1
Followup-To: comp.parallel
Keywords: MasPar MP-1, Network Bandwidth
Reply-To: anshu@bass.bu.edu (Anshu Aggarwal)
Organization: Boston University
Date: 31 Dec 92 16:47:36 GMT


Hello, does anyone have any ideas where I can get information about
the performance evaluation of the MP-1's communication network? 



--
						   - Anshu Aggarwal
						     (anshu@bass.bu.edu)
"Morality is the herd-instinct in the individual."
				      	- Friedrich Nietzsche

Newsgroups: comp.parallel
From: jeff@is.s.u-tokyo.ac.jp (Jeff McAffer)
Subject: Looking for concurrent systems monitoring stuff
Apparently-To: comp-parallel@ames.arc.nasa.gov
X-Bytes: 612
Reply-To: jeff@is.s.u-tokyo.ac.jp
Organization: University of Tokyo / Object Technology International
Date: Tue, 29 Dec 1992 09:07:54 GMT

I am conducting research into the behaviour (performance,
interaction...) of concurrent (parallel and distributed) systems.  As
such, I am looking for people who are talking about/interested in
instumentation of such systems and techniques for analyzing gathered
data.  

I'm not sure if this is the right news group.  If it is, what's
happening in these areas?  If not, could someone direct me to an
appropriate news group, mailing list, person (people).

References to conference and journal articles, books... would also be
gratefully accepted.

Thanks in advance.
--
--
ato de, |m        -- Death by stereo!

Newsgroups: comp.parallel
From: sscott@mcs.kent.edu
Subject: BAKS: Basler Algorithmen Klassifikations-Schema
Organization: Clemson University
Date: Wed, 23 Dec 92 23:51:51 EST

I understand that you have a technical report regarding the
classification of parallel algorithms.  I heard that an english version
is in the works....  and may be done by now.  Will you please forward
both the english and german versions of this document.  (or where they
may be obtained from)

Thank you,  Stephen.

---------------------------------------------------------------------------
Stephen L. Scott				Phone:  216-672-4004  x215
Heterogeneous Processing Research Group		voice mail:  x466
Kent State University				Fax:    216-672-7824
Math Sciences Building				email:  sscott@mcs.kent.edu
Kent, OH  44242


Newsgroups: comp.parallel
From: kaminsky-david@CS.YALE.EDU (David Kaminsky)
Subject: Re: Linda / The Parform
Organization: Yale University Computer Science Dept., New Haven, CT 06520-2158
Date: 21 Dec 1992 15:42:31 -0500

In article <1992Dec21.132725.23905@hubcap.clemson.edu> Steven Ericsson Zenith <z
enith@kai.com> writes:
>
>I find these numbers difficult to believe.
> ...
>Firstly, bells start ringing for the single processor case.  Why?
>Because they are all the same and to my knowledge these systems don't
>all use the same compiler.  I expect to see some variation.
>No indication is given of what the 1 processor time means - is this the
>sequential execution time under the respective system compiler?  It
>should be. The above numbers can only begin to make sense if the base
>compiler *is* the same in all cases - otherwise we do not know what we
>are comparing.
>

	I think I can answer some of Steve's concerns.

        When evaluating parallel systems, honest speedup is measured
against an optimized sequential code.  I believe that is what they
have done.  (I worked with them in producing the Linda measurements.)

>Since this problem is obviously more than embarrassingly parallel I'd
>like to know how much, if any, of the interaction mechanism was used
>during computation. If the answer is, as I suspect, that after the data
>and work distribution, insignificant interaction took place then the
>above tells us something about the parallel decomposition of the problem
>but sweet Fanny Adams about any of the systems tested.
>

        The problem examined was an iterative heat diffusion code.
The matrix is decomposed into blocks.  At each iteration, boundary
data is exchanged between pairs processors holding adjacent blocks.
The time measured was wallclock time.  For more information on the
algorithm used, I'd recommend reading the paper.

David


Newsgroups: comp.parallel
From: kostas@siemens.com. (Konstantinos Diamantaras)
Subject: Re: Torus vs. Hypercube
Organization: Siemens Corp. Res., Inc.
Date: Mon, 28 Dec 1992 22:04:33 GMT

In the following discussion torus means 2-D mesh with wrap-around. I am
not aware of higher dimensional toruses although can define them I assume.
The torus of P1xP2 processors has 2xP connections (P=P1xP2).
The hypercube of P processors has Pxlog_2(P)/2 connections
(each processor connects to log_2(P) neighbors). So even if
P is a power of 2 the torus cannot be the same as the hypercube.
Also P has to be a power of 2 for hypercube but this is not necessary
for a torus. However, for P=4 and P=8 a torus and a hypercube
are the same. Also I think all toruses can be embedded
into appropriate size hypercubes. For good reference see
Thomson Leighton "Introduction to Parallel Algorithms and Architectures"
Morgan Kaufman, San Mateo CA, 1992.

Hope this helps

		Kostas Diamantaras

Newsgroups: comp.parallel
From: dbg@SLAC.STANFORD.EDU (David B. Gustavson)
Subject: Re: Bus arbitrator and lock implementation
Apparently-To: <comp-parallel@uunet.uu.net>
Followup-To: comp.parallel,comp.unix.programmer,comp.sys.intel.
Organization: SLAC Computation Research Group
Date: Thu, 31 Dec 1992 05:30:12 GMT

In article <1992Dec28.160326.27290@hubcap.clemson.edu>,
sundaram@eng.uiowa.edu (Subbiah Sundaram) wrote:
> ... (In particular I would like to know about 
> the bus arbitrator implementations on shared memory parallel
> machines.(Books, papers, articles, etc.))
> 
It depends how parallel a machine you want. For small parallel machines,
where you can tolerate a bus backplane/bottleneck, you could look at IEEE
Std 896.1, Futurebus+, and 896.2. Futurebus+ has two arbiter schemes, one a
distributed bused one with many bits of priority for realtime scheduling
applications, and a faster one using centralized arbiter logic.

If you want a shared-memory parallel machine that can scale up to larger
applications, you should take a look at ANSI/IEEE Std 1596-1992, the
Scalable Coherent Interface. The concept of arbitration is quite different
there, because it was designed for a high degree of parallelism. It only
acts like a bus, providing bus-like services to the user--actually it uses
many independent links that can be active at the same time, performing
independent communications. SCI also defines multiprocessor synchronization
operations and locks that can be exported through an arbitrary interconnect
(ring, switch, mesh, whatever)--they don't use the strategy of bringing the
whole system to a momentary halt like the old bus-based locks did (using
read-modify-write operations and the bus bottleneck to best advantage).
However, if you're in a hurry, keep in mind that SCI isn't really available
yet (the SCI interface chip, which includes all the transceivers, FIFOs,
and protocol logic has slipped to Jan/Feb for the GaAs version, which
supports two 1-gigabyte/s links; the CMOS version isn't expected until
March, and will be slower but cheaper).

You can get the documentation on Futurebus+ or SCI from the IEEE the same
way you get any other IEEE standard. Let me know if you want more info on
SCI, I have a few Email status files I can mail you.

--------------------------------------------------------------
-- David B. Gustavson, Computation Research Group, SLAC, POB 4349 MS 88,
    Stanford, CA 94309   tel (415)961-3539  fax (415)961-3530
-- What the world needs next is a Scalable Coherent Interface!
-- Any opinions expressed are mine and not necessarily those
   of the Stanford Linear Accelerator Center, the University, or the DOE.

Newsgroups: comp.parallel
From: maniattb@cs.rpi.edu (Bill Maniatty)
Subject: Re: Torus vs. Hypercube
Apparently-To: comp-parallel@cis.ohio-state.edu
Organization: Clemson University
Date: Tue, 29 Dec 1992 22:08:12 GMT

In article <1992Dec29.210648.18508@hubcap.clemson.edu>, heller@Think.COM (Steve Heller) writes:
|> 
|> In article <1992Dec29.142815.27527@hubcap.clemson.edu> David Karr <karr@cs.cornell.EDU> writes:
|> 
|>    In article <1992Dec27.201910.28352@ee.eng.ohio-state.edu> bai@rainier.eng.ohio-state.edu (Baback A. Izadi) writes:
|> 
|>    >Couple of weeks ago, I think heard a speaker claiming that
|>    >2-dimensional Torus and hypercube have basically the same
|>    >topology. How could this be true?
|> 
	[Stuff Deleted]

The topology of the connections imbedded in the torus might make a 2
dimensional torus more connected than the corresponding hypercube.

Consider an 8 nearest neighbor connectivity with toroidal wrap, with O being
the central processor, the others labelled after the points on a compass:

           NW N NE
             \|/
            W-O-E
             /|\
           SW S SE

(a real world example of this is found in a MasPar MP-1),
which is more connected than the corresponding ``Manhattan'' style connection:

              N
              |
            W-O-E
              |
              S

If we look at a simple 2 dimensional hypercube (square)
versus the corresponding 8 nearest neighbor topology with toroidal wrap
the hypercube requires 2 hops to go to opposing corners, while every node
in the 8 nearest neighbor torus can be reached in just one hop.

	[Stuff Deleted]

|> The fact that the 4^2 torus is isomorphic to the binary 4-cube led to an
|> interesting question here at TMC about six months ago.
|> 
|> Is the 4^k torus isomorphic to the binary 2k-cube?
|> 
|> The answer and the proof (which I found quite fun) is left as an excercise
|> to the reader.
|> 
|> -steve

Is this a closely guarded corporate secret :-) ?

Bill

-- 
|
|	maniattb@cs.rpi.edu - in real life Bill Maniatty
|

Newsgroups: comp.parallel,comp.arch
From: gottlieb@allan.ultra.nyu.edu (Allan Gottlieb)
Subject: Re: BBN Monarch
Organization: New York University, Ultracomputer project
	<1992Dec15.134558.7762@hubcap.clemson.edu>
	<1992Dec16.134859.20701@hubcap.clemson.edu>
	<1992Dec18.133247.10850@hubcap.clemson.edu>
Date: 22 Dec 92 22:41:35

In article <1992Dec18.133247.10850@hubcap.clemson.edu> jkenton@world.std.com (Jeff Kenton) writes:

   gottlieb@allan.ultra.nyu.edu (Allan Gottlieb) writes:

   >   If you mean the TC2000, we are still using ours.

   >No the Monarch was different.  Bit serial network interface, MANY
   >processors.  It was viewed as having a research component unlike the
   >TC2000, which was planned as a product.  (The second sentence is
   >somewhat speculation on my part)

   The TC-2000 was a real product.  We thought we did a good job on it, but
   it turned out to be difficult to find a market niche for.

I think perhaps I wasn't clear.  I know for sure the TC2000 was a real
product.  We have used one to test some coordination algorithms on a
different (but similar) architecture from our own ultra.  What I
wasn't sure about was my assertion that monarch was viewed as having a
large research component and not planned to lead directly to a product.

   [ Howdy Allan -- keep those puzzles coming! ]

[Sure, providing readers like you keep the answers coming--A
tech-review-theoretic comment]