From: johnh@macadam.mq.edu.au (John Haddy)
Subject: Re: Beginners Question: RAS, CAS, and Refresh?
Organization: Macquarie University, School of Mathematics, Physics, Computing and Electronics
Date: Wed, 19 Aug 1992 03:26:55 GMT

In article <etxansk.714131335@garbod20>, etxansk@garbo.ericsson.se writes:
|>  I've been looking at chip descriptions for some common
|> memory circuits. 
|> 
|>  There are pins on them named RAS, CAS, and Refresh. I know
|> it's basic knowledge, but I'm not sure where to find good
|> documentation on this.
|> 
|>  The RAS and CAS signals are probably input signals to the
|> chip used during addressing. I've assumed that they're used
|> to tell the chip whether it's the most or least significant
|> part of the address vector that's currently on the address
|> bus. If I'm right about this, how come there are _two_
|> addressing control signals?
|> 
|>  For the Refresh signal: I can't recall if this one really
|> is a pin on the chip or if it's some event that's done with
|> other signals. I've heard that certain types of chips need
|> this signal in order to work properly. What is the CPU (or
|> the main clock, or the addressing logic) supposed to do to
|> give the memory chips the refresh?
|>  
|>  Anders Skelander
|>  

For starters, the acronyms RAS and CAS stand for Row Address Strobe and Column
Address Strobe, respectively. These signals, and the need to refresh, are
peculiar to Dynamic RAM chips.

You are correct in assuming that they are used for multiplexing the address bus.
Internally, the DRAM operation involves a (slow) row select operation and a (much
faster) column select in order to access a bit of data for reading or writing.
The relative operation times for row and column select mean that it makes sense
to give the DRAM chip a "head start" on the Row portion of the address. In
addition, the multiplexing of the address allows for a smaller pin count and
allows a higher density of chips when used in a system.

Refresh is not usually a signal; it refers to an operation performed to maintain
data integrity. The DRAM chip requires that each cell be rewritten at least once
every n microseconds (n is chip dependent, but often 4 or 8 milliseconds for
modern chips). Since most systems cannot guarantee that this will happen during
the course of normal program execution, an explicit refresh cycle is usually
performed. A refresh cycle may be performed either in a burst of distributed over
time The choice is usually determined by whether system performance will suffer
more from a short dead stop every (say) 4msec than from intermittent delays every
15usec. A refresh cycle consists of (usually sequentially) accessing each Word
line in turn. Because a sense amplifier (the bit that determines whether a bit is
a "one" or "zero") exists for each column, all the bits in one row may be
refreshed at a time.

Note that this feature, of all columns being activated at once by a word line, is
used to enable high speed DRAM access. For sequential address location accesses,
only one row address needs to be supplied, which causes the sense amplifiers on
the Data Lines to access the capacitors holding the charge which indicates a
logic "one" or "zero". Successive accesses then need only select _which_ one of
the sense amplifiers to activate. Thus a multiple read cycle can run something
like RAS, CAS, CAS, CAS, CAS (where RAS, CAS indicate the latching of a row or
column address)

If the system uses a DRAM controller chip, this can be programmed to
automatically refresh the DRAM. Otherwise, the CPU would have to be interrupted
by a timer once every 4 msec in order to service the DRAM refresh requirements.

From the Hitachi DRAM Data Book:

"The dynamic RAM memory cell consists of 1 MOS transistor and 1 capacitor, as
shown in Figure 1. It detects the data in the cell (1 or 0) by the charge stored
in the capacitor. Dynamic RAM offers a higher density than static RAM because it
uses fewer components per chip."

"However, dynamic RAM data must be rewritten (called refresh) in a defined cycle,
because the charge stored in the capacitor leaks."

Figure 1: Memory Cell of Dynamic RAM

                        |
                   -----|-------o------ Word Line
                        |       |
                        |      ===
                        b______| |____
                        |             |
                        |            ---
                        |            ---
                        |             |
                        |            ___
                        |            ///
                     Data Line

..."The multiplexed address inputs are latched as follows: RAS (row address
strobe) selects one word line according to the row address signal, and one column
decoder is selected by CAS (column address strobe) following a column address
signal."

Hope this helps. A good place to read up on memory technology is in the data
books and application notes of the manufacturers themselves.

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