HDTenEightyP/NetNews huggingface dataset:
From: eoahmad@ntuix.ntu.ac.sg (Othman Ahmad)
Subject: Re: XILINX development system on the PC.
Organization: Nanyang Technological University - Singapore
X-Newsreader: TIN [version 1.1 PL6]
Date: Sun, 8 Nov 1992 13:43:40 GMT

Manolis Stratakis (strataki@cerberus.csi.forth.gr) wrote:
:     Hello,
: 
: 	has anybody had any experience with the XILINX development system
: 	(FPGA hardware design system) for IBM PC compatibles? We are
: 	thinking of buying one, and would like to know more about it,
: 	like efficiency of the system, compatibility, support, etc.
: 
I have one, for not at the hardware side. I do not recommend the futurenet 
version because I've problems with connectivity and expansibility .
	I recommend that you choose others. Now the recommended one is the
Viewlogic which is a very good package apparently. I prefer Orcad because I'm
used to it but the Vst simulator interface was not ready at that time.
	Support here in Singapore is not so good. They are more interested in
Selling their tools than their chips. If we try to integrate into our 
existingh cad tools, they don't look keen, and even got it wrong e.g. thinking
that the Vst simulator interface is built into the orcad interface.
	Be careful with the XC4000 which needs 12Mbyte RAM minimum.
	THE autorouter looks efficient, for my small design which only took
5 % of the 9 thousand gate XC3000(XC3020?). You have manual routing option
as well. THERE IS a logic optimisation package.
	The old versions even have pld converter which is now extra.

The latest LIBRARIES COME WITH ttl compatible parts. 

I recommend Xilink very highly but be careful with the tools. 

--
Othman bin Ahmad, School of EEE,
Nanyang Technological University, Singapore 2263.
Internet Email: eoahmad@ntuix.ntu.ac.sg
Bitnet Email: eoahmad@ntuvax.bitnet
From: bbaker@beta.tricity.wsu.edu (Bill Baker)
Newsgroups: comp.lsi.cad
Subject: Call for papers: Hardware Accelerators for VLSI Design
Date: 6 Nov 92 20:36:18 GMT
Article-I.D.: serval.1992Nov6.203618.13361
Organization: Washington State University Tri-Cities, Richland WA
Originator: bbaker@beta.tricity.wsu.edu


                          
                            Call for Papers

                            Special Issue on

                 Hardware Accelerators for VLSI Design

VLSI DESIGN: An International Journal of Custom-Chip Design, Simulation and
Testing

A special issue of the VLSI Design Journal will be devoted to Hardware 
Accelerators for VLSI Design.  Topics of interest include, but are not 
limited to, the following:

	* Accelerators for logic simulation
	* Accelerators for analog simulation
	* Mixed analog/digital simulation acceleration
	* Parallel architectures for simulation acceleration
	* Placement, routing, and design-rule-check engines
	* Parallel, distributed simulation algorithms
	* Accelerators for VLSI testing and fault simulation

Instructions for Submitting Manuscripts

Manuscripts should be no more than 25 double-spaced pages (about 6000 words)
in lenth including all figures and references.  Papers must not have been
previously published or currently submitted for publication elsewhere.
Manuscripts should have a title page that includes the title of the paper,
full name(s) and affliation(s) of the author(s), complete physical and
electronic address(es), telephone number(s), and an abstract.

DEADLINES

	* Four copies of the full manuscript are due by March 1, 1993
	* Notification of acceptance is July 1, 1993.


Send Submissions and Questions to:

Dr. Ausif Mahmood, Guest Editor
School of Electrical Engineering and Computer Science
Washington State University at Tri-Cities
100 Sprout Road
Richland, WA 99352

Phone: (509) 375-9234
Email: mahmood@beta.tricity.wsu.edu


Dr. George W. Zobrist, Editor-in-Chief
Department of Computer Science
University of Missouri-Rolla
Rolla, MO 65401

Phone: (314) 341-4492
Email: c2816@umrvmb.umr.edu
Newsgroups: comp.lsi.cad
Subject: What is Synopsys ?
From: mohan@tulip.cse.utoledo.edu (Mohan Pakkurti)
Date: 11 Nov 92 08:21:20 EST

Can someone tell me what Synopsys stands for ?

Thanks :)
--mohan
-- 
===============================================================================
+ Mohanakrishna Pakkurti            + mohan@jupiter.cse.utoledo.edu           +
+ HOME: 2239 University Hills Blvd #204, Toledo OH 43606. Phone:(419)536-9073 +
===============================================================================
From: sss@ole.cdac.com (Stephen Sugiyama)
Newsgroups: comp.lsi.cad
Subject: Re: Cascade Design Automation ?
Keywords: VLSI CAD
Date: 11 Nov 92 21:02:27 GMT
Article-I.D.: ole.1992Nov11.210227.6973
Organization: Cascade Design Automation, Bellevue, WA

In article <1992Nov11.114035.11102@uoft02.utoledo.edu> mohan@tulip.cse.utoledo.edu (Mohan Pakkurti) writes:
> Can someone give me some info about  Cascade Design Automation.
> --mohan

Well, we read Usenet news.

On a more serious note, if you have some specific questions, send me
some mail and I'll try to get them answered.

--
Stephen Sugiyama 
sss@ole.cdac.com

Cascade Design Automation - 3650 131st Ave SE, Suite 650, Bellevue, WA  98006
-- 
Stephen Sugiyama
sss@ole.cdac.com
Newsgroups: comp.lsi.cad
From: aranake@cse.uta.edu (Sandeep Suresh Aranake)
Subject: Register allocation,with corrections
Organization: Computer Science Engineering at the University of Texas at Arlington
Distribution: usa
Date: Thu, 5 Nov 1992 20:37:15 GMT


I was sleepy when I posted my query on the net yesterday midnight.
I am reposting it with corrections.

Are there synthesis systems which support functional
pipelining during allocation of if-then-else behaviours ?
As I understand, there is a possibility of both branches
being active at the same-time if pipelining is used. Can
I ftp the software if it exists.

How is the optimality of the resources allocated in branches 
ensured ? I am particularly interested in register allocation. 

Thank you in anticipation.
regards,

Sandeep
From: ivanw@stein.u.washington.edu (Ivan Wemple)
Newsgroups: comp.lsi.cad
Subject: netlist comparisons
Date: 10 Nov 92 02:36:46 GMT
Article-I.D.: u.1992Nov10.023646.2310
Organization: University of Washington, Seattle



Hello all:

I am in the process of debugging a piece of software
which translates a flattened circuit simulator input
netlist into a 'hierarchical' netlist (ie, one which
contains subcircuit definitions and instances).

Question:

Is there a tool around which will compare two circuit
simulation input files and determine if they are the
same *topologically*?

My current technique involves running lengthy hspice
simulations and comparing the outputs... a long and
tedious process.

Thanks in advance!

Ivan Wemple
ivan@dtrl.ee.washington.edu
From: obiliset@duke.ecs.umass.edu (Sashi V Obilisetty)
Newsgroups: comp.lsi.cad
Subject: alpha chip
Date: 11 Nov 92 17:57:42 GMT
Reply-To: obiliset@sulu.ecs.umass.edu
Organization: University of Massachusetts at Amherst

I guess the best way to ensure that there is no skew is to have
one big buffer, and then have lines from this driver feeding all
other modules requiring clocks. What I am concerned about is the
amount of heat/power dissipation that would occur due to this big
driver.
Won't it create a hot spot on the chip? The power supply is 3.3V, 
is this the reason why it works?

Also, the chip is designed using 0.75um process with min. channel
lengths of 0.5um. How can we have long lines running in this technology?
Wouldn't the transmission line effects become prominent at this point,
and therefore it makes sense to use distributed driving??

Will be glad if someone would clear these doubts.
Thank You.

Sashi
Newsgroups: comp.lsi.cad
Subject: Cascade Design Automation ?
From: mohan@tulip.cse.utoledo.edu (Mohan Pakkurti)
Date: 11 Nov 92 11:40:34 EST

Can someone give me some info about  Cascade Design Automation.

Their Design Automation Products and user experiences. I will sumarize any
responces that you give me. Thanks.

:)
--mohan
-- 
===============================================================================
+ Mohanakrishna Pakkurti            + mohan@jupiter.cse.utoledo.edu           +
+ HOME: 2239 University Hills Blvd #204, Toledo OH 43606. Phone:(419)536-9073 +
===============================================================================
Newsgroups: comp.lsi
From: vrkaramc@mtu.edu (Karamchedu)
Subject: Current-mode Subthreshold Analog VLSI
Organization: Michigan Technological University
 
Date: Sat, 7 Nov 1992 23:09:13 GMT


Are there any forthcoming conferences/conventions allowing for presentations
or discussions of Current-mode Subthreshold Circuits (perhaps with some 
applications or demonstrations of neural circuits) ? 


Any feelers and hints on probable dates, locations would be greatly 
appreciated.

PLEASE E-MAIL ME DIRECT.

Thank you

Karamchedu Raj

Dept of EE

 
-- 

Instruments and moods are two facets of Being.


Newsgroups: comp.lsi
From: obiliset@honey.ecs.umass.edu (Sashi V Obilisetty)
Subject: question about alpha design
Reply-To: obiliset@sulu.ecs.umass.edu
Organization: University of Massachusetts at Amherst
Date: Wed, 11 Nov 1992 21:12:58 GMT

I guess the best way to ensure that there is no skew is to have
one big buffer, and then have lines from this driver feeding all
other modules requiring clocks. What I am concerned about is the
amount of heat/power dissipation that would occur due to this big
driver.
Won't it create a hot spot on the chip? The power supply is 3.3V, 
is this the reason why it works?

Also, the chip is designed using 0.75um process with min. channel
lengths of 0.5um. How can we have long lines running in this technology?
Wouldn't the transmission line effects become prominent at this point,
and therefore it makes sense to use distributed driving??

Will be glad if someone would clear these doubts.
Thank You.

Sashi

Xref: sparky comp.lsi:681 comp.lsi.cad:1116
From: sandeep@amd.com (Sandeep Srinivasan)
Newsgroups: comp.lsi,comp.lsi.cad
Subject: Re: Capacitance Estimation
Date: 5 Nov 92 06:08:14 GMT
Organization: /etc/organization

hi,
to estimate approx equivalent diffusion/gate capitance knowing
devices sizes ( i.e. W/L ) there is a nice paper
called " Logical effort:Designing for Speed on the
Back of an Envelope"
by 
  " Ivan E. Sutherland and Robert F. Sproull"

published in Advanced Research in VLSI 1991 UC Santa Cruz..

This gives a good picture of how to estimate
capacitance/delay of paths in  mos cktc...  with limited
knowledge of process paramaters... 


sandeep
From: killoran@ll.mit.edu (Mike Killoran)
Newsgroups: comp.lsi
Subject: Help needed compiling Magic & Irsim on HP700 series machine
Date: 12 Nov 92 21:12:56 GMT
Reply-To: killoran@ll.mit.edu (Mike Killoran)
Organization: MIT Lincoln Laboratory
Originator: killoran@ll.mit.edu (Mike Killoran)

Hi,

I'm trying to compile irsim (a simulator that comes with
magic) on an HP 730.  It compiles without errors, but bus
errors when reading in the parameters file.

It looks like the function which allocates space is not
aligning the data properly.  Has anyone gotten irsim to
work on an HP 700 series machine?  I could really use
some help here.

As an aside for those who don't know, magic is a VLSI 
layout editor for designing integrated circuits.  Irsim
is a switch level simulator that comes with it.


Mike Killoran
killoran@ll.mit.edu
Newsgroups: comp.lsi
From: swm11@cl.cam.ac.uk (Simon Moore)
Subject: hardware sorting
Keywords: hardware, sorting, earliest-deadline-first scheduling
Organization: U of Cambridge Computer Lab, UK
Date: Fri, 6 Nov 1992 16:54:07 GMT


I have a requirement for a hardware sorter to sort
deadlines for high speed real-time earliest deadline
first scheduling.  New deadlines can arrive at a peak
rate of one every cycle and the earliest deadline
needs to be extracted every 8 cycles.

I would be very interested in anyone who has come
across any hardware to perform such high speed
sorting.  (N.B. Batcher sorting networks are not
practical because they require several cycles to
sort a single set of values.)

 - Simon

[Simon Moore][University of Cambridge, Computer Laboratory][swm11@cl.cam.ac.uk]
Newsgroups: comp.lsi
From: yegna@cat.syr.edu (Yegnashankar Parasuram)
Subject: Re: Subset of VHDL for synthesis.
Organization: CASE Center, Syracuse University
Date: Wed, 11 Nov 92 21:08:45 EST

In article <3201@ucl-cs.uucp>, M.Nigri@cs.ucl.ac.uk (Meyer E. Nigri) writes:
|> 
|> Dear all,
|> 
|> I would like to know the present state regarding a formal definition
|> for a subset of VHDL aiming at synthesis.
|> 
|> I believe there is a group (VHDL Synthesis Working Group in Europe???) that
|> is trying to specify this subset.
|> 
|> Does anybody know how I can get info on this subject?
|> 
|> Thanks a lot,
|> 
|> Meyer.
|> 
|> PS: I will summarise to the group the responses I get on this

Hi,

You might want to take a look at the following :

VHDL for Simulation, Synthesis and Formal Proofs of Hardware, edited by Jean
Mermet (Kluwer Academic Publishers).  This is a collection of papers, some of
which might be of interest to you.

Towards the Correct Synthesis of VHDL Specifications, PhD dissertation of 
Xinning Wang, ECE department Syracuse University.

-Yegna.

#########################################################################

The contents of this article are the author's own views - they do not 
represent the view of any organisation such as the CASE centre or 
Syracuse University.

#########################################################################
# Yegnashankar Parasuram.						#
# Graduate Student at CE Department of Syracuse University.		#
# Office  : 2-128, Centre for Science & Technology.			#
# email   : yegna@cat.syr.edu.						#
#########################################################################

"THERE IS NOTHING THAT CANNOT BE DONE, UNLESS YOU THINK IT CAN'T BE DONE"
From: bbaker@beta.tricity.wsu.edu (Bill Baker)
Newsgroups: comp.lsi
Subject: Call for papers: Hardware Accelerators for VLSI Design
Date: 6 Nov 92 20:37:33 GMT
Article-I.D.: serval.1992Nov6.203733.13466
Organization: Washington State University Tri-Cities, Richland WA
Originator: bbaker@beta.tricity.wsu.edu


                          
                            Call for Papers

                            Special Issue on

                 Hardware Accelerators for VLSI Design

VLSI DESIGN: An International Journal of Custom-Chip Design, Simulation and
Testing

A special issue of the VLSI Design Journal will be devoted to Hardware 
Accelerators for VLSI Design.  Topics of interest include, but are not 
limited to, the following:

	* Accelerators for logic simulation
	* Accelerators for analog simulation
	* Mixed analog/digital simulation acceleration
	* Parallel architectures for simulation acceleration
	* Placement, routing, and design-rule-check engines
	* Parallel, distributed simulation algorithms
	* Accelerators for VLSI testing and fault simulation

Instructions for Submitting Manuscripts

Manuscripts should be no more than 25 double-spaced pages (about 6000 words)
in lenth including all figures and references.  Papers must not have been
previously published or currently submitted for publication elsewhere.
Manuscripts should have a title page that includes the title of the paper,
full name(s) and affliation(s) of the author(s), complete physical and
electronic address(es), telephone number(s), and an abstract.

DEADLINES

	* Four copies of the full manuscript are due by March 1, 1993
	* Notification of acceptance is July 1, 1993.


Send Submissions and Questions to:

Dr. Ausif Mahmood, Guest Editor
School of Electrical Engineering and Computer Science
Washington State University at Tri-Cities
100 Sprout Road
Richland, WA 99352

Phone: (509) 375-9234
Email: mahmood@beta.tricity.wsu.edu


Dr. George W. Zobrist, Editor-in-Chief
Department of Computer Science
University of Missouri-Rolla
Rolla, MO 65401

Phone: (314) 341-4492
Email: c2816@umrvmb.umr.edu
From: M.Nigri@cs.ucl.ac.uk (Meyer E. Nigri)
Newsgroups: comp.lsi
Subject: Subset of VHDL for synthesis.
Date: 9 Nov 92 12:27:19 GMT


Dear all,

I would like to know the present state regarding a formal definition
for a subset of VHDL aiming at synthesis.

I believe there is a group (VHDL Synthesis Working Group in Europe???) that
is trying to specify this subset.

Does anybody know how I can get info on this subject?

Thanks a lot,

Meyer.

PS: I will summarise to the group the responses I get on this
+--------------------------+-----------------------------------------------+
|Meyer Elias Nigri         |   JANET:mnigri@uk.ac.ucl.cs                   |
|Dept. of Computer Science |  BITNET:mnigri%uk.ac.ucl.cs@UKACRL            |
|University College London |Internet:mnigri%cs.ucl.ac.uk@nsfnet-relay.ac.uk|
|Gower Street              | ARPANet:mnigri@cs.ucl.ac.uk                   |
|London WC1E 6BT           |    UUCP:...!mcvax!ukc!ucl-cs!mnigri           |
+--------------------------+-------------------------+---------------------+
|Tel: +44 71 387-7050      | Fax: +44 71 387-1397    |    Telex: 28722     |
|                 ext. 3708|                         |                     |
+--------------------------+-------------------------+---------------------+
Newsgroups: comp.lsi,comp.lsi.cad
From: arnief@sail.LABS.TEK.COM (Arnie Frisch)
Newsgroups: comp.lsi.testing
Subject: Re: Boundary Scan JTAG 1149.1 Experience?
Date: 11 Nov 92 16:56:38 GMT
Article-I.D.: sail.12871
Organization: Tektronix, Inc., Beaverton,  OR.

In article <1992Nov10.215505.7919@philabs.philips.com> ncl@philabs.philips.com (Nai-Chi Lee) writes:
>	[ JTAG Version 0 ]
>	  The initial JTAG proposal was created by Frans Beenker (Philips
>	Research Labs, The Netherlands), Chantal Vivier (Bull Systems,
>	France) and Colin Maunder (British Telecom Research Labs, UK) in
>	June 1986





Yes, the initial document was completed in 1986, but work started on
this several years before.  I said they had been working on this for
about 8 years, and I think this checks out.

Arnold Frisch
Tektronix Laboratories
From: vinoski@ch.apollo.hp.com (Stephen Vinoski)
Newsgroups: comp.lsi.testing
Subject: Re: Boundary Scan JTAG 1149.1 Experience?
Summary: lighten up, Arnie
Date: 10 Nov 92 00:19:18 GMT
Organization: Hewlett-Packard Corporation, Chelmsford, MA

In article <12860@sail.LABS.TEK.COM> arnief@sail.LABS.TEK.COM (Arnie Frisch) writes:
>NOW...  I WANT TO TAKE EXTREME ISSUE WITH YOUR INFERENCE THAT THE
>APOLLO 10K ARCHITECTURE FOR SCAN IS SOMEHOW BETTER THAN BOUNDARY SCAN.
>
>The P1149.1 standard is the engine that is driving the future of
>built-in test.  Departures from this standard slow the process of
>progress.  The issue is not whether something is better (and I doubt
>that your example qualifies) but whether the standard is "good
>enough".  If it is good enough, it should be used, and if it is used
>people will find that it has much more capability than is visible on
>the surface.  For example, did you know that ATT uses boundary scan as
>the basis for communication of internal BIST results from chips to
>boundary scan controllers in production test applications?  Did you
>know that this use, and extensions of this methodology, are in
>development at many major sites in the US and elsewhere?
>
>Did you know that a substantial infrastructure - involving HW and SW is
>being created around P1149.1 and its extensions, an infrastructure that
>will not support other architectures and scan methodologies?  Do you
>think it is smart and cost effective and productive to depart from the
>standard under these conditions?

Do you realize that the DN10000 scan architecture was developed before
1149.1?  How can you accuse us of "departing from the standard" when
the standard wasn't even around when we did this work?

The DN10k scan architecture and 1149.1 are different beasts.  Each has
its good features and not-so-good features, and each does some things
better than the other.  Having written hundreds of thousands of lines
of scan software, I personally believe that the DN10k architecture is
easier for software to deal with when it comes to board-level testing.
But that is only my opinion, and it could be wrong.  But you will
allow me to have my own opinions, won't you, Arnie?  Or is there only
one standardized opinion, too?

1149.1 is the best standard we have today, but it is not the be-all
and end-all of scan test architectures.  It is worthwhile for anyone
involved in scan testing to study the DN10000 scan architecture and
others so that their good features can be incorporated into the next
scan test standard.  Do you think it is "smart and cost effective and
productive" to reinvent the wheel?

Chill out, Arnie.

-steve
From: arnief@sail.LABS.TEK.COM (Arnie Frisch)
Newsgroups: comp.lsi.testing
Subject: Re: Boundary Scan JTAG 1149.1 Experience?
Date: 10 Nov 92 16:40:21 GMT
Article-I.D.: sail.12867
Organization: Tektronix, Inc., Beaverton,  OR.

In article <BxH4w7.ts@scd.hp.com> vinoski@ch.apollo.hp.com (Stephen Vinoski) writes:
>In article <12860@sail.LABS.TEK.COM> arnief@sail.LABS.TEK.COM (Arnie Frisch) writes:
...........
>Do you realize that the DN10000 scan architecture was developed before
>1149.1?  How can you accuse us of "departing from the standard" when
>the standard wasn't even around when we did this work?

Do you realize that JTAG (the Joint Test Action Group) had been working
on this for about 8 years, and that they were well ahead of the DN10000
architecture when they started writing the basis for the P1149.1
standard?
........
>1149.1 is the best standard we have today, but it is not the be-all
>and end-all of scan test architectures.  It is worthwhile for anyone
>involved in scan testing to study the DN10000 scan architecture and
>others so that their good features can be incorporated into the next
>scan test standard.  Do you think it is "smart and cost effective and
>productive" to reinvent the wheel?

As I understand it, consultants were hired to do the major part of the
IC design for the 10K - including the scan design.  They subsequently
came out with a product for testing scan designs and tried to sell it -
unsuccessfully - under the banner "Gillytronics".  Seems like something
was lacking in their methodology.

Arnold Frisch
Tektronix Laboratories