From: ljo@r2d2.eeap.cwru.edu (L. Jonas Olsson)
Newsgroups: comp.unix.pc-clone.32bit
Subject: Re: Which motherboard?
Date: 15 Dec 1992 02:54:22 GMT
Organization: Case Western Reserve Univ. Cleveland, Ohio (USA)
NNTP-Posting-Host: johnny5.eeap.cwru.edu

In article <1992Dec13.204606.10000@texhrc.uucp> someone@Texaco.com (Larry D. Pyeatt) writes:

[old article citations and some of Larry's text deleted]

>But I still don't know _which_ boards, or cache controllers to
>stay away from.  Does anyone have any specific information?
>
>Thanks.

I have the data sheets for the Opti 82C482 and 82C493 in two text files,
but cannot distribute them as they have a copyright.

The 482 is an early chip that was can mix 256kB and 1MB simms, when using
4MB simms they can not be mixed with any other sizes. The 493 is a later
version that can mix 256kB, 1MB, and 4MB simms and use up to 512kB of cache
memory. I think the 493 has been replaced by 495 for ISA computers.

The Opti 82C482 can only cache the first 16MB of RAM, whereas the 493 can
cache up to 64MB of memory. The original 493 is supposed to have a bug,
hidden refresh does not work for 4MB simms. My PC uses the 82C495 and
has no problems with hidden refresh of 4MB simms, so either the problem
was fixed or there were no problem.

Here's an excerpt from the 82C493 data sheet:
---start excerpt---
SYSC (82C493) Register Description, OPTi chipset 486SXWB

Ref:  OPTi-486SXWB PC/AT Chipset Preliminary Data Book
      Version 1.1, August 16, 1991


          There are twelve configuration registers in the 82C493 -
          REG1-REG12.  The registers are accessed through I/O ports 22H
          and 24H.  Location 22H is the "Index Address".  This address
          corresponds to the specific register which points to the
          required data value accessed through port 24H.  Thus,
          reading or writing to a specific register is a two step
          operation:

          1) write to I/O port 22H with the register index.

          2) write or read the data to or from I/O port 24H.

          Every access to port 24H must be preceded by a write of the
          index value to port 22H even if the same data register is
          being accessed.  After power up, the configuration registers
          assume default values.  All bits marked as Reserved must be
          programmed zero.

          Reg#  Register Name                     Index

           1    Control Register 1                 20H
           2    Control Register 2                 21H
           3    Shadow RAM Control Register 1      22H
           4    Shadow RAM Control Register 2      23H
           5    DRAM Control Register 1            24H
           6    DRAM Control Register 2            25H
           7    Shadow RAM Control Register 3      26H
           8    Control Register 3                 27H
           9    Non-cacheable Block 1 Register 1   28H
           10   Non-cacheable Block 1 Register 2   29H
           11   Non-cacheable Block 2 Register 1   2AH
           12   Non-cacheable Block 2 Register 2   2BH

[skipped many register descriptions]

          Control Register 3
          Index : 27H

           BIT
          POSITION  FUNCTION                                   DEFAULT

           3-0      Cacheable address range for local          0001
                    memory, see following table

           4        Video BIOS at C0000h-C8000h area           1
                    non-cacheable
                    0 = Cacheable, 1 = Non-cacheable

           6-5      Unused                                     00

           7       Enable NCA# pin to low state, 0 = disable   1
                   1 = enable

                    3 2 1 0        Cacheable Address Range

                    0 0 0 1         4 MByte
                    0 0 1 0         8 MByte
                    0 0 1 1         12 MByte
                    0 1 0 0         16 MByte
                    0 1 0 1         20 MByte
                    0 1 1 0         24 MByte
                    0 1 1 1         28 MByte
                    1 0 0 0         32 MByte
                    1 0 0 1         36 MByte
                    1 0 1 0         40 MByte
                    1 0 1 1         44 MByte
                    1 1 0 0         48 MByte
                    1 1 0 1         52 MByte
                    1 1 1 0         56 MByte
                    1 1 1 1         60 MByte
                    0 0 0 0         64 MByte

---end excerpt---

	Jonas Olsson
	ljo@po.cwru.edu



Newsgroups: comp.unix.pc-clone.32bit