From: ted@telematics.com (Ted Goldblatt)
Subject: cache controller chip for 68040?
Summary: anyone know of one?
Organization: Telematics Intl., Inc.; Ft. Lauderdale, FL
Date: Mon, 13 Apr 1992 23:11:16 GMT

We are considering designing a 68040 based processor card as an
enhancement to our existing 68k based multiprocessor system.  This
system uses a global memory, accessed over a relatively slow (8 Mhz),
relatively narrow (32 bit) bus that does not support bursting, but IS
transaction oriented (request/response, with a maximum of 4 requests
outstanding per requestor (board); actually permitted outstanding
requests and actual latency varies amongst the various available
memory subsystems).

The existing processor cards (68020 based) use 64k direct mapped
write-through caches, with write invalidate.  The new board would
use a significantly larger cache (how big TBD), and preferably with
write-back.  Unfortunately, given the application area (high
performance datacomm) and our existing software, use of s/w selected
write-back vs write-through (based on shared or "global" vs unshared
memory regions) would be of limited benefit, since little operand
memory can be a priori declared unshared (much (most?) is I/O
buffers, "shared" with various comms (I/O) processors); that which
could be distinguished is still a problem, as our O/S is priority
driven, with process floating and no processor affinity if it
violates priority, so a non-coherent write-back cache would need to 
be flushed on a context switch, which largely eliminates the benefits 
of the large cache (generally short run times between context switches).

Therefore, what I would like is a cache that supports h/w cache
coherency protocols adequate for a write-back cache.  It appears that
due to limited volumes and limited development resources (2 faces of
the same coin; if the volumes were there, someone would be freed up
to do the work :-)), this is not feasable for us to build ourselves.
So, I am trying to find an off-the-shelf solution.

Our local Moto salesdroid indicates that Moto has no such part, and
is not aware of anyone else that has one.  What I am trying to find
is a part (or less desirable, a chip set) that is available to us
(either a commodity part, or someone's in-house part that they would
be willing to sell (relatively small volumes, 100's to 1000's per
year), which would ideally support:

   68040 interface (24Mhz at least, 32 Mhz preferable)
   32 bit memory interface (wider it tolerable, just requires more glue
      logic, but maybe no more than we will require to talk to our bus 
      anyway).
   Support a range of cache sizes (minimum ~128K?, maximum at least 1M?)
   2 way associative (but direct mapped is probably OK at these sizes)
   Uses commodity SRAMs for tags and data (anything else may be 
      prohibitively expensive, would have to be investigated)
   Supports a full write-back protocol (protocol used by 88110 is OK, that
      used by R4000MC(?) or Cypress SPARC chip (CY7C605) may be OK (I don't
      know those well enough to say).  It must not require too many signals
      to support the coherency protocol (only a couple (5-6?) will be 
      available.
   Probably other stuff that I can't think of off-hand :-)

Does anyone know of a chip or chip set like this?  Failing that, does anyone
know of any (non-68040) cache controller chips which can (with reasonable 
glue logic) be interfaced to an '040.  Failing THAT, does anyone have any 
other ideas?

(BTW, I am a s/w type (O/S), not a h/w type; hence the reason for any comments
above that don't really make sense :-)).

Thanx for any assist!
-- 
Ted Goldblatt    ted@telematics.com     (305) 351-4367
    Telematics Intl., Inc.   Ft. Lauderdale, FL