HDTenEightyP/NetNews huggingface dataset:
From: takefuji@donald.EEAP.CWRU.Edu (Yoshiyasu Takefuji)
Newsgroups: comp.internet.library
Subject: Re: Free Access to some dbases should be allowed
Date: 12 Dec 1992 04:26:10 GMT
Organization: EEAP, CWRU, Cleveland
NNTP-Posting-Host: donald.eeap.cwru.edu

Date: Fri, 11 Dec 92 09:54:34 PST
From: Guy R Thomas <gthomas@unixg.ubc.ca>
Subject: Re: Free Access to some dbases should be allowed


In comp.internet.library it is  writen:

By: tdowling@lib.washington.edu (Thomas Dowling)

>Subject: Re: RE:Free Access to some dbases should be allowed
>Organization: University of Washington Libraries

>>         In addition, there are many government agencies that freely make
>> their data available to vendors like Dialog or Compuserve...


>Can anyone confirm this?  I was under the impression that Uncle Sam picked 
>up a few bucks by *selling* these databases to vendors.

Just the last week the Canadian Government hosted a conference with the goal
of placing the responsibility for the transmition, and disemination of 
government databases firmly in the private sector.  The rational was that,
paraphrasing keynote speaker, librarians were little more than
scrap dealers when it came to information technology.  So, yes,  this is the
trend in Canada at least.

> > I think in
>> the information industry there is a giant conspiracy to keep timely data
>> out of the hands of John Q. Public by making John's data acquisition
>> costs as expensive as possible...


>I'd be amazed to learn that the "information industry" is organized enough 
>to conspire anything.  If you mean the database providers, you're talking 
>about a few private companies, and then some real power brokers like the 
>National Library of Medicine, the American Psychological Association, or 
>the Institution of Electrical Engineers.  Hardly conspirators. 

In Canada the government is active in organizing them.

>>  ...This smells of Nazism...

>>         You can't tell me that the information industry and the
>> government want current data to be readily available to anyone...

>I won't tell you anything of the sort until you specify whom you mean 
>by the "information industry".

The Canadian government has a very clear idea of what it is.

Guy R. Thomas
gthomas@native-ed.bc.ca
From: takefuji@donald.EEAP.CWRU.Edu (Yoshiyasu Takefuji)
Newsgroups: comp.internet.library
Subject: Re: A question on Internet Resources
Date: 18 Dec 1992 17:58:53 GMT
Organization: EEAP, CWRU, Cleveland
NNTP-Posting-Host: donald.eeap.cwru.edu

Newsgroups: comp.internet.library
From: aldridge@netcom.com (Jacquelyn Aldridge)
Subject: Re: A question on Internet Resources
Date: Thu, 17 Dec 1992 21:27:51 GMT

        Being lucky enough to be in the bay area...I'm paying $20 a month
for almost unlimited time on Netcom. E-mail, newsgroups, telnet, ftp.
        The largest cities seem to be connecting up first. We also have
another system called Portal which offers the same. 
        Companies hire time and connections starting at 165 a month. Netcom
also sells compile time for some companies for programming. 
--Jackie--
From: takefuji@donald.EEAP.CWRU.Edu (Yoshiyasu Takefuji)
Newsgroups: comp.internet.library
Subject: Re: A question on Internet Resources
Date: 17 Dec 92 18:49:58 GMT
Organization: EEAP, CWRU, Cleveland
NNTP-Posting-Host: donald.eeap.cwru.edu


Date: 17 Dec 1992 09:25:18 -0700
From: Ray Harwood <RHARWOOD@east.pima.edu>
Subject: Re: A question on Internet Resources

> (3) The restrictions on commercial use of the internet discourage people
> from providing commercial resources.  [stuff deleted]

Please note that the non-commercial use restriction in the Acceptable Use
Policy is *not* an "Internet" policy, but rather an NSF-network provider
policy.  The Internet is comprised of several backbone networks, and each
network provider is responsible for determining their own definition of
Acceptable Use.  Since NSF-net connects colleges and (ostensibly) research
institutions to the Internet and is funded with *tax* dollars, no-one is
"permitted" to derive direct financial gain from such a connection.

However, get your Internet service through a member of CIX, the Commercial
Internet Exchange, and you PAY for your access with *your* dollars, but you get
a much broader definition of acceptable use.  Yes, a company can even SELL
things over Internet (I'm planning on establishing a commercial connection in
January to distribute contract notices from sources like the CBD, for example),
but since the resources are not FREE to commercial users, they will typically
charge for their services.
======================================================================
There is a pretty sizable list of backbones/gateways into Internet that are
availabel as pay services for which no *restrictive* AUP exists.  I've found
personal accounts in the $39/month range, and full-blown TCP/IP-host connection
for $250/month unlimited 24-hour connection.

Ray
-----
Ray Harwood           |Data Basix           |Adjunct Faculty, East Campus,
Voice: (602)721-1988  |PO Box 18324         |   Pima Community College
FAX:   (602)721-7240  |Tucson, AZ 85731     |Instructor in Ada and Pascal
CompuServe: 76645,1370|AppleLink: DATA.BASIX|Internet: rharwood@east.pima.edu
From: takefuji@donald.EEAP.CWRU.Edu (Yoshiyasu Takefuji)
Newsgroups: comp.internet.library
Subject: swiss-france library
Date: 12 Dec 1992 04:03:58 GMT
Organization: EEAP, CWRU, Cleveland
NNTP-Posting-Host: donald.eeap.cwru.edu

From: g_jorba@cc.uab.es
Subject: Re: French Library
Date: 11 Dec 92 17:37:22 +0200

You can try to telnet to sibil.switch.ch, in Lausanne, Switzerland,
a catalog that provides access to the Swiss-French network,
including catalogs in Friburg, Geneve, Lausanne, Neuchatel, Ticino
and Wallis.


Ferran Jorba
VTLS system manager
Centre de Processament de Dades
Universitat Autonoma de Barcelona
Internet:   g_jorba@cc.uab.es
Bitnet:     g_jorba@ebccuab1
Newsgroups: comp.arch
From: lando@zycar.lmsc.com (Jim Landowski x45016)
Subject: Re: COMPAQ PROPOSED SCALABLE I/O ARCHITECTURE
Reply-To: lando@aic.lockhhed.com
Date: Wed, 16 Dec 92 18:12:36 GMT

This bus concept is in the spirt of ATM (Asynchronous Transfer Mode) 
technology which I am very much in support of. ATM can be emensely
flexible not only in periphrial support but also in direct network and
multiprocessing support as well. SUN Micro's new highend
server is based on an ATM type bus in support of parallel processing.
I enthusiastically support this proposal as an end user and as an
embedded systems builder. I need it and I need it cheap. Cheap comes
with volume so the PC market is a great place to start.

One suggestion or recommendation would be to not exclude from the design
the hooks necessary for multiprocessing or direct interconnect between
remote systems (i.e. distributed processing or periphrial sharing). Multi-
CPU connect might be simply accomplished with dual or multiport IOC's as
follows,

                 CPU1    CPU2
                  |       |
         memory---|       |---memory
                 MIOC   MIOC
                    \   /  \
                     IOC  dev3
                     / \
                 dev1  dev2

 The network could physically be the interconnect between an IOC and dev1 or
 MIOC and IOC. The only discriminant is the speed.

  My 2 cents. ;-)

-------------------------------------------------------------------------------
James G. Landowski			-------   /\   |   /
Lockheed Research & Dev.		  -----  /__\  |  |
Palo Alto, CA.  			    --- /    \ |   \
lando@aic.lockheed.com
From: keith@ksmith.uucp (Keith Smith)
Newsgroups: comp.arch
Subject: Re: Compaq's Proposed Scalable I/O Architecture
Date: 20 Dec 92 21:53:32 GMT
Distribution: usa
Organization: Keith's Computer, Hope Mills, NC

In article <1992Dec18.031032.7378@netcom.com> nagle@netcom.com (John Nagle) writes:
>     A few questions:
>
>     - Presumably there is a card form-factor and connector defined for
>       this standard.  Could you say more about that?

Please do. The lego-maniac desires to know :)

>
>     - Similarly, there is presumably an inter-box cable and connector
>       defined, or will be.  Comments?  Incidentally, are the signals
>       differential-drive, or do we have to worry about common-mode noise
>       and grounding?  And do peripheral devices get to draw power from
>       the big box over this interface?

I think a totally seperate power bus would be in order.  Also I would
like to see a big time specification for the connectors, High
reliability, gold plated, multiple wiping.  25 pins with interleaved
grounds for the data bus,  maybe a 10-15 pin seperate power bus.

>     - Given that Microsoft's NT supports multiprocessors (16 CPUs have
>       been demonstrated) and Compaq's position as a high-end vendor for
>       Microsoft-compatible iron, I'm suprised that Compaq is proposing an
>       I/O architecture that is single-CPU oriented.  Why?

Why do you say this is Single CPU?

>
>     - Another likely multiprocessor application appears in laptop-type
>       "docking stations", where the laptop plugs into a desktop machine.
>       Is this bus suitable for that application?
>
>					John Nagle

And the lego-maniac says, yes please,, let me plug a cord from my laptop
into the end of the last cube on my system & keep on trucking.
-- 
Keith Smith          uunet!ksmith!keith            5719 Archer Rd.
Digital Designs      BBS 1-919-423-4216            Hope Mills, NC 28348-2201
Somewhere in the Styx of North Carolina ...
Newsgroups: comp.arch
From: richard@meiko.com (Richard Cownie)
Subject: Re: RISC assemblers question
Organization: Meiko Scientific Corp.
Date: Thu, 17 Dec 1992 17:39:30 GMT

masticol@cadenza.rutgers.edu (Steve Masticola) writes:
: Hi,
: 
: I've met a couple of people who have attempted to write assemblers for
: RISC machines, who say that it's a difficult job. Can someone give me
: an inkling as to why?
: 
: I'm not saying that it isn't; the reason just isn't obvious to me
: right now.
: 
: Thanks,
: - Steve (masticol@cs.rutgers.edu).

Writing a basic assembler for most RISC machines must surely be easy,
because the instruction formats are few and simple.  However, I can
think of several things which can make it harder:

  1) For a processor like the original MIPS, the assembler is responsible
     for identifying pipeline hazards and re-ordering the code and
     inserting no-ops to avoid them.

  2) For machines with delayed branches and suchlike, the assembler
     often tries to optimise by filling the delay slot.  I've just
     been looking at the Sun SPARC assembler, and it has a huge pile
     of peephole optimization code.

  3) In the quest for simplicity of the instruction set, some things
     usually get swept under the carpet and become difficult, e.g.
     loading immediate constants into registers.  Most RISC's implement
     the common cases of small +ve and -ve integer constants simply
     and efficiently, but loading a random 32-bit constant may be hard.
     On the SPARC, this takes 2 instructions, on the ARM, which is what
     I'm thinking of in particular, it could take up to 4 instructions,
     as immediate constants were only 8 bits shifted by any even number!
     Sounds bizarre, but actually it catches most of the common cases.
     Anyway, it's nice for the assembler writer to hide these kinds of
     architectural warts with pseudo-instructions.

     And then if the things you're loading is a relocatable address ...

So I guess the answer is, as for most software, you can get 80% of
the functionality with 20% of the work, but getting the last 20% is
hard.



-- 
Richard Cownie (a.k.a. Tich), Meiko Scientific Corp 
email: richard@meiko.com
phone: 617-890-7676
fax:   617-890-5042       
Newsgroups: comp.arch,comp.arch.storage
From: simonich@croatia.eng.hou.compaq.com (Chris Simonich)
Subject: Re: ?Concurrent DMA possible on smarter PC buses (EISA/MCA/Localbus)
Keywords: EISA,MCA,Localbus,VESA,PC,IBM,smartIO
Organization: Compaq Computer Corp.
Date: Thu, 17 Dec 1992 19:11:31 GMT

In article <1992Dec17.153141.3926@urbana.mcd.mot.com> dfields@urbana.mcd.mot.com writes:
>In article <1992Dec16.211712.13142@twisto.eng.hou.compaq.com>, simonich@croatia.eng.hou.compaq.com (Chris Simonich) writes:
>> In article <1gntdfINNu7@cbl.umd.edu> mike@cbl.umd.edu (Michael Santangelo) writes:
>>>Can EISA, MicroChannel, or the new VESA LocalBus on PC's allow
>>multiple controllers plugged into them (say two smart bus mastering
>>>SCSI disk controllers on one of these buses) xfer data simultaneously
>>>to main memory (DMA)?
>>>
>>Generally, shared bus architectures are shared by time-division multiplexing.
>>In short, only one device may use the "bus" at a time, so the answer to your
>>question is No.
>
>I read waht he said and wasn't so sure from the example he gave that the
>question he asked is the one he wanted to ask.  To controllers can be doing
>DMA trnasfers at the same time byspliting the transfers into smaller chunks
>and doing the "time-division multiplexing" of the bus via an arbitraition
>scheme.
>
>>There was a post about a new I/O architecture from Compaq.  This architecture
>>does allow multiple controllers to perform simultaneously.
>
>If the MIOC in Compaq's proposal is implemented with a multi-port interface
>to main memory then it will.  You would loose some on cost of course.
>--
>Dave Fields	Motorola Computer Group		dfields@urbana.mcd.mot.com
>SVR4: The Winchester Mystery Kernel		uiucuxc!udc!dfields

A multi-port interface to memory is not required.  If two devices on an IOC
are performing DMA simultaneously, all that is required is that the IOC
send the data upstream at a rate equal to that of the total of the devices.
There is nothing preventing the upstream channel on the IOC from running
at 100 MHz.  Of course, another way to solve the problem would be to use
additional buffering in the IOC, for example.  The point is that from the
devices point of view it doesn't have to share its channel with anybody at
any time.
--
======================================================
Christopher Simonich        simonich@twisto.compaq.com
Compaq Computer Corp.       [713] 374-1898
======================================================
From: snail@lsl.co.uk
Newsgroups: comp.arch
Subject: Date request
Date: 16 Dec 92 16:11:33 GMT
Organization: Laser-Scan Ltd., Cambridge

In article <1992Dec14.134109.3367@fasttech.com>, zeke@fasttech.com (Bohdan Tashchuk) writes:
> A 10/21/92 semi-official net posting on NextStep claims it runs on SXs:

Hi folks, this is not a flame, just a request.

The date above refers to 21 November 1992. That may seem obvious to some of
you. Lets switch the 21 to an 8. In America the date is now 8 November 1992. In
the UK the date in now 10 August 1992. Some places have dates as Year/Month/Day
too. It would be more clear if everyone wrote the month name as a name (until
2001 anyway). ie: 21/NOV/92.

The above aside, I'm always puzzled as to how the American date convention
started: Mont/Day/Year is neither LSB or MSB, where as Day/Month/Year and
Year/Month/Day have obvious reasoning behind them.
-- 
snail@lsl.co.uk      

muso/unix joke: "which debugger do you use?"
                "I use dbx..."
                "Oh really, we use Dolby C..."
Motorola inside.
Newsgroups: comp.arch,comp.arch.storage
From: simonich@croatia.eng.hou.compaq.com (Chris Simonich)
Subject: Re: ?Concurrent DMA possible on smarter PC buses (EISA/MCA/Localbus)
Keywords: EISA,MCA,Localbus,VESA,PC,IBM,smartIO
Organization: Compaq Computer Corp.
Date: Wed, 16 Dec 1992 21:17:12 GMT

In article <1gntdfINNu7@cbl.umd.edu> mike@cbl.umd.edu (Michael Santangelo) writes:
>Can EISA, MicroChannel, or the new VESA LocalBus on PC's allow
>multiple controllers plugged into them (say two smart bus mastering
>SCSI disk controllers on one of these buses) xfer data simultaneously
>to main memory (DMA)?
>
Generally, shared bus architectures are shared by time-division multiplexing.
In short, only one device may use the "bus" at a time, so the answer to your
question is No.

There was a post about a new I/O architecture from Compaq.  This architecture
does allow multiple controllers to perform simultaneously.

--
======================================================
Christopher Simonich        simonich@twisto.compaq.com
Compaq Computer Corp.       [713] 374-1898
======================================================
Newsgroups: comp.arch
From: zs@munta.cs.mu.OZ.AU (Zoltan Somogyi)
Subject: Re: Logic Minimization Algorithms
Organization: Computer Science, University of Melbourne, Australia
Date: Thu, 17 Dec 1992 02:35:25 GMT

roberts@angelo.amd.com (Dave Roberts) writes:
>Does someone have references of articles that describe this stuff?

%A Robert K. Brayton
%A Gary D. Hachtel
%A Curtis T. McMullen
%A Alberto L. Sangiovanni-Vincentelli
%T Logic minimization algorithms for VLSI synthesis
%D 1984
%I Kluwer Academic Publishers
%C Boston
%P 193

Zoltan Somogyi <zs@cs.mu.OZ.AU>
Department of Computer Science, University of Melbourne, AUSTRALIA
From: mcdowell@exlogcorp.exlog.com (Steve McDowell)
Newsgroups: comp.arch
Subject: SuperSparc User Guide order number?
Date: 12 Dec 92 17:54:30 GMT
Organization: EXLOG, Inc.


Does anyone know the TI order number for the user guide to 
the TMS390Z50 SuperSparc? I called the TI response center
and they sent me a form telling me that if I bought the 
developer's kit for $50K that I could get the set of 
documentation. 

I'm only interested in the User's Guide. 
-- 
Steve McDowell             . . . . o o o o o 		Opinions are 
Exlog, Inc.	                  _____      o     	mine, not my 
mcdowell@exlog.com      _____====  ]OO|_n_n__][.    	employers..
		       [_________]_|__|________)<
From: dneedham@oucsace.cs.ohiou.edu (Douglas Wade Needham)
Newsgroups: comp.arch
Subject: USA vs. World (was Yanks vs. Brits)
Date: 19 Dec 92 17:45:28 GMT
Organization: Ohio University CS Dept,. Athens

I started to mail it, but felt strong enough to go through the hassle of
turning my reply into a followup...

It might be "Here we go again", but it is a valid point.  While I am,
as you say, a "Yank" like the gentleman at microsoft, I too have found
it very frustrating...to put it very simply...IT MAKES NO () SENSE!!!
Just like the measurements system that the USA uses.  And just as the
rest of the world uses MKS or some derivative of it, the majority of
the world to my knowledge uses YY/MM/DD, DD/MM/YY or something of that
nature, and NOT the XX/DD/XX form that we use predomanately here.

Maybe the US should take the hint, jump on the band-wagon and ride along
with the rest of the world.  Otherwise, the USA will end up like the brother
who decided to walk to the town in the next county rather than hitch up the
wagon and ride there.  If the first brother does not get on the wagon, who
gets to town first (reguardless of whether or not the first brother can
beat-up the second)???

The UK went to metric, abandoning the measurement system US civilians use.
This also should say something.

NUFF SAID!!! Besides, this is not the best news group for it.

Douglas Wade Needham
UNIX Software/Hardware Specialist
Written 92.12.19 !!!




-- 
Email:	dneedham@oucsace.cs.ohiou.edu  
USnail:	2330 South Clinton Street,  Fort Wayne,IN 46803
Phone:  (219)455-4004 (office) (219)456-1420 (home)
Newsgroups: comp.arch
From: bryanw@iastate.edu (Bryan J Welch)
Subject: grad. project - Thank you
Organization: Iowa State University, Ames, IA
Date: Sun, 13 Dec 1992 21:32:08 GMT


A while ago I posted a request for info on processors and design in a 
graduate multiprocessor design project.  We got lots of replies, and it 
helped a lot.  

I just wanted to thank everyone for their help.  When the project is 
finished I'll try to post something describing the entire architecture
in case anyone is curious, and to see what everyone thinks.

Thanks again,

-Bryan Welch

-- 
Bryan Welch	N0SFG
Center for Nondestructive Evaluation
Internet: bryanw@iastate.edu, bwelch@cnde.iastate.edu 

Newsgroups: comp.arch
From: rminnich@super.org (Ronald G Minnich)
Subject: Re: IBM's FIRST RISC System/6000(tm) based Shared Memory Parallel Processor
Keywords: mp shared-memory parallel multiprocessor risc smp
Organization: Supercomputing Research Center (Bowie, MD)
Date: Sun, 13 Dec 1992 13:48:12 GMT

In article <1g86boINNh5m@fido.asd.sgi.com> mtj@babar.asd.sgi.com (Michael Jones) writes:
> (claim 1) It's been a _long time_ since a multicomputer or other
> non-coherent computing complex was seen as an interesting platform 
> for the problems Mr. Mitchell mentions which include CFD and FEA 
> solvers.

IBM gave a talk on the machine at the cluster workshop. 
It is called the Power/4 now, the Power/128 is in the works. 
Power/4 is 4 cpus, and Power/128 is of course 128. 
Kernel is AIX, but Mach 3.0 runs on it as well. Getting Mach up on the 
machine looked like an adventure, as the MP code assumes coherent caches.
The person who did Mach stated that he felt that much of the work
done would apply to a coherent cache machine as well.
I.e. the things you do to code for a non-coherent cache machine would 
improve performance on a coherent cache machine. My experience agrees
with this.

The speakers stated flatly that coherent cache machines can not scale. 
Here is where you have to watch the use of the word 'scale'. There is 
scalability in that you can add more nodes, a la SCI or KSR; and there is 
performance scalability in that adding more nodes doesn't get you into
N^2 communications  costs (which can easily happen with coherent
cache machines not on a bus; take a look at the time it takes on 
a cache-coherent shared-memory machine using a ring with lots of nodes 
to write a variable which is in every CPUs cache. Examples: MemNet or 
one of its more recent incarnations:see ICPP 91, Computer a month or two ago). 
The Power/128 people are concerned with
performance scalability. [As an aside, the Cray APP, also described at the
workshop, uses a noncoherent cache scheme as well]. 

Currently there are four RS6000s (980s ?), with 128 Mb each, with a crossbar,
and eight shared memory modules. First cut of the crossbar was done
with Xilinx; later cuts are custom. 

In user mode, the shared area obeys the following rules:
1) Granularity of object size for sharing: page size
2) Only ever one writer for a page, multiple readers
3) to sync. a page back, write it to memory and invalidate cached copy

I like the model. I am biased; I started using this model four 
years ago, albeit on an Ethernet. I think they will find a need for some useful
variations on rule (3), however.

ron

-- 
you want windows? I got windows. 4608 by 3600,    | rminnich@super.org
16 channels of sound, 4' by 6'. Fun.              | (301)-805-7451 or 7312
Most abused words: open, scaleable, [more later]  |
Newsgroups: comp.arch
From: schwenk@oin.cis.udel.edu (Peter A. Schwenk)
Subject: Any new transputers from INMOS since T800?
Organization: University of Delaware, Newark
Date: Fri, 11 Dec 1992 20:17:18 GMT

I was doing a little reading on the transputer architecture, and I couldn't
find out if INMOS has put out any successors to the T800.  Anybody know
anything about that?

Thanks in advance,

	Peter Schwenk (schwenk@cis.udel.edu)
Newsgroups: comp.arch,comp.sys.dec,comp.sys.sgi,comp.sys.hp