From: mulligan@wotangate.sc.ti.com (Danny Mulligan)
Newsgroups: comp.lang.vhdl
Subject: Re: info on VHDL simulators requested
Keywords: VHDL 1076
Date: 8 Oct 92 16:02:22 GMT
Article-I.D.: csc.1992Oct8.160222.2942
Reply-To: mulligan@wotangate.sc.ti.com
Organization: Texas Instruments Houston

In article 205@news.service.uci.edu, cho@balboa.eng.uci.edu (Jae Cho) writes:
>I would like to hear about the experiences of
>users of Model Technology VHDL simulator and
>those who use Mentor Graphics VHDL simulator.
>
>I heard that Mentor's is not full 1076 complient.
>Is this true?  On the other hand, I heard that
>the device models from LMI is not supporting
>Model Technology yet.

We recently did some CAD tool evaluations so I have some info on this.
(We evaluated Mentor System 1076, Synopsys VSS & Mentor VHDLsim.)

Mentor Graphics have two VHDL simulators.  One is called System_1076 and
comes from their Idea Station software which is mainly used by ASIC
designers.  The other is VHDLsim which comes from their GDT tool set
and is mainly used by full-custom IC designers.  System_1076 is build upon
their QuickSimII simulator, VHDLsim is built on their Lsim simulator.

VHDLsim is 100% compatible with the IEEE VHDL std.  System_1076 is not.
Mentor have a plan to fix the missing VHDL constructs in the next two releases
of System_1076.  The current version is Ver 8.1, the next version is 8.2 due
at the end Nov/start Dec.  The version after that which is supposed to finish
the enhancements and make System_1076 100% compliant is due some time in the
middle of 1993.  The following explains what is missing & when it will be
fixed.  (This info is copied from a slide that Mentor gave me last month.)

    8.2 ENHANCEMENTS
    - Records
    - Generics affecting structure
    - Access types
    - User defined attributes
    - Abstract data types on schematics
    - Incremental part loading and incremental change capability
    - Aggregates and record aggregates
    - Attribute declarations
    - Library. All (includes default configs)

    REQUESTED FUNCTIONS BEYOND 8.2
    - Aliases
    - Physical types
    - Generate
    - Configuration declarations

The lack of 100% compliance was not a problem for us as we will be using the
synthesizable subset of the VHDL language anyway.  Probably the only things
we would have missed are generate statments and configurations - and we could
work around these anyway.  System_1076 has a poor user interface when you are
using the IEEE std_logic_1164 package - we weren't able to display a
std_logic_vector as a hex bus - binary only (which is a bummer when you have
43 bit busses like we do).  There are no such problems when you use the
Mentor supplied Qsim_types package.  Mentor promise to fix these user
interface problems in the next (8.2) release.

VHDLsim is a very new product (Version 1.0 was released in Aug) and has some
problems with quality and reliability.

I have been told by someone who's opinion I respect that Vantage have the best
VHDL simulator but I have absolutely no personal experience to back that up.
Maybe someone else out there can share some info about their experiences with
Vantage?

Needless to say - all the above are my personal opinions and not TI's.

Danny       mulligan@wotangate.sc.ti.com