From: michael@Canada.lsil.com (Michael Smith)
Subject: Re: headland chip set memory decoding.
Reply-To: michael@Canada.lsil.com
Organization: LSI Logic Corporation of Canada, Inc.
Date: Fri, 18 Dec 1992 14:08:55 GMT

> I would like to be able to use DEBUG i/o instruction to access
>the Headland chip set hardware and reenable the slot for error diagnosis.
>   My initial musings around a dissembly of the BIOS indicate that CMOS
>location x'8F' is used for this function( o70,8f then i71 or o71,xx) but how
>this location maps to memory control is a mystery. Any help would be appreciate
>d.
>Regards

Which chipset are you working with?  Shasta, or Summit, or ....?

On the Shasta chipset (i.e. HTK342) (not completely sure about Summit) there is a
double-indexing scheme to access the internal registers.

Taking from the chipset manual:

	To program the INDEX registers, one must execute the following procedure:

	i) Write I/O Location 28H with Value = INDEX (00-1FH for HT321 chip)
	ii) Write to I/O Location 24H with Control Value for the selected INDEX

	To Read INDEX registers, execute the following procedure:

	i) I/O Write Location 28H with Value = INDEX (00-1FH for HT321 chip)
	ii) I/O Read Location 24H - Control Value of selected INDEX is presented


INDEX 0024H is mapped as:	(DRAM Options Port #1)

Bits	Value	Meaning
 1:0	0 0	1 bank of DRAM
 	0 1	2 banks
	1 0	3 banks
	1 1	4 banks

INDEX 0025H	(DRAM Options Port #2)

Bits	Value	Meaning
 1:0		Type of DRAMS in bank 0
 3:2		Type of DRAMS in bank 1
 5:4		Type of DRAMS in bank 2
 7:6		Type of DRAMS in bank 3

	0 0	256k
	0 1	1MB
	1 0	4MB
	1 1	16MB


INDEX 0028H	(Data Transfer Port)

Bits	Value	Meaning
3:0	1100	TOP_OF_REMAP_MEMORY register (MSB)
	1101	TOP_OF_REMAP_MEMORY register (LSB)
	1110	TOP_OF_MEMORY register (MSB)
	1111	TOP_OF_MEMORY register (LSB)

4:5		Reserved

6	0	Read Transfer
	1	Write Transfer

7	0	No action
	1	Initiate Transfer


INDEX 0029H	(RAM Address Register)

Bits	Value	Meaning
 4:0		RAM address register contents
 7:5		Reserved

INDEX 002AH	(Data Transfer Port)

Bits	Value	Meanining
7:0		Data register contents



To write to a RAM location:

1. Set RAM Address Register:
	- IOW to address 28H with value 29H
	- IOW to address 24H with RAM address value

2. Set Data Transfer Port:
	- IOW to address 28H with value 2AH
	- IOW to address 24H with data of value to be transferred

3. Initiate the write transfer
	- IOW to address 28H with value 28H
	- IOW to address 24H with value
		a) bits 3:0 specify the destination of the transfer
		b) bit 6 set
		c) bit 7 set


To properly change the amount of DRAM that you have, the banks must be specified
properly and the top of memory must also be set.

If you want more information, I can send you a FAX of the appropriate part of the
data sheets.

In case you're wondering, Headland is actually a division of LSI-Logic.  The chipsets
are designed up here in Toronto, Canada, with the exception of the portable chipsets
which are done in California.

I don't know if the above information will help, it depends on the chipset that you
are using....

---
     Michael Smith - Chipset Design Engineer

Phone: (416) 620-7400         michael@canada.lsil.com
Fax:   (416) 694-5005

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