Newsgroups: comp.sys.mac.hardware
Subject: About IIsi upgrade heat...
From: seth@physc1.byu.edu
Date: 15 Nov 92 19:09:01 -0700
Distribution: world
Organization: Brigham Young University

Hi. I have been doing some thinking about some of the responses posted here 
about the IIsi myself, and I would like to address the heat problem. In a 
response posted just a few back from this response (I forget the guy's name)
He asked the question of whether (or why) extra heat is generated. I don't
understand why it is IF it is. First, let me clarify one thing: I am a physics
student and not an EE guru, so I don't claim to know all kinds of chip stuff,
but I do know a bit of physics that is involved.
	Ok, so with the introductions out of the way, here's my opinion...
	When you increase the clock speed to 25 MHz, which is a 25% increase
in clock speed, you are NOT increasing the current through the chip by 25%,
as has been stated by several people in regards to the IIsi "upgrade". If it
did, the power would not go up 25%, as has also been stated by several people.
Since the formula for power is P=I^2*R, a current that was 1.25% of the
original current would produce an increase of (1.25)^2=1.563%. I seriously 
doubt that this is happening. Now, why have I said that the current does not
increase by 25%? Having a clock speed of 20 MHz means that in one second there
are 20 million cycles of "on-off" or whatever the chip sees as one pulse. This
means that each cycle lasts 1/2000000 of a second, and with a certain fraction
of a second where current flows and a certain fraction where it doesn't (or
whatever a complete clock cycle is composed of). With an increase in clock 
speed from 20 MHz to 25 MHz, you do not see an increase in current of 25%
because we are NOT looking at an increase of 5 million clock cycles PLUS the
original 20 million clock cycles EACH OF 1/2000000 of a second duration. We
are really looking at an increase of 5 million clock cycles AND A REDUCTION
in the period of each clock cycle. What this means is that we are NOT making
one second any longer by increasing our clock speed; we are making our clock 
cycles shorter so that we can fit 5 million more of them into every second.
This means that each clock cycle will produce heat for a SHORTER amount of
time, and that therefore even though there are 5 million more clock cycles
you end up with no more heat than before. I am sorry that I am bad at
explaining this. I hope that some EE freakmo who can explain it better than
me will write in and do so. Now, there is more. I have no idea what the
increase in clock speed will do to the impedance of the chip. A circuit 
consisting of capacitors and inductors and such has inductance, which like
resistance affects how much current flows through a circuit for a given voltage
drop. I don't know much about this stuff, as my last electronics (read: my
ONLY electronics class) was quite a while ago, but I do know that how well an
ac signal passes through a capacitor varies with frequency. I don't know if
the signal inside a coputer chip is AC or not, but it is possible that some
inductance value of the chip would change with the increase in clock speed, 
and thus change the power dissipated by the chip. I don't know about the
validity of the last couple of statements, so I would appreciate it if some
semicunductor guru would comment on this. I don't care if I get flamed for 
being dead wrong; I would like to know. But, these ideas sound reasonable to
me, so I posted this note to see what kind of response it generates. Now, as
for why a heat sink has allowed some peoples' IIsi's to work under the upgrade
when it did NOT work before, I have a hypothesis. Here goes: In some chips,
manufacturing defects and abnormalities sometimes might result in some current
path in the circuit being too close to another circuit path, resulting in 
more interference with each other. Now, an oscillating current will radiate
radio waves according to physics, so these radio waves might be interfering
with each other or there could be some capacitance thing or any number of
types of interference between the two traces. Now, an increase in frequency 
generally means an increase in power broadcast for radio waves and such, and
it could be that this increase in the radio wave energy pushes the chip over
the edge, to where the interference between traces finally proves fatal for
the chip and you get false signals as a result. Now, a semicunductor does NOT
behave the same as a metal as far as temperature response is concerned. While
in a metal a decrease in temperature causes a decrease in resistance, and thus
an increase in current for a given voltage, in a semicunductor a decrease in
temperature actually results in an INCREASE in resistance, which would result
in less current for a given voltage. So, by decreasing the temperature in the
chip you are also decreasing the current inside the chip, which would 
probably result in lesser interference due to radio wave emission and such, 
which would allow your chip to finally be within its operable range again. Now,
I do NOT know these statements to be true. They are at best educated guesses 
about what could be going on inside the chip. But, they are at least to me
plausible, and I welcome comment by someone who knows more than I. If they are
true, and this really is happening, then it would mean that if you ran a IIsi
pumped up to 25 MHz and HAD to have a heat sink to get it to work, you are
defintely sitting right on the edge of your tolerances, and it won't take
much change in your operating environment to get your machine to have all
sorts of errors. If my machine turns out to be like that when I do the upgrade
I will put the 40 MHz crystal back in and LEAVE the heat sink on. 
	Well, for what it was worth...
Seth Leigh
BYU Physics Dept.

Newsgroups: comp.sys.mac.hardware