From: ronkko@cc.helsinki.fi
Subject: VLSI CHIP SETS (Oli: Ei-asiaa...)
Organization: University of Helsinki
Distribution: sfnet
Date: Sun, 3 Jan 1993 14:39:01 GMT

In article <OAHVENLA.93Jan3002748@lk-hp-4.hut.fi>, oahvenla@snakemail.hut.fi 
(Osma Ahvenlampi) writes:

> YOW! Miss{ t{ll{isest{ aikataulusta on puhuttu?! Eih{n t{ss{ sitten 
> kannattaisi ruveta laajentamaan tai vaihtamaan konetta, kun inttikin on 
> edess{...

Aikataulusta en tied{, mutta grafiikkapiirien ominaisuuksista kertoi Lewis 
Eggebrecht Toronton WOCissa. Seuraava leike on Scott Withingtonin katsauksesta
(joka oli comp.sys.amiga.review-ryhm{ss{; sis{ll|n luotettavuutta en pysty
arvioimaan enk{ ota siit{ vastuuta;-).

FUTURE VLSI CHIP SETS

        CONSUMER AND LOW END SYSTEMS

        - 2 chips each with >100k transistors
        - synchronous to video clock
        - 160 - 280 pin packages
        - 32 bit DRAM or VRAM
        - 57 MHz pixel clock
        - ECS & AGA downwardly compatible. Ensuring this is one of the
          things that slows development
        - Support for 1, 2, & 4 MB floppy drives using standard technology
        - support for ALL 32 bit Motorola CPUs (including 680x0, and 880x0)
        - 8x memory bandwidth over AGA, 2x (at least) blitter performance
        - 800 x 600 72 hz resolution, higher at lower refresh rates.
        - 1 - 24 bit colour at any resolution (this was decided the week
          before WOCA, at Pasedena he said 16 bit)
        - FIFO serial port with large buffer to support very high baud rates
        - 8 meg chip RAM, all but unlimited fast RAM

HIGH END SYSTEMS

        - 4 chips (750k - 1M transistors)
        - 32/64 bit VRAM
        - 57 - 114 Mhz pixel clock (asynchronous design)
        - chunky pixel mode (commonly used in IBM PC systems) which will be
          supported by the blitter (bit instead of word)
        - CD-ROM with 100 Mbit/sec transfer rate
        - frame buffer/grabber built in
        - screen promotion
        - 1k x 1k x 24 bit 72 hz screens (more at lower refresh)
        - 8 voice 16 bit >100Khz sound
        - on-demand DMA
        - 12 - 20 x memory bandwidth (32-64 bit memory)
        - 32 bit blitter (8x performance of AGA)
        - 24 bit true colour mode
        - will support multiple simultaneous chip sets working together,
          allowing separate displays, or drastically higher resolutions
          (multiprocessing)
        - enhanced hardware compress/decompress including JPEG/MPEG
        - video upgrade modularity
        - 100 Khz
        - 32 bit processor independent bus for new CPU's (multiprocessing)
          including RISC chips (they should announce a choice for RISC chip
          in less than 1 year)
        - asynchronous design
        - 1 downside is that it may not be 100% ECS/AGA compatible


PS. Katsaus l|ytynee kokonaisuudessaan nic:st{, jos se joltakulta meni
ohi silmien.

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  Reijo Ronkko     University of Helsinki, Dept. of General Microbiology,
                   Mannerheimintie 172, 00300 Helsinki, FINLAND
                   Fax +358-0-4735426     Ronkko@cc.helsinki.fi
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