From: derek@slab.slip.uiuc.edu (Derek Taubert)
Subject: The DMA thing (was Re: ROM 01 vs ROM 3)
Reply-To: derek@slab.slip.uiuc.edu (Derek Taubert)
Organization: Damage, inc.
Date: Fri, 22 Jan 1993 14:49:15 GMT

Whoops, sorry about that.  Here's the version for those of you who wanted to
read it:

unknown@apple.com (Matt Ackeret) asked me:

>  Anyway, also, have you ever figured out a way to get a full 24 bit
>  address from the RAM card slot?  If you could, it's then just a
>  matter of a very few simple 7400 series gates to demultiplex to
>  the correct SIMM/RAM bank, thus it'd be hella easy to build an 8
>  meg RAM card.  (I really dunno why Apple screwed up and didn't
>  simply put all 24 address lines to the RAM connector!)

>  Also, what exactly *IS* the deal with DMA?  I mean, there's a DMA
>  pin (at least I know there is to all of the regular slots, even on
>  previous //s)...  So what exactly is the conflict with RAM cards?

  Since your 2 questions are directly related, I'll try to answer both at the
same time.

  First, the memory connector on the IIgs does not have the full 24 address
lines for a very good reason.  The way Apple did it makes it very easy to
build an expansion board with DRAMs because the refresh and address
multiplexing is handled by circuitry on the main motherboard.  With the
addition of signals CROW0 - CROW1, it specifically makes it very easy to build
a memory board with 4 rows of DRAMs (256K or 1M DRAMs).
  Disregarding the address lines used for ROM access from the memory slot -
another lecture, the address lines FRA0-FRA9 supply both the row address and
the column address for DRAMs.  They are multiplexed onto these lines at
different times, corresponding to when CRAS and CCAS are enabled.  (I can tell
that you knew some of this, but I thought I'd elaborate for other folks)
  Now then, those 2 sets of addresses (row and column) and CROW0, CROW1 come
from the lower 22 bits of the main processor's address lines.  2^22 = you
guessed it, 4 Meg.  You should notice that this figure is not by coincidence
the same amount of memory that you can normally DMA to without a hitch.

  Let's review how the 65816 supplies a 24 bit address with only 16 address
lines on the physical processor, shall we?  During the rising edge of phase 2,
the bank address (highest 8 address bits) appears on the data lines.  The FPI
knows this, and uses the data lines to get those 4 bits that it needs to make
22 during a normal CPU cycle.  It is possible to do this manually (latch the
bank address off of the data lines), in fact you have to if you wish to put
more than 4 Meg on a RAM card.  For normal CPU memory accesses, this will work
just groovy.

  (Time for a Ross Perot - Here's the deal)  DMA is another story.  DMA cards
are designed to run the address and data lines just like the processor does,
so that the rest of the circuitry in the machine really doesn't care who is in
control.  However, when a DMA operation is occurring to the lower 4 Meg of
memory, the old Apple II cards won't be supplying a bank address during the
middle of the phase 2 clock.  Oops, how are we going to be compatible with
this?  No biggie, the FPI just goes and looks at address $C037 (which actually
happens to be an internal register to the FPI, so no memory access is
necessary) and uses that in place.  Groovy.
  Well, this causes a problem for the lonely memory card that doesn't have
$C037 as an internal register, and wishes to have more than 4 Meg on board.
It REALLY causes trouble if the lonely memory card is disregarding completely
what comes from the FPI, and just using the bank address it gets off of the
data lines for figuring out DRAM addresses - this is how we get 100% DMA
incompatible cards.

  The following may or may not be true, so somebody correct me if I'm wrong.
DMA compatibility above 4 Meg is not a function of the memory card, it is a
function of the DMA device that wants to do it.  Simply stated, if a card
wants to DMA to an address above the 4 Meg limit, it has to look just like the
65816 and supply the bank address on the data lines during the middle of
phase 2.

Clear as mud?  I though so.

Derek