From: email!vlsivie.tuwien.ac.at!ekrem@uunet.uu.net (Ekrem Saban)
Newsgroups: fj.mail-lists.apollo
Subject: Some errors and workarounds in Genesil
Date: 14 Apr 92 14:31:21 GMT
Distribution: fj
Organization: Technical University of Vienna
Return-Path: <apollo-list-errors@srvr1.engin.umich.edu>


Hi,

I will mail some errors I encountered in Genesil schematic, and the
workarounds.

********************************************************8
11.3.1992, 17:40

I found an error in Schematic entry. I created in a module called Shifter a
datapath which had only one interface and two busses. The interface had
a left and right shifter without a latch at all. There after I defined the
DP, I added it to the Shifter module with Add INstance from LocalLib. I
had following in- and outputs:

Ins:
D_IN  8 bits

SL_IP
SR_IP
EN
SL


Outs:
SL_OP
SR_OP

D_IN  8 bits

I had also automatically generated an icon which I later changed. I deleted
the bounding box and added a polygon and a few lines. Then, I shifted theports to a propper place and renamed some of them, both at icon and schematic
view. I made then several times an Accept Design, and got following errors:

.........

--- starting accept design ---
Starting schematic checks
check icon ports vs schematic ports
Errors: 1   Warnings: 0

Icon vs schematic port check:
  Errors:
    Schematic ports SL and SR_IP are at the same location

Schematic checks complete, 1 errors 0 warnings
cancelled


I marked several times these two ports in icon view, renamed them, but had
always the same result. Then, I started to do the changes in icon view deleting
the two ports, and got following error:

--- starting accept design ---
Starting schematic checks
check icon ports vs schematic ports
Errors: 1   Warnings: 0

Icon vs schematic port check:
  Errors:
    Schematic port 'SL' not found in icon view
    Schematic port 'SR_IP' not found in icon view
    Schematic ports SL and SR_IP are at the same location

Schematic checks complete, 3 errors 0 warnings
cancelled

After that, I renamed one of the ports and got the following error:

......
Icon vs schematic port check:
  Errors:
    Schematic port 'SL' not found in icon view
    Schematic port 'SR_IP' not found in icon view
    Schematic ports SL and SR_IP are at the same location


Fortunately, the tool crashed after I try to solve the problem by regenerating
the icon and all the ports, and when I started SCHEMATIC again, it accepted
the module without the dubious "location" error.

Work around: leave schematic after saving your design, then start it
again.

*****************
Schematic error (13.3.)

An 8 bit tristate buffer and inverter have the same in/output, called IN<8>
and OUT<8>, respectively. Their gates are connected to inv; this input isfirst inverted with a one bit, direct inv for the buffer. After an exceptdesign, following error message appears:

......
Computing gfl net flags ...
Writing gfl file gflmodel_tmp ...
Simulation model for _LOGIC_0 is up to date
*** ERROR: regime unspecified for tristate net OUT[0]
*** ERROR: regime unspecified for tristate net OUT[4]
bad net timing attributes
{
        error 1
        wr_genlconns 1
        schem_dogfl 1
        schem2genesil 1
}
cancelled

*************************
Schematic error (14.4.1992)

I defined following module, called cnt, as follows:

Module
type    name    inputs  outputs Clk     Set     Ctrl
-----------------------------------------------------
LAT     I320    D1      Q1      C1      Set
LAT     I349    D2      Q2      C2      Set
MUX     I54     I1, Q2  D1                      CTR
                (0, 1)

INV     I399    Q2      I1

portin  PH_A            C1
portin  PH_B            C2
portin  H_nCNT          CTR
portin  RES             Set

portout Addr    Q1

clkinfo I196    C2
clkinfo I199    C1
-----------------------------------------------------

Accept Design worked without errors or warnings. When I go to SIMULATION/SIMULATE, it said at the end of a long listing in the MESSAGES area, where
the only warning was

) WARNING:Schematic option is on, this is a read only mode.

.......
) Done with command  MARK:SIMULATOR MODEL--------------in Module:  /cnt
) Times: real=11s; cpu=2.1s (u=1.1s, s=0.9s) (c=1.9s)
)  Done with currency check
)  Linking sim model ...
)  Linking done
) phasea= 0  phaseb= 0
) phasec= PH_B undivided
pi
)    is of type  module  with  14 ports
) port 1 I TRUE  to  NC = H
) port 3 I FALSE  to  NC = L
) port 5 CI PH_B  to  NC = 0
) port 7 O Addr  to  NC = i
) port 9 I H_nCNT  to  NC = z
) port 11 I RES  to  NC = z
) port 13 CI PH_A  to  NC = z
sn RES 1
sn H_nCNT 1
ck
pi
)    is of type  module  with  14 ports
) port 1 I TRUE  to  NC = H
) port 3 I FALSE  to  NC = L
) port 5 CI PH_B  to  NC = 1
) port 7 O Addr  to  NC = i
) port 9 I H_nCNT  to  NC = 1
) port 11 I RES  to  NC = 1
) port 13 CI PH_A  to  NC = z

I couldn't find out *why* the simulator is not excepting PH_A as a phaseinput.
I have used the simulator often, but had never a problem with the phases.
Workaround: no real work around exists.

However, I made the following changes in the circuit above: I removed port
PH_B, and added an inverter as follows

Module
type    name    inputs  outputs Clk     Set     Ctrl
-----------------------------------------------------
INV     I410    C1      C2

This is obviously wrong, as the "PH_B" generated in this way is no more
non-overlapping. However, the SIMULATOR liked this "solution", and the module
cnt seemed working there:


)  Linking done
) phasea= 0  phaseb= 0
) phasec= PH_A undivided
pi
)    is of type  module  with  12 ports
) port 1 I TRUE  to  NC = H
) port 3 I FALSE  to  NC = L
) port 5 O Addr  to  NC = i
) port 7 I H_nCNT  to  NC = z
) port 9 I RES  to  NC = z
) port 11 CI PH_A  to  NC = 0
sn RES 1
sn H_nCNT 1
ck
pi
)    is of type  module  with  12 ports
) port 1 I TRUE  to  NC = H
) port 3 I FALSE  to  NC = L
) port 5 O Addr  to  NC = 1
) port 7 I H_nCNT  to  NC = 1
) port 9 I RES  to  NC = 1
) port 11 CI PH_A  to  NC = 1
sn RES 0
ck
pi
)    is of type  module  with  12 ports
) port 1 I TRUE  to  NC = H
) port 3 I FALSE  to  NC = L
) port 5 O Addr  to  NC = 1
) port 7 I H_nCNT  to  NC = 1
) port 9 I RES  to  NC = 0
) port 11 CI PH_A  to  NC = 1
sn H_nCNT 0
sk
pi
)    is of type  module  with  12 ports
) port 1 I TRUE  to  NC = H
) port 3 I FALSE  to  NC = L
) port 5 O Addr  to  NC = 0
) port 7 I H_nCNT  to  NC = 0
) port 9 I RES  to  NC = 0
) port 11 CI PH_A  to  NC = 0
sk
pi
)    is of type  module  with  12 ports
) port 1 I TRUE  to  NC = H
) port 3 I FALSE  to  NC = L
) port 5 O Addr  to  NC = 1
) port 7 I H_nCNT  to  NC = 0
) port 9 I RES  to  NC = 0
) port 11 CI PH_A  to  NC = 1
sk
pi
)    is of type  module  with  12 ports
) port 1 I TRUE  to  NC = H
) port 3 I FALSE  to  NC = L
) port 5 O Addr  to  NC = 1
) port 7 I H_nCNT  to  NC = 0
) port 9 I RES  to  NC = 0
) port 11 CI PH_A  to  NC = 0
sk
pi
)    is of type  module  with  12 ports
) port 1 I TRUE  to  NC = H
) port 3 I FALSE  to  NC = L
) port 5 O Addr  to  NC = 0
) port 7 I H_nCNT  to  NC = 0
) port 9 I RES  to  NC = 0
) port 11 CI PH_A  to  NC = 1

Now, the sematically wrong module (with none non-overlapping phases) works!!
But I doubt if it will work in real life.

******************************************
Schematic implementation error (14.4.1992)

When doing an add instance, one gets an Add-Instance window which has twosub windows, one for the selected library, the other for the contents ofthis library. The hot keys are for both windows starting with the numbers1 to 5. If one goes to the bottom window to add the logic_lib alu, say, (s)he
seems to have the choice to do it with the hot key [3]. This is not the case,
and the hot keys pressed in the bottom window (called in this case 'logic_lib')
are selecting the according entry in the 'Selected library' window, if the
same entry exists there also.

--

_________________________________________________________________ _ _______
     ________  	A. Ekrem SABAN		 /    Technische Universitat Wien
   /|    |    ekrem@vlsivie.tuwien.ac.at/ Inst. f. Technische Informatik
  /_|__  |__			       /	     Abt. HW & VLSI  
 /  |       |		      	      /Tel   : (1)58801/8144 ( 7-13 UTC)
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