HDTenEightyP/NetNews huggingface dataset:
From: mtj@babar.asd.sgi.com (Michael Jones)
Newsgroups: comp.arch
Subject: Re: TFP announcement from SGI?
Date: 27 Jan 1993 20:48:34 GMT
Organization: Silicon Graphics, Inc.
Distribution: world
NNTP-Posting-Host: babar.asd.sgi.com
Keywords: sgi arch tfp mips

Not an advertisement, just an answer and a pointer to more information.

In article <...>, dhess@Xenon.Stanford.EDU (Drew William Hess) writes:
|> The San Jose Mercury News had a small article today re: SGI's announcement
|> of their new supercomputers.  They also mentioned that the Power Challenge
|> systems use the TFP, which is, I believe, based on an earlier MIPS design
|> (R4000, I suppose) but with a floating point unit on steroids.  Has SGI
|> made any formal announcement of the TFP?  

Yes. Today at 10:00am EST in Washington DC. It was broadcast live via
satellite to a number of locations, including our corporate campus.

|> I believe that SGI did most of the development on the TFP in-house before
|> acquiring MIPS, so is SGI/MIPS going to make it available to third parties
|> as they do with the Rx000 series?

You can ask your sales rep, or can call the TFP marketing group for more
information about the True Floating Point (TFP) performance, architecture, 
and availability. The toll-free SGI information number is (800)800-7441.

|> On a related note, I thought that the new supercomputers had been dubbed
|> "Onyx," but the article makes no mention of this name.  Is the family
|> of supercomputers called "Challenge" and "Power Challenge," and the first
|> member of the family called "Onyx," or what?  I'm unclear on exactly
|> what was announced yesterday after reading the SJMN article (wouldn't be 
|> the first time).

Monday's press releases covered the Indigo XZ, the Indigo2, and Onyx. The
Onyx systems support up to 24-R4400 CPU's and up to 3 RealityEngine2's. A
high-speed 1.2 GByte/sec interconnect bus, new power, and other system
features are also involved. Onyx features the RealityEngine2, an advance
over the existing RealityEngine, and a lower-cost VTX system as well.

Today the Challenge server was announced and shown. It shares the same
system structure as Onyx, but exchanges graphics with more CPU's. The
new TFP processor and memory system architecture were also discussed. The
Power Challenge systems house up to 18-TFP CPUs, each with 300 MFlops
performance, for 5.4 GFlops system peak capability. Deskside versions
of both Challenge and Power Challenge exist.

The TFP architecture is quite innovative. Your sales rep, or the people
at the number above, can provide more information.

-- 

Be seeing you,      mtj@sgi.com  415.390.1455  M/S 7L-590
Michael Jones       Silicon Graphics, Advanced Graphics Division
                    2011 N. Shoreline Blvd., Mtn. View, CA 94039-7311
Newsgroups: comp.arch
From: Steinar.Haug@delab.sintef.no (Steinar Haug)
Subject: Re: Machines with cond. assignment instruction?
Organization: SINTEF DELAB, Trondheim, Norway.
	<C18y70.FCA@hermes.hrz.uni-bielefeld.de>
Date: Sat, 23 Jan 1993 17:48:23 GMT

horst@techfak.uni-bielefeld.de (Horst Hogenkamp) writes:
> As far as I know the definition of the SPARC architecture
> includes conditional moves from version 9 on.

Does anybody know if the SPARC Architecture Manual for version 9 is available
yet? Or any other written documentation for version 9? (I already have the
Architecture Manual for version 8.)

When I asked SPARC International some months ago, I was told that version 9
information was only available to members...

Steinar Haug, system/networks administrator
SINTEF DELAB, University of Trondheim, NORWAY
Email: Steinar.Haug@delab.sintef.no, 
	sthaug@idt.unit.no, steinar@tosca.er.sintef.no
Newsgroups: comp.arch
From: zrepachol@cc.curtin.edu.au
Subject: Re: Alpha 21064-AA chip manual
Organization: Curtin University of Technology
Date: Sat, 23 Jan 1993 21:18:44 GMT

In article <1993Jan21.170228.25261@vbohub.vbo.dec.com>, kaiser@mammal.vbo.dec.com (Peter Kaiser) writes:
> 
> The "DECchip 21064-AA Microprocessor Hardware Reference Manual" just arrived
> on my desk, so it's evidently now available.  Order number EC-N0079-72.
> 

What is in it? Any must have info over and above the 21064 'Data Sheet' and
the intro to design rev 1 stuff?

~Paul

Newsgroups: comp.arch
From: rf@cl.cam.ac.uk (Robin Fairbairns)
Subject: Re: UNIBUS and/or QBUS interface description?
Organization: U of Cambridge Computer Lab, UK
Date: Tue, 26 Jan 1993 13:24:42 GMT

In article <1993Jan25.181621.14786@bernina.ethz.ch>, merz@ips.id.ethz.ch (Andreas Merz) writes:
|> I am looking for documentation for the UNIBUS and the QBUS interfaces.
|> Where can i find something? (books, files, etc.)

I have a DEC handbook (copyright 1979, I'm afraid) called PDP11 Bus
Handbook, which I have always used for that sort of reference.  It's
not beyond the bounds of probability that it's now out of print...  :-)

However, the preface has as its final paragraph:

  An excellent discussion of buses in general, and the UNIBUS and
  LSI-11 bus in particular, can be found in the book COMPUTER
  ENGINEERING, A DEC View of Hardware Systems Design, written by
  [Bell, Mudge, McNamara] ... Digital Press; ... 1978

(I'm sure DEC won't mind me infringing their copyright to that extent...
--
Robin (Keep Radio 3 != Classic FM) Fairbairns       rf@cl.cam.ac.uk
U of Cambridge Computer Lab, Pembroke St, Cambridge  CB2 3QG, UK
Newsgroups: comp.arch
From: mbjr@austin.ibm.com ()
Subject: Re: Machines with cond. assignment instruction?
Originator: mbjr@bretz.austin.ibm.com
Date: Fri, 22 Jan 1993 15:07:52 GMT
Organization: IBM Austin


Some other machines that have conditional assignment instructions:

1- The IBM TJWatson VLIW, developed by K.Ebcioglu. Its instructions
	are best represented as a tree such as

		if cc1 then
			R1=R2+R3
		else if cc2
`			R2=R3+R4
		else 
		        R3=R4+R5

   In other words, it allows for some form of ANDing of condition codes
to be specified on the (long) instruction.

2- The SIGNETICS LIFE processor: there, every opcode has a third (boolean)
	input. It also is a VLIW

3- The Multiflow TRACE has a "conditional assignment" opcode

	The references are


[1] @Article(IBMVLIW,
        Author="K. Ebcioglu",
        Key="IBM_VLIW",
        Title="Some Design Ideas for a VLIW Architecture for
Sequential-natured Software",
        Journal="Proceeding of the IFIP Working Conference on Parallel
Processing",
        Place="Pisa, Italy",
        Month="April",
        Year="1988")

[2]@Article(LIFE,
        Author="J. Labrousse, G. Slavenburg",
        Key="LIFE",
        Title="CREATE-LIFE: A Design System for High Performance VLSI Circuits",
        Journal="ICCD 1988")

[3]@Article(Colwell88,
        Author="R. P. Colwell et al.",
        Key="Colwell88",
        Title="A VLIW architecture for a trace scheduling compiler",
        Journal="IEEE Trans. Comp.",
        Month="Aug",
        Year="1988")
-- 
	Mauricio Breternitz Jr, Ph.D.	 	mbjr@futserv.austin.ibm.com
	IBM AWD - Internal ZIP 9461
	11400 Burnet Road - Austin, TX 78758
	Austin TX 78758				 phone (512) 838 8531
Newsgroups: comp.arch
From: rschnapp@metaflow.com (Russ Schnapp)
Subject: Re: Machines with cond. assignment instruction?
Organization: Metaflow Technologies Inc.
Date: Mon, 25 Jan 1993 22:10:41 GMT

In article <1k0840INNjk0@ilx018.intel.com>, gss@ilx018.intel.com (Shavit Amir) writes:
|> The best way to perform a conditional move
|> is to have compares set or clear all the bits in a register.
|> Once that is done, conditional moves are simple.
|> 
|> AND R1, R2 -> R4    /* R1 containes the condition code */
|> ANDNOT R1,R3 -> R4
|> 
|> 
|> Gad

A conditional move is  "if (cond) a = b;"
while your solution is "if (cond) a = b else a = 0"
-- 

...Russ Schnapp
Email: netcom!metaflow!rschnapp or rschnapp@Metaflow.com or rschnapp@BIX.com
Metaflow Technologies   Voice: 619/452-6608x230;  FAX: 619/452-0401
La Jolla, California    Unless otw specified, I`m speaking only for myself!
Newsgroups: comp.arch
From: nynikkel@ssp11.seri.philips.nl (Jan Nikkelen)
Subject:         Post an article to current group
Originator: news@phcoms.seri.philips.nl
Organization: SERI-CEN Network Services, Philips C&P, Eindhoven, The Netherlands
X-Newsreader: Tin 1.1 PL4
Date: Fri, 22 Jan 1993 12:05:56 GMT
From: godmar@cs.tu-berlin.de (Godmar Back)
Newsgroups: comp.arch
Subject: IBM RS/6000 inverted pagetable / hashing alg.
Date: 28 Jan 1993 21:18:20 GMT
Organization: Technical University of Berlin, Germany
Distribution: h
NNTP-Posting-Host: luckwill.cs.tu-berlin.de

 I'm working on a preparation on the IBM RS/6000 machine architecture,
particularly its storage control system.

I've read a few articles dealing with that subject, but I can't figure
out, how the hashing algorithm works. Let me give you a short explanation
how I see these things upto the point I don't understand.

 The effective address of 32 bit is extended, using the segment ID
addressed by the corresponding segment register, to a 52 bit wide
virtual address. This virtual address is divided into a 40 bit wide part,
(the 40 most significant bits, referred to as virtual pagenumber) and
a 12 bit wide part containing the offset in the page.

 The purpose of an inverted pagetable is to assign the real 
pagenumber to the virtual pagenumber. It contains one entry for
every real page, that means, for instance, entry No. 4711 contains
the virtual pagenumber of the virtual page currently mapped to the
4711st real page.

 During normal storage access you have to assign virtual pagenumbers to
real pagenumbers, i.e. to find out which page table entry contains
the virtual pagenumber you are referring to. This is done by hashing.
A hashvalue is computed from the virtual pagenumber, and in a hashtable
a possible index for the page frame table is looked up. Afterwards
the virtual pagenumber is compared with the virtual pagenumber found
in that entry of the page frame table with this looked up index.
In case of collision you must follow a chained list in the pagetable.

The problem is, that the page frame table entry contains only the
27 high order bits of the virtual page number (which is 40 bit wide).
How can you be sure, that the entry found in the hashtable contains the
right virtual pagenumber ?

 Or, is it perhaps guaranteed by the hashing algorithm, that addresses
with equal lower parts (the 13 low order bits) are always hashed to
different indices in that hashtable, therefore providing different 
anchors for these lists? This could probably be done by
using those bits as some kind of subindex for the hashtable, maybe
the least significant bits of the index. The remaining bits would be
computed by hashing the 27 most significant bits. But that's just
a supposition, I don't know it exact.

Another question is, how big the hashtable is, and if its size is fixed
or not, and from which parameters it depends.

Thanks to everybody who has read upto this point, I'm sure that my
german-style English must be quite difficult to understand.

Thank you very much in advance! Please e-mail reply.

Godmar
Newsgroups: comp.arch
From: swm11@cl.cam.ac.uk (Simon Moore)
Subject: Re: Idea on super fast memory system
Organization: U of Cambridge Computer Lab, UK
Date: Wed, 27 Jan 1993 18:08:41 GMT

Tony Veijalainen suggested on memory chip cache and interleaved memory
segments, but what about pipelined memory access + interleaving?

 - Simon

[Simon Moore][University of Cambridge, Computer Laboratory][swm11@cl.cam.ac.uk]
From: davidsen@ariel.crd.GE.COM (william E Davidsen)
Newsgroups: comp.arch
Subject: Re: Harvard architecture
Date: 25 Jan 93 15:33:33 GMT
Reply-To: davidsen@crd.ge.com (bill davidsen)
Organization: GE Corporate R&D Center, Schenectady NY

In article <1993Jan24.180434.2420@nidat.sub.org>, Nitezki@NiDat.sub.org (Peter Nitezki) writes:

| Basically the second!
| 
| Once it was called Zuse architecture (then von Neumann took over).
| After a while it got a writable control/instruction (as you like it) store  
| and was called Harvard architecture; just to take over in the modern DSP  
| designs.

  I agree, and I don't have the refference, either.

  As a historical note, back in the bad old days I had an app which just
wouldn't fit in the 64k I could address with a Z80. And the budget
didn't allow something else (not that there was mush at that time). With
the help of a friend to hack the hardware, I came up with a solution, a
version of CP/M which loaded the program in one memory bank in so-called
"master mode," then jumped to the program in "slave mode."

  What we had done was bank switching, such that when the CPU did an
opcode fetch, the M1 cycle, it came from the code bank, and when the CPU
did any other data access it went in the "data" bank. The program was
all written in a B offshoot called IMP, so I could easily avoid the self
modifying code prevalent at that time.

-- 
bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
	A terible poker player can have a winning hand,
	A obnoxious fool can have a good idea.
	Both are winners, regardless of who has them.
Newsgroups: comp.arch
From: awolfe@moo.Princeton.EDU (Andrew Wolfe)
Subject: Re: Best 486dx setup.
Followup-To: awolfe@princeton.edu
Originator: news@nimaster
Organization: Princeton University
Date: Thu, 21 Jan 1993 15:50:17 GMT

In article <edm.727580219@wrs.com>, edm@wrs.com (Ed McClanahan) writes:
|> Okay, so I had a few of the specifics wrong before...

Can we take this 'I bought this' thread elsewhere please.  There are several
PC and Intel BBoards.


-- 
--------------------------------------
Andrew Wolfe
Assistant Professor
Department of Electrical Engineering
Princeton University
Xref: sparky comp.sys.sgi:19036 comp.lang.c++:19737
From: tpm@ecs (TP Monks)
Newsgroups: comp.sys.sgi,comp.lang.c++
Subject: Re: C++ templates, link simulation.
Date: 22 Jan 93 10:49:20 GMT

tpm@ecs.soton.ac.uk (TP Monks) writes:


>I'm using cfront on an sgi machine and have come across a problem.
>It appears that the link simulator is not capable of picking up
>undefined symbols in libraries.  I had a quick hunt through the doc 
>but didn't spot any mention of this... perhaps I was too quick..

It turns out that this is a bug for which there is a patch, for those
who are interested.

Tim

--
-----------------------------------------------------------------------------
Tim Monks                                Vision, Speech and Signal Processing
tpm@ecs.soton.ac.uk                                    Southampton University
Tel: +44 (703) 592774                                   Fax: +44 (703) 592895
Newsgroups: comp.sys.sgi
From: James Petts <pettsj@visigoth.demon.co.uk>
Subject: Re: emacs on CD that came with my Indigo?
X-Xxmessage-Id: <A784078465010855@visigoth.demon.co.uk>
X-Xxdate: Thu, 21 Jan 93 07:55:48 GMT
Organization: No Affiliation
X-Useragent: Nuntius v1.1.1d13
Date: Thu, 21 Jan 1993 07:55:49 GMT

In article <1993Jan21.023658.3069@odin.corp.sgi.com> Chris Carlson,
carlson@support.newport.sgi.com writes:
>Also, FYI, there is a copy of version 18.59 of GNU Emacs provided on the
>Developer's Toolbox CD as well as Epoch 4.0b1.  Both have been compiled
>successfully and run without any modification.

I've not come across this CD. Could you give more details about it pls?

 ===> James Petts <===

*** CAUTION - READ THIS .sig AT YOUR OWN RISK! ***************************
*                                                * NOTE! VISIGOTH HAS NO *
* Q. Wenn ist das Nunstueck git und Slotermeyer? * CONNECTION WITH ANY   *
* A. Ja!... Beiherhund das Oder die Flipperwaldt * OTHER SITE AT         *
*    gersput!                                    * DEMON.CO.UK           *
*                                                *                       *
**************************************************************************
*  pettsj@visigoth.demon.co.uk (preferred), pettsj@cix.compulink.co.uk   *
**************************************************************************
From: mikes@bioch.ox.ac.uk (Mike Smith)
Newsgroups: comp.sys.sgi
Subject: xdbx on SGI
Date: 27 Jan 93 09:53:19 GMT
Organization: Department of Biochemistry, University of Oxford
Originator: mikes@newton.bioch



Has anybody out there managed to build xdbx on their SG?

I know we have edge but I'd rather use one piece of sortware on all the
machines, and also the particular bug I'm looking at is one that only
shows itself when it displays on another (non-gl) screen.

Cheers,

Mike
From: tpm@ecs (TP Monks)
Newsgroups: comp.sys.sgi
Subject: 4D/20 UPGRADE!!
Date: 21 Jan 93 09:42:27 GMT


We have a good ol' 4D20G at the university here, and money from a grant
which will soon expire which may allow for an upgrade, but will not allow
for a new machine.  Is it possible to upgrade the machine to something
a bit more desirable in a vaguely cost effective way?

Tim
--
-----------------------------------------------------------------------------
Tim Monks                                Vision, Speech and Signal Processing
tpm@ecs.soton.ac.uk                                    Southampton University
Tel: +44 (703) 592774                                   Fax: +44 (703) 592895
From: olson@anchor.esd.sgi.com (Dave Olson)
Newsgroups: comp.sys.sgi
Subject: Re: Logical volumes as swap
Keywords: lv logical-volumes efs
Date: 26 Jan 93 06:26:49 GMT
Distribution: usa
Organization: Silicon Graphics, Inc.  Mountain View, CA

In <1993Jan25.225415.13319@eos.arc.nasa.gov> ssmith@eos.arc.nasa.gov (Stephen Smith) writes:
| 	Has anyone used logical volumes for swap under IRIX 4.05x?
| We've an interest in combining two smaller devices into one large swap
| area.

No, but you can easily have multiple swap areas (with less overhead
than an lv, low though that is).  See 'man swap'.
--
Let no one tell me that silence gives consent,  |   Dave Olson
because whoever is silent dissents.             |   Silicon Graphics, Inc.
    Maria Isabel Barreno                        |   olson@sgi.com
Newsgroups: comp.sys.sgi
From: yaron@aristo.tau.ac.il (Yaron Zabary)
Subject: Re: eudora, popmail/serialpop on IRIX
Organization: Tel-Aviv University Computation Center
X-Newsreader: TIN [version 1.1 PL8]
Date: Fri, 22 Jan 1993 18:15:28 GMT

Andrew Cassin (acas@cgl.citri.edu.au) wrote:
: pgiltner@epas.utoronto.ca (Philip W. Giltner Jr.) writes:

: >I would greatly enjoy getting eudora up & running on my system here at
: >the ole' university of Toronto Epas machine. Unfortunately, epas is

: handy. Alter your machines (epas) /usr/etc/inetd.conf to include
: the following lines:

: pop     stream  tcp     nowait  root    /usr/etc/popper         popper
: pop2    stream  tcp     nowait  root    /usr/etc/popper         popper

 Don't forget to add the relevant line to /etc/services (or to NIS maps).

pop       109/tcp
pop2      110/tcp

  (or was it the other way round, but it doesn't really matter, because you
want inetd to launch the same program for both TCP ports).

--

-- Yaron.
Newsgroups: comp.sys.sgi
From: ldl@cs.utah.edu (Louis Langholtz)
Subject: Problem running amd on multiprocessor IRIX host
Date: 25 Jan 93 13:07:06 MST
Organization: University of Utah Computer Science

We've been seeing a problem with amd running on a 4-processor sgi IRIX host.
I'm wondering if anyone else has seen this problem and if anyone has a fix for
it that they will send me. If you respond please email me directly as I don't
often get the chance to read this newsgroup.

Basically after running smoothly for several weeks the load average on
the host will start to climb without stopping. Amd gets into a blocking
situation where amd kids come about and are unable to resolve requests.
The kids just sit invincible in the kernel (kill -9 as root doesn't kill'em)
and load down the machine. We've seen this problem with several versions
of amd, most recently:

amd 5.2.2.2 of 1992/05/31 16:53:21 bsd44-alpha #0: Sun Dec 27 22:12:57 MST 1992
Built by ldl@lotus.cs.utah.edu for a mips running irix4 (big-endian).

Interestingly the same versions of amd have always worked fine on single
processor sgi IRIX hosts which points strongly at there being a bug in
IRIX's handling of multiprocessing that causes amd's troubles. So why doesn't
sgi's automounter have the same problem? Did sgi hack in a work around to
their own automounter? Can someone from sgi confirm any of this?

Thanks much.
--
Lou
-- 
Lou
unixsys
Newsgroups: comp.sys.sgi
From: senseman@lucy.brainlab.utsa.edu (David M. Senseman)
Subject: South Texas SGI User Group Meeting
Keywords: Onyx, Indigo Extreme, RealityEngine
Organization: University of Texas at San Antonio
Distribution: tx
Date: Wed, 27 Jan 1993 05:14:50 GMT

                SOUTH TEXAS SGI USER GROUP 
                     WINTER MEETING
                      ~~~~~~~~~~~

Date:      Friday, February 12th

Place:     John Peace Library Regent's Room
           University of Texas at San Antonio
           6900 N. Loop 1604 W. 
           San Antonio, Texas 

Schedule:  5:00 PM  Drinks & Demos 
           6:00 pm  Buffet Dinner
           7:00 pm  Technical Presentations
           8:30 pm  Open Discussions


Demostrations
__________________________________________________

On hand will be an SGI Crimson workstation equipped
with the high-end RealityEngine graphics subsystem.


Technical Presentations
__________________________________________________

Jeff Brown and Trey Prinz will present an overview 
of SGI's new product offerings:

 Indigo XZ(tm)        -- MIPS R4000 cpu (64-bit, 100 MHz)
  FAST                   2X the graphics performance
                           of the Indigo XS24
                         $23,000

 Indigo2 Extreme(tm)  -- MIPS R4400 cpu (64-bit, 150 MHz)
  FASTER                 2 Fast SCSI-II channels 
                           (10 MB/s throughput)
                         GIO and EISA buses
                         $35,000

 Onyx(tm)             -- MIPS R4400 cpu's (64-bit, 150 Hz)
  FASTEST                Multi-processors (up to 24 cpu's)
                         Good performance :)
                         $643,900
     


Sponsorship
_________________________________________________

South Texas SGI User Group meetings are sponsored by
UTSA's Center for Information Visualization and are
free to the public. 

For more information please contact:
      David M. Senseman, Director
      Center for Information Visualization
      University of Texas at San Antonio
      (210) 691-5485 (voice)
      senseman@lonestar.utsa.edu

-- 
David M. Senseman, Ph.D.              | Imagine the Creator as a low 
(senseman@lonestar.utsa.edu)          | comedian, and at once the world 
Center for Information Visualization  | becomes explicable.
University of Texas at San Antonio    |               H.L. Mencken
From: olson@anchor.esd.sgi.com (Dave Olson)
Newsgroups: comp.sys.sgi
Subject: Re: Compressed backups
Date: 23 Jan 93 19:05:07 GMT
Organization: Silicon Graphics, Inc.  Mountain View, CA

In <35176@adm.brl.mil> rose@baby.swmed.utexas.edu (Rose Oguz) writes:

| It seems to me that I can compress data before backing up by using -Z in 
| the bru command.  I have not figured out how to restore compressed files.
| Can someone please tell me what I need to do.

bru stores the fact that *it* compressed a file in the per-file header
on tape.  You don't need to do anything special to list or extract
such tapes.
--
Let no one tell me that silence gives consent,  |   Dave Olson
because whoever is silent dissents.             |   Silicon Graphics, Inc.
    Maria Isabel Barreno                        |   olson@sgi.com
From: LEVINE%FIDLER.decnet@sunman.chinalake.navy.mil
Newsgroups: comp.sys.sgi
Subject: Lost my list of new Info-Iris news groups
Date: 26 Jan 93 14:02:53 GMT


	The title says it. While cleaning up my old mail, the list of
info-iris news groups got the heave. Could some one send me a copy
of the new news groups ??

Michael N. LeVine  Naval Air Weapons Station, China Lake, Ca 93555, USA
Internet: levine%fidler.decnet@chinalake.navy.mil
(619) 939-2614  avn  437-2614 

 "Waiter, there's a bug in my soup!"        
 "No, Sir, it's not a bug, it's a feature!" 

Newsgroups: comp.sys.sgi