From: "jeff ruck" <jeff.ruck@channel1.com>
Newsgroups: comp.sys.amiga.hardware
Subject: cisc -vs- risc
Date: 9 Oct 92 16:02:39 EST
Reply-To: "jeff ruck" <jeff.ruck@channel1.com>
Distribution: comp
Organization: Channel 1 Communications

-> For the average to be 1.3 cycles per instruction, the effective
-> through-put of some must be 1 cycle. Maths I reckon.

1.2 to 1.3 cycles per instruction is getting very close to 1.0.
Although I don't think of it as an average, where some instructions are
1.1 cycles and others are 1.5 (which thus gives you an average of 1.3).
As many as 4 in 6 (I'm not 100% sure here) instructions require delayed
branching which will further slow things down.  All in all, most
instructions are around 1.2-1.3 cycles so the average quickly approaches
this.

-> In reality, every instruction goes through 6 stages:
-> instrution prefetch, decode, effective address calculation,
-> operand fetch, execution and writeback.
-> The stages work concurrently, with dual prefetch circuits
-> to cope with conditional branching (Both options covered).

That is true for a processor that uses a six-stage pipeline.  To give
another example, the Mips R4000SC uses an eight-stage pipeline, the
Alpha uses a seven-stage pipeline, and the i960CA has a three-stage
pipeline.  They're all different architecture designs.  If you want the
break down for any of those, or other third-generation processors ask.
I have the info filed.

-> In other words, there are two pipeline circuits, both able to execute
-> the whole instruction set? Assuming the two instructions don't
-> rely on one another, two instructions are completed (effectively) in
-> one cycle? Rather neat, if I take your meaning.

Let me give you a little more information (I was breif in my
previous explanation) with examples:  In a Superscalar design, the
processor issuses as many as 2 to 3 instructions per clock cycle via
parallel functional units.  The Alpha, i960, T9000 (and others) have
*four* functional units, this is even better!  Furthermore, it's well
known that in RISC designs a large percentage (perhaps as high as 50%
for Mips RISC processors [source unknown]) of the instructions are
Integer ALU ones. Thus, by having multiple ALUs provides a way of
speeding things up.  The design of more than one ALU is more apparent in
third-generation RISC designs.

Don't get my wrong, all of this is very complex.  When you start issuing
(as many as, which isn't always the case) 2 or 3 instructions per clock
cycle the problems of register conflicts and data sharing become very
complicated.  These problems are bad enough with a single pipeline, let
alone a multiple ones.  So new techniques of register renaming, and
register scoreboarding were designed to help detect and reduce data
dependencies and register conflicts.  As far as branching in
Superscalar designs, a branch can be as many as 2 cycles.  This just
isn't good enough (i.e. it's bad for a high-performance superscalar
design). The RISC designers had to come up with other/different ideas to
handle branching in a superscalar design.  So compilers were written
with a "branch detection bit" which *helped* with the scheduling of the
instructions.

I hope I've answered your question and/or curiousity.  I'm trying to
discuss too many things in too little of space.  My information is very
choppy, but you (hopefully) will get the gist of it . If there's
something (specific) you'd like to know about I'll do my best to give an
explanation.

--jeff

PS  I'm currently reading a paper on scheduling.  It hopefully give me
some insight for a paper on scheduling algorithms in RISC designs.
--
Channel 1 (R)   Cambridge, MA

From: colin@netgate.fido.de (Colin Hirsch)
Sender: uucp@netgate.fido.de