HDTenEightyP/NetNews huggingface dataset:
From: sysrick@orion.spd.louisville.edu (Rick McTeague)
Subject: Re: Help needed compiling Magic & Irsim on HP700 series machine
Date: Fri, 13 Nov 1992 14:15:56 GMT
Organization: University of Louisville

In <1992Nov12.211256.5202@ll.mit.edu> killoran@ll.mit.edu (Mike Killoran) writes:

>I'm trying to compile irsim (a simulator that comes with
>magic) on an HP 730.  It compiles without errors, but bus
>errors when reading in the parameters file.

>It looks like the function which allocates space is not
>aligning the data properly.  Has anyone gotten irsim to
>work on an HP 700 series machine?  I could really use
>some help here.

You've got it exactly right. The problem is that a template used for memory
allocation doesn't set things up right for longword alignment on a PA-RISC
processor. Here is a diff of (your source directory path here)/irsim/src/irsim/mem.c

diff mem.c mem.c_orig
93c93
<     double      align[1];
---
>     int      align[1];
102c102
<     double          align[1];	/* dummy used to force word alignment */
---
>     int          align[1];	/* dummy used to force word alignment */
534d533
< 

Rick
-- 

Rick McTeague
Electrical Engineering Department, Speed Scientific School
University of Louisville, Louisville, KY 40292
(502) 588-7020

Internet: sysrick@starbase.spd.louisville.edu

Disclaimer: I'm a stand-up comedian; if anyone takes me seriously, I'm
            doing something wrong!
From: alex@rolls.dsp.hellnet.org (Alexander Meidel)
Newsgroups: comp.lsi
Subject: MOSFET BSIM Model
Date: 23 Nov 92 14:55:46 GMT
Organization: DSP Semiconductors, Israel.


  I am looking for good description of MOSFET BSIM 
  
  Model for HSPICE. If somebody can recommend me 

  books or articles with detail explanation for 

  each parameter and especially for semi-empirical

  ones.


  Please, mail for me direct. My e-mail address:

  alex@dsp.hellnet.org

  Thanks for advance.

----------------------------------------------------------------

  MEIDEL ALEXANDER    DSP SEMICONDUCTORS ISRAEL

                      alex@dsp.hellnet.org
----------------------------------------------------------------
Newsgroups: comp.lsi
From: yegna@cat.syr.edu (Yegnashankar Parasuram)
Subject: Problem using spice2g6
Organization: CASE Center, Syracuse University
Date: Fri, 20 Nov 92 01:44:42 EST

Hi all,

I am right now trying to simulate my MAGIC layouts using
Berkeley spice.  I am using 2g6, since I don't have their 
recent version at my place.  

The problem is that even for small cells with hardly 16 
transistors, I sometimes get the following error :

"
1*ERROR*:  INTERNAL TIMESTEP TOO SMALL IN TRANSIENT ANALYSIS
0          TIME =  2.00961D-07;  DELTA =  2.71138D-17;  NUMNIT =   6710
"

I get this error quite at random and am not able to make out what is
it that I am doing wrong.  I am doing a transient analysis and tried 
tweaking all the relevant options (ITL3, ITL4, ITL5) in the .OPTIONS
card.  But the error won't go !

I cannot also simulate rapidly changing signals (50ns clocks), since I
get this error.

I would be grateful if anyone could tell me how I can get over this problem.

Also I am working with an old version of the spice users guide (10/1/83).
Does anyone know where I can ftp a more detailed guide with a description
of error messages that I get while simulating my circuit.

Thanks !

-Yegna.




Newsgroups: comp.lsi
From: maarten@dutecaj.et.tudelft.nl (M. Hofman)
Subject: Carry sum redundancy.
Organization: Delft University of Technology, Dept. of Electrical Engineering
Date: Thu, 19 Nov 1992 14:51:20 GMT

Hi!

While working on a research on the usability of redundant arithmetic in general
purpose processors I stumbled upon a few problems. Maybe they aren't very big,
but I can't find the answer nonetheless. I'd like to ask the people on this
newsgroup for a solution.

It is all about carry sum redundancy. I know how it works, but in none of the
articles was something about the representation of negative numbers using carry
sum redundancy. Could somebody please tell me how one represents negative numbers
in carry sum redundancy?

The other problem I had was with the difference between carry sum redundancy and
signed digit redundancy. I mean, is there a difference in usage of hardware, speed
or complexity of the circuits needed?

Any help is much appreciated.

Greetings,

Maarten Hofman.

Newsgroups: comp.lsi,comp.lsi.testing
From: jcooley@world.std.com (John Cooley)
Subject: E-mail Synopsys Users Group (ESNUG)
Organization: The World Public Access UNIX, Brookline, MA
Date: Wed, 18 Nov 1992 09:23:20 GMT


  If you're using the Synopsys Design Compiler and/or their ATPG product, you 
  might be interested in joining the E-Mail Synopsys Users Group (ESNUG).

  What we are is a group of hardware designers from all over the world who
  wish to trade experiences, bug reports and the techniques that we've
  found that work best in getting a design from a behavioral description
  to a final fully tested product.

  A Sample of What We Discuss:

	- Known Synopsys Compiler Bugs    - Implementing Boundry Scan

	- Mentor related issues    - EDIF related issues

	- Hierarchical Compliations   - design_analyzer   - JTAG

	- How Various ASIC Vendors Model Their Macros.   - Clock Constraints

	- Using ATPG Tools   - The Best Way To Write State Machines in Verilog

	- Using VHDL   - System Simulation vs. Synopsys Friendly Code

	- Clever Workarounds to Known Pitfalls   - Testing Strategies

  In order to insure an open discussion, but yet keep our respective managers
  happy in having our company's projects remain SECRET, submissions to be 
  posted to the ESNUG mailing list can be stripped of identifying engineers 
  and company names if so requested.

  In addition, to further secure privacy and to avoid e-mail headers that
  are hundreds of names long, each mailing is a batch of singlely addressed 
  e-mail letters.

  If you know of anyone who may be interested in this, please give them
  my e-mail address (jcooley@world.std.com or jcooley@miracle.com) or you can 
  send me their address!
					- John Cooley
					  ESNUG Moderator

 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
     /o o\  /  it's a FEATURE!"   |    Backup Address: jcooley@miracle.com
    (  >  )                       |              (508) 429-4357
     \ - /       |   Snail Mail: P.O. Box 6222, Holliston, MA 01746-6222
     _] [_       |     "This here ain't no one's opinion 'cept my own."


Newsgroups: comp.lsi
From: danr@ais.org (Daniel Romanchik)
Subject: Re: board test
Organization: UMCC
Date: Sat, 21 Nov 1992 19:57:01 GMT

In article <lglr0dINN5oj@news.bbn.com> ekearns@bbn.com (Edward Joseph Kearns) writes:
>
>You are more than welcome to comp.lsi.testing.  In fact 1149.1 is 
>exactly why I came here a few weeks ago.  There was considerable
>response to my request for experince on the topic of boundary-scan,
>and by judging the responses I received, you will find no better
>forum to ask such questions.  Apparently this is where the 1149.1 
>experts occasionally hang out.
>
   Great! I'm glad to see some talk about board test here.

>I ordered and received some books from IEEE.  "The Test Access Port
>and Boundary Scan Architecture" by Maunder and Tulloss,  and also
>"Integrating Design and Test: Using CAE Tools for ATE Programming"
>by Ken Parker, so I've been busy reading.
>
    Ken Parker has a new book out, _The Boundary Scan Handbook_.  It's
published by Kluwer, and I think it's pretty good.  I can post my
review of it here if people are interested.

Regards, Dan
=====================================================================
        Dan Romanchik              |        danr@umcc.ais.org
       Technical Editor            |         (313) 930-6564
   Test and Measurement World      |     MCI Mail: tmwromanchik
=====================================================================
   "You can't test in quality" --  ancient Test Engineering maxim
=====================================================================
Newsgroups: comp.lsi.testing
From: mdanjou@gel.ulaval.ca (Martin D'Anjou)
Subject: Analog Testing Machine
Keywords: analog, test
Reply-To: mdanjou@gel.ulaval.ca
Organization: Dept. Genie Electrique, Universite Laval
Date: Wed, 18 Nov 1992 20:03:05 GMT

Hello,
	We would like to ear about any analog testing machine that tests analog chips.
	The tester should be able to drive (or ground) any pin (up to 16 pins at the same time at a rate of 20MHz) to any voltage (-8 to +15V @ 5mA/pin) or to any current (-5mA to +5mA/pin).
	The machine should be able to log (up to 16 pins (not the same pins as above!) at the same time at a rate of 20MHz) any voltage (-8 to +15V @ 5mA/pin) or any current (-5mA to +5mA/pin).
	Does any body knows if this machine exists? Where can we get it? How much $$$? Availability? We would rent it first.

	We currentely use two multimeters and one regulated variable power supply. DC measurements require 544 manipulations per chip. Any suggestion would help.

Martin d'Anjou
mdanjou@gel.ulaval.ca
From: chuck@ksr.com (Chuck Shavit)
Newsgroups: comp.lsi.testing
Subject: OOP and Testing
Date: 17 Nov 92 09:54:22 EST
Distribution: comp.lsi.testing
Organization: Kendall Square Research Corp.


Dear netters,

Writing ATPG and other testing-related tools in object oriented languages
(C++ comes to mind) seems like a good idea.  Did anyone in NetLand actually
do it?

Thanks,

Chuck Shavit, chuck@ksr.com
Kendall Square Research
Newsgroups: comp.lsi.testing
Subject: Re: board test
From: dlr@testeng.ksc.nasa.gov (Doug Reed)
Date: 20 Nov 92 17:20:46 EST
Organization: Voice Systems Engineering, Kennedy Space Center

>So Doug, While I'm trying to formulate my next question, let's hear 
>one from you!  Have you had any 1149.1 implementations tossed your way
>in board test.  Did your testers handle the task.  Who wrote the b-scan
>test vectors?  Did you have any internal scan paths?  Multiple paths?
>What where the major hurdles?  Did anything go completely wrong?
>
>Anyone else...?
>
>Ed Kearns

Ed:
So far we haven't had any 1149.1 designs come our way. I don't think
that the design guys in NASA have really gotten into it yet... they
are using XiLinx and Altera stuff to keep us pretty busy and I'm not
sure that if they started using 1149.1 chips whether they would write
on-board code for BIT or just for us board test people to crank out 
quicker tests. BTW, our board test equipment is being used for depot /
interlevel repair of broke boards that used to work. So 1149.1 tests
would be good for getting up a quick test of the board, but later 
(as time allows or testing requires) it would behoove us to write a 
more complete test. The built-in RAM tests that HP provides with the
tester tests a minority of addresses, and while that ok for the 
manufacturing environment looking for incorrectly mounted or dead chips
in quick test time, doesn't provide a thorough test in the depot 
environment.

Major hurdles? Getting design to put in gates to disable ttl
oscillators... :^) ... no flame intended. All things considered
we actually have a pretty good rapport with the design people.

Regards, Doug

-- 
+-----------+---------------------------------+--------------------------+
| Doug Reed | HP3065AT Board Test Engineering | Kennedy Space Center, FL |
| Ham Call N4QVY | #include <std_disclaimer> | Lockheed Space Operations |
+----------------+---------------------------+---------------------------+
Newsgroups: comp.lsi.testing
Subject: Re: board test
From: dlr@testeng.ksc.nasa.gov (Doug Reed)
Date: 20 Nov 92 17:24:26 EST
Organization: Voice Systems Engineering, Kennedy Space Center

>In article <1992Nov18.170306.4244@titan.ksc.nasa.gov>, dlr@testeng.ksc.nasa.gov (Doug Reed) writes:
>|> stuff deleted...
>|> genrag 1296 functional tester and the last 6 on an hp3065at.
           ^^^^-- should be 1796 tester. Ah, good, at least I'm
                  starting to forget!
>|> Regards, Doug

-- 
+-----------+---------------------------------+--------------------------+
| Doug Reed | HP3065AT Board Test Engineering | Kennedy Space Center, FL |
| Ham Call N4QVY | #include <std_disclaimer> | Lockheed Space Operations |
+----------------+---------------------------+---------------------------+
From: ekearns@bbn.com (Edward Joseph Kearns)
Newsgroups: comp.lsi.testing
Subject: Re: board test
Date: 19 Nov 1992 01:21:17 GMT
NNTP-Posting-Host: bbn.com

dlr@testeng.ksc.nasa.gov (Doug Reed) writes:
....
>Anyway, let me know if I'm off-base here or what.

>Regards, Doug

You are more than welcome to comp.lsi.testing.  In fact 1149.1 is 
exactly why I came here a few weeks ago.  There was considerable
response to my request for experince on the topic of boundary-scan,
and by judging the responses I received, you will find no better
forum to ask such questions.  Apparently this is where the 1149.1 
experts occasionally hang out.

For those that may be wondering, I'm still digesting all the 
information I was sent.  I've gone ahead and set up in-house demo's 
with TI and Fluke/Philips.  I've spoken with Alpine Image Systems, 
National Semiconductor, Teradyne, Tektronix...

I ordered and received some books from IEEE.  "The Test Access Port
and Boundary Scan Architecture" by Maunder and Tulloss,  and also
"Integrating Design and Test: Using CAE Tools for ATE Programming"
by Ken Parker, so I've been busy reading.

So Doug, While I'm trying to formulate my next question, let's hear 
one from you!  Have you had any 1149.1 implementations tossed your way
in board test.  Did your testers handle the task.  Who wrote the b-scan
test vectors?  Did you have any internal scan paths?  Multiple paths?
What where the major hurdles?  Did anything go completely wrong?

Anyone else...?

Ed Kearns
BBN Systems & Technologies
Bellevue, Washington
206-957-3271
Newsgroups: comp.lsi.testing
From: msengup@eos.ncsu.edu (MAITREYA  SENGUPTA)
Subject: Re: board test
Organization: North Carolina State University
Date: Thu, 19 Nov 1992 01:27:59 GMT

In article <1992Nov18.170306.4244@titan.ksc.nasa.gov>, dlr@testeng.ksc.nasa.gov (Doug Reed) writes:
|> I've been looking for an appropriate newsgroup in which to discuss
|> board test and related topics and it seems that this is the closest
|> that there is. Sci.electronics is too general and has too much flow,
|> but comp.lsi.testing seems to have appropriate discussion (at least
|> on 1149), and would like to see if other individuals agree (or
|> disagree). I've been in board test for ~12 yrs with 6 on the 
|> genrag 1296 functional tester and the last 6 on an hp3065at.
|> 
|> Anyway, let me know if I'm off-base here or what.
|> 
|> Regards, Doug
|> 
|> -- 
|> +-----------+---------------------------------+--------------------------+
|> | Doug Reed | HP3065AT Board Test Engineering | Kennedy Space Center, FL |
|> +-----------+----+---------------------------++--------------------------+
|> | Ham Call N4QVY | #include <std_disclaimer> | Lockheed Space Operations |

	For what it's worth, I think this is a perfectly appropriate forum for
discussing board test related issues. Unless you want to start up an new 
"comp.lsi.board.testing" group or something :-). 

Regards;

Maitreya (just my .02 worth) Sengupta.
Newsgroups: comp.lsi.testing
Subject: board test
From: dlr@testeng.ksc.nasa.gov (Doug Reed)
Date: 18 Nov 92 17:03:05 EST
Organization: Voice Systems Engineering, Kennedy Space Center

I've been looking for an appropriate newsgroup in which to discuss
board test and related topics and it seems that this is the closest
that there is. Sci.electronics is too general and has too much flow,
but comp.lsi.testing seems to have appropriate discussion (at least
on 1149), and would like to see if other individuals agree (or
disagree). I've been in board test for ~12 yrs with 6 on the 
genrag 1296 functional tester and the last 6 on an hp3065at.

Anyway, let me know if I'm off-base here or what.

Regards, Doug

-- 
+-----------+---------------------------------+--------------------------+
| Doug Reed | HP3065AT Board Test Engineering | Kennedy Space Center, FL |
+-----------+----+---------------------------++--------------------------+
| Ham Call N4QVY | #include <std_disclaimer> | Lockheed Space Operations |
Newsgroups: comp.lsi.testing
From: albert@sc.hp.com ()
Subject: Re: board test
Organization: Hewlett Packard, Semiconductor Test Systems
X-Newsreader: Tin 1.1 PL4
Date: Wed, 18 Nov 1992 22:42:44 GMT

dlr@testeng.ksc.nasa.gov (Doug Reed) writes:
: I've been looking for an appropriate newsgroup in which to discuss
: board test and related topics and it seems that this is the closest
: that there is. Sci.electronics is too general and has too much flow,
: but comp.lsi.testing seems to have appropriate discussion (at least
: on 1149), and would like to see if other individuals agree (or

Are there any LSI parts on the board?  Do VLSI parts cound as LSI?
How about some really big MSI parts? How about a 74bct8374?

Given that USENET is an anarchy, I guess my vote counts.

Albert Alcorn
Hewlett Packard
Semiconductor Systems Center
Digital IC Test products
(408|T) 553-7482
albert@sc.hp.com
From: johnl@iecc.cambridge.ma.us (John R. Levine)
Newsgroups: comp.compilers
Subject: report on USSA parser generator available
Keywords: parse, FTP, tools
Date: 15 Nov 92 06:10:44 GMT
Article-I.D.: comp.92-11-069
Reply-To: John R. Levine <johnl@iecc.cambridge.ma.us>
Organization: Compilers Central

I've put a postscript copy of Boris Burshteyn's report on his USSA parser
generator in the compilers FTP archive at primost.cs.wisc.edu as ussa.ps.Z.

It's not in the mail archive because it's much too big to mail.

Regards,
John Levine, johnl@iecc.cambridge.ma.us, {spdcc|ima|world}!iecc!johnl
-- 
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Newsgroups: comp.compilers
From: jeremy@sw.oz.au (Jeremy Fitzhardinge)
Subject: Re: Code optimization questions
Reply-To: jeremy@sw.oz.au (Jeremy Fitzhardinge)
Organization: Softway Pty Ltd
Date: Mon, 16 Nov 1992 08:10:20 GMT
Keywords: optimize, bibliography

cse264ce@cs.ucsd.edu (What Is) writes:
>[1] Is there any info on optimizers that take advantage of profiler
>    information?

There is the Coagulating Code Generator which uses basic-block level
profiling information to order the code generation phase.  The idea used
is that most used code should get first choice in registers etc.  It also
uses profiling information of control flow between basic blocks to
generate optimal linkages between them.  It does that at all levels (from
basic blocks to procedures).  It can also arrange for a code sequence to
take inputs in multiple ways depending on how control is passed to it.

The Mips C compiler will use pixie output to arrange code in a
cache-friendly way.

@inproceedings{karr84,
     AUTHOR = {Karr, Michael},  
     BOOKTITLE = {SIGPLAN notices},  
     MONTH = {June},  
     ORGANIZATION = {ACM},  
     PAGES = {11},  
     PUBLISHER = {ACM},  
     TITLE = {Code Generation by Coagulation},  
     YEAR = {1984}
}

@inproceedings{morris91,
title="CCG:  A Prototype Coagulating Code Generator",
booktitle="Proceedings of the ACM SIGPLAN '91 Conference on Programming
 Language Design and Implementation",
month=June,
pages="45--58",
author="W.G. Morris",
year=1991
}

	J
--
jeremy@sw.oz.au ph:+61 2 698 2322-x122 fax:+61 2 699 9174
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Newsgroups: comp.compilers
From: Dik.Winter@cwi.nl (Dik T. Winter)
Subject: Re: IEEE arithmetic handling
Reply-To: Dik.Winter@cwi.nl (Dik T. Winter)
Organization: CWI, Amsterdam
Date: Mon, 23 Nov 1992 20:32:17 GMT
Keywords: arithmetic


jlg@cochiti.lanl.gov (J. Giles) writes:
 > This is easily accomplished.  Let `b' be the base of your floating point
 > representation and let `p' be the number of digits in your significand.
 > Then, output followed by input is the identity if:
 > 
 >         (m-1)     p
 >       10      >= b  - 1
 > 
 > Where `m' is the number of decimal digits output.

bill@amber.csd.harris.com (Bill Leonard) writes:
 > This doesn't seem to work.  Take an example: let b=2, p=4.  Thus
 >  p
 > b  - 1 = 15, so m=3.  Now consider the binary number 1.001, which has
 > 4 binary digits (as dicated by p=4).  This number, in decimal, is exactly
 > 1.125, which requires 4 decimal digits, thus exceeding the number m.

No problem, you output 1.12 or 1.13 whatever you fancy.  Now when you read
that back in you get your original back.  Unless your read routines are
wrong of course and read 1.12 or 1.13 back in as 1.25 or 1.00.  That is
the major part, not that output is exact but that output followed by input
is exact.

 >            (Of course, a computer using base 3 would be pretty strange.
 > :-)

On occasion on alt.folklore.computers you will read about that Russian
ternary beast.
-- 
dik t. winter, cwi, kruislaan 413, 1098 sj  amsterdam, nederland
home: bovenover 215, 1025 jn  amsterdam, nederland; e-mail: dik@cwi.nl

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Newsgroups: comp.compilers
From: Dave Gillespie <daveg@thymus.synaptics.com>
Subject: Re: Pascal parser wanted, was COBOL !
Reply-To: Dave Gillespie <daveg@thymus.synaptics.com>
Organization: Compilers Central
Date: Thu, 19 Nov 1992 21:45:09 GMT
Keywords: Pascal, parse

> Does anyone out there know where I could get source for a COBOL compiler ?
> Similarly for PASCAL... even a subset !
> [Past requests for Cobol parsers have turned up nothing free.  Isn't there
> some Pascal code in comp.sources.something? -John]

You can get my Pascal to C translator, p2c, from csvax.cs.caltech.edu.  An
earlier version of it was also posted to comp.sources.unix a couple years
ago; that may be what John is thinking of.

P2c parses a number of Pascal dialects, including Turbo Pascal, HP Pascal,
and several others, as well as some Modula-2.  It generates C code with a
variety of stylistic options.  If you wanted to strip off just the parser,
you could probably do that fairly easily.  The parser is an ad-hoc
recursive-descent affair, rather than a Yacc or Bison grammar.  (I found
the ad-hoc approach to work well for Pascal, and especially for the
bizarre composite of many Pascal dialects that I have to parse.)

								-- Dave
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Newsgroups: comp.compilers