From: mjohnson@netcom.Netcom.COM (Mark Johnson)
Newsgroups: comp.lsi
Subject: A problem for CMOS designers
Date: 19 Aug 92 03:16:00 GMT
Organization: Netcom Online Communications Service

A fun design problem just crossed my desk & I thought the
readers here might enjoy it.  It's about the right
complexity to be one of three or four problems on a one
week homework assignment in an IC design course for grad
students.  At least, in my opinion :-).

The challenge (and thus the fun) in the problem is figuring
out how to deal with signals that are less than one threshold
voltage away from the power rail.  My solution, for example,
contains a weirdness that would have to be called "seldom
employed" :-).

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
PROBLEM: You have a plain ordinary CMOS 2 micron technology
         to work with; it has an enhancement-mode NMOS
         transistor (VT = +0.75 volts) and an enhancement-mode
         PMOS transistor (VT = -0.75 volts).  By design rule
         law, all P-wells must be tied to 0.00 volts and
         all N-wells must be tied to +5.00 volts.

         Also by design rule law, you are not allowed to
         construct explicit resistors or capacitors or BJTs;
         all you have to work with are N-FETs and P-FETs.

     --->    Design an "inverting circuit" which switches
     --->    at Vin=0.4 volts.  That is, when you plot
     --->    Vout versus Vin (the so-called DC transfer function),
     --->    a sharp transition from high to low occurs at
     --->    Vin=0.4 volts.


         SPECIFICATIONS

             Speed is unimportant; if your circuit takes eight
             hundred nanoseconds to sense the input voltage
             and then switch its output, that's perfectly fine.
          
             It's OK for your circuit to be multi-stage;
             so if you happen to get a noninverting topology,
             just go ahead and slap a CMOS inverter on the
             end.  Hell, slap on three inverters. :-)
          
             Your circuit must not source or sink any current
             to/from the input.

             The value "0.4 volts" need not be too precisely
             achieved.  To be concrete, here are the
             Vout versus Vin specs (for nitpickers only).
             To make life easy, these specs need to be
             met only when the fab process parameters are
             at their typical (nominal) values, and the
             VDD voltage is exactly 5.000 volts, and the
             die is at room temperature (298 Kelvin).

                (i)   When Vin<0.2 , you must have Vout>4.9
                (ii)  When Vin>0.6 , you must have Vout<0.1
          
             If your circuit has hysteresis (which I don't
             recommend), both branches of the hysteresis
             loop must fit in the region defined in (i)
             and (ii) above.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Practically every set of real life CMOS process parameters
is just fine for doing the problem; what we seek is an "Eureka"
insight in circuit _topology_, moreso than a precise set of
device sizes ready for mask layout.  So the Correct Answer
to the problem is a topology and a prose explanation of why
that topology will give an "inverter" that switches at
0.4 volts (rather than at 0.1 volts or 0.7 volts or at VDD/2).


Enjoy!
  -- M. Johnson
Xref: sparky comp.lsi:530 comp.lsi.cad:874