From: adrian@csqx.cs.rhbnc.ac.uk (A Johnstone)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Re: Help needed with DMA circuit design
Date: 9 Oct 92 10:49:09 GMT
Reply-To: adrian@csqx.cs.rhbnc.ac.uk (A Johnstone)
Organization: Dept of Comp Sci, Royal Holloway & Bedford New College Uni London

In article <1992Oct8.075020.25475@ips.oz.au>, bruce@corona.syd.ips.oz.au (Bruce Paterson) writes:
 
|> As part of a larger system, I am currently designing a special purpose I/O
|> and control board on the ISA bus (16 bits). After the board "does its thing",
|> it has a block of data in its FIFO buffer (16 bits, of known length up to 2k).
|> It then generates an interupt. The interupt handling software then reads a 
|> status register on the I/O board, which resets the interupt and provides some
|> information. Then it simply reads each word of the data and then writes it to
|> memory. This seems fairly straightforward, but it should be quicker to do it
|> via DMA - but how? I find my reference "AT Bus Design" by Solari, very hard to
|> understand on this point.
|> 
|> The following seems possible:
|> (1) Interupt and read status, as above. Then the DMA handling routine sets up
|> the DMA controller.
|> That seems clear enough, but I can't seem to see how the DMA is then started.
|> The best I can guess is -
|> (2) Write to the I/O board some sort of "ready for DMA" instruction.
|> The I/O board hardware then drives the appropriate DRQ line high.
|> (3) Sometime later, the platform drives the appropriate DACK line low, and
|> the I/O board responds by driving DRQ low.
|> (4) The platform DMA controller then does successive I/O reads - memory writes
|> until the ammount of data (as loaded during (1) above into some register in
|> the DMA controller) has been transfered.
|> (5) The platform DMA controller sets the appropriate DACK line high. (it also
|> strobes TC high, but I don't seem to need that.)

This is all basically correct: you start the DMA off on the PC by programming the
8237A DMA controller and then unmasking its DMA request bits in much the same way 
as you would unmask an interrupt in the PIC.

|> Questions:
|> (a) Is the above the correct way, or is it workable but there is a better
|> way (or am I way off)? If there is a better or correct way, what is it or
|> where can I find it? (circuits please, not specification legalise.)
|> (b) What about loss of refresh cycles on an ISA bus during DMA? My system
|> may "do its thing" up to 100 times per second.
|>  
Refresh is handled by DMA channel 0 which has highest priority, so you should
be all right. On the PC, only single cycle DMA is allowed (as opposed to block 
mode) specifically to allow the refresh DMA a chance to run. Of course this does
reduce the overall throughput. If you're brave (a British Civil Service word
meaning dumb) you can program the 8237 to do block mode, but make sure that
the refresh a chance.

|> Other information:
|> (i) The system is designed for remote unattended operation so it must be
|> robust.
|> (ii) Small quantities (initially only one) so custom chips are out.
|> 
|> Thanks in advance.
|> 

If you send me more details of your circuit I'll show you how to wire it up for 
DMA. Postscript or FAX might be the thing, I don't know that News lends itself
to electronic diagrams! Roll on the day when all engineers use HDL's. My 
FAX number is 044 784 443420

                         Adrian

                  Adrian
Newsgroups: comp.sys.ibm.pc.hardware