HDTenEightyP/NetNews huggingface dataset:
From: zawodny@arbd0.larc.nasa.gov (Dr. Joseph M Zawodny)
Subject: Re: "Program code area full"
Organization: NASA Langley Research Center, Hampton, VA
Distribution: usa
Date: Thu, 1 Oct 1992 19:59:27 GMT

Yet another point/observation.  If IDL knows enough to print an error message
why can't it just dynamically allocate some more memory to do the job and not
bother the user.

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Joseph M. Zawodny   (KO4LW)                      NASA Langley Research Center
 zawodny@arbd0.larc.nasa.gov                      MS-475,    Hampton VA, 23681
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
From: knight@ll.mit.edu (Fred Knight)
Newsgroups: comp.lang.idl-pvwave
Subject: Re: Notes on CURVEFIT.PRO
Date: 6 Oct 92 17:16:37 GMT
Reply-To: knight@ll.mit.edu (Fred Knight)
Organization: Group 45, MIT Lincoln Lab.
Originator: knight@ll.mit.edu (Fred Knight)


In article <5OCT199223161224@stars.gsfc.nasa.gov>, landsman@stars.gsfc.nasa.gov|> (They are simple enough to add by individual users but I think it would
|> be better if RSI would standardize them.)
|> 
|>      (1)  Add a keyword determining the maximum number of iterations to
|>           be attempted.
|>      (2)  Add a keyword giving the chi square of the final fit.
|>      (3)  Add a /DEBUG or /VERBOSE keyword giving the results of each 
|>           iteration (these are now commented lines in the code)
|>      (4)  Add a parameter to choose which parameters to hold constant and
|>           which parameters to vary
I'd make this a keyword, e.g., /FIXED=[1,0,0,1,0] to hold the first and fourth
parameters constant.

|>      (5)  Maybe use the STATUS parameter of the INVERT function to signal
|>           a small pivot element
I would also add:

	(6)  Optional upper and lower bounds for varied parameters.
-- 
=Fred Knight (knight@ll.mit.edu)	(617) 981-2027
 C-483\\MIT Lincoln Laboratory\\244 Wood Street\\Lexington, MA  02173
From: cho@balboa.eng.uci.edu (Jae Cho)
Subject: info on VHDL simulators requested
Newsgroups: comp.lang.vhdl
Organization: University of California, Irvine
Date: 2 Oct 92 17:49:01 GMT

I would like to hear about the experiences of
users of Model Technology VHDL simulator and
those who use Mentor Graphics VHDL simulator.

I heard that Mentor's is not full 1076 complient.
Is this true?  On the other hand, I heard that
the device models from LMI is not supporting
Model Technology yet.

I would appreciate the responses.

Jae Cho.

P.S:  BTW, for those of you who wanted me to
      summarize the VHDL simulator information,
      I will post it as soon as I get all the
      informations sorted out.
Newsgroups: comp.lang.vhdl
From: kbunker@labhp9.cs.utah.edu (Kent Bunker)
Date: 6 Oct 92 12:06:41 MDT
Organization: University of Utah
Subject: on line VHDL documentation 


I'm just getting interested in behavioral descriptions.  Does anyone
know of some public domain documentation that describes VHDL?  I also
would be interested in any good text sources that could be purchassd.
- thanx  - Kent Bunker  kbunker@peruvian.utah.edu
From: shiv@cs.man.ac.uk (Shiv Sikand)
Newsgroups: comp.lang.vhdl
Subject: VHDL & CADENCE
Summary: request for info
Keywords: vhdl, cadence
Date: 5 Oct 92 12:21:20 GMT


I'm would be interested to hear from people who have used Cadence and VHDL
(not verilog). I am interested in both Edge and Opus, the functionality of
Cadence VHDL-XL, ease of use, other third party VHDL products used with
Cadence tools and any recommendations.

Thanks.

--
---------------------------------------------------
+ Shiv Sikand                                     +
+ AMULET Research, Department of Computer Science +
+ The University, Oxford Road, Manchester M13 9PL +
+ shiv@cs.man.ac.uk, +44-61-275-6149              +
+          ! I speak only for myself !   	  +
+   ---> Power savers do it asynchronously <---   +
---------------------------------------------------
From: MAS@ESONVM2.VNET.IBM.COM
Date: Mon, 28 Sep 92 10:09:44 FST
Newsgroups: comp.lang.vhdl
Subject: VHDL Random function
Reply-To: maskesonvm2.vnet.ibm.com
Organization: usetopt
News-Software: Usenet 3.0
X-X-From: Gerard Mas

Bonjour a tous,

I have learned that the new VHDL standard will include a random function.
In the mean time I would appreciate if someone might help me by sending
me his own, even if it is not a real random function.

Many thanks in advance,
Amicalement
Gerard

<Gerard Mas                          >
<IBM Essonnes Development Laboratory >
<VHDL Microcontroller modelling      >
<FRANCE                              >
<Internet address: gerardkvnet.ibm.com >
Newsgroups: comp.lang.vhdl
From: xiong@fzi.de (Xiong Xun)
Subject: Re: VHDL benchmark circuits
Reply-To: fzi.de
Organization: Forschungszentrum Informatik (FZI), Karlsruhe, Germany
Date: Thu, 1 Oct 1992 15:09:12 GMT

In article <1992Sep30.143317.5630@msuinfo.cl.msu.edu>, adc@tardis.msu.edu (Alan D. Cabrera) writes:
|> Does anyone know where I can get some VHDL benchmark circuits?
|> 
|> 
|> ---
|> Alan Cabrera				internet:  adc@tardis.cl.msu.edu
|> Computer Laboratory			phone:     (517) 353-3027
|> Michigan State University		fax:       (517) 353-9847
|> 514 Computer Center			bitnet:    CABRERA@MSU
|> East Lansing, MI 48824


ftp mcnc.mcnc.org
                               
cd pub/benchmark

...


X.X.
Newsgroups: comp.lang.vhdl
From: saji@thor.ece.uc.edu (Sandeep  Aji)
Subject: Re: Intermetrics 3.1 Analyzer Question
Originator: saji@thor.ece.uc.edu
Keywords: Intermetrics, analyzer, syntax
Organization: Unversity of Cincinnati, ECE Dept
Date: Sun, 27 Sep 1992 04:11:42 GMT


In article <1992Sep25.204535.6071@linus.mitre.org>, lac@linus.mitre.org (Lisa A. Crook) writes:
|> 
|> I have a question concerning the time expression syntax accepted by the
|> analyzer in the Intermetrics version 3.1 VHDL toolset.  While the Synopsys
|> analyzer, for example, requires a space preceding the time unit in a time
|> expression, Intermetrics accepts the time expression "10ns", as in
|>         wait for 10ns;
|>               or
|>         generic ( delay : time := 10ns;
|> 
|> But does Intermetrics *require* that there *not* be a space preceding the
|> time unit?  Would it also accept the expression "10 ns"?
|> 
|> Thanks in advance.
|> Lisa
|> --
|> Lisa A. Crook
|> lac@linus.mitre.org
|> The Mitre Corporation, Bedford, MA



 Intermetrics version 3.0 accepts both "10 ns" and "10ns". So I guess version 3.1
 should accept it too. (Vantage ver. 3.110 does not allow "10ns" though)

 
 Sandeep Aji
 Computer Architecture Lab.,
 University of Cincinnati.




-- 
  | 	Sandeep A. Aji			| saji@thor.ece.uc.edu      |
  |     University of Cincinnati   	| saji@hagar.ece.uc.edu     |
  |        FINAL FOUR 1992              | 	                    |
  |                                     | 			    |
From: steven@chicago.crhc.uiuc.edu (Steven Parkes)
Newsgroups: comp.lang.vhdl
Subject: Re: Intermetrics 3.1 Analyzer Question
Keywords: Intermetrics, analyzer, syntax
Date: 27 Sep 92 14:40:17 GMT
Article-I.D.: roundup.1a4h4hINN9id
Distribution: world
Organization: Center for Reliable and High-Performance Computing, University of Illinois
NNTP-Posting-Host: chicago.crhc.uiuc.edu

In article <1992Sep25.204535.6071@linus.mitre.org>,
lac@linus.mitre.org (Lisa A. Crook) writes:

|> I have a question concerning the time expression syntax accepted by the
|> analyzer in the Intermetrics version 3.1 VHDL toolset.  While the Synopsys
|> analyzer, for example, requires a space preceding the time unit in a time
|> expression, Intermetrics accepts the time expression "10ns", as in
|>         wait for 10ns;
|>               or
|>         generic ( delay : time := 10ns;

This issue was specifically addressed by the VHDL Analysis and Standardization
Group and the results are published in `The Sense of the VASG' available
through the IEEE.

Basically, they note that the Language Reference Manual states that there must
be a space between the `10' and the `ns' but that numerous examples do not have
the requisite space.  Moreover, several implementations accept the non-space
version.  After reflecting that modifying the language to accept the non-space
syntax introduces certain ambiguities, the conclusion was to leave the
language spec the way it is and to clean up the examples.

steven parkes ---------------------------------------
Center for Reliable and High-Performance Computing --
University of Illinois                             --
steven@crhc.uiuc.edu --------------------------------
Newsgroups: comp.lang.vhdl
From: dukes@mickey.eng.ohio-state.edu (Michael Dukes)
Subject: Re: VHDL benchmark circuits
Organization: The Ohio State University Dept of Electrical Engineering
Date: Mon, 5 Oct 1992 23:48:07 GMT

In article <1992Oct1.150912.20607@fzi.de> fzi.de writes:
>In article <1992Sep30.143317.5630@msuinfo.cl.msu.edu>, adc@tardis.msu.edu (Alan D. Cabrera) writes:
>|> Does anyone know where I can get some VHDL benchmark circuits?
>|> 
>|> 
>|> ---
>|> Alan Cabrera				internet:  adc@tardis.cl.msu.edu
>|> Computer Laboratory			phone:     (517) 353-3027
>|> Michigan State University		fax:       (517) 353-9847
>|> 514 Computer Center			bitnet:    CABRERA@MSU
>|> East Lansing, MI 48824
>
>
>ftp mcnc.mcnc.org
>                               
>cd pub/benchmark
>
>...
>
>
>X.X.


ftp verify.el.wpafb.af.mil

cd pub/VBM

mike dukes
dukes@verify.el.wpafb.af.mil

Newsgroups: comp.lang.vhdl
From: xiong@fzi.de (Xiong Xun)
Subject: RTL-->Gates
Reply-To: fzi.de
Organization: Forschungszentrum Informatik (FZI), Karlsruhe, Germany
Date: Tue, 6 Oct 1992 13:16:44 GMT

Anyone there knows where I can get the gate level specifications (both
structural and behavioral) for the RTL components (adder, mux, register ...). 
Is there any such library in the public domain? Thanks for any help!

Xun Xiong
Newsgroups: comp.lang.vhdl
From: adc@tardis.msu.edu (Alan D. Cabrera)
Newsgroups: comp.lang.vhdl
Subject: VHDL benchmark circuits
Date: 30 Sep 92 14:33:17 GMT
Reply-To: adc@tardis.msu.edu
Organization: Michigan State University

Does anyone know where I can get some VHDL benchmark circuits?


---
Alan Cabrera				internet:  adc@tardis.cl.msu.edu
Computer Laboratory			phone:     (517) 353-3027
Michigan State University		fax:       (517) 353-9847
514 Computer Center			bitnet:    CABRERA@MSU
East Lansing, MI 48824
From: lc1bocv1@cine88.cineca.it
Newsgroups: comp.lang.idl
Subject: idl info wanted
Date: 3 Oct 92 10:52:43 +0100
Organization: CINECA, Italian Interuniversity comp. centre

MY BOSS is upset because he doesn't know what IDL is,and if he is
upset ,i 'm upset ,too ( you know what I mean ).    
Please let me known :
- what is IDL (a know only it is a graphyc package ) ?
  is it a standard or a commercial package ?
   if it is a commercial one where is possible to buy it ?   
- on which kind of computer does it run ?
Thanks a lot for your survival ( for me ) replay.   
fabrizio ravegnani.

i is IDL
From: terry@esrg.ucsb.edu (Terry Figel)
Newsgroups: comp.lang.idl
Subject: NetCDF and HDF support in IDL-- When will it be here?
Date: 5 Oct 92 21:08:37 GMT
Reply-To: terry@esrg.ucsb.edu (Terry Figel)
Organization: UCSB Earth Space Research Group


-- 
I wanted to know when a version of IDL which reads NetCDF and HDF file will
be realeased.  I want to know if I should get someone else's or just wait for a new release of IDL.

Anybody know any dates?
-Terry

___________________________________________________________________________
Terry Figel				Internet: terry@esrg.ucsb.edu
Earth Space Research Group, UCSB	Phone   : 805-893-7039  
5276 Hollister Ave. #260		Fax     : 805-964-0157
Goleta CA 93111
___________________________________________________________________________
From: cindy@zoran.hellnet.org (Cindy Eisner)
Newsgroups: comp.lang.verilog
Subject: Re: Variable width assignments?
Date: 27 Sep 92 06:23:59 GMT
Organization: Zoran Microelectronics LTD. Haifa, Israel.

In article <rfall-240992171955@andrich.mv.us.adobe.com>, rfall@mv.us.adobe.com (Richard Fall) writes:
> Does anyone know if there's an easy way of doing the following
> in Verilog?
> 
>     I would like to be able assign a fixed value (say, zero),
>     declared as a single parameter ("zero") in assignment
>     statements where the variable on the LHS of the statements
>     may be of different bit width.
>     
> ...
> 
>     Before you rush to tell me that Verilog already does that
> by zero-extending the RHS side to fit the LHS side, I'll point
> out that I may want to do the same thing with a parameter in
> which zero-extending is not the correct behavior.  For
> example, I may want the value "5555...." to be assigned to
> registers that may be any multiple of 4 bits wide.
> 

besides doing zero-extension, verilog also does automatic truncation.

thus you can define:

parameter fives = 64'h5555555555555555;

and then assign it to a lhs of any width <= 64.  the extra bits will simply
be discarded.

-- 

    Cindy Eisner,                     Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: cindy@Zoran.HellNet.Org
    Advanced Technology Center
    Haifa 31204, Israel               Could be my employer doesn't agree.
From: adrian@csqx.cs.rhbnc.ac.uk (A Johnstone)
Newsgroups: comp.lang.verilog
Subject: Re: Verilog products for the PC
Keywords: Verilog
Date: 2 Oct 92 13:30:44 GMT
Reply-To: adrian@csqx.cs.rhbnc.ac.uk (A Johnstone)
Organization: Dept of Comp Sci, Royal Holloway & Bedford New College Uni London

View Logic (which can run on PC's as well as workstations) has a VHDL subsystem.
On the evrsion we have it is almost completely brain damaged, but they are now 
advertising a full implementation for the new release which is (I believe) shipping.


                           Adrian
From: nwillhit@ncratl.AtlantaGA.NCR.COM (Nelson Willhite)
Newsgroups: comp.lang.verilog
Subject: Re: Verilog products for the PC
Keywords: Verilog
Date: 30 Sep 92 19:28:14 GMT
Organization: NCR Engineering and Manufacturing Atlanta -- Atlanta, GA

In article <1992Sep29.155942.14669@henson.cc.wwu.edu> hanson@henson.cc.wwu.edu
(Ken Hanson) writes:
>I am interested in Verilog products for the PC (either DOS or windows based).
>If you know of any could you please send me a list of what they are called
>and who produces them.  The same goes for VHDL products.
>
>               Thanks, 
>
>                       Ken Hanson (hanson@henson.cc.wwu.edu)

Verilog Simulator for Windows ($3000+$600 maintenance):

Simucad, Inc. (Product is called Silos III)
(510) 487-9700
32970 Alvarado-Niles Rd.
Union City, CA 94587

VHDL Simulator for Windows or DOS 
($495 DOS version/$1495 Windows version):

Model Technology Inc.
15455 N.W. Greenbrier Parkway, Suite 210
Beaverton, OR 97006
(503)690-6838

These are the only two I know about.

Nelson Willhite
Newsgroups: comp.lang.verilog
From: lsto@huldra.tdata.no (Lech Slawomir Tomczak)
Subject: Verilog-HDL Mode for emacs
Organization: Tandberg Data A/S, Oslo, Norway
Date: Tue, 29 Sep 1992 10:15:35 GMT
X-Newsreader: Tin 1.1 PL3

[ Article crossposted from comp.emacs ]
[ Author was Lech Slawomir Tomczak ]
[ Posted on Mon, 28 Sep 1992 13:11:25 GMT ]

Does anybody have a Verilog-HDL mode for emacs?
If so, please mail to lsto@tdata.no

Lech Tomczak, Tandberg Data A/S, Oslo, Norway
Newsgroups: comp.lang.verilog
From: marek@cadence.com (Marek Ryniejski; x6259)
Subject: Public Domain Verilog perser/compiler
Organization: Cadence Design Systems/CAE Div, Lowell MA
Distribution: comp
Date: Wed, 23 Sep 1992 10:24:55 GMT


    Need a public domain Verilog parser/compiler. At least
lex and yacc files would be great. Please, send email
to marek@cadence.com .
--
Marek
From: hanson@henson.cc.wwu.edu (Ken Hanson)
Newsgroups: comp.lang.verilog
Subject: Verilog products for the PC
Summary: Verilog products for the PC
Keywords: Verilog
Date: 29 Sep 92 15:59:42 GMT
Article-I.D.: henson.1992Sep29.155942.14669
Organization: Western Washington University

I am interested in Verilog products for the PC (either DOS or windows based).
If you know of any could you please send me a list of what they are called
and who produces them.  The same goes for VHDL products.

		Thanks, 

			Ken Hanson (hanson@henson.cc.wwu.edu)
Newsgroups: comp.lang.verilog
From: johnw@oakhill.sps.mot.com (John Waite)
Subject: Coding for Synopsys
Organization: Motorola Microcontroller Division, MMTG, Austin, TX.
Date: Mon, 28 Sep 1992 20:30:59 GMT


Is there an FAQ having to do with coding for Synopsys?
Is there a newsgroup about coding for Synopsys?

Inquiring Brains Don't Know Yet,


-- 
John Waite             		AMCU Modular Microcontrollers
Motorola, Inc.			Systems Design
Mail Stop OE-320		
6501 William Cannon Dr. West	
Newsgroups: comp.lang.verilog
From: yount@fox.ece.cmu.edu (Charles Robert Yount)
Subject: legality of force?
Organization: Electrical and Computer Engineering, Carnegie Mellon
Distribution: comp
Date: Fri, 2 Oct 1992 20:45:53 GMT


I'm trying to find out what's legal on the lhs of a force statement.

I have the following:

module romp;
.
.
wire [0:31] alu_a;
.
.
endmodule

force romp.alu_a[2] = 1'b1;    <-- gives error; illegal lhs
force romp.alu_a = 1'b1;       <-- is ok.

Why won't the first one work?  Is there another way to force the value
of one bit?

Thanks in advance!
Chuck Yount, CMU ECE
From: elliot@Wellspring.COM (Elliot H. Mednick)
Newsgroups: comp.lang.verilog
Subject: Variable width assignments?
Distribution: world
Date: Sun, 27 Sep 92 01:03:16 GMT
Organization: Wellspring Solutions, Sutton, MA.
Reply-To: elliot@Wellspring.COM

In article <rfall-240992171955@andrich.mv.us.adobe.com> rfall@mv.us.adobe.com writes:
 >     I would like to be able assign a fixed value (say, zero),
 >     declared as a single parameter ("zero") in assignment
 >     statements where the variable on the LHS of the statements
 >     may be of different bit width.
 >
 > [example omitted]
 > 
 >     Before you rush to tell me that Verilog already does that
 > by zero-extending the RHS side to fit the LHS side, I'll point
 > out that I may want to do the same thing with a parameter in
 > which zero-extending is not the correct behavior.  For
 > example, I may want the value "5555...." to be assigned to
 > registers that may be any multiple of 4 bits wide.
 > 
 >     If there were a "sizeof" operator, this would be easy
 > to do by using it in conjunction with repeated concatenation
 > to produce the desired effect, but no such operator appears to
 > exist.

There isn't a "sizeof" operator, but there is no reason for one since the
length of the lvalue is always known and almost always easily determined.
What you want (if I understand the question correctly) is some variation
on the following:

`define smallsize 4
`define longsize 16
parameter constant = 1'h5;

reg [`smallsize-1:0] foo;
reg [`longsize-1:0] foolong;
...
foo = {`smallsize/4 {constant}};
foolong = {`longsize/4 {constant}};
...

Note that this will only work for sizes that are multiples of the radix
size.  If you need sizes that are not multiples, then define a long constant
which is the largest you would ever need and use it for everything (Verilog
will truncate as necessary):

`define longsize 64             // in bits
parameter constant = 1'h5;
paramater longconstant = {`longsize/4 {constant}};
...
foo = longconstant;
foolong = longconstant;
fooverylong [58:0] = longconstant;
...

Both examples are synthesizable.

Newsgroups: comp.lang.sigplan
From: bh@anarres.CS.Berkeley.EDU (Brian Harvey)
Newsgroups: comp.lang.scheme
Subject: Re: Mixing read and read-char
Date: 30 Sep 1992 16:25:01 GMT
Organization: University of California at Berkeley
NNTP-Posting-Host: anarres.cs.berkeley.edu

net@cs.tu-berlin.de (Oliver Laumann) writes:
>   (begin (read) (read-char))
> [...]
>I have noticed that different Scheme implementations behave differently
>in this case.

Yeah, good point!  This is one of those out-of-proportion-to-its-interest
big pains in the neck in trying to write portable Scheme code.

Probably it's easiest to be consistent if we say that the (read) should not
read the whitespace following the symbol, because then we don't have to think
about special cases.  (For example, what if you have symbol, space, newline.
Should the read absorb both, or just the space?)  But I'd be perfectly happy
with either behavior in the standard as long as something is in the standard.

While we're at it let's standardize ERROR, and let's have clearscreen and
setcursor (for text, I mean, not graphics).
From: Conal.Elliott@eng.sun.COM
Newsgroups: comp.lang.scheme
Subject: Re: CommonLisp "loop" macro for Scheme?
Date: 1 Oct 92 15:56:41 GMT
Article-I.D.: grover.13944.717955001
Organization: The Internet


Thanks to those who've replied.  I should have specified that I need
the fancy loop macro with all those special symbols (for, as, unless,
collect, ...), since that's what the program I'm porting uses.

                        - Conal
From: bevan@cs.man.ac.uk (Stephen J Bevan)
Newsgroups: comp.lang.scheme
Subject: Re: substring + why so many essential procedures
Date: 27 Sep 92 12:52:52 GMT
	<BEVAN.92Sep21112540@jaguar.cs.man.ac.uk>
	<JAFFER.92Sep22121638@camelot.ai.mit.edu>
	<BEVAN.92Sep23094831@tiger.cs.man.ac.uk>
	<PK.92Sep24140627@talitiainen.cs.tut.fi> <BEVAN.92
Organization: Department of Computer Science, University of Manchester
In-reply-to: pk@cs.tut.fi's message of 27 Sep 92 10:33:49 GMT

In article <PK.92Sep27123349@hakki.cs.tut.fi> pk@cs.tut.fi (Kellom{ki Pertti) writes:
   I guess it is just a matter of taste: your approach requires some
   actions by the user of the application, whereas I would like to be
   able to write applications in such a way that the application itself
   could provide the missing functionality. Of course the former does not
   rule out the latter,

Your phrasing suggests to me that you consider it weaker in some way.
The only "weakness" I see is that the method I propose it outside of
the language (as RnRS doesn't have the facilities to support one
insider the language) whereas you'd prefer one inside the language.
I see no reason why my method should require any more work by the user
than an a solution internal to the language.  If you can provide
specific examples of the things that are worrying you, then I'll do my
best to solve them.


   so maybe we should try to come up with something along the lines
   that you suggested that does need a RnRS to back it up.

[ I hope that was meant to be "does NOT need ..." ]

Well my solution is on the table for discussion.  If anybody else has
a any critisism of it or even a solution of your own, how about
throwing your hat into the ring?

bevan
From: conal@grover.Eng.Sun.COM (Conal Elliott)
Newsgroups: comp.lang.scheme
Subject: CommonLisp "loop" macro for Scheme?
Date: 29 Sep 1992 16:32:03 GMT
Organization: Sun Microsystems - 3D Graphics Technology Group - Mountain View, CA
Distribution: world
Reply-To: conal@grover.Eng.Sun.COM
NNTP-Posting-Host: grover

I'm looking into porting a Common Lisp program to Scheme, but it uses
the loop macro (among other, lesser, CL dependencies).  Does anyone
know of a loop macro implementation for Scheme?

Even better, are there packages for easing the job of porting CL
programs to Scheme?

---

                        - Conal Elliott