HDTenEightyP/NetNews huggingface dataset:
From: leonard@qiclab.scn.rain.com (Leonard Erickson)
Newsgroups: comp.security.misc,comp.org.eff.talk
Subject: Re: Stupid Licenses (YUCK!)
Date: 31 Dec 92 12:58:50 GMT
Article-I.D.: qiclab.1992Dec31.125850.9263
Reply-To: Leonard.Erickson@f51.n105.z1.fidonet.org
Organization: SCN Research/Qic Laboratories of Tigard, Oregon.

bhayden@teal.csn.org (Bruce Hayden) writes:

>leonard@qiclab.scn.rain.com (Leonard Erickson) writes:

>>>Why can't they just provide a release that fixes the old bugs without
>>>introducing (known) new ones?  Featurality first is the only explanation.

>>Well, I know of a case where this was tried, but one of the fixes involved
>>switching from a no longer supported (and *buggy*) comm library to a new
>>library that turned out to be buggier than expected. While waiting for
>>the fixes, the programmers decided to add a few of the "easy" features
>>users had been requesting. Which (of course) lead to a few new bugs.

>Appears to me to be a management problem, not a technical problem.

Hey, the programmers *are* the management. The outfit in question
is approximately 3 people *total*. 

Not everybody has huge staffs. This applies to a *lot* of the software
out there. Borland, Microsoft, and the other*big* companies can afford the
resources to do things your way. All the small outfits (especially the
shareware ones) *can't*. 

-- 
Leonard Erickson		      leonard@qiclab.scn.rain.com
CIS: [70465,203]			 70465.203@compuserve.com
FIDO:   1:105/51	 Leonard.Erickson@f51.n105.z1.fidonet.org
(The CIS & Fido addresses are preferred)
Xref: sparky comp.security.misc:2351 comp.org.eff.talk:7864
From: bhayden@teal.csn.org (Bruce Hayden)
Newsgroups: comp.security.misc,comp.org.eff.talk
Subject: Re: Stupid Licenses (YUCK!)
Date: 21 Dec 92 14:29:06 GMT
Organization: Colorado SuperNet, Inc.

charlie@umnstat.stat.umn.edu (Charles Geyer) writes:

>In article <1992Dec19.023609.26000@news2.cis.umn.edu> I wrote:

>  It is fair to say that no computer company puts quality first, ahead of
>  featurality.  Until they do, quality will remain abysmal.

>In article <bhayden.724865911@teal> bhayden@teal.csn.org (Bruce Hayden) replies:
>> Just take a software engineering course. We know how to test for bugs,
>> how to do software QC. We just don't do it. Often the company that is
>> shipping the premature software has a QC section. Almost as often
>> that QC group is at some level preempted by marketing. But how does
>> it look when I ask for that QC data when I sue you for defective
>> software. This is what is called a "smoking gun" by attorneys.

>Sounds to me like from a legal standpoint the best thing would be to replace
>fire the QC people so they won't generate any "smoking guns".

Well - you may be right. However, the lack of a QC group is in itself
an indication of a lack of due care. Needless to say though, this latter
is probably harder to prove in court.

>Things won't change until someone markets quality computer software and
>hardware and gives the customers a choice.  You can buy a Japanese car
>and tell Detroit to stuff it.  Why can't you buy a computer like that?

I would argue that it is the expectation level. I will admit that I will
often buy (and use) the feature rich program over the stable competitor.
However - I am running Windows, and not OS/2 precisely because I couldn't
get OS/2 to keep from crashing. It wasn't worth the effort, given that
Windows does everything that I want. Also note - I may not switch to
OS/2 when a stability release finally does happen. So it may starting
to happen.

>BTW this isn't an anti-American comment.  I just bought an American car
>(I'm giving Detroit one last chance).

Well, I have given up on Detroit. Especially when I had to drive them
as rentals. I can remember the dash board coming off into my lap in
an Escort with less than 5,000 miles on it. We tried the Chevy and the
Ford when we last bought a vehicle (last year), but quickly narrowed
it to either a Datsun (ok - Nissan) or a Toyota.

Bruce E. Hayden
(303) 758-8400
bhayden@csn.org
Newsgroups: comp.security.misc
From: eronald@fml.tuwien.ac.at (Edmund Ronald)
Subject: Morris info needed for article
Keywords: Worm, Internet
Organization: Technical University of Vienna
Date: Wed, 30 Dec 1992 21:46:52 GMT

 I need to find info on the Morris worm story, on the Internet somewhere,
 for an article I have to write this weekend. I am a Paris based computer
 writer, and my email in Paris is eronald@cnam.cnam.fr

Thanks for your time!


Newsgroups: comp.lsi.cad,comp.arch
From: philip@xilinx.com (Philip Freidin)
Subject: Re: Why no tri-state outputs in FPGA cells?
Organization: Xilinx Inc.
Date: Tue, 22 Dec 1992 19:12:51 GMT

In article <1992Dec17.170431.2520@xilinx.com> philip@xilinx.com (Philip Freidin) writes:
>
>Enter advertising mode:
>
>	One of the facilities of the Xilinx products that differentiates us
>	from all the other lowly wanna-bees is that our XC3000 and XC4000
>	products are full of tri-state buses. These are driven by what we

		etc... etc... blah blah.....  and other self-serving
		stuff about his company's products.

Here is some info on another manufacturer's products:

Concurrent Logic has a product called the CLI6005 (a member of a family
of products, but this is all I have seen data on so far) which has the
following characteristics (Note that I do not work for this company, nor
am I a "happy user" of their products. I am just doing some "truth in
advertising" stuff, and hope my management doesn't catch me :-)  )


The CLI6005 is an array of 7 by 7 big tiles (49 tiles) each madeup of
8 by 8 blocks (64 blocks per tile) for a total of 3136 blocks.

Each block can implement 1 or 2 2-input gates (not an exhaustive list
like the Xilinx products, but an interesting mix of combinations), or
a mux or a flipflop with 1 or 2 gates ( much simpler list of options).
Each block also includes a tristateable buffer, that connects to 
bus lines that span a tile (ie upto 8 tbufs in a row or column within
a tile). Their are facilities for these buses to span more than 1
tile, although some of this seems unidirectional. As their are 49 tiles
with atmost 32 of these tile spanning bus lines, theoretically you
could have 1568 such tbuf lines. Of course such a configuration couldn't
do anything useful. The architecture certainly could support a few
hundred such lines, and have logic and routing available to do useful
stuff.

	Philip Freidin  (408)879-5180


-- 
Philip Freidin: Product Planning Manager, Xilinx, INC
(rest of clever .sig still under construction....
		coming to a terminal near you, Real Soon Now (tm))

Newsgroups: comp.lsi.cad
From: cchase@cs.cornell.edu (Craig Chase)
Subject: Re: Parallel transistors in irsim
Organization: Electrical Engineering, Cornell University, Ithaca NY
Date: Tue, 22 Dec 1992 18:35:19 GMT

The patch I posted (and that Christos corrected) was for version 8.3, I believe that it works equally well with 8.6.

mark

-- 
----------------------------------------------------------------------
Mark Linderman            |         Cornell University
linder@ee.cornell.edu     | Department of Electrical Engineering
----------------------------------------------------------------------
From: killoran@ll.mit.edu (Mike Killoran)
Newsgroups: comp.lsi.cad
Subject: Re: Parallel transistors in irsim
Date: 22 Dec 92 17:50:21 GMT
	<BznDwt.8sz@deshaw.com>
Reply-To: killoran@ll.mit.edu (Mike Killoran)
Organization: group_102

In article <BznDwt.8sz@deshaw.com> christos@deshaw.com (Christos Zoulas) writes:

>   I don't know if this is the latest version of irsim, maybe Mark can
>   give us a clue about which version of irsim these patches are for, and
>   the author can tell us which version of irsim he is running?

>   Mark should also recompile irsim in the cad account :-)....


	According to version.c in src/irsim, I am using version 8.6.  I got
this along with magic from gatekeeper.dec.com a few months ago.  Is this the
latest?

	Thanks for the patches to allow for the dynamic allocation of parallel
transistors.  Is this any better than changing MAX_PARALLEL however? (besides,
obviously, storage space)  After changing MAX_PARALLEL the complaint about
too many parallel transistors went away... and the other message (internal
error: no events but npending set) showed up.  Will your patch fix this problem?

	-Thanks again,

	Mike Killoran
	killoran@ll.mit.edu
Newsgroups: comp.lsi.cad,comp.cad.cadence,misc.jobs.misc
From: vlsi2@sol.cs.wmich.edu (Vlsi Research)
Subject: Names of VLSI Companies
Keywords: VLSI, CAD, Names, Addresses
Organization: Western Michigan Univ. Comp. Sci. Dept.
Date: Thu, 31 Dec 1992 05:00:11 GMT

I am compiling a list of companies that either fabricate VLSI chips
and/or develop VLSI CAD tools. I shall greatly appreciate if you could 
email me name, address (postal, email), and telephone number of such 
companies.

Thanks

Sid
vlsi2@cs.wmich.edu
Newsgroups: comp.lsi.cad
From: christos@deshaw.com (Christos Zoulas)
Subject: Re: Parallel transistors in irsim
Organization: D. E. Shaw & Co.
Date: Tue, 22 Dec 1992 06:26:52 GMT

In article <1992Dec22.023221.1664@cs.cornell.edu> cchase@cs.cornell.edu (Craig Chase) writes:
>killoran@ll.mit.edu (Mike Killoran) writes:
>>We are trying to simulate a large chip (~700,000 transistors) with
>>irsim.  There are many (almost 7,000) parallel transistors making 
>>up the clock distribution cell.  When simulating this chip, irsim
>>gives the following complaint about all of the parallel transistors:
>
>>No problem, just edit conn_list.c, increase MAX_PARALLEL to 7000.
>>Do the same in globals.h and then recompile.  No problem.  Right?
>
>We had the problem with parallel transistors as well and fixed it by 
>dynamically allocating the array and increasing its size as needed.  What 
>follows is a context diff.  The first diff (to cad_dir.c) Is not really 
>to your problem, but I include it anyway.  (BTW, these fixes were done 
>by Christos Zoulas a couple years ago).
>
>Good luck,
>mark linderman (linder@ee.cornell.edu)
>

Since I was mentioned in this posting :-), I have to say that I did
send this fix to Arturo Salz two years ago and it never made it to the
irsim distribution. I think that the patch Mark posted is backwards
[patch will say that you need to apply -R]. It is missing a very
important part. In net.h you'll need to change n_par to something
larger than a character, otherwise you'll be indexing random values
when the number of parallel transistors goes above 127.  Here's a
forward patch to that...

I don't know if this is the latest version of irsim, maybe Mark can
give us a clue about which version of irsim these patches are for, and
the author can tell us which version of irsim he is running?

Mark should also recompile irsim in the cad account :-)....

G'night,

christos

*** net.h.orig	Thu Sep 13 16:39:48 1990
--- net.h	Tue Dec 22 01:19:12 1992
***************
*** 156,162 ****
      char     ttype;		     /* type of transistor */
      char     state;		     /* cache to remember current state */
      char     tflags; 		     /* transistor flags */
!     char     n_par;		     /* index into parallel list */
      Resists  r;			     /* transistor resistances */
      long     x, y;		     /* position in the layout (optional) */
      tptr     tlink;		     /* next txtor in position hash table */
--- 156,162 ----
      char     ttype;		     /* type of transistor */
      char     state;		     /* cache to remember current state */
      char     tflags; 		     /* transistor flags */
!     unsigned short n_par;	     /* index into parallel list */
      Resists  r;			     /* transistor resistances */
      long     x, y;		     /* position in the layout (optional) */
      tptr     tlink;		     /* next txtor in position hash table */
Newsgroups: comp.lsi.cad
From: jcastle@boi.hp.com (Jim Castleberry)
Subject: Re: Magic for DOS
Date: Tue, 29 Dec 1992 23:59:50 GMT
Distribution: usa
Organization: Hewlett-Packard, Boise Printer Division

In article <1992Dec20.204402.1020@noose.ecn.purdue.edu> helz@ecn.purdue.edu (Randall A Helzerman) writes:
>I've heard of a version of Magic for DOS.  Can anybody point me to
>an ftp site or tell me how I can get it?  Thanks!

From file note.10 on gatekeeper.dec.com, ftp dir /pub/DEC/magic/notes:

	[...]
	An earlier release of MAGIC, version 4, has been ported 
	to both the DOS and OS/2 operating systems.  
	The DOS version contains a fully functional editor,
	but is limited in memory size, as well as some other
	functions (no CIF file exchange).
	The OS/2 version is complete and requires 
	2 Megabytes of RAM.  Both versions require EGA 
	or VGA color graphics and a Microsoft-compatible mouse.
	Both versions of the software are being made 
	available in binary form to anyone in the U.S. by
	the MOSIS Users' Group for just a $25 handling fee.  
	To order, contact:
	
	     Bill Bryan, Chairman
	     MUG Steering Committee
	     P. O. Box 22366
	     Knoxville, TN 37933
	     Phone: (615)-576-6844
	     FAX:   (615)-576-2813
	     Email: bryanwl@ornl.gov
	[...]

A pointer to this info is contained in the FAQ for this newsgroup.

Newsgroups: comp.lsi.cad
From: u7410@sequoia.btv.ibm.com (Anthony R. Bonaccio/557822)
Subject: Re: Magic for DOS
Date: Tue, 22 Dec 92 14:04:32 GMT
Organization: IBM Technology Products, Burlington VT

In article <1992Dec20.204402.1020@noose.ecn.purdue.edu>, helz@ecn.purdue.edu (Randall A Helzerman) writes:
|> I've heard of a version of Magic for DOS.  Can anybody point me to
|> an ftp site or tell me how I can get it?  Thanks!

Get in touch with Professor Ron Williams at the University of Vermont  
(williams@uvm-gen.emba.uvm.edu).  He published a paper on this topic about
a year and a half ago in the IEEE Trans. on Education.

Tony Bonaccio                                     IBM Technology Products
From: aok@rice.berkeley.edu (Alan Kamas)
Newsgroups: comp.lsi.cad
Subject: Ptolemy 0.4 Release Now Available
Date: 23 Dec 1992 07:40:37 GMT
Organization: University of California, Berkeley
Distribution: world
NNTP-Posting-Host: rice.berkeley.edu
Keywords: dsp, ftp

The 0.4 release of Ptolemy is now available.

Ptolemy provides a highly flexible foundation for the specification,
simulation, and rapid prototyping of systems.  It is an object
oriented framework within which diverse models of computation can
co-exist and interact.  For example, using Ptolemy a data-flow
system can be easily connected to a hardware simulator which in turn
may be connected to a discrete-event system, etc.  Because of this,
Ptolemy can be used to model entire systems.

In addition, Ptolemy now has code generation capabilities.  From a
flow graph description, Ptolemy can generate both C code and DSP
assembly code for rapid prototyping.  Note that code generation is
not yet complete, and is included in the current release for
demonstration purposes only.

Ptolemy has been used for a broad range of applications including
signal processing, telecomunications, parallel processing, wireless
communications, optical phase lock loops, real time systems, and
hardware/software co-design.  Ptolemy has also been used as a lab
for signal processing and communications courses.  Currently Ptolemy
has hundreds of users in over 75 sites, both in industry and academia.

Ptolemy is available for the Sun 4 (sparc) and DecStation (MIPS)
architectures.  A port to the HP workstation is in progress.
Installing the system requires 49 Mbytes for Ptolemy (64 Mbytes
after you optionally rebuild) and 16 Mbytes for the Gnu tools
subset.  At least 8 Mbytes of physical memory are required.

Ptolemy has been developed at UC Berkeley over the past 3 years.
Further information, including papers and the complete release
notes, is available from the FTP site.

A license is no longer required to receive Ptolemy.  The source code,
binaries, and documentation are available by anonymous ftp from
	ptolemy.berkeley.edu
[ftp "ptolemy.bekeley.edu". login as "anonymous". cd "pub". get README]
--
Alan Kamas					aok@eecs.berkeley.edu
558 Cory Hall					phone: (510) 643-7683
University of California at Berkeley		fax:   (510) 642-2739
Berkeley, CA, 94720 USA
Newsgroups: comp.lsi.cad,comp.arch
From: sgolson@trilobyte.com (Steve Golson)
Subject: Re: Why no tri-state outputs in FPGA cells?
Organization: Trilobyte Systems
Date: Thu, 24 Dec 1992 01:38:54 GMT

In article <1992Dec14.221541.25270@dartvax.dartmouth.edu> pichet@coos.dartmouth.edu (Pichet Chintrakulchai) writes:
>Hello,
>
>I've been working on a project designing a processor with FPGA's.  One severe
>limitation I found is that their cells do not have tri-state outputs and thus
>forcing me to use MUXes on buses consuming a lot of the resources.
>
>Does anybody have any idea why they didn't make these cell outputs tri-state?

Possibly for the same reason that gate array vendors often don't allow
tri-state buses inside a design: it's hard to guarantee that you always
have only one driver on the bus (i.e. no multiple drivers, and no
floating buses).

-seg

Steve Golson -- Trilobyte Systems -- Carlisle MA -- sgolson@trilobyte.com
"As the people here grow colder, I turn to my computer..." -- Kate Bush
Newsgroups: comp.lsi.cad
From: killoran@ll.mit.edu (Mike Killoran)
Newsgroups: comp.lsi.cad
Subject: Parallel transistors in irsim
Date: 21 Dec 92 19:16:40 GMT
Reply-To: killoran@ll.mit.edu (Mike Killoran)
Organization: group_102


Hi,

We are trying to simulate a large chip (~700,000 transistors) with
irsim.  There are many (almost 7,000) parallel transistors making 
up the clock distribution cell.  When simulating this chip, irsim
gives the following complaint about all of the parallel transistors:

There are too many transistors in parallel (> 300)
Simulation results may be inaccurate, to fix this
you will need to increase this limit in conn_list.c

No problem, just edit conn_list.c, increase MAX_PARALLEL to 7000.
Do the same in globals.h and then recompile.  No problem.  Right?

Now, sure enough, the parallel transistor message is gone, but
now irsim says:

time 100ns; there are pending events (839)
.
.
.
internal error: no events but npending set


What's going on here?  I found where these errors are produced,
but can't figure out whats causing them.  Some things I tried
have left more questions than they answered.  Such as; I set
the MAX_PARALLEL to 600.  Same internal error, but no complaint
about the parallel transistors!  Just what is MAX_PARALLEL?  I 
then removed a large cell from the design and replaced it with 
a dummy cell (just connecting wires) -- but left all 7,000 parallel
transistors in place -- and got no errors.

So it seems that the internal error is not due to the parallel 
transistors, but the number of nodes to keep track of?

If anyone could shed some light on this problem, I'd be happy.



Mike Killoran
killoran@ll.mit.edu
Newsgroups: comp.lsi.cad
From: cchase@cs.cornell.edu (Craig Chase)
Subject: Re: Parallel transistors in irsim
Organization: Electrical Engineering, Cornell University, Ithaca NY
Date: Tue, 22 Dec 1992 23:20:32 GMT

killoran@ll.mit.edu (Mike Killoran) writes:
>   ...
>	Thanks for the patches to allow for the dynamic allocation of parallel
>transistors.  Is this any better than changing MAX_PARALLEL however? (besides,
>obviously, storage space)  After changing MAX_PARALLEL the complaint about
>too many parallel transistors went away... and the other message (internal
>error: no events but npending set) showed up.  Will your patch fix this problem?
>	Mike Killoran
>	killoran@ll.mit.edu

Mike,
I wish I could tell you that it would, but since I have not seen the       
problem (and actually have been out of VLSI circles for a couple years) I  
can't say that it will.  However, if you did not patch the header file     
that Christos mentioned (net.h) you could certainly be getting all sorts   
of problems.  The index into the array is defined as char.  If the offset  
has the 7th bit as one, it is treated as a NEGATIVE offset.  This will     
screw you to no end.  It is imperative that you make it an unsigned short  
or something like that.

mark


-- 
----------------------------------------------------------------------
Mark Linderman            |         Cornell University
linder@ee.cornell.edu     | Department of Electrical Engineering
----------------------------------------------------------------------
Xref: sparky comp.lsi.cad:1256 comp.lsi:760
From: johne@PROBLEM_WITH_INEWS_GATEWAY_FILE (John Eaton)
Subject: Re: synopsys schematic into cadence
Date: Mon, 28 Dec 1992 15:57:08 GMT
Organization: Hewlett-Packard VCD
X-Newsreader: Tin 1.1 PL5

Yatish Kumar (yak@bnr.ca) wrote:
: 
: 
: hi,
:   I am trying to read in an edif schematic from
: synopsys into cadence edge.  Unfortunately the only
: route seems to be a set of "dci" routines that
: cadence half provides.
: 
:   These routines cannot handle:
: 
: 	a.  Busses as output by synopsys.
Try setting:
edifout_no_array = "true";

in .synopsys
-------------------

John Eaton 
!hp-vcd!johne


Newsgroups: comp.lsi,sci.electronics
From: wkt@csadfa.cs.adfa.oz.au (Warren Toomey)
Subject: Spice Models available by anon ftp
Organization: Australian Defence Force Academy, Canberra, Australia
Date: Thu, 24 Dec 1992 00:03:02 GMT

A while ago I asked for pointers to ftpable Spice models, and got few replies.
I've managed to find some Spice models via anonymous ftp, and I've made all
the ones I've found ftpable from a machine here at work.

The site minnie.cs.adfa.oz.au contains ftpable models in the directory
Spice/Models. Each collection is in compressed tar format. The file
models.lst list the name of all the models in the directory.

I'd be interested in adding to my collection. So if you have any other models,
please let me know. I'm now interested in CMOS/TTL models (74LS & 4000
series).

	Merry Christmas!

		Warren Toomey		wkt@csadfa.cs.adfa.oz.au
Newsgroups: comp.lsi,comp.lsi.cad
From: bcarlson@lynx.cat.syr.edu (Brad Carlson)
Subject: yield estimation in digital CMOS VLSI
Organization: Syracuse University
Date: Wed, 23 Dec 92 14:53:17 EST

Please reply to bcarlson@sbee.sunysb.edu

Can anybody tell me if a model exists for the distribution of the delay of a
digital CMOS VLSI circuit as a function of process parameter variation?
That is, given the nominal delay of a circuit, I want to estimate
the yield for a given operating frequency.
References to articles describing such a model are sufficient.

Thanks in advance,
Brad Carlson
SUNY Stony Brook
Newsgroups: comp.lsi
From: eleleetk@nuscc.nus.sg (Teng-Kiat Lee)
Subject: SPICE model ftp site
Organization: National University of Singapore
X-Newsreader: Tin 1.1 PL4
Date: Wed, 30 Dec 1992 03:48:10 GMT


Hello, there was a posting recently about ftp-able spice
models from a site minnie.cs.adfa.oz.au. Has anyone out
there been successful in accessing the machine at all?

Thanks,
Kiat
----------------
Teng-Kiat Lee                        VLSI CAD & Design Lab
Internet: eleleetk@nuscc.nus.sg      Microelectronics Div.
Bitnet:   eleleetk@nusvm.bitnet      Dept. of Electrical Engineering
                                     National University of Singapore
Voice:    (065)-772-6319             10 Kent Ridge Crescent
          (065)-467-1518             Singapore 0511
----------------------------------------------------------------------          
Newsgroups: comp.lsi,comp.periphs,comp.arch,comp.arch.storage
From: sundaram@blackmail.eng.uiowa.edu (Subbiah Sundaram)
Subject: Req: Fastest CAM?
Date: Sun, 3 Jan 1993 17:39:13 GMT
Organization: Department of Elect. and Comp. Engr., University of Iowa, USA.
Keywords: Content Addressable memory

Hi,

	I want some info regarding Content Addressable memory.
I want to know about commercially available highspeed CAM's. I would
like to have information like the speed and the size of the CAM. 

Thanks,
Subbiah.

Newsgroups: comp.lsi