From: S_JUFFA@IRAV1.ira.uka.de (|S| Norbert Juffa)
Newsgroups: comp.sys.intel
Subject: Re: Setting of flags by "Shr" on different processors.
Date: 11 Jan 1993 13:06:40 GMT
Organization: University of Karlsruhe, FRG
Distribution: world
NNTP-Posting-Host: irav1.ira.uka.de
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In <1993Jan8.143630.14931@bilver.uucp> wbeebe@bilver.uucp writes:

> In article <1993Jan7.154426.3421@odin.diku.dk> terra@diku.dk (Morten Welinder) writes:
> 
> >	Mov	Ax,0
> >	Mov	Cl,0
> >	Cmp	Ax,-1		; Clear zero flag
> >	Shr	Ax,Cl		; Result is zero.
> 
> If I'm not mistaken, shift instructions with CL=0 will not execute, but
> will be handled as NOPs. I'm not sure what you complaining about.
> 
> -- 
> William H. Beebe, Jr. - wbeebe@bilver.UUCP
>                  UUCP - {ucf-cs,peora,uunet}!tarpit!bilver!wbeebe
>                       - bilver Public Access Unix, Orlando FL
>                       - (407)644-8327  2400/9600  24 hours  8N1


There has been a discussion here recently about the operation of the shift
instructions on Intel's 80x86 processors in the case that the shift count
is zero. The descriptions of the shift instructions in Intel's programmer's
manuals seem to be incomplete with respect to this problem. Only the 286
programmer's manual mentions that the flags are unaffected by the shift
instructions if the shift count is zero. Note that, starting with the Intel
80186, shift counts are masked off to the range 0..31. If the count is zero
after the masking operation, the shift instructions will not affect the flags
either. I tested the shift instructions on the 8086 and the 80386 and found
that indeed the flags are unaffected if the shift count is zero. Obviously,
shift instructions with a shift count of zero are executed as NOPs on all
80x86 CPUs. This includes the shift double instructions SHLD and SHRD, for
which the 386 and 486 programmer's manuals explicitly state that a shift
count of zero transforms the instructions into NOPs.

Norbert Juffa   (s_juffa@iravcl.ira.uka.de)


The relevant parts of the description of the shift instructions from Intel's
manuals follow:


Description of shift instructions in Intel 386 and 486 programmer's manuals
---------------------------------------------------------------------------

Operation

(* COUNT is the second parameter *)
(temp) <- COUNT;
WHILE (temp <> 0)
DO
  IF instruction is SAL or SHL
  THEN CF <- high-order bit of r/m;
  FI;
  IF instruction is SAR or SHR
  THEN CF <- low-order bit of r/m;
  FI;
  IF instruction = SAL or SHL
  THEN r/m <- r/m*2;
  FI;
  IF instruction = SAR
  THEN r/m <- r/m /2 (*Signed divide, rounding toward negative infinity*);
  FI;
  IF instruction = SHR
  THEN r/m <- r/m /2; (*Unsigned divide*);
  FI;
  temp <- temp - 1;
OD;
(* Determine overflow for the various instructions *)
IF COUNT = 1
THEN
  IF instruction is SAL or SHL
  THEN OF <- high-order bit of r/m <> (CF);
  FI;
  IF instruction is SAR
  THEN OF <- 0;
  FI;
  IF instruction is SHR
  THEN OF <- high-order bit of operand;
  FI;
ELSE OF <- undefined;
FI;


Description

[...]


Flags Affected

The OF flag is affected for single shifts; the OF flag is undefined for
multiple shifts; the CF, ZF, PF, and SF flags are set according to the result.



Description of shift instructions in Intel 286 programmer's manual
------------------------------------------------------------------

Flags modified

Overflow (only for single-shift form), carry, zero, parity, sign


Flags undefined

Auxiliary carry; also overflow for multibit shifts (only).


Operation

[...]
The overflow flag is set only if the single-shift forms of the instructions are
used. For left shifts, it is set to 0 if the high bit of the answer is the same
as the result carry flag (i.e., the top two bits of the original operand were
the same); it is set to 1 if they are different. For SAR it is set to 0 for all
single shifts. For SHR, it is set to the high-order bit of the original operand.
Neither flag bit is modified when the count value is zero.



Description of shift left instruction in Intel 8086 programmer's manual
-----------------------------------------------------------------------

Operation

(temp) <- COUNT
do while (temp) != 0
  (CF) <- high-order bit of (EA)
  (EA) <- (EA) * 2
  (temp) <- (temp) - 1
if COUNT = 1 then
  if high-order bit of (EA) != (CE)
     then (OF) <- 1
  else (OF) <- 0
else (OF) undefined


Flags affected

CF, OF, PF, SF, ZF
AF undefined


Description

SHL/SAL destination,count

SHL and SAL (Shift Logical Left and Shift Arithmetic Left) perform the same
operation and are physically the same instruction. The destination byte or
word is shifted left by the number of bits specified in the count operand.
Zeros are shifted in on the right. If the sign bit retains its original value,
then OF is cleared.
Newsgroups: comp.sys.intel