HDTenEightyP/NetNews huggingface dataset:
From: zakis@monu6.cc.monash.edu.au (mr john d zakis)
Newsgroups: comp.lang.vhdl
Subject: Re: VHDL (lex, yacc) : request
Date: 8 Apr 92 04:48:20 GMT
Organization: Monash University (Caulfield Campus)  Australia

In article <ku169cINNr59@spim.mips.com> philip@mips.com writes:
>
> I am also interested in obtaining any type of source code for a
>VHDL grammar parser.
>

So am I
thanks.

-- 
John Zakis              (zakis@monu6.cc.monash.edu.au)
Department of Electrical and Computer Systems Engineering
Monash University, 900 Dandenong Rd.,  Caulfield East 3145,  AUSTRALIA.
(ph) +61 3 573 2467  (fax) +61 3 572 2796
From: jh75629@cs.tut.fi (Hassinen Jari Juhani)
Newsgroups: comp.lang.vhdl
Subject: VHDL desc. of Sparc
Date: 9 Apr 92 13:25:49 GMT
Distribution: comp
Organization: Tampere Univ. of Technology, Finland.



Hello!

I am searching for VHDL-description of SPARC. Perhaps
you could forward this mail to someone who knows about
these vhdl things if you do not.

I am searching vhdl-description to my work on the
Tampere University of Technology.

Jari Hassinen
Tampere Univ. of Tech.
Finland

--

-jjh-

*** Toyota (oli: 911 ;) sen olla pit{{ ***
From: roberts@slc.unisys.com (Doug Roberts)
Newsgroups: comp.lang.vhdl
Subject: Synopsys and HP700
Date: 2 Apr 92 16:50:36 GMT
Organization: Unisys, Salt Lake City, Utah

HP 700 workstation? We are doing that here, and I am curious what your 
experiences have been.
From: roberts@slc.unisys.com (Doug Roberts)
Newsgroups: comp.lang.vhdl
Subject: synopsys, hp700, again
Date: 2 Apr 92 17:16:29 GMT
Organization: Unisys, Salt Lake City, Utah


We are installing the Synopsys synthesis software on a hp700 workstation.
Anybody else out there doing that? And what were your experiences? We are
just getting started.
Thanks.
.
Newsgroups: comp.lang.vhdl
From: rvutukur@uceng.UC.EDU (Raghunath Vutukuru)
Subject: BSDL
Organization: College of Engineering, University of Cincinnati
Date: Tue, 7 Apr 1992 13:24:21 GMT

Hi,
  
We are developing boundary scan structure synthesis and test vector 
generation tools as part of high-level synthesis system for multi-chip 
module design. 
  
We are looking into BSDL( Boundary Scan Description Language) to use it
as a means of specifying the various options in boundary scan structures
that should be synthesized automatically. Also the same description in BSDL
is intended be used by the test generation tool. 
  
We would appreciate any feedback on the usage of BSDL and its completeness
in describing the architecture for the purpose of synthesis and test vector
generation. We would also like to get in touch with people who are using
BSDL. Please send your mail to
   
         rvutukur@thor.ece.uc.edu
  
Thanks
  
Raghu Vutukuru and Prasad Subbarao
Electrical and Computer Engineering
University of Cincinnati
Cincinnati
-- 
Raghunath Vutukuru   email : rvutukur@uceng.uc.edu 
Electrical and Computer Engineering, University Of Cincinnati, Cincinnati.
From: hofstede@cs.utwente.nl (Jaap Hofstede)
Newsgroups: comp.lang.vhdl
Subject: Re: VHDL (lex, yacc) : request
Date: 10 Apr 92 07:41:45 GMT
Organization: University of Twente, Dept. of Computer Science

mickey@mogadon (Laurent ROCHETTE) writes:
> 
> I'm looking for a file containing a VHDL description grammar in lex and yacc format.
> Any location or file will be welcome.
> 	Thanks.
> 	
> -------------------------------------------------------------------------

I just finished a scanner and parser for VHDL. I have used REX and LALR
from the GMD compiler toolbox. It is not too difficult to transform
the REX and LALR files to LEX and YACC, although it is much easier to
change over to the GMD toolbox.

I am now polishing up the grammar with comments about the (necessary)
differences from the Language Reference Manual. I hope to complete this
within one week. I will be glad to send the files by email to whoever
is intereseted. Please ask me by email. I have already noted the names
of mickey, philip and zakis.

Jaap Hofstede                             Tel:   +31 53 893788
Dept. of Computer Science (INF/SPA)       Fax:   +31 53 356531
University of Twente                      Email: hofstede@cs.utwente.nl
PB 217
NL-7500 AE ENSCHEDE
The Netherlands
Newsgroups: comp.lang.verilog
From: odonohue@Cadence.COM (Sean P. O'Donohue)
Subject: Re: specify blocks
Keywords: verilog
Organization: Cadence Design Systems, Inc.
Date: Tue, 14 Apr 1992 06:28:51 GMT

In article <1992Apr11.231312.3546@henson.cc.wwu.edu> hanson@henson.cc.wwu.edu (Ken Hanson) writes:
>I am new to the verilog HDL, and am looking for a better description of 
>the use of specify blocks.  It appears to me that they are used to 
>force time constraints on signal propagation in a module.   And when
>a constraint has been reached a signal reg variable may be set to indicate
>this.  Is this correct?  Are there any other purposes to specify blocks,
>any good examples of thier use?  Any help would be appreciated.
>
>
>	  -- Ken Hanson (hanson@henson.cc.wwu.edu)

Specify blocks are used to specify timing constraints and timing checks.
Another very common use is "specparams"  They are variables that can be
read via the PLI routines and used for back annotating information back
into the verilog data structure.  Such as input/output capacitance, drive
strenghts and other cell dependant specifications.  For more details
on this look in the PLI reference manual and the example delay calculators
that ship with Verilog.



Newsgroups: comp.lang.verilog
From: gord@jericho.uunet.uu.net (Gord Wait)
Subject: parameters
Organization: S-MOS Systems, Inc. (Vancouver Design Center)
Date: Fri, 3 Apr 1992 22:20:32 GMT

In article <1992Mar30.211350.14338@ncsu.edu> hdeshma@eos03a-16pa.eos.ncsu.edu (HARSHAVARDHAN  DESHMANE) writes:
>
>although the parameter declaration is intuitive to use,
>can the same things be done by declaring the parameters
>to integers?
>In what way is a 'parameter' different from an integer? Sorry
>if this sounds silly, but I am unclear about the real reason
>for the declaration.
>
>harsh
>________________________________________________________________________________
>Harshavardhan Deshmane                                   * no fancy stuff*
>ECE Dept, North Carolina State University
>________________________________________________________________________________

For one thing, parameters can be altered when you instantiate a model.
For example:

	module testparams;
	parameter p1 = 5;
	parameter p2 = 8;

	initial
	  begin
	    $write("p1 is %d, p2 is %d\n", p1, p2);
	  end
	endmodule


Now when you use it you can change the values of P1 and P2 like this:

	module junk;
	
	item1 testparams;
	item2 #(1, 2) testparams;
	item3 #(9,10) testparamsl

	endmodule

In the above example item1 will print out the original values of 5 and
8, item2 will print out values of 1 and 2, and item three will print
out values of 9 and 10 for the p1 and p2 parameters. RTFM, page 12-8
volume 1 of Cadence Verilog 1.6.0.1

Gord


-- 
Gord Wait 	SMOS Systems Vancouver Design Centre
uunet!jericho!gord
From: hanson@henson.cc.wwu.edu (Ken Hanson)
Newsgroups: comp.lang.verilog
Subject: specify blocks
Summary: purpose of specify blocks
Keywords: verilog
Date: 11 Apr 92 23:13:12 GMT
Article-I.D.: henson.1992Apr11.231312.3546
Organization: Western Washington University

I am new to the verilog HDL, and am looking for a better description of 
the use of specify blocks.  It appears to me that they are used to 
force time constraints on signal propagation in a module.   And when
a constraint has been reached a signal reg variable may be set to indicate
this.  Is this correct?  Are there any other purposes to specify blocks,
any good examples of thier use?  Any help would be appreciated.


	  -- Ken Hanson (hanson@henson.cc.wwu.edu)
Newsgroups: comp.lang.verilog
From: odonohue@Cadence.COM (Sean P. O'Donohue)
Subject: Re: Attention Verilog AE's
Organization: Cadence Design Systems, Inc.
Date: Fri, 10 Apr 1992 00:03:37 GMT

In article <1992Apr2.162404.26989@berlioz.nsc.com> cdyer@vulture.nsc.com writes:
>Hello! Are there any Verilog AE's monitoring this news group?   The
>reason I ask this question is that I would like to see Verilog AE's get
>actively involved in this group by answering questions, posting bug
>reports, posting hot-fixes, and posting "white papers."  Your support
>can help to make Verilog a stronger product in the market and can help
>us work with your product more effectively!
>


I am a Verilog Field Application Engineer owrking out of the Irvine,Ca.
(Los Angeles, California) office.  Whenever I am not in the field and
can get a chance to log in and read the NEWS I will reply to whatever
questions might come up on this newsgroup.  I am encouraging other Application
Engineers in my office and others to participate in this group when
they get the time.

Sean O'Donohue
Field Applications Engineer, Cadence Design Systems
714-752-8451


Xref: sparky comp.lang.verilog:139 comp.lang.vhdl:217
From: kinzel@ibr.cs.tu-bs.de (Jens Kinzel)
Newsgroups: comp.lang.verilog,comp.lang.vhdl
Subject: UDL/I language desription?
Summary: looking for UDL/I language description
Keywords: UDL/I
Date: 8 Apr 92 09:25:39 GMT
Organization: TU Braunschweig, Informatik (Bueltenweg), Germany

I am looking for UDL/I language description to discuss differences
between VERILOG/VHDL and UDL/I. Is there anyone, who knows about an
article about this subject, and where to get it?


						Jens
From: rml@corwin.hw.stratus.com (Robert Larrivee)
Newsgroups: comp.lang.verilog
Subject: converting verilog pin states to GenRad Tester
Keywords: tester
Date: 9 Apr 92 10:32:13 GMT
Followup-To: rml@corwin.hw.stratus.com
Organization: Stratus Computer, Inc.

I am looking for a way to convert verilog pin states to a GenRad
DTS(digital test source). The DTS is for an incircuit machine.  We are looking
at creating a PLI routine, using the vcd file (verilog common dump), or 
creating a task to monitor when the pins changed state.  Monitoring the 
states would be easy but verilog does not have a "sense" state as a tester does, 
so it doesn't know when a bidir is driving or receiving.		Thanks for any info!!!

Bob
Newsgroups: comp.lang.verilog
From: odonohue@Cadence.COM (Sean P. O'Donohue)
Subject: Re: parameters
Organization: Cadence Design Systems, Inc.
Date: Tue, 14 Apr 1992 06:20:15 GMT

In article <1992Apr3.222032.11639@jericho.uunet.uu.net> gord@jericho.uunet.uu.net (Gord Wait) writes:
>In article <1992Mar30.211350.14338@ncsu.edu> hdeshma@eos03a-16pa.eos.ncsu.edu (HARSHAVARDHAN  DESHMANE) writes:
>>
>>although the parameter declaration is intuitive to use,
>>can the same things be done by declaring the parameters
>>to integers?
>>In what way is a 'parameter' different from an integer? Sorry
>>if this sounds silly, but I am unclear about the real reason
>>for the declaration.
>>
>>harsh
>>________________________________________________________________________________
>>Harshavardhan Deshmane                                   * no fancy stuff*
>>ECE Dept, North Carolina State University
>>________________________________________________________________________________
>
>For one thing, parameters can be altered when you instantiate a model.
>For example:
>
>	module testparams;
>	parameter p1 = 5;
>	parameter p2 = 8;
>
>	initial
>	  begin
>	    $write("p1 is %d, p2 is %d\n", p1, p2);
>	  end
>	endmodule
>
>
>Now when you use it you can change the values of P1 and P2 like this:
>
>	module junk;
>	
>	item1 testparams;
>	item2 #(1, 2) testparams;
>	item3 #(9,10) testparamsl
>
>	endmodule
>
>In the above example item1 will print out the original values of 5 and
>8, item2 will print out values of 1 and 2, and item three will print
>out values of 9 and 10 for the p1 and p2 parameters. RTFM, page 12-8
>volume 1 of Cadence Verilog 1.6.0.1
>
>Gord
>
>
>-- 
>Gord Wait 	SMOS Systems Vancouver Design Centre
>uunet!jericho!gord
>
You can also reference the parameters hierarchacly
	module junk;
	defparam junk.item4.p1=123; //this replaces p1 in
					//instance item4
 	testparams item1; 		//NOTE:
	testparams #(1, 2) item2;	//paramters appear after
	testparams #(9,10) item3;	//module name and before
	testparams #(9,10) item4;	//instance names.
	endmodule			//(This was an error in Gord's
					//example)
From: hl@cypress.com (Hank Lim)
Newsgroups: comp.lang.verilog
Subject: where are the archives for this group?
Summary: is this newsgroup archived?
Keywords: archives, geeks
Date: 14 Apr 92 16:59:15 GMT
Organization: Aspen Semiconductor, San Jose, CA
Originator: hl@as07

Hello veriloggers,

Are the archives for this newsgroup available by ftp?
If the answer is host uunet.uu.net is anyone else besides
myself having trouble ftp'ing to this host?

Thanks, Hank.

*******************************************************
"... remember it takes double-E's to spell GEEK ... "
Xref: sparky comp.lang.verilog:142 comp.lang.vhdl:227
From: fujiwara@tdo.sps.mot.com (FUJIWARA-Makoto)
Newsgroups: comp.lang.verilog,comp.lang.vhdl
Subject: Re: UDL/I language desription?
Keywords: UDL/I
Date: 10 Apr 92 08:47:56 GMT
Followup-To: comp.lang.verilog
Organization: Nippon MOTOROLA Ltd. Tokyo, Japan

kinzel@ibr.cs.tu-bs.de (Jens Kinzel) said:
 |I am looking for UDL/I language description to discuss differences
 |between VERILOG/VHDL and UDL/I. Is there anyone, who knows about an
 |article about this subject, and where to get it?


	I have UDL/I news letter March 1,1992, Vol1, Number 2:
	which says: Contact Information
	........................................
	UDL/I Committee U.S.A Branch
	Address :c/o Fintronic U.S.A Inc.
	1360 Willow Rd. suite 205
	Menlo Park, CA 94025,
	U.S.A
	
	Phone:	(415) 325-4474
	Fax:	(415) 578-0260
	........................................

	From them you may receive copy of version 1.0h4 ( 5/14/1991 ),
	although most recent version is: v1.0j ( 11/26/91 )
-- 
	Makoto Fujiwara 
	 Semiconductor Product Division, Nippon Motorola Ltd,
	  Tokyo, Japan
	   E-mail : fujiwara@tdo.sps.mot.com
From: Guenther.Goerz@informatik.uni-erlangen.de (Guenther Goerz)
Newsgroups: comp.lang.scheme
Subject: Scheme use in universities
Date: 15 Apr 92 13:00:57 GMT
Organization: The Internet
X-Unparsable-Date: Wed, 15 Apr 92 14: 57:20 MET DST

There are two new items for the list of educational uses of Scheme:

At my university (of Erlangen-Nuernberg) Scheme is used as *the*
first language in "Problem-oriented Programming for Computer Scientists"
(from next year on: "Algorithmics I") which is a obligatory course
for c.s. freshmen (1st semester) and therefore being taught every winter
semester.  Audience last winter: ca. 250 students.

From 1989 to 1991 I was with the university of Hamburg where I
lectured "A2" (= Data Structures and Algorithms) where Scheme is and
has been *the* language.  This course is also obligatory for freshmen
in c.s.  (2nd semester) and is being taught every summer semester.
Audience: ca. 280 students

---Guenther
-- 
Prof. Dr. Guenther Goerz          Phone: (+49 9131) 699-126; -140
Univ. Erlangen-Nuernberg            Fax: (+49 9131) 699-198
IMMD8 - KI (Computer Science)    e-mail: goerz@informatik.uni-erlangen.de
Am Weichselgarten 9                      goerz@sumex-aim.stanford.edu
D-8520 ERLANGEN
Newsgroups: comp.lang.scheme
Subject: Yet news about PC-Scheme
From: vuilleum@uni2a.unige.ch
Date: 7 Apr 92 20:38:54 +0200
Organization: University of Geneva, Switzerland

   Since 1988, Texas hasn't provided any major enhencement to PC-Scheme.
Source code is available, but so dirty and buggy that nobody could maintain
it, not to say making any innovative use of it.
   Anyway, there are still quite a lot of people who are interested in
developping under a small yet powerfull Scheme interpreter, running on PC
computers. Some users recently wanted Mouse support, other R^4, and so on.

   Now we have been working for some months on a general update of PC-Scheme
source code; C-written parts have been translated into Borland C (instead
of the obsolete Lattice), auto-modifying code has been cleaned in order to
run on 486 computers, BGI graphics will be implemented and further extensions
are widely open (including R^4).
   Although the original code looks really ugly, the algorithmic foundments
of PC-Scheme are really good: it is implemented as a virtual machine,
memory use and garbage collecting are optimized through pseudo-pages, and
everything is build up to be extended. One lack: no documentation... but
we shall write down what we understood of this huge code and what we did
modify before the new source code will be distributed.

   The upgraded version of PC-Scheme (Geneva version) will be available as
soon as finished and when the License Agreements with Texas Instruments will
be settled down. Right know, we are searching for a contact in Texas; any 
reply on this point would be appreciated. If no major problem occurs, Beta
version should be available in the very next months.

   Suggestion and remarks are welcome. Please use E-mail.
   
                                           Laurent Bartholdi &
                                           Marc Vuilleumier,
                                           University of Geneva.

----------------------------------------------------------------------------
Does a chicken like to peck ?                              (Garfield)
----------------------------------------------------------------------------
From: jmiller@crl.DEC.COM
Newsgroups: comp.lang.scheme
Subject: "Real world" Scheme use
Date: 14 Apr 92 18:59:58 GMT
Reply-To: JMiller@crl.dec.com
Organization: The Internet

OK, OK, it comes up every once in a while and we all get bothered
about it, but I'm giving a talk about Scheme and I would like to have
as many instances of the use (or proposed use) of Scheme outside of
research laboratories as possible.  I'll be glad to summarize the
responses.

Thanks in advance.

--Jim Miller
(JMiller@crl.dec.com)
Newsgroups: comp.lang.scheme
From: nix@asd.sgi.com (Just a man with a mind like a scrambled egg)
Subject: Re: Neato Scheme programming problem
Organization: Erisian Liberation Front
	<1992Apr16.173557.21190@bronze.ucs.indiana.edu>
Date: Fri, 17 Apr 1992 02:20:43 GMT

harlan@copper.ucs.indiana.edu (Pete Harlan) writes:

   My solution uses side-effects, but only to avoid doing a lot more
   consing.  Since the input function is only allowed to do cars and
   cdrs, that's safe.

You can do it without side-effects: once you've created the cell that
tells you whether the function begins with car or cdr, you can create
a cell which tells you what it does next with (cons previous-input
previous-input):

(define (cxr-name cxr)
 (let ((magic-car (cons '() '()))
       (magic-cdr (cons '() '())))
   (set-car! magic-car magic-car)
   (set-cdr! magic-car magic-car)
   (set-car! magic-cdr magic-cdr)
   (set-cdr! magic-cdr magic-cdr)

   (letrec ((loop
	     (lambda (result-list test-input)
	       (let ((x (cxr test-input)))
		 (cond
		  ((eq? x magic-car)
		   (loop (cons 'a result-list) (cons test-input test-input)))
		  ((eq? x magic-cdr)
		   (loop (cons 'd result-list) (cons test-input test-input)))
		  (#t result-list))))))
     (loop '() (cons magic-car magic-cdr)))))


Nick Thompson		nix@sgi.com		...!uunet!sgi!nix

	Shortly after 5:00 on Monday, April 19th, 1943, Hofmann
	climbs onto his bicycle and heads for home.

	There is an unexpected detour.
From: bh@anarres.CS.Berkeley.EDU (Brian Harvey)
Newsgroups: comp.lang.scheme
Subject: Re: New York Times article
Date: 15 Apr 92 14:34:05 GMT
Article-I.D.: agate.shestINNomr
Organization: University of California at Berkeley
NNTP-Posting-Host: anarres.cs.berkeley.edu

70262.630@compuserve.COM (Iain Ferguson) writes:
>For three years I taught BASIC and Pascal at the high school level in the UK. 
>The problem was, the kids would be interested for several weeks, and then as a
>rule they would turn off.  I tried changing the textbook.  I tried projects 
>and group work.  Wrote my own stuff.  Even CAI.  You name it, I tried it.  But
>the result was always bored kids and a frustrated teacher.  It must be me, I 
>thought.
>Currently, I'm involved with teaching Scheme to a high school class in 
>Florida, and I'm only now beginning to understand what the problem was. In the
>Scheme class it took us about six weeks to learn about lists, define, cond, 
>lambda and recursion.  I won't pretend it was easy, but in my experience it 
>was certainly no more difficult than teaching BASIC or Pascal syntax.  And 
>then the kids started to write programs, and they've been writing them ever 
>since.  

Although I'm all in favor of teaching kids Lisp, I think it's a little too
simplified to say "Pascal -> bored, Lisp -> interested."

In my own high school teaching experience, in the dark ages before Scheme
was available, I taught a little bit of Lisp and a lot of Logo.  But what
most turned kids on was programming in C, despite the fact that C is the
most syntaxy language ever invented.  The reason was that we were a Unix
facility, with [C] source code, and so there was a lot of real work to be
done if you could program in C.  Kids put up with all the difficulties in
order to have access to the operating system interface.

There was a cost to this situation: only a small number of kids did get past
the hurdles and become really good C programmers.  (I think I turned out 40
or 50 over the course of three years after the Unix system was installed.)
The other kids took a semester course and that was enough for them.  It may
be that using a less syntaxy language like Scheme makes it possible for more
kids to get past the competence hurdle.

I think the crucial point in my high school teaching was that I spent most
of my time programming, not teaching.  Kids would watch what I was doing
and want to be doing that too.  The ambitious ones would jump in, and I'd
help them.  Pretty soon we got to where a new kid's first impression of the
computer center was that there were a dozen kids hard at work on interesting
and useful projects, and then it was self-perpetuating.

The only point is, it's possible to teach Lisp boringly, and it's possible
to teach other languages like C interestingly.  That doesn't mean the choice
of language is irrelevant -- I'd rather teach Lisp.  But for me at least it
has to be in a context in which there's a lot of real work (not exercises)
that the kids can do in Lisp.

Is anyone besides me an Iain interested in this discussion?  Or should we
move it over to comp.edu or something?
Newsgroups: comp.lang.scheme