From: jabarby@sun5.vlsi.waterloo.edu (J.A. Barby)
Subject: CMC's Working Group on Test Strategy needs your input
Summary: survey on testing needs and directions for Canadian universities
Keywords: CMC tester requirements
Organization: University of Waterloo
Distribution: can
Date: Tue, 7 Apr 1992 02:52:26 GMT
Expires: Fri, 15 May 1992 04:00:00 GMT

CMC's WGTS is gathering advice from people who test chips about how the
CMC should handle test equipment and related issues in the future.  If
you test chips or your grad students test chips, please considering
emailing me a completed survey.
Thank you,
Jim Barby

======================================================================

 Questions Related to Test Equipment Use/Deployment

The CMC has asked several people to participate in forming a policy for
the future acquisition, use, and deployment of testing equipment.
Since this will affect all of Canadian academic microelectronic
researchers, I would appreciate it if you could please discuss this
with your colleagues (both EE and CS if appropriate), and get back to
me by email, <jabarby@vlsi.UWaterloo.ca> with your collective wisdom.
The following questions should be addressed, but add additional
questions (and answers) if you think they are important.

1. It is perceived that expensive test equipment should be shared
   amongst universities.  What arrangements would be appropriate?  
   (a) should there be travel money for the people who are not near
       the tester?
   (b) should the host university be given some technical support to
       handle the extra work involved in hosting their colleagues?
   (c) how do you choose the host university?

2. Should a mixture of low-cost and expensive testers be provided?  If
   so, what are the minimum requirements for low-cost digital, and
   low-cost analogue testers?  How many "expensive" testers should be
   deployed?  What are the criteria for allocating this resource?
   Presumably, everyone who is testing chips might have a low-cost
   tester on-site.

3. Do you think that you could do your testing by network?  I.e. have
   someone put your chip into the device-under-test socket and talk to
   the tester from a remote site.  This can already be done in a
   limited way with the IMS.  Would you need a scope hooked up to your
   chip?  Would you need lots of support from the person who is at the
   other end (e.g. would they have to understand the chip?).  How
   often would someone have to attach probes to a chip?

4. How about a cost sharing arrangement?  Could universities find the
   money to make up the difference if CMC provided a percentage of the
   purchase price?

5. What testing arrangements should be made for high performance
   technologies like BiCMOS, .5um CMOS, GaAs?  Networking?  Travel to
   location X?  What tester performance specs would be needed?
   What speed or vector rate is most suitable?
	200MHz, 400MHZ, 600MHz or higher?
   What number of I/O channel is sufficient?
	64, 80, 128, 256 or higher?
   What vector depth is desirable?
	256K, 512K, 1024K or higher?

6. Are there any issues related to testing techniques?  E.g.
   functional testing vs BIST.  Functional testing might require a more
   "hands on" approach (e.g. using a scope, or measuring power
   consumption, etc.).

7. What about exotic attachments to a tester?  

8. Should analog testing be treated the same way as digital?
	centralized?

9. Is mixed signal capability essential?  Can mixed signal testing be
   performed easily through networking or by a trained operator given
   detailed instructions?

10. Should CMC buy or rent the testing setup for high performance
    technologies or just purchase service from some firms?

======================================================================
-- 
 Jim Barby  <jabarby@vlsi.UWaterloo.ca>
 VLSI Group, University of Waterloo, Waterloo, Ontario, Canada, N2L 3G1
 519-885-1211x3995, FAX 519-746-5195
Newsgroups: can.vlsi