From: mathew <mathew@mantis.co.uk>
Newsgroups: alt.games.lynx
Subject: Re: Whaddabout the so-called Jaguar? (was Re
Date: Thu, 17 Dec 92 14:34:49 GMT
Distribution: world
Organization: Mantis Consultants, Cambridge. UK.

stripes@eng.umd.edu (Josh Osborne) writes:
> In article <De7RVB2w165w@mantis.co.uk> mathew@mantis.co.uk (mathew) writes:
> >For instance, some RISC chips have heavy pipelining, so that when they hit a
> >jump they've already decoded the next couple of instructions.  Rather than
> >waste all that effort, they execute 'em anyway before jumping.
> 
> Which isn't that confusing after the 2nd day of writing RISC code.

It isn't confusing, but it's hard to write good code for.

> >Some RISC chips don't have stacks; you have to use registers to pass all you
> >arguments.  Because this could lead you to run out of registers quite
> >rapidly, some RISCs have 128 or more of the little buggers.  Sometimes
> >they're arranged in banks, so that a single instruction is equivalent to
> >swapping out all the registers and another instruction swaps them back in
> >again.
> 
> Yes, and no.  The SPARC (banks of registers), and the AMD29k's (192 user
> visiable GP 32 bit registers), and others are like this, mostly.  All RISCs
> can do stacks.

Since you can implement a stack using registers and indirection,
obviously.  But some do not have built in stack instructions.

> >Some RISC chips have unlikely addressing modes.  Since you've got
> >instructions of fixed width, something simple like "move 1 into register D1"
> >leaves lots of bits unneeded.  So they implement operations like "take
> >registers A1 and A2, add together, add the specified offset, indirect throug
> >that location, get the value stored there, exclusive-or with the value in th
> >memory location pointed to by A3, and increment A3".
> 
> No they don't.  This is the one thing that RISC CPU's do not do.

Tell that to ARM.

> >Even CISC chips have odd little tricks.  For instance, on the 68000 the
> >quickest way to multiply a register by 4 is to add the value to itself twice
> >because there's no hardware barrel shifter.  RISC chips have similar "tricks
> >because of the stuff that's left out in order to ensure that all instruction
> >take 1 cycle.
> 
> (a) not all instructions take one cycle, for example FMUL on the i860
> takes 3 cycles to multiply 2 FP numbers.

If I were being as dogmatic as you, I would say "RISC chips do not
have multi-cycle instructions".  Since I'm not, I'll merely remark
that having all or almost all instructions take the same number of
cycles is one of the defining criteria of RISC design.

> >These sorts of features mean that it can be very hard to write good RISC
> >assembler by hand.  In fact, today's compilers can produce faster, more
> >compact RISC code than all but the finest assembler programmers.
> 
> Bull.  I am a good assembler programmer, but not one of the finest.  I can
> beat AMD's C compiler, Gcc on the AMD29k, Sun's stock cc on the SPARC, IBM
> and metaware on the ROMP, the older (never used the newer) Intel i860 compile
> (which beat out IBM's ROMP compiler in the "who can slow down their own box
> the most" awords...)

I was talking about leading edge compilers.  Sun cc indeed!

> Alpha reference, or an HPPA one (yet).  Anyone with some time, and some (not
> alot) can beat a C compiler, even on a RISC.  I'll admit it is harder, but I
> think it has more to do with the quality of the compilers then the chip.

And this is a major point.  Productivity of assembler programmers is
already a tenth of that of high-level language programmers, even
before you add extra complexity caused by the hardware design of RISC
chips.


mathew
-- 
Lung cancer and arteriosclerosis.
For people who like to smoke.

Newsgroups: alt.games.lynx