HDTenEightyP/NetNews huggingface dataset:
From: trevore@vast.unsw.edu.au (Trevor Elbourne (Supr. Hell) BE)
Subject: plotting a viewdraw schematic
Organization: University of New South Wales
X-Newsreader: Tin 1.1 PL4
Date: Fri, 18 Dec 1992 05:46:40 GMT

I haven't been able to plot any of the schematics i have created in
viewdraw. I keep receiving a "Plotter cant open pcf" message. The
manual says to check the permissions on the sysplt directory but this
doesn't make much sense on a pc.

Any help would be greatly appreciated.

Thanks,
Trevor.

--
"Let me be the first to offer you my sincerest contrafibularities."
	- E. Blackadder

Trevor Elbourne 			VLSI and Systems Tecnology (VaST) lab
trevore@vast.unsw.edu.au                Dept of Computer Science & Engineering
trevore@cs.unsw.oz.au                   University of New South Wales
Newsgroups: comp.lsi.cad
From: ronald@opal.cs.tu-berlin.de (Ronald Hindmarsh)
Subject: NT-Spice under Win3.1 with Win32s/October release?
Keywords: Spice Win32s NT
Organization: Techn. University of Berlin, Germany
Date: Mon, 14 Dec 1992 12:47:03 GMT

Can I run the spice3 port for Windows NT on Windows 3.1 with #
the Win32s extension, which comes with the october release of
Windows NT?

----------------------------------------------------------------------
 Ronald Hindmarsh                      e-mail: ronald@cs.tu-berlin.de
 Institut fuer Technische Informatik
 TU Berlin FR 3-9
 Franklinstr. 29                            Phone: (+49) 30 314-73432
 W-1000 Berlin 10                             Fax: (+49) 30 314-21103
----------------------------------------------------------------------
From: karplus@cse.ucsc.edu (Kevin Karplus)
Newsgroups: comp.lsi.cad
Subject: Re: how to get COSMOS from CMU
Date: 12 Dec 1992 03:52:40 GMT
Organization: University of California, Santa Cruz
Distribution: inet
Reply-To: karplus@ce.ucsc.edu (Kevin Karplus)
NNTP-Posting-Host: ararat.ucsc.edu

I can't help pointing out that there are several porgams out there
besides espresso and sis (though both of those are indeed very good).

I'd like to put in a plug for my program (ITEM) which is available by
anonymous FTP from ftp.cse.ucsc.edu.  The released version of ITEM is
from last January, but we hope to have a new release "real soon now".
We've got a lot of new stuff working, but we haven't gotten around to
making all the changes needed to run with the new g++ libraries.

Incidentally, the FAQ file for this newsgroup answers the question
asked in gory detail---including almost every publically accessible
logic minimizer. 

Kevin Karplus
-- 
Kevin Karplus		karplus@ce.ucsc.edu

Due to budgetary constraints the light at the end of the tunnel is
being turned off.
Newsgroups: comp.lsi.cad,comp.arch
From: jsnow@moons.sim.es.com (John Snow)
Subject: Re: Why no tri-state outputs in FPGA cells?
Organization: Evans & Sutherland Computer Corp.
Date: Wed, 16 Dec 1992 19:13:47 GMT

pichet@coos.dartmouth.edu (Pichet Chintrakulchai) writes:

>Hello,

>I've been working on a project designing a processor with FPGA's.  One severe
>limitation I found is that their cells do not have tri-state outputs and thus
>forcing me to use MUXes on buses consuming a lot of the resources.

>Does anybody have any idea why they didn't make these cell outputs tri-state?

>Thanks.
>Pichet Chintrakulchai		(pichet@dartmouth.edu)

Xilinx FPGAs do have tri-state buffers that can be used to create buses or to do
wired-OR type logic.

--John
--
-----------------------------------------------------------------------------
John F. Snow                                         jsnow@moons.sim.es.com
Evans & Sutherland Computer Corp.    
Salt Lake City, Utah                                 (801) 582-5847
Newsgroups: comp.lsi.cad
From: tgzhang@MtHolyoke.edu (Tian Ge Zhang)
Subject: ftp site for Macrocell in Magic
Organization: Mount Holyoke College
X-Newsreader: Tin 1.1 PL5
Date: Mon, 14 Dec 1992 15:55:55 GMT




Hello, I am an undergr. student at Mount Holyoke College. I am working on
the Magic cad tool for my independent project which is to design a digital
circuit for playing Tit tak toe game, the circuit layout I came up with
uses about 72 gates. 

I wonder if anybody knows any ftp sites that provide scmos cells ready to
use, especially the Macrocells functions such as 8-3 line Encoders, 4- 16
line decoders.  My intension is to speed up the design by using the made
cells instead of drawing them myself by connecting basic gates(NAND, NOR),
that way it can save much time. Anyone have a clue about this? Thanks to
aue company which provides basic functions, but I would be happier if
there are well-made macrocells.  Thanks in advance.

--Tian  tgzhang@mhc.bitnet

Newsgroups: comp.lsi.cad
From: dataram@tigger.jvnc.net (Dataram Corp. PO Box 7528)
Subject: Fault Grading
Originator: dataram@tigger.jvnc.net
Organization: JvNCnet, Princeton University, NJ
Date: Fri, 11 Dec 1992 20:35:54 GMT

Does anyone know of a way to fault grade my Viewlogic based gate array
design with Cadences Verifault tool?
      Regards,
            Chuck

-- 
**********************************************************
* Chuck Staatse       Dataram Corp.  609-799-0071 x 330  *
*  chuck@dataram.jvnc.net |  chuck@dataram.com           *
**********************************************************
Newsgroups: comp.lsi.cad
From: sie@irisa.fr (Oumarou Sie)
Subject: CIF to EDIF
Keywords: CIF EDIF translator
Organization: Irisa, Rennes(FR)
Date: Tue, 15 Dec 92 16:31:31 GMT

Hello,

I am looking for a translator from CIF to EDIF and would be grateful if someone
has or knows where I can get one.

Please send me an email.

---------
Oumarou SIE
sie@irisa.fr

Xref: sparky comp.lsi.cad:1218 comp.os.ms-windows.programmer.win32:2466
From: robert@koko.csustan.edu (Robert Zeff)
Newsgroups: comp.lsi.cad,comp.os.ms-windows.programmer.win32
Subject: NT-Spice update available
Date: 15 Dec 92 20:13:04 GMT
Organization: CSU, Stanislaus

I have uploaded my latest version on Spice for Windows NT to:
fpt.cica.indiana.edu.  It's in the /pup/pc/win3/uploads directory.
(It'l be moved to the NT directory sometime later.
I've added multiple plot windows, command history via a Combo Box and
a few other tools for faster database regen and plotting.  I've reduced
the frequency of shareware nagging.

A few answers to FAQ's:
1.  I will not distribute Berkeley source code outside the U.S.
2.  Spice32 / Nutmeg32 will not run on a win3.1 system yet.  The
    Win32s dll seems to have a bug.  I will post a version that
    runs under the Win3.1 / Win32s as soon as I have it ready.

-robert
-- 
Robert Zeff                         (209) 577-4268 work, 577-8548 FAX
Xref: sparky comp.lsi.cad:1212 comp.lsi:743
From: eht@northstar.dartmouth.edu (Edward H. Truex)
Newsgroups: comp.lsi.cad,comp.arch
Subject: Re: Why no tri-state outputs in FPGA cells?
Date: 15 Dec 92 19:38:37 GMT
Organization: Dartmouth College, Hanover, NH

In article <1992Dec15.010020.9274@super.org> cfreese@super.org (Craig F. Reese) writes:
>
>You don't say which FPGA you are using but the Xilinx 4000 series does
>contain tristate buffers for just the kind of purpose you describe.
>The buffers are not on each CLB but adjacent.  There are some
>limitations as to where the buffers can connect up.  I have found
>designs where the functionallity did _not_ work for a given device (due
>to the size of the FPGA, size of my design, and the tristate buffer/bus
>resources) but a larger chip probably would have.  In many other
>designs I have not used any tristate logic (so I'm glad the CLBs aren't
>all tristate by default).


I am working with Pichet (the originator of this thread) on a very 
similar design, and I think his question can be rephrased.  What we
are really trying to figure out is 

Is there an electrical reason why the short pieces of interconnect 
(those that are connected through Xilinx's 'PIP's) cannot be tristated?

The long lines obviuosly don't present any electrical problems as they 
are simply edge to edge pieces of wire.  Are the pass transistors in 
the interconnect points the problem? 

Here's the motivation for our inquiries...

With the current Xilinx parts (I am using XC4010's) the number of
busses that can be implemented is severely limited by the number
of long lines.  In a design that requires many wide busses (I am
currently working on a 32 bit microprocessor) the number of long
lines available is not enough to implement a true bus structure.
As a result, I am forced to use a large number of fairly wide
multiplexers, and a correspondingly large number of CLBs and routing 
resources.  The ability to tristate the output of each CLB while
attaching it to a piece of "normal" routing would eliminate (or
reduce) bus constraints on chip, in addition to (possibly) freeing 
up some of the CLBs that were previously used for bus redirection
to be used for "useful" logic.

Thanks for any insights,
Tad Truex
From: edward@minster.york.ac.uk
Newsgroups: comp.lsi.cad
Subject: LCA design entry using viewdraw
Date: 18 Dec 92 23:11:48 GMT
Organization: Department of Computer Science, University of York, England

Hi Folks!

	When using the long lines in the xilinx 3090 to implement a wide 
wired-AND function, must we explicitly attach a pull-up to the end of the 
long line or is this implicitly assumed when you attach a long line 
attribute to the net.   The pull-up primitive that is available in most
CAD support for the LCA's seem to refer to the IOBs pull-ups.  I assume
the pull-ups at the end of long lines are not IOB pull-ups.  

	I am confused.  Any help appreciated.  Thanks.

- edward
------------------------------------------------------
Edward Walker
Dept. of Computer Science
University of York
York, YO1 5DD
U.K.

Internet: edward@minster.york.ac.uk
Xref: sparky comp.lsi.cad:1236 misc.jobs.contract:4583 comp.cad.cadence:552 ne.jobs:1391
From: botticel@baggins.crd.ge.com (David J. Botticello Jr.)
Newsgroups: comp.lsi.cad,misc.jobs.contract,comp.cad.cadence,ne.jobs,misc.jobs.resume
Subject: IC Layout Designer/Dracula Consultant for hire
Keywords: Dracula IC PCB layout Verification
Date: 20 Dec 92 13:57:27 GMT
Reply-To: botticel@baggins.crd.ge.com (David J. Botticello Jr.)
Distribution: usa
Organization: GE Corporate R&D Center
Originator: botticel@baggins

I am an independant consultant specializing in Full Custom IC Layout Design
and writing verification rulesets using Dracula III(tm) from Cadence Design 
Systems. I currently have schedule space for a couple more contracts. I have 
7 years experience in custom IC design in both straight CMOS AVLSI and 
specialized BiCMOS processes. I also have 5 years experience in using Dracula 
to accomplish verification of layout of Printed Circuit Boards as well as MCMs.
I have also utilized Dracula for other CAD test issues relating to automated 
PCB testing prior to componant placement.

I am an off-site consultant. My rates are reasonable at $50/hour. (Consider
that some Vendors get up to $1500 a day!) I will quote jobs based upon
the amount and complexity of the layout required. (Obviously Standard
Cell design will be somewhat easier than Full Custom with high transitor per
square mil ratios). In my years as a Layout Designer I find that the 
average is about 3 leaf cells (15-25 devices per cell Full Custom) per
man-week), but I will give more detailed quotes upon receipt of schematics
and design rules. 

In my experience runsets take anywhere from 5 workdays to 6 workweeks. I will 
provide estimates given parameters of your process and the type of Design
Rules you need to have checked. My rates for Dracula Programming do not 
include toll charges for connection to your computers. (An account on your 
computers with access to Dracula is required) These will be billed monthly.

All layout work will be completed on a Calma Design Station and output will
be in Calma Stream Format on 1/2" Reel tape. Possible modem transfers can
be discussed.

I am a US citizen and am willing to sign non-disclosure agreements. All code
generated becomes the property of the hiring firm, though I reserve the right
to use similar techniques developed in conjunction with any contract on any
future contract.


Dave Botticello - phone(voice) 518-399-3615 Home 518-393-8671
E-mail - botticel@zeppo.crd.ge.com  or uunet!crd.ge!zeppo!botticel or   
         botticello@crd.ge.com      or botticel%zeppo@crd.ge.UUCP
	 70343,24@compuserve.com    
 


-- 
Dave Botticello  - GE CRD  - phone(voice) 518-387-6065 
E-mail - botticello@crd.ge.com             botticel%zeppo@crd.ge.UUCP    
       - uunet!crd.ge!zeppo!botticel       70343.24@compuserve.com
land   - P.O. Box 8 KWC-1604 Schenectady, N.Y. 12301 
Xref: sparky comp.lsi.cad:1210 comp.arch:11640
From: pichet@coos.dartmouth.edu (Pichet Chintrakulchai)
Newsgroups: comp.lsi.cad,comp.arch
Subject: Why no tri-state outputs in FPGA cells?
Date: 14 Dec 92 22:15:41 GMT
Organization: Dartmouth College, Hanover, NH
Originator: pichet@coos.dartmouth.edu

Hello,

I've been working on a project designing a processor with FPGA's.  One severe
limitation I found is that their cells do not have tri-state outputs and thus
forcing me to use MUXes on buses consuming a lot of the resources.

Does anybody have any idea why they didn't make these cell outputs tri-state?

Thanks.
Pichet Chintrakulchai		(pichet@dartmouth.edu)
Newsgroups: comp.lsi.cad
From: yak@bnr.ca (Yatish Kumar)
Subject: synopsys schematic into cadence
Originator: yak@bcrks222
Keywords: synopsys edif schematic cadence
Reply-To: yak@bnr.ca (Yatish Kumar)
Organization: Bell-Northern-Research (BNR)
Date: Tue, 15 Dec 1992 15:04:29 GMT



hi,
  I am trying to read in an edif schematic from
synopsys into cadence edge.  Unfortunately the only
route seems to be a set of "dci" routines that
cadence half provides.

  These routines cannot handle:

	a.  Busses as output by synopsys.
	b.  Translation of layers between synopsys
	    and cadence.  As a result symbols often
	    come out invisible.

  Has anyone got a successful set of scripts that do
  the same thing ?

  Any help would be appreciated.

Thanks.
Yatish Kumar
(613) 765-2753
yak@bnr.ca
From: philip@xilinx.com (Philip Freidin)
Subject: Re: Why no tri-state outputs in FPGA cells?
Organization: Xilinx Inc.
Date: Wed, 16 Dec 1992 18:43:40 GMT

In article <1992Dec14.221541.25270@dartvax.dartmouth.edu> pichet@coos.dartmouth.edu (Pichet Chintrakulchai) writes:
>Hello,
>
>I've been working on a project designing a processor with FPGA's.  One severe
>limitation I found is that their cells do not have tri-state outputs and thus
>forcing me to use MUXes on buses consuming a lot of the resources.
>
>Does anybody have any idea why they didn't make these cell outputs tri-state?
>
>Thanks.
>Pichet Chintrakulchai		(pichet@dartmouth.edu)


-- 
Philip Freidin: Product Planning Manager, Xilinx, INC
(rest of clever .sig still under construction....
		coming to a terminal near you, Real Soon Now (tm))

Newsgroups: comp.lsi.cad,comp.cad.cadence
From: dataram@tigger.jvnc.net (Dataram Corp. PO Box 7528)
Subject: Using SCAN
Originator: dataram@tigger.jvnc.net
Keywords: Scan 
Organization: JvNCnet, Princeton University, NJ
Distribution: usa
Date: Sun, 20 Dec 1992 18:45:30 GMT

I will be designing a 90K- 100K gate array but have never used SCAN 
before. Could someone point me to some literature. If you have a little
 time and have been through this before, I would appreaciate talking to
you for a few minutes.
      Regards,
            Chuck

-- 
**********************************************************
* Chuck Staatse       Dataram Corp.  609-799-0071 x 330  *
*  chuck@dataram.jvnc.net |  chuck@dataram.com           *
**********************************************************
Newsgroups: comp.lsi.cad
From: "Bob Montante" <bobmon@sandshark.cs.indiana.edu>
Subject: Magic & CIF layers?
Summary: Want pointers to info
Organization: dyskaryotic
Distribution: na
Date: Wed, 16 Dec 1992 10:41:25 -0500

Hello all,

I'm using the Magic drafting program (on an X terminal) to lay out a
VLSI circuit for fabrication, and when I convert it to CIF format I get
some errors involving the CSN and CSP layers.  I can't find any doco.
about the layers; the man page mentions a "technology manual" but
I can't find any such around here.

Can someone please give me some pointers to information on the layers
used by different technologies, and their rules for use?  (My problem is
that the CSN and CSP layers "disagree between parent and child cell",
whatever that means.)

thanks in advance,
-bob,mon.
Newsgroups: comp.lsi.cad
From: jensen@neocad.com (Jeff Jensen)
Subject: Re: Why no tri-state outputs in FPGA cells?
Organization: NeoCAD, Inc.
Date: Tue, 15 Dec 1992 16:55:28 GMT

One possible reason is that the implementation of tri-statable outputs
usually includes an additional series pass transistor in the output path
of the cell. This additional resistance causes additional delay. Given that
speed limitations are a critical problem for FPGAs, you don't want to build
in a fixed additional delay.

Jeff Jensen
Neocad

-- 
  Jeff Jensen   Neocad Inc.   2585 Central Ave.   Boulder, CO 80301
  (303) 442-9121 X116  Internet: jensen@neocad.com  UUCP: neocad!jensen
----------------------------------------------------------------------
"... watch from high atop Tokyo Tower as the twisted world you created
From: mayo@pa.dec.com (Bob Mayo)
Newsgroups: comp.lsi.cad
Subject: Re: Magic transistor netlists
Date: 12 Dec 1992 01:19:31 GMT
Organization: DEC Western Research Lab
Distribution: inet
NNTP-Posting-Host: mayo.pa.dec.com
Keywords: magic,spice,netlists

In article <1992Dec11.120248.425@gmd.de> huebner@eissn5.gmd.de writes:
>Hi netters,
>Does anybody know what the next line produced by magic means???
>Ok, I know it's a line of a transistor netlist. But where are
>the source gate drain and bulk nodes?
>
>p bsp.ch.2_0/I10 bsp.row_2_0/aoi21s_0/6_4_86# bsp.row_2_0/fts_0/Vdd 2 29 51 60

See the file ~cad/src/magic/doc/man/sim.5 for a specification of the .sim
file format.

--Bob
Newsgroups: comp.lsi.cad,comp.arch
From: cfreese@super.org (Craig F. Reese)
Subject: Re: Why no tri-state outputs in FPGA cells?
Organization: Supercomputing Research Center (Bowie, MD)
Date: Tue, 15 Dec 1992 01:00:20 GMT

In article <1992Dec14.221541.25270@dartvax.dartmouth.edu> pichet@coos.dartmouth.edu (Pichet Chintrakulchai) writes:
>
>I've been working on a project designing a processor with FPGA's.  One severe
>limitation I found is that their cells do not have tri-state outputs and thus
>forcing me to use MUXes on buses consuming a lot of the resources.
>
>Does anybody have any idea why they didn't make these cell outputs tri-state?
>
>Thanks.
>Pichet Chintrakulchai		(pichet@dartmouth.edu)


You don't say which FPGA you are using but the Xilinx 4000 series does
contain tristate buffers for just the kind of purpose you describe.
The buffers are not on each CLB but adjacent.  There are some
limitations as to where the buffers can connect up.  I have found
designs where the functionallity did _not_ work for a given device (due
to the size of the FPGA, size of my design, and the tristate buffer/bus
resources) but a larger chip probably would have.  In many other
designs I have not used any tristate logic (so I'm glad the CLBs aren't
all tristate by default).

Xilinx Technical Support; 1-800-255-7778.  (I'm not sure if they'll
talk to you on this number or whether this is just for people
with support contracts but it would be a good place to start.)

Craig

P.S. I have no connection with Xilinx other than being a user of
there products.  I have both good and bad things to say about their
stuff.

*** The opinions expressed are my own and do not necessarily reflect 
*** those of any other land dwelling mammals....

"The problem ain't what we don't know; it's what we know that just ain't so
Either we take familiar things so much for granted that we never think about 
how they originated, or we "know" too much about them to investigate closely."
-----------------
Craig F. Reese                           Email: cfreese@super.org
Institute for Defense Analyses/
Supercomputing Research Center 
17100 Science Dr.
Bowie, MD  20715-4300
From: cpwen@asterix.CS.Berkeley.EDU (Chih-Po Wen)
Newsgroups: comp.lsi.cad
Subject: Looking for benchmark suite for circuit simulators
Date: 18 Dec 1992 07:02:47 GMT
Organization: University of California, Berkeley
Distribution: usa
NNTP-Posting-Host: asterix.cs.berkeley.edu
Keywords: Parallel Timing Simulation

Hi,

I am working on a parallel timing simulator on the
CM5 multiprocessor. A prototype is working now, giving
speedups up to over 50 for some MOS circuits on a 64-procesor CM5.

While the speedup numbers are quite nice-looking, I
have no idea what they mean to the community of users of
timing simulators -- the speedup is certainly program
and machine dependent.

Is there a standard benchmark suite around that 
can help me to validate my work (in terms of 
absolute running time)? The only thing that
comes close to that is the "ISCAS benchmark suite".
However, I was not able to locate works that use
them to compare the performance of circuit simulators.
Is there such a thing in CAD research as the fastest
program or machine for simulating a set of benchmark
circuits?

Thanks.

Chih-Po

Chih-Po Wen
graduate student
Computer Science Division
U.C. Berkeley
-- 
Chih-Po Wen                                                         
Computer Science Division, University of California at Berkeley
cwen@genesis.Berkeley.EDU
Xref: sparky comp.lsi.cad:1211 comp.lsi:742
From: richardw@hub.parallan.com (Richard Walter)
Newsgroups: comp.lsi,comp.arch
Subject: Re: Intel's 100-Million Transistor Device
Date: Wed, 09 Dec 92 17:39:06 PST
Organization: Parallan Computer, Mountain View CA

pngai@adobe.com (Phil Ngai) writes:

> In article <DOCONNOR.92Dec8082938@potato.sedona.intel.com> doconnor@sedona.in
> >Second, don't forget about flash. Intel is building way-dense
> >flash memories, and claims flash will be denser than DRAM
> >as device geometries shrink further.
> 
> Could you please tell me where I can buy Intel FLASH devices?
> Or should I ask _when_ I can buy them?
> 
> -- 
> Remember Melvin Ancheta.

Where to buy Intel FLASH devices?  Why not call INTEL ???????????
They have been in full production and available for at least a year, if
not longer.  (I'll be showing my age here, but FLASH ROMs are the ONLY
ROM chips which I have ever used, and I graduated in '90).  You should
have absolutely no problems getting F010 (128Kx8) or F020 (256Kx8) chips
in either 32-DIP or 32-PLCC.  The newer F001 (1Mx8) chips should be
into general availability by now, but they only come in 40TSOP packages,
so they are not easy to work with (ie: soldered on board, not socketed),
so most of them are used in PCMCIA memory type cards.

I can name at least 4 major PC makers who are shipping systems with
FLASH BIOS ROMs.  They are great for upgrading, the users can just dial
up a BBS and download a new BIOS.  Most companies don't want to
advertise it much because of the fear of some complete bone-headed loser
idiot writing a virus which wipes out ROMs.  That would be a major
problem.  (Intel lore: Early 386SL specs had a pin on the processor
called FLASH_DISASTER which meant that you were in the middle of re-
flashing your ROMs when something happened.  If the pin was active on
a boot, then the SL was supposed to fetch it's code from the parallel
port and not from the ROM.  That way you could rescue a dead machine
without needing to pop the chip.  That pin, however, was dropped from
later versions and never made it into the chips.)

Also, Intel owns the FLASH market (yea, USA!), but they are not the only
people who have FLASH chips.  AMD and Atmel make them also.  (In fact,
AMD and Atmel make 5V only flash;  The Intel ones still require 12V
to program).  Also, AT&T makes serial FLASH ROMs which are used in the
SunDisk(tm) solid state drive system.

Now, to the point of FLASH overtaking DRAM in size with shrinking geometry,
although I've heard this argument, I admit that I don't understand it.
Can't DRAM take advantage of shrinking geometry also?  So if a FLASH cell
can be made smaller than a DRAM cell, then why aren't FLASH cells in
today's technology smaller than DRAMS in today's technology, and so would
have higher density?  Anyone??

Sincerely,
Richard Walter
richardw@parallan.com
Newsgroups: comp.lsi,comp.lsi.cad,comp.lsi.testing,biz.comp.hardware