From: root@rkamiga.UUCP (Rick Kelly)
Newsgroups: comp.sys.amiga.misc
Subject: Re:  Everything killer on the way!!!
Distribution: world
Date: 7 Apr 92 13:26:45 EST
Organization: Rick's Amiga

In article <1992Apr4.222543.7610@athena.mit.edu> kdmiller@m4-035-16.MIT.EDU (Kenneth D Miller) writes:
>Okay, for all you people who are wondering what's going on, this machine was
>described in an issue of BYTE magazine.  The article describes an effort by
>IBM, Apple, and Intel (the Evil Triumvirate... ;) to create a RISC-based
>personal computer called the
>
>		POWER-PC
>
>This is from BYTE, remember, so unless BYTE is up to something stupid (NO it
>was NOT an April issue!  At least I don't think so).
>
>The CPU _IS_ a variant upon the one in IBM RS/6000's.  The machine _WILL_
>emulate Motorola 680x0 and Intel 80x86 processors, albeit not as fast as the
>higher-end models (it's only 4x faster than the '040, supposedly).

Motorola is under contract to manufacture the processor for the POWER PC.
They will also make other RS/6000 chip sets as a second source for IBM.

The POWER PC, at least in the first machines, will probably be AIX with the
Mac GUI.  It will have the ability to run Mac applications.

>This is all I can remember now.  If you want to know more, go find back-issues
>of BYTE from '92, maybe early '91, but I remember reading it only a month or
>two ago, and it was a new issue.  It's about RISC being the "architecture of
>the future" and so forth...
>
>
>On a related subject, here's my idea of how Motorola could create a really cool
>processor that would probably be faster and simpler, without being that much
>nastier to program on (hell, you could run in and CONVERT binaries!)
>
>Okay, everyone who's ever coded in assembly knows how a 680x0 CPU works, right?
>
>	<operator> <from> <to>
>
>or something like that, where <from> and <to> can be one of 13+ addressing 
>modes.  Fine.  Well, being in the know (right, well...), the 680x0 CPU's have
>so much microcode it's not even funny.  SO... here's what I think should happen
>
>1. make all operators (exept MOVE) ONLY work on Registers
>2. make several forms of MOVE.  They could be divided into two classes:
>   move TO a register, and move FROM a register.  The non-register source/dest
>   would be the usual 680x0 addressing modes.
>3. make about 256 registers available, as a "page" of special on-chip RAM (1K)
>   this way, there would be ways to access the "registers" in clever and useful
>   ways (but simple to implement in hardware)
>4. divide those huge MULx and DIVx instructions into one-bit increments, each
>   of which is ridiculously fast, so you can have just as many bits in your
>   multiplies and divides as you want (only want to multiply two 8-bit numbers
>   together?  fine...just use 8 steps).  This isn't too bogus.  The MIPS-X
>   architecture(s?) use it.
>
>So, what does everybody think?  It would reduce the hideous number of possible
>instructions on the high-end Motorola chips to a reasonable few.  Oh, sure,
>it would take more instructions to do anything, but the instructions could be
>WAY faster and possibly even shorter.  Ever notice how big a single instruction
>can get?  ~16 bits for the instruction itself, which includes addressing mode
>and stuff like that, up to 32 bits for direct Longword data...pretty ugly, eh?
>The way I have in mind, the instruction would be a byte, and the "parameters"
>such as which register to use would also be bytes.  Not too shabby, maybe we
>could hope for a 50% reduction in instruction size?
>
>Oh well, enough rambling for now...

The Motorola 88000 series chips seem to be fairly nice.

--
Rick Kelly		Rick's Amiga		Framingham, Mass.

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Newsgroups: comp.sys.amiga.misc