HDTenEightyP/NetNews huggingface dataset:
From: wkt@cserve.cs.adfa.oz.au (Warren Toomey)
Subject: Re: SPICE model ftp site
Organization: Australian Defence Force Academy
Date: Sun, 3 Jan 1993 23:44:03 GMT

In article <1992Dec30.034810.23230@nuscc.nus.sg>, eleleetk@nuscc.nus.sg (Teng-Kiat Lee) writes:
|> 
|> Hello, there was a posting recently about ftp-able spice
|> models from a site minnie.cs.adfa.oz.au. Has anyone out
|> there been successful in accessing the machine at all?
|> 

My apologies! Minnie.cs.adfa.oz.au went down while I was away on holidays, and
didn't reboot itself ( it _is_ a PC after all ). It's now back up and
available for anon ftp again.

Cheers all,

	Warren Toomey	wkt@csadfa.cs.adfa.oz.au        
Newsgroups: comp.lsi,sci.electronics
From: jmacphai@cue.bc.ca (James MacPhail)
Subject: Lattice & GAL questions...
Organization: Softwords Research International Ltd., Victoria, B.C., Canada
Date: Mon, 28 Dec 92 02:37:39 GMT

Is there a Lattice Semiconductor engineer or e-mail address
here-abouts? I'm looking for the answers to the following:

What's the difference between a GAL16V8 and a GAL16V8A?

What are the product term disable fuses useful for?
(Other than the obvious... why are these in the architecture?
do they alter the speed/power dissipation?)

Why is the architecture configuration still accessible after
programming the security fuse? It seems to me that this saves
a few hours for the buggers off-shore (or on-shore!) that are going
to reverse engineer my product!

And finally... why is the 16V8 so much cheaper than the 22V10? 
A factor of two seems reasonable to me, but 4-6x seems excessive.
I've been putting in two 16V8s instead of a 22V10 in most cases,
and am happy to continue to do so, but it seems to me that there
would be more profit for Lattice if the 22V10 came down some.

Thanks for your time...

James MacPhail  jmacphai@cue.bc.ca  james@mirg2.phy.queensu.ca
Newsgroups: comp.lsi.testing
From: danr@ais.org (Daniel Romanchik)
Subject: Re: Groups for ESD, SPC ?
Organization: UMCC
Date: Thu, 24 Dec 1992 15:15:37 GMT

>In <88910001@teecs.UUCP> smithr@teecs.UUCP (Robert Smith) writes:

>Sorry if I'm in the wrong group but does anyone know if there is a group
>on the net discussing electro static discharge, SPC related to
>electronic production or reliability in general? I'd appreciate any
>suggestions on the right groups. Thanks.

>Bob.

I think you've got the right group.  

I don't think this is what you're asking, but there are several
professional groups that concern themselves with ESD. One is the
EOS/ESD Association.  Their address is 200 Liberty Plaza, Rome, NY
13440, telephone (315) 339-6937.

The EMC Society of the IEEE discusses technical aspects of the ESD
event, while the Reliability Society discusses all reliability issues.
Another group that concerns itself with electronics reliability is the
Electronics Division of the American Society of Quality Control. You
can reach the IEEE at 345 E  47th St., NY, NY 10017, telephone (212)
705-7900.  The ASQC is at 611 E. Wisconsin Ave., Milwaukee, WI 53202,
telephone (215) 299-5400.

Have fun, Dan
=====================================================================
        Dan Romanchik              |        danr@umcc.ais.org
       Technical Editor            |         (313) 930-6564
   Test and Measurement World      |     MCI Mail: tmwromanchik
=====================================================================
   "You can't test in quality" --  ancient Test Engineering maxim
=====================================================================
P.S.  If any of you out there want a copy of our magazine, please send
me your US Mail address, and I'll have our office send a sample copy.
From: aran@hard18.acri.fr (Aran Aidan)
Newsgroups: comp.lsi.testing
Subject: Termination resistors JTAG test
Keywords: JTAG, termination
Date: 29 Dec 92 09:25:46 GMT
Organization: Advanced Computer Research Institute

Dear Test Netters,   
I would like to know  if there is  an I.C with termination resistors mount or built-in, which is an  IEEE 1149.1 compatible including the Boundary Scan and TAP controller. The termination is for 100K ECL levels 50 Ohm parallel termination. this I.C should support at least the EXTEST instruction. 

Please let me know if  you have any knowledge about such a commercial I.C, 
or about in-house I.C which can be offered to ACRI.
Thanks, Happy holidays, and Happy New Year
Aran 
______________________________________________________________________
| EMAIL   : aran@acri.fr        |            Aran AIDAN                |
| PHONE   : (33) 72 35 80 06    | Advanced Computer Research Institute |
| switchboard :  72 35 84 00    | Tour Suisse, 1 Bd Marius VIVIER-MERLE|
| FAX     : (33)72 35 84  10    |     69443 LYON Cedex 03  / FRANCE    |
|_______________________________|______________________________________|




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 ______________________________________________________________________
| EMAIL   : aran@acri.fr        |            Aran AIDAN                |
| PHONE   : (33) 72 35 80 06    | Advanced Computer Research Institute |
| switchboard :  72 35 84 00    | Tour Suisse, 1 Bd Marius VIVIER-MERLE|
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Newsgroups: comp.lsi.testing
Subject: Re: maximum-length LFSRs
From: michele@deis21.cineca.it (Michele Favalli)
Date: 23 Dec 92 10:50:04 +0100
Distribution: comp.lsi.testing
Organization: Dept. of Electronics, Computer Science & Systems, Univ. of Bologna, Italy

Primitive polynomials are tabulated, look for instance: 

   author = "P. H. Bardell and W. H. Mc{A}nney and J. Savir",
   address = "New York",
   publisher = "John Wiley & sons",
   title = "Built-In Test for VLSI - Pseudorandom Techniques",
   year = "1987",

or 

   author = "S. W. Golomb",
   address = "S. Francisco",
   publisher = "Holden-Day",
   title = "Shift-Register Sequences",
   year = "1967",

Best regards 

Michele Favalli

============================================================================== 

Michele Favalli 
DEIS - University of Bologna                 tel. 39-51-644-3082 
Viale Risorgimento 2                         fax. 39-51-644-3073
40136 Bologna - ITALY                        e-mail: michele@deis16.cineca.it 

==============================================================================
Newsgroups: comp.lsi.testing
From: arul@ecs.comm.mot.com (Arul Ganeswaran)
Subject: testing
Organization: Motorola Singapore
Distribution: mot
Date: Tue, 29 Dec 1992 09:33:00 GMT

testing. please ignore

Newsgroups: comp.lsi.testing
From: s92068to@sfc.keio.ac.jp (Tetsuya Ohnishi)
Subject: test test test
Organization: Keio University Shonan Fujisawa Campus, Fujisawa Japan
Date: Sat, 2 Jan 1993 09:44:42 GMT


test

tetsu
Newsgroups: comp.lsi.testing
From: abdullas@newton.ccs.tuns.ca (Ahmad Samsudin Abdullah)
Subject: this is a test
Date: Tue, 22 Dec 1992 04:37:50 GMT
Distribution: *.test
Organization: Technical University of Nova Scotia, Halifax, N.S.

just testing  ............
Newsgroups: comp.lsi.testing
From: abdullas@newton.ccs.tuns.ca (Ahmad Samsudin Abdullah)
Subject: testing only
Date: Wed, 23 Dec 1992 20:20:55 GMT
Distribution: *.test
Organization: Technical University of Nova Scotia, Halifax, N.S.

  This is a test only..............
From: dean@cbmvax.commodore.com (Jeff Dean - LSI Test)
Newsgroups: comp.lsi.testing
Subject: Re: maximum-length LFSRs
Date: 21 Dec 92 15:05:59 GMT
Distribution: comp.lsi.testing
Organization: Commodore

In article <20246@ksr.com> chuck@ksr.com (Chuck Shavit) writes:
>I am looking for an algorithm to compute a primitive polynomial of a Linear
>Feedback Shift Register.  A primitive polynomial is a polynomial that cause
>an n-bit LFSR to generate a sequence 2**n-1 different numbers (usually
>there are many such polynomials for a given n; I am interested in just
>one...).
>Chuck Shavit
>Kendall Square Research
>chuck@ksr.com

Chuck - why bother computing them?  Find an error correcting codes text at the
library or bookstore.  They should have tables of pre-computed primitive polys
over GF(2) for you.  I have a table in my hands for degrees 2 through 28, so
if you need one in that range let me know.

jd
-- 
==============================================================================
|   |\ /|                                               Commodore Technology |
|   'O O`   Jeffrey Dean                                   1200 Wilson Drive |
|   > v <   VLSI Test and Design Assurance            West Chester, PA 19380 |
|     ^                                                   dean@commodore.com |
==============================================================================
Newsgroups: comp.compilers
From: chased@rbbb.Eng.Sun.COM (David Chase)
Subject: Re: Building a Lattice
Reply-To: chased@rbbb.Eng.Sun.COM (David Chase)
Organization: Sun
Date: Fri, 18 Dec 1992 21:13:04 GMT
Keywords: theory

un027705@wvnvms.wvnet.edu (Jon Beck) writes:
>Can anyone point me to an algorithm for building a lattice?

Go grubbing around in copies of the JACM from the last two or three years.
Look for an article whose title contains "efficient implementation" and
"lattice operations" in it.  (I'm afraid that's the best reference I can
give your; perhaps someone will have better information, or a neatly
organized stack of JACMs close at hand.)

>I happen to be specifically interested in a lattice whose meet is set
>intersection, whose join is set union, and whose partial ordering
>function is subset, but of course that shouldn't matter to the
>algorithm.

Ok, but...

>I'm posting here because it seems as though a compiler for a language
>which has multiple inheritance should have such an algorithm for
>building the inheritance hierarchy, which for multiple inheritance is
>a lattice.

You might want to provide a little bit more context here.  If you are
really doing your "is subtype of" implicitly, that is

    "I am a foo" = "I do the things a foo can do"

as opposed to

    "I am a foo" = "the programmer said my base type is a foo"

then you have a lattice, but if it is the second choice, then all you get
is a partial order, and not (necessarily) a lattice.

If you are also doing run-time type checking, you ought to verify that the
type system you are using is in fact useful.  I think that traveling up
and down in a DAG (or partial order, or lattice) is wrong, for instance.
(I think this because I think that classes should act like black boxes
with defined interfaces, and that their internals should not be affected
by where they are inherited.)

David Chase
Sun
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From: davidc@panix.com (David B. Chorlian)
Newsgroups: comp.compilers
Subject: Re: No Last Call Optimization on Sparc and DECstation
Keywords: Lisp, optimize
Date: 2 Jan 93 20:46:54 GMT
Article-I.D.: comp.93-01-004
Reply-To: davidc@panix.com (David B. Chorlian)
Organization: PANIX Public Access Unix, NYC

Tail Recursion folding on LISP-like languages:

If I recall correctly Brian Harvey's book in which he discusses
the implementation of LOGO on the Atari 6502 machines, it too
had tail recursion folding.

David B. Chorlian
Neurodynamics Lab
SUNY/HSCB 
davidc@panix.com
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Newsgroups: comp.compilers
From: preston@dawn.cs.rice.edu (Preston Briggs)
Subject: Re: Building a Lattice
Reply-To: preston@dawn.cs.rice.edu (Preston Briggs)
Organization: Rice University, Houston
Date: Sat, 19 Dec 1992 18:18:26 GMT
Keywords: theory

un027705@wvnvms.wvnet.edu (Jon Beck) writes:
>Can anyone point me to an algorithm for building a lattice? I happen to be
>specifically interested in a lattice whose meet is set intersection, whose
>join is set union, and whose partial ordering function is subset, but of
>course that shouldn't matter to the algorithm.

I've looked at this question for several days, trying to think how to
answer it.  I don't think it's a sensible question.

Computer scientists talk about lattices a lot.  Sometimes people use them
to help reason about problems.  But the idea of implementing a lattice is
harder to get a handle on.

A specific lattice has a meet, a join, a partial ordering, a universe of
values, perhaps including Top and Bottom elements.  Note though, that
there's no algorithmic component.

In your example,

	join is set union
	meet is set intersection
	ordering is subset
	a lattice element is a set of <something>
	top is set of all <something>s
	botttom is the empty set

Perhaps you're asking about how to implement the sets and the union,
intersection, and subset operators.  Best to consult an algorithms book,
perhaps 

	The Design and Analysis of Computer Algorithms
	Aho, Hopcroft, and Ullman
	Addison Wesley

Alternatively, you might be asking about how to declare a lattice type (or
type constructor), perhaps so you can declare many lattices and pass them
around as first-class objects.  In a dynamically-typed language like
Smalltalk (or whatever), you'd basically need an object that took three
functions as parameters: the meet, join, and ordering operators.  In a
strongly-typed language, the problem is much more difficult (and
interesting).  Perhaps it could be done cleanly in Russell; it doesn't
seem to make sense in languages like C++.

>it seems as though a compiler for a language which has multiple
>inheritance should have such an algorithm for building the inheritance
>hierarchy, which for multiple inheritance is a lattice.

It's also a lattice with single inheritance and no inheritance.  However,
most compilers don't have a reason to explicitly construct a lattice to
handle type resolution or whatever.  Instead, lattices are sometimes
useful to help a language designer reason about the type system of a
particular language.

Preston Briggs
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Newsgroups: comp.compilers
From: vanpraet@imec.be
Subject: compilers for DSP processors
Reply-To: vanpraet@imec.be
Organization: Compilers Central
Date: Mon, 21 Dec 1992 11:18:33 GMT
Keywords: DSP, question

This article was already posted (in a different form) on comp.dsp but it
only triggered a few interesting answers. Maybe comp.compilers can give
additional input.

As far as I know most of the code for a DSP-processor is written in
assembly language because either there is no suitable compiler available
or the compiled code is not good enough. Code generated by a C-compiler
for a commercial DSP-processor would be about 5 times as big as the same
algorithm manually coded in assembler. This is a generalization that can
offend some of you but I heard this from various sides, even from some DSP
processor manufacturers. Although the manufacturers also said that it will
be better in the future, as new DSP processors are designed with compilers
for High Level Languages in mind.
 
- Do you agree on the above ? (the quality of DSP compilers)
- What causes this factor of 5 on the code size ?
   e.g. -> The instruction set of a DSP processor does not lend itself
   	   to conventonal compiling techniques ?
        -> the High Level Languages are not useful for DSP? 
            - not enough parallelism in C (too difficult to extract the
              parallelism)?
            - too many possible constructs in C ? (a subset of C is better)
            - non-procedural languages as e.g. Silage are better ?
        -> no global ordering and scheduling of the generated code ?
        -> no possibility of using all the provided tricks for the DSP
           processors ?
            - no or not enough use of the low-overhead-loop facility of a
              processor as the "DO" for Motorola and the "RPT" for Texas
              Instruments processors ?
            - no use of special addressing ? (e.g. in circular buffers)
            - no use of special block data moves ?
            ...
         ...

I also know of three code generation approaches that would generate more
optimal code : - The GABRIEL (PTOLEMY) system of prof. Lee at Berkeley
                 (mainly targeted towards the Motorola 56k)
               - The code generator for Texas Instruments' TMS320C30 in the
                 DSP-station of EDC (in Belgium)
               - The SPW (Signal Processing Workstation) by Comdisco, Inc.

These don't start from a procedural language (resp. from block diagrams or
from Silage) and have some sort of library of manually written
code-pieces. They also perform some sort of global scheduling and
optimization. Anyone used these ? What is their quality on real life
examples ?

You can reply by email or post a follow-up (don't include this whole thing
!).  If I get significant answers, a summary will be posted.
--
Johan Van Praet  | IMEC , Kapeldreef 75
vanpraet@imec.be | 3001 HEVERLEE , BELGIUM
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Newsgroups: comp.compilers
From: bjornc@groucho.csd.uu.se (Bj|rn Carlson)
Subject: Re: Building a Lattice
Reply-To: bjornc@groucho.csd.uu.se (Bj|rn Carlson)
Organization: Computing Science Department, Uppsala University, Sweden
Date: Tue, 22 Dec 1992 19:33:41 GMT
Keywords: theory

>>Can anyone point me to an algorithm for building a lattice?

>Go grubbing around in copies of the JACM from the last two or three years.

The reference is:
"Efficient Implementation of Lattice Operations"
Hassan Ait-Kaci, Robert Boyer, Patrick Lincoln, and Roger Nasr
ACM Transactions on Programming Languages and Systems
January 1989, vol 11, #1
115-147

>I happen to be specifically interested in a lattice whose meet is set
>intersection, whose join is set union, and whose partial ordering
>function is subset, but of course that shouldn't matter to the
>algorithm.

The idea of the algorithm is that a set is encoded as a bit-vector,
where the coding maps meet and join to bitwise-and and bitwise-or.
The article also deals with compact encodings of sparse sets.

--
Bjorn Carlson
Computing Science Department
Uppsala University
Box 311 S-751 05
Uppsala Sweden

Bjorn.Carlson@csd.uu.se (bjornc@csd.uu.se, bjornc@sics.se)
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Newsgroups: comp.compilers,comp.arch
From: Andre.Marien@cs.kuleuven.ac.be (Andre Marien)
Subject: Sun sparc behavior
Reply-To: Andre.Marien@cs.kuleuven.ac.be (Andre Marien)
Organization: Dept. Computerwetenschappen K.U.Leuven
Date: Tue, 22 Dec 1992 11:00:50 GMT
Keywords: sparc, architecture

While trying to get some ideas for optimization, we run into some oddities
which we cannot explain. We have no solid background in architecture, but
would like to have some explanation for the observed behavior.  Our
test frame should have all data and instructions in the cache.  (compare
loop with NN nops with loop where N nops are replaced).

First, any store takes 5 cycles on a sparc 1, and 7 cycles on a sparc 2
server.  Is this number related to the pipeline depth ?  Why is it that
stores take at least 5 cycles, even if the surrounding code is just
no-ops?

Our guesses:
1) the pipeline is emptied for some reason.
2) The cache can only deliver on datum at the time, so it cannot deliver
   both an instruction and data.
   As reading takes 2 cycles on all sparcs tested, it is not unreasonable
   for us for the store to take 3 cycles. But 5 ??

Second, two consecutive stores add 2 cycles. Two consecutive loads add no
cycle.  This seems to imply that despite the fixed cost, the write
buffer(s) is not available in time.  However, three stores after each
ather only incur these 2 extra cycles once !?  On the sparc 2 server, it
looks as if the distance between two stores should be odd to avoid those 2
cycles. We think it may have to do with the pipeline organization, but
have no clue.

Third, on the sparc 2 server, we notice that a load + store takes 7
cycles, not 9, independent of whether we store to the location of the load
or not.  The same is true for the combination store + load. Putting some
noops between the load/store or store/load increases the number of cycles
just by that number.How can an independent load make a store go faster ??

If any kind soul can give some feed-back or references, we would be happy.
We know we don't need the architecture definition, but some docs on the
implementation. Some clues we obviously missed would already be very nice.

Andre' Marien
bimandre@cs.kuleuven.ac.be
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Newsgroups: comp.compilers
From: japancs@cs.arizona.edu (Japan CS Project)
Subject: SIG Notes Series (SIGPL meeting held on October 5, 1989)
Reply-To: japancs@cs.arizona.edu (Japan CS Project)
Organization: Compilers Central
Date: Wed, 23 Dec 1992 18:42:48 GMT
Keywords: bibliography

------------------------------------------------------------------------
SIG Notes Series (SIGPL meeting held on October 5, 1989)

            published by

Information Processing Society of Japan  (in Japanese)
------------------------------------------------------------------------

[Collection and dissemination of this information supported in part by
 ONR Grant N0001492J1737.]

Incremental Garbage Collection by Multiple Reference Management of
 Data Objects in KL1
	by Y. KIMURA, T. CHIKAYAMA and N. TAKEI(2)
	 Institute for New Generation Computer Technology, 1-4-28,
	 Mita, Minato-ku, Tokyo 108, Japan
	 (2)  Fujitsu Social Science Laboratory Ltd., 1-6-4 Oosaki,
	  Shinagawa-ku, Tokyo 141, Japan

An Incremental Analysis on Degraded Parse Tree
	by K. KAIJIRI
	 Faculty of Engineering, Shinshu University, 500 Wakasato,
	 Nagano 380, Japan

Stream Based Description of Parallel Semantic Analysis
	by H. NISHIYAMA and K. ITANO(2)
	 The Doctoreal Program in Engineering, Graduate School,
	 University of Tsukuba, 1 Tennodai, Tsukuba, Ibaraki, Japan
	 (2)  Institute of Information Sciences and Electronics, 
	  University of Tsukuba

An Extension of Object-Oriented Distributed Programming Language
 for Multi-users Environment of OZ: Object-Oriented Open Distributed System
	by M. TSUKAMOTO, N. TANAKA(2), S. NAKAGOME(3), H. SHINOHARA(4),
           T. KONDO(5) and I. MIZUTANI(6)
	 Electrotechnical Laboratory, 11-4, Umezono, Tsukuba Science City,
         305, Japan
	 (2)  Matsushita Electric Industrial Co. Ltd.
	 (3)  ABC Co. Ltd. 
	 (4)  Matsushita Electric Industrial Co. Ltd.
	 (5)  Sharp Corporation
	 (6)  Sumitomo Electric Industries, Ltd.
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Newsgroups: comp.compilers,comp.std.c,comp.std.c++