From: tjehl@sedona.intel.com (Timothy Jehl)
Subject: Pentium vs 68060 (was: Intel vs Motorola)
Originator: tjehl@sedona
Reply-To: tjehl@sedona.intel.com
Organization: Intel Corporation.
Date: Fri, 11 Dec 1992 21:58:53 GMT


andy@onkyo.incubus.sub.org (Andreas Goehler) writes:
> 
> Who knows ANYTHING about Intel's new 586 alias P5 alias Pentium ???
> 
> Will it be 64-bit Data and Address Bus. Will it be 8-bit internal as all
> other x86 ??? Does it include a 386 unit as planed earlier ??? Is it any
> competition to the new MC68060 as soon as both of these processors are out.
> Another thing, what power usage will the 586 have ???
> 

PART I - the Pentium
====================

   Well, let me tell you a bit about what is public knowledge about the
Pentium processor.
   1) It is superscaler (two integer execution units, as well as a
      pipelined floating point unit)
   2) Expected performance of 100+ MIPS
   3) Floating point with a 5-10x improvement over a 33Mhz i486(tm)
   4) 64 bit external bus
   5) 32 bit internal integer path
   6) 64 bit floating point path
   7) more total cache, with separate code and data caches
   8) 100% compatible with previous generation software
   8) Systems in production in 1993

Editorial comment: "8-bit internal bus"?!?!?!  Where'd you get that?


PART II - the 68060
===================

Now, a reprint of a previous article which I posted to comp.sys.amiga.misc:


1) Design targets

   >3x performace over 040-25 with existing compilers

** editorial comment - there is an implication here that the architecture
   will be such that code ordering will affect performance (no surprise on
   a modern processor), and that new compiler technology will be part of the
   performance increase (i.e. the software that you already own may not get
   the full benefit of the performance increase)

   >2 million transitors, .5 micron triple metal, 3.3v static

   '040 style package with similar bus

   '040 code compatible for user-mode code

2) Architecture

   Superscaler pipeline
      4 stage inst. fetch pipeline
      parallel 4 stage operand execution pipelines

** editorial comment - looking at the block diagram, there appears to
   to be a single floating point unit, which is attached to one of these
   pipelines, implying that you can execute two integer instructions in
   parallel, or one integer and one floating point if the code is ordered
   properly.

      Branch cache for instruction fetch prediction (the block diagram
         implies that it is a brance target cache, rather than a branch
         cache)

   Internal Harvard architecture
      Execution pipelines are in lock-step
      Simultaneous but in-order execution
      Supports precise exception model

   '040 compatible bus
      32 bit address and data buses
      support for cache line bursts (16 bytes = 4 words)

3) Assorted block diagrams which I am not going to attempt to duplicate
   in an ASCII file.

4) Dispatch algorithm

   A bunch of verbage describing the dispatch algorithm.

   On integer code, analysis shows 50-60% of instructions from existing
      compilers would be executed as pairs.

** editorial comment - this is a low number, but is a result of no
   optimization on existing code.  New compiler technology should be
   able to drive this number up near the 75-80% range.

5) Branch cache

   yep, it's a branch target cache

   branch history information is kept for branch prediction

   one clock penalty for incorrect branch prediction

6) FPU

   compatible with 68040 FPU programming model
      extended precision operation
      IEEE 754 compliant

    Implemented in one of the integer pipelines

    3 units - add, multiply, divide

    3 cycle adds, 4 cycle multiplies, 24 cycle divides

7) Pipeline diagram which I am not going to attempt to duplicate
   in an ASCII file.

8) Summary

   060-50 w/ new compiler  ~3.5x  040-25 with existing compiler

   design targeted for 50/66 MHz, with 3.3 V operation

** editorial comment - lower voltage operation also normally
   implies a lower frequency specification on a CMOS product

   production volumes in the first half of 1994

PART III - the comparison
=========================

   I have no intention of getting into the processor flame wars.  Both
companies have given reasonable comparisons of their next generation
products with their present products.  However, the Intel part will be
in production systems in 1993, while the Motorola part will not be out
before 1994.
   I hope this is at least a partial answer to some of your questions.

TJ


-- 

"It really only matters to the people who care."

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