From: wyle@synopsys.com (Mitch Wyle)
Newsgroups: biz.comp.software
Subject: (March 16) SYNOPSYS ADDS VHDL DEBUGGING TO VHDL SYSTEM SIMULATOR
Date: 24 Jul 92 02:27:35 GMT
Organization: Synopsys Inc.

3-D Debugging environment helps IC and system designers
generate fast, efficient, correct VHDL

MOUNTAIN VIEW, Calif. Mar. 16, 1992 Synopsys Inc. today announced the
availability of their 3-D Debugging environment for debugging high-level
integrated circuit (IC) and system designs in VHDL, the industry-standard
very-high-speed integrated circuit (VHSIC) Hardware Description Language.
3-D Debugging is offered in Synopsys' VHDL System Simulator Version 2.2a,
which began shipping this month.

Synopsys also announced the availability of its COVERAGE utility within
the 3-D Debugging environment.  COVERAGE, the first utility of its kind
in the electronic design automation industry, executes and profiles every
line of VHDL source code, detecting bottlenecks and untested sections
of VHDL.  COVERAGE helps ensure design quality by showing designers
sparsely exercised regions of their VHDL description which require more
thorough analysis and simulation.

Another industry first in Synopsys' 3-D Debugging environment is the
back-annotation of bit values, bus values, and enumerated types from the
simulation results onto the block diagram.  Backannotation enhances the
visual connection between the simulation values and the actual net in
the design a connection which is often difficult for a designer to make,
especially if the schematic has been synthesized and net names have been
chosen by the synthesizer.  By making the link easier, 3-D Debugging
offers a more productive debugging environment.


Synopsys' VHDL System Simulator and its 3-D Debugging environment
support the full power of VHDL, which enables designers to create
and debug electronic systems at the behavioral, RTL, and gate levels.
3-D Debugging is a requirement for VHDL use because of these different
levels of abstraction, and the need of designers to debug at the level
in which the design is created and viewed.

3-D Debugging enables designers to analyze and debug their design in
three dimensions: VHDL source-level text, block diagram, and waveform.
Source-level debugging is required for behavioral and some RTL
descriptions, where the designer needs to query and analyze the VHDL text.
Block diagram debugging is necessary for RTL and gate-level designs, where
the designer needs to view the system as a structural representation,
rather than as VHDL source code.  Waveform viewing is useful for all
domains and levels of abstraction.

Debugging designs at the gate level is inefficient," said Jeff
Lewis, group marketing manager for simulation products at Synopsys.
"The more time designers spend up front, debugging VHDL at the RTL and
behavioral levels, the more correct their designs are when they get
to the implementation stage."  "3-D Debugging automates the high-level
debugging process and can directly point designers to potential problems,
rather than passively presenting reams of data and expecting designers to
notice any anomalies.  Debugging this way is much more likely to produce
working designs the first time, in much less time than with conventional
debugging techniques."  3-D Debugging is tuned for the way VHDL designers
operate:  enter VHDL code, debug design, modify code, quickly re-analyze,
and re-simulate.  After debugging the VHDL description, designers are
able to automatically generate a correct gate-level implementation
using Synopsys' VHDL synthesis tools, and optimize the design for
performance, area, and testability using Synopsys' Design Compiler
and Test Compiler.  Using this high-level design methodology, designers
can spend more time focusing on functional implementation and debugging,
and less time debugging the gate-level implementation.

3-D Debugging is available in Synopsys' VHDL System Simulator and
Simulation Graphical Environment (SGE) Version 2.2, and is available
immediately.  U.S. pricing for these two tools which provide the
complete 3-D Debugging environment, a 100 percent implementation of
the VHDL language, and a complete simulation design environment starts
at $34,000.  Synopsys Inc. develops, markets and supports high-level
design automation (HLDA) software for designers of integrated circuits
and electronic systems.  The Company currently offers a comprehensive
set of synthesis, simulation, and test tools, which are supported on
the most widely used UNIX workstations.

3-D Debugging, VHDL System Simulator, Design Compiler and Test Compiler
are trademarks, and Synopsys is a registered trademark, of Synopsys Inc.
All other brands or products are trademarks or registered trademarks of
their respective holders and should be treated as such.

For more information, contact:

Lois DuBois                    lois@synopsys.com
Synopsys Inc                   (415) 694 4255
700 E. Middlefield Rd.         (415) 965 8637 (fax)
Mountain View, CA  94043-4033  (800) 843 5669 x4255
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