From: storm@cs.mcgill.ca (Marc WANDSCHNEIDER)
Subject: Re: RISC goes CISC?
Organization: SOCS - McGill University, Montreal, Canada
Date: Sun, 8 Nov 1992 19:39:46 GMT

In article <1992Nov6.092012.19239@rhein-main.de> vhs@rhein-main.de writes:
>Wasn't one of the principles of RISC the principle of putting as much work
>as possible from execution to compile time?

	Only indirectly perhaps.  The basic philosohpy is that if the
instruction isn't used very frequently, then there is little reason to include
it in the instruction set.

	However, it is entirely possible to get a little overzealous and
reduce instructions to the point where they would be TOO small, and compilers
would end up making the "Hello World" program 100k or so (exaggeration).

>Under this assumption, how does e.g. SuperSPARC fit this principle? As far
>as I know the processor does a lot of cross-checking between pipelines,
>squashing instructions depending on non-trivial conditions, etc. Is that done
>just to maintain compatibility with previous implementations?

	This is strictly a hardware IMPLEMENTATION detail, and doesn't really
affect the programmer instruction set or model.  The problem with the Super-
Sparc is that it tries to issue three instructions per clock cycle.  If there
are dependancies between the instructions, then problems will arise, and
special hardware must be added to the processor to take whatever actions
are necessary so that the meaning of the program remains intact.

>Could, theoretically, the most recent compilers take care of this
>at compile-time, thus eliminating the need for run time

	Compilers are EXTREMELY difficult to write, and can only do a good
job at best of reordering instructions so that pipeline dependancies are 
avoided.  It is also enitrely possible that a situation will arise where
it is just impossible to remove dependancies....

>Aren't pipelines necessary so that instructions that take several cycles
>(i.e. "complicated" instructions) can be issued one per cycle? Wouldn't

	Pipelines are one way of achieving the Ideal 1 instruction issued
every clock cycle.

>it conform more to the RISC principle to keep instructions so simple
>that they only *need* one cycle to execute and concentrate on a *fast*

	Given current technologies, it could end up being EXTREMELY difficult
to make instructions  execute in one clock cycle, if the clock cycles starting
dropping below a certain time.  There is just so much that goes on, and gates
can only go so fast.  Thus, the compromize is to try and overlap execution.

>Will PCs ever compare favorably to workstations? 

	Intel is slowly finding that the CISC way of doing things is not
always optimal.  Pipelining a CISC chip is painstaking brutal, and they 
are thus focusing their efforts on the new Pentium chip, which will largely
be a RISC chip which can execute the 486 instruction set if need be.

>Will Jane marry Tarzan?

	No, she ran off to Vegas with a Lesbian Biker Lover named Despina.
Last I heard, they were rumored to be Mud-Wrestling at the Hotel De Sleeze.


ToodlepiP!
Marc 'em.
-- 
  storm@cs.mcgill.ca           McGill University         "-- Attack ships on
  Marc Wandschneider           Montreal, CANADA             fire "
	Any opinions expressed are not mine, but those of the Demon Lord
      Yeegeheeegenogohugu who possessed me whilst I munched on Raisin Bran.