From: wayne@backbone.uucp (Wayne Schlitt)
Subject: Re: Any new instructions in a i486?
Followup-To: comp.sys.intel
Organization: The Backbone Cabal
Date: Fri, 11 Dec 1992 22:44:22 GMT


There have been a fair amount of discussion in comp.sys.intel about
what new instructions the i486 has (and if the Cyrix 486SLC/486DLC
implement them.)

So far, the only reliable source about what the Cyrix 486's implements
comes from Michael Slater's Microprocessor Reports magazine.  He says
that all of the new 486 instructions are implemented.  He does not
explicitly say that the new 486 flags and control register changes
were implemented.  (these changes can only be seen in supervisor mode)

NeXTStep is said to not run on the Cyrix 486 chips because "they are
not real 486's".  No one has come up with a reliable reason _why_ NeXT
doesn't think they are "real 486's" or why NeXTStep won't run on them.


Anyway, quoting from my 1990 i486(tm) Microprocessor Programmer's
Reference Manual from Intel, chapter 21.3:

---  start of quote  ---

21.3 DIFFERENCES FROM THE 386(tm) CPU

Very few differences exist between the programming models of the 386
DX or SX and i486 processors.  The i486 processor defines new bits in
the EFLAGS, CR0, and CR3 registers, and in entries in the first- and
second-level page tables.  On the 386 processors, these bits were
reserved, so the new architectural features should not be a
compatibility issue.


21.3.1 New Flag

The AC flag (bit position 18), in conjunction with the AM bit in the
CR0 register, controls alignment checking.


21.3.2 New Exception

The alignment-check exception (exception vector 17) reports unaligned
memory references when alignment checking is being performed.


21.3.3 New Instructions

There are three new application instructions:

*  The BSWAP instruction

*  The XADD instruction

*  The CMPXCHG instruction

There are three new system instructions, used for managing the cache
and TLB: 

*  The INVD instruction

*  The WBINVD instruction

*  The INVLDPG instruction


The form of the MOV instruction used to access the test registers has
changed.  New test registers have been defined for the cache, and the
model of the TLB accessed through the test registers has changed.


21.3.4 New Control Register Bits

Five new bits have been defined in the CR0 register:

* the NE bit

* the WP bit

* the AM bit

* the NW bit

* the CD bit


Two new bits have been defined in the CR3 register:

* the PCD bit

* the PWT bit


21.3.4 New Page-Table Entry Bits

Two bits have been defined in page table entries for controlling
caching of pages:

* the PCD bit

* the PWT bit


21.3.6 Changes in Segment Descriptor Loads

On the 386 processor, loading a segment descriptor would always cause
a locked read and write to set the Accessed bit of the descriptor.  On
the i486 processor, the locked read and write occur only if the bit is
not already set.


---  end of quote  ---  (all typos are mine)

That's the entire section on the differences.  You have to go look at
other parts of the manual to find out what the details are, but
basically they come down to this:


The BSWAP instruction is useful for change the byte orders to/from little
endian <==> big endian.  


The XADD and CMPXCHG instructions are useful for implementing
semaphores in multi-processor systems.  Not something a normal
application would have much use for.


The supervisor instructions INVD, WBINVD invalidate the cache and the
latter one also makes sure that the write-back buffers get flushed.
There is a not saying that these instructions are
implementation-dependent; its function may be implemented differently
on future Intel processors.

The INVLPG instruction invalidates a TLB entry.  it is also noted as
an implementation-dependent instruction that may change.


The AM bit in CR0 and the AC flag are used to implement alignment
checking.  If these bits are set, then various alignment restrictions
are enforced.  (2 byte items must be on a even byte boundary, 4 byte
items must be on a 4 byte boundary, etc)


the NE bit enables the numerical error detection for floating-point

the WP bit prevents supervisor programs from overwriting user level data

the NW bit says that the cache is not write-through

the CD bit disables the cache

the PCD bit is the Page-Level Cache Disable

the PWT bit is the Page-Level Writes Transparent


all and all, there are _very_ few real differences between the 386 and
the 486.

-wayne
Newsgroups: comp.arch