HDTenEightyP/NetNews huggingface dataset:
From: jab3@cec2.wustl.edu (John Alonzo Breen)
Subject: Re: Resolved signals
Organization: Washington University, St. Louis Mo.
Date: Mon, 27 Jul 1992 12:57:46 GMT

In article <memo.540055@cix.compulink.co.uk> jmessenger@cix.compulink.co.uk writes:
>
>Here are a couple of apparently simple questions, but I can't find the
>answers in the LRM or the interpretations:
>
>subtype RTYPE is RESOLVED INTEGER;
>type ARR is ARRAY (0 to 1) of RTYPE;
>
>signal S: ARR;
>
>I know that RTYPE is a resolved subtype.  But
>is S    a resolved signal?   (I believe not)
>Is S(0) a resolved sigal?    (Who knows?)
>

This is basically what the Std_Logic and Std_Logic_Vector types in the
1164 package are, I believe.  S would be a composite of resolved
signals.  This is important, because if S was itself resolved, you
couldn't drive one element of S without having drivers for all the
other elements in the same process.

Unfortunately, this has the disadvantage that S is not implicitly
convertible to an array of integers (although the elements of S are
implicitly convertible to integers).  In other words, if you had a
port of type "ARRAY (0 to 1) of INTEGER", you couldn't directly
connect it to a signal of type ARR without a conversion function.
--
John A. Breen                   |
jab3@cec1.wustl.edu             | This space unintentionally left blank
johnb@hobbes.mdc.com            |
Tel: (314)234-4341              |
From: kuhlmann@upenn5.hep.upenn.edu (Hans B. Kuhlmann)
Newsgroups: comp.lang.verilog
Subject: Looking for a (possibly) missing TTL lib
Summary: SN74LS74 missing
Date: 22 Jul 92 14:47:14 GMT
Distribution: na
Organization: University of Pennsylvania

I cannot find the SN74LS74 gate in the TTL library.  Is it missing
from the distribution or have I lost it?

Many thanks.

- Hans
From: eli@netcom.com (Interpretive Systems)
Newsgroups: comp.lang.verilog
Subject: Re: X based utilities
Date: 21 Jul 92 15:41:59 GMT
Organization: Netcom - Online Communication Services  (408 241-9760 guest)

In article <1992Jul20.193826.22430@news.mentorg.com> jayaram@simdiv1.mentorg.com (Bellave S. Jayaram) writes:
>Hi folks,
>	I am trying to find out if people have written/used any utilities 
>for Verilog (other than those that come with it) based on X windows.  Areas 
>in which such tools may be useful are, for eg., 
>
>a) Model library browsing 
>b) Stimulus generation
>c) Post-processing
>d) Debugging
>
>	If such tools do not exist, I would also like to get some feedback 
>on what utilities people would like to see/use.
>
>	I will summarize if there is enough response.
>

Veritools Inc (415) 941-6870 and interHDL (408) 749-8775 have some tools
for c) and d) above.
Newsgroups: comp.lang.verilog
From: etxmesa@eos.ericsson.se (Michael Salmon)
Subject: Reliability of `undef
Keywords: verilog-xl `undef
Reply-To: etxmesa@eos.ericsson.se (Michael Salmon)
Organization: Ericsson Telecom AB
Date: Wed, 29 Jul 1992 07:14:31 GMT

I am trying to include a computer generated casex into a verilog model.
The inclusion was performed painlessly using `include however the casex
has to be included in several places with different statements used in
each place. To get around this the include file has numerous `ifdefs.
My problem is that the `defines stay defined so if I `define a in
module A and b in module B then in effect I get ab in module B. I
guessed that an `undef existed but I couldn't find it in the
documentation so I used strings to scan the executable and found the
keyword, tried inserting `undefs and all worked as I wanted. Now I am
worried about using an undocumented feature and about synthesising. I
am using VERILOG-XL 1.6.0.1 and I wondered if anyone had any comments
on my dilema. BTW basically my only control over the include file is to
post process it, I can't change its format.

Thank you in advance.

-- 

Michael Salmon

#include	<standard.disclaimer>
#include	<witty.saying>
#include	<fancy.pseudo.graphics>

Ericsson Telecom AB
Stockholm
From: savel@hal.COM (Bharat P. Savel)
Newsgroups: comp.lang.verilog
Subject: Re: Getting round verilog hierarchical structure
Date: 28 Jul 92 17:24:05 GMT
Organization: HaL Computer Systems Inc.
NNTP-Posting-Host: gorn.hal.com

with that kind of instantiations, a performance problem may arise. for 
instance, we do not know the size of A, B or C. true, it is a great way to
go structural, but when the 3 units become very big, speed drops.

an alternate way be to have 3 tasks or 3 @always statements. but is this
what you want?
-- 
-------------------------------------------------------------------------------
Bharat P. Savel                                     /tmp/Design_Engineer
Ext. 1307
Motto: If we can't fix it, it ain't broke
Newsgroups: comp.lang.verilog
From: eversole@acae037.cadence.com (Richard Eversole; x6239)
Subject: Re: Looking for a (possibly) missing TTL lib
Reply-To: eversole@acae037.cadence.com (Richard Eversole; x6239)
Organization: Cadence Design Systems, Inc.
Distribution: na
Date: Mon, 27 Jul 1992 10:28:37 GMT

Try SN74LS74A

This is the name in verilogTLL lib under Composer 4.2
There is no model of the SN74LS74  (Note missing A) in 
the Cadence supplied library.
-- 
  
  =====================================================================

    eversole@cadence.com
  
    Live long and prosper !
From: Chijioke.Anyanwu@brunel.ac.uk (Chijioke D Anyanwu)
Newsgroups: comp.lang.verilog
Subject: Getting round verilog hierarchical structure
Date: 27 Jul 92 16:46:15 GMT
Organization: Brunel University, West London, UK

Modules in Verilog are organised in a hierarchical structure which,
presumably, is in keeping in line with standard programming practice.
However, I've come up against situations when this rigid structure has
been a problem. 

As a simple example, consider the system below in which A, B and C are
modules (representing hardware blocks) with dedicated links to each other.

			      _______
			      |     |
			      |  A  |
			      |     |
			      -------
			      /    |
			     /     |
			    /      |
		     -------       |
		     |     |       |
		     |  B  |       |
		     |     |       |
		     -------       |
			   \       |
			    \      |
			     \     |
			      -------
			      |     |
			      |  C  |
			      |     |
			      -------

In developing a verilog model, A could instantiate B and C but, as far as
I can see, this would then mean the link from B to C would not be possible
as there is no way of directly linking a module to another module which it
is neither instantiated by nor instantiates.

I've usually been able to get round this using one of two methods of
indirect linking (which I call transit and transmission) but while they 
work alright, it's just not the same as direct links and can be quite
inconvenient. I'd like to know if anyone else has had this problem and if
there is some hidden means of implementing direct links in such situations.

Chijioke.
Newsgroups: comp.lang.verilog
From: cranston@ayn.com (W. Scott Cranston)
Subject: Re: Getting round verilog hierarchical structure
Organization: Cadence Design Systems, Lowell MA, United States of America
Date: Fri, 17 Jul 1992 02:36:24 GMT

In article <dank.712282499@blacks.jpl.nasa.gov> dank@blacks.jpl.nasa.gov (Dan Kegel) writes:

> Chijioke.Anyanwu@brunel.ac.uk (Chijioke D Anyanwu) writes:
> >Modules in Verilog are organised in a hierarchical structure which,
> >presumably, is in keeping in line with standard programming practice.
> >However, I've come up against situations when this rigid structure has
> >been a problem. 
> >As a simple example, consider the system below in which A, B and C are
> >modules (representing hardware blocks) with dedicated links to each other.
> > [ Diagram of A, B, and C, with a signal running from each to each. ]
> 
> Why not use an overlying module which invokes A, B, and C,
> and uses module ports for all communication?
> Seems more egalitarian than putting any of A, B, or C higher or lower.
> - Dan Kegel (dank@blacks.jpl.nasa.gov)

Or...remember that one can always use a complete hierarchical path to
access objects in any other module in the system.  

For instance:

module a;

wire m;

xor x1(m, b.t, c.t);

endmodule


module b;
wire w1, t;

nand n1(t, w1, c.t);

endmodule


module c;
wire w1, w2, t;

nor n1(t, w1, w2);

endmodule

I believe this will give you what you want.

Scott Cranston
Cadence Design Systems



+---------^>        "The Spirit of Massachusetts is the Spirit of America"
|        <                    -Massachusetts Division of Tourism
+-------. \   7     "Right..."
         \_\_/                -cranston@cadence.com
--
+---------^>        "The Spirit of Massachusetts is the Spirit of America"
|        <                    -Massachusetts Division of Tourism
+-------. \   7     "Right..."
         \_\_/                -cranston@cadence.com
Xref: sparky comp.lang.verilog:291 misc.misc:3071
From: jcooley@seqp4.sequoia.com (John Cooley)
Newsgroups: comp.lang.verilog,misc.misc
Subject: Evil Synopsys
Date: 31 Jul 92 13:40:10 GMT
Organization: Sequoia Systems Inc., Marlboro, Mass.


> From: wyle@synopsys.com (Mitch Wyle)
>
> I am about to post the following press information to biz.comp.software:
> 
> Subject: (Jan 24)   SYNOPSYS PORTS SYNTHESIS AND SIMULATION TOOLS
> Subject: (March 16) SYNOPSYS ADDS VHDL DEBUGGING TO VHDL SYSTEM SIMULATOR
> Subject: (April 13) SYNOPSYS INTEGRATES HIGH-LEVEL DESIGN TOOLS
> Subject: (May 4)    SYNOPSYS INTRODUCES TEST COMPILER PLUS
> Subject: (May 11)   TEXAS INSTRUMENTS ENDORSES SYNOPSYS VHDL SYSTEM SIMULATOR
> Subject: (June 1)   SYNOPSYS SIGNS AGREEMENT WITH NEC ELECTRONICS INC.
> Subject: (June 8)   SYNOPSYS INTRODUCES BREAKTHROUGH IN SYNTHESIS TECHNOLOGY
> Subject: (June 22)  SYNOPSYS TO ACQUIRE MAJORITY INTEREST
> Subject: (July 8)   Y. HIRANO NAMED PRESIDENT OF NEWLY ESTABLISHED NIHON
> 
> Please send flames, comments, and opinions to me: wyle@synopsys.com


I am SHOCKED and OFFENDED at this flagrant and irresponsible posting
on comp.cad.cadence by their evil arch-rival software competitor: SYNOPSYS!

And, worst yet, it's something from their marketting department!

Does Synopsys have no respect for Cadence's software tools?

The next thing you know, you'll have that joker posting notices again on
comp.cad.cadence for Synopsys users to join the E-mail Synopsys User Group!

Something's gotta be done!  <chuckle chuckle>

===========================================================================
Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
===========================================================================
     !!!     "It's not a BUG,    |           jcooley@sequoia.com
    /o o\  /  it's a FEATURE!"   |         jcooley@sds.sequoia.com
   (  >  )                       |        "Yes, We make trees here!"
    \ - /       |
    _] [_       |        "This here ain't no one's opinion 'cept my own."
From: cindy@zoran.hellnet.org (Cindy Eisner)
Newsgroups: comp.lang.verilog
Subject: Re: Getting round verilog hierarchical structure
Date: 29 Jul 92 07:47:27 GMT
Organization: Zoran Microelectronics LTD. Haifa, Israel.

In article <Bs23x4.330@brunel.ac.uk>, Chijioke.Anyanwu@brunel.ac.uk (Chijioke D Anyanwu) writes:

> In developing a verilog model, A could instantiate B and C but, as far as
> I can see, this would then mean the link from B to C would not be possible
> as there is no way of directly linking a module to another module which it
> is neither instantiated by nor instantiates.


please elaborate on what you mean by "direct link"?  i don't see any problem
in having a signal between each pair of A-B, A-C, B-C, so i guess this is 
not what you mean.

-- 

    Cindy Eisner,                     Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: cindy@Zoran.HellNet.Org
    Advanced Technology Center
    Haifa 31204, Israel               Could be my employer doesn't agree.
Newsgroups: comp.lang.verilog
From: vasu@leland.Stanford.EDU (Swaminatha Vasudevan)
Subject: Verilog Synthesis
Organization: DSG, Stanford University, CA 94305, USA
Date: Wed, 29 Jul 92 03:05:23 GMT

Who makes ASIC synthesis s/w for Verilog besides Synopsys and Cadence?

\V

Newsgroups: comp.lang.verilog
From: dank@blacks.jpl.nasa.gov (Dan Kegel)
Subject: Re: Getting round verilog hierarchical structure
Organization: Image Analysis Systems Group, JPL
Date: Tue, 28 Jul 1992 00:14:59 GMT

Chijioke.Anyanwu@brunel.ac.uk (Chijioke D Anyanwu) writes:
>Modules in Verilog are organised in a hierarchical structure which,
>presumably, is in keeping in line with standard programming practice.
>However, I've come up against situations when this rigid structure has
>been a problem. 
>As a simple example, consider the system below in which A, B and C are
>modules (representing hardware blocks) with dedicated links to each other.
> [ Diagram of A, B, and C, with a signal running from each to each. ]

Why not use an overlying module which invokes A, B, and C,
and uses module ports for all communication?
Seems more egalitarian than putting any of A, B, or C higher or lower.
- Dan Kegel (dank@blacks.jpl.nasa.gov)
From: echen@hardy.u.washington.edu (Ed Chen)
Newsgroups: comp.lang.verilog
Subject: Re: Verilog Synthesis
Date: 29 Jul 92 08:13:34 GMT
Organization: University of Washington, Seattle

In article <1992Jul29.030523.28537@leland.Stanford.EDU> vasu@leland.Stanford.EDU (Swaminatha Vasudevan) writes:
>Who makes ASIC synthesis s/w for Verilog besides Synopsys and Cadence?
>
>\V

COMPASS Design Automation Tools - VLSI Technologies, Phoenix AZ.

					Ed
					echen@u.washington.edu
Newsgroups: comp.lang.sigplan
From: ppc1@cec1.wustl.edu (Peter Pui Tak Chiu)
Subject: Simplification
Organization: Washington University, St. Louis Mo.
Date: Sat, 25 Jul 1992 11:51:15 GMT


hi everyone,

i have a real naive question:

        how to do symbolic simplification using scheme, lisp or anything...?

what i mean is symbolic simplification like MATHEMATICA.

here are some examples:

          (* a (+ b (/ c a))) ==> (+ (* a b) c)
          (+ (* a b) (* a c)) ==> (* a (+ b c))

these are just very simple cases and are intended to explain what i mean...
i want to know a way to find the "simplest form" of any algebric expression.
not only those which are as simple as the above.

can anyone tell me how to do it or refer me to some books that talk about it?

thanks in advance

peter

Newsgroups: comp.lang.scheme
From: quale@saavik.cs.wisc.edu (Douglas E. Quale)
Subject: Why the lisp machine is important to me (was Re: Information on DYLAN)
Organization: Undergraduate Projects Lab, UW Madison
Date: Mon, 27 Jul 1992 06:53:09 GMT

In article <HOPKINS.92Jul25163954@delta9.turing.ac.uk> hopkins@turing.ac.uk (Don Hopkins) writes:
>quale@saavik.cs.wisc.edu (Douglas E. Quale) writes:
>
>   gjc@mitech.com (George J. Carrette) writes:
>   >In article <691@data.rain.com>, kend@data.rain.com (Ken Dickey) writes:
>   >
>   >> [Seriously, there is a lot of deep stuff here.  But hardly unknown!]
>   >
>   >No deeper than MIT LISPMACHINE microcode and its operating system, 
>   >I can assure you. Lots of reinvention and re-syntaxing of previously 
>   >implemented stuff. 
>   >
>   >-gjc
>
>   I disagree.  Efficient implementations on stock hardware are a different
>   kettle of fish.  MIT Lispmachine microcode was a dead end.
>
>So are SPARC and MIPS machines, designed to run portable assembly
>languages like C.  
>
>	-Don

Time will tell, but they run some languages other than C pretty well too.

But seriously, my short statement was just a reaction to what I saw as
an offhand rejection of some good work, and I realize that it might itself
be taken as an offhand rejection of the good work done on the lisp machines.
Part of the problem is that very little of the lisp machine work has been
published.  (I think it is extremely disengenuous to claim that work is
reinvention of unpublished stuff.)  There are a couple MIT AI Memos, the
most notewothy of which is on GC.  David Moon wrote a few articles over the
years on Symbolics hardware.  I don't know of anything good published on
the history of Flavors, which is a shame because I think that some history
of the early OOP on the lisp machines would be very interesting.  Despite
this, Some reasons why the Lisp Machine is important to me:

It provided an early example of a good software prototyping environment.

The lisp language reached its modern form (a clearly recognizable ancestor
of CL).

Work on Flavors was important to lisp OOP.

It led to some fruitful work on GC.

It provided an excellent prototype for the workstation.  Single (sometimes
dual, I think) user machines, large semiconductor memory + VM, large
bitmapped display, mouse as a pointing device, and high-speed networking.
Sharing this distinction with work from Xerox Parc, I think this is the
LM's most important legacy.


In the last sense, a little bit of the lisp machine lives on in all of
today's workstations.
-- 
Doug Quale
quale@saavik.cs.wisc.edu
Newsgroups: comp.lang.scheme
From: bartlett@bartlett.pa.dec.com (Joel Bartlett)
Subject: Re: Scheme->C for the Macintosh
Reply-To: bartlett@decwrl.dec.com
Organization: DEC Western Research Lab
Date: Thu, 23 Jul 92 01:32:43 GMT

I don't know of any port of Scheme->C to the Mac.  I suspect most of the
difficulty in doing such a port would come in the fact that the Mac OS is not
UNIX like.  However, it is much easier to get Scheme->C up on your Sun. 
Besides
the basic Scheme->C release, you need the patch file put together by MCC.  Both
are to be found in pub/DEC/Scheme-to-C on gatekeeper.dec.com.

jfb
Newsgroups: comp.lang.scheme
From: blume@news@informatik.hu-berlin.de (Matthias Blume)
Subject: Re: Simplification
Originator: blume@euklid
Reply-To: blume@news@informatik.hu-berlin.de (Matthias Blume)
Organization: Humbolt University, Department of Computer Science
Date: Tue, 28 Jul 1992 08:11:47 GMT


In article <1992Jul25.115115.27145@wuecl.wustl.edu>, ppc1@cec1.wustl.edu (Peter Pui Tak Chiu) writes:
|> 
|> hi everyone,
|> 
|> i have a real naive question:
|> 
|>         how to do symbolic simplification using scheme, lisp or anything...?
|> 
|> what i mean is symbolic simplification like MATHEMATICA.
|> 
|> here are some examples:
|> 
|>           (* a (+ b (/ c a))) ==> (+ (* a b) c)
|>           (+ (* a b) (* a c)) ==> (* a (+ b c))
|> 
|> these are just very simple cases and are intended to explain what i mean...
|> i want to know a way to find the "simplest form" of any algebric expression.
|> not only those which are as simple as the above.
|> 
|> can anyone tell me how to do it or refer me to some books that talk about it?
|> 
|> thanks in advance
|> 
|> peter
|> 

At the moment I don't have a book at hand for advise.  But consider the following
remark:

There is no strict definition of what is simple.  For instance

(f(x) + g(x))^3

may be considered ``simple'' for its brevity, while

f(x)^3 + 3*f(x)^2*g(x) + 3*f(x)*g(x)^2 + g(x)^3

may be considered ``simple'' for the possibility to apply further operators like
INT(egral) or something like that.
In fact, simplification, whatever it means, is the most difficult part in every
formula manipulation system, so you cannot expect a quick, short and exhaustive
answer to your ``real naive'' question.

In fact, the trouble is not, how to do it in any particular programming language
(though LISP and Scheme are a good choice), but how to do it at all!

-- 
-- m.b
Matthias Blume, blume@informatik.hu-berlin.de,
Humboldt-Uni zu Berlin, FB 16 (Informatik), [Dept. of Computer Science]
From: rat@ruth.UUCP (David Douthitt)
Newsgroups: comp.lang.scheme
Subject: TI Scheme
Date: 28 Jul 92 01:44:06 GMT
Organization: Network XXIII - +1 608 238 6388


I purchased (yes PURCHASED!) a copy of TI Scheme not long ago..

I'd like to use it for some programming projects, but I'd really like to
be able to compile it into a releasable form - as in public domain
form.  Best I could tell, the FastLoad (fsl) formatted files still
required the full implementation of Scheme to run.  I couldn't find
any method that relied on libraries or a run-time.

I called TI and got bounced FOUR times at LEAST until I reached someone
(or two) who insisted that I could not have gotten this scheme (or should
not have been able to) and that support for this (obsolete) product would
cost me hundreds and hundreds of dollars, at some hourly rate just to
TALK to a technician.

Remind me never to buy another TI product again..... Never ran into such
a snobbish company before .....er... but then there's IBM.  Yet, their
tech support DID help me very well recently - and without megabucks.


--
UUCP: ....!remote.halcyon.com!ruth!rat  |  Network XXIII - +1 608 222 9253
InterNet: rat@ruth.UUCP                 |  32 Megs of Usenet/Fidonet programs!
==== Apple II Forever! ====             |  Files available more ways than
                                        |  any other BBS in America!
Files via: anon uucp, Fidonet FREQ, mail to archive-server@ruth.uucp, etc.
Newsgroups: comp.lang.scheme
From: wand@dec5120z.ccs.northeastern.edu (Mitchell Wand)
Newsgroups: comp.lang.scheme
Subject: Re: Readings [Re: Compilar Book]
Date: 30 Jul 92 19:16:31 GMT
Article-I.D.: dec5120z.WAND.92Jul30141631
Distribution: comp
Organization: College of Computer Science, Northeastern University

Richard W. Kreutzer writes:

   Can anyone recommend a comprehensive text on compilation techniques
   of Scheme?

You might also want to look at Peter Lee's book:  

@Book{Lee91,
  author = 	"Lee, Peter",
  title = 	"Topics in Advanced Language Implementation",
  publisher = 	"MIT Press",
  year = 	"1991",
  address = 	"Cambridge, MA",
}

--Mitch 

--
Mitchell Wand
College of Computer Science, Northeastern University
360 Huntington Avenue #161CN, Boston, MA 02115     Phone: (617) 437 2072
Internet: wand@flora.ccs.northeastern.edu          Fax:   (617) 437 5121
Newsgroups: comp.lang.scheme
From: oz@ursa.sis.yorku.ca (Ozan Yigit)
Subject: Re: Readings [Re: Compilar Book]
Organization: York U. Student Information Systems Project
	<1992Jul31.102728.954@msus1.msus.edu>
Distribution: comp
Date: Fri, 31 Jul 1992 20:26:24 GMT

f00020@TIGGER.STCLOUD.MSUS.EDU writes:

	[a repeat of my entire post elided]

	Are any of these reports available on the net anywhere? 
   Thanks.

Bartlett's SCHEME->C paper is available in the Scheme Repository
under /txt. I haven't seen the rest of the papers in machine readable
form, so you will have to ask their authors. If I get a hold of them,
I will place them under the repository.

oz
From: rat@ruth.UUCP (David Douthitt)
Newsgroups: comp.lang.scheme
Subject: GS Scheme
Date: 28 Jul 92 01:48:27 GMT
Organization: Network XXIII - +1 608 238 6388


Has anyone played with this?

If I could get my GS to come up... <sigh>... I might give it a shot.


--
UUCP: ....!remote.halcyon.com!ruth!rat  |  Network XXIII - +1 608 222 9253
InterNet: rat@ruth.UUCP                 |  32 Megs of Usenet/Fidonet programs!
==== Apple II Forever! ====             |  Files available more ways than
                                        |  any other BBS in America!
Files via: anon uucp, Fidonet FREQ, mail to archive-server@ruth.uucp, etc.
Newsgroups: comp.lang.scheme
From: kees@diku.dk (Kees Van Schaik)
Subject: IEEE R4 definition of Scheme, omission?
Date: Tue, 21 Jul 1992 12:19:06 GMT
Organization: Department of Computer Science, U of Copenhagen


  In the 

    "Revised 4 Report on the Algorithmic Language Scheme"

  there appears to be some inconsistency between the description of
  Definitions (section 5.2, page 12) and the Formal Syntax (section 7.1,
  pages 32-34).

  The description of the Definitions in section 5.2 (page 12) mentions the
  form:

    (define (<variable> . <formal>) <body>)

  as "non-essential" syntax, whereas the the grammar in section 7.1.5 (page
  34) does not accept this form.

  As there are several "non-essential" forms that are part of the grammar
  given in section 7.1 I would expect this to be an omission instead of
  something intentional. I would, however, like to know for certain whether
  it is, because I am making a parser for scheme that should adhere to the
  IEEE standard or at least document places where it does not.

  Is there anybody out there who can tell me?


	Kees