From: pryan@rp.CSIRO.AU (Philip Ryan)
Subject: Request for comparisons - Cadence/Mentor.
Followup-To: comp.lsi.cad
Keywords: comparison, Cadence, Mentor Graphics.
Organization: CSIRO Division of Radiophysics/Australia Telescope National Facility
Date: Wed, 11 Nov 1992 01:13:51 GMT


A comparison of Mentor Graphics and Cadence tools for IC design.
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My employer is looking at buying some brand new design tools for IC design,
and so I'm after some comparisons of the two main companies we would probably
invest our money in, namely Mentor Graphics and Cadence.

To give you some idea of where we stand, you're looking at a fairly compact
design effort -- we would probably have a few licenses for schematic entry, one
for simulation, and one for fault grading. We will be getting the foundry to do
the chip layout of course. The products will be standard cell and gate array
designs, with some FPGA work (probably Xilinx). Size in the low to mid 10s of
thousand gates is expected.

We are not total neophytes; there is someone new being hired who I believe has
done some designs, my supervisor has done a couple (semi custom GaAs), and 
I've designed one 15,000 gate chip. In addition there is an installed base of
Valid software, principally used in the past for circuit board design, though
it is going out of favour and will likely be dropped (in return for a "trade
in" from whomever sells us a system).


There was a recent post in comp.sys.mentor asking for help/info on Version 8.x
and I'm hoping that some of the replies for that post will be useful to me.

I do have a few areas that weren't mentioned in that post, especially because
I'm interested in comparing the Mentor product with Cadences.

The areas we'd like comparisons in are:

1)   Foundry support:
     
     Both in terms of libraries available, and ease of design flow when you
     send a data base in to a foundry. I assume foundries tend to have
     preferred paths ? Or at least paths of least hassle ? 

2)   Tool support:

     What is the level of support provided both in terms of information and
     assistance when getting started with the tools? How serious are they
     about getting bug fixes out? I assume the standard response from both is
     "that's not a bug, it's been documented", but perhaps one is better?

3)   Quality of the software:
              
     i)   ease of use,
     ii)  the interface -- is it carefully thought out?
                        -- are the tools integrated ?
                        -- is there good inter-process communication ?
     iii) documentation -- well written, and organised ?
                        -- is it actually useful ?

4)   Simulation:

     We have received conflicting reports from the Cadence and Mentor agents
     as to problems with each others simulator. Is it true that Quicksim II
     has some bad problems with gate capacity, is slow and requires scads of
     memory? Is Viewlogic an overpriced and outmoded simulator which is not as
     widely supported by foundries? Which one will make our girlfriends
     happier about our working hours?

     How do the respective simulators sit with the schematic entry programs ?
     Things like point and click links between nets on the schematic and traces
     in the simulator window appeal.

5)   Learning curves:

     Which system will have us up to speed and doing real work the soonest?

     I realise this is also closely linked to the quality of the documentation
     and the interface. Personally I'm already biased on this, having done
     one chip with Mentor (version 7) and (recently) being forced to migrate
     to Valid and start a chip design with it. I've found the Valid gear quite
     poorly documented, haphazardly arranged (both docs and the interface), and
     overall just hard to get the hang of. I had a much better time learning
     how to use the Mentor. (Although I must admit there are some features of
     the Valid software which weren't present with Mentor and whcih I've found
     very useful.)

     However, I have not had the chance to use Mentors Version 8, nor have I
     used Cadences offering (composer & verilog). So I don't know.

6)   Miscellaneous.

     One other thing which is of interest is how peacably the tools live with
     X windows. Perhaps it's a local problem, but I have noticed with Valid a
     tendency for some windows to STEAL my cursor when I was typing away in
     another window. God forbid!

     It's possible that the Cadence tools and Mentors version 8 might have
     similar quirks,  and we'd like to hear about them too.

     We have also had some quite keen approaches from a Viewlogic dealer.
     Actually, an agent for ES2 who would like us to use Viewlogic and an ES2
     design kit for our chip work. Has anyone had any experience with these?


Is there something I've left out but should be considering ? If you think so,
please tell me.


If you do have some views on these points (and preferably some experience
using the tools) I would quite appreciate hearing from you. The best possible
review would be from someone who has done a chip or two using both platforms.
:-) But I don't think I'll hold my breath for something so fortuitous.


I read the groups I've posted this to (and will be reading much more carefully
for the next week or two) so feel free to post, but I will gratefully take
direct mail and summarise it for the net if there's interest. (I don't mean
that I'll just cat it all together and repost it.)

Thank you for reading this far (it was long wasn't it?), and thanks in advance
for any comments you can send.

Philip Ryan.
pryan@rp.csiro.au

PS: those aren't spelling mistakes where you think I've used 's' by mistake
instead of 'z'. They're for real -- we spell (and speak) differently to the
way they do in America. ;-)

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Newsgroups: comp.lsi.cad