From: robert@metropolis.com (Robert Munyer)
Subject: Re: 040 caching
Organization: Metropolis Software, Inc.
Date: Thu, 23 Jul 1992 06:46:30 GMT


In article <1992Jul22.025300.10797@news.columbia.edu>
gmw1@cunixa.cc.columbia.edu (Gabe M Wiener) writes:

> Can someone explain exactly what is going on when a program "trips over" the
> 040 cache?

People will try to tell you that the problem is caused by self-modifying code,
but that's not the whole truth.  The problem happens any time the processor
tries to execute code at ANY location that has recently been modified, unless
the cache has since been flushed.  It doesn't matter who modified the location.

The problem is that the processor funnels data from ONE memory address space
through TWO caches, and these two caches do not automatically communicate with
each other when they need to.  Because the caches don't handle the situation
automatically, the programmer has to do it manually.  But of course, in some
cases, the program was written BEFORE the 68040 was designed!

                          +-----------------+
                     _____|Instruction Cache|____
                    /     +-----------------+    \
          +---+    /                              \    +------+
          |CPU|---<                                >---|Memory|
          +---+    \         +----------+         /    +------+
                    \________|Data Cache|________/
                             +----------+

Let's say the CPU (actually, the program that is running in the CPU) wants to
save a machine-language routine into the memory starting at location 2E30A6,
and then later on it wants to run that routine.  When the CPU is saving the
routine, it sends the data to the Data Cache.  On the 68030, the Data Cache
will immediately send these data on through to the memory, because the 68030
has a "write-through" cache.  On the 68040, the Data Cache does NOT immediately
send the data on through -- it waits until it "feels like it".  When the CPU
tries to execute the routine at location 2E30A6, it reads the data through the
Instruction Cache.  Now, if this happens before the Data Cache has "gotten
around to" sending those data on through to the memory, the CPU will be getting
the data that USED TO BE THERE instead of the data that are SUPPOSED TO BE
THERE NOW.  Most likely the user will see "Sorry, a system error occurred".

The 68030 also has two separate caches that do not communicate automatically,
but on the 68030 the Data Cache is "write-through" so this problem does not
occur.  There is a similar problem that DOES occur on the 68030, but it only
happens if the CPU tries to
     (1) execute a location, and
     (2) modify that location, and
     (3) execute that location again.
(Remember that on the 68040, just doing number 2 and number 3 will cause a
crash, even without ever doing number 1).  This 68030 situation is probably the
source of the belief that "self-modifying code" is what causes the problem.

> Does the 040 cache have any relation to the external cache that can be added
> in the PDS slot?

Not in this case.  The PDS cache cards have only ONE cache, and there is no
"back way" for the CPU to get to the memory without going through the cache, so
there is no way for the data to get "out of sync".  Now, if you had TWO cache
cards, and they didn't communicate with each other, and the CPU chose between
them more or less at random, THEN you'd have a similar problem.  Peripherals
which use DMA might cause a similar problem with cache cards, but that's
"beyond the scope of this discussion 8^)".

> Why does this problem not manifest itself on IIci's with cache cards?

See above.

> Apparently there is some sort of Apple CDEV that can be used to turn the 
> 040 cache on and off.

I think the Apple one requires you to reboot whenever you turn the cache on or
off.  There's a better control panel device (called CacheOut, I think) that can
turn it on and off automatically whenever you (or your system) switches from
one application to another.

By the way, before somebody corrects me, I should mention that on the 68040
the Instruction Cache and the Data Cache are INSIDE the processor chip.  In my
diagram above, when I said "CPU" I meant the central processing unit in the
chip, not the whole chip.

Sorry this is a bit long winded.  I hope at least it's easy to understand.

______________________________________________________________________
Robert Munyer            |   "I may be synthetic, but I'm not stupid."
robert@metropolis.com    |      -- Bishop, _Aliens_
Disclaimer: this does not necessarily represent the views of my employer.