From: ananth@wet.COM (Sekhar Ananthakrishnan)
Newsgroups: misc.jobs.resumes
Subject: MSEE seeking a position in hardware/VLSI desgin.
Date: 27 Jul 92 17:44:22 GMT
Distribution: usa
Organization: Wetware Diversions, San Francisco

Dear Sir/Madam:

I am interested in a position in VLSI/hardware design related 
to parallel computing. I have recently completed my master's
degree in Electrical Engineeing from Louisiana State University,
Baton Rouge. My major field of study was computer engineering. 
During the course of my master's program the main focus of my 
course work and research has been in the area of hardware/VLSI
design for parallel computing and fault tolerant computing.  
 
My master's thesis titled "Reliability Evaluation of Multistage 
Interconnection Networks with Multimode Failures" presents 
techniques to evaluate the performance of various interprocessor 
communication networks. As a result of my work on this project 
I have an excellent understanding of design issues and concepts
involved in parallel/ fault tolerant computing.

I have authorization to work in the United States and 
am willing to relocate to any part of the country. If you 
would like further information, please call me at (415)-474-4457. 

Thank you for your consideration.

 
                                          Sincerely,
                                          
                                          Sekhar C. Ananthakrishnan    

------------------------------------cut here----------------------------
                     

                           Sekhar C. Ananthakrishnan
                              1563 Lombard Street
                            San Francisco, CA 94123
                               Phone 415-474-4457
                            e-mail: ananth@wet.uucp

OBJECTIVE     A Design Engineering position in VLSI/hardware related to 
              parallel computing.

EDUCATION     Master of Science in Electrical Enginering
              Louisiana State University - May 1992
              Major: Computer Engineering 
                  
                Master's Thesis: Reliability Evaluation of Multistage 
                Interconnection Networks with Multimode Failures.

              COURSES:

              *VLSI Systems Design           *Digital Computer Design
              *Structure and Design          *Operating Systems
               of Digital Systems
              *Reliable Design of            *Neural Networks
               Digital Systems                  
              *Parallel Processing and       *Microprocessor Based Systems
               Parallelizing Compilers        Design
              *Design and Analysis of        *Principles of Parallel
               Parallel Algorithms            Processing
              *Structure of Computers
               Computations 

              Bachelor of Engineering
              University of Madras, India-August 1989
              Major: Electronics and Comminication

PROJECTS      * Evaluated the  performance of Fault Tolerant Multistage  
                Interconnection Networks with Multimode Failures. 
                Developed efficient algorithms for various reliability   
                measures of these networks while considering degraded 
                mode of network components. (Master's Thesis)

              * Evaluated the performance of Hypercube and Mesh  based 
                Multicomputers. Studied the graceful degradation of  		
                hypercube and mesh based multicomputers and computed 
                the task based reliability to establish if a degraded
                system could complete a given task. Performed  
                simulations to verify the accuracy of the computations.

	      * Designed a 40 pin integrated circuit for pattern matching 
                of alphanumeric characters represented by 7 bit ASCII 
                code. Designed the IC using systolic arrays and 
                implemented the design using CMOS technology. Designed the
                layout and performed simulations for this chip using CAD 
                tools.

              * Developed software for the implementation of the D   
                Algorithm for detection of stuck-at-faults in digital logic
                circuits.Thesoftware was designed to read circuit 
                specifications and fault location and generate a test input
                sequence that would enable fault detection at the specified 
                location.

              * Implemented a Neural Network using Feedback and Delta  
                learning algorithms for storage of binary patterns. Also 
                developed a back propogation neural network as a classifier
                system to map specified inputs to specified outputs. Also
                implemented the Adaptive Resonance Theory for pattern 
                recognition using feedback neural networks.

COMPUTER      Languages:            C, C++, Pascal, Assembly (68000, 8086)
SKILLS        Operating Systems:    Unix (BSD and SunOS), MS-DOS  and 
                                    VAX-VMS
              Computer Systems:     Encore Multimax, Sun and DEC
                                    Workstations, IBM PC compatibles 
                                    and Apple Macintosh.
              Graphic Environment:  Suntools, DEC windows, MS Windows, 
                                    X Windows. 
              CAD Tools:            MAGIC, Esim


WORK          * Graduate Research Assistant 
HISTORY	        Department of Electrical and Computer Engineering
                Louisiana State University, Baton Rouge
                May 1991-August 1991

                 Worked on a research project involving the reliability   
                 and performance evaluation of Multistage Interconnection 
                 Networks and Hypercubes.

                 Developed algorithms for the computation of reliability 
                 of interconnection networks while considering multimode 
                 failures.

                 Researched the existing techniques for computation of  
                 reliability of interconnection networks and algorithms 
                 for multimode failure analysis of various systems.
		
              * Technical Assistant
                Library Systems, University of Maryland, College Park
                May 1990-August 1990
                
                 Installed and maintained the library computers and the 
                 library network

              * Industrial Training
                Digital Instruments and Controls, Inc. 
                Madras, India
                November 1988-Januray 1989                
                
                 Designed and implemented a port sharing network to   
                 facillitate access to shared resources by different 
                 terminals.

              * Summer Internship
                Software Division, Rail India Technical and Economic
                Services 
                New Delhi, India.
                June 1988-July 1988
                
                 Worked on various software projects.

REFERENCES    Available on request