HDTenEightyP/NetNews huggingface dataset:
From: anadeem@ampere.comp.graphics.research (Ahmed Nadeem)
Newsgroups: comp.lang.idl
Subject: Edge Detection And Segmentation Using Khoros And PV-WAVE Software
Date: 27 Jan 93 08:16:40 GMT
Article-I.D.: ampere.ANADEEM.93Jan27011640
Distribution: comp.lang.idl
Organization: /home/ampere1/anadeem/.organization

Netters,
        I am currently working on a research project that involves generating
solid or geometric models from MRI images. Part of the procedure will require 
me to possibly perform Thresholding & Edge Detection on my MRI images in order
to find out which pixels lie on boundaries between two different regions. 
Thus, I would like to have an Image Processing Software package that has good 
Edge Detection and Classification ( Segmentation ) modules/routines.  
        I have heard a lot about Khoros ( University Of New Mexico) and 
PV-WAVE (Precision Visuals) and was curious if other professionals or students
had any experience on how good they are for the above purposes. Suggestions 
on other software packages are also much welcome.
                                                       Thanks,
                                                              Ahmed Nadeem
Newsgroups: comp.lang.idl
From: Patrick McClaughry <patrick_mcclaughry@sematech.org>
Subject: Definitive text on IDL
X-Xxmessage-Id: <A7840DF8CB02160E@manzana.eng.sematech.org>
X-Xxdate: Thu, 21 Jan 93 14:23:20 GMT
Organization: SEMATECH
X-Useragent: Nuntius v1.1.1d17
Date: Thu, 21 Jan 1993 14:20:40 GMT

Could someone please email or post references to texts
on IDL.  If this is a FAQ, sorry.
Thanks,
--Pat
From: anadeem@ampere.comp.graphics.research (Ahmed Nadeem)
Newsgroups: comp.lang.idl
Subject: MRI And CT-SCAN Images Of Dogs?
Date: 27 Jan 93 08:15:10 GMT
Article-I.D.: ampere.ANADEEM.93Jan27011510
Distribution: comp.lang.idl
Organization: /home/ampere1/anadeem/.organization

Netters,
      I am currently working on a research project that involves construction 
of realistic, solid or geometric models for dogs.
      Does anyone know where I can get serial section images( MRI, CT-SCAN, 
etc ) for dogs?
                                                       Thanks,
                                                              Ahmed Nadeem
From: cliffc@tekeda.PEN.TEK.COM (Clifford E Cummings)
Newsgroups: comp.lang.verilog
Subject: Re: Verilog code for Inverted, Open collector, Output Enable Bus
Keywords: Inverted, Open collector, Output Enable Bus
Date: 21 Jan 93 20:53:48 GMT
Organization: Tektronix, Inc., Beaverton,  OR.

In article <C17p8K.7nA@iphase.com> phan@iphase.com (Tai Phan) writes:
>If anyone knows a simple way to describe in Verilog an Open collector, 
>Inverted, with Output enable bus, please help.  The parameters are as follow:
>
>// Verilog code
>
>input [31:0] inp;               // Input bus
>input oen_;                     // Output enable
>output [31:0] outp_;            // Output bus
>
>// When oen_ is 1, outp_ should be 32'hzzzzzzzz
>// when oen_ is 0, outp_ is 0 if inp is 1, and z if inp is 0 (OC inverted)
>// For single bit, I have the code that works:
>
>wire [31:0] outp_;
>assign outp_[31] = (~oen_ && inp[31]) ? 'b0 : 'bz;
>assign outp_[30] = (~oen_ && inp[30]) ? 'b0 : 'bz;
>.......
>and so on
>
>Thanks,
>
>Tai Phan
>--------
>Interphase Corp.
>(214) 919 9000
>phan@iphase.com

Is this what you are looking for? (this example can be run)

`timescale 1ns/100ps
module oc_bus( outp_, inp, oen_);
  // Verilog code
  input [31:0] inp;               // Input bus
  input oen_;                     // Output enable
  output [31:0] outp_;            // Output bus

  triand (strong1, highz0) [31:0] outp_ = (~oen_ ? ~inp : 32'bz);

endmodule

module oc_bus_test;
  reg  [31:0] inbus;
  reg         busen_;
  wire [31:0] outbus;

  oc_bus b1( outbus, inbus, busen_);

  initial
  $monitor("inbus = %h | busen_ = %h | outbus = %h \n",
      inbus, busen_, outbus,
      "                               (binary)= %b \n", 
      outbus);

  initial begin
    #000 inbus = 32'hffff0000; busen_ = 1'b1;
    #100 inbus = 32'h0000ffff; busen_ = 1'b0;
    #100 inbus = 32'h00ff5500; busen_ = 1'b0;
    #100 $finish;
  end
endmodule

Regards - Cliff Cummings - cliffc@tekeda.pen.tek.com
Newsgroups: comp.lang.verilog
From: phan@iphase.com (Tai Phan)
Subject: Verilog code for Inverted, Open collector, Output Enable Bus
Followup-To: phan@iphase.com
Summary: Inverted, Open collector, Output Enable Bus
Keywords: Inverted, Open collector, Output Enable Bus
Organization: Interphase Corporation, Dallas Texas
Date: Thu, 21 Jan 1993 16:17:07 GMT

Greetings,

If anyone knows a simple way to describe in Verilog an Open collector, Inverted,
with Output enable bus, please help.  The parameters are as follow:

// Verilog code

input [31:0] inp;               // Input bus
input oen_;                     // Output enable
output [31:0] outp_;            // Output bus

// When oen_ is 1, outp_ should be 32'hzzzzzzzz
// when oen_ is 0, outp_ is 0 if inp is 1, and z if inp is 0 (OC inverted)
// For single bit, I have the code that works:

wire [31:0] outp_;
assign outp_[31] = (~oen_ && inp[31]) ? 'b0 : 'bz;
assign outp_[30] = (~oen_ && inp[30]) ? 'b0 : 'bz;
.......
and so on
But this takes a lot of space, and typing. I want to use one or two lines
to describe the entire 32 bits bus.

Thanks,

Tai Phan
--------
Interphase Corp.
(214) 919 9000
phan@iphase.com


-- 
Tai Phan  X218
phan@iphase.com
Xref: sparky comp.lang.verilog:507 comp.arch:12364
From: dank@blacks.jpl.nasa.gov (Daniel R. Kegel)
Newsgroups: comp.lang.verilog,comp.arch
Subject: Free Xilinx Simulation Interface for Verilog
Date: 22 Jan 93 18:48:41 GMT
Organization: Image Analysis Systems Group, JPL
NNTP-Posting-Host: blacks.jpl.nasa.gov

A free Xilinx to Verilog interface program is available for anonymous 
ftp from punisher.caltech.edu in pub/dank/xnf2ver.tar.Z.

This program is not really ready for prime time, but I thought I'd 
make the sources available (with the permission of M J Colley) so
others could play with & possibly improve it.
I think I made it a lot more solid than it was, but it still can't handle
real world designs yet.

Here's part of the README:

		  XNF to Verilog Translator

			M J Colley
		Department of Computer Science
		    University of Essex
		      Wivenhoe Park
		        Colchester
		      Essex CO4 3SQ
		           UK

		email: martin@essex.ac.uk

Disclaimer:

This program was written by a postgraduate student as part of his M.Sc
course, it was designed to form part a larger system operating with the
Cadence Edge 2.1 framework. This should be bourne in mind when considering
the construction and/or operation of the program.

Warrenty:

This source code is provided with NO warrenty whatsoever. It is left up to
the user to satisfy themselves that the output produced is correct.

Copyright:

The source code is copyright of the Department of Computer Science, University
of Essex, UK. You are free to use and/or modify the code to your own needs. You
are asked to inform the copyright holder should you distribute this code to a 
third party.

Contents:

This archieve contains the following:

  The XNF to Verilog translator source code and makefile.
  Verilog models for the D_FF and LATCH flipflops used by the translator.
  CLB and IOB timing data file.
  SED scripts for setting the model timing and the script generator program.
  A postprocessor to set the delay timing of the nets.

...
Newsgroups: comp.lang.verilog
From: guillaum@pogo.trl.OZ.AU (Andrew Guillaume)
Subject: Verilog books
Followup-To: comp.lang.verilog
Keywords: reference
Reply-To: a.guillaume@trl.oz.au
Organization: The Okefenokee Swamp
Date: Fri, 29 Jan 1993 04:53:21 GMT


G'day !

I have a feeling this may be a faq, but I haven't seen a faq list, so here
goes:

I have just started with Cadence's Verilog-XL, and the least I can say about
the reference manual is that it is far from being helpful. I would like to
know from the Verilog experts out there what books (reference, and users
guide, introductory and advanced stuff) can be recommended. Full information
would be very welcome, so that I may order the books asap, and get going.

Thanks in advance

Andrew Guillaume
TRL, Melbourne, Australia
a.guillaume@trl.oz.au
Newsgroups: comp.lang.verilog
From: tobin@btree.uucp (Roy Tobin)
Date: Thu, 21 Jan 93 18:13:49 GMT
Organization: Brooktree Corporation
Subject: Request for information on a verilog mode for GNU Emacs
Distribution: na

I am interested in finding out if someone has written a verilog mode
for GNU Emacs, similar to c-mode.  I know of such a mode for VHDL, but
my interest lies in Verilog.

 Roy L. Tobin                   Brooktree Corporation
 UUCP: ..!ucsd!btree!tobin      9950 Barnes Canyon Road
 Net: btree!tobin@ucsd.edu      San Diego, CA  92121-2790       (619)
535-3537
From: patel@key.amdahl.com (Chandresh Patel)
Newsgroups: comp.lang.verilog
Subject: Re: Verilog code for Inverted, Open collector
Date: 22 Jan 93 21:43:55 GMT
Reply-To: patel@key.amdahl.com
Distribution: world
Organization: Amdahl Corporation, Advanced System Division

In article 8369@tekig7.PEN.TEK.COM, cliffc@tekeda.PEN.TEK.COM (Clifford E Cummings) writes:
> In article <C17p8K.7nA@iphase.com> phan@iphase.com (Tai Phan) writes:
> >If anyone knows a simple way to describe in Verilog an Open collector, 
> >Inverted, with Output enable bus, please help.  The parameters are as follow:
> >

Stuff deleted...

> Is this what you are looking for? (this example can be run)
> 
> `timescale 1ns/100ps
> module oc_bus( outp_, inp, oen_);
>   // Verilog code
>   input [31:0] inp;               // Input bus
>   input oen_;                     // Output enable
>   output [31:0] outp_;            // Output bus
> 
>   triand (strong1, highz0) [31:0] outp_ = (~oen_ ? ~inp : 32'bz);


I believe it should be:

triand (highz1, strong0) [31:0] outp_ = (~oen_ ? ~inp : 32'bz);


> 
> endmodule
> 
> module oc_bus_test;

Stuff deleted...

> endmodule
> 
> Regards - Cliff Cummings - cliffc@tekeda.pen.tek.com




---
Chandresh Patel			Amdahl Advanced Systems, Fremont CA
patel@key.amdahl.com


Newsgroups: comp.lang.verilog
From: jcooley@world.std.com (John Cooley)
Subject: Joining ESNUG
Organization: The E-mail Synopsys Users Group (ESNUG)
Date: Thu, 21 Jan 1993 05:44:07 GMT


  If you're using the Synopsys Design Compiler and/or their ATPG product, you 
  might be interested in joining the E-Mail Synopsys Users Group (ESNUG).

  What we are is a group of hardware designers from all over the world who
  wish to trade experiences, bug reports and the techniques that we've
  found that work best in getting a design from a behavioral description
  to a final fully tested product.  This is a grassroots forum independent
  of Synopsys, Inc.

  A Sample of What We Discuss:

	- Known Synopsys Compiler Bugs    - Implementing Boundry Scan

	- Mentor related issues    - EDIF related issues

	- Hierarchical Compliations   - design_analyzer   - JTAG

	- How Various ASIC Vendors Model Their Macros.   - Clock Constraints

	- Using ATPG Tools   - The Best Way To Write State Machines in Verilog

	- Using VHDL   - System Simulation vs. Synopsys Friendly Code

	- Clever Workarounds to Known Pitfalls   - Testing Strategies

  In order to insure an open discussion, but yet keep our respective managers
  happy in having our company's projects remain SECRET, submissions to be 
  posted to the ESNUG mailing list can be stripped of identifying engineers 
  and company names if so requested.

  In addition, to further secure privacy and to avoid e-mail headers that
  are hundreds of names long, each mailing is a batch of singlely addressed 
  e-mail letters.

  If you want to join ESNUG, please send me e-mail to "jcooley@world.std.com"
  saying you wish to join and why.  (Please don't send a copy of this letter
  back to me, I know what you're refering to when you're writing.)

					- John Cooley
					  ESNUG Moderator

 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
     /o o\  /  it's a FEATURE!"   |    Backup Address: jcooley@miracle.com
    (  >  )                       |              (508) 429-4357
     \ - /       |   Snail Mail: P.O. Box 6222, Holliston, MA 01746-6222
     _] [_       |     "This here ain't no one's opinion 'cept my own."
From: hunt@squid.Eng.Sun.COM (Jim Hunt)
Newsgroups: comp.lang.verilog
Subject: Books on Verilog
Date: 27 Jan 1993 03:49:17 GMT
Organization: Sun
Distribution: usa
NNTP-Posting-Host: squid

I think I saw it here once before, but since it is always changing...

What is currently the best book to learn Verilog from.  I know there
are several new ones out, and haven't had time to read any.  Is there
someone who is teaching Verilog who has an informed opinion on this.

As always, send mail, I'll sumarize in a week or so.

And no, even though I did it myself long ago, I don't think reading
the manual is a good way to learn verilog. :-)

-- 
jim hunt@Eng.Sun.COM		Yeah, well, disclaim THIS!
From: shome@eeserv.ee.umanitoba.ca (Tapas Shome)
Newsgroups: comp.lang.verilog
Subject: Best possible Verilog Reference: Also software Harddware co-design
Summary: Need reference fro verilog, and co-design.
Keywords: Co_design, verilog
Date: 27 Jan 93 06:22:55 GMT
Organization: University of Manitoba, Winnipeg, Canada

I Must thank all of those who responded to my previous posting.
I however need further assistance.

What is the best possible verilog reference. I have the Moorby text.

Also is there any text book on hardware and software-co-design
that stresses the use of verilog.
In general what is the best possible reference for co-design
which can be used for complex project. 
Note this issue of IEEE computer has  one page info,
" Hardware-software codesign: what is needed for Success?"
P.A. Subramanyam. Hand out from the First International Workshop
on Hardware-Software codesign, Sponcered by ACM and IEEE, Estes Park, Colo, 1992.

I will appreciate all openions.

Tapas.

Shome@eeserv.ee.umanitoba.ca

--
Parallel Systems are easier to built than to use them---- MIT. 
E_mail: (Tapas Shome )shome@eeserv.ee.umanitoba.ca, tshome@ccu.umanitoba.ca
AIM: Ordnung ist das halve Leben. Arbeit macht Ordnung.
Newsgroups: comp.lang.scheme
From: oz@ursa.sis.yorku.ca (Ozan Yigit)
Subject: Re: Unspecified values in R4RS
Organization: York U. Student Information Systems Project
	<OZ.93Jan22114638@ursa.sis.yorku.ca> <1jpf3e$2m1@agate.berkeley.edu>
Date: Fri, 22 Jan 1993 22:40:29 GMT

Brian Harvey writes:

| 	..I was arguing that, e.g., DISPLAY should be required to return
| a nonprinting value, instead of "unspecified" as the standard now says.
| Right now if you write a program like

| (define (praise thing)
|   (display thing)
|   (display " is great!") )

| you get interactions like

| > (praise "Ice cream")
| Ice cream is great!#f

| which is not what you wanted.

But if you want trivial interactions such as these to work as you would
like them to, you may just as well do something like what David Kelsden
sent me the other day:

   (define void (string->symbol ""))

   (define (praise thing)
     (display thing)
     (display " is great!")
     void)

Is this not easier than changing the whole language definition? ;-)

... oz
From: gjc@mitech.com (George J. Carrette)
Newsgroups: comp.lang.scheme
Subject: Re: Unspecified values in R4RS
Date: 25 Jan 93 13:11:07 GMT
Organization: Mitech Corporation, Concord MA

In article <1jp5n7$nm@agate.berkeley.edu>, bh@anarres.CS.Berkeley.EDU (Brian Harvey) writes:
> ...  If we don't know by now, then it doesn't matter, and you
> might as well humor me!  :-)

How would you go for this set of return values:

(define ..)   => #<return-value-of-define>
(display ...) => #<return-value-of-display>
(set! ...)    => #<return-value-of-set!>





Newsgroups: comp.lang.scheme
From: hanche@ams.sunysb.edu (Harald Hanche-Olsen)
Subject: Re: Unspecified values in R4RS
Organization: University at Stony Brook, NY
	<1jukvoINNgis@columbia.cs.ubc.ca>
	<JAFFER.93Jan24154351@montreux.ai.mit.edu>
Date: Sun, 24 Jan 1993 22:26:49 GMT

>>>>> In article <JAFFER.93Jan24154351@montreux.ai.mit.edu>, jaffer@zurich.ai.mit.edu (Aubrey Jaffer) writes:

 > Multiple values are looking like they will be included in R5RS.
 > Unfortunately, the following langage appears in the proposal:

Is a draft of r5rs available?  Any indication which way the low-level
macro stuff is moving?

- Harald
From: jaffer@zurich.ai.mit.edu (Aubrey Jaffer)
Newsgroups: comp.lang.scheme
Subject: Re: Unspecified values in R4RS
Date: 24 Jan 93 20:43:51 GMT
	<1jukvoINNgis@columbia.cs.ubc.ca>
Organization: M.I.T. Artificial Intelligence Lab.

In article <1jukvoINNgis@columbia.cs.ubc.ca> manis@cs.ubc.ca (Vincent Manis) writes:

   Yes!!! This has a number of pedagogical advantages, not least of which
   is that it makes clear the difference between an expression (evaluated
   primarily for value) and a command (evaluated only for effect). For
   proficient programmers, this isn't a big deal, but for beginners it's
   essential. 

   I like the Chez Scheme approach. There's a void type, with only a single
   value. The procedure (void) yields this value, and (void? x) is a
   type-checking predicate. This is a simple, clean, approach, and is quite
   compatible with existing Schemes. (If your Scheme doesn't have an
   #unspecified, you can always use a gensym.) Apart from this, the only
   other change which has to be made is to have the top level print nothing
   when the result is void.

Multiple values are looking like they will be included in R5RS.
Unfortunately, the following langage appears in the proposal:

  Except for continuations created by the CALL-WITH-VALUES procedure,
  all continuations take exactly one value, as now; the effect of
  passing no value or more than one value to continautions that were
  not created by the CALL-WITH-VALUES procedure is unspecified (as
  indeed it is unspecified now).

If this language were weakened to allow those continuations which
ignore the returned value to receive either 0 or 1 values, then (VOID)
could be replaced by (VALUES).  The read-eval-print loop could then
print all the values it receives (sometimes none).

I think it might also be worthwhile that an implementation make all
the procedures which currently return unspecified values return 0
values and check for using missing values.
From: drcc@chuma.ec.usf.edu. (David Cabana (MTH))
Newsgroups: comp.lang.scheme
Subject: Re: Where I can find IEEE P1178 standard?
Date: 24 Jan 93 12:44:40 GMT
Organization: Univ. of South Florida, College of Arts & Sciences

In article <1993Jan21.113805.3467@news.cs.indiana.edu> chaynes@cs.indiana.edu (Chris Haynes) writes:
>In article <C1732H.8BB@dei.unipd.it> gandalf@sabrina.dei.unipd.it (ROBERTO AVANZI) writes:
>>I believe you can FTP a draft of the [IEEE standard]
>>from nexus.yorku.ca, or from
>>some other scheme repository. It is not the final text (it is called p1178d4)
>>but it's very close, and I've been told there's almost no difference.
>>Hope this helps
>>Roberto
>
>IEEE (like other standards organizations) explicitely proscribes the
>distribution of standard drafts, electronically or otherwise, after
>publication of the standard.  This keeps folks from believing they have the
>standard when they don't. 

I think IEEE could come up with a checksum or some other method of
digital authentication if they chose to.  They just want some of your
money before letting you have a copy of the standard.

		drcc@chuma.csc.usf.edu
  
Newsgroups: comp.lang.scheme
From: droth@silver.ucs.indiana.edu (David Roth)
Subject: Re: gambit compiler??
Organization: Indiana University
Date: Mon, 25 Jan 1993 20:59:13 GMT

In the README file that comes with the source code for the compiler, it
says:
"Note that the system is distributed with a pre-built version of the
interpreter.  If you want the icon to appear and would like to be able
to automatically open the interpreter when you double-click ".scm" and
".O" files, you should do the following:

Using ResEdit (or similar program), you should change the creator of
"MacGambit Interpreter" to "gaml" and set the bundle bit.  Also, you
should copy the following resources from the pre-built "MacGambit
Interpreter" into the newly created one:

ICN# BNDL FREF gaml"


So...should I do this with the compiler also?

And also, is there a postscript file available for the online help files
for MacGambit?  I have the R4RS file already, and only need the
MacGambit-specific material.


Thanks!!


David Roth
droth@silver.ucs.indiana.edu

PS.  MacGambit IS a great system!  Much much much better than
MacScheme...
Thanks to the creators!
Newsgroups: comp.lang.scheme
From: peschko@kelp.micro.umn.edu (Edward Peschko)
Subject: compiler for Sun 4's (compiler.com)
Organization: University of Minnesota, Minneapolis: Under Grad Workstation Lab.
Date: Fri, 22 Jan 1993 06:28:58 GMT

hello --

I was wondering where I could get a copy of the compiler.com world image file
for my copy of scheme --- so I could actually make binaries instead of having
to run through the interpreter all the time.

Thanks much...

Ed
Newsgroups: comp.lang.scheme
From: blume@kastle.Princeton.EDU (Matthias Blume)
Subject: Re: Unspecified values in R4RS
Reply-To: blume@kastle.Princeton.EDU (Matthias Blume)
Organization: Dept. of Computer Science, Princeton University
Date: Sat, 23 Jan 1993 17:38:00 GMT

In article <1jqqjc$b4p@agate.berkeley.edu>, bh@anarres.CS.Berkeley.EDU
(Brian Harvey) writes:
|> oz@ursa.sis.yorku.ca (Ozan Yigit) writes:
|> >But if you want trivial interactions such as these to work as you would
|> >like them to, you may just as well do something like what David Kelsden
|> >sent me the other day:
|> >
|> >   (define void (string->symbol ""))
|> >
|> >   (define (praise thing)
|> >     (display thing)
|> >     (display " is great!")
|> >     void)
|> >
|> >Is this not easier than changing the whole language definition? ;-)
|> 
|> *You* can write programs like that, and *I* can write programs like
|> that, but *my students* are going to fall into any pitfalls that the
|> language leaves in their path.

Oh!  I had a better opinion about Berkeley students...  If you tell them that
the Scheme system responds by printing the result of an expression *every*
time and if you show them your little ``praise'' example to see the
problem they should get it immediately.  Your ``pitfall'' is really not
such a big deal to justify changes to the language!

|> 
|> I'm not suggesting that an entirely pitfall-free language is possible
|> or desirable, but this particular pitfall (stupid return values from
|> commands called for effect) seems to be easily avoidable and to have
|> no redeeming features.

The ``redeeming'' feature has a name: orthogonality.  One of the major
advantages (in terms of simplicity) of Scheme was that everything has a
value.  To invent ``unspecified values'' is just the same as re-inventing
the distinction between commands and expressions.  Once we have this doesn't it
appear to be a nasty pitfall if we are still allowed to write ``commands'' in
``expression'' contexts.  No, we are not moving toward ML -- we will
probably end up with Pascal!

-Matthias
From: secrist@msdsws.enet.dec.com (Strong datatypes for weak minds.)
Newsgroups: comp.lang.scheme
Subject: Mini-Scheme ?
Date: 21 Jan 93 03:00:42 GMT
Organization: Digital Equipment Corporation


Anybody have a cut-down Scheme smaller than SIOD or SCM that would
fit, without overlaying, into 64K on a microprocessor ?

How about "parallel" Schemes (i.e. many microprocessors, gray-code
serial-linked, etc.) ?

Regards,
rcs

Newsgroups: comp.lang.scheme