From: gaetano@cs.washington.edu (Gaetano Borriello)
Subject: Int'l Conference on CAD, ICCAD93 (CFP: papers due 4/12/93)
Organization: Computer Science & Engineering, U. of Washington, Seattle
Date: Tue, 26 Jan 93 17:04:35 GMT

           IEEE/ACM International Conference on CAD-93

                        November 7-11, 1993
                          Santa Clara, CA


                    ****  CALL FOR PAPERS  ****


The 1993 INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN will be
held November 7-11, 1993.  ICCAD is oriented towards Electrical
Engineering CAD professionals, concentrating on CAD for Electronic
Circuit Design.  It is sponsored by the	IEEE Circuits and Systems 
Society, the IEEE Computer Society/DATC, and the Association for 
Computing Machinery/SIGDA.

                     **  AREAS OF INTEREST  **

Original technical papers on (but not limited to) the following topics
are invited:

1)	COMBINATIONAL LOGIC SYNTHESIS:  Two-level and multi-level
	logic optimization (area, timing, power), FPGA optimization,
	BDD techniques, don't care methods, technology mapping

2)	SEQUENTIAL LOGIC SYNTHESIS:  Finite state machine-synthesis,
	FSM decomposition, sequential optimization (e.g., retiming), 
	asynchronous design, formal verification

3)	HIGH-LEVEL SYNTHESIS, VERIFICATION:  Pipeline, memory system
	and DSP synthesis; scheduling, allocation, synthesis systems, 
	high-level synthesis for test, binding

4)	TIMING MODELING, ANALYSIS AND OPTIMIZATION:  Delay modeling,
	timing estimation including path sensitization and false path 
	analysis, clocking optimization, area-power-delay trade-off
	scenarios 

5)	ANALOG MODELING, SIMULATION AND SYNTHESIS:  All aspects of
	circuit simulation, modeling issues for simulation, analog
	synthesis 

6)	PROCESS AND DEVICE MODELING AND SIMULATION:  New device
	models, process simulation, yield analysis manufacturability 

7)	DISCRETE SIMULATION:  Switch, logic and high-level modeling
	and simulation 

8)	ROUTING AND LAYOUT VERIFICATION:  Routing for IC, PCB and
	multichip substrates, DRC, ERC, circuit extraction/verification, 
	symbolic design and compaction 

9)	PLACEMENT AND FLOORPLANNING:  Placement, floorplanning,
	partitioning, area estimation, module generation, layout
	systems, cell layout, MCM physical design issues, performance
	driven layout

10)	BIST and DFT:  Hardware techniques to improve testability,
	analysis of BIST/DFT schemes, partial and boundary scan 

11)	ATPG and GENERAL TEST:  ATPG, delay fault testing, general
	test issues, fault simulation

12)	FRAMEWORKS AND CAD SYSTEMS:  Tool integration, design
	representation, user interfaces, databases, design languages,
	case, design management, total CAD systems

13)	ISSUES IN SYSTEM DESIGN:  Hardware/software co-design, system
	partitioning, design for manufacturability, CAD tools for
	advanced systems, CAD tools for concurrent engineering, tools
	for advanced systems


                **  AUTHOR INFORMATION AND FORMAT  **

Authors should submit:

* 1 cover page including:
	- Title of paper.
	- The category 1-13 that most closely matches the paper's content.
	- Complete name, return address, telephone number, fax number 
		and affiliation of each author.
	- Clear identification of the corresponding author.
	- Papers will be reviewed anonymously.  ONLY the cover page
		should identify the authors and their affiliations.

* 10 copies of one page abstract
	- Abstract, typed on separate page should state clearly and 
		precisely what is new and point out the significant
		results.  The IMPACT, or potential impact, of the
		contribution will play a major role in evaluation.

* 10 copies of the completed paper not to exceed 20 pages, double-
   spaced, figures, tables and references included.
	- Papers exceeding 20 pages or previously published
		will be returned to the authors.  THIS INCLUDES
		WORKSHOP PROCEEDINGS.  For further information send
		a one-line email message to:  icpubpap@dac.com
	- Authors should objectively address the significance
		of their contribution as demonstrated through
		theoretical advances, algorithmic/heuristic advantages
		tested on "real" examples, and objective comparisons
		to existing techniques.


*** SEND TO:	ICCAD-93 Publication Department
		MP Associates, Inc.
		7490 Clubhouse Rd., Suite 102
		Boulder, CO  80301
		telephone:  303/530-4562


Proposals for Panel Sessions and Tutorials are invited.  Please send 
complete proposals including the participants to the Program
Chairperson.


                     **  AUTHOR'S SCHEDULE  **

Deadline for submissions:	Postmarked  April 2, 1993
Notification of acceptance:		    July 5, 1993
Deadline for final version:		    August 9, 1993



GENERAL CHAIRPERSON:
Michael Lightner
University of Colorado
CB 425
Dept. of E & C Engineering
Boulder, CO  80309
303/492-5180
fax:  303/492-2758
email:  lightner@boulder.colorado.edu


PROGRAM CHAIRPERSON:
Jochen Jess
Eindhoven Univ. of Tech.
Den Dolech 2
Postbus 513
5600 MB Eindhoven, The Netherlands
+31-40-473353
fax:  +31-40-464527
email:  jess@es.ele.tue.nl


PUBLICATIONS CHAIRPERSON:
Richard Rudell
Synopsys, Inc.
700 E. Middlefield Rd.
Mountain View, CA  94043
415/962-5000
fax:   415/965-8637
email:  rudell@beeblebrox.synopsys.com

Newsgroups: comp.lang.verilog