From: drk@cs.washington.edu (Daniel Kerns)
Newsgroups: misc.jobs.resumes
Subject: MSCS+6 years exp; C,C++,Lisp,assm.; Compiler/Architecture low level; relocatable
Date: 23 Aug 92 21:50:22 GMT
Distribution: misc
Organization: The University of Washington, Seattle WA 98195, USA


Dear Prospective Employer:

I am searching for a challenging R&D position in an area related to the
interface between computer architecture's and their operating systems and
compilers. In addition to the Master of Science degree that I will earn in
August, my qualifications come backed with over five years of solid
industrial experience and numerous internships.

My current research area is the computer architecture/compiler domain. The
last two years have been spent working on an instruction scheduling
problem. The technique I developed is designed to take advantage of the
uncertain memory latencies that future computers will have. It works by
measuring the instruction level parallelism in a block of code and then
scheduling loads taking into consideration the average amount of
parallelism in the code. The result is better performance when memory
latency is changing. In order to validate our claims, my technique, called
Balanced Scheduling, was implemented within the framework of the GNU GCC
compiler. Before working on this compiler project I had two internships
with Thinking Machines working on RAID I/O systems and CM2 microcode. My
most recent full time positions saw me working on unusual UNIX kernel
issues for Multiflow Computer and managing microcode development for a
super minicomputer at Data General.

My resume does not mention some of the usual things like: "I've used UNIX
and C++." I have all of these skills and more. What is more important is
that I am a versatile person who is not going to be scared off by something
new or daunting.

I look forward to talking with you in the next few weeks.

	Thanks

		Dan Kerns

----------------------------------------------------------------------

                        Daniel R. Kerns

6379 NE Radford Drive		       	 Home: (206)525-6149
Seattle, WA 98115		         Work: (206)543-5118
				         Internet: kerns@cs.washington.edu

POSITION DESIRED:

A position designing, implementing and maintaining complex software and
hardware systems. The ideal position would utilize skills relating to the
interactions of hardware, applications, operating systems and compilers.

EDUCATION:

The University of Washington, 1988 - 1992.
Master of Science - Department of Computer Science and Engineering, September 1992.

    Research interests: Compilation for parallel architectures, Parallel
    Programming and Parallel Computer Architecture.  Thesis: Balanced
    Scheduling - Managing uncertain latency.

Rochester Institute of Technology, 1979-1983
Bachelor of Technology, 1983
Systems Software Science - School of Computer Science

    Concentration: Operating Systems and Compilers.

High School: The American School of the Hague 1976-1979

PROFESSIONAL WORK EXPERIENCE:

Development Engineer, Multiflow Computer, Branford, CT 06405.
December 1986 - September 1988

Member of the Operating System Kernel Group.  Responsible for porting TRACE
UNIX (BSD 4.3) to the Multiflow TRACE 14 and TRACE 28 VLIW processors.
Responsible for the Virtual Memory System and the processor support
``microcode.'' In Multiflow processors, the macroinstruction length varies
from 256 to 1024 bits in length.  There are 720 general registers to
context switch.  As many as 16 individual memory operations may be in
progress simultaneously.  Some of the problems involved in supporting an
operating system on the Trace include efficient context switching, virtual
memory management and management of the variable instruction widths.
Designed and implemented an Interprocedural Optimizer which optimizes
procedure calls and rewrites the object code for higher performance.
Designed and implemented a specialized simulator that statically searches
for processor resource violations. Worked extensively in the field on
Beta-test machines and benchmarking.  Some exposure to sales and marketing.

Senior Hardware Engineer, Data General Corporation, Westborough, MA.
April 1986 - November 1986

Responsible for the architecture of a future (never manufactured)
generation of highly parallel Data General processors.  Specifically
architecture development. This included specification of the RISC-style
processor, Memory, IO Systems, Compiler and OS support necessary to produce
a well balanced machine. In addition to guiding the CPU groups efforts, my
responsibilities included coordination of both Operating Systems and
Language Development.

Hardware Engineer II, Data General Corporation, Westborough, MA
April 1984 - April 1986

Wrote all of the Privileged and System Microcode of the MV/20000 including
Virtual Memory and I/O.  Became responsible for MV/20000 microcode and tool
development.  Was managing three microcoders through the final 1-1/2 years
of the project.  Designed the DG implementation of Tightly Coupled
Multiprocessors. Coordinated OS implementation and Hardware Scheduling.
Implemented (along with a hardware designer) DG's first multiprocessor.  A
Dual MV/4000 that was used for OS and Diagnostic Development.  High
exposure to DG Operating System internals.  Designed and implemented the
software to support MV/20000 lab debug. This includes numerous tools that
enable the engineers to effectively use the prototypes.  Specifically
microcode assemblers, simulators, design rule checkers, disassembler and an
unique microcode compaction tool.

Received the ``Directors Award for Outstanding Contribution'' for my
MV/20000 work and the Multiprocessor effort.  Multiprocessor implementation -
Patents applied for.

Hardware Engineer I, Data General Corporation, Westborough, MA
April 1983 - April 1984

Initial responsibility at DG was to implement a microarchitecture simulator
for the MV/20000.

ACADEMIC WORK EXPERIENCE:

Graduate Student Intern, Thinking Machines Corporation, Cambridge, MA 02142
January through March 1990.

Designed and implemented new features for the Data Vault RAID storage
system. These techniques (a new access method) substantially increased disk
throughput for applications that searched large data bases. The assignment
involved writing and modifying code at all levels of the Connection Machine
System Software.

Graduate Student Intern, Thinking Machines Corporation, Cambridge, MA 02142
July through September 1989.

Designed and implemented a diagnostic test suite for a new type of
macroinstruction set being added to the Connection Machine (CMIS).  My
personal goal for the summer was to get exposure to massively parallel
architectures and computation.

Research Assistant, The University of Washington, Seattle, WA 98195
April 1990 - August 1992
September 1989 - December 1989

During this time, my research focused on ways to effectively schedule
instructions for machines where memory latency is uncertain.  Secondary
focus on high performance computer architecture and programming languages.

Graduate Staff Assistant, The University of Washington, Seattle, WA 98195
September 1988 - June 1989

The responsibilities of a GSA include answering and resolving user problems
with the Computer Science Department's computing resources.  Taught several
introductory courses for new students unfamiliar with the timesharing
environment that the department uses (UNIX).  These included: UNIX Program
Development Tools and The UNIX Networking environment.

TEACHING:

Teaching Assistant, University of Washington
January - March 1991.  Computer Science 501 (Graduate level compilers).

Instructor, University of Washington Extension
April - June 1989 and October - December 1989.  Introduction to UNIX.

OTHER EXPERIENCE:

City of Seattle, 1992 - Public Service.

Chairman, Transportation Advisory Citizens Team - Advises the City on
transportation issues.  Member, Seattle Bicycle Advisory Board - Advises
the City on bicycle issues.

Sykes Datatronics, Rochester, NY

10 months during '81 - '83  (Co-op employment)

Developed a machine (SMDR/Canada) that costs and bills telephone calls by
monitoring the output of a PBX.

Tenneco Walker Europe, BV, Amselveen, The Netherlands.

Summer '79 and '80 (Co-op employment).  Developed international financial
software.

Rochester Institute of Technology

Part-Time '79 - '83.  Programming Consultant, Grader, Timesharing
Consultant and Computer Operator.

J.I. Case (Europe), BV, Leiden, The Netherlands.

Summer '78.  General Programmer.  Marketing simulation group.

PERSONAL INFORMATION:

	Birth date: August 1, 1961; Married; United States Citizen
--
				Dan Kerns	drk@cs.washington.edu
				Univ. of Washington, Computer Science
Newsgroups: misc.jobs.resumes