From: provo_b@kosmos.wcc.govt.nz (Bart)
Newsgroups: sci.electronics
Subject: RE: 68HC11 input capture code wanted?
Date: 22 Jan 1993 06:36:19 GMT
Organization: Wellington City Council (Public Access), Wgtn, Nz
Reply-To: provo_b@kosmos.wcc.govt.nz
NNTP-Posting-Host: kosmos.wcc.govt.nz

>From: geoffrey@cosc.canterbury.ac.nz (Geoff Thomas)
>Date: Tue, 19 Jan 1993 04:05:27 GMT
> I'm wanting to write some code for the HC11 Input Capture system, and
> I'd like to get hold of some examples.

Following are some *extracts* from my HC11 code to sense wall distances
on my ultrasonic wall sensing micromouse.  The circuit diagrams can be
found in my NELCON'92 paper:
 "Robotic Control and Sensing, an HC16 application."
 NELCON'92 Proceedings, August 1992, pp 81-88.  
There will be copies at the Dept. of EEE at Canterbury Uni.

Refer 68HC11 data book or Reference Manual M68HC11RM/AD for meaning
of undefined labels  or bit mask values, (standard HC11 acronyms have
been used).

The code uses the HC11 TOC (Timer Output Compares) 1,2,3,4,5 to generate
the 4 orthogonal sonic sense pulse gates, which are synchronised to an HD6340
generated ultrasonic drive signal.  TOC1 is used to turn ON the selected
pulse gates, whilst TOCs 2,3,4,5 turn them off after the desired burst time.
TOC 2,3,4,5 interrupts are enabled, and their service routine enables return
pulse capture and prepares TOC1 for the next pulse, if any.

* Task specific equates: Note: S_Gn = Sonic Gate north - front looking pulse.

SGn .equ   OC1D6 ; Assert S_Gn to 1 on TOC1| Data bits to assert outputs
SGs .equ   OC1D5 ; Assert S_Gs to 1 on TOC1| OC2 thru OC5.
SGe .equ   OC1D4 ; Assert S_Ge to 1 on TOC1| Register: OC1D
SGw .equ   OC1D3 ; Assert S_Gw to 1 on TOC1| Clear immediately after Pulse(s)

--- relevant RAM locations ----
         ...
N_time  .rmb 2 ; Pulse return time, ex TIC2, front wall.
S_time  .rmb 2 ; Pulse return time, ex TIC1, back wall.
Son_Act .rmb 1 ; TOC action bits.  Set to action sonic pulses.
Son_Rpt .rmb 1 ; Sonic pulse repetition period, to nearest ms <= 63.
         ...

--- Interrupt initialization:
           ...
Front_Back LDX   #REG_CON    ; point to HC11 control bit & register bank.
           BSET  TCTL2-REG_CON,X,EDG1A+EDG2A ; capture on rising edges
           BCLR  TCTL2-REG_CON,X,EDG1B+EDG2B ; ensure other bits zero.
           BCLR  TMSK1-REG_CON,X,IC2I+IC3I   ; ensure interrups off.

           LDX   #TIC_IRQ    ; Redirect PROVON interrupts for TICs 2,3.
           STX   TIC1VC      ; [PROVON = Provo's Monitor for 6800 series]
           STX   TIC2VC      ; for front/back pulse interrupts
           ...

--- After pulse(s) have been sent - Turn on TIC interrupts in HC11.
--- THIS SECTION IS part of SUBROUTINE Pls_End which is accessed by the
--- TOC interrupt service routine which runs at the end of the usonic pulses.
          ...
back_on   BRCLR Son_Act,SGs,front_on
          BSET  TMSK1-REG_CON,X,IC1I ; enable back, south, sense interrupt
front_on  BRCLR Son_Act,SGn,walls_on
          BSET  TMSK1-REG_CON,X,IC2I ; enable front, north, sense interrupt

walls_on  BSR  Rpt_Calc ;Check update TOC repeat time? Ret: Z=1 if no repeats.
          CLC           ;IF Z=1, indicate no repeating ie Return with Z,C=1,0.
          BEQ  PE_Quit  ;Exit if Rpt_Tim is zero
          LDD  Rpt_Tim  ;Else get TOC update interval and go update TOC1 etc.
*                       ;& Fall into Son_repit.
*********
*   Son_Repit is Subroutine to fire up next sonic burst after time interval
*   in D
[ultrasonic burst has pulse period and burst length tuned to suit either 
 wall follow or long distance scan] 

--- TIC interrupt routines:

TIC_IRQ:   LDX  #REG_CON ; point to HC11 device register bank.
                         ; Timer Input Capture interrupt service routines
*--------------------------------------------
* TIC_IRQ checks flags on return pulse inputs.
*   If Son_Act flags set, then check return flags.
*       IF ( flag set and capture time <= Max ) Dir_Time = capture time
*        ELSE Dir_time = $0000
*   Else capture time not updated.

           LDY  #$0000
Tst_SGn    BRCLR Son_Act,SGn,Tst_SGs ; North wall-sense enabled?
           STY   N_time              ; Yes, default it incase!
           BRCLR TFLG1-REG_CON,X,IC1F,Tst_SGs  ; If flag clear, check South!
           INY                       ; - indicate valid TIC IRQ
nth_off    LDAA  #IC1F               ; clear North flag!
           STAA  TFLG1-REG_CON,X
           BCLR  TMSK1-REG_CON,X,IC1I ; and disable North interrupt

           LDD   TIC1-REG_CON,X   ; flag was set, get bounce time
           SUBD  Son_BEG0         ; subtract pulse start time
           CPD   #Maxscan         ; If too long,
           BGT   Tst_SGs          ;   default it!
           STD   N_time           ; store value - represents front distance.

Tst_SGs    BRCLR Son_Act,SGs,TIC_Fin ; South wall-sense enabled?
           STY   S_time
           BRCLR TFLG1-REG_CON,X,IC2F,TIC_Fin ; Problem if flag clear!!
           INY                       ; indicate a valid IRQ.
sth_off    LDAA  #IC2F               ; clear South flag!
           STAA  TFLG1-REG_CON,X
           BCLR  TMSK1-REG_CON,X,IC2I ; and disable south interrupt

           LDD   TIC2-REG_CON,X
           SUBD  Son_BEG0         ; subtract pulse start time
           CPD   #Maxscan         ; is time value excessively large?
           BGT   TIC_Fin
           STD   S_time           ; save 'distance' to rear wall.

TIC_Fin    CPY  #0                ; if zero then no IRQs found, spurious.
           BNE   TIC_end
           LDX  #bad_TIC          ; point to error message "TIC?"
           LDAB  TFLG1            ; get Timer flags, see if Input capture??
           JSR   Print_it         ; print flags and message
           JSR   CRLF
TIC_end    RTI

TOC_IRQ:                    ; Accessed AFTER pulses, NOT by TOC1 !.
           JSR   Print_Son  ; development assist in tuning sonic pulses
           JSR   Pls_End    ; Pls_End will fix all!
           RTI              ; Pls_End a subroutine to assist debugging.

As it is always useful to have 'online' chats with experienced practitioners
of the art, I suggest you may like to contact Peter Kell, Senior Lecturer
at the Dept. of Electrotechnology, Christchurch Polytechnic.  He teaches 
microprocessor hardware and Software Engineering and has designed and
developed an HC11 training unit for teaching, (refer his paper in NELCON'92
Proceedings, "Microcontroller Training towards 2000", pp 139p-145. I am most
impressed with his work and hope to obtain a class set of his units to
support our teaching.
------------------------------------------------------------
> Also, how can I get in contact with the HC11 mailing list?

I have *NOT* had anything from the HC11 list for some time now, since about
the time Bob Wier moved to another site.  Does it still exist somewhere in
net-land?? 

Regards, Bart.
Bart Provo    |provo_b@kosmos.wcc.govt.nz |School of Electronic Engineering
PO Box 47-105 |access via: PC/AT+modem on |Central Institute of Technology
TRENTHAM      |home phone, (answer phone) |Private Bag 39-807
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Newsgroups: sci.electronics