HDTenEightyP/NetNews huggingface dataset:
From: izahi@bsc.no (Raul Izahi Lopez Hernandez)
Newsgroups: comp.lsi.cad
Subject: Re: VLSI CAD for IBM PC needed.
Date: 9 Apr 92 07:22:22 GMT
Organization: Bergen Scientific Centre, Bergen, NORWAY

In article <2APR199212211063@vxcrna.cern.ch> bialas@vxcrna.cern.ch (BIALAS,Wojtek) writes:
>I am student of Faculty of Electronics at Technical University in 
>Cracow, Poland, Europe. I am searching for CAD software for
>VLSI design that would run on IBM PC AT (386,486...). As I am at
>educational site , may be there exist free software . Does anyone
>can help me ? 
>Any help on software for VAX Station 3100 is also needed.
>
>Thanks in advance,
>
>Wojtek Bialas
>
>email :  "bialas@vxcern.cern.ch" or
>         "wbialas@vsk07.ifj.edu.pl" 
>	Ither# 192.86.14.08

If you do an anonymous ftp to

	gatekeeper.dec.com

and then 
cd to pub/comp.sources.unix

you will find all sorts of tools there as well as in other comp.sources
directories there.

Best wishes
-- 
Raul Izahi Lopez	IBM Bergen Environmental Sciences and Solutions Centre
izahi@bsc.no
From: agarwal@dadd.ti.com (Suresh Agarwal)
Newsgroups: comp.lsi.cad
Subject: test for cfp
Date: 15 Apr 1992 15:57:28 -0500
Organization: CS Dept, University of Texas at Austin
NNTP-Posting-Host: cs.utexas.edu

Please ignore.  This is only a test
Newsgroups: comp.lsi.cad
From: dataram@tigger.jvnc.net (Dataram Corp. PO Box 7528)
Subject: Schematic Conversion
Originator: dataram@tigger.jvnc.net
Organization: JvNCnet, Princeton University, NJ
Distribution: usa
Date: Mon, 13 Apr 1992 12:03:41 GMT

We need to convert about 10 Viewlogic schematics to Cadence/Valid GED
schematics. I understand the by using the EDIF schematic packages
from each company that this could be done. IS THERE A CHEAPER WAY???
The libray parts are the same for each design (Actel). If you have
any ideas, please send e-mail.
                                   Thanks,
                                     Chuck Staatse

-- 
**********************************************************
* Chuck Staatse       Dataram Corp.  609-799-0071 x 284  *
*  chuck@dataram.jvnc.net |  chuck@dataram.com           *
**********************************************************
Newsgroups: comp.lsi.cad
From: mdick@acns.nwu.edu (Matthew S. Dick)
Subject: Software for timing diagrams
Organization: Northwestern University, Evanston, Illinois
Date: Mon, 6 Apr 1992 17:08:26 GMT

Hi, I'm looking for a piece of software to create, modify, and display/print  
circuit timing diagrams.  If anyone knows of such a program please email me.

matt dick
msd@casbah.acns.nwu.edu
From: karplus@cse.ucsc.edu (Kevin Karplus)
Newsgroups: comp.lsi.cad
Subject: Re: Clarification - Multi-level Synthesis o/p mis ....
Date: 15 Apr 92 04:06:43 GMT
Reply-To: karplus@ce.ucsc.edu (Kevin Karplus)


Somnath Viswanath asks:        
 
   I want a multi-level netlist in terms of primitives e.g.  AND/OR/NOT
   that mis generates JUST PRIOR TO TECHNOLOGY MAPPING as I want to
   compare with another TECHNOLOGY MAPPING ALGORITHM I DO NOT WANT TO
   COMPARE AGAINST MIS DECOMPOSITION/FACTORING OR ANY OTHER
   PRE-PROCESSING ALGORITHMS THAT MIS TECHNOLOGY MAPPER USES.

   I also do not want to just create a library of AND/OR/NOT and use the
   mapper to give me a netlist - that would defeat the purpose of my
   comparison. Ideally I would like to start with the same set of
   expressions/equations that mis TEHCNOLOGY MAPPING PHASE operates upon.

Unfortunately, the question asks for something that doesn't exist.
MisII's internal form is not a multi-level netlist in terms of primitives,
it is a network of arbitrary gates.  Conversion to primitives would
require some form of decomposition or mapping, and as Somnath
observes, this decomposition will affect the results.

The term "technology mapping" gets used for many different things.
I prefer to use it just for the covering of a fine-grain network with
legal gates in the target technology, and not include the
decomposition into a fine-grain network.

Now, it is possible to get at the fine-grain network that misII
generates for tech mapping (I believe you can get it with the
tech_decomp command).  Unfortunately, this network may not be at all
suitable for other technology mappers, since it consists entirely of
2-input NANDs (or NORs) and inverters.

Comparing different technology mappers is dificult, because the
starting point makes a big difference, and optimizer scripts are usually
tuned to work well with one particular mapper.

Starting with the further handicap that the technology mapper accepts
only primitive gates in the inputs, makes it diffcult to find an
optimizer that will produce acceptable input files (without doing its
own technology mapping).

The ITEM system can be forced to put out its internal format (oops, I
take that back---it doesn't in the released version), but this
wouldn't help much, as its internal format uses 2-1 muxes rather than
primitive gates.  In fact, ITEM does not (yet) have a mapper to
primitive gates.

It is currently almost impossible to compare bare technology
mappers---about the best we can do is compare
"decomposition+technology mapper".  In fact, many of the recent
technology mapping papers for table-lookup FPGAs have rather similar
mapping algorithms, with most of the differences in the decomposition
(and the interaction between the decomposition and delay estimates).

Kevin Karplus
From: rose@src.honeywell.com (Fred Rose)
Newsgroups: comp.lsi.cad
Subject: timing analysis tools
Date: 8 Apr 92 19:34:54 GMT
Article-I.D.: src.1992Apr8.193454.23239
Organization: Honeywell Systems & Research Center



 I am evaluating timing analysis and transmission line analysis tools. I
understand that Quantic and Quad are the leading candidates, now that Swiftlogic
has gone belly up. I am interested in doing boards and chips. I want a nice
integration with Mentor also. If anyone has experience, recommendations, etc.
I would appreciate it. I'll post a summary if I get enough responses

Thanks in advance
Fred


---------------------------------------------------------
Fred Rose                            
Honeywell Systems and Research Center
MS-2100                    e-mail: rose@src.honeywell.com            
3660 Technology Dr.        Phone : (612) 782-7106
Minneapolis, MN 55418      Fax   : (612) 782-7438
-- 
---------------------------------------------------------
Fred Rose                            
Honeywell Systems and Research Center
MS-2100                    e-mail: rose@src.honeywell.com
From: kimsa@atlantic.cps.msu.edu (Sang Chul Kim )
Newsgroups: comp.lsi.cad
Subject: seeking for a technology library
Date: 7 Apr 92 03:44:16 GMT
Distribution: usa
Organization: Dept. of Computer Science, Michigan State University
Originator: kimsa@atlantic.cps.msu.edu


    Is there a cell library which contains gates such that there 
  are MULTIPLE templates (in other word, choices) for each gate 
  type (for example, 2 input XOR gate) ?
  For a gate type, all its templates differ in area, delay, etc.

  Any technology and any data format is OK. Any hint about where to
  get such a library will be greatly appreciated.

  Sincerely Yours,

  S. KIM
From: sviswan@eos.ncsu.edu (SOMNATH  VISWANATH)
Newsgroups: comp.lsi.cad
Subject: Clarification - Multi-level Synthesis o/p mis ....
Keywords: Multi-level Synthesis, mis
Date: 11 Apr 92 15:30:34 GMT
Organization: North Carolina State University


        Thanks for the ideas, just a clarification -

        I want a multi-level netlist in terms of primitives e.g.
 AND/OR/NOT that mis generates JUST PRIOR TO TECHNOLOGY MAPPING as I
 want to compare with another TECHNOLOGY MAPPING ALGORITHM I DO NOT
 WANT TO COMPARE AGAINST MIS DECOMPOSITION/FACTORING OR ANY OTHER
 PRE-PROCESSING ALGORITHMS THAT MIS TECHNOLOGY MAPPER USES.
        I also do not want to just create a library of AND/OR/NOT and
 use the mapper to give me a netlist - that would defeat the purpose of
 my comparison. Ideally I would like to start with the same set of
 expressions/equations that mis TEHCNOLOGY MAPPING PHASE operates upon.

                        thanks,

                                        somnath viswanath
Newsgroups: comp.lsi.cad
From: harry@neuron6.jpl.nasa.gov (Harry Langenbacher)
Subject: Re: Plotting Magic Layouts on HPGL/Postscript Devices?
Keywords: Magic, HPGL, Postscript
Organization: JPL Pasadena CA
Date: Mon, 6 Apr 1992 19:26:45 GMT

In article <1992Apr6.043510.28004@ccu1.aukuni.ac.nz> rgbowmkr@ccu1.aukuni.ac.nz (Richard Bowmaker) writes:
>Does anyone out there know of a program or method for plotting Magic
>layouts on HPGL or Postscript Devices ? I just need the plots for
>documentation, and a Versatec is somewhat out of our league.
>

this is my favorite:

-From: christos@theory.TC.Cornell.EDU (Christos S. Zoulas)
-Subject: CIF to color and bw PostScript filter available
-Date: 8 Nov 91 05:33:58 GMT
-We have modified Arturo Salz's pplot program to output color PostScript
-from CIF files. The source is available from :
-    tesla.ee.cornell.edu:/pub/cad/pplot.tar.Z
-Christos Zoulas         | 389 Theory Center, Electrical Engineering,
-christos@ee.cornell.edu | Cornell University, Ithaca NY 14853.
-christos@crnlee.bitnet  | Phone: (607) 255 0302, Fax: (607) 255 9072

also
>Article 959 of comp.lsi:
>Subject: Plotting Magic/Cif (summary)
>Date: 30 Nov 89 20:33:53 GMT
>Reply-To: rph@cs.brown.edu ()
>
>Here's a summary of plotting programs people have written
>me about:  thanks to all those that let me know about them
>
>cif2ps  version 2 (Gordon W. Ross, MITRE):
>	a much better version of cif2ps, extending the code
>	of cif2ps (Marc Lesure, Arizona State University) and
>	cifp (Arthur Simoneau, Aerospace Corp).  It features
>	command line options for depth and formatting.  Can
>	extend one plot over several pages (up to 5 by 5, or
>	25 pages). By default, uses a mixture of postscript gray fill
>	and cross-hatching.  
>
>	It was posted to comp.sources.misc,
>	and is available by ftp from uunet.uu.net(192.48.96.2) as:
>	comp.sources.misc/volume8/cif2ps.Z.
>
>flea    Edward Allen Luke, Mississippi State University
>	Does line drawings with crosshatching for postscript,
>	versatec, and hp plotters.  Many options (depth, label
>	depth, scale, path, format...) and probably easy to
>	modify for other devices.
>
>	Available by ftp from zeus.ee.msstate.edu in 
>	pub/flea.tar.Z.
>
>vic     Part of the U. of Washington's Northwest Lab, for Integrated
>	Systems Cad Tool Release (previously UW/NW VLSI Consortium).
>	Does postscript and HP pen plotters.  
>	Only available as part of the package, and I haven't tried it.
>	Contact Vicky Palm (palm@june.cs.washington.edu) for more
>	information on the entire set of tools.

-- 
Harry Langenbacher 818-354-9513 harry%neuron6@jpl-mil.jpl.nasa.gov
Neuroprocessing & Analog Computing Devices Group, FAX 818-393-4540
JPL,  M/S 302-231, 4800 Oak Grove Dr, Pasadena CA 91109        USA
From: kimsa@atlantic.cps.msu.edu (Sang Chul Kim )
Newsgroups: comp.lsi.cad
Subject: seeking for a technology library
Date: 7 Apr 92 03:46:46 GMT
Distribution: usa
Organization: Dept. of Computer Science, Michigan State University
Originator: kimsa@atlantic.cps.msu.edu


    Is there a cell library which contains gates such that there 
  are MULTIPLE templates (in other word, choices) for each gate 
  type (for example, 2 input XOR gate) ?
  For a gate type, all its templates differ in area, delay, etc.

  Any technology and any data format is OK. Any hint about where to
  get such a library will be greatly appreciated.

  Sincerely Yours,

  S. KIM
Newsgroups: comp.lsi.cad
From: burra@sun1.coe (Gangadhar Burra)
Subject: MAGIC-HPGL
Organization: Texas Tech
Date: Thu, 16 Apr 1992 19:10:51 GMT

Is there anyway I can get HPGL plots out of Magic or CIF files? It
does not matter how convoluted the procedure may be, so long as I can
reach the final objective.

Any help would be deeply appreciated.

Gangadhar.
From: jon@alpha.ee.ufl.edu (Jon Mellott)
Newsgroups: comp.lsi.cad
Subject: Logic Automation, behavioral models
Keywords: Logic Automation
Date: 12 Apr 92 19:20:32 GMT
Organization: EE Dept at UF

Is there anybody out there using Logic Automation behavioral models
with Valid (Cadence) RapidSim? Please e-mail.

Jon Mellott
Newsgroups: comp.lsi.cad
From: dataram@tigger.jvnc.net (Dataram Corp. PO Box 7528)
Subject: Re: seeking for a technology library
Originator: dataram@tigger.jvnc.net
Organization: JvNCnet, Princeton University, NJ
Distribution: usa
Date: Tue, 7 Apr 1992 12:15:19 GMT

We are currently looking at adding Spice capabilities to our
VALID/Cadence Sparc Stations. The two packages that seem to
come up are PSpice and HSpice. Could someone who has used both
packages, please comment on their experience.
            Thanks
                Chuck


-- 
**********************************************************
* Chuck Staatse       Dataram Corp.  609-799-0071 x 284  *
*  chuck@dataram.jvnc.net |  chuck@dataram.com           *
**********************************************************
Xref: sparky comp.lsi.cad:511 alt.cad:182
From: chinatti@phoenix.Princeton.EDU (Stephen A. Chinatti)
Newsgroups: comp.lsi.cad,alt.cad
Subject: downloading xilinx from PC
Date: 13 Apr 92 22:36:43 GMT
Organization: Princeton University
Originator: news@ernie.Princeton.EDU

I was wondering if anyone on these groups has experience downloading the
bitfile for a xilinx XC4003 chip (or any 4000 series, I guess) from the cable
for the PC (or other machine).  I am working on a project using the new
xilinx chips, and so far have been unable to successfully wire the 5 pin cable
to the 4003.  It appears that the cable has the following 5 connections:
                      _
     Din            D/P           CCLK        Vcc    GND
  (data in)  (done/not prog) (config clock)  

I have played around with several different connection schemes, with no
success as of yet.  Usually, I get an error while downloading that 
"DONE didn't go high" after it sends the bitfile to the chip.
The documentation for the XC4003 contains many different configurations for
downloading bitfiles, but it doesn't show any configurations with this 
exact cable.  There is no documentation available here on the cable
itself, and no one here has done downloading onto the 4000 series from the PC.
If anyone has any experience with this, or knows of someone else that can help
me, PLEASE let me know.  

	Thanks in advance,
	Steve C
-- 
Steve Chinatti, EMTA <internet:chinatti@phoenix.Princeton.EDU> 
EECS student, Princeton University, Princeton, NJ           
Newsgroups: comp.lsi.cad
From: harry@neuron6.jpl.nasa.gov (Harry Langenbacher)
Subject: Encapsulated postscript for magic/cif plots ?
Keywords: magic cif encapsulated postscript
Organization: JPL Pasadena CA
Date: Wed, 15 Apr 1992 22:48:20 GMT

I'm posting for someone else, but I'd like to know too:

>I noticed your post about pplot and went to grab it from Cornell,
>hoping that it would solve all my problems in my attempts to produce
>magic output for inclusion into latex documents.
>
>Well, pplot does a better job at producing ps files than flea or
>cif2ps does, but it still doesn't give me eps files.
>
>Do you know of a good method for incorporating magic files into latex
>documents? 
>
>
>...
>--douglas
>
>BTW: There is a utility called ps2epsf that I tracked down using
>archie. This might be what we're looking for, but I haven't had the
>time to compile it yet. It uses ghostscript and pbmplus to generate
>the correct bounding box on the ps file.
>
>
> Douglas Yarrington                                 yarri@ee.eng.ohio-state.edu
>
-- 
Harry Langenbacher 818-354-9513 harry%neuron6@jpl-mil.jpl.nasa.gov
Neuroprocessing & Analog Computing Devices Group, FAX 818-393-4540
JPL,  M/S 302-231, 4800 Oak Grove Dr, Pasadena CA 91109        USA
From: hoff@fasic5.fnal.gov (James R. Hoff)
Newsgroups: comp.lsi.cad
Subject: Re: Encapsulated postscript for magic/cif plots ?
Keywords: magic cif encapsulated postscript
Date: 16 Apr 92 16:07:33 GMT
Organization: Fermi National Accelerator Lab

In article <1992Apr15.224820.1879@jato.jpl.nasa.gov>, harry@neuron6.jpl.nasa.gov (Harry Langenbacher) writes:
|> >BTW: There is a utility called ps2epsf that I tracked down using
|> >archie. This might be what we're looking for, but I haven't had the
|> >time to compile it yet. It uses ghostscript and pbmplus to generate
|> >the correct bounding box on the ps file.
|> > Douglas Yarrington                                 yarri@ee.eng.ohio-state.edu
|> >
|> -- 
|> Harry Langenbacher 818-354-9513 harry%neuron6@jpl-mil.jpl.nasa.gov
|> Neuroprocessing & Analog Computing Devices Group, FAX 818-393-4540
|> JPL,  M/S 302-231, 4800 Oak Grove Dr, Pasadena CA 91109        USA

We use pplot followed by ps2epsi (aka ps2epsf) at Fermi, and, by and large, it
works well.  We are able to encorporate designs into FrameMaker.  However, 
ps2epsi hangs if the design is large (around 2000 transistors is the limit).
So we aren't completely satisfied either.  After struggling with this problem
for nearly a year, I'm ready to toss the whole problem and draw the documents
with Crayons.

				Jim Hoff
From: amcooke@waikato.ac.nz
Newsgroups: comp.lsi.cad
Subject: L-Edit usage
Date: 15 Apr 92 20:53:43 GMT
Article-I.D.: waikato.1992Apr15.085343.7425
Organization: University of Waikato, Hamilton, New Zealand



Yes, another post from little old New Zealand.  

Like Massey, we here at Waikato are intending to get a chip fab'd in the not
too distant future, we are currently using L-Edit on PCs.

Our big questions are:

1: Will we be able to get a design out on this system?

2: Has anyone out there done this?

3: If no to the above, what is the minimal system for an impoverished little
University to produce a simple (~5K transistor) chip?

Thanks,
  
  Al.


AMCooke@Waikato.ac.nz
Physics Department
University of Waikato
New Zealand
Newsgroups: comp.lsi.cad
From: rick@cs.sunysb.edu (Rick Spanbauer)
Subject: reasonably priced schematics capture packages
Organization: State University of New York, Stony Brook
Date: Mon, 13 Apr 1992 19:07:53 GMT

I recently upgraded my PC to run Windows 3.1 and had the rather
unpleasant surprise that my current schematics capture package
(Phase Three Capfast) will not run.  Does anyone have any
experience/suggestions with other schematics capture packages
that are compatible with Windows 3.1?  I would prefer something
"Window-ized", but can live with a package that lives in a DOS
window.  

					Rick Spanbauer
					SUNY/Stony Brook
From: paul@eros.Berkeley.EDU (Paul Cohen)
Newsgroups: comp.lsi.cad
Subject: Re: OCTTOOLS 5.1, how do I get it?
Date: 15 Apr 92 15:08:22 GMT
Article-I.D.: agate.shgt6INNouq
Organization: University of California at Berkeley
NNTP-Posting-Host: eros.berkeley.edu

In article <1992Apr15.040059.20025@cs.rose-hulman.edu> mgrjhb@NeXTwork.Rose-Hulman.Edu (Jon H. Bohlke) writes:

>   How do I go about getting the OCTTOOLS 5.1 distribution via ftp?  I  
>recently did this (about 5 months ago) for the 5.0 distribution, but the  
>account I used has a new password (and I don't know it).  Help!!

If you have an FTP account, it was moved, some time ago, from
shambhala.berkeley.edu to ic.berkeley.edu. If you forgot the password,
send e-mail to octtools@ic.berkely.edu.

The Octtools are not available via anonymous FTP.

Paul Cohen
paul@aha.com
From: rvutukur@uceng.UC.EDU (Raghunath Vutukuru)
Newsgroups: comp.lsi.cad
Subject: BSDL
Date: 7 Apr 92 13:45:48 GMT
Organization: College of Engineering, University of Cincinnati

Hi,
  
We are developing boundary scan structure synthesis and test vector 
generation tools as part of high-level synthesis system for multi-chip 
module design. 
  
We are looking into BSDL( Boundary Scan Description Language) to use it
as a means of specifying the various options in boundary scan structures
that should be synthesized automatically. Also the same description in BSDL
is intended be used by the test generation tool. 
  
We would appreciate any feedback on the usage of BSDL and its completeness
in describing the architecture for the purpose of synthesis and test vector
generation. We would also like to get in touch with people who are using
BSDL. Please send your mail to
   
         rvutukur@thor.ece.uc.edu
  
Thanks
  
Raghu Vutukuru and Prasad Subbarao

-- 
Raghunath Vutukuru   email : rvutukur@uceng.uc.edu 
Electrical and Computer Engineering, University Of Cincinnati, Cincinnati.
From: chinatti@phoenix.Princeton.EDU (Stephen A. Chinatti)
Newsgroups: comp.lsi
Subject: downloading xilinx from PC
Date: 13 Apr 92 22:45:58 GMT
Organization: Princeton University
Originator: news@ernie.Princeton.EDU

I was wondering if anyone on these groups has experience downloading the
bitfile for a xilinx XC4003 chip (or any 4000 series, I guess) from the cable
for the PC (or other machine).  I am working on a project using the new
xilinx chips, and so far have been unable to successfully wire the 5 pin cable
to the 4003.  It appears that the cable has the following 5 connections:
                      _
     Din            D/P           CCLK        Vcc    GND
  (data in)  (done/not prog) (config clock)  

I have played around with several different connection schemes, with no
success as of yet.  Usually, I get an error while downloading that 
"DONE didn't go high" after it sends the bitfile to the chip.
The documentation for the XC4003 contains many different configurations for
downloading bitfiles, but it doesn't show any configurations with this 
exact cable.  There is no documentation available here on the cable
itself, and no one here has done downloading onto the 4000 series from the PC.
If anyone has any experience with this, or knows of someone else that can help
me, PLEASE let me know.  

	Thanks in advance,
	Steve C
-- 
Steve Chinatti, EMTA <internet:chinatti@phoenix.Princeton.EDU> 
EECS student, Princeton University, Princeton, NJ
From: luciano@athos.Berkeley.EDU (Luciano Lavagno)
Newsgroups: comp.lsi
Subject: Re: where to get espresso
Date: 6 Apr 92 18:40:52 GMT
Article-I.D.: pasteur.1992Apr6.184052.9754
Reply-To: luciano@athos.Berkeley.EDU (Luciano Lavagno)
Organization: UC Berkeley IC CAD Group

gatekeeper.dec.com, anonymous ftp, pub/misc/espresso.tar.Z
What's wrong with the octtools version, anyway ?
Luciano
-- 
Luciano Lavagno    Dept of EECS, Univ of California, Berkeley, CA 94720, USA
+1-510-642-5012    luciano@ic.Berkeley.EDU
Newsgroups: comp.lsi,comp.lsi.cad
From: news@massey.ac.nz (USENET News System)
Subject: problems with OCTTOOLS
Reply-To: M.Pearson@massey.ac.nz
Organization: School of Maths & Info. Sci., Massey University, Palmerston North, NZ
Date: Tue, 14 Apr 1992 05:21:02 GMT


I am hoping to have a chip fabricated that has been designed using
OCTTOOLS in the near future. I have recently found out there are a
number of potental problems with octtools including:

     - The MOSIS pads provided with version 5.0 do not work
     - The cif generated is not necessarily correct

Has anybody out there managed to sucessfully fabricate a chip using
octtools to produce the design. If so what path was used and where was
the chip fabricated? 

Any help will be greatly appreciated.

Murray Pearson
Department of Computer Science
Massey University
Palmerston North
NEW ZEALAND

Email M.Pearson@massey.ac.nz
Xref: sparky comp.lsi:322 comp.lsi.cad:513