From: saha@hal.com (Uttam Saha)
Newsgroups: misc.jobs.resumes
Subject: VLSI circuit/logic design/verification
Date: 14 Apr 92 22:00:26 GMT
Distribution: usa
Organization: HaL Computer Systems
Originator: saha@sahara


                              UTTAM K SAHA
                          3201 Loma Verde DR. # 15
		            SAN JOSE, CA 95117
			    E-mail: saha@hal.com

 TEL:408-866-5625(res)                              TEL:408-379-7000 X 1078(work)
 --------------------------------------------------------------------------------
 OBJECTIVE: A position as a VLSI circuit/logic design and verification  Engineer.
             
 EXPERIENCE:  HaL Computer Systems, Inc. Campbell, CA.
              MACRO DESIGN ENGINEER: November 1991 - present.

             Performed circuit simulation using SPICE, logic simulation
	     using AIDA simulators, created schematic using ECS and layout 
             using MAGIC. Performed design rule check and layout vs. schematic
             verification for a 32 bit Comparator and Parity checker for Cache
             memory.  Created a delay table and documentation for the design.	    

	     Created text files for layout using HLS (HaL layout systems)
	     for 36 bit register with a clock driver. Performed design rule
	     check and layout vs. schematic verification using Checkmate.
             Created a delay table and documentation for the design.

             Implemented a 64 CLA(carry lookahead adder) adder using AIDA
             Design language(ADL) in primitives. Created Schematics using
             ECS. Generated test patterns for logic simulation using AIDA
             simulators and timing libraries for time verification using
             timver - AIDA tool.

             Currently working on macros for floating point units.

 COURSE PROJECTS:

	    Dynamic Content Addressable Memory: Designed a six transistors 
	    dynamic CAM cell which can store three stages(zero, one and
	    Don't care). Simulated the memory chip using SPICE and RSIM and 
	    laid out using MAGIC for fabrication.

	    Designed a 4 x 4 multiplier using Booth Algorithm. Created the
	    layout of the multiplier using MAGIC and performed the simulation.

            Developed an algorithm to calculate the size of transistors and simu-
	    lated for several voltage characteristics and timing requirement of
	    a CMOS digital Schmitt trigger.

	    Developed an algorithm for the synthesis of Mixed Polarity Exclusive
	    Sum of Product expression for arbitrary size.

            Modeled  FIFO (first in first out) using VERILOG.

 COMPUTER SKILLS:
	    Languages:    C, FORTRAN77
	    System:       UNIX, SPARC station, Macintosh, VAX
            Design Tools: Engineering Capture Sys.(ECS), CapFast,  MAGIC,
			  ADL(AIDA design lang.), RTL(register transfer lang).
			  HLS(HaL Layout System), VERILOG XL, Network C, Checkmate

	    Simulators:   HSPICE, RSIM, PGL, timver, Verilog, netlist,
                          AIDA Logic Simulators.

EDUCATION: M.S. Electrical and Computer Engineering, March 1991
	    Portland State University, Portland, Oregon.

	    B.S. Mathematics, June 1988
	    Portland State University, Portland, Oregon.
			  
 COURSE HIGHLIGHTS:
            Digital I.C. Design and analysis   Digital logic Design
	    Computer aided VLSI sys. design    Electronic Circuits Design
	    VLSI design tech. & Methodology    Solid State Devices
	    Mathematical Statistical theory    Optoelectronics
	    Numerical Analysis

 OTHER EXPERIENCE:

	    Coordinator of International Cultural Programs at Portland State Univ.

	    Student supervisor at PSU Food Service.

 PERSONAL:   H-1 visa is being process and willing to relocate

 REFERENCES: Available on request.