From: rdt154k@monu6.cc.monash.edu.au (mr  n    benci)
Newsgroups: comp.sys.atari.st.tech
Subject: Repost - MegaST (not STe) Bus Connections
Keywords: MegaST Bus Connections
Date: 9 Apr 92 23:35:52 GMT
Organization: Monash University, Melb., Australia.


As there has been some discussion on the Mega ST internal bus of late
the following post briefly details the bus connections and what each
pins function is. Refer to any MC68000 data book for more info.
What is presented has been abreviated slightly but no
vital information was edited out. The whole document runs for about 10 
pages, most of it esoteric, dealing with Atari's reasons for the bus and
copyright info plus a lengthy Introduction on the design of the bus. No real
information. Hope this is of help. If you have any queries please don't
hesitate to call me. Best of luck.	

As to whether this is legal or not - I don't know. If problems do arise
as to the legality please inform me as I don't want to cause any serious
problems. Some parts are copied (ie; typed in by hand, by myself) verbatim
from the original documents.

---------------------------<cut here>---------------------------------------

		Atari Mega ST internal bus.

	Mechanical Description:

	Two sizes of expansion card are supported. One, the half card
is half the depth of the Mega St unit. The other, the full
card is the full depth of the unit. In either case, the card
butts up to the rear panel of the St unit which has been provided with a 
removeable hatch through which connectors and/or cables can be mounted.

	The expansion card connects to the St motherboard through a 64
pin connector mounted on the bottom (solder) side of the expansion board.
This connector plugs directly into its mate mounted on the motherboard.
Standoffs, 25mm in length, are mounted into the bottom case through the
motherboard. the expansion card is then screwed down to the standoffs.
The standoffs and screws are not supplied with the Mega St and thus should
be included with the expansion card. A hole located in the left rear of
the expansion card fits around a plastic stud to provide extra strain
relief for rear mounting connectors (See diagrams).

	Electrical Description:

	The signals provided on the 64 pin connector are essentially the
pins of the 68000 processor. These signals are all unbuffered. They are
intended to drive one LS TTL load on the expansion board. driving more than
one load or driving excessive capacitance may cause imporper St operation.
For this reason it is not acceptable to connect to the expansion connector
in any manner other than the one outlined in the previous section (e.g.
connecting directly with a cable is not acceptable.

	The bus may be arbitrated away from the processor using the normal
68000 protocol. However, the bus grant signal provided on the connector is 
the end of the daisy chain. Response time will be effected by the DMA going 
on in the system (e.g. disk activity, hardware bit-blt transfers, etc). If
the peripheral requires DMA to occur while interrupts are enabled, care must
be taken to limit the transfers to bursts of less than about 50 bus cycles
allowing adequate time between bursts to process the interupts.

	The timing of the bus is that of any 8Mhz 68k processor. Since the
signals provided are essentially the processor pins, connecting peripherals
in the same manner as you would to any 8Mhz 68k should work with no problem.
DMA is the exception. The bus cycle produced even while the bus is arbitrated
away from the processor must look exactly like an 8Mhz 68k bus cycle. This
constraint is necessary to provide the proper sharing of the memory between
the processor and the video. In all transfers, DTACK must be provided/sampled
as required by the 68k processor specification. Also, transfers may not last
more than 64 clock cycles. The St will automatically generate a bus error if
AS is held low for more than 64 clock cycles.

	The following diagram shows a top view of the connector on the
motherboard with its associated pin numbers and signal names. This connector
(TRW no. 009-00002-8, JAE no. ME03-R64P-D4T2-A1 or equivalent) is the male
side. The expansion board uses the female side (TRW no. 009-00005-6, JAE no.
ME03-64S-D4R1-A1 or equivalent).

				____
			d4  (1) .  . (2)  d5
			d3  (3) .  . (4)  d6
			d2  (5) .  . (6)  d7
			d1  (7) .  . (8)  d8
			d0  (9) .  . (10) d9
		       /AS (11) .  . (12) d10
		      /UDS (13) .  . (14) d11
		      /LDS (15) .  . (16) d12
		      R//W (17) .  . (18) d13
		    /DTACK (19) .  . (20) d14
		       /BG (21) .  . (22) d15
		    /BGACK (23) .  . (24) GND
		       /BR (25) .  . (26) a23
		       GND (27) .  . (28) a22
		       CLK (29) .  . (30) a21
		       GND (31) .  . (32) GND
		     /HALT (33) .  . (34) a20
		    /RESET (35) .  . (36) a19
		      /VMA (37) .  . (38) a18
		         E (39) .  . (40) a17
		      /VPA (41) .  . (42) a16
		     /BERR (43) .  . (44) a15
		      /NMI (45) .  . (46) a14
		    /INT-5 (47) .  . (48) a13
		    /INT-3 (49) .  . (50) a12
		       FC2 (51) .  . (52) a11
		       FC1 (53) .  . (54) a10
		       FC0 (55) .  . (56) a9
			a1 (57) .  . (58) a8
			a2 (59) .  . (60) a7
			a3 (61) .  . (62) a6
			a4 (63) .  . (64) a5
				----
		<front of ST            rear of ST>

	        Top view of motherboard connector.

	The following is a brief description of each signal on the connector.
For more detailed info consult a 68000 processor manual.

	CLK

	This signal is an 8.0106Mhz TTL compatible, 50% duty cycle square wave.

	/RESET, /HALT

	In combination these two signals can be used to indicate a system
	reset. The /RESET can be used by itself to indicate a system or s/w
	reset (RESET instruction executed). These are both bidirectional
	(open collector) signal terminated on the motherboard with a 1K and
	a 4K7 pullup respectively. They may be driven according to standard
	68000 processor timing to acheive the functions of the 68000's
	/RESET and /HALT lines.

	A system reset will occur at powerup and any time the reset switch
	is pressed. It causes both lines to go low for at least 1ms. A
	software reset will cause only the /RESET line to go low for
	approximately 15us.

	A1-A23

	These lines provide the 23-bit address directly from the 68000
	processor. Terminated with 4K7 pullups on the motherboard.

	D0-D15

	16 bit bidirectional data bus. Terminated with 10K pullups on the
	motherboard.

	FC0, FC1, FC2

	These lines indicate the processor status for the current bus cycle.
	They are directly driven by the 68000 processor. Terminated by 10K
	pullups on the motherboard.

	/AS

	When low, indicates valid address on address bus. Terminated with
	4K7 pullups on motherboard.

	R//W

	When high, processor is doing a read. When low, processor is doing
	A write. Terminated with 4K7 pullups on motherboard.

	/UDS, /LDS

	/UDS indicates upper 8 bits, ie; D8-D15. /LDS indicates lower 8 bits,
	ie; D0-D7. Terminated with 4K7 pullups on motherboard.

	/DTACK

	Bidirectional signal used to indicate a completed data transfer.
	Terminated on motherboard with a 1K pullup

	/BERR

	Used to tell the processor or DMA device that no peripheral device
	has reponded to the current bus cycle. The ST will automatically
	generate this signal if a bus cycle does not complete within 64 clock
	cycles. Terminated on motherboard with 4K7 pullup.

	E

	Enable clock used for 6800 peripherals. 60/40 duty cycle.

	/VPA

	Open collector line used to indicate that a 6800 type cycle should
	be executed. Terminated by 4K7 pullup.

	/VMA

	This signal is used to synchronise 6800 type bus transfers with the
	E clock.

	/BR

	Indicates that the bus will be released at the end of the current
	bus cycle. This signal is daisy chained through the other DMA
	devices on the motherboard, it does not come directly from the
	processor.

	/BGACK

	Open collector signal used by a DMA device to claim bus mastership.
	Terminated by 4K7 pullup on motherboard. Should also be terminated
	on expansion board with another 4K7 pullup.

	/NMI, /INT-5, /INT-3

	These signals are used to asynchronously generate a level 7, level 5
	or level 3 interrupt. These are the only levels which can be generated
	externally. If they all occur simultaneously, the highest priority
	(level 7) will be acknowledged first. The expansion card is responsible
	for responding to any interrupt acknowledges for interrupts which it
	generates. These acknowledges can be either vectored or auto-vectored.
	All three lines are terminated by a 1K pullup on the motherboard.

	Power:

	Power is supplied to the expansion card through a pigtail cable which
plugs onto a six pin connector on the motherboard. The connector on the mother-
board is AMP no. 171825-6. The mating connector on the pigtail from the
expansion borad is AMP no. 171822-6. The drive capabilities are as follows;

			PIN 1 - +5VDC @ 750mA
			PIN 2 - +5VDC
			PIN 3 - GND
			PIN 4 - GND
			PIN 5 - GND
			PIN 6 - +12VDC @ 500mA

	Software Considerations:

	The mediation of available addresses should not be necessary since only
one expansion card may be plugged in at any one time. Atari has set aside the
addresses C00000 through CFFFFF, FF0000 through FF7FFF and FFFE00 through
FFFFFD for use by outside developers. Spurious accesses to FFFFFE/FFFFFF may be
generated.

	You can't add RAM which will work as video memory and/or will allow
DMA. Also if memory is extended on the expansion card, the operating system
will not clear it or allow it to be allocated.

--------------------------------<cut here>------------------------------------

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