HDTenEightyP/NetNews huggingface dataset:
From: jan@pallas.neuroinformatik.ruhr-uni-bochum.de (Jan Vorbrueggen)
Newsgroups: comp.arch
Subject: Re: T9000 crossbar/C104 packet router (was  Re: Fujitsu VPP500)
Date: 30 Sep 92 15:13:10 GMT
	<JAN.92Sep28120824@pallas.neuroinformatik.ruhr-uni-bochum.de>
	<1992Sep29.092704.19684@inmos.co.uk>
Organization: Inst. f. Neuroinformatik, Ruhr-Universitaet Bochum, FRG
In-reply-to: roger@gimli.inmos.co.uk's message of Tue, 29 Sep 1992 09:27:04 GMT

In article <1992Sep29.092704.19684@inmos.co.uk> 
roger@gimli.inmos.co.uk (Roger Shepherd) writes:

   Jan Vorbrueggen now appears to get the T9000 transputer and the C104 
   packet router muddled up:

				    Its datapath thus is 32 bits times 4 wide.
   >|  Nonetheless, it seems to take up 68% of chip area. David May remarked
   >|  that "nobody should tell you anymore that crossbars are too costly or
   >|  can't be implemented".

Nah, Roger, I wouldn't make such a mistake on something I've been waiting
for two years now...
What I meant was that each port is 32 bits wide, and there are four of them,
so you effectively have 128 bits of data going along the chip every cycle.
That the C104 indeed switches 32 links at 4 wires each is accidental.
And again, my newsposting software hit and removed the hyphen; I meant
6 to 8%, which compares quite well with your ~10%.

	Jan
From: jaap@alice.att.com (jaap)
Newsgroups: comp.arch
Subject: Re: What was the intended advantage of using 36bits CPU?
Date: 6 Oct 92 17:11:01 GMT
Article-I.D.: alice.23821
Reply-To: jaap@alice.UUCP ()
Followup-To: alt.folklore.computers
Organization: AT&T, Bell Labs

In article <1992Oct6.130859.14666@terminator.cc.umich.edu>
 >sarr@sinshan.citi.umich.edu (Sarr J. Blumson) and others write:
 > >Everything was once a multiple of 6 - 60 bits, 36 bits, 12 bits, 24 bits.
 > >Except for the DDP-19 which had 19-bit words.
 > 
 > Or the GE-2x5 (can even people at Dartmouth have forgotten them?)
 > which had 20 bit words.
 > 

Or the Electrologica X-1 & X-8, which had 27 bit words.  Followups
directed to alt.folklore.computers.

	jaap
From: mikeh@kralizec.zeta.org.au (Michael Hore)
Newsgroups: comp.arch
Subject: Re: Not using integers
Date: 30 Sep 92 04:31:30 GMT
Organization: Kralizec Dialup Unix Sydney: +61-2-837-1183 V.32


rschnapp@metaflow.com (Russ Schnapp) writes:

>As I recall, the A-series is a tagged architecture, so there would be only one
>ADD, SUB, etc., instruction despite the data format.  The tag automatically
>indicates the datatype, and therefore, the kind of operation to perform.  Or
>didn't the tags go that far?

If I remember right, there was one tag bit which distinguished numeric
from everything else, and for numerics the other 47* bits were data.
Floats and integers weren't distinguished by the tagging.

Non-numerics had 2 extra tag bits -- 3 in all.

*47?  That would be right for the B5500, but now I recall the B6700
had a 51-bit word, including the 3 tag bits.  So did numerics use
50 bits?

--  Mike.

--------------------------------------------------------
Mike Hore        Internet:    mikeh@kralizec.zeta.org.au
Newsgroups: comp.arch
From: eugene@wilbur.nas.nasa.gov (Eugene N. Miya)
Subject: Re: What was the intended advantage of using 36bits CPU?
Organization: NAS, NASA Ames Research Center, Moffett Field, CA
Date: Mon, 5 Oct 92 22:07:27 GMT

Well you guys caught up with IBM being the motive (i,.e. where CAR/CDR
came from).  It was basically numeric.  I just scanned a reference
while cleaning up entries for the parallel biblio which noted numeric precision
requirements for late 40s machines.  32-bits was too marginal (7.2 digits
decimal FP).  36-bit machines had those 4 additional bits as critical.
I think it was about 1948 or so that paper was written (had nothing to
do with parallelism, so I deleted it).

Terrible memories porting 36-bit numeric codes (Univac not DEC-10)
to 32-bit architectures (they dropped it in the end).

Just passing thru.

--eugene miya, NASA Ames Research Center, eugene@orville.nas.nasa.gov
  Acting Associate Editor, Software and Publication Reviews
  Scientific Programming
  {uunet,mailrus,other gateways}!ames!eugene
Seeking Books to buy:	Bongard, Pattern Recognition
			Imhof, Cartographic Relief Presentation
			Books on or by Benjamin Whorf
			Wulf et al, The Design of an Optimizing Compiler
	Yeah John, I want this one, too, after borrowing a library copy.
From: cprice@mips.com (Charlie Price)
Newsgroups: comp.arch
Subject: Re: Roger Ross quote about Alpha being the only 64-bit micro?
Date: 28 Sep 92 22:44:07 GMT
Organization: MIPS Technology, Inc
NNTP-Posting-Host: lloyd.mti.sgi.com

In article <14813@auspex-gw.auspex.com> guy@Auspex.COM (Guy Harris) writes:
>There's an interview with Roger Ross of in the latest Open Systems
>Toady(sic) in which, among other things, he's quoted as saying:
>
>	The only real 64-bit processor out there is Alpha.  The MIPS
>	chip is not a 64-bit machine -- not the way I measure it.  And
>	neither are the rest and neither is SPARC.  All of them have
>	attributes of 64-bit-wide widgets, which makes sense from a
>	bandwidth standpoint.  But a true 64-bit machine has 64-bit
>	registers, 64-bit adders, quad multipliers.  Only Alpha has
>	that.  The present machines are merely 32-bit machines that
>	implement 64-bit paths.
>
>Now, I thought the R4000 had 64-bit registers, and presumed it had
>64-bit adders.  Is it merely lacking the quad multipliers?  Or is Ross
>mistaken?  Or is it lacking something else?

The R4000 has:
 64-bit regs
 64-bit adder
 64x64 -> 128 bit multiply

Perhaps what it lacks for Roger is a revenue stream into his pocket.
I've found Roger's reported remarks in the past difficult to decipher.
I can't decide if he is ill-informed, stupid, dishonest, or some
combination of them.  His comment about the R4000 seems in character.
-- 
Charlie Price    cprice@mti.sgi.com        (415) 390-4457
SGI (MTI) / MS 10U-178 / 2011 N. Shoreline Blvd / Mountain View, CA   94043   
Newsgroups: comp.arch,comp.lang.misc
From: jan@pallas.neuroinformatik.ruhr-uni-bochum.de (Jan Vorbrueggen)
Subject: Re: Goals, Cost, and Flexibility (was Re: "Training" of programmers)
In-reply-to: hrubin@mentor.cc.purdue.edu's message of 1 Oct 92 02:05:58 GMT
Organization: Inst. f. Neuroinformatik, Ruhr-Universitaet Bochum, FRG
	<1992Sep29.232852.22456@CS.ORST.EDU> <BvF75z.GBA@mentor.cc.purdue.edu>
Date: 1 Oct 92 11:05:50

In article <BvF75z.GBA@mentor.cc.purdue.edu> 
hrubin@mentor.cc.purdue.edu (Herman Rubin) writes:

                        On parallel machines, the cost of any test
   is usually at least the cost of completely doing both branches.

Come on Herman, why do you insist than a parallel machine must be SIMD?
Any MIMD machine can, of course, emulate a SIMD machine, and do your
tests efficiently. And newer SIMDs, like the MasPar, have some ability
to perform conditional operations without deactivating/activating sets
of processors, though I wouldn't know whether that applies to your examples.
So your comment really only applies to the CM1/2...
From: khilnany@cps.msu.edu (Mahesh I Khilnany)
Newsgroups: comp.arch
Subject: 32 bit divider
Date: 4 Oct 92 02:26:33 GMT
Organization: Dept. of Computer Science, Michigan State University
Originator: khilnany@indian.cps.msu.edu

Hi netters,

I am looking out for a 32 bit divider for a circuit I am designing. I can either buy one (if it is available) or design one using Feild Programmable gate arrays.

My questions are:

Is there a 32-bit divider available?

Is it plausable to design one using FPGA's?

What other options are available?

Answers to any of the 3 questions are welcome. Please e-mail to my account and I can summerize and post the results on the net.

Mahesh Khilnany
Newsgroups: comp.arch
From: swm11@cl.cam.ac.uk (Simon Moore)
Subject: Re: One Instruction Computers
Reply-To: swm11@cl.cam.ac.uk (Simon Moore)
Organization: U of Cambridge, England
Date: Fri, 2 Oct 1992 08:56:16 GMT

In article <1992Oct1.164945.16703@ringer.cs.utsa.edu>,
srobbins@ringer.cs.utsa.edu (Steven Robbins) writes:
|> In article <1992Oct1.161751.8498@swift.cs.tcd.ie>
butrfeld@swift.cs.tcd.ie writes:
|> >dinda@cae.wisc.edu (Dinda Peter) asks:
|> >
|> >> Prevoiusly someone had posted am message regarding one instruction
|> >> computers - I believe a 3 operand conditional subtract instruction.
|> >> I believe there was also a pointer to a paper that had been written
|> >> on the subject.  Please email.
|> >
|> >Could you let me know as well ? Thanks,
|> >					Andrew Butterfield
|> >					butrfeld@.cs.tcd.ie
|> 
|> One reference is "The ultimate RISC" by D.W. Jones in Computer Architecture
|> News, Vol 16, No. 3, June 1988.
|> 

% in year order:

@conference{Lipovski76,
author="G J Lipovski",
title="Architecture of a Simple, Effective Control Processor",
booktitle="Second Symposium on Micro Architecture",
organisation="EUROMICRO",
pages="187-194",
year=1976}

@article{Azaria83,
author="H Azaria and D Tabak",
title="Design Consideration of a Single Instruction Microcomputer - A
Case Study",
journal="Microprocessing and Microprogramming",
volume=11,
pages="187-194",
year=1983}

@article{Jones88a,
author="D W Jones",
title="The Ultimate RISC",
journal="Computer Architecture News",
pages="48-55",
volume=16,
number=3,
year=1988}

@article{Jones88b,
author="D W Jones",
title="The Minimal CISC",
journal="Computer Architecture News",
volume=16,
number=3,
year=1988}

@article{Griffin88,
author="G W Griffin",
title="The Ultimate Ultimate RISC",
journal="Computer Architecture News",
volume=16,
number=3,
pages="26-32",
year=1988}

@conference{Moore91,
author="S W Moore and G Morgan",
title="The resursive {MOVE} machine: r-move",
booktitle="RISC architectures and applications",
organisation="IEE colloquium 1991/163",
year="1991"}


[Simon Moore][University of Cambridge, Computer Laboratory][swm11@uk.ac.cam.cl]
From: transfer@framentec.fr (Mr Tranfert File)
Newsgroups: comp.arch
Subject: Re: need ftp site for Specmark program
Date: 5 Oct 92 09:08:45 GMT
Organization: Framentec, Paris, France

...
True, but some of the SPEC benchmarks stem from freely available
code.  I would say that if you are simply interested in researching
..
This ought to be available pretty easily.  I'm not sure about others --
anybody have suggestions?
...

As far as I know, Doduc is definitively a PD piece since "immemorial" :-) time (BTW its new
life with the f2c's translated version cannot be anything else but PD too).  And you can
either ftp them from our server ftp.enst.fr or get thru email from your servitor.

I might say so too about Tomcat since I would be surprised that W.Gentzsch ("EuroBen") would
object to it (be free of any string).

--nh
Nhuan DODUC,
Framentec-Cognitech, Paris, France, doduc@framentec.fr
Association Francaise des Utilisateurs d'Unix, France, doduc@afuu.fr
Newsgroups: comp.arch
From: mfx@cs.tu-berlin.de (Markus Freericks)
Subject: Re: One Instruction Computers
Organization: Technical University of Berlin, Germany
	<1992Oct1.164945.16703@ringer.cs.utsa.edu>
	<1992Oct2.085616.16222@infodev.cam.ac.uk>
Date: Fri, 2 Oct 1992 12:09:40 GMT

There is another way to build a one-instruction computer: Let the only
instruction be "move" and memory-map the ALUs. This is great if you
have ALUs that realize multi-cycle operations (e.g. trig FP, table
lookup). Also, code generation is somewhat easy :-)

There are some articles by Petr Kroha describing code generation for
such machines. I cannot find references at the moment, but the
forthcoming LNCS about code generation generators (collection of
papers presented at the Dagstuhl Workshop '91) should contain one.

Markus
-- 
Markus Freericks	| email: mfx@cs.tu-berlin.de	
TU Berlin Sekr.FR 2-2 	| phone: +49-30-314-21390
Franklinstr.28/29	| priv.: +49-30-872523
D-1000 Berlin 10	|"Inertia makes the world go 'round."
Newsgroups: comp.arch
From: srobbins@ringer.cs.utsa.edu (Steven Robbins)
Subject: Re: One Instruction Computers
Organization: University of Texas at San Antonio
Date: Thu, 1 Oct 1992 16:49:45 GMT

In article <1992Oct1.161751.8498@swift.cs.tcd.ie> butrfeld@swift.cs.tcd.ie writes:
>dinda@cae.wisc.edu (Dinda Peter) asks:
>
>> Prevoiusly someone had posted am message regarding one instruction
>> computers - I believe a 3 operand conditional subtract instruction.
>> I believe there was also a pointer to a paper that had been written
>> on the subject.  Please email.
>
>Could you let me know as well ? Thanks,
>					Andrew Butterfield
>					butrfeld@.cs.tcd.ie

One reference is "The ultimate RISC" by D.W. Jones in Computer Architecture
News, Vol 16, No. 3, June 1988.

Newsgroups: comp.arch
From: bmtong@cucs11.cs.cuhk.hk (Tong Bo-Ming)
Subject: Re: HELP: What does ARJ(or other) do besides Huffman Encoding ?
Organization: Faculty of Engineering, The Chinese U. of Hong Kong
Date: Fri, 2 Oct 1992 02:50:40 GMT

root@sean.tomsk.su (Alex Povzner) writes:


>        What does ARJ (or any other archive program) do in order to
>achive archivating the source volume into a half of it ? I.e. what does
>it do besides Huffman Encoding ? I've tried a pure Huffman Encoding
>and I've never got more than 1.5 compression ratio. Does anybody know : why ?


>                                                Alex Povzner
>----------------------
>root@sean.tomsk.su
>Tomsk,Siberia,Russia (Moscow,balalaika,etc)

	Why not try HIGHER-ORDER Huffman ?  The principle is simple.  You
have the stats for 't' and you assign a code to 't' accordingly.  But 't'
will occur more frequently after the letter 'e' than 'z', using this
information will often yield a higher compresssion ratio.  For 2nd-order,
you will need 256 x 256 = 64K to store the model (but you don't have to
store it if you build a standard model and change it every time you
encode or decode a word).

							Tong Bo Ming
From: jwreilly@mipos2.intel.com (Jeffrey Reilly)
Newsgroups: comp.arch
Subject: Re: need ftp site for Specmark program
Summary: SPEC, NCGA
Date: 30 Sep 92 15:09:32 GMT
Organization: Intel Corporation, Santa Clara, CA USA

In article <2AC8F951.9029@news.service.uci.edu> jtien@venice.eng.uci.edu (Joe Tien) writes:
>
>Could someone tell me the ftp site for the Specmark benchmark program (in C).

The SPEC benchmarks suites are licensed software products. You can
obtain information about obtaining them from:

SPEC
c/o NCGA
2722 Merrilee Drive
Fairfax, Virginia 22031-4499

Phone: 703-698-9600, ext 318
Fax: 703-560-2752

Prices:
SPEC CINT92		$425
SPEC CFP92		$575
SPEC CINT92/CFP92	$900
SPEC SDM		$1450
SPEC Release 1		$1000

Accredited Universities can receive a 50% discount on the benchmark
suites.

>Thanks much,
>
>Joe Tien
>jtien@balboa.eng.uci.edu

Jeff 
Intel's Representitive To SPEC

Jeff Reilly			| "There is something fascinating about
Intel Corporation		| science. One gets such wholesale returns
jwreilly@mipos2.intel.com	| of conjecture out of such a trifling
(408) 765 - 5909		| investment of fact" - M. Twain
Newsgroups: comp.arch
From: michalj@fuw.edu.pl (Michal Jankowski)
Subject: Re: No special branch/jump formats?
Organization: Warsaw University Physics Dept.
	<josef.717144694@uranium> <6265@m1.cs.man.ac.uk>
	<1992Sep30.103944.10780@odin.diku.dk>
Date: Thu, 1 Oct 1992 14:21:29 GMT

>>>>> On 30 Sep 92 10:39:44 GMT, thorinn@diku.dk (Lars Henrik Mathiesen) said:

Lars> mshute@cs.man.ac.uk (Malcolm Shute) writes:

Lars> As Roger Ivie wrote, JMP (and JSR) leave out one level of indirection
Lars> --- or rather, they cause the next instruction to be fetched from the
Lars> same address where MOV would fetch the word to be moved. Of course,
Lars> this leaves some cases of MOV <X>,PC that do not have an equivalent
Lars> JMP <Y>, and vice versa; but some of those cases can be simulated:

Lars> 	MOV @(R3),PC	becomes	JMP @0(R3)	--- one location more

This is wrong.
Actually:
        MOV R3,PC       <->     JMP (R3)
        MOV (R3),PC     <->     JMP @0(R3)
        MOV XXX(R3),PC  <->     JMP @XXX(R3)
        MOV (R3)+,PC    <->     JMP @(R3)+
	MOV @XXX(R3),PC  no equivalent
        MOV @(R3)+,PC    no equivalent

I'll post a table with all the addressing modes tomorrow.

   Michal J.
Newsgroups: comp.arch,comp.lang.misc
From: dschleef@sage.cc.purdue.edu (John Paul George Ringo, III)
Newsgroups: comp.arch
Subject: DRAMs, etc.
Date: 30 Sep 92 23:28:06 GMT
Article-I.D.: mentor.BvEzuv.2x2
Organization: Purdue University Computing Center

I am not extremely familiar with ICs, and especially DRAMs, but this
has been bothering me for several years:

Even though a dram may have a time such as 70ns attached to it, does
this mean that the chip can only give one peice of information every 70ns?
In other words, is it possible to pipeline a DRAM, say, sending it an 
address every 30 ns and picking up the corresponding data 70 ns after
the address was sent?

thanks.

dave.
(Dave Schleef)
Newsgroups: comp.arch
From: ssimmons@convex.com (Steve Simmons)
Subject: >>>>>> Best Grad Schools for Computer Engineering?
Date: Tue, 29 Sep 1992 12:26:02 GMT
Organization: Engineering, CONVEX Computer Corp., Richardson, Tx., USA
X-Disclaimer: This message was written by a user at CONVEX Computer
              Corp. The opinions expressed are those of the user and
              not necessarily those of CONVEX.


Ugh.... Don't choose a grad school!!!! Choose an advisor!!!!!

Graduate work is not like undergraduate work.  The most important work 
that you do is the research, not taking tests. 

Therefore, do the following...

- Determine your areas of interest. The basic areas are software engineering,
graphics, architecture, compilers, operating systems, etc... 

- Go to the library and take out a stack of magazines in these areas. 
Both ACM and IEEE publish excellent work in this area.

- Get a list of 10-20 authors doing work in this area.  Usually, one or
two will grab your interest.  Call each up and explain your interests.  
Make sure that they are still pursuing this area.  Professors change their
minds about their interests.  Ask them what they will be doing a year from 
now. 

- Talk to their grad students.  See how many have graduated recently.  I know 
of one prof who had students spending 5 years on Master's thesises. 

- Look are your grades and GREs.  Be sure that you are not too far off from
the school's requirements.  Getting into grad school is like getting a job.
Your professor must want to work with you. 

Thank you. 


						Steve Simmons
From: john@gu.uwa.edu.au (John West)
Newsgroups: comp.arch
Subject: Re: One Instruction Computers
Date: Sun, 4 Oct 1992 06:41:30 GMT
Organization: University Computer Club --- Perth, Western Australia
NNTP-Posting-Host: mullet.gu.uwa.edu.au

mfx@cs.tu-berlin.de (Markus Freericks) writes:

>There is another way to build a one-instruction computer: Let the only
>instruction be "move" and memory-map the ALUs. This is great if you
>have ALUs that realize multi-cycle operations (e.g. trig FP, table
>lookup). Also, code generation is somewhat easy :-)

I wrote a simulator for one of these many years ago (it was on a C64. I no
longer have the code, but its pretty simple to write). I was quite surprised
at how easy it was to program - once you've got a macro assembler for it, and
start building a decent set of macros, it is straightforward. The subroutine
call macro even worked first time...
Writing a compiler for it shouldn't be too difficult - optimizing the code
is the nasty part.

John West
-- 
For the humour impaired: Insert a :-) after every third word
Newsgroups: comp.arch
From: rschnapp@metaflow.com (Russ Schnapp)
Subject: Re: Which is the Best RISC Arcitecture ?
Organization: Metaflow Technologies Inc.
Date: Mon, 28 Sep 1992 20:23:36 GMT

In article <1992Sep25.175419.3718@odin.corp.sgi.com>, mash@mash.wpd.sgi.com (John R. Mashey) writes:
|> In article <14782@auspex-gw.auspex.com>, guy@Auspex.COM (Guy Harris)
|> writes:
|> |> >    > (I know SPARC, MIPS, 88k, POWER, DSP96002)
|> 
|> |> >To those, add
|> |> >     Lightning  (Metaflow / LSI Logic)
|> |> >     Pinnacle   (Ross Tech / Cypress)
|> |> 
|> |> No, don't bother adding them.  He already mentioned both of them, by
|> |> implication.  Hint: what's the first acronym in his parenthesized
|> 
|> To amplify the "by implication", one more time: there are *architectures*
|> and there are *implementations* or those architectures.  Any time you lose
|> track of which is which, you have a good chance of getting confused.
|> That is: SPARC is an architecture, and things like Lightning
|> implementations
|> of that architecture ... or would be, if they existed, which they
|> don't: this is a second reason not to add that one in particular,
|> as that specific project is long gone...

Well, I can't say anything about the Lightning project being long gone,
though it it has been out of OUR hands for quite a long time.  You
would have to talk to LSI Logic about it.

I will refrain from making hyperbolic claims, but we are working on an
implementation that will be better than Lightning.  Better yet, we have
greater control over the entire project, which is a double-edged
sword:  We can make sure that all the right things happen; but, we will
be able to blame nobody but ourselves if a working version doesn't hit
the market while the window is open!

So, don't give up on an out-of-order execution, high performance
SPARC!  (But don't go asking your friendly neighborhood RISC vendor
for one just yet.)

As to the "architecture" question, that depends upon what the original
questioner meant.  If he meant Instruction Set Architecture, then you're
right -- Cypress/Fujitsu/TI are all just implementors of the SPARC ISA.
There is another question of what is the best microarchitecture, or
computer organization.  Among just the SPARC ISA implementations, the
fundamental internal architectures vary widely.  
-- 

...Russ Schnapp
BIX: rschnapp           Email: uunet!metaflow!rschnapp or rschnapp@metaflow.com
Metaflow Technologies   Voice: 619/452-6608x230;  FAX: 619/452-0401
La Jolla, California    Unless otw specified, I`m speaking only for myself!
From: mash@mash.wpd.sgi.com (John R. Mashey)
Newsgroups: comp.arch
Subject: Re: Roger Ross quote about Alpha being the only 64-bit micro?
Date: 29 Sep 92 01:12:30 GMT
Organization: Silicon Graphics, Inc.

In article <14813@auspex-gw.auspex.com>, guy@Auspex.COM (Guy Harris)
writes:
|> There's an interview with Roger Ross of in the latest Open Systems
|> Toady(sic) in which, among other things, he's quoted as saying:
|> 
|> 	The only real 64-bit processor out there is Alpha.  The MIPS
|> 	chip is not a 64-bit machine -- not the way I measure it.  And
|> 	neither are the rest and neither is SPARC.  All of them have
|> 	attributes of 64-bit-wide widgets, which makes sense from a
|> 	bandwidth standpoint.  But a true 64-bit machine has 64-bit
|> 	registers, 64-bit adders, quad multipliers.  Only Alpha has
|> 	that.  The present machines are merely 32-bit machines that
|> 	implement 64-bit paths.
|> 
|> Now, I thought the R4000 had 64-bit registers, and presumed it had
|> 64-bit adders.  Is it merely lacking the quad multipliers?  Or is Ross
|> mistaken?  Or is it lacking something else?

Ross is "mistaken".  This is a clear, definite *mis*-statement of fact
that
has been openly published for quite a while...

The R4000 chip is every bit as 64-bit as Alpha is.  Both have 64-bit
integer
registers, 64-bit adders, and 64-bit data paths.  

Re: "quad multipliers":
	a) Alpha has 2 instructions that do 64X64->64, one for upper
	half, and one for lower half of the product.
	b) R4000 has 64X64->128, filling 2 registers.
However, in DEC parlance:
	word = 16 bits
	double = 32 bits
	quadword = 64 bits
and in MIPS parlance:
	halfword = 16 bits
	word = 32 bits
	doubleword = 64 bits

Hence, Mr. Ross is "right": R4000 does not have "quadword" multipliers
although it certainly has 64-bit ones...

-- 
-john mashey    DISCLAIMER: <generic disclaimer, I speak for me only, etc>
UUCP:    mash@sgi.com 
DDD:    415-390-3090
USPS:   Silicon Graphics 7U-005, 2011 N. Shoreline Blvd, Mountain View, CA
94043