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Subject: Superchips for supercomputing.
Date: Fri, 2 Oct 92 18:35:29 EDT

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Superchips for supercomputing.

 {OP992,SUPERCOMPUTERS/FUTURE TECHNOLOGIES,Superchips for
supercomputing,The technology for fast gallium arsenide chips is
making strides:, but familiar silicon still has plenty of
potential,The microprocessors used in workstations may be the
best choice for massively parallel machines } {FH4,Harold Dozier
Convex Computer Corp.,     } Semiconductor technology for central
processing units of supercomputers is in a state of flux. Though
long the leader, silicon emitter-coupled logic (ECL) now faces
competition from silicon bipolar complementary metal-oxide- sem-
iconductor
 (biCMOS) ICs and gallium arsenide ICs. In fact, a variant of
ECL, called emitter collector dotted logic (ECDL) may also vie
with its progenitor ["A dotted kind of logic," p. 68]. Even
within the GaAs category, novel logic structures may soon jostle
for position. To further confuse the picture, ordinary CMOS chips
for workstations may be the best choice for massively parallel-
processing supercomputers of the future.
     In supercomputers' central processing units (CPUs), biCMOS
is making a strong bid for fast RAMs, although it is also the
primary high-speed logic in midrange supercomputers like Convex's
C3400 family. In the present generation of fast RAMs, biCMOS usu-
ally has longer input and output delays than ECL (about 2.5 ns
versus 1.2 ns for ECL). For one thing, the bipolar transistors
produced by biCMOS processing are not as well optimized as ECL
transistors.  For another, signals to or from external ECL ICs
have to be translated at biCMOS I/O boundaries.
     I/O delays account for much of the total delay of small RAM
chips, say 1K bytes, to the advantage of semiconductor processes
with faster I/O. But as the amount of memory on a chip increases,
the speed of the core memory itself plays an ever larger role in
overall RAM performance. BiCMOS utilizes CMOS to implement a
memory cell that is smaller than the ECL one, but, unlike pure
CMOS, has bipolar devices to drive row and column lines and for
sense circuitry.
     So for large RAMs, to offset slower-than-ECL I/O and perfor-
mance reduced by bipolar-driven internal circuits, biCMOS offers
smaller core memory, shorter internal signal paths (particularly
on row and column lines), and overall faster core access. BiCMOS
can be especially effective in self-timed RAMs, where internal
core memory cycle time is the worst constraint.
     For CPU logic, biCMOS uses a CMOS gate structure with
bipolar-buffered outputs. The logic gates produced are smaller
but slower than the ECL variety, but fast enough for midrange
supercomputers. Representative cycle times are 20 ns for biCMOS
versus 5 ns or less for ECL.
     CHIP TO CHIP. Depending on the system architecture, part of
the disparity in gate speed between biCMOS and ECL can be miti-
gated by the larger number of (smaller) gates per biCMOS chip.
Extra functionality can be put on a biCMOS chip, to reduce the
number of chip-to-chip delays.
     As for GaAs versus ECL, until recently ECL held the edge in
terms of available logic gates per chip (gate count). But GaAs is
no longer immature.  There is now near-parity in terms of perfor-
mance and gate count between ECL devices and direct-coupled
field-effect-transistor logic (DCFL) GaAs devices in volume
production--and GaAs consumes less power.
     GaAs also has more logic gates per unit area. ECL gate
structures are not as simple nor as small as equivalent DCFL gate
structures, but ECL chips can be fabricated in larger sizes, at
equal cost, thanks to the more mature silicon-based technology
and the availability of larger silicon wafer sizes with lower de-
fect density. The upshot is that ECL and DCFL GaAs are roughly
equal in performance and cost. For both, a state-of-the-art clock
speed is 200 MHz and gate count is 50 000 gates per chip.
     Gallium arsenide's lower power dissipation can count for a
lot. If dissipating less power produces no advantage at the sys-
tem level, the point is moot. But in the Convex C3800 supercom-
puter, air cooling, rather than liquid-refrigerant cooling, was a
system requirement. Here, the lower dissipation of GaAs was the
overriding reason for its being favored over ECL.
     Incidentally, DCFL is not the only logic form that can be
implemented in GaAs. The high-density GaAs chips now on the mark-
et are mostly DCFL, which has transistors much like silicon n-
channel MOS transistors, but is usually built of only NOR gates
rather than NOR, NAND, or complex gates.
     This simple gate structure is what saves DCFL most power.
Per function, DCFL requires less die area than does ECL. This
means that signal paths within gates and especially between them
are shorter than in ECL and are therefore more lightly loaded.
Thus, the same switching delay can be achieved with lower
current.
     Current-mode logic (CML), which closely resembles ECL, can
also be built in GaAs. With GaAs CML, faster-switching FETs re-
place the bipolar transistors in ECL, but CML mops up even more
power than ECL. Moreover, GaAs CML structures are much more com-
plicated than DCFL gates, so a GaAs-based CML chip would have a
far lower gate count than either DCFL or ECL. CML is used in com-
munications circuits, but seems not to be the primary logic tech-
nology in any commercial supercomputer. Still, that could change
as GaAs technology advances.
     The neglect of CML so far in supercomputers points up the
fact that the machines' designers do not jump to use a new high-
speed technology the minute someone announces that it has been
fabricated in an R&D lab. It costs tens or even hundreds of mil-
lions of dollars to develop a new supercomputer, and companies
cannot afford to have a project of that magnitude fail or slip
because one of the parts used in the design turns out to be un-
manufacturable.
     Undoubtedly the supercomputer industry is driven toward
high-performance technologies by its quest for ever-higher system
performance. But just aligning a new supercomputer design with a
new generation of higher-density, smaller-geometry ICs is risk
enough; considering technologies that have no production history
behind them is too dangerous. After all, it took the better part
of a decade for GaAs ICs to advance from
  a concept to a commercial product for supercomputers.
     In short, supercomputers will probably continue to use the
same three primary IC technologies--biCMOS, ECL, and GaAs--for
several years to come.  Advances are likely to come through im-
provements in these technologies rather than from commercializa-
tion of a new technology.
     A case in point is biCMOS technology, which is ripe for im-
provement. Many suppliers created their biCMOS processes by ad-
ding additional--but not necessarily optimal--bipolar capability
to an existing CMOS process. Others have added not necessarily
optimal CMOS capability to an existing bipolar process. Some chip
suppliers have even taken both approaches.
     One view of the future holds that there will not be separate
ECL, biCMOS, and CMOS processes, especially for logic and high-
speed RAM, though separate, specialized processes will continue
to be used for dynamic RAM. Semiconductor vendors will create a
single process that can simultaneously produce very good, high-
density CMOS and high-performance bipolar transistors and resis-
tors.
     Then a CMOS process will simply be a silicon process with
some of the bipolar transistor steps left out. But if resistors
are needed, they can be added easily. And if a mostly ECL chip
needs some MOS transistors, they can be added at little extra
cost.
     This should happen in the fairly near future, so it may be
pointless to debate whether the future high-speed RAM technology
will be ECL or biCMOS, and whether CMOS will replace biCMOS or
ECL as a logic technology. It is to be hoped that, with this pro-
cess integration, some standard will emerge for high-speed signal
levels. Then it will no longer be necessary to deal with CMOS
logic and dynamic RAMs, with their positive power supplies and
signal swings, in the same system as ECL-type negative supplies
and swings.
     GaAs MEMORY. As to GaAs, that technology may eventually pro-
duce large stand-alone RAM chips. Already, small GaAs RAMs have
found some use in supercomputers and even in workstation servers.
But ECL and biCMOS are still the technologies of choice for fast
static RAMs. Before that changes, two impediments must be over-
come.
     One is just the immaturity of high-transistor-count GaAs
technology. With smaller GaAs wafer sizes, larger cell sizes, and
lower yields than an equivalent silicon wafer, it is not yet
cost-effective to produce GaAs RAMs in higher densities. But GaAs
processes are becoming more refined; they are likely to produce
RAM cell geometries close to those of the most compact CMOS cells
in the near future.
     The second impediment will take some industry cooperation to
overcome: incompatible signal levels. Commercial high-density
GaAs logic chips handle external signals at ECL and TTL levels;
but they vary widely from product to product and vendor to vendor
in internal signal levels (anywhere from greater than zero to
near -5 V). I/O level translation causes delay that robs GaAs of
part of its speed advantage, and this will continue unless a
standard direct GaAs signal level convention is developed.
     Meanwhile, GaAs logic devices should continue to advance ra-
pidly in gate count. GaAs gate density started out low and chips
started out small, but for good reason. Their developers had
enough trouble building good GaAs MESFETs of any size and could
not press the state of the art in lithography or expect a large
defect-free chip area. (MESFETs, or metal-semiconductor FETs, are
junction devices, in contrast to MOSFETs, or metal-oxide- sem-
iconductor FETs, in which an insulating layer separates the metal
from the semiconductor.)
     But there is nothing that would prevent GaAs MESFETs from
attaining the same small geometry as silicon MOSFETs. Already,
individual MESFETs are nearly as small as MOS transistors. What
GaAs needs is silicon-like contact and interconnection methods
that let more transistors be hooked up in a given area. Extras
like the GaAs equivalent of polysilicon resistors would also help
RAM cells. And, of course, larger, more economical GaAs wafers
are on the way; GaAs wafers are now about 10 cm in diameter, and
they are likely to increase to 15 cm next year--smaller than
today's 20-cm silicon wafers, but gaining.
     When it comes to NAND gates and similar series circuits,
GaAs junction FETs need extra diodes, whereas silicon MOSFETs do
not. Here, silicon-based technologies may retain some superiority
in functional density, but not nearly as much as in the past.
     TOP OF THE LINE. CML GaAs, now neglected, may prove viable
in the future for the highest-performance supercomputers. In the
recent past, the density of CML GaAs chips has been too low; too
many CML chips are needed, and the resulting interconnection de-
lay offsets the logic's tremendous speed--already about 1 GHz.
But as DCFL GaAs approaches biCMOS densities, CML {C,5.6}Module
for a super-computer consists of an array of ICs directly mounted
on a printed-circuit board by gold-to-gold bonding. Each fully
packaged IC contains 10 000 logic gates. Vertical pins are for
interconnections to other circuit boards.   GaAs should draw
closer to ECL logic density. When that happens, CML's speed may
well compensate for its high power dissipation in top-of-the line
supercomputers.
     Nevertheless, it is impossible to speculate on the longevity
of silicon versus GaAs. Both materials have their pros and cons.
The higher carrier mobility of GaAs lets it switch more current
with smaller devices. Silicon can grow an insulator for the gate
dielectric of insulated-gate FETs and its bipolar transistors are
backed by years of evolution.
     A trend that may favor silicon logic in supercomputers is
the growing popularity of massively parallel processing (MPP), in
which large numbers of small, lower-performance processors
operate in parallel, replacing a single large processor. A good,
cost-effective choice for CPUs in an MPP supercomputer may be the
same reduced-instruction-set computer (RISC) chips used in
workstations--relatively inexpensive silicon CMOS chips today and
biCMOS in the next generation.
     More certainty is possible over the role of customized
versus standard memory in superconductor CPUs. As suppliers fit
more and more transistors into the chip, much high-speed RAM has
moved onto the logic chips, and this trend seems likely to con-
tinue. Any discrete memory chips will take the form of
application-specific RAMs--that is, RAMs designed for a particu-
lar application in a particular supercomputer. Supercomputer
manufacturers are forced to optimize RAMs for individual applica-
tions instead of making do with less-than-optimum catalog parts.
Today, IC suppliers are working directly with those manufacturers
on custom RAM designs, instead of offering new, very high-speed,
standard RAMs to the market.
     Will wafer-scale integration show up in supercomputers? The
technology was widely touted a few years ago. The principle
behind it is to put a complete subsystem on a single semiconduc-
tor wafer by processing several different device types on it and
by interconnecting the good devices as required. So far, however,
the technology has not been cost-effective. Just one good device
too few of a required type, and the whole wafer has to be dis-
carded. Enough good devices of all types, and the wafer is likely
to contain unused good devices and have a low functional density.
     If wafer-scale integration has a place, it may be in some
mass-memory applications, but not in the CPU of a supercomputer.
Multichip modules (MCMs) are a far better alternative. MCMs com-
bine several bare chips in a single package where chip-to-chip
interconnections enjoy a favorable environment designed to minim-
ize signal delay.
     ABOUT THE AUTHOR. Harold Dozier is vice president of ad-
vanced development at Convex Computer Corp., Richardson, Texas.
From 1988 through 1990, he managed the design of the GaAs-based
C3800 supercomputer. He is now selecting an application-specific
IC technology for a future massively parallel processing product.
{FH2,A dotted kind of logic} {A2}For its next generation of
supercomputers, to be introduced in about four years, Cray
Research Inc. will use a new form of silicon bipolar IC. The
emitter-coupled logic (ECL) so widely favored for high-speed com-
putation will give way to emitter and collector dotted logic
(ECDL). "Dotted" refers to the fact that several emitters or col-
lectors are physically connected to form a logic function.
     ECDL is both faster and more efficient than ECL. Clock rates
above 500 MHz (that is, clock cycles less than 2 ns) have already
been demonstrated.
     An ECDL cell performs two levels of logic: emitter-dotted
wire-AND gates are connected to a collector-dotted wire-OR gate
[see figure]. As the signal gain in the logic circuit is less
than 1, each cell is provided with an amplifying current-switch
driver. In ECDL, the signal is restored in the amplifier after
two dotted logic stages; in ECL, in contrast, each stage contains
a signal-amplifying current switch.
     The logic and driver circuits operate with low-swing signals
of 500 mV on a low-voltage supply of -2.7 V. These low levels,
and the absence of ECL-type series gating, account for ECDL's ul-
trashort gate delays and low power dissipation (65-90 ps and
0.7-0.8 mW per gate). Comparable ECL gates, fabricated with the
same silicon bipolar process and subject to identical loading,
experience gate delays of 100-150 ps at 2-3 mW per gate.
     All switching within an ECDL circuit is in phase; that is,
an output is high when its input is high. As soon as an input be-
gins changing, the internal nodes begin changing in the same
direction. The internal signal is not inverted as in ECL, and
there is no threshold that must be passed before the internal
signal begins changing. This in-phase characteristic gives ECDL
its high fan-in capacity. It is not subject to the delay that oc-
curs in inverting nodes when multiple inputs switch simultaneous-
ly. Moreover, ECDL input transistors are connected in an
emitter-follower configuration that presents a high input im-
pedance and minimum load to the preceding driver.
     Only one transistor is needed for each input, and all input
transistors for a logic cell may be placed within the same col-
lector region, or tub. This leads to compact logic layouts on the
chip. And the regular pattern of the input transistors greatly
simplifies generation of macrocells.
     Each cell's current-switch driver may be set to any of eight
programmable current levels to minimize the power consumption and
thereby achieve the required delay for the interconnection-metal
load and fan-out of the cell. The driver is programmed by
computer-aided design software after the logic macros have been
placed and the cell interconnections have been routed. The power
programming keeps loading delays as low as 18 ps/mm of intercon-
nect and 1.1 ps per fan-out load at a 3.2-mA switch current.
     The current-switch driver produces output signals having
symmetrical rise and fall profiles. The symmetry decreases tran-
sient noise induced on power buses and adjacent signal lines to
one-twentieth that of an emitter follower.
     We are now making arrays of ECDL containing more than 50 000
logic gates and 300 input and output drivers on a 10-bymm silicon
chip, for a total of more than 1 million devices (resistors and
transistors). Also built into the chip are a fixed clock distri-
bution network and a boundary scan register for testing.--Jan
Wikstrom and Tony Vacca, Cray Research Inc., Chippewa Falls, Wis.
{A2}Emitter and collector dotted logic (ECDL) creates a sum of
products in negative logic. For the 8+2 input cell shown here,
first-level AND gates are formed by linking emitters to nodes
AND1 and AND2. A second-level OR gate is formed by linking
diode-connected collectors to the node labeled OR. The power-
programmable driver produces both true and complementary output
signals for distribution on the chip. *eof*eot

Copyright 1992, IEEE Spectrum.

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