From: horen@netcom.com (Jonathan B. Horen -- [408] 736-3923)
Subject: VLSI, ASIC, PAL, PCB Designer 11+ years experience
Organization: NetCom -- OnLine Communication Services
Distribution: ba
Date: Fri, 1 Jan 1993 17:35:08 GMT


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                             CYRUS YAMIN


                      Tel:  (408) 749-1962 [home]
1786 Lamont Court                                 Sunnyvale, CA  94087
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SUMMARY
=======

A result-oriented project leader with more than eleven years hands-on
experience in the design and development environment. Major strengths
are the hardware design of ASICs, PALs, printed-circuit-board logic,
and systems. Additional skills utilizing the CAE tools, hardware 
modeling and synthesis (VHDL, ABEL) in design verification. A 
dependable, thorough, well-organized technical leader who delivers
engineering tasks on time.


TECHNICAL SKILLS
=================

Programming and Test Languages:  Pascal, C, Mediator
Systems and Test Equipment:  VAX-11/780: VMS, Sentry 50, S780
Workstation and Simulation:  Racal-Redac: Visula/Cadat, Daisy: DNIX,
                             Sun: UNIX, Valid



EXPERIENCE
==========
_____________________
Schlumberger
ATE Division
San Jose, CA
1990 to present

PROJECT LEADER.  Responsible for system hardware design,
	implementation and characterization of controller boards and
	subsystems for S780 In-Circuit tester. Managed system-wide
	projects, such as universal AC/DC, controller, and interconnect
	subsystems.

   o	Completed design and manufacturing introduction of System
	Control Card (SCC) for S780/S790 test systems. Features 
	include real-time parallel and serial port controller/monitor
	using the VME bus interface, utilizing Programmable Logic
	(PAL) and FPGA.

   o	Designed and introduced to manufacturing the protocol-controlled
	Serial Port Interface Board (SPIB). Reduced hardware and software
	overhead by using the MC68050 programmable micro-controller.

_____________________
Schlumberger
ATE Division
San Jose, CA
1987 - 1989

STAFF DESIGN ENGINEER.  Responsible for design and simulation of ASIC
	gate array, ECL/CMOS logic design and test developments.

   o	Designed, developed, and verified the latch buffer gate array,
	using the VTI CMOS process, achieving higher current output
	drive and lower noise on power bus and switching outputs.

   o	Produced full-fledged design and fabrication of Pin Control
	assembly for a low-cost test system utilizing double-sided
	surface mount technology to achieve higher device density on
	board. Features included mixed ECL and CMOS ASICs in timing
	and logic paths.

   o	Automated the S70 and ECL interface module, including
	instruments such as HP5328 counter-timer and HP8016 word
	generator to test high-speed ECL boards. Wrote extensive
	MEDIATOR and Pascal programs to control the interface and
	instruments.

_____________________
Schlumberger
ATE Division
San Jose, CA
1984 - 1986

SENIOR DESIGN ENGINEER.  Responsible for design of the ECL/CMOS
	logic boards, system integration, and development of system
	options.

   o	Completed design and manufacturing introduction of digital
	ECL/CMOS Pin Control and timing multiplexer boards. Features
	included controlled impedence, differential signal path, and
	utilized 100K ECL logic and Programmable Logic Array (PAL).

   o	Led project for the 100MHz option of the Sentry 50, including
	precise coordination of activities of hardware design, 
	modification of software diagnostics, and calibration efforts
	for on-time delivery to customers.

   o	Integrated and brought-up various high-speed boards for Sentry
	50/100MHz test systems. Wrote extensive diagnostic programs
	to debug and troubleshoot the timing multiplexer and formatting
	boards. 

_____________________
Schlumberger
ATE Division
San Jose, CA
1981 - 1983

DESIGN ENGINEER.  Responsible for design and development of ASIC gate
	arrays for the S50 test system.

   o	Designed, implemented, simulated, and tested various ASICs
	using the 100K ECL National process, including timing and
	formatting gate arrays. These gate arrays were used in the
	shared-timing architecture of the Sentry 50 test system, and
	included multiplexing features for maximum number of timing
	paths, lowest possible noise and cross-talk, with minimum
	path-to-path skew delay.



EDUCATION
=========

BSEE.  University of Louisiana, May 1981.

Stanford Graduate Instructional Courses (completed related courses to
	projects).

University of Phoenix, MBA program (completed introductional courses).
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