From: jon@alpha.ee.ufl.edu (Jon Mellott)
Subject: Re: Microcoded processors?
Organization: EE Dept at UF
Date: Sun, 12 Apr 92 17:50:24 GMT

In article <PSHUANG.92Apr12015958@w20-575-3.mit.edu>, pshuang@athena.mit.edu (Ping-Shun Huang) writes:
|> In article <1992Apr10.214150.5525@cs.tu-berlin.de> tolk@opal.cs.tu-berlin.de (Robert Tolksdorf) writes:
|> 
|>  > are there or have there been microcoded microprocessors on which the
|>  > microprogram could be changed during runtime thus changing the
|>  > semantics of assembly-code??
|> 
|> I recall an article in Byte magazine about four years back about a CPU
|> with similar characteristics (the only specifics I remember were that
|> this made emulating other CPU's relatively cheap, i.e. taking somewhat
|> less than the usual order of magnitude hit in performance). I believe
|> the article included the acronym "WISC" for Writeable Instruction Set,...

If we're talking about single chip microprocessors, this is not 
really a very realistic approach. To start, the microcontrol store 
on classic CISC microprocessors (e.g., 680x0 family) occupies a large
portion of the die area. The microcode store is typically implemented 
with a PLA -- this is a very efficient in terms of die area.
Writable control stores would probably be implemented in SRAM.
Unfortunately, SRAM uses lots of die area so the control store would
be huge. For example, the i486 uses about 1/3 of the die area for 
an 8 KB SRAM cache -- although the cache tags are included in this.
Typically, microcoded systems have wide control word widths, so, 
with such a relatively small amount of memory you wouldn't have too many
words of control store.

As a pre-emptive reply, I'll say that AMD does have a nifty little 
programmable, UV-erasable (EPROM based) single chip microsequencer with 
a small control store. This sort of approach would not be attractive 
because it is probably not going to be easy or cheap to get a big 
microprocessor implemented on such a process.

Another reason not to take this approach is that it would probably be 
difficult to change the microcode of the current generation of CISC 
microprocessors (e.g., 80486, 68040). These processors have borrowed 
some RISC features like hardwiring the most commonly used instructions
and other time critical paths. I'm not saying that it couldn't be done,
just that it would be painful.

Finally, microprogramming a commercial architecture would probably 
be quite painful. Only hardware/software engineers with lots of free time
would be able to tackle it. The average user would see little benefit from 
such an approach.

On a positive note, if you want to microprogram a machine to tackle 
specific problems, the best bet is to build it yourself out of commercially
available building blocks. TI has an excellent series of thirty-two bit 
building blocks, the 74ACT8800 series. This series of parts includes 
microsequencers, register files, ALUs, integer multipliers, double-precision 
floating point multiplier-accumulators, barrel shifters, and the like. 
Coupled with some of those nifty AMD EPROM based microsequencers (those 
come in a 28 pin package, by the way), you could build a machine with 
multiple instuction issue, heavy pipelining, etc...

Good luck

Jon Mellott
(jon@alpha.ee.ufl.edu)
High Speed Digital Architecture Laboratory
University of Florida