From: veit@du9ds3.uni-duisburg.de (Holger Veit)
Subject: Re: Benchmark Circuits for Digital circuit test pattern generation
Date: 21 Aug 92 09:35:25 GMT
Reply-To: veit@du9ds3.uni-duisburg.de
Organization: Uni-Duisburg FB9 Datenverarbeitung

In <18341.2a92f106@levels.unisa.edu.au> 8809787l@levels.unisa.edu.au writes:

>Dear reader

>In many papers in the field of fault diagnosis and Test generation for digital
>circuits I have seen benchmark circuits used to make comparison between the
>speed and effeciency of various test generation methods.

>I have commonly seen labels such as C880, C5315 or C7552 used to describe or
>mension these benchmark circuits. In many papers on this topic also I have seen
>the following reference to this circuits mensioned:

>(*) F. Brglez and H. Fujiwara, "A neutral netlist of ten combinational
>benchmark circuits and a target translator in FORTRAN," in Proc. IEEE Int.
>Symp. on Circuits and Systems, Kyoto, Japan, June 5-7, 1985

>One place that I found this reference mensioned was in :

>(*) Short Papers "Expremental Evaluation of Testability Measure for Test
>Generation" by Chandra & Patel in IEEE trans. on Computer Aided Design Vol. 8,
>No. 1 January 1989.

>I need to know the following:

>(1) What are these benchmark circuits ?

These are gate netlists of existing or synthesized circuits issued exactly 
for the purpose to get comparable results for some developed simulation or
testing software. If you want to know what their function is, 
I can't help you much.

>(2) Where can I get these from ?

The original source of the ISCAS'85 benchmarks is the FTP server from
mcnc.org. In Europe there is a copy at ftp.uni-duisburg.de (134.91.4.132)
in /pub/cad/ISCAS85.tar.Z (this site is "here"). 

>(3) What is the Brglez & Fujiwara reference ( I could not locate it ) ?

This seems to be one of big mysteries in research on testing. The references
give some page numbers that are outside the range of pages of the
ISCAS proceedings. Seems to be an unofficial addendum, or researchers like
referring much more than reading ;-) Anyway, the ISCAS85.tar.Z file 
contains a TeX file which gives some information.

>(4) How can I use the above benchmark netlist to test a test generation method?

The package contains net lists as well as fault lists, so the base information
is given. Unfortunately, there is no list, which of the faults are redundant.

>(5) Is there a updated version of this which has come out since 1989 ?

There is a "nonredundant" set of the same combinational circuits which is
dated 1991. It is in the above package.
The so-called ISCAS'89 benchmarks (names starting with "s" instead of "c")
are sequential benchmark circuits for the same purpose.

>I would be very greatfull if some one could help me by responding to the
>following e-mail address:

>		8809787L@LV.LEVELS.UNISA.EDU.AU

>Thank you very much, and hope to hear from you soon.

>Yours faithfully
>Peyam Pourbeik


>School of Electronic Engineering
>University of South Australia ( Levels campus )
>Adelaide, South Australia, Australia

Hope that helps

Holger

-- 
|  |   / Holger Veit             | INTERNET: veit@du9ds3.uni-duisburg.de
|__|  /  University of Duisburg  | BITNET: veit%du9ds3.uni-duisburg.de@UNIDO
|  | /   Dept. of Electr. Eng.   | "No, my programs are not BUGGY, these are
|  |/    Inst. f. Dataprocessing |          just unexpected FEATURES"
From: hai@hpfcso.FC.HP.COM (Hai Vo-Ba)
Date: Fri, 21 Aug 1992 14:18:23 GMT
Subject: Verilog to TEGAS translator
Organization: Hewlett-Packard, Fort Collins, CO, USA