From: tzen@atlantic.cps.msu.edu (Ten Hwan Tzen)
Newsgroups: misc.jobs.resumes
Subject: PhD/CS Parallel Processing, Optimizing Compilers (self-relocate)
Date: 7 Apr 92 07:38:19 GMT
Distribution: usa
Organization: Department of Computer Science, Michigan State University
Originator: tzen@atlantic.cps.msu.edu


Dear Prospective Employer:

  I am looking for a research and software development position in the 
  areas of  parallelizing compilers,  superscalar compilers,  parallel 
  programming environments, and parallel and distributed processing. I 
  just received my Ph.D. degree  in computer science,  specializing in 
  these areas.

  My thesis research is focused on  compilation techniques for parallel 
  machines. I proposed advanced loop scheduling and loop transformation 
  techniques that can be applied in compilers and  programming tools to 
  speed  the execution  of iterative  loops.  During  the  course of my 
  dissertation research I gained significant experience with the theory 
  and practice of compiler design,  in particular loop optimization for 
  parallel and superscalar machines.

  In addition, I have finished  several projects  in multiprocessor and 
  distributed systems dealing with loop scheduling, performance modeling, 
  numerical applications, architecture simulators, and data bases, which 
  provided me  with  solid  experiences in  high-performance  computing,
  parallel  processing and  object-oriented  programming.  I have  also  
  familiarized myself with  the parallel machines available at Michigan 
  State University, including the nCUBE, BBN GP1000, and CONVEX C240.


  Prior to attending graduate school, I obtained extensive experiences 
  in directing commercial product development during four years of work 
  in industry.  My  work experiences  include  project  leader,  system 
  engineer, and researcher.  Enclosed please find my a copy of my resume. 
  I am looking forward to the opportunity of discussing my qualifications 
  and possibility of employment with you.  
  Thank you for your kind consideration.

  Sincerely,

    Ten H. Tzen

=================================================================== 

                          Ten H. Tzen

1403 B Spartan Village                          Home: (517) 355-0761
East-Lansing, MI 48823                        Office: (517) 355-9309
                                            E-mail: tzen@cps.msu.edu

OBJECTIVE:
---------

  A research  and development position  in the areas of parallelizing 
  compilers, superscalar compilers, parallel programming environments,  
  and distributed processing. 

EDUCATION:
---------

   Ph.D. Computer Science, Michigan State University, March 92.

      Thesis advisor: Professor Lionel M. Ni.
      Thesis topic  : Advanced Loop Parallelization: Dependence 
                    Uniformization and Trapezoid Self-Scheduling. 

        (1) Data Dependence Uniformization overcomes the difficulties 
        of  parallelizing  a nested  loop  with irregular  dependences 
        among iterations. Serial execution in such a loop is no longer 
        necessary.  Concurrent  execution can  be applied  to obtain a 
        higher speedup. 

        (2) Trapezoid Self-Scheduling is a new scheduling scheme for 
        DOall loops  which achieves  a better  workload  balance  by 
        inducing a smaller scheduling overhead than other scheduling 
        schemes employed currently. 

   M.S. Computer Science, Michigan State University, Sept. 1988.

   B.B.A. Electrical Engineering, Tsing-Hua University, June 1981.
                                         Hsin-Chu, Taiwan, R.O.C.

EXPERIENCE:
----------

  -- System Analyst (6/88--Present)          Michigan State University 

     I have extensive experience managing a network of PCs, MACs and a 
     HP3000-922 for the College of Osteopathic Medicine.  In addition, 
     I also developed several information systems on HP-922 in 
     Speedware/4GL.

  -- Research Assistant (3/89--9/89)         Michigan State University 

     Solving a system of polynomials is an importment and fundamental 
     technique  to  a  large  class  of  scientific  and  engineering 
     applications.  The  traditional methods  on  serial machines are 
     extremely  time-consuming.  I developed a parallel algorithm for 
     Homotopy  method on  a 64-node  nCUBE machine  which  applies an 
     efficient  merge checking  and rollback procedure to speedup the 
     computation.

  -- Project Leader (3/86--3/87)            Mitac Computer Organization 
                                                         Taipei, Taiwan 

     I have directed the research and development for Chinese PCs and 
     its communication software to VAX and IBM mainframe.  I overcame 
     the  difficulty  of Chinese I/O  for  IBM mainframe  without any 
     internal technical support from IBM. 

  -- System Engineer (7/84--3/86)                  China Computer Corp. 
                                                         Taipei, Taiwan

     Developed and maintained a Chinese information system on VAX/VMS 
     which includes Chinese printing system,  Chinese word processor, 
     and Chinese terminal. 

  -- Assistant Researcher (6/83--7/84)  Industry Technical Research Lab. 
                                                        Hsin-Chu, Taiwan

     I participated in  the design of  a Computer  Numerical Controller 
     (CNC)  which is  composed of  two MC-68000  processors and  a Z-80 
     processor. This project included the hardware design, an operating 
     system and  the numerical  control program for a Machining Center. 
     Techniques of the  project  have been  successfully transferred to 
     several companies in industry. 


PUBLICATIONS:
------------

    "Dependence Uniformization: A Loop Parallelization Technique"
     (with L.~M.~Ni),
     accepted by IEEE Transactions on Parallel and Distributed Systems 
     and International Conference on Parallel Processing, August 1992.

    "Trapezoid Self-Scheduling: A Practical Scheduling Scheme for 
     Parallel Compilers" (with L.~M.~Ni), 
     accepted by IEEE Transactions on Parallel and Distributed Systems. 

    "Dynamic Loop Scheduling for Shared-Memory Multiprocessors"
     (with L. M. Ni), Proceedings of the 1991 International Conference 
     on Parallel Processing, August 1991.

    "Resource Contention in Shared-Memory Multiprocessors: A 
              Parameterized Performance Degradation Model"
     (with A.~Nanda, H.~Shing and L.~M.~Ni),
     Journal of Parallel and Distributed Computing, July 1991.

    "A Replicate Workload Framework to Study Performance Degradation 
     in Shared-Memory Multiprocessors"
     (with A.~Nanda, H.~Shing and L.~M.~Ni), Proceedings of the 1990 
     International Conference on Parallel Processing}, August 1990. 

    "PowerCube: A Software Package for Solving Load Flow Problems"
     (with L.~M.~Ni, F.~Salam, and X.~H.~Sun), Proceedings of the 32rd 
     midwest Symposium on Circuit and Systems, August 1989.

    "A Universal Simulator for Parallel Architectures"
     (with H.~Shing and T.~Y.~Chang),
     Technical Report MSU-CPS-88-11, June 1988.

MAJOR PROJECTS:
--------------

    --  A Loop Transformation Tool for Multiprocessors: (ongoing)
    This  project  studies  the  data dependence  analysis  and  loop 
    transformation techniques for multiprocessors.  A simple language 
    is designed in which  arbitrary nested loops can be  represented.  
    Several  dependence  tests  are  applied  to  extract  dependence 
    relation between loops, iterations and statements.  This  project  
    is implemented in object-oriented approach (C++).

    -- A Performance Degradation Modeling for Multiprocessors:
    This project studies the performance degradation in shared-memory
    multiprocessors  as a result  of contention for shared resources.  
    A replicate  workload  framework with  a flexible  mechanism  for 
    workload specification is proposed for measuring performance. The 
    proposed model  has been  successfully  employed to  measure and 
    compare the performance of BBN GP1000, BBN TC2000, and Sequent 
    Balance.

    -- A Universal Simulator for Parallel Architectures:
    This project introduces a description language for defining pseudo 
    SIMD machines and  systolic arrays with various connectivities and 
    topologies.  With some extension  to C language, SIMD and systolic 
    array computation can be simulated. Algorithms for some well-known 
    problems have  been  simulated on  pseudo  machines  with  various 
    topologies including  mesh, hypercube, CCC, etc.

    -- A Parallel Hashing Data Base:
    This project studies the parallel hashing algorithm for 
    distributed data bases.  It applies linear hashing for insert and 
    delete operations, and allows concurrent accesses from different 
    processors. 

    -- An Error-Free Simulation Model For Ethernet:
    For most of Ethernet simulation models, the propagation delay is
    assumed to be a constant.  To exactly evaluate the throughput and 
    normalized delay, in this model, the configuration of Ethernet can 
    be  flexibly  defined by  system  parameters which  include signal 
    velocity,  network bandwidth,  interframe time, backoff delay, and 
    so on.


ACTIVITIES:
----------

    Member, IEEE Computer Society. 
    President, Chinese Student Association in MSU, 9/1988--6/1989. 


REFERENCES:
----------

    Available upon request.