HDTenEightyP/NetNews huggingface dataset:
From: bowman@csrp.tamu.edu (Kenneth P. Bowman)
Newsgroups: comp.lang.idl-pvwave
Subject: Floating point system variables on RS6000
Followup-To: comp.lang.idl-pvwave
Date: 23 Nov 1992 22:19:03 GMT
Organization: Texas A&M University
Distribution: world
NNTP-Posting-Host: bowman.tamu.edu

Due to some underflow problems, I have noticed that the system variables
!DTOR, !PI, and !RADDEG are floats.  Since all arithmetic on the RS6000 is
done in double precision, is there any reason not to store these as double
precision?  Aside from the improved precision, it would obviate the need
for the (invisible) conversion fromfloat to double at the system level. 
(I know there is a !DPI double precision system variable.)

---------------------------------------------------------------------------
Dr. Kenneth P. Bowman                          409-862-4060
Climate System Research Program                409-862-4132 fax
Department of Meteorology                      bowman@csrp.tamu.edu
Texas A&M University
College Station, TX   77843-3150
From: Albert.Koelmans@newcastle.ac.uk (Albert Koelmans)
Newsgroups: comp.lang.vhdl
Subject: Re: Papers on hardware verification?
Date: 20 Nov 92 09:26:00 GMT
Organization: University of Newcastle upon Tyne, UK, NE1 7RU

S_KARL@iravcl.ira.uka.de (|S| Holger Karl) writes:


>I know this isn't the very proper newsgroup for this question, but is anybody
>out there able to tell me about papers on other publications concerning the
>verification of hardware using abstract methods like higher order logic or
>sequent calculus? Any hints would be highly appreciated! If this seems
>interesting to more people, I will collect the answers and post them.

Check out the Springer and North-Holland catalogues. You'll find several
conference proceedings of interest.

--

E-mail address:  Albert.Koelmans@newcastle.ac.uk
Computing Science Department, University of Newcastle upon Tyne,
Newcastle upon Tyne, NE1 7RU, UK (telephone +44 091-2228155,fax 2228232)
From: strataki@cerberus.csi.forth.gr (Manolis Stratakis)
Newsgroups: comp.lang.vhdl
Subject: Verilog LSI/MSI libs?
Date: 20 Nov 1992 10:42:56 GMT
Organization: FORTH - ICS, P.O.Box 1385, Heraklio, Crete, Greece 71110 
       tel: +30(81)221171, 229302 fax: +30(81)229342,3 tlx: 262389 CCI
Distribution: world
NNTP-Posting-Host: cerberus.csi.forth.gr


	Hello,

	does anyone know, if there are any LSI and/or 
	MSI libraries for Verilog, and how could we 
	obtain them?

	Please reply by e-mail.

	Thanks in advance,
	Manolis Stratakis.

Xref: sparky comp.lang.vhdl:540 comp.lang.verilog:440
From: dominick@protocol.zycad.com (Dom Paniscotti)
Newsgroups: comp.lang.vhdl,comp.lang.verilog
Subject: Wanted: VHDL to Verilog Translator
Keywords: VHDL Verilog translator
Date: 20 Nov 92 21:24:27 GMT
Reply-To: dominick@protocol.zycad.com
Organization: Protocol, a Division of ZYCAD Corporation
NNTP-Posting-Host: hayaku.protocol.zycad.com


Does anyone know where I could find a behavioural VHDL to
Verilog translator?  or possibly a yacc grammar for VHDL? 

                Thanks in advance,
                        Dom
Newsgroups: comp.lang.vhdl
From: jcooley@world.std.com (John Cooley)
Subject: E-mail Synopsys Users Group
Organization: The World Public Access UNIX, Brookline, MA
Date: Wed, 18 Nov 1992 09:21:12 GMT


  If you're using the Synopsys Design Compiler and/or their ATPG product, you 
  might be interested in joining the E-Mail Synopsys Users Group (ESNUG).

  What we are is a group of hardware designers from all over the world who
  wish to trade experiences, bug reports and the techniques that we've
  found that work best in getting a design from a behavioral description
  to a final fully tested product.

  A Sample of What We Discuss:

	- Known Synopsys Compiler Bugs    - Implementing Boundry Scan

	- Mentor related issues    - EDIF related issues

	- Hierarchical Compliations   - design_analyzer   - JTAG

	- How Various ASIC Vendors Model Their Macros.   - Clock Constraints

	- Using ATPG Tools   - The Best Way To Write State Machines in Verilog

	- Using VHDL   - System Simulation vs. Synopsys Friendly Code

	- Clever Workarounds to Known Pitfalls   - Testing Strategies

  In order to insure an open discussion, but yet keep our respective managers
  happy in having our company's projects remain SECRET, submissions to be 
  posted to the ESNUG mailing list can be stripped of identifying engineers 
  and company names if so requested.

  In addition, to further secure privacy and to avoid e-mail headers that
  are hundreds of names long, each mailing is a batch of singlely addressed 
  e-mail letters.

  If you know of anyone who may be interested in this, please give them
  my e-mail address (jcooley@world.std.com or jcooley@miracle.com) or you can 
  send me their address!
					- John Cooley
					  ESNUG Moderator

 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
     /o o\  /  it's a FEATURE!"   |    Backup Address: jcooley@miracle.com
    (  >  )                       |              (508) 429-4357
     \ - /       |   Snail Mail: P.O. Box 6222, Holliston, MA 01746-6222
     _] [_       |     "This here ain't no one's opinion 'cept my own."


From: gotom@hpysoln.tky.hp.com (Masaharu Goto)
Date: Thu, 19 Nov 1992 16:35:39 GMT
Subject: HELP:Verilog to VHDL translator
Organization: YHP Hachioji IT, Tokyo Japan
Newsgroups: comp.lang.vhdl


Subject: Verilog-HDL to VHDL translator

 Does anyone have information or experience about Verilog-HDL to VHDL 
translator?  

 My situation is

 I am designing an IC using Verilog-XL simulator.  On the other hand 
We will buy Mentor QuickSim2 for PC board simulation. It is very nice if
I could simulate the PC board with QuickSim2 including IC behavior model I 
write in Verilog.
 We will start the board simulation next April. I don't require
full timing simulation. Bulk delay simulation or even unit delay simulation
is still OK.  This time, purpose of the trial is pilot run of the Mentor
system rather than design verification itself. 

 Any kind of information/suggestions are appreciated.
From: eli@netcom.com (Interpretive Systems)
Subject: Re: HELP:Verilog to VHDL translator
Summary: A Verilog to VHDL translator is available from interHDL Design Corp
Organization: Netcom - Online Communication Services (408 241-9760 guest)
Date: Mon, 23 Nov 1992 23:20:24 GMT


A Verilog to VHDL translator is available from interHDL Design Corp,
1270 Oakmead PkWy #209, Sunnyvale, CA 94086
Tel (408) 749-8775, FAX (408) 749-8823
Newsgroups: comp.lang.vhdl
From: grabay@dit.upm.es (Gualberto Rabay Filho)
Subject: VHDL and LOTOS
Organization: Dept. Ingenieria de Sistemas Telematicos, UPM, Madrid, Spain.
Distribution: comp.lang.vhdl
Date: Tue, 17 Nov 1992 15:48:48 GMT


I am a PhD student at Tech. University of Madrid and  I am interested
in formal specification themes.

Nowadays I am  working in two tasks:
- Specification of Hardware using LOTOS (ISO Language). 
- Translation from LOTOS to VHDL.

I would like to contact other persons who are working in these
subjects to change ideas and experiences.

Yours sincerely

Gualberto Rabay 

----------------------------------------------------------------
* Gualberto Rabay Filho  
* U.Politecnica de Madrid * ETSIT - Depto. de Ing. Telematica  
* Ciudad Universitaria      * 28040 -  Madrid -SPAIN 
* phone:(34-01) 5495762     * ext: 442 
* email: grabay@buho.dit.upm.es   *                         
----------------------------------------------------------------
From: S_KARL@iravcl.ira.uka.de (|S| Holger Karl)
Newsgroups: comp.lang.vhdl
Subject: Papers on hardware verification?
Date: 19 Nov 92 13:06:03 GMT
Organization: University of Karlsruhe (FRG) - Informatik Rechnerabt.
NNTP-Posting-Host: irav1.ira.uka.de
X-News-Reader: VMS NEWS 1.23


Hi, 
I know this isn't the very proper newsgroup for this question, but is anybody
out there able to tell me about papers on other publications concerning the
verification of hardware using abstract methods like higher order logic or
sequent calculus? Any hints would be highly appreciated! If this seems
interesting to more people, I will collect the answers and post them.

Thanks 
Holger Karl
From: rknight@gec-rl-hrc.co.uk (Roger Knight (B21))
Newsgroups: comp.lang.vhdl
Subject: Re: Subset of VHDL for synthesis.
Keywords: VHDL Synthesis portability
Date: 18 Nov 92 19:53:47 GMT
Organization: GEC Hirst Research Centre

In article <3200@ucl-cs.uucp> you write:
>
>I believe there is a group (VHDL Synthesis Working Group in Europe???) that
>is trying to specify this subset.
>
If you are interested in writing portable VHDL then a subset of
the syntax is not very useful. The most important area were
the synthesis tools differ is in the interpretation of semantics.

For example we are using Mentor's AutoLogic and working with customers
who have Racal and Synopsys.  The Racal user doesn't think our VHDL
will synthesise well on SilcSyn because it doesn't do resource
sharing and so the same (large) adder would be built separately
for each decode in the controlling state machine. AutoLogic builds
a single adder cells and multiplexes the input where needed.  They've
also found nested IF's don't give good results on Racal so avoid
using them.  We've never had that sort of problem and use netsted
IF's all the time.

Even clock recognition is not simple. We have described clocks
as IEEE 1164 9-state logic and used the syntax:-
   IF clk = '1' AND clk'LAST_VALUE = '0' AND clk'EVENT THEN
This tells AutoLogic the clock has changed and is a rising edge.
Unfortunately when our customer tried to compile it under Synopsys
he had to remove the 'LAST_VALUE test. OK using 'LAST_VALUE is pedantic 
but logically more correct since a 'X' to '1' transition is not a rising
edge and so without the 'LAST_VALUE test there could be differences
between a VHDL simulation and synthesised logic's behaviour when
a 'X'-->'1' vector is applied to a clock.

There are also incompatibilities in the way arithmetic is interpreted.
Should bit level values be magnitude or 2's complement? How do you
define overflow in arithmetic operations? A VHDL simulator will
report a run-time error on overflow but the synthesised logic can't!
Would the logic wrap around through zero, reset or go to some
random undefined value?

The good news is Synopsys, Mentor and Viewlogic are supposed to
be working together on a unified arithmetic library for the IEEE
1164 logic type ( the IEEE only defined logical operations on the
type).  I just hope its not too diferent from the arithmetic which
Mentor have already implemented! 

Roger Knight                   rknight@gec-rl.hrc.co.uk
VHDL ASIC Design Group
Hirst Research Centre,
GEC-Marconi Ltd.

DISCLAIMER: I said it not my company.If any of the above is bu****t,
misleading or just plain wrong - thats your problem not mine.
Newsgroups: comp.lang.vhdl
From: lma@dayton.Stanford.EDU (Larry Augustin)
Subject: Re: 3rd Party Verilog Compilers
Organization: DSO, Stanford University
Distribution: usa
Date: 17 Nov 92 00:19:29 GMT

jwest@wisc (Jeff West) writes:

>bjdunlop@shamash.cdc.com (Bruce Dunlop) writes:
>: 
>: A company called Chronologic Simulation was mentioned as having a fast
>: verilog compiler, in a previous post here.  Can someone give me their
>: phone number?
>: 
>: Also, does anyone have any good/bad experiences with it?
>: 

>Contact:
>  Craig Combes
>  Chronologic
>  (415)965-3312

Fintronic claims to have a very fast Verilog simulator.  Contact Alec
Stanculescu (alec@fintronic.com), (415) 325-4474.

Larry
From: jwest@wisc (Jeff West)
Newsgroups: comp.lang.verilog
Subject: Re: 3rd Party Verilog Compilers
Date: 16 Nov 92 19:28:59 GMT
Distribution: usa
X-Newsreader: Tin 1.1 PL3

bjdunlop@shamash.cdc.com (Bruce Dunlop) writes:
: 
: A company called Chronologic Simulation was mentioned as having a fast
: verilog compiler, in a previous post here.  Can someone give me their
: phone number?
: 
: Also, does anyone have any good/bad experiences with it?
: 

Contact:
  Craig Combes
  Chronologic
  (415)965-3312
From: Scott.Johnson@FtCollinsCO.NCR.COM ( Scott Johnson)
Newsgroups: comp.lang.verilog
Subject: Re: Does Cadence still exist?
Date: 17 Nov 92 10:32:51 GMT
Organization: NCR Microelectronics, Ft. Collins, CO
In-reply-to: kenh@leps5.phys.psu.edu's message of 16 Nov 92 05:34:26 GMT

>>>>> On 16 Nov 92 05:34:26 GMT, kenh@leps5.phys.psu.edu (Ken Hornstein) said:
K> Nntp-Posting-Host: leps5.phys.psu.edu

K> I tried calling the number I have for Cadence, but it was disconnected.  Is
K> Cadence still in existance?  If so, could someone post/e-mail me their
K> number?  If not, does anyone know of anyone who has taken over support
K> for Verilog?

K> Thanks,

K> --Ken

Their hotline support number is 1-800-CADENC2 (This is from memory, but
I believe correct) as long as you are paying maintenance, you should get
support.

--
-----------------------------------------------------------
E-Mail:  Scott.Johnson@FtCollinsCO.NCR.com
	 uunet!ncrlnk!ncr-mpd!Scott.Johnson
My opinions are mine and mine alone (unless I only live in your dream, in
which case they are yours and I denounce all responisbility).
GA to SK
From: hendrix@haber.Eng.Sun.COM (George Haber)
Newsgroups: comp.lang.verilog
Subject: Re: Wanted: VHDL to Verilog Translator
Date: 23 Nov 1992 20:20:57 GMT
Organization: Sun Microsystems, Inc.
Distribution: world
Reply-To: hendrix@haber.Eng.Sun.COM
NNTP-Posting-Host: haber

	Try InterHDL Systems they have a Verilog -> VHDL translator

		Phone	408 749 8775
		Fax	408 749 8823

George
From: cindy@zoran.hellnet.org (Cindy Eisner)
Newsgroups: comp.lang.verilog
Subject: Re: Avoiding inertial delay in delay lines
Date: 18 Nov 92 06:16:17 GMT
Organization: Zoran Microelectronics LTD. Haifa, Israel.

In article <1992Nov16.163807.15366@dsg.tandem.com>, leung@DSG.Tandem.COM (Steven Leung) writes:
> 
> 
> BTW, putting the delay after the assignment operator appears to have
> some effects on scheduling. Even "a = #10 b;" has some difference from
> "#10 a = b;". (Don't know whether this is considered as a bug though.)
> 

look in the manual.  "a = #10 b;" means sample b NOW, and assign its value to
a in 10 time units.  on the other hand, "#10 a = b;" means wait 10 time units
starting from now, and then sample b and immediately assign the sampled value
to a.  

parts of this discussion seem to have passed my news feed by, but from what
i gather, using "a <= #10 b;" (non-blocking) should work for the original 
poster, since it will schedule the current value of b to be assigned in another
10 time units.  in the meantime, if b changes, before the 10 time units is up,
say at time 3, verilog will be free the execute the assignment again, and 
schedule another assignment at time 3+10=13.  

notice:  1.  you must use a non-blocking assignment, with the delay after
             the equals

         2.  you must make sure that the current always statement does not
             contain (other) blocking assignments which will mess up the
             scheduling of this assignment.  

hope this helps.

cindy.

-- 

    Cindy Eisner,                     Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: cindy@Zoran.HellNet.Org
    Advanced Technology Center
    Haifa 31204, Israel               Could be my employer doesn't agree.
From: gotom@hpysoln.tky.hp.com (Masaharu Goto)
Date: Thu, 19 Nov 1992 16:34:47 GMT
Subject: HELP:Verilog to VHDL translator
Organization: YHP Hachioji IT, Tokyo Japan
Newsgroups: comp.lang.verilog


Subject: Verilog-HDL to VHDL translator

 Does anyone have information or experience about Verilog-HDL to VHDL 
translator?  

 My situation is

 I am designing an IC using Verilog-XL simulator.  On the other hand 
We will buy Mentor QuickSim2 for PC board simulation. It is very nice if
I could simulate the PC board with QuickSim2 including IC behavior model I 
write in Verilog.
 We will start the board simulation next April. I don't require
full timing simulation. Bulk delay simulation or even unit delay simulation
is still OK.  This time, purpose of the trial is pilot run of the Mentor
system rather than design verification itself. 

 Any kind of information/suggestions are appreciated.
From: strataki@cerberus.csi.forth.gr (Manolis Stratakis)
Newsgroups: comp.lang.verilog
Subject: Verilog LSI/MSI libs?
Date: 20 Nov 1992 10:40:44 GMT
Organization: FORTH - ICS, P.O.Box 1385, Heraklio, Crete, Greece 71110 
       tel: +30(81)221171, 229302 fax: +30(81)229342,3 tlx: 262389 CCI
Distribution: world
NNTP-Posting-Host: cerberus.csi.forth.gr


	Hello,

	does anyone know, if there are any LSI and/or 
	MSI libraries for Verilog, and how could we 
	obtain them?

	Please reply by e-mail.

	Thanks in advance,
	Manolis Stratakis.
From: pbrans@netxcom.netx.com (Pat Brans)
Newsgroups: comp.lang.verilog
Subject: Contacting Verilog
Date: 16 Nov 92 17:27:52 GMT
Distribution: usa
Organization: NetExpress Inc., Vienna, VA, USA

Does anyone know email addresses for the company Verilog ?
I'd like to get in touch with them.

____
Pat Brans.


Newsgroups: comp.lang.verilog
From: eli@netcom.com (Interpretive Systems)
Subject: Re: HELP:Verilog to VHDL translator
Summary: Verilog to VHDL translator is available from interHDL
Organization: Netcom - Online Communication Services (408 241-9760 guest)
Date: Mon, 23 Nov 1992 23:14:31 GMT


A translator from Verilog to VHDL is available from interHDL Design Corp.
1270 Oakmead PkWy, #209, Sunnyvale, CA 94086
Tel (408) 749-8775, FAX (408) 749-8823
Newsgroups: comp.lang.verilog
From: jcooley@world.std.com (John Cooley)
Subject: Invite to Join ESNUG
Organization: The World Public Access UNIX, Brookline, MA
Date: Wed, 18 Nov 1992 09:20:17 GMT


  If you're using the Synopsys Design Compiler and/or their ATPG product, you 
  might be interested in joining the E-Mail Synopsys Users Group (ESNUG).

  What we are is a group of hardware designers from all over the world who
  wish to trade experiences, bug reports and the techniques that we've
  found that work best in getting a design from a behavioral description
  to a final fully tested product.

  A Sample of What We Discuss:

	- Known Synopsys Compiler Bugs    - Implementing Boundry Scan

	- Mentor related issues    - EDIF related issues

	- Hierarchical Compliations   - design_analyzer   - JTAG

	- How Various ASIC Vendors Model Their Macros.   - Clock Constraints

	- Using ATPG Tools   - The Best Way To Write State Machines in Verilog

	- Using VHDL   - System Simulation vs. Synopsys Friendly Code

	- Clever Workarounds to Known Pitfalls   - Testing Strategies

  In order to insure an open discussion, but yet keep our respective managers
  happy in having our company's projects remain SECRET, submissions to be 
  posted to the ESNUG mailing list can be stripped of identifying engineers 
  and company names if so requested.

  In addition, to further secure privacy and to avoid e-mail headers that
  are hundreds of names long, each mailing is a batch of singlely addressed 
  e-mail letters.

  If you know of anyone who may be interested in this, please give them
  my e-mail address (jcooley@world.std.com or jcooley@miracle.com) or you can 
  send me their address!
					- John Cooley
					  ESNUG Moderator

 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
     /o o\  /  it's a FEATURE!"   |    Backup Address: jcooley@miracle.com
    (  >  )                       |              (508) 429-4357
     \ - /       |   Snail Mail: P.O. Box 6222, Holliston, MA 01746-6222
     _] [_       |     "This here ain't no one's opinion 'cept my own."
From: smb@afterlife.ncsc.mil (Steve M. Burinsky)
Newsgroups: comp.lang.verilog
Subject: Re: Avoiding inertial delay in delay lines
Date: 16 Nov 92 04:52:05 GMT
Organization: The Great Beyond

In article <1992Nov12.163116.17205@dsg.tandem.com> leung@DSG.Tandem.COM (Steven Leung) writes:
>
>	a <= #10 b;	/* transport delay */
>

I cannot see why a non-blocking assignment should operate any differently
than a blocking assignment in terms of how events are scheduled.  Thus,
I expected that the above would not work.  However, it does, as does

	#10 a <= b;

I cannot see why this should work.  Anyone have an explanation?
-- 

Steve M. Burinsky
smb@afterlife.ncsc.mil
Newsgroups: comp.lang.verilog
From: swood@bnr.ca (Steve Wood)
Subject:  Memory Addressing in verilog
Originator: swood@bcrks50
Keywords:  address, register array, bounds check
Reply-To: swood@bnr.ca (Steve Wood)
Organization: Bell-Northern Research, Ltd
Date: Wed, 18 Nov 1992 18:19:33 GMT


I am trying to write a behavioural model for a family of modular 1- and
2-port memories and am new to the verilog language.  

I have been experimenting with "writing" (i.e. procedural assignment to
a memory register array) to the memory array with array index (address) set to "X".
Such a condition is a serious error in a real memory, however verilog seems
to ignore any out of range or unknown index when it is part of the LHS of a
procedural assignment.

My question is: does verilog do any bounds checking on index values to register
                arrays or do I have to implement such checks myself?
-- 
regards,

============================================================================================
Steven Wood			Phone: 613-763-2830
Memory Development		ESN:     6-393-2830
Bell Northern Research          Email: swood@bnr.ca (internet)
============================================================================================
From: kenh@leps5.phys.psu.edu (Ken Hornstein)
Newsgroups: comp.lang.verilog
Subject: Does Cadence still exist?
Date: 16 Nov 92 05:34:26 GMT
Organization: Penn State, Laboratory for Elementary Particle Science

I tried calling the number I have for Cadence, but it was disconnected.  Is
Cadence still in existance?  If so, could someone post/e-mail me their
number?  If not, does anyone know of anyone who has taken over support
for Verilog?

Thanks,

--Ken
Newsgroups: comp.lang.verilog
From: dicks@cfsmo.honeywell.com (Richard D. Schlotfeldt)
Subject: Does OVI read mail?
Organization: J. Random Misconfigured Site
Date: Mon, 23 Nov 1992 22:37:44 GMT
X-Newsreader: TIN [version 1.1 PL6]
X-Posted-From: sun3a-hyde.honeywell.com
NNTP-Posting-Host: sol.ctr.columbia.edu

Does anyone read mail sent to ovi@netcom.com? I have sent mail
a couple times, but have never received a response or results.
Most recently I asked to be added to the mailing list for
the monthly newsletter.

Dick Schlotfeldt
2470 Cohansey Street
Roseville, MN 55113
From: bjdunlop@shamash.cdc.com (Bruce Dunlop)
Newsgroups: comp.lang.verilog
Subject: Re: emacs verilog mode
Date: 18 Nov 92 02:45:56 GMT
Organization: Control Data Corporation, Arden Hills, MN

In article <1992Nov14.172220.16606@zip.eecs.umich.edu> riepe@quip.eecs.umich.edu (Michael Anthony Riepe) writes:
>I have seen several requests for an emacs verilog mode go past this
>group, but no-one ever posted a reply.  If this is a FAQ, I apologize,

I received a couple of replies by email, but maybe they weren't posted here.
I wrote one myself, or more exactly, I hacked up ada mode to make a ver-mode.
There were two other replies, one from someone at Cadence ( I apoligize for
forgetting the names).  I have these, but neither one worked for me, because
I use Lucid lemacs.  I think the Cadence person was going to post a new
version here soon.  I could post mine if anyone is interested.

********************************************************************
*   Jim Dahlberg		 Computing Devices International   *
*   bjdunlop@shamash.cdc.com		A Ceridian Company         *
********************************************************************