From: alheid@sedist.cray.com (Greg Alheid)
Subject: Re: differences between "normal" IBM PC compatible and IBM PS/2
Organization: Cray Research, Inc.
Date: 14 Aug 92 19:25:53 CDT

  This is a correction to my orginial posting. Sorry, I should have 
had the book to do this with in the first place, 8^(

  The book I am NOW referencing is:
 _THE MICROCHANNEL ARCHITECTURE HANDBOOK_ 
 by Chet Heath and Winn L. Rosch
 A Brady Book, Distributed by Prentice Hall Trade
 ISBN 0-13-583493-7
 COPYRIGHT 1990 (close to 2 years old)

|> 
|>   The bus for the IBM PC and AT is now know as ISA bus, (Industry
|> Standard Arch). The problems with the ISA bus and how the PS/2 and 
|> MCA bus (Micro Channel Arch.) solved them are:
|> 
|>  - ISA uses edge triggered interrupts, unable to share interuppts.
|>  + MCA uses level triggered interrupts, allowing shared interuppts.
|> 

  The following is in error:

|>  - ISA is limited to 12 address lines for I/O devices, 4096 device
|>     addresses but each device can take four at least, so more like
|>     only 1024 "devices". But the system consumes something like the
|>     first 512 devices for necessary system functions.
|>  + MCA has 16 address lines for I/O devices, so it has 65,536 device
|>     addresses, but again more like 16,384 devices. System still
|>     needs the first 512 devices but it is not as noticeable.  8^)

   The corrected statements are:

  - Orginial ISA boards used only 10 address lines to decode an 
     I/O device, constraining the ISA bus to 1024 device addresses.
     Of that the system uses most of the first 256 devices address 
     leaving 768 devices addresses. But each "I/O device" can take 
     three device address for command, status and data, so there is 
     more like a limit of about 256 "I/O devices".
  + MCA boards are required to use 16 address lines to decocode an 
     I/O devices address, so MCA is capble of 65,536 device addresses.
     But again the system uses most of the first 256 devices address. 
     This leaves 65,280 device addresses to use. If three device 
     address are used (cmd-status-data), only 21,760 "I/O devices".
|>
|> 
|>  - ISA has noisy signal lines (lack of "good" grounding) which can
|>     be a source of strange problems.
|>  + MCA has more ground signals between data, so is less noisy.
|> 

  The following is in error:

|>  - ISA is "normally" 8 Mhz and can only transfer two bytes every
|>    two clock periods, so 8 Mbytes max. transfer rate. 
|>  + MCA is "16 Mhz minimun, and can with "burst" transfers can go
|>    over 50 MBytes a sec. (Don't really remember what current max
|>    value is.)

   The corrected statements are:
 
  - ISA is "normally" 8 Mhz and can only transfer two bytes every
    three clock periods, (adr-wait-data) giving a 5.3 Mbytes/sec
    transfer rate. The ISA bus has been run as fast 12.5 MHz, which 
    will give a 8.3 MBytes/sec. max. transfer rate.
  + MCA bus"normally" runs at 10 MHz, but the book "hints" that
    the bus is not constrained in this and could run at 20 Mhz in
    the future. There are also several `transfer modes' available, 
    burst, streaming and multiplexed streaming I/O transfers as well 
    as a matched memory cycle for CPU r/w that can be implemented. 

     The maximium transfer rates on a 10 MHz MCA bus:

                                 16-bit MCA       32-bit MCA
     Normal transfers           10MBytes/sec     20 MBytes/sec
     (adr/data)

     short Burst and long
     Streaming transfers        20MBytes/sec     40 MBytes/sec
     (adr/data data data ..)

     Multiplex Streaming       (not available)   80 MBytes/sec
     (as above and uses the
      `idle' adr lines to 
      transfer data as well, 
      for a 64-bit transfer)

     Matched Memory cycle                        21.3 MBytes/sec
     (matched memory cycle
      changes the timing of                     (32 MBytes/sec w/o
      the MCA bus to 62.5                        added wait state
      nanosec. for a 187.5                       at 62.5 Nanosec.
      4 byte adr-wait-data                       and 40 MBytes/sec
      transfer cycle. This                       with 50 nanosec
      is on a 16 Mhz model                       timing)
      80 as an example.)

|>   There are several other problems of the ISA bus solved by the
|> PS/2 and MCA design but I would have to copy them from a book to
|> get them technically right.

   I had to check the book to get these corrections! The book lists 
mechcanical problems of insertion forces, which can cause problems 
with bending the motherboard. Also being able to disable an I/O
board that fails.

|> 
|>   Also PS/2s also have a Watchdog timer which will cause a NMI and
|> will allow the system to recover from program loops and "some" other
|> possible causes of system hangs. But the software to do has to be
|> available like it is in OS/2. (This feature is not dependent on the
|> MCA design)
|> 
|> 

-- 
____________________________________________________________________
| Greg Alheid               |  Everything is going well so I am    |
| alheid@pittpa.cray.com    |  not sure what the problem is.   8^) |
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