From: dcp79807@csie.nctu.edu.tw ()
Subject: Summary of Trace Generator (LONG)!
Organization: Computer Science & Information Engin., Chiao-Tung U, Taiwan, ROC
X-Newsreader: TIN [version 1.1 PL6]
Date: Mon, 16 Nov 1992 09:16:18 GMT




Dear Netter:

	This is the summary of the responses to my previous question about
trace generation.  Thanks to the following people answering my question!

	Jeff Hollingsworth
	Tien-Fu Chen
	Ruth S.
	David Chaiken
	Andreas Krall

Miller Lin

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	
From hollings@cs.wisc.edu Wed Nov 11 13:24:02 1992
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Date: Tue, 10 Nov 92 23:22:33 -0600
From: hollings@cs.wisc.edu (Jeff Hollingsworth)
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To: dcp79807@csie.nctu.edu.tw
Subject: Re: Trace generator wanted (Uniprocessor or MP)!!
Newsgroups: comp.os.research
Organization: University of Wisconsin, Madison -- Computer Sciences Dept.
Cc: 
Status: OR


I know of AE and QP from the University of Wisconsin.  They are available for
anonymous ftp from primost.cs.wisc.edu.

-- 
-------------------------------------------------------------------------------
Jeff Hollingsworth					Work: (608) 262-6617
Internet: hollings@cs.wisc.edu				 FAX: (608) 262-9777
Home: hollings@warthog.madison.wi.us			Home: (608) 256-4839
X.400: <pn=Jeff.Hollingsworth;ou=cs;o=uw-madison;prmd=xnren;c=US>

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

From tchen@cs.washington.edu Thu Nov 12 10:00:02 1992
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Date: Wed, 11 Nov 92 17:55:49 -0800
From: tchen@cs.washington.edu (Tien-Fu Chen)
Return-Path: <tchen@cs.washington.edu>
Message-Id: <9211120155.AA13155@june.cs.washington.edu>
To: dcp79807@csie.nctu.edu.tw
Subject: RE: Trace generator wanted (Uniprocessor or MP)
Status: OR


Regarding MP, the following message posted couple of months ago
may be helpful to you. As to UP, I'd suggest to use "pixie" tool
in most of DecStations. If you have any question, feel free to
let me know.

BTW, I'd like to inquire about one person from you. Do you know
a person called "Wu3 Chong1 Cheng"? He is my classmate in Taiwan University.
As far as I know, he got a MS from Chung Hsing U. and a Ph.D student
in your department. But I am not aware of whether he graduated or not.
If you happened to know him, can you pass my e-mail address to him?
I'd like to contact him. Thanks a lot.


Tien-Fu Chen (tchen@cs.washington.edu)
Department of Computer Science and Engineering
University of Washington
Seattle, WA 98195



-------------- cut (previously saved message) -----------
Newsgroups: comp.parallel
From: govindr@pike.ee.mcgill.ca (Govind Ramaswamy)
Subject: Re: Parallel Architecture Simulators - Summary (Long)

Hi!

In the first place, thanks to everyone who responded to my earlier 
posting in the net! In particular thanks to the following who 
provided information on the parallel architecture simulators
available by anonymous ftp.  

> Nan C Schaller (ncs@cs.rit.edu)

> David Kotz (dfk@wildcat.dartmouth.edu)

> Jihong Kim (jihong@cs.washington.edu )

> Walt Ligon (walt@cc.gatech.edu)

> Jaswinder Pal Singh (jps@samay.stanford.edu)

> Stefan Engelhardt (Engelhardt@informatik.uni-stuttgart.dbp.de)

> Marshall Brain (brain@eos.ncsu.edu)

> Jim Burrill (burrill@aai.com)

> Hemant Rotithor (hemant@wpi.WPI.EDU)

> George Wilson (gwilson@umiacs.UMD.EDU)

> Zhongyun Zhang (zz@cs.princeton.edu)

> Stephen Goldschmidt (comments@meadow.stanford.edu)


Lastly, I received at least 10 requests to post a summary in the 
net. So here it is:

Thanks again to every one,
Govind
=-----------------------------------------------------------=
Govindarajan Ramaswamy		      Ph: (514) 398 8169 (O)
VLSI Design Laboratory		          (514) 287 8964 (H)
Electrical Engineering	             
McGill University                     Fax: (514) 398 4470
3480 University Street	              
MONTREAL, H3A 2A7, Canada	govindr@pike.ee.mcgill.ca
=-----------------------------------------------------------=


___________________________________________________________________

  THE  P A R A L L A X I S  MASSIVELY PARALLEL PROGRAMMING SYSTEM
___________________________________________________________________

             -----------------------------------
              Announcing Parallaxis Version 2.0
             -----------------------------------

Parallaxis is a procedural programming language based on Modula-2, but extended
for data parallel (SIMD) programming. It has been developed at the Universitaet
Stuttgart (Germany) and is in the public domain since 1990. The main approach
for machine independent parallel programming is to include a description of the
virtual parallel machine with each parallel algorithm. The declaration includes
the number of identical processors with local memory (PEs), the names of
communication ports, and the network topology for data exchange among PEs. With
this information contained in each program, the parallel algorithm becomes
simpler (e.g. symbolic names for communication directions) and easier to
understand.

In Version 2 we extended the language in several ways:
  o multiple configuration and connection structures allow
    semi-dynamic topologies
  o new data exchange operations for exchanging data with inactive PEs
    and with implicit reductions allow general m:n connections
  o data structures pointer and variant record have been added

The simulation system has also been extended:
  o compiler optionally generates cross-reference files for the
  o symbolic debugger on Parallaxis source level

The Parallaxis system comprises a compiler and a simulator (except forthe MasPar
, which is the only parallel implementation as of today). The
versions currently available are:
  * IBM-PC              (DOS)
  * Apple Macintosh     (MAC OS)
  * Sun3 w/ coproc.     (OS 4.0)
  * Sun3 w/o coproc.    (OS 4.0)
  * SPARCstation / Sun4 (OS 4.0)
  * DECstation          (Ultrix)
  * VAXstation          (Ultrix)
  * HP 9000/300         (Unix)
  * HP /800 series      (Unix)
  * Cray-2              (scalar only, sorry)
  * Apollo              (available soon)
  * MasPar MP-1         (available July 1991)

The software packages and a number of example programs are available via
"anonymous ftp" from:
    ftp.informatik.uni-stuttgart.de    (129.69.211.1)
    in subdirectory    pub/parallaxis
Please send remarks and bug reports to: braunl@informatik.uni-stuttgart.de

There is also a new User Manual for Parallaxis Version 2.0 .
You may order a copy by sending a fee (cash or cheque) of DM 10.00 (Europe)
or US$ 15.00 (outside Europe) to:
       Thomas Braunl, Univ. Stuttgart IPVR
       Breitwiesenstr. 20-22, D-7000 Stuttgart 80
       Germany

FAX:     +49 (711) 7816-346

==========================================================================
Thomas Braunl                  e-mail:  braunl@informatik.uni-stuttgart.de
Univ. Stuttgart IPVR, Breitwiesenstr. 20-22, D-7000 Stuttgart 80,  Germany
==========================================================================

HINTS FOR VERSION 2

The power operator is now "**".

It is now possible to define multiple topologies at once (disjunct or overlay),
or different topologies for procedures that are not nested. If multiple
topologies are used, the topology name has to be specified for each PARALLEL
block.

Since connections are now semi-dynamic, there are no lengthy connection lists
any more at the beginning of each PARZ intermediate code program.

The simulator has been extended to operate source level debugging. For this
reason, the compiler optionally generates a cross reference file (".xrf").


LITERATURE

in English:

Barth, Braunl, Sembach:  Parallaxis Version 2  User Manual
  Computer Science Report, no. 2/91, Universitaet Stuttgart, Feb. 1991
  --> This report is a must for using Parallaxis !! <--
  -->         Contact the address below.            <--

Barth, Braunl, Sembach:  Parallaxis User Manual
  Computer Science Report, no. 3/90, Universitaet Stuttgart, March 1990

Braunl:  Parallaxis:  A Flexible Parallel Programming Environment for
   AI Applications,  Applications of Artificial Intelligence VII,
   Orlando Florida, March 1989, pp. 275 (11)

Braunl:  A Specification Language for Parallel Architectures and
   Algorithms, Fifth International Workshop on Software Specification and
   Design, Pittsburgh Pennsylvania, May 1989, pp. 49 (3)

Braunl:  Structured SIMD Programming in Parallaxis,
   Structured Programming, vol. 10, no. 3, July 1989, pp. 121 (12)

Braunl:  Transparent Massively Parallel Programming with Parallaxis,
   ISSM International Conference on Parallel and Distributed Computing and
   Systems, New York NY, Oct. 1990


in German:

Barth:  Entwicklung eines Compilers fuer die parallele Programmiersprache
   Parallaxis, Studienarbeit Nr. 835, Universitaet Stuttgart, March 1990

Barth:  Entwicklung eines Compilers fuer Parallaxis mit
   dynamischen Verbindungsstrukturen, Diplomarbeit Nr. 705,
   Universitaet Stuttgart, Nov. 1990

Braunl:  Massiv parallele Programmierung mit dem Parallaxis-Modell
   Informatik-Fachberichte Nr. 246, Springer-Verlag 1990.

Krauskopf:  Ein massiv paralleles Verfahren zur Stereobildauswertung,
   Diplomarbeit, Universitaet Stuttgart Nr. 707, Nov. 1990

Liebelt:  Entwicklung und Untersuchung von massiv parallelen Hidden-Surface-
   und Raytracing-Algorithmen, Diplomarbeit Nr. 769, Universitaet Stuttgart,
   Jan. 1991

Sembach:  Entwicklung eines Simulators fuer die parallele
   Zwischensprache PARZ, Studienarbeit Nr. 834, Universitaet Stuttgart,
   March 1990

Sembach:  Entwicklung eines symbolischen Debuggers fuer das parallele
   Sprachensystem Parallaxis/PARZ, Diplomarbeit Nr. 706, Universitaet Stuttgart,
   Nov. 1990

Verba:  Massiv-parallele Algorithmen zur Loesung von Problemen der linearen
   Algebra, Studienarbeit Nr. 904, Universitaet Stuttgart, Nov. 1990

Walter:  Entwurf von massiv parallelen Simulated Annealing Algorithmen,
  Studienarbeit Nr. 925, Universitaet Stuttgart, Jan. 1991
^L
What's New in Version Two
=========================

In version 2 of the Parallaxis language definition and the Parallaxis
Programming System we did some major extensions, the most important being the
introduction of semi-dynamical connection structures. Parallaxis programs may
now have several independent or overlapping interconnection structures at a
time, and different connection structures at different times (linked to
procedure scopes). We tried to be upward compatible as much as possible,
however, there are two minor changes you might have to do in order to run
your old (version 1) Parallaxis programs:


How to upgrade old Parallaxis Programs

*       change power operator symbol from "^" to "**"
*       suffix load/store commands in procedures without selection
        with "[*]" selection


Language Changes

Data Types and Operators
        *       Pointers
        *       Variant Records
        *       power operator "**"
Dynamic data structures and variant record structures have been added. Syntax
and Semantics is identical to Modula-2. The power operator had to be changed
to double asterik, since the "^" symbol is now used for dereferencing pointer
expressions.

Multiple Configuration and Connection Structures
Several configuation and connection structures may be defined globally for the
entire program, or locally for each procedure. Procedures with configuration/
connection structures may not be nested inside each other. Multiple

configuration/connection structures may be defined on disjointed sets of PEs
(with the possibility of interconnections between these groups), each having
its individual data declaration. Several configuration/connection structures
may also be defined on the same set of PEs, resulting in an overlay structure.

PE selection syntax in PARALLEL, LOAD/STORE, and REDUCE statements has been
changed slightly because of this extension. Besides the PE-range, a selection
also has to specify the name of the configuration in case there are more than
one (massively parallel MasPar computer system (16,384 PEs). We hope to be
able to start distribution soon!

REGISTRATION / ORDER SHEET FOR THE PARALLAXIS SOFTWARE PACKAGE

Please fill in the blanks and return to:

       Dr. Thomas Braunl
       Universitaet Stuttgart
       Fakultaet Informatik
       Postfach 10 60 37
       D-7000 Stuttgart 10
       Germany

       e-mail:  braunl@informatik.uni-stuttgart.de


Name:     (first, last)      ..................................................

Company:  (if any)           ..................................................

Address:  (street)           ..................................................

          (city, ZIP)        ..................................................

          (country)          ..................................................

E-mail:                      ..................................................


Intended Use of Parallaxis:  ..................................................

                             ..................................................

                             ..................................................

                             ..................................................


Application Areas:           ..................................................

                             ..................................................

                             ..................................................

                             ..................................................


--------------------------------------------
| This is a [REGISTRATION]  / an [ORDER] . |   (please mark)
--------------------------------------------
(please make sure to accompany order with payment!)

[    ]  Parallaxis User Manual (order)

Computer systems used:       ..................................................
(floppies ordered, resp.)
                             ..................................................

                             ..................................................

                             ..................................................


Thank you for your cooperation!


---------------------------------------------------------------

________________________________________________________________________________		
		Blitzen Simulator
________________________________________________________________________________		


Hello,
   Last week a notice about the Blitzen Simulator and Tutorial
Package was posted. [Blitzen is a massively parallel SIMD machine.]
An additional technical report useful to those doing serious programming
on the simulator is now available, and an ftp site has been established.
   Over 120 people have requested the Blitzen package so far (if you did
you should have received it by now). Because of the large demand,
an anonymous ftp directory has been established on the machine
"mcnc.mcnc.org". Use ftp with a user name of "anonymous" and a
password of "guest", cd into the directory named "pub", and cd
into the directory named "blitzen" to get to it.
   Currently you will find three files in this directory: 1) an
"Index" file that describes the contents of the directory, 2)
a file named "blitz.pkg" containing the Blitzen Simulator and
Tutorial Package, and 3) A file named "blitz_tr" containing
the MCNC technical report entitled "Processing Element
and Custom Chip Architecture for the Blitzen Massively Parallel
Processor". This report provides an in-depth look at the architectural
features of Blitzen, and can probably be considered "essential" if you
are planning to do serious Blitzen programming.
   If you have questions, or if you are unable to use ftp and would
like a copy of the simulator package or the technical report,
please send email to "brain@adm.csc.ncsu.edu".

                                                Thank You,
                                                   Marshall Brain.

-------------
Below is a copy of the original package announcement:

Hello,
   There is now available a free package containing a simulator, tutorials
and example code for a massively parallel SIMD machine named "Blitzen".
Blitzen was developed for NASA as a follow-on to the MPP by a group
of folks from NCSU, UNC, Duke and MCNC.
   The package is intended to allow students and other people interested
in learning about massively parallel architectures to get hands-on
experience with a SIMD machine. The simulator will compile and run on
just about any Unix system. The tutorials introduce you to the
Blitzen architecture (which is very similar to the MPP architecture),
the SIMD mindset, and a fairly large amount of example code that
exercises different features of the architecture. There is also some
image processing code included in the package. The package would
make a nice core for a class on massively parallel machines.
   This package was created to consolidate the simulator and some
tutorial information for students learning about Blitzen here at NCSU.
It is being made publicly available in the hope that other unversities
and companies can use it to give students exposure to massively parallel SIMD
architectures. These architectures are becoming more popular, but
the scarcity of Connection Machines and MPPs tends to limit student
access to these systems. The availability of a free, portable and
easy-to-install simulator might help to remedy the situation.
   If you are interested in receiving the package, you can send
email to:

        brain@adm.csc.ncsu.edu

I will ship you the package by return email.

                                Thanks,
                                   Marshall Brain.



________________________________________________________________________________

		mpsim   portable hypercube simulator
        	Dunigan   ORNL   dunigan@msr.epm.ornl.gov
________________________________________________________________________________

MPSIM
        Portable (to most UNIX systems) message-passing simulator
        that supports both C and FORTRAN.  Uses forks and pipes
        to support up to 8 to 16 processes on UNIX BSD 4.x, SYS V 3.x,
        DYNIX, Encore, Ultrix, Sun, XENIX, Tek UNIX, 3B2s.  Simulates
        Intel iPSC/1 and iPSC/2 hypercubes and produces trace file of message
        events.  Trace-file analyzers produces tabular or graphical
        summaries.  (Encore and Sequent versions will utilize
        multiple processors.)


top directory contains sample programs and trace file postprocessors
  (nstats.c, ccplot.c, trace1.c)


src/
        the beef, do a make here to create mpsim and simlib.a
        mpsim.man and makefiles; also sample build scripts (sbld, sfbld)

---------------------------------------------------------
Information on other ORNL parallel processor simulators

  ORNL  parallel processor simulators
      dunigan     last change: 8/3/88

directories:  (source distribution size)

  mpsim/  portable simulator, sample programs   (122KB)
        src/   mpsim source

  smpsim/  sequent version (NS32x32) of mpsim using shared memory  (147KB)

  sysVsmpsim/  beta version of mpsim  using System V shared memory   (62KB)


  ppsim/  interpretive simulator   (2.8MB)

        doc/     man entries and such
        postp/   postprocessor of trace files
        samples/ sample codes
        lll/     original LLNL distribution
        seqdn/   version of simulators for Sequent (32032 CPUs only)
           kernel/ library source, aspp source
           local/  sample bld and makefile for applications
        sundn/   version of simulators for Sun workstations (Sun 3/68881 only)
           kernel/ library source, aspp source
           local/  sample bld and makefile for applications
        vaxdn/   version of simulators for VAX UNIX 4.x/Ultrix
           kernel/ library source, aspp source
           local/  sample bld and makefile for applications

Simulator summary:

We have several hypercube simulators and a simulator for shared-memory
parallel processors; all support C and Fortran.  A brief summary:

Name    Runs on              Granularity     Performance    Debugging
                                                Info           Help
ppsim   Vax, Sequent, Sun      fine             yes            yes
mpsim   Any Unix with pipes    coarse           no             yes
smpsim  Sequent                coarse           no             yes


PPSIM
        Interpretive parallel processor simulator, based on "Multitasker"
        by Eugene Brooks, modified to support message-passing parallel
        processors.  Provides instruction level tracing, program
        tunable message-passing parameters (startup time, node-to-node
        rates, host-to-node rates, packet size).  Trace file post-processing
        programs provide concurrency plots and tabular summary
        of message passing behavior.  Supports C and f77 on UNIX 4.x
        on VAX, Sun 3 (68020/68881), or Sequent (32032) processors.
        Message-passing software emulates Intel iPSC/1 hypercube subroutines.
        Shared-memory simulation supports, locks, events, barriers,
        semaphores, enqueue, and task creation.  We have used this package
        in teaching graduate course in parallel programming.

SMPSIM
        MPSIM converted to use shared-memory of Sequent for message
        passing.

The above table is a bit of an over simplification, of course.  ppsim
gives an interpretive simulation at the level of individual
instructions and has tunable performance parameters.  It runs as a
single process under Unix and gives meaningful, graphical performance
output and is also useful for debugging.  mpsim uses multiple Unix
processes communicating via pipes.  It is helpful for debugging but
doesn't give very meaningful performance info.  Its advantage over
ppsim is faster execution (in terms of wall clock time).  smpsim is a
specialization of mpsim to the Sequent in which communication by pipes
is replaced by communication via shared memory, which is much faster
still.  In fact smpsim simulates an iPSC in faster than real time for
the same number of (real) processors.

Documentation:

man entries are included in the various distribution directories.
Additional technical reports:

 "A message-passing multiprocessor simulator",Dunigan, ORNL/TM-9966
 "A portable hypercube simulator", Dunigan, ORNL/TM-10410
 "Denelcor HEP multiprocessor simulator, Dunigan, ORNL/TM-9971
 "A multitasking kernel for the C and Fortran programming languages",
    Brooks, LLNL UCID-20167

Work-in-progress:

  dcube-- hypercube simulator using TCP/IP-connected workstations
          as the nodes
          "Hypercube Simulation on a Local Area Network", Dunigan,
          ORNL/TM-10685

dunigan@msr.epm.ornl.gov

________________________________________________________________________________

		Reconfigurable Architecture Workbench
		            Walt Ligon	
________________________________________________________________________________

	

I have been working on a parallel architecture simulator, the Reconfigurable
Architecture Workbench (RAW) that might be of interest to you.  RAW allows
you to write programs using C and execute them as if on a wide variety of
different parallel architectures.  The programs are compiled to an
architecture independent code (AIC) and then compared to an architecture
description code (ADC) at execution time in order to determin the performance
of the program.  RAW will simulate the following types of architectures:
SIMD machines, MIMD machines, as many or as few processors as you have
memory to simulate (I have simulated 8192 SIMD processing elements requiring
about 25M of main storage, MIMD processing elements require a bit more
storage), shared memory or message passing, and just about any kind of network
you can imagine.  currently I don't have a cache simulator installed, but
there are folks working on that.

RAW has been used by a number of students to develop parallel programs in
both SIMD and MIMD modes using a wide variety of the features mentioned.
The biggest problem with you using RAW is that RAW is not a production piece
of software, only a small part of the C library is implemented, documentation
is minimal, and debugging facilities are almost non-existant.  There is also
no guarantee that a student won't encounter a bug that is not his fault at
all and there is no support whatsoever for RAW (other than sending me mail
and asking if I have time to look at the problem).

Not to be too pessemistic.  Like I said, a number of students have successfully
implemented programs with little or no problems at all.  I'm not sure I'd throw
100 green-horns at it, but it might make an interesting tool to take out for
a test drive for a group of motivated students (IOW I wouldn't stake the entire
course on it just yet).  Actually, I am very interested in getting the rough
edges smoothed off and having the system exercised more fully.  If you were to
get excited about it, we could discuss getting some of the remaining parts
finished off by myself, some of the students here, and maybe some of your
graduate students who are into system software stuff.  Really, most of what
is needed is pretty simple but time consuming stuff that I haven't really
needed, so I haven't taken the time to get it all squared away.

Anyway, if you want to know more, drop me a line, I can send you a paper about
it or even arrange for you to get the code.  Let me know.

Walt Ligon
walt@cc.gatech.edu


________________________________________________________________________________
		
		Image Understanding Architecture Simulator
			 
				Jim Burrill
________________________________________________________________________________

We can make available to you a simulator for the first generation
of the Image Understanding Architecture that runs under SunOs 4.1
on a Sparcstation or Sun4.  The Image Understanding Architecture
is a massively parallel computer utilizing a SIMD grid of bit serial
processors at the bottom level and a MIMD grid of TI TMS320C25 DSP
processors at the intermediate level.  Programs to be run on the
simulator may be written in Forth & C for the SIMD level and Assembler
or C for the intermediate level (you must obtain the C25 C compiler from
TI).  You can read about this system in "Parallel Architectures and
Algorithms for Image Understanding" ed by V.K. Prasanna Kumar,
Academic Press, 1991.

   Jim Burrill
   burrill@aai.com

________________________________________________________________________________

			    Tango System
			Stephen Goldschmidt
________________________________________________________________________________


There are two published tecnical reports on Tango:

CSL-TR-90-410  Tango Introduction and Tutorial
CSL-TR-90-439  Tango:  A Multiprocessor Simulation and Tracing System

You may obtain an unofficial PostScript copy of these reports via
anonymous FTP from meadow.Stanford.EDU (36.64.0.20).  The files are in
the /tango directory (tutorial.ps and methodology.ps).

Also, there is a paper on Tango in the Proc. ICPP of 1991:
 Multiprocessor Simulation and Tracing Using Tango

If you have specific questions, send them to me at:
 comments@meadow.Stanford.EDU

The Tango code is property of Stanford University.  To obtain the source
code, you must also obtain a Stanford Academic License Agreement from:

   Stanford University / Office of Technology Licensing
   857 Serra Street, Second Floor
   Stanford, CA  94305-6225
   tel: (415) 723-0651
   fax: (415) 725-7295
   email: otl@popserver.Stanford.EDU

I cannot send Tango source to you until you have returned a signed copy
of this Agreement.  (Note that we currently do not distribute Tango outside
the United States.)  Media available are:  reel-to-reel tape (1600 bpi),
cartridge tape (60 Mb), and uuencoded electronic mail.

Please be aware that Tango only runs on machines that use Mips processors.
Versions are available for Ultrix (DecStations), Irix (SGI machines),
and UMips (Mips M/120).  Porting Tango to a Sun or Vax architecture would
be a major undertaking.

Stanford does not provide any support for Tango.  This is prototype
code and is not an efficient implementation.  A more efficient
replacement for Tango, using lightweight threads and running as much as
50x faster, has been developed at Stanford, but is not being
distributed.

Stephen Goldschmidt, Tango Guru, comments@meadow.Stanford.EDU

________________________________________________________________________________

> From: gwilson@umiacs.UMD.EDU (George Wilson)

1. There is a StarLisp simulator for the Connection Machine
that I believe is in the public domain. I believe it can be had by
anonymous ftp from think.com.

________________________________________________________________________________

> From: hlv@think.com (Harry Voorhees)

Thinking Machines is pleased to announce that the latest *Lisp Simulator is
freely available.  The *Lisp Simulator is a simulator for *Lisp, one of the
programming languages used to program the Connection Machine.

Thinking Machines provides free, with the *Lisp Simulator, an on-line
'Getting Started in *Lisp' manual.  This manual is also available
in hardcopy without charge from Thinking Machines (see ordering *Lisp
documentation below)

The *Lisp Simulator is available via anonymous ftp in the /public directory
of think.com in the subdirectory /cm/starlisp.  The file that can be ftp'ed
is a Unix 'shar' file called

starsim-f19-sharfile

or

starsim-f19-sharfile.Z

(where f19 may be replaced in the future by a higher release number)

The F19 version of the *Lisp Simulator is compatible with the latest *Lisp
software (version 6.1) for the Connection Machine hardware.  It is written
in portable CLtL I.

This sharfile provides the necessary sources and systems for the *Lisp
Simulator to run under Symbolics, Lucid, Allegro and Franz Common Lisps.
Porting the *Lisp Simulator to other Common Lisp's is generally a simple
matter.

The 'Getting Started in *Lisp' manual is available free of charge.  Other
documentation for the *Lisp language is available at cost from Thinking
Machines Corporation.  The *Lisp Reference Manual and the Dictionary
together are $100.  Send a request and/or a check or a purchase order to:

Thinking Machines Corporation
245 First Street
Cambridge, MA  02142-1264
Attn:  Katy Smith

Or by sending e-mail to:
Internet:       documentation-order@think.com
uucp:           harvard!think!documentation-order


Note: People wishing to distribute the *Lisp Simulator should distribute it
using the sharfile in /public and not from the sources provided on-site at
Connection Machine customer installations, since these sources do not
provide all the documentation, instructions and auxiliary files useful in
installing the *Lisp Simulator at a non Connection Machine site.

Caveat: Thinking Machines will continue to provide support for the *Lisp
Simulator for Thinking Machine's Connection Machine customers.  Thinking
Machines is under no obligation to provide support for other users of the
*Lisp Simulator, either in porting or using it.



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From rshtokha@cis.udel.edu Thu Nov 12 04:56:27 1992
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To: dcp79807@csie.nctu.edu.tw
Subject: Re: Trace generator wanted (Uniprocessor or MP)!!
Newsgroups: comp.parallel
Organization: University of Delaware, Newark
Cc: 
Date: Wed, 11 Nov 92 20:29:05 GMT
From: rshtokha@cis.udel.edu
Message-Id:  <9211112029.aa01337@bambam.cis.udel.edu>
Status: OR

I've used a package named Abstract Execution (AE) - A Technique for efficiency
Tracing Programs, by James R. Larus (larus@cs.wisc.edu).
The package can obtained by anonymous ftp to

                  Host ftp.uni-kl.de   (131.246.9.95)
                  Location: /pub1/packages/gnu
                  DIRECTORY rwxrwxr-x       512  Oct 28 02:11   ae

Hope it helps.

Ruth S.

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From chaiken@hing.LCS.MIT.EDU Thu Nov 12 07:08:25 1992
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Date: Wed, 11 Nov 92 18:06:38 -0500
From: chaiken@hing.LCS.MIT.EDU (David Chaiken)
Message-Id: <9211112306.AA27325@hing.LCS.MIT.EDU>
To: dcp79807@csie.nctu.edu.tw
Cc: kerr@ai.mit.edu
Subject: Address Traces for Parallel Proecessors
Reply-To: David Chaiken <chaiken@hing.LCS.MIT.EDU>
Status: OR

I am one of Anant Agarwal's graduate students in the Alewife group at
MIT.  Debby Wallach (another MIT student who read your article in
comp.parallel) referred your request to me, because I am in charge of
distributing our group's multiprocessor trace data.

We distribute 64 processor FORTRAN and MUL-T (a parallel LISP 
dialect) traces that were gathered at IBM and MIT.  You can 
read about these traces in an article that Anant's group wrote for 
the June, 1990 issue of Computer magazine.

One MUL-T and three FORTRAN traces are available in DEC TK-50, DEC
TK-70, SUN QIC-150, Exabyte (8mm), and 9-track formats.  The traces
are compressed using UNIX compress and written to tape with the UNIX
tar program.

The sizes of the compressed traces are as follows:

	SPEECH 	22 Mbyte
	SIMPLE 	66 Mbyte
	WEATHER	76 Mbyte
	FFT	16 Mbyte

I would be happy to send you these four traces if you send a check to
cover the cost of the tapes and postage.  The data is free, but the media
cost money.

        Format                 Cost            Postage
        ------                 ----            -------
	DEC TK-50/TK-70   2 @ $24.95 = $49.90 + $4.00 = $53.90
	SUN QIC-150       2 @ $30.96 = $61.92 + $4.00 = $65.92
	Exabyte (8mm)     2 @ $ 8.00 = $16.00 + $4.00 = $20.00
	9-track           2 @ $16.80 = $33.60 + $4.00 = $37.60

Please send your address and a check payable to "MIT - Alewife Data" to:

   David Chaiken
   NE43-633
   Massachusetts Institute of Technology
   545 Technology Square
   Cambridge, MA 02139

-David

P.S.  You can also get the ATUM traces by anonymous ftp.  If you're interested
in fewer processors, you might be interested in these traces.  Let me know.

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From @TWNMOE10.EDU.TW:ANDI@MIPS.COMPLANG.TUWIEN.AC.AT Thu Nov 12 22:10:24 1992
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Date: Thu, 12 Nov 92 15:08:43 +0100
From: andi@mips.complang.tuwien.ac.at (Andi Krall E185/1 +43158801/4462)
Message-Id: <9211121408.AA09261@mips.complang.tuwien.ac.at>
To: dcp79807@csie.nctu.edu.tw ()
Subject: Re: Trace generator wanted (Uniprocessor or MP)!!
Status: OR

Every UNIX box has a trace generator, called dbx (the debugger). Set the
debugger variables so, that every executed instruction is displayed and
set no page limit and type stepi <number of instructions>.
Sometimese you have troubles with signals.
Happy tracing,
   Andi
--
Andreas Krall, andi@mips.complang.tuwien.ac.at
+431 58801/4462  fax +431 5057838
Technische Univ. Wien, Inst.f. Computersprachen E185/1
Argentinierstr.8/4, A-1040 Wien Austria


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--
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Chih(4)-Zong(2) Lin(2)				| e-mail address:            
Dept. Computer Science & Information Engineering|   dcp79807@csie.nctu.edu.tw 
National Chiao-Tung University			| 
Hsinchu, Taiwan, Republic of China		|
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