HDTenEightyP/NetNews huggingface dataset:
From: ask@sei.cmu.edu (Alan Koch)
Newsgroups: comp.cad.cadence,comp.text.frame
Subject: Re: FrameMaker
Date: 18 Nov 92 18:56:49 GMT
Organization: The Software Engineering Institute


In article <4046@phred.UUCP>, kimb@phred.UUCP (Kim Butler) writes:

|> 	I am still confused.  If I have 20 FrameMaker and 10 FrameView
|> licenses, and I have 10 FrameView/Cadence from Cadence.  When you run
|> Frame the path set by FMHOME is where the license is found.  So, you either
|> use all FrameView/Cadence or all the other, but you can not add or
|> combine.  I guess a script would have to be set to start Cadence setting
|> the FMHOME for the session.  THIS SUCKS.
|> 
|> Please correct me if I am wrong in my thinking.  

You are basically right.  What you have is two "work groups".  One has a total
of 30 licenses (20 Maker and 10 Viewer), and the other has 10 Viewer licenses.
The whole idea of work groups is to let you isolate one group's licenses from
the others.  (See the discussion of Work Groups in the "Setting up floating
licenses" chapter of _Installing_FrameMaker_.)

It sounds like you really want one work group with all 40 licenses available
to everyone.  The correct way to do this would be to buy the 40 licenses from
Frame and NONE from Cadence.  This would require Cadence to have a licensing
scheme that allowes existing Frame Licensees to use their existing licenses.

That is what you should explore.  And if Cadence won't do such a thing, then
in your words, "THIS SUCKS."

ask@sei.cmu.edu

Alan S. Koch
Software Engineering Institute
Carnegie Mellon University
Pittsburgh, PA  15213
Newsgroups: comp.cad.cadence
From: ianj@meiko.co.uk (Ian Jamison)
Subject: Verilog to Edif conversion.
Followup-To: comp.cad.cadence
Keywords: verilog edif convert
Reply-To: ianj@meiko.co.uk
Organization: Meiko Ltd.
Date: Thu, 19 Nov 1992 12:11:11 GMT

Hi all,

I have a gate-level verilog description of a chip and would like
to convert it to an EDIF netlist. I believe that Synopsis could
do this for me but I don't have (or want to have) Synopsis.

Anyone got a utility for this, or know where I can get one.

Public domain would be nicest, but other info would be appreciated
also.

Many thanks,
Ianj.

Xref: sparky comp.cad.cadence:491 comp.text.frame:3414
From: kimb@phred.UUCP (Kim Butler)
Newsgroups: comp.cad.cadence,comp.text.frame
Subject: FrameMaker
Date: 17 Nov 92 23:43:24 GMT
Reply-To: kimb@phred.UUCP
Organization: Physio-Control


Recently, i was given this article:

Hi.  I have a large software application installed on my
system from Cadence Design Systems.   It is a IC design tool
and all documentation is online in Frame format.   
The problem is I have been unable to use Frame Viewer from 
outside the Cadence tool framework.
My questions:
Is Frame Viewer licensed?   Where is the license file?
>>Is it possible to use viewer as I wish?   What's the trick?
>>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>Peter A. Stokes ~~~~~~~~ pas@jupiter.ic.cmc.ca ~~~~~~~ (613) 545-2923 ~~~~~

Here is someones response:

>To the best of my knowledge, it is contractually unacceptable for CDS 
>licensees to use the FrameViewer distributed by Cadence to do anything 
>other than view Cadence online documentation.  Since you obviously have
>Maker licenses (as indicated in your post), why not just use Maker and
>lock your documents (it will seems as though you're using Viewer)?
>--
>Michele Vening
>Motorola ASIC DA Frame Support                  (602) 821-4253
>Chandler AZ			           FAX: (602) 821-4963
>vening@chdasic.sps.mot.com.jj

Now my response:

	I am still confused.  If I have 20 FrameMaker and 10 FrameView
licenses, and I have 10 FrameView/Cadence from Cadence.  When you run
Frame the path set by FMHOME is where the license is found.  So, you either
use all FrameView/Cadence or all the other, but you can not add or
combine.  I guess a script would have to be set to start Cadence setting
the FMHOME for the session.  THIS SUCKS.

Please correct me if I am wrong in my thinking.  

Thanks, Kim Butler
From: ees1in@ee.surrey.ac.uk (Ivailo Nedelchev)
Newsgroups: comp.cad.cadence
Subject: layout -> text -> layout
Keywords: cadence
Date: 23 Nov 92 22:12:50 GMT
Organization: University of Surrey, Guildford, England


is there any way to convert layout to text file
then to edit this file and back to layout?

thank you
ivailo

-- 

 _   /|
 \`0.o'
 =(_|_)=- 
    V   
Newsgroups: comp.cad.cadence
From: parviz.fariborz@analog.com
Subject: Re: edifout problem - schematics
Originator: parviz@osiris
Organization: Analog Devices, Inc.
Date: Thu, 19 Nov 1992 19:42:19 GMT

In article <BxyrIF.6J4@newcastle.ac.uk> Albert.Koelmans@newcastle.ac.uk (Albert Koelmans) writes:
>
>I've been trying to generate edif output from schematics without much
>success. The program complains it can't fine 'ipin', 'opin' etc., even if I
>copy the schematics for them from the library into my own directory.
>
>Has anyone seen this problem before? Any pointers on how to get round it? Any
>help would be very appreciated since the problem is holding us up.
>
>Thanks
>

The ipin, opin and iopin are the cells for the Cadence's input, output and
io ports. They are in a library named basic that Cadence ships out with the
software. You need to set your library path to the directory where the basic
library is located.



-- 
|-------------------------------------|----------------------------------------------|
|        Parviz Fariborz              | INTERNET: Parviz.Fariborz@Analog.Com         |
|      Analog Devices Inc.            | UUNET: !uunet!spd.analog.com!parviz.fariborz |
|-------------------------------------|----------------------------------------------|
Newsgroups: comp.cad.cadence
From: toma@baritone (Thomas Arneberg)
Subject: Phantom NLP inheritance in Composer
Organization: Cray Research Inc.
Date: 23 Nov 92 14:05:52 CST

We have encountered a "feature" of Composer that is driving us crazy.

If we descend down the hierarchy and look at a symbol placed in a
schematic, and that symbol has an NLP label to display a property that the
symbol DOES NOT HAVE, then it will "inherit" the value of the property from
the schematic above this. The problem is, it only APPEARS to inherit the
value...it does not come up when netlisted, nor does it show up when the
schematic is printed. It only shows up when descend-edited or descend-read.

EXAMPLE
-------
This manifests itself for us with a property called 'm'. SPICE understands m
to be a scale factor, so generally we give all of our subcircuit symbols an
NLP label to display m if it exists (e.g. "M=[@m:%]").

Now suppose you have a top-level schematic called Top. In this schematic
there is a symbol called Adder, with a property m=3. Further suppose that
in the Adder schematic, there is a cell called Nor2. This Nor2 symbol does
NOT have any m property attached to it, since the user only wanted one of
them. But the Nor2 master symbol DOES have the NLP label as described above, 
so that the m property will be displayed if there is one.

When Top is netlisted for SPICE, the m=3 will appear on the Adder line, but 
no m-factor will appear on the Nor2 line. So far, so good. If you plot the
Adder schematic, or edit it from the library browser, you'll see no sign
of an m-factor on the Nor2 symbol. That's good too.
 
THE PROBLEM IS, if you descend-edit into the Adder schematic from Top, then
the Nor2 symbol will appear to have m=3 attached to its symbol (apparently
inherited from the Adder symbol in the Top schematic above). This is a 
phantom -- there is in fact no m property on Nor2. (The "Edit properties..."
command shows no sign of 'm'.) 
 
You could argue that it's merely a cosmetic problem, but you can imagine 
that if the user WANTED Nor2 to have m=3, the appearance of this phantom 
property could lull him into a false sense of security.
 
 
Does anyone know of any way to make a symbol NOT appear to "inherit" a
property from above, or whether this "feature" is fixed in 4.2.1?
Thanks,

  - Tom A.
---------------------------------------------+------------------------------
;-) I'd rather be ____  Thomas R. Arneberg   | Inet: toma@cray.com
:-) singing in a |____| Senior IC Design Eng.| UUCP: ...!uunet!cray!toma
:-) Barbershop  _|   _| Cray Research, Inc.  | CLAIM TO FAME: Loni Anderson 
:-) Quartet!   (_)  (_) Chippewa Falls, Wisc.|   went to my high school 
---------------------------------------------+------------------------------
Xref: sparky comp.cad.cadence:505 comp.lsi:704 comp.lsi.cad:1157
From: arindam@cs.uwindsor.ca (Arindam Das)
Newsgroups: comp.cad.cadence,comp.lsi,comp.lsi.cad
Subject: prune
Keywords: PDExtract, 1.2 um cmos4s, layout, nmos-array
Date: 20 Nov 1992 03:55:21 GMT
Followup-To: poster


           Ref:  article on Gate-array simulation problem
hi netters,

a week back I had posted an article regarding the problem
of hspice simulation of an extracted layout of an nmos-array.
The problem was: what to do with the unused nmos transistors
in the array that was creating the simulation problem.

A pointer was shown to me by Keith Sabine at keiths@Cadence.COM.

The pointer was: "use the pdv prune command in PDextract rules
file."

In PDV manul of Edge it is said that "prune" has to be used
in PDcompare rules file. Now I might create a schematic rep
for the corresponding layout if the circuit is containing
12 or 13 nmos transistors and then try PDCompare but
I DON'T WANT  to draw schematics of the circuit that contains
hundred nmos transistors (say in a 10 by 10 nmos transistors array)!

However, I tried Keith's pointer as follows and ended up with
following errors. I must have made some mistake which I can't figure
out:



The rules file I have got is pdvrules4  (for Cmos4s) supplied
by CMC. It has switches like do_drc, do_extract, do_autogen, etc.

1. I wildly used the "prune" command at the end of do_extract switch and
the message was as it should be:

  undefined layer:  prune

2. Next I tried to use pdCompare for  the extracted rep of the layout.
   Please note that i did not have the schematic rep. So I just wildly
   tried to compare the same extracted layout and the message was:

   netlist not distinct


COULD someone tell me a work-around so that I can use the "prune"
command effectively ?

thanx

-arindam
-- 
Arindam Das                            email: arindam@CS.Uwindsor.Ca
dept. of comp. sci.                           ph# 253-4232Ext 3003/3007
U. of Windsor, Ont, Canada             
From: gotom@hpysoln.tky.hp.com (Masaharu Goto)
Date: Thu, 19 Nov 1992 16:37:37 GMT
Subject: HELP:Verilog to VHDL translator
Organization: YHP Hachioji IT, Tokyo Japan
Newsgroups: comp.cad.cadence


Subject: Verilog-HDL to VHDL translator

 Does anyone have information or experience about Verilog-HDL to VHDL 
translator?  

 My situation is

 I am designing an IC using Verilog-XL simulator.  On the other hand 
We will buy Mentor QuickSim2 for PC board simulation. It is very nice if
I could simulate the PC board with QuickSim2 including IC behavior model I 
write in Verilog.
 We will start the board simulation in next April. I don't require
full timing simulation. Bulk delay simulation or even unit delay simulation
is still OK.  This time, purpose of the trial is pilot run of the Mentor
system rather than design verification itself. 

 Any kind of information/suggestions are appreciated.
Newsgroups: comp.cad.cadence
From: pas@jupitercmc.ca (Peter Stokes)
Subject: Re: FrameMaker
Reply-To: pas@jupiter.ic.cmc.ca
Organization: Canadian Microelectronics Corporation
Date: Fri, 20 Nov 1992 15:21:21 GMT

In article <522@idtinc.UUCP>, cwp@idtinc.UUCP (Chuck Phillips) writes:
|> In article <4046@phred.UUCP> kimb@phred.UUCP writes:
|> 
|> Even more deleted to save space.
|> 
|> people who know may feel free to correct this if I have remembered it
|> wrong) the contract basically states that the FrameViewer that Cadence
|> uses in its toolset is not to be used as a stand alone product. It can
|> only be used in conjunction with Cadence's Design Framework II.

Not only does it appear that it should not used standalone, IT CAN'T 
(at least I have not been successful in firing up viewer from outside
of the 4.2a framework).  BUT, if you setenv FRAMEUSERSD_HOST to
a host which is running a Frame license server (from a separate,
paid-for Frame purchase and license installation), you can use
the Cadence frame distribution (install_dir/frame) to run Framemaker 
or Frameviewer or whatever you are licensed to run as per FRAMEUSERSD_HOST.

Peter

PS:  Type the following in your CIW sometime:

hiMakerHelp("/full/path/to/any/frame.doc" "anyOrNoneHypertextTag")

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Peter A. Stokes ~~~~~~~~ pas@jupiter.ic.cmc.ca ~~~~~~~ (613) 545-2923 ~~~~~
Canadian Microelectronics Corporation ~~~~~~~~~~~ Kingston, Ontario, Canada
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Xref: sparky comp.cad.cadence:502 comp.lsi.cad:1156 comp.lsi:703
From: cindy@ca41.zoran.hellnet.org (Cindy Eisner)
Newsgroups: comp.cad.cadence,comp.lsi.cad,comp.lsi
Subject: edif 2 verilog translator
Keywords: edif, verilog, altera
Date: 19 Nov 92 09:26:08 GMT
Followup-To: comp.cad.cadence
Organization: Zoran Microelectronics LTD. Haifa, Israel.


hi all,

unfortunately, i have to do the following:  translate an edif netlist into
verilog using the cadence tool e2v (formerly of gateway design automation).
the edif netlist was generated by the max+plus II compiler of altera corporation.

now:  my problem is that the delays in the edif netlist get lost in the 
translation.  i know less than nothing about edif, but what i am seeing is
that in the edif netlist, the delays are all on instances of a special cell
called "DELAY".  i have generated two versions of the edif netlist:  in the first,
the delay is specified using the property "TPD".  in the second, the delay
is specified using "portDelay".  

when the delay is specified using property "TPD", i have tried the "map property"
statement in the .map file of e2v.  however:  it seems i need to choose one of
TPLH, TPHL, etc. - but i apparently want all of them.  how can i do this?  in
any case, i get warning messages of the following format:

(?E2V) ***WARNING***  Property TPD  mapped to  TPLH (in cell NTSC in library ALTERA) not relevant for a module instance OR2_96

and the resulting verilog netlist (using +force) contains no delays.

when the delay is specified using "portDelay", i get error messages of the
following format:

(?E2V) ***WARNING***   Feature not supported :  portdelay cannot be backannotated using portinstance  port \1  of instance AND3_8 : cell NTSC lib ALTERA

and again, the resulting verilog netlist (using +force) contains no delays.

does anyone have a clue?

alternately, does anyone know how i can get the altera compiler to use
"pathDelay", which seems to work fine, rather than "portDelay"?  or to put
the delays on the cells themselves rather than on these silly cells called
"DELAY"?

thanks,

cindy.

--

    Cindy Eisner,                     Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: cindy@Zoran.HellNet.Org
    Advanced Technology Center
    Haifa 31204, Israel               Could be my employer doesn't agree.
-- 

    Cindy Eisner,                     Tel: 972-4-551551
    CAD group,                        Fax: 972-4-551550
    Zoran Microelectronics LTD,       E-mail: cindy@Zoran.HellNet.Org
    Advanced Technology Center
    Haifa 31204, Israel               Could be my employer doesn't agree.
Newsgroups: comp.cad.cadence
From: clifs@netcom.com (Clif Schieck)
Subject: Composer verilog users
Organization: Netcom - Online Communication Services  (408 241-9760 guest) 
Distribution: na
Date: Thu, 19 Nov 1992 17:22:27 GMT


At one of my clients site, we were trying to generate a symbol
from the Xilinx post routed verilog netlist file so we could
bring the xilinx part back into the system for board level
simulation and were unable to generate a symbol from the
verilog view because of a bug from Cadence. Below is a description
of the problem and the solution:

Problem: When I did a check and save on the read only verilog
textual window, cadence composer asks me if I want to generate
a symbol. I answered yes and it says symbol generated but when
I checked in the browser there was not symbol view. Only the
original functional view. What went wrong? There were no error
or warning messages in the ciw window.
  
Solution: There is a bug with cds version 4.2.58.5 that makes it
necessary to do a lbCheckOut "900" in order to generate
a functional view off a symbol. Product 900 is skill development.
This is because the procedure ssg requires skill development.

In order to fix this problem type the following in the ciw
window first:

lbCheckOut "900"

If you don't have a skill dev license and need the functional
to symbol generator, get the key on loan from you local sales
person until Cadence fixes this bug.

You should not be required to have product 900 checked out in
order to run this option. This is a little silly. 


-- 
------------------------------------------------------------------------------
Clif Schieck               | CAD/CAE Software
Independent Consultant     | Schematic Capture, Simulation,Logic Synthesis,HDL
clifs@netcom.com           | Installation, Custom Interfaces, Cadence Skill
408-296-5432               | System, IC, Gate Array, FPGA

Newsgroups: comp.cad.cadence
From: jcooley@world.std.com (John Cooley)
Subject: Invite To Join ESNUG
Organization: The World Public Access UNIX, Brookline, MA
Date: Wed, 18 Nov 1992 09:19:26 GMT


  If you're using the Synopsys Design Compiler and/or their ATPG product, you 
  might be interested in joining the E-Mail Synopsys Users Group (ESNUG).

  What we are is a group of hardware designers from all over the world who
  wish to trade experiences, bug reports and the techniques that we've
  found that work best in getting a design from a behavioral description
  to a final fully tested product.

  A Sample of What We Discuss:

	- Known Synopsys Compiler Bugs    - Implementing Boundry Scan

	- Mentor related issues    - EDIF related issues

	- Hierarchical Compliations   - design_analyzer   - JTAG

	- How Various ASIC Vendors Model Their Macros.   - Clock Constraints

	- Using ATPG Tools   - The Best Way To Write State Machines in Verilog

	- Using VHDL   - System Simulation vs. Synopsys Friendly Code

	- Clever Workarounds to Known Pitfalls   - Testing Strategies

  In order to insure an open discussion, but yet keep our respective managers
  happy in having our company's projects remain SECRET, submissions to be 
  posted to the ESNUG mailing list can be stripped of identifying engineers 
  and company names if so requested.

  In addition, to further secure privacy and to avoid e-mail headers that
  are hundreds of names long, each mailing is a batch of singlely addressed 
  e-mail letters.

  If you know of anyone who may be interested in this, please give them
  my e-mail address (jcooley@world.std.com or jcooley@miracle.com) or you can 
  send me their address!
					- John Cooley
					  ESNUG Moderator

 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
     /o o\  /  it's a FEATURE!"   |    Backup Address: jcooley@miracle.com
    (  >  )                       |              (508) 429-4357
     \ - /       |   Snail Mail: P.O. Box 6222, Holliston, MA 01746-6222
     _] [_       |     "This here ain't no one's opinion 'cept my own."


Newsgroups: comp.cad.cadence,comp.text.frame
From: pas@jupitercmc.ca (Peter Stokes)
Subject: Re: FrameMaker
Reply-To: pas@jupiter.ic.cmc.ca
Organization: Canadian Microelectronics Corporation
Date: Wed, 18 Nov 1992 18:49:23 GMT

In article <4046@phred.UUCP>, kimb@phred.UUCP (Kim Butler) writes:
|> 
|> Recently, i was given this article:
|> 
|> Hi.  I have a large software application installed on my
|> system from Cadence Design Systems.   It is a IC design tool
|> and all documentation is online in Frame format.   
|> The problem is I have been unable to use Frame Viewer from 
|> outside the Cadence tool framework.
|> My questions:
|> Is Frame Viewer licensed?   Where is the license file?
|> >>Is it possible to use viewer as I wish?   What's the trick?
|> >>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|> >>Peter A. Stokes ~~~~~~~~ pas@jupiter.ic.cmc.ca ~~~~~~~ (613) 545-2923 ~~~~~
|> 
|> Here is someones response:
|> 
|> >To the best of my knowledge, it is contractually unacceptable for CDS 
|> >licensees to use the FrameViewer distributed by Cadence to do anything 
|> >other than view Cadence online documentation.  Since you obviously have
|> >Maker licenses (as indicated in your post), why not just use Maker and
|> >lock your documents (it will seems as though you're using Viewer)?
|> >--
|> >Michele Vening
|> >Motorola ASIC DA Frame Support                  (602) 821-4253
|> >Chandler AZ			           FAX: (602) 821-4963
|> >vening@chdasic.sps.mot.com.jj
|> 
|> Now my response:
|> 
|> 	I am still confused.  If I have 20 FrameMaker and 10 FrameView
|> licenses, and I have 10 FrameView/Cadence from Cadence.  When you run
|> Frame the path set by FMHOME is where the license is found.  So, you either
|> use all FrameView/Cadence or all the other, but you can not add or
|> combine.  I guess a script would have to be set to start Cadence setting
|> the FMHOME for the session.  THIS SUCKS.
|> 
|> Please correct me if I am wrong in my thinking.  
|> 
|> Thanks, Kim Butler

Permit me to confuse the issue even more:   If you 
look in the Cadence software hierarchy, there is no
Frame{viewer,maker} license file to be found!

Peter

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Peter A. Stokes ~~~~~~~~ pas@jupiter.ic.cmc.ca ~~~~~~~ (613) 545-2923 ~~~~~
Canadian Microelectronics Corporation ~~~~~~~~~~~ Kingston, Ontario, Canada
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
From: rpalmer@Think.COM (Ralph Palmer)
Newsgroups: comp.cad.cadence
Subject: Allegro 5.1 negative pad offset bug
Date: 23 Nov 1992 14:13:41 GMT
Organization: Thinking Machines Corporation, Cambridge MA, USA
Distribution: world
NNTP-Posting-Host: basie.think.com


I spent last Wednesday tracking down a bug involving negative pad offsets
in Allegro 5.1.  A pad offset in a pad stack is a useful way of creating 
a window opening around both pads of a surface mount discrete component 
such as a 1206 resistor.  The 5.1 bug is that the artwork program to create
gerbers takes the absolute value of the offset.  It treats positive
offsets fine, but negative offsets get treated as a positive value.  The
pad in the *.brd look fine, the error is only noticible when you create
gerbers and plot them or read them back in. 

Valid/Cadence is aware of the problem and has a patch.  It is a real pain
to spend time tracking down a known bug.  Would it be possible for the 
Cadence people to post application alerts, bug reports and fixes to this
newsfile?

					Ralph Palmer
					rpalmer@think.com
					Thinking Machines Corporation