HDTenEightyP/NetNews huggingface dataset:
From: kenb@dadd.ti.com (Ken Butler)
Subject: Re: test
Organization: Texas Instruments, Inc., Dallas, TX
Date: Tue, 13 Oct 1992 15:11:01 GMT

Tracy,

Regarding "Re: test", you write:

Tracy> Just to insert something on testing, speaking as someone who was
Tracy> unable to attend ITC this year because of administrative
Tracy> obligations, I would love to know what the hallway-scuttlebut said
Tracy> were the most exciting papers.  I have access to the proceedings,
Tracy> but it is a thick book.  I missed hearing people chat in the
Tracy> hallways about "so-and-so's outrageous talk" or "what's his name's
Tracy> new insight."

I think that the Maxwell, Aitken, Johansen, and Chiang paper garnered
considerable interest from the crowds.  I also noted that sessions
containing papers on IDDQ testing seemed to have a large number of
attendees in general.

I'm sure that there were others with large crowd draws, but those are the
examples that I remember.  Anybody else have an additional/different
impressions than I did?

Ken
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Texas Instruments                           (214) 997-2049 (FAX)
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Newsgroups: comp.lsi,comp.lsi.cad
From: burra@eesun1.ttu.edu (Gangadhar Burra)
Subject: Spice3e2 and X11R5
Organization: Texas Tech University
Date: Sat, 10 Oct 1992 15:40:29 GMT
X-Posted-From: eesun1.ee.ttu.edu
NNTP-Posting-Host: sol.ctr.columbia.edu

Hello, 

Has anybody ever compiled Spice3e2 (assuming this is the latest from Berkeley)
under X11R5 environment. When I do, the linker complains that it has an
undefined symbols asciiStringWidgetClass (which I presume is from Xaw).

Any help on this would be greatly appreciated.

Thanks
Gangadhar Burra
burra@sun1.coe.ttu.edu or burra@eesun1.ee.ttu.edu
Texas Tech Univ
Dept. Elec. Engg.
Newsgroups: comp.lsi
From:  rand@utech.nsk.su (Ryabchenko A.G.)
Subject: A Fabrication p-n Junction for a CMOS Bandgap Reference?
Reply-To: rand@utech.nsk.su
Organization: Association University Technologies (UNITECH)
Date: Thu,  8 Oct 92 13:07:48 +0800 

 A Fabrication of p-n Junction for a CMOS Bandgap Reference
for Differential Signal Refference?
 Sincerely yours, Andrey G. Ryabchenko.


Newsgroups: comp.lsi,sci.electronics
From: sls@elecard.tomsk.su (Sergey Shinkevich)
Subject: WANTED: Bt858 pin layout.
Keywords: Bt858
Reply-To: sls@elecard.tomsk.su
Organization: Elecard ltd hq
Date: Mon, 12 Oct 92 13:48:43 +0700

Dear netters,

Can you please send me the pin layout of Bt858 by BrookTree.

Please send it to the adress below, NOT to this group.

Sergey Shinkevich.
sls@elecard.tomsk.su




Newsgroups: comp.compilers
From: henry@zoo.toronto.edu (Henry Spencer)
Subject: Re: Compiler Libraries and/or built-in routines
Reply-To: henry@zoo.toronto.edu (Henry Spencer)
Organization: U of Toronto Zoology
Date: Fri, 9 Oct 1992 17:08:40 GMT
Keywords: library

I wrote:
>1. You can generate the FP instructions anyway and set up a trap handler
>to interpret them...  Actually, the *right* way to handle the issue is for
>the operating system to do this for you, so it *always* looks to you like
>the hardware does FP, except that sometimes it's kinda slow... :-)

Credit where credit is due dept...

To the best of my knowledge, the first person to think of this approach
was Mike Tilson at HCR (now SCO Canada).  The original pdp11 Unix method
was to compile the trap handler into each program.  This was clumsy and
meant having two different flavors of binary.  Mike worked out some simple
modifications to the trap handler that permitted stuffing it into the
kernel instead.

(Note, I'm not claiming Mike thought of the general concept of emulating
unimplemented instructions.  That's been around for a long time, and of
course that was what the original trap handler did.  The specific issue at
hand is providing floating-point emulation as a system service, available
to all programs without special preparation.)

Worked pretty well, too.  Actually, programs *could* tell whether they
were getting real FP or the emulator, even without running timings, but
that was simply because the emulator didn't try all that hard to match the
hardware exactly.  Cleanly-written programs that didn't care about the
last decimal place just ran, either way.  When we finally got hardware FP
on our 11, not a single thing in the system software needed changing.

(A surprising number of *user* programs broke... but when we investigated,
it always turned out that they were broken already.  Notably, the emulator
didn't trap division by zero, and the hardware did...)
-- 
Henry Spencer @ U of Toronto Zoology, henry@zoo.toronto.edu  utzoo!henry
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From: bart@cs.uoregon.edu (Barton Christopher Massey)
Newsgroups: comp.compilers
Subject: Re: Register Files
Keywords: registers, optimize, comment
Date: 7 Oct 92 08:21:21 GMT
Reply-To: bart@cs.uoregon.edu (Barton Christopher Massey)
Organization: University of Oregon Computer and Information Sciences Dept.

ssimmons@convex.com (Steve Simmons) writes:
> [machines with separate register sets] can fetch, decode and execute both an
> integer and a floating point instruction on the same cycles. 
>
> Be careful about some of the hype in the marketing literature. The Intel
> i860 has been doing that for 4 years now.

Much earlier, the 11/70 did this.  Some predecessors of mine at
Reed built a nice numerical ODE solver which did this in
handcrafted assembly, and did about double the speed.  Then the
11/785 came along and the overlap was gone -- a sad waste of
hard work :-).

					Bart Massey
					bart@cs.uoregon.edu
[Overlapped integer and floating operations have been common for years.  The
360/91 did so in a very complicated way in 1969, and the Intel 8087 ran in
parallel with the 8086 in about 1978. -John]
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Newsgroups: comp.compilers
From: J.A. Eccleston <ecclesja@cs.aston.ac.uk>
Subject: Functional Languages
Reply-To: J.A. Eccleston <ecclesja@cs.aston.ac.uk>
Organization: Compilers Central
Date: Fri, 9 Oct 1992 16:06:34 GMT
Keywords: functional, question

I am writing concerning Functional Language compilation.

My final year project is to write a functional language for either the IBM
PC or SUN SPArc.

I would rather spend more of my available time on implementing the
mechanics of functional language compilation at the Lambda calculus level
to G-code levels, rather than worrying about native code generation.

To this end I was hoping that somebody on the Net might know of a public
domain G-Code compiler for either of the machines mentioned above.

If any one could help I would be most grateful.

Yours Sincerely

J.A. Eccleston (ecclesja@cs.aston.ac.uk)
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Xref: sparky comp.compilers:1728 misc.jobs.offered:12231
From: compilers-sender@iecc.cambridge.ma.us (Compilers daemon)
Newsgroups: comp.compilers,misc.jobs.offered
Subject: Compiler positions available
Keywords: jobs
Date: 11 Oct 92 14:58:59 GMT
Article-I.D.: comp.92-10-044
Reply-To: compilers-sender@iecc.cambridge.ma.us (Compilers daemon)
Organization: Compilers Central

This is a weekly digest of ``help wanted'' and ``position available''
messages received at comp.compilers.  Messages must advertise a position
having something to do with compilers and must also conform to the
guidelines periodically posted in misc.jobs.offered.  To submit a message,
mail it to compilers@iecc.cambridge.ma.us.


-------------------------------

Date: Mon, 5 Oct 92 13:19:08 -0400
Reply-To: paulb@rcx1.ssd.csd.harris.com (Paul Beusterien)
Subject: Compiler jobs at Harris in Ft. Lauderdale

Harris Computer Systems Division (HCSD) is looking for entry-level and
experienced software engineers to join our language processor group.  We
would like to find a highly motivated person with a strong interest and
background in compiler technology.  We develop C, Fortran and Ada
compilers that share a common code generator(CCG).  CCG uses
state-of-the-art code generation and optimization techniques.  It
generates code for multiple architectures including the latest Harris
Night Hawks based off of Motorola's 88000 family of RISC processors.

HCSD is a division of the Harris Corporation, a high-tech company
specializing in information, communications, and aerospace technology.
The Computer Systems Division, headquartered in Ft. Lauderdale, Florida,
designs and manufactures multi-processor computer systems.  These systems
are used for real-time simulation, ADA development systems, multi-level
secure systems, power plant control systems, space systems, weather radar
systems, and other applications with real-time computing needs.

All positions require U.S. citizenship or permanent residency.  In
addition, a BSCS is required as is a grade point average of at least 3.0
on a 4.0 scale.  A strong background in UNIX and C is also preferred.

If you are interested in joining our software development team and
enjoying the pleasures of the South Florida lifestyle we'd like to hear
from you. 

Send your resume to

	Paul Beusterien
	Harris Computer Systems Division
        Mail Stop #161
	2101 W. Cypress Creek Road
	Ft. Lauderdale, FL  33309-1892

Or email a copy to

       paulb@travis.csd.harris.com
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From: Cheryl_Lins@gateway.qm.apple.com (Cheryl Lins)
Newsgroups: comp.compilers
Subject: Re: instruction scheduling using genetic algorithms
Keywords: parallel, optimize, bibliography
Date: 12 Oct 92 21:42:01 GMT
Reply-To: "Cheryl Lins" <Cheryl_Lins@gateway.qm.apple.com>
Organization: Compilers Central

marco@einstein.et.tudelft.nl (M. van Harsel) writes:
>I am desperately seeking references and implementations on
>instruction scheduling using genetic algorithms.

As far as i know, you're delving into uncharted waters. So, assuming
you're a researcher, this should keep you busy for some time! :-)

Most scheduling problems using GAs have involved such things as production
and job shop schedules. I've never seen a paper on the use of GAs for the
instruction scheduling problem. (Doesn't mean one doesn't exist). Here are
some references to related problems which might help:

  Title: Genetic algorithms and job shop scheduling.
  Author: Biegel, John E.; Davern, James J.
  Proceedings of the 12th Annual Conference on Computers Industrial
Engineering
  Source: Computers & Industrial Engineering v 19 n 1-4 1990. p 81-91
  Publication Year: 1990

  Title: School bus routing using genetic algorithms.
  Author: Thangiah, Sam R.; Nygard, Kendall E.
  Conference Title: Applications of Artificial Intelligence X:
Knowledge-Based Systems
  Source: Proceedings of SPIE - The International Society for Optical
Engineering v 1707. Publ by Int Soc for Optical Engineering, Bellingham,
WA, USA. p 387-398
  Publication Year: 1992

  Title: Efficient multiprocessor scheduling based on genetic algorithms.
  Author: Hou, E. S. H.; Hong, R.; Ansari, N.
  Conference Title: 16th Annual Conference of IEEE Industrial Electronics
Society - IECON'90
  Source: Power Electronics Emerging Technologies IECON Proceedings
(Industrial Electronics Conference) v 2. Publ by IEEE, Computer Society,
Los Alamitos, CA, USA (IEEE cat n 90CH2841-5). p 1239-1243
  Publication Year: 1990

  Title: A genetic algorithm for job shop.
  Author: Falkenauer, E.; Bouffouix, S.
  Conference Title: Proceedings of the 1991 IEEE International Conference
on Robotics and Automation
  Source: Proceedings - IEEE International Conference on Robotics and
Automation v 1. Publ by IEEE, IEEE Service Center, Piscataway, NJ, USA
(IEEE cat n 91CH2969-4). p 824-829
  Publication Year: 1991

I also highly recommend Lawarence Davis' book "Handbook of Genetic
Algorithms".  It has an excellent and very readable tutorial as well as
numerous papers on applications of GAs.

Cheryl Lins, Oberon-2 Paladin. lins@apple.com
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Newsgroups: comp.compilers
From: cliffc@cs.rice.edu (Cliff Click)
Subject: Strength reduction of constant multipliers
Reply-To: cliffc@cs.rice.edu (Cliff Click)
Organization: Compilers Central
Date: Tue, 13 Oct 1992 15:13:58 GMT
Keywords: arithmetic, optimize, comment

I can send or post C code to do strength reduction of constant
multipliers.  It is reasonably fast (linear in the number of bits, i.e.
32) but not optimal.  If you are interested, reply to me.

Cliff
[I put in similar strength reduction to the AIX 1.0 C compiler for the ROMP;
basically you scan across the constant multiplier and for every non-zero bit
you add in the multiplicand shifted appropriately.  See Knuth, Volume 2,
pages 444-466 for more than you wanted to know on this topic. -John]
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From: karbasia@quartzite.cps.msu.edu (Hamid Karbasiafshar)
Subject: Optimization of livermore.c for gcc
Reply-To: karbasia@quartzite.cps.msu.edu (Hamid Karbasiafshar)
Organization: Michigan State University
Date: Fri, 9 Oct 1992 13:49:18 GMT
Keywords: optimize, benchmarks

I would like to know how to optimize the compilation of livermore.c
benchmark for a gcc compiler on sparc or convex machines

Thanks,
Hamid K.

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Newsgroups: comp.compilers
From: sanjay@equalizer.cray.com (+Sanjay Krishnamurthy)
Subject: Re: Getting GCC to software pipeline loops
Reply-To: sanjay@equalizer.cray.com (+Sanjay Krishnamurthy)
Organization: Compilers Central
Date: Tue, 13 Oct 1992 02:20:19 GMT
Keywords: optimize, GCC

>For my studies in cache memories I need a compiler which performs the
>SOFTWARE PIPELINING transformation to the code.  [How do I make GCC do that?]

What you already have in GCC is some form of instruction scheduling within
basic blocks. I would recommend adding some stuff which I elaborate below
to enhance this scheduler to pipeline code. Minimum perturbation is the
name of the game.

I will concentrate on pipelining loops with subscripted variable accesses
dominating the references in the loop.  You would first have to add some
mechanism to GCC to disambiguate memory references. Lets say you settle
for annotating the RTL such that every memory reference in a candidate
loop has its subscripting function appended to it. You will have to carry
loop bound information along too. There are a bunch of simple tests for
dependence analysis summarized in the paper "Efficient and exact
dependence data dependence analysis," D.E.Maydan, J.L.Hennessy and
M.S.Lam, SIGPLAN'91. Or if you are too lazy, get Michael Wolfe's Tiny
restructuring tool and use the dependence tests in it. After this first
step, you will (hopefully) have a dependence graph with either direction
or distance information. You are just one small step away from pipelining
the loop.

What you need now is a schedule of instructions which respects all the
dependence edges. The simplest schedule obeying this constraint can be
found by using a form of list scheduling-schedule a guy ASAP ignoring all
forms of resource constraints (huh, you might say.  Hang on dude...)

Hand the above schedule to the GCC scheduler which will then generate the
final form of the pipelined loop.

I am not sure what you mean by "without too much hustle." Does this
qualify??

Just wondering...
-Sanjay M. Krishnamurthy
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Newsgroups: comp.compilers
From: macrakis@osf.org (Stavros Macrakis)
Subject: Re: strength reduction of constant multiplication ?
Reply-To: macrakis@osf.org (Stavros Macrakis)
Organization: OSF Research Institute
Date: Mon, 12 Oct 1992 19:27:07 GMT
Keywords: arithmetic, theory

Youfeng Wu <wu@sequent.com> writes:

   ...It is beneficial to replace the multiplication by a sequence of
   [shift and add instructions]

   ...But I found out that for certain cases this algorithm is not
   optimal.  Do anyone know a reference on this subject?

Preston Briggs alluded to this, but to be more explicit: this problem is
very similar to the problem of computing powers with a minimal number of
multiplications.  The big difference is that shift(i) usually costs the
same as shift(1).  For a discussion of the power problem, in the form of
"addition chains", see Knuth's Art of Computer Programming vol 2
(Seminumerical Algorithms).

	-s
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Newsgroups: comp.compilers
From: marco@einstein.et.tudelft.nl (M. van Harsel)
Subject: Instruction scheduling using genetic algo. references
Reply-To: marco@einstein.et.tudelft.nl (M. van Harsel)
Organization: Delft University of Technology, Dept. of Electrical Engineering
Date: Tue, 13 Oct 1992 15:12:16 GMT
Keywords: optimize, bibliography

Dear readers, hello again,  

A few days ago I asked for references on instruction scheduling using
genetic algorithms. I was asked to summarize and send the reactions.
I would like to thank everyone who contributed with tips and references. 
 
I received the following literature list:

S.J. Beaty. A Study of Instruction Scheduling Using Genetic
Algorithms.
PhD thesis Mechanical Engineering Department, Colorado
State University Colorado 1991

Steven Beaty, Genetic Algorithms and Instruction Scheduling
24th Ann. Intl. Symp. on Microarchitecture
Albuquerque, NM, Nov. 1991, pp. 206-211.

Steven Beaty and Gearold Johnson and Darrell Whitley
Motivation and Framework for Using Genetic Algorithms
for Microcode Compaction, 
Proceedings of the 23th Microprogramming Workshop (MICRO-23)
Orlando 1990

Beaty, S.J.  Genetic Algorithms for Instruction
Sequencing and Scheduling
Proceedings from the Workshop on Computer Architecture Technology
and Formalism for Computer Science Research and Applications
Istituto per le Ricerche sui Sistemi Informatici Paralleli via
P. Castellino 111, 80125 Napoli (Italy) 1992
__
Marco van Harsel
A. Pauwstr 18
2613 DA Delft
The Netherlands
telephone : 015-131788 (countrynum = 31)
e-mail :  marco@duteca.et.tudelft.nl
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Newsgroups: comp.compilers
From: kendall@centerline.com (Sam Kendall)
Subject: Re: Register Files
Reply-To: kendall@centerline.com (Sam Kendall)
Organization: CenterLine Software, Inc.
Date: Wed, 7 Oct 1992 07:42:00 GMT
Keywords: registers, optimize

Steve Hobbs writes:

   A more interesting question is why doesn't the Alpha AXP architecture
   have any instructions that transfer values directly between the split
   register sets....  Transfers between registers banks are not all that
   common and increasing the speed of other operations even a small
   percentage justifies this decision.

Interesting!  SPARC also lacks instructions to transfer between integer
and float registers.  For the same reason?

Oddly, on SPARC, floating values are passed to functions, and returned
from functions, in integer registers.  This means that for a value to
get from a float register in the caller, to a float register in the
callee, requires that the value pass as follows:

						     function call
	float register -> memory -> integer register ---------------->
						     reg window shift
	integer register -> memory -> float register

Was the SPARC calling convention done this way to keep it simple (since
float registers are not windowed), even at the expense of performance,
or is there another explanation?

----
Sam Kendall
CenterLine Software, Inc. (formerly Saber Software)
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From: wjw@eb.ele.tue.nl (Willem Jan Withagen)
Newsgroups: comp.compilers
Subject: Re: Problems with gmd compiler tool 'rex'
Keywords: tools
Date: 7 Oct 92 23:50:59 GMT
Article-I.D.: comp.92-10-034
Reply-To: wjw@eb.ele.tue.nl (Willem Jan Withagen)
Organization: Eindhoven University of Technology, The Netherlands

=>Are there known problems with the latest version of rex in the gmd compiler
=>toolkit ('cocktail')?
=>Building and installing the toolkit went smoothly, but doing 'make test'
=>fails after rex spews out a lot of error/warning messages.

You get a list with characters which trigger the default action when 
encountered in the #STD# state. This can of course be errors in the input 
you source when you are running in scanner.

The other items are mostely information items.

I'm just back from CC '92, a compiler workshop in Paderborn Germany.
Where I met Josef Grosch, ( I also met many other nice people [Hi Deborah
8-)]) and I think that very soon a Cocktail mailing-list will be started.
(We certainly had a large number of downloads for the DOS/OS-2 version)

The main puroses for this will be:
  -	Create a group of people trying to use the same set of tools and learn
	from others' experiences.
  -	Let Josef see some concrete feedback on his tools.
  -	To keep up the high standards in comp.compilers.

In a week and half I'll be off on vacation for 4 weeks, and Josef was
going to consider my proposal and run the server in Karlsruhe. So by the
time I'm back I hope we can talk on the cocktail mailing list.

	Willem Jan Withagen.
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Eindhoven University of Technology   
P.O. 513                     		Tel: +31-40-473401,Fax: +31-40-448375
5600 MB Eindhoven            		The Netherlands
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Newsgroups: comp.compilers
From: marco@einstein.et.tudelft.nl (M. van Harsel)
Subject: instruction scheduling using genetic algorithms
Reply-To: marco@einstein.et.tudelft.nl (M. van Harsel)
Organization: Delft University of Technology, Dept. of Electrical Engineering
Date: Fri, 9 Oct 1992 14:52:29 GMT
Keywords: optimize, question

Dear readers,

I am desperately seeking references and implementations on
instruction scheduling using genetic algorithms.  Any help will be
appreciated.

Marco van Harsel
A. Pauwstr 18
2613 DA Delft
The Netherlands
telephone : +31 15 131788
e-mail :  marco@duteca.et.tudelft.nl
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Newsgroups: comp.compilers,comp.lang.fortran
From: steve@hubcap.clemson.edu ("Steve" Stevenson)
Subject: Fortran 90
Reply-To: steve@hubcap.clemson.edu ("Steve" Stevenson)
Organization: Clemson University
Date: Mon, 12 Oct 1992 14:57:32 GMT
Keywords: Fortran, parse

I would like to try something, but I need to find a PD parser for Fortran-90.
I would appreciate getting something, particularly if it was in yacc and/or
it is easy to modify. 

Thanks.

Steve
-- 
Steve (really "D. E.") Stevenson           steve@hubcap.clemson.edu
Department of Computer Science,            (803)656-5880.mabell
Clemson University, Clemson, SC 29634-1906
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Newsgroups: comp.compilers