HDTenEightyP/NetNews huggingface dataset:
From: scott@labtam.labtam.oz.au (Scott Colwell)
Subject: Re: Destroying Xilinx FPGAs by improper configuration?
Organization: Labtam Australia Pty. Ltd., Melbourne, Australia
Date: Tue, 12 Jan 1993 00:22:24 GMT

luoni@jasper.mlb.semi.harris.com (Perry Luoni) writes:

>In article <1993Jan11.142553.5103@ips.cs.tu-bs.de> koch@eis.cs.tu-bs.de (Andreas Koch) writes:
>>Is it possible to physically destroy a Xilinx 3000 series LCA
>>by programming only (meaning: outside electrical parameters
>>are within valid bounds)? Since we are in the process of
>>establishing FPGA design labs, we would like to know if
>>we have to watch out for critical design flaws which would
>>endanger our LCAs. Any hints are appreciated!
>>
>>Andreas Koch
>>-- 
>>Andreas Koch                                Email  : koch@eis.cs.tu-bs.de
>>Institut f"ur theoretische Informatik       Phone  : x49-531-391-2384
>>Abteilung Entwurf Integrierter Schaltungen  Phax   : x49-531-391-5840
>>Gaussstr. 11                                Telex  : 95 25 26

>Yes, it is possible to short a lot of nodes together with the wrong data programmed into
>the LCA.  If you are using the Xilinx design software you don't have to worry about
>it though.  The software will prevent you from programming it wrong.  


We are worried about this too.  We have been told that as long as the
configuration only causes internal drivers to clash with each other, the
device will survive, but if you cause pin drivers to clash with other
devices on your board, the device can be permanently damaged.

We are not totally convinced that this is good advice.  We have seen a device
get _very_ hot with only internal contention.


By the way, the problem is not doing this at the design stage.  If you are
building 200 units a week using an LCA in a pqfp package, you are going to
get a percentage of boards that will not correctly load the LCA config
from the prom.  (this is most likely when you use the parallel prom mode)
We see our prototype get very hot when it can't read the prom correctly
and we are worried that we will have the LCA destroyed on each board that
has a fault that stops the config prom from loading correctly.

-- 
Scott Colwell				Labtam Australia Pty. Ltd.
net:	scott@labtam.labtam.oz.au	41 Malcolm Rd., Braeside
phone:	+61-3-587-1444			Melbourne, Australia  3195
From: glipton@lafcol.lafayette.edu (Gary Lipton)
Newsgroups: comp.lsi.cad
Subject: PD VHDL tools
Date: 7 Jan 93 14:39:52 GMT
Organization: Dept. of EE, Lafayette College, Easton, PA
Originator: glipton@lafcol

I would like to find some public-domain VHDL simulation or
synthesis tools.  Thanks.

Gary Lipton
Lafayette College
-- 

* Gary Lipton                                   *
* Dept. of Electrical Engineering               *
* Lafayette College                             *
Newsgroups: comp.lsi.cad
From: philip@xilinx.com (Philip Freidin)
Subject: Re: Why no tri-state outputs in FPGA cells?
Organization: Xilinx Inc.
Date: Fri, 8 Jan 1993 19:47:44 GMT

In article <16200@auspex-gw.auspex.com> daryl@bovill.auspex.com (Daryl Starr) writes:
>I have heard from a gate array vendor that internal tristate requires lots
>of power (I assume from floating inputs being affected by noise) and thus
>has not been allowed. I would think that FPGA cells would be susceptible
>to the same problem.
>
>Daryl

Some time ago I posted an article detailing how our wonderful chips solve
this problem. Briefly:
	Internal tristates can draw more than normal power under two 
	conditions, Contention and Floating nets. 

	Contention is fixed by doing your design right, and not letting
	it happen.

	Floating nets are an issue if they float for more than a few
	nanoseconds. They can drift to VDD/2 which will cause recievers
	to draw continuous power (a few mA each). The Xilinx chips solve
	this with a circuit called a "weak keeper", that sustains the
	net value after the driver has been three-stated.

Note that other FPGA vendors that have three-state drivers do not have this
circiut, and so could get into problems if three state nets are left to
float.

Philip


-- 
Philip Freidin: Product Planning Manager, Xilinx, INC
(rest of clever .sig still under construction....
		coming to a terminal near you, Real Soon Now (tm))

Newsgroups: comp.lsi.cad,sci.electronics
From: luoni@jasper.mlb.semi.harris.com (Perry Luoni)
Subject: Re: Destroying Xilinx FPGAs by improper configuration?
Date: Mon, 11 Jan 1993 20:15:25 GMT
Organization: Harris Semiconductor, Melbourne FL

In article <1993Jan11.142553.5103@ips.cs.tu-bs.de> koch@eis.cs.tu-bs.de (Andreas Koch) writes:
>Is it possible to physically destroy a Xilinx 3000 series LCA
>by programming only (meaning: outside electrical parameters
>are within valid bounds)? Since we are in the process of
>establishing FPGA design labs, we would like to know if
>we have to watch out for critical design flaws which would
>endanger our LCAs. Any hints are appreciated!
>
>Andreas Koch
>-- 
>Andreas Koch                                Email  : koch@eis.cs.tu-bs.de
>Institut f"ur theoretische Informatik       Phone  : x49-531-391-2384
>Abteilung Entwurf Integrierter Schaltungen  Phax   : x49-531-391-5840
>Gaussstr. 11                                Telex  : 95 25 26

Yes, it is possible to short a lot of nodes together with the wrong data programmed into
the LCA.  If you are using the Xilinx design software you don't have to worry about
it though.  The software will prevent you from programming it wrong.
From: mdanjou@gel.ulaval.ca (Martin D'Anjou)
Newsgroups: comp.lsi.cad
Subject: Re: Is there a simple layout editor for the MAC
Date: 5 Jan 93 21:14:15 GMT
Reply-To: mdanjou@gel.ulaval.ca
Organization: Dept. Genie Electrique, Universite Laval

I am interested to that too. If there is a version for the PC I would appreciate to
know more about it (i.e. is it shareware?, where can I get it, etc.)

Martin d'Anjou
mdanjou@gel.ulaval.ca
From: kardank@ERE.UMontreal.CA (Kardan Kaveh)
Newsgroups: comp.lsi.cad
Subject: Looking for circuit-board layout software
Date: 11 Jan 93 00:38:25 GMT
Distribution: na
Organization: Universite de Montreal

I apologize if this is not the correct group.

I am trying to find a software package called, I believe, Redac.  It is
supposed to be a printed-circuit board layout package for the PC.

If you know where I can get info on this or similar packages, please email
me at:

	kaveh@mtrpls.login.qc.ca

Thanks,

Kaveh

-- 
------------
Kaveh Kardan                                       kaveh@taarna.UUCP
Systeme Taarna                                     kardank@eole.umontreal.qc.ca
Montreal Quebec Canada                             (514)844-8448
Newsgroups: comp.lsi.cad,sci.electronics
From: luoni@jasper.mlb.semi.harris.com (Perry Luoni)
Subject: Re: Destroying Xilinx FPGAs by improper configuration?
Date: Tue, 12 Jan 1993 15:25:38 GMT
Organization: Harris Semiconductor, Melbourne FL

In article <scott.726798144@labtam> scott@labtam.labtam.oz.au (Scott Colwell) writes:
>luoni@jasper.mlb.semi.harris.com (Perry Luoni) writes:
>
>>In article <1993Jan11.142553.5103@ips.cs.tu-bs.de> koch@eis.cs.tu-bs.de (Andreas Koch) writes:
>>>Is it possible to physically destroy a Xilinx 3000 series LCA
>>>by programming only (meaning: outside electrical parameters
>>>are within valid bounds)? Since we are in the process of
>>>establishing FPGA design labs, we would like to know if
>>>we have to watch out for critical design flaws which would
>>>endanger our LCAs. Any hints are appreciated!
>>>
>>>Andreas Koch
>>>-- 
>>>Andreas Koch                                Email  : koch@eis.cs.tu-bs.de
>>>Institut f"ur theoretische Informatik       Phone  : x49-531-391-2384
>>>Abteilung Entwurf Integrierter Schaltungen  Phax   : x49-531-391-5840
>>>Gaussstr. 11                                Telex  : 95 25 26
>
>>Yes, it is possible to short a lot of nodes together with the wrong data programmed into
>>the LCA.  If you are using the Xilinx design software you don't have to worry about
>>it though.  The software will prevent you from programming it wrong.  
>
>
>We are worried about this too.  We have been told that as long as the
>configuration only causes internal drivers to clash with each other, the
>device will survive, but if you cause pin drivers to clash with other
>devices on your board, the device can be permanently damaged.
>
>We are not totally convinced that this is good advice.  We have seen a device
>get _very_ hot with only internal contention.
>
>
>By the way, the problem is not doing this at the design stage.  If you are
>building 200 units a week using an LCA in a pqfp package, you are going to
>get a percentage of boards that will not correctly load the LCA config
>from the prom.  (this is most likely when you use the parallel prom mode)
>We see our prototype get very hot when it can't read the prom correctly
>and we are worried that we will have the LCA destroyed on each board that
>has a fault that stops the config prom from loading correctly.
>
One solution would be to current limit the supplies when you are testing the part.
There really isn't any way to eliminate the problem.  If you look at the schematics
to the 3000 series you will see you can pretty much connect anything with anything
or short damn near every node in the chip together.  If you want to try to burn one
out just for fun try programming every memory location to a one, I'm pretty sure
you will have a near worst case condition.   If you guys want to buy some radiation hardened
parts (3090) we will be selling them next year for about $3500.00 a piece.


Newsgroups: comp.lsi.cad
From: dinesh@surya.ece.uc.edu (Dinesh Bhatia)
Subject: CFP: Special Issue on FPGAs
Keywords: FPGA                            
Organization: University of Cincinnati
Date: Fri, 8 Jan 1993 22:30:50 GMT

                              CALL FOR PAPERS

                               VLSI DESIGN

 An International Journal of Custom-Chip Design, Simulation, and Testing

                              Special Issue

                                   on

                   Field-Programmable Gate Arrays (FPGAs)


Field-Programmable Gate Arrays (FPGAs) have  emerged as a revolutionary technology 
for very rapid prototyping. FPGA based systems allow total configurability and have 
achieved performance close to that of supercomputers. Real time hardware emulation
is very easily accomplished using FPGAs. 

This special issue will explore innovative 
ways for enhancing FPGA architecture, CAD for FPGAs, and FPGA applications.

Original contributions are sought in all areas related to FPGAs. Specific topics of
interest include, but are not limited to:


	o FPGA Architecture

	        Logic Block and Routing Architecture, New Innovative Designs.

	o CAD for FPGAs

	       Logic Synthesis, Partitioning, Placement and Routing, Testing.

	o FPGA Applications

	       Rapid Prototyping, Hardware Emulators, Accelerators.

	o Fabrication Technology

	       Programming Technology.

Prospective authors are invited to submit five copies of complete manuscript of high 
quality research contributions by May 31, 1993 to the Guest Editor: 

	Dr. Dinesh Bhatia, Guest Editor
	ECE Department, ML 0030	
	University of Cincinnati	
	Cincinnati, OH 45221-0030
	Phone: 513-556-2570	
	E-mail: Dinesh.Bhatia@UC.EDU

Instructions for Manuscript Preparation:

	Papers should not exceed 30 double spaced pages. This includes figures and
tables if any. Paers should not have been previously published. Also we cannot accept
papers that have been submitted elsewhere for publication. Papers should include
a clear title, author(s), address(es), telephone number(s), and FAX number(s). A
clear abstract not to exceed 300 words and a list of key words is also required. A
publication history for paper is also required for previously published abstracts
and conference notes. 

FOR FURTHER DETAILS PLEASE CONTACT DR. DINESH BHATIA

PUBLISHER: 

        Gordon and Breach Science Publishers



Xref: sparky comp.lsi.cad:1264 comp.os.ms-windows.misc:5943 comp.os.ms-windows.programmer.misc:4625
From: robert@koko.csustan.edu (Robert Zeff)
Newsgroups: comp.lsi.cad,comp.os.windows.programmer.win32,comp.os.ms-windows.misc,comp.os.ms-windows.programmer.misc
Subject: Spice for Windows3.1 & Windows NT uploaded
Date: 6 Jan 93 02:51:22 GMT
Organization: CSU, Stanislaus

32 bit Spice for Windows NT & Windows 3.1

I have uploaded my port of Berkeley's Spice ver 3e2 for 
Windows3.1 / Windows NT.  I've included the necessary files and
setup to install the Windows Win32s DLL if the target system is
Windows 3.1.  Win32s is Microsoft's 32 bit solution to allow 32
bit Windows NT binarys to run on the 16 bit Windows 3.1 system.

This version of Spice is full gui application.

(Spice is a powerful circuit simulator)

Robert Zeff                         (209) 521-1448, fax (209) 522-5866
CServe: 70323,1251

-- 
Robert Zeff                         (209) 577-4268 work, 577-8548 FAX
Xref: sparky comp.lsi.cad:1257 comp.arch:12065
From: daryl@bovill.auspex.com (Daryl Starr)
Newsgroups: comp.lsi.cad,comp.arch
Subject: Re: Why no tri-state outputs in FPGA cells?
Date: 4 Jan 93 17:09:02 GMT
Followup-To: comp.lsi.cad
Organization: Auspex Systems

I have heard from a gate array vendor that internal tristate requires lots
of power (I assume from floating inputs being affected by noise) and thus
has not been allowed. I would think that FPGA cells would be susceptible
to the same problem.

Daryl
Xref: sparky comp.lsi.cad:1288 sci.electronics:22512
From: zeke@fasttech.com (Bohdan Tashchuk)
Newsgroups: comp.lsi.cad,sci.electronics
Subject: Re: Destroying Xilinx FPGAs by improper configuration?
Date: 12 Jan 93 11:36:15 GMT
Article-I.D.: fasttech.1993Jan12.113615.4416
Organization: Fast Technology   Beaverton, OR

In <scott.726798144@labtam> scott@labtam.labtam.oz.au (Scott Colwell) writes:
>luoni@jasper.mlb.semi.harris.com (Perry Luoni) writes:

>>In article <1993Jan11.142553.5103@ips.cs.tu-bs.de> koch@eis.cs.tu-bs.de (Andreas Koch) writes:
>>>Is it possible to physically destroy a Xilinx 3000 series LCA
>>>by programming only (meaning: outside electrical parameters
>>>are within valid bounds)?

>>Yes, it is possible to short a lot of nodes together with the wrong data programmed into
>>the LCA.  If you are using the Xilinx design software you don't have to worry about
>>it though.  The software will prevent you from programming it wrong.  

>We are worried about this too.  We have been told that as long as the
>configuration only causes internal drivers to clash with each other, the
>device will survive, but if you cause pin drivers to clash with other
>devices on your board, the device can be permanently damaged.

>We are not totally convinced that this is good advice.  We have seen a device
>get _very_ hot with only internal contention.

There are additional ways you can get the devices to fail in the field. The
parts are CMOS, so, for example, if you accidentally let internal nodes
float, the part may conduct more current, get real hot, and fail soft.
Any type of floating node is bad for CMOS, since even dinky little inverters
can draw lots of current when their inputs are floating. And, of course, this
is very lot dependent.

Another poster mentioned that the design software protects you, but that wasn't
always true in the past, and I'm not sure if it's 100% true now. Also, where I
used to work one of the engineers would do all his own routing, since he got
much higher utilization than the software could do. A floating node or two did
slip thru, though, which caused some soft failures out in the field. These
were easy to diagnose, since the Xilinxes did get real hot. We gave our
customers the choice of a new serial PROM with new configuration bits or to
return the product to the factory for replacement of the Xilinx itself.
(Those PQFPs are no fun to rework!) Most customers chose the PROM, and
invariably the overstressed Xilinxes worked fine and ran nice and cool with
the new PROMs. Of course they may well have longer term reliability problems.
Newsgroups: comp.lsi,comp.lsi.cad,comp.lsi.testing,comp.arch,biz.comp.hardware
From: wyle@synopsys.com (Mitch Wyle)
Subject: Synopsys 1992 news summary posted to biz.comp.software
Organization: Synopsys Inc.
Date: Mon, 4 Jan 1993 22:29:21 GMT

Capsule summaries of all Synopsys press releases in 1992 posted to
biz.comp.software.

--
Mitch Wyle                     wyle@synopsys.com
Synopsys Inc                   (415) 694 4076 
700 E. Middlefield Rd.         (415) 965 8637 (fax)
Mountain View, CA  94043-4033  (800) 843 5669 x4076
Xref: sparky comp.lsi:774 comp.lsi.cad:1285 ieee.announce:109
From: tcp@philabs.philips.com (Tom C. Pirnat)
Subject: More Spice Models Needed
Organization: Philips Laboratories, Briarcliff Manor, NY.
Distribution: usa
Date: Thu, 7 Jan 1993 22:33:38 GMT


    Here we go again...
    I too am looking for specific Spice model files!  I downloaded the files
 graciously made available at minnie (discussed in the previous thread).  
 However, after scanning through the listing of models, I was unable to find 
 the model I was searching for (okay so I did not check EVERY model in EVERY 
 file but one must admit that there were alot of models to look through-thank
 you Warren!).  Specifically, I am looking for Power Bipolar models.  I would
 like a model for a device that has a Vceo >=800V.  

 Does such a beast exist?  If so where?

Thomas Pirnat
tcp@briar.philips.com
-- 
    Thomas Pirnat
    tcp@briar.philips.com 
Newsgroups: comp.lsi,comp.dcom.modems
From: mike@cd.com (Mike Heins)
Subject: Serial Communication Chips
Followup-To: gina@cd.com
Summary: Wanted: Suggestions for High-speed serial chips and U(S)ARTS
Keywords: serial UART USART comm
Organization: Central Data Corp., Champaign, IL
Date: Wed, 6 Jan 1993 19:20:40 GMT


Hi,

I'm looking for high performance serial communications chips
for a multi-port application.  The chip should be capable
of 115 Kbaud and have deep receive and transmit fifos (16 bytes 
or greater).  Please send any suggestions via email to gina@cd.com.

Thanks,
Gina
------------------------
Central Data Corporation	"Makers of the scsiTerminal Server"
1602 Newton Drive		(800) 482-0315
Champaign, IL 61821		mike@cd.com   or  ..!uunet!cendata!mike
Newsgroups: comp.lsi
From: dinesh@surya.ece.uc.edu (Dinesh Bhatia)
Subject: CFP: Special Issue on FPGAs
Keywords: FPGAs
Organization: University of Cincinnati
Date: Fri, 8 Jan 1993 22:29:27 GMT


                             CALL FOR PAPERS

                               VLSI DESIGN

 An International Journal of Custom-Chip Design, Simulation, and Testing

                              Special Issue

                                   on

                   Field-Programmable Gate Arrays (FPGAs)


Field-Programmable Gate Arrays (FPGAs) have  emerged as a revolutionary technology 
for very rapid prototyping. FPGA based systems allow total configurability and have 
achieved performance close to that of supercomputers. Real time hardware emulation
is very easily accomplished using FPGAs. 

This special issue will explore innovative 
ways for enhancing FPGA architecture, CAD for FPGAs, and FPGA applications.

Original contributions are sought in all areas related to FPGAs. Specific topics of
interest include, but are not limited to:


	o FPGA Architecture

	        Logic Block and Routing Architecture, New Innovative Designs.

	o CAD for FPGAs

	       Logic Synthesis, Partitioning, Placement and Routing, Testing.

	o FPGA Applications

	       Rapid Prototyping, Hardware Emulators, Accelerators.

	o Fabrication Technology

	       Programming Technology.

Prospective authors are invited to submit five copies of complete manuscript of high 
quality research contributions by May 31, 1993 to the Guest Editor: 

	Dr. Dinesh Bhatia, Guest Editor
	ECE Department, ML 0030	
	University of Cincinnati	
	Cincinnati, OH 45221-0030
	Phone: 513-556-2570	
	E-mail: Dinesh.Bhatia@UC.EDU

Instructions for Manuscript Preparation:

	Papers should not exceed 30 double spaced pages. This includes figures and
tables if any. Paers should not have been previously published. Also we cannot accept
papers that have been submitted elsewhere for publication. Papers should include
a clear title, author(s), address(es), telephone number(s), and FAX number(s). A
clear abstract not to exceed 300 words and a list of key words is also required. A
publication history for paper is also required for previously published abstracts
and conference notes. 

FOR FURTHER DETAILS PLEASE CONTACT DR. DINESH BHATIA

PUBLISHER: 

        Gordon and Breach Science Publishers

Newsgroups: comp.lsi.testing
From: brad@titan.austin.ibm.com (Brad Garton)
Subject: Readership
Date: Tue, 12 Jan 1993 14:36:51 GMT
Reply-To: brad@titan.austin.ibm.com  (Brad Garton)
Organization: IBM Advanced Workstation Division

Sure, 
 I am, 

 Brad Garton
 Advanced Workstation and Systems Division
 IBM
 Austin, Texas
___________________________________________________________
| Brad Garton  (512) 838-1333 | brad@titan.austin.ibm.com |
| I speak for myself not IBM  | VNET: GARTON AT AUSTIN    |
+---------------------------------------------------------+
Newsgroups: comp.lsi.testing
From: mdanjou@gel.ulaval.ca (Martin D'Anjou)
Subject: Data acquisition device
Organization: Universite Laval
Date: Mon, 11 Jan 1993 20:11:16 GMT

I would like to hear from those of you who would be interested in the 
following data acquisition device:

	- 32 Parallel Analog Inputs for DC (and temp) measurements (upgradable to 256)
	- 16 bit precision
	- 200 GOhms input impedance
	- 1 micro-volt resolution
	- Single-ended, differential or pseudo differential modes
	- Connects to ANY computer system via RS-232 (future version is plan to be HP-IB or VME or VXI)
	- low cost
	- 120 dB Rejection of 50 and 60Hz

Idealy suited for DC measurements of a chip. It is a datalogger. It can log interrupts (and the time at which it occurs) on any channel. Does frequency measurements. This is not a high speed machine but it is high accuracy and understands multi-channel low voltages levels.
It can be used as a stand-alone device, it can log data for any amount of time (up to the available RAM).
Very easy to program:
.7			voltage level at channel 7
.;7 9			voltages from channel 7 to 9, continuously
etc.

Respond by e-mail please.

Martin d'Anjou
mdanjou@gel.ulaval.ca 
Newsgroups: comp.lsi.testing
From: kenb@dadd.ti.com (Ken Butler)
Subject: Readership
Organization: Texas Instruments, Inc., Dallas, TX
Distribution: comp
Date: Mon, 11 Jan 1993 19:28:35 GMT

I'm curious about the readership of this newsgroup.  I've seen some
postings from some universities and a few assorted other postings, but
I'd suspect that are many more "comp.lsi.testing" readers out there.

Would people care to post their name and affiliation to the newsgroup?

Thanks.

Ken

--

*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
Kenneth M. Butler                           (214) 917-1759 (office)
Texas Instruments                           (214) 917-7966 (FAX)
P.O. Box 650311 MS 3937                     kenb@dadd.ti.com
Dallas, TX 75265
*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
Newsgroups: comp.lsi.testing
From: greason@ptdcs2.intel.com (Jeff Greason ~)
Subject: Re: Readership
Keywords: Survey of Readership
Organization: Intel Corporation -- Aloha, Oregon
Date: Tue, 12 Jan 1993 17:28:36 GMT

Jeff Greason
Sr. Design Engineer
Lead Vehicle Design: Portland Technology Development
Intel Corporation
From: jlew@sfsuvax1.sfsu.edu (Jimmy Lew)
Newsgroups: comp.lsi.testing
Subject: Re: Testing..
Date: 9 Jan 93 05:35:19 GMT
Organization: San Francisco State University

this is a test
test
test 
this really works
From: elliott@optilink.COM (Paul Elliott)
Newsgroups: comp.lsi.testing
Subject: Readership
Keywords: Survey of Readership
Date: 12 Jan 93 19:06:18 GMT
Organization: DSC/Optilink Access Products


Present!



-- 
--------     Paul Elliott - DSC Optilink - Petaluma, CA USA      ----------
     {uunet,pyramid,tekbspa}!optilink!elliott -or- elliott@optilink.com
    "If I had known it was harmless I would have killed it myself." - PKD

Newsgroups: comp.lsi.testing