From: nieznan@zeppo.crd.ge.com (John A. Nieznanski)
Newsgroups: misc.jobs.resumes
Subject: EE: Mixed Signal ASICs / Multi-Chip Modules / Relocatable
Date: 7 Apr 92 16:52:17 GMT
Distribution: usa
Organization: GE Corp. Research & Development, Schenectady, NY






General Electric Co.
Corporate Research & Development
Bldg. KW  Room C1639
P.O. Box 8
Schenectady, NY 12301
April 6, 1992


Dear Engineering Professional,

I am writing to you to inquire into career opportunities that your organization
may have for electrical engineers with a background in analog/digital hardware
design and related supporting activities.

Currently, I am a Senior Consultant with General Electric Consulting Services,
and have been working at GE's Corporate Research and Development Center for 
the past five years. Previously, I was a Senior Design Engineer in the Digital
Laboratory of Raytheon Co's. Missile Systems Division in Bedford, MA for nearly
four years. Through my education and experience, I have gained a broad exposure
to advanced electrical engineering applications, particularly in the design and
test of digital and mixed-signal ASIC's, multi-chip modules and microprocessor
based subsystems.
                                       
These subsystems have been successfully demonstrated and integrated into a wide
range of both prototype and production hardware. Examples include missile
systems, high performance power supplies, ultrasonic medical imaging systems, 
lighting systems, and space-based systems for various government contractors
and national laboratories as well as commercial industry.

Enclosed please find my experience profile detailing my academic and 
engineering career history. I am most interested in learning what contributions
I can make to your organization's efforts. I consider myself to be a highly
motivated, versatile professional who can accept challenging responsibilities
and deliver consistent, high quality results on schedule and within budget.

I look forward to talking with you in the near future. If you need to contact 
me, my telephone number is 518-371-1727 (home) or 518-387-5006 (office).

Sincerely,



John Nieznanski


















			    JOHN A. NIEZNANSKI


Home:   5 Starboard Ct.                         Office: GE/CRD, KWC1639, POBox 8
        Waterford, NY 12188                             Schenectady, NY 12301
Phone:  (518) 371-1727                          Phone:  (518) 387-5006
                                                E-mail: nieznan@crd.ge.com
 
 
OBJECTIVE:      Energetic self-starter seeks opportunity to apply extensive
                design and test experience with advanced ASIC and Multi-Chip
                Module technology in a challenging, growth oriented environment.


EXPERTISE:      MIXED-SIGNAL ASIC DESIGN, DIGITAL VLSI DESIGN, MICROPROCESSOR
                BASED DESIGN, MULTI-CHIP MODULES, TEST DEVELOPMENT, HARDWARE
                INTERFACING, DESIGN FOR TESTABILITY, PROCESS DEVELOPMENT, CAD
                TOOL DEVELOPMENT, DEVICE MODELLING/CHARACTERIZATION, PROJECT
                LEADERSHIP. ADEPT AT OVERCOMING ORGANIZATIONAL, STRUCTURAL AND
                FUNCTIONAL BOUNDARIES TO OBTAIN OBJECTIVES.


EDUCATION:      Colgate University, Hamilton, NY     
                B.A. in Physics - 1977

                Dartmouth College/Thayer School of Engineering, Hanover NH
                B.E. in Electrical Engineering - 1983
                Thesis - "A Microprocessor-Based Sidereal Clock/Calculator"

                Microprocessor Design (6/83) Raytheon Co.
                VLSI Design (6/85) Raytheon Co.
                Solid State Fundamentals (12/87) GE/CRD
                Basic Power Electronic Circuits (9/88) GE/CRD
                Design of MOS Analog Integrated Circuits (6/89) MIT
                Power Electronic Conversion Principles (7/90) GE/CRD
                "C" Programming (7/91) GE/CRD


COMPUTER SKILLS:
 
Hardware:       SUN 3/4, DEC VAX, IBM PC, MENTOR/APOLLO
O/S:            UNIX, VMS, MS-DOS, AEGIS/DOMAIN
Languages:      C, Fortran, Basic, Pascal, PL/M, Assembly
CAD Tools:      Logic simulation, analog simulation, mixed mode simulation, 
                physical layout, schematic capture, netlist extraction, 
                parasitic extraction, back-annotation, design rule checking,
                AUTOCAD.
Test Tools:     fault simulation, CAD/test translation, test development S/W.


ATE/LAB EQUIPMENT:

ATE:            IMS XL/2, Tektronix LT-1000, Fairchild SENTRY VII.
LAB:            Logic analyzers, Curve tracers, Impedance/gain-phase analyzers,
                various oscilloscopes, waveform/pulse generators, IEEE-488 
                (GPIB) controlled equipment, In-circuit emulators.


EXPERIENCE:     May 1990 to present (GECON Consultant to GE/CRD)
                HDI MULTI-CHIP MODULE DESIGN/TEST ENGINEER 

Responsible for providing technical leadership in design and testing of hybrid 
MCM's (Multi-Chip Modules) fabricated with HDI (High Density Interconnect)
process. HDI modules are used to obtain a superior performance advantage over 
similar circuitry implemented with standard packaging technology. As such, 
MCM technology is used in applications where performance is critical, e.g. 
space-based systems. IC technologies used include TTL, bulk CMOS, CMOS/SOI, 
GaAs. Project leader/customer interface on several programs for Air Force 
Weapons Lab (SPIRIT), Lawrence Livermore National Labs (RISC, RISC 3-D), 
Defense Nuclear Agency (ONYX, OTM). Lead effort to develop proprietary die 
pretest/recovery process to enable insertion of burned-in, fully characterized,
known good die into a MCM. Co-author of paper to be presented at IEEE MCMC-92
(Multi-Chip Module Conference) detailing proposal to die vendors for providing
value added services to MCM foundries through enhancement of above die pretest/
recovery process for application in wafer level processing. Developed methods 
for incorporating floating gate technology devices (Flash EEPROM) which are UV
erasable in die form. Presently developing 3-D stack technology for RISC MCM 
architectures. KEY SKILLS: DESIGN, ANALYSIS, MEASUREMENT OF MULTI-CHIP MODULES;
RISC ARCHITECTURES; PROCESS DEVELOPMENT; PROJECT LEADERSHIP.

                November 1986 - April 1990 (GECON Consultant to GE/CRD)
                CMOS/BiCMOS ANALOG/DIGITAL ASIC DESIGN/TEST ENGINEER

Performed wide variety of design and test tasks to support development of
custom/semi-custom mixed signal IC's for use in high performance power
supplies, ultrasound medical systems and lighting systems utilizing CMOS and
BiCMOS processes. Specific responsibilities included circuit design, device
modelling, device characterization, SPICE simulation, logic simulation, layout,
parasitic extraction, design rule checking, performance testing. Analog
subcircuits include numerous op-amps, comparators, voltage controlled
oscillators, delay stages, one shots, under/over voltage detectors, bandgap 
references, high voltage transmission gates, voltage to current converters, 
various buffers and drivers. Digital subcircuits include both combinational 
and sequential gates. KEY SKILLS: CIRCUIT DESIGN; PHYSICAL LAYOUT; DEVICE 
CHARACTERIZATION AND MODELING; INTEGRATED CIRCUIT PERFORMANCE TESTING.
		                                                 
                July 1986 - October 1986
                ASIC DESIGN ENGINEER - RAYTHEON CO./MSD - Bedford, MA

Supervised the design and testing of a CMOS VLSI (gate array) Digital Logic
Chip. The multi-function CMOS gate array was designed to upgrade the
performance of existing TTL devices used in ground-based missile hardware.
KEY SKILLS: CIRCUIT DESIGN; LOGIC SIMULATION; PROJECT LEADERSHIP.

                November 1985 - July 1986
                ASIC DESIGN ENGINEER - RAYTHEON CO./MSD - Bedford, MA

Designed two-thirds of a CMOS VLSI Digital Signal Processor Chip. The chip 
is a central part of an advanced missile-borne signal processing system with 
VHSIC-grade performance ratings performing all of the arithmetic algorithms 
required for the system. KEY SKILLS: DSP ALGORITHM DESIGN; MICROCONTROLLER 
DESIGN; MICROCODE DEVELOPMENT.
                                                                 
                January 1985 - November 1985
                ASIC DESIGN ENGINEER - RAYTHEON CO./MSD - Bedford, MA

Was solely responsible for the concept, design, development and testing of a
VLSI Built-In, Self-Test Circuit and a Design For Test Methodology. The system
involved the design of a general purpose testability macrocell (CTC - Chip Test
Controller) with both manual and automatic test capabilities for use on all
VLSI/VHSIC circuits. The CTC incorporates a pseudo-random number generator as a
test vector source and a signature analyzer for data compression. The CTC 
communicated off-chip via a 4 pin interface and an enhanced version of the 
protocol which was later adopted as the IEEE JTAG 1149.1 standard. KEY SKILLS:
DESIGN FOR TEST STRATEGIES; STRUCTURED DESIGN TECHNIQUES; FAULT SIMULATION.

                October 1983 - December 1984
                CAD ENGINEER - RAYTHEON CO./MSD - Bedford, MA

Participated in the implementation and maintenance of a Mentor Graphics/Apollo
CAD/CAE System. The system was implemented to develop digital ASIC's for 
missile system hardware. Responsible for developing accurate digital models for 
installation into numerous cell library databases. Utilized SPICE simulation 
data of primitive functions to derive timing characteristics for complex 
digital models. Generate behavioral models for large macrocells using Pascal.
Developed routines for translating simulator output into SENTRY tester input.
KEY SKILLS: CELL LIBRARY DEVELOPMENT, CAD/TEST TRANSLATOR DEVELOPMENT.

                February 1983 - October 1983
                TEST ENGINEER - RAYTHEON CO./MSD - Bedford, MA

Solely responsible for generating and developing test programs and tester
interfaces for digital circuit boards. KEY SKILLS: CIRCUIT ANALYSIS; TEST
SOFTWARE DEVELOPMENT.

                February 1978 - September 1981
                RETAIL ELECTRONICS MGR. - RADIO SHACK/TANDY CORP. - Roch., NY

Supervised the daily operations of several low to medium volume, company-owned
retail electronics outlets in the Rochester, NY area. Specialized in the
marketing of TRS-80 computers for personal and small business applications.
Numerous management and sales awards. KEY SKILLS: PROFIT/LOSS RESPONSIBILITY;
CONSUMER ELECTRONICS MARKETING; INVENTORY CONTROL; SALES STAFF MANAGEMENT.


HONORS, AWARDS, PUBLICATIONS:

Co-author, "Window on the Infrastructure - Known Good Die", IEEE MCMC-92
Cost savings suggestion implemented by Raytheon Co., May 1985; awarded $5,490 
Harvey V. Picker '36 Physics Prize for Scholarship, April 1977
Co-author, "On the Distance to the Origem Loop", Ap. J., April 15, 1977


PERSONAL:

Hobbies include team sports, travel, writing/recording music. 
Technical volunteer/scientific advisor to local school districts.