HDTenEightyP/NetNews huggingface dataset:
From: heike@irs241.inf.tu-dresden.de (Heike Garbe)
Subject: Re: book and review
Keywords: books
Reply-To: heike@irs241.inf.tu-dresden.de (Heike Garbe)
Organization: Free University of Berlin, Germany
Date: Wed, 9 Sep 1992 20:42:54 GMT


In article <592603tx7cTa00@amdahl.uts.amdahl.com>, aurora@uts.amdahl.com
(Sunic Aurora) writes:
|>
|>A few weeks ago, someone had posted an article containing a list of
|>books on VHDL.
|>He had also included a brief review.
|>Could anyone mail me a copy of that article.
|>  Thanks
|>            sunil
|>


I'd mail your the FAQ-files.

Heike.
From: aurora@uts.amdahl.com (Sunic Aurora)
Newsgroups: comp.lang.vhdl
Subject: book and review
Summary: books on vhdl
Keywords: books
Date: 8 Sep 92 16:35:00 GMT
Organization: Amdahl Corporation, Sunnyvale CA


A few weeks ago, someone had posted an article containing a list of books on VHDL.
He had also included a brief review.
Could anyone mail me a copy of that article.
  Thanks
            sunil
From: praveen@sirius.mcc.com (Praveen Vishakantaiah)
Newsgroups: comp.lang.vhdl
Subject: Specifying sequential behavior
Date: 14 Sep 92 20:23:03 GMT
Organization: Microelectronics and Computer Technology Corp.

I am trying to use VHDL to specify the RESET sequence of a finite state
machine. Has anybody tried to do this before? The general question is, 
how do you specify the behavior of a module which is sensitive to a 
sequence of values (can be potentially very long)? Here is an example:

entity SEQ_BLOCK is
   port (CLOCK : in Bit;
	 INPUT : in Bit_Vector(1 downto 0);
         STATE : out Bit_Vector(1 downto 0));
end COUNTER;

Now, I want to specify that STATE becomes "00", if INPUT is "00" on the
first positive edge of the clock, followed by "11" on the second positive
edge of the clock followed by "01" on the third positive edge of the 
clock.

Any ideas or previous experiences to handle this sort of a thing in VHDL?

Thank you,
Praveen Vishakantaiah.

------------------------------------------------------------------------------
-- Microelectronics and Computer Technology Corporation, | Ph : (512)338-3736|
-- 3500 W. Balcones Center Drive                         | e-mail :          |
-- Austin, TX 78759.                                     | praveen@mcc.com   |
------------------------------------------------------------------------------
-- ALSO A HARD WORKING MEMBER OF :-)                     |
-- Computer Engineering Research Center,                 | Ph : (512)471-8013|
-- University of Texas, Austin.             e-mail : praveen@cerc.utexas.edu | 
-----------------------------------------------------------------------------
From: narayan@ceres.ics.uci.edu (Sanjiv Narayan)
Subject: Re: Specifying sequential behavior
Newsgroups: comp.lang.vhdl
Organization: UC Irvine Department of ICS
Date: 14 Sep 92 23:15:58 GMT
Distribution: usa

In <1992Sep14.202303.13701@mcc.com> praveen@sirius.mcc.com (Praveen Vishakantaiah) writes:

>I am trying to use VHDL to specify the RESET sequence of a finite state
>machine. Has anybody tried to do this before? The general question is,
>how do you specify the behavior of a module which is sensitive to a
>sequence of values (can be potentially very long)? Here is an example:
>
>entity SEQ_BLOCK is
>   port (CLOCK : in Bit;
>	 INPUT : in Bit_Vector(1 downto 0);
>         STATE : out Bit_Vector(1 downto 0));
>end COUNTER;
>
>Now, I want to specify that STATE becomes "00", if INPUT is "00" on the
>first positive edge of the clock, followed by "11" on the second positive
>edge of the clock followed by "01" on the third positive edge of the
>clock.



  How about having the following process in the entity SEQ_BLOCK:

  --------------------------------------------------
  process
  begin

     wait until (CLOCK='1' and not(CLOCK'stable) );

     if (INPUT = "00") then
        wait until (CLOCK='1' and not(CLOCK'stable) );

        if (INPUT = "11") then
           wait until (CLOCK='1' and not(CLOCK'stable) );

           if (INPUT = "01") then
              STATE <= "00" ;
           end if;
        end if;
     end if;

  end process;
  --------------------------------------------------


  Sanjiv Narayan
  Univ. of California, Irvine


Newsgroups: comp.lang.vhdl
From: psbapat@mtu.edu (   BAPAT)
Subject: Re: book and review
Keywords: books
Organization: Michigan Technological University
Date: Sat, 12 Sep 1992 18:55:01 GMT

In article <592603tx7cTa00@amdahl.uts.amdahl.com>, aurora@uts.amdahl.com (Sunic Aurora) writes:
> 
> A few weeks ago, someone had posted an article containing a list of books on VHDL.
> He had also included a brief review.
> Could anyone mail me a copy of that article.
>   Thanks
>             sunil


Me too. Thanks.

-- 

Pushpak Bapat                      | LIFE IS LIKE A SEWER; WHAT YOU GET OUT 
e-mail: psbapat@mtu.edu            | OF IT DEPENDS ON WHAT YOU PUT INTO IT!
Michigan Technological University  |                           - Tom Lehrer
From: mike.kopp@gtri.gatech.edu (Mike Kopp)
Newsgroups: comp.lang.vhdl
Subject: extended integer size?
Date: 8 Sep 92 16:38:07 GMT
Followup-To: comp.lang.vhdl
Organization: Georgia Tech Research Institute

I am working on a high-level design in which I use integer variables.  Some
of the variables can have up to 16 bits (unsigned) so that if multiply two
of them the result could be 32 bits unsigned.  My vhdl implementation uses
32-bit integers so the largest unsigned integer is 31 bits so I cannot
represent the result using standard integers.  Has anyone implemented a
portable "integer-like" type to extend the integer size to some arbitrary
but fixed length?  Has anyone any suggestions as to how I should proceed?

-----------
Mike Kopp                                    
Electronic Support Measures Laboratory   	       
Georgia Tech Research Institute 	       	       	mike.kopp@gtri.gatech.edu
Newsgroups: comp.lang.idl
From: amir@fina.ugo.no 
Subject: Test
Reply-To: amir@fina.ugo.no 
Organization: FINAB Co.
Date: Sun, 6 Sep 1992 13:04:13 GMT


It is a test
                  Amir


Newsgroups: comp.lang.idl
From: offenberg@stars.gsfc.nasa.gov (JOEL D. OFFENBERG (301) 286-5801)
Subject: Widget IDL question
News-Software: VAX/VMS VNEWS 1.4-b1  
Organization: NASA/GSFC-Laboratory for Astronomy and Solar Physics
Date: Mon, 14 Sep 1992 18:37:00 GMT

We are having trouble with using the Widget version of IDL when there are m
multiple IDL sessions on the same workstation...As with regular IDL, there
is a clash over the color tables.  In non-widget IDL, this usually causes
the screen to go dark when the wrong window is selected, etc.  However,
when there are two WIDL sessions at the same time, the color table clash
when trying to create a widget causes your IDL session to crash.

Is there a way to have multiple (W)IDL sessions share one color table?  Or 
part of one?  

I don't know if this question has been asked before, but if it has, please 
forward the answer to me... 

	Thanks,
	Joel D. Offenberg
	(Offenberg@Stars.gsfc.nasa.gov)
From: hampton@ecadsr.enet.dec.com (Jonathan D. Hampton)
Subject: Displaying waveforms?
Organization: Digital Equipment Corporation
Date: Wed, 9 Sep 1992 15:18:21 GMT


I'm using Cadence's VERILOG-XL tool and I was wondering if anyone
can tell me how to display simulation results as waveforms on the screen
or in a file.  The tutorial mentions a graphical output facility, but
the manuals do not.

Can anyone help?

Thanks.

Hamp 


-----

Jonathan "Hamp" Hampton 	  hampton@ecadsr.enet.dec.com


	"Zipperphobia?  *BUTTON* your fly!"

-----
From: manley@optilink.UUCP (BIFF!!!!1)
Newsgroups: comp.lang.verilog
Subject: constant expressions, parameters, `define
Date: 15 Sep 92 22:48:54 GMT
Distribution: usa
Organization: DSC/Optilink Access Products


I'd like to do the following:

parameter pOW = 27;
parameter [pOW-1:0]  
  Xvob = pOW'b1 << 26;
         ^^^

Apparently, verilog doesn't allow this wanting instead:

  Xvob = 27'b1 << 26;
         ^^

I guess I have to use: 

`define pOW 27
parameter [`pOW-1:0]  
  Kibo = `pOW'b1 << 26;  

I'd been using parameters instead of `defines to avoid
having to use the ` on macro substitutions.  Why does
verilog require the ` ?  This aspect of the language
seems a little ridiculous.

I'd like to get rid of the "26" as well, replacing it with a 
variable so that I can do things like:

i = `pOW-1;
parameter [`pOW-1:0]
  Obik = `pOW'b1 << i; i=i-1;
  Xibo = `pOW'b1 << i; i=i-1;

Oh yeah, I want to take my source into synopsys for synthesis.

Any comments? Ideas?

--
dave
manley@optilink.com
Newsgroups: comp.lang.verilog
From: kenr@orleans.storage.tandem.com (Ken Rose)
Subject: Re: Displaying waveforms?
Organization: Tandem Computers Inc, Cupertino CA
Date: Wed, 9 Sep 1992 18:54:30 GMT

In article <1992Sep9.142630.9560@engage.pko.dec.com>, hampton@ecadsr.enet.dec.com (Jonathan D. Hampton) writes:
> 
> I'm using Cadence's VERILOG-XL tool and I was wondering if anyone
> can tell me how to display simulation results as waveforms on the screen
> or in a file.  The tutorial mentions a graphical output facility, but
> the manuals do not.
> 
> Can anyone help?
> 
> Thanks.
> 
> Hamp 
> 
> 



You need a copy of the "Graphical OUtput for the Verilog Product
Family" reference manual.  Your dealer should be able to supply
you with a copy.

-- Ken
____________________________________________________________________
Ken Rose    (kenr@storage.tandem.com)
The Usual Disclaimer:  Any opinions expressed above are mine alone, not
those of my employer (who is kind enough to allow me Usenet access).
From: ericj@hwcae.Honeywell.COM (Eric Jacobsen)
Subject: Re: Displaying waveforms?
Organization: Honeywell, Air Transport Division; Phoenix, AZ
Date: Wed, 9 Sep 1992 20:01:57 GMT

   In article <1992Sep9.142630.9560@engage.pko.dec.com>, hampton@ecadsr.enet.dec.com (Jonathan D. Hampton) writes:
   > 
   > I'm using Cadence's VERILOG-XL tool and I was wondering if anyone
   > can tell me how to display simulation results as waveforms on the screen
   > or in a file.  The tutorial mentions a graphical output facility, but
   > the manuals do not.
   > 
Assuming your system has all the appropriate hooks, all you need in your
code is:

	$gr_waves( "label", signal,
		   "label2", signal2,
		   "bus", bus_name,
		   "more", stuff );

Up to 21 labels (I think) can be displayed in one group. You can define
more than one group and switch between them.

Put the $gr_waves(...); in your .vt file.

Hope this helps...

--
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
* Eric Jacobsen        Honeywell Inc.                           *
|     1-602-436-3941   Commercial Flight Systems, Air Transport |
* HVN       436-3941   US Mail: P.O. Box 21111, MS 2Q34C1       *
| FAX 1-602-436-1310   Phoenix AZ 85036-1111                    |
* INet: ericj@hwcae.honeywell.com                               *
| UUCP: uunet!hwcae.honeywell.com!ericj@uunet.uu.net            |
* The opinions expressed are my own and therefore better        *
| thought out than my employer's.                               |
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

Newsgroups: comp.lang.verilog
From: praveen@sirius.mcc.com (Praveen Vishakantaiah)
Subject: Veritools
Organization: Microelectronics and Computer Technology Corp.
Date: Tue, 15 Sep 1992 14:05:06 GMT

I tried to use the veritools that I obtained by doing an "ftp" from
netcom.netcom.com (this information was posted earlier by someone), but
got this message:

   vflat: "vflat" no such feature configured

Any ideas as to what the problem maybe? Do I need to do something before
I can starting using the tools.

Also, in the README file in the vflat directory, it says:

   Another version of the program, in addition to flattening can also 
   translate the netlist from Verilog to several other formats such as 
   FutureNet, VHDL, EDIF. IKOS or MOTIVE.

I could not find any such program that can translate netlists in Verilog
to other HDL. I was particularly interested in translating Verilog
netlists into VHDL netlists.

Thank you,
Praveen Vishakantaiah.

------------------------------------------------------------------------------
-- Microelectronics and Computer Technology Corporation, | Ph : (512)338-3736|
-- 3500 W. Balcones Center Drive                         | e-mail :          |
-- Austin, TX 78759.                                     | praveen@mcc.com   |
------------------------------------------------------------------------------
-- ALSO A HARD WORKING MEMBER OF :-)                     |
-- Computer Engineering Research Center,                 | Ph : (512)471-8013|
-- University of Texas, Austin.             e-mail : praveen@cerc.utexas.edu | 
-----------------------------------------------------------------------------
Newsgroups: comp.lang.verilog
From: hampton@ecadsr.enet.dec.com (Jonathan D. Hampton)
Subject: Re: Displaying waveforms?
Organization: Digital Equipment Corporation
Date: Fri, 11 Sep 1992 14:09:12 GMT


In article <ERICJ.92Sep9140157@calcutta.cfsat.Honeywell.COM>, ericj@hwcae.Honeywell.COM (Eric Jacobsen) writes...
>   In article <1992Sep9.142630.9560@engage.pko.dec.com>, hampton@ecadsr.enet.dec.com (Jonathan D. Hampton) writes:
>   > 
>   > I'm using Cadence's VERILOG-XL tool and I was wondering if anyone
>   > can tell me how to display simulation results as waveforms on the screen
>   > or in a file.  The tutorial mentions a graphical output facility, but
>   > the manuals do not.
>   > 
>Assuming your system has all the appropriate hooks, all you need in your
>code is:
> 
>	$gr_waves( "label", signal,
>		   "label2", signal2,
>		   "bus", bus_name,
>		   "more", stuff );
> 
>Up to 21 labels (I think) can be displayed in one group. You can define
>more than one group and switch between them.
> 
>Put the $gr_waves(...); in your .vt file.
> 
>Hope this helps...
> 
>--
>*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
>* Eric Jacobsen        Honeywell Inc.                           *
>|     1-602-436-3941   Commercial Flight Systems, Air Transport |
>* HVN       436-3941   US Mail: P.O. Box 21111, MS 2Q34C1       *
>| FAX 1-602-436-1310   Phoenix AZ 85036-1111                    |
>* INet: ericj@hwcae.honeywell.com                               *
>| UUCP: uunet!hwcae.honeywell.com!ericj@uunet.uu.net            |
>* The opinions expressed are my own and therefore better        *
>| thought out than my employer's.                               |
>*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
> 

Thanks to all who replied here and by mail!  I found the manual.

Hamp


-----

Jonathan "Hamp" Hampton 	  hampton@ecadsr.enet.dec.com


	"Zipperphobia?  *BUTTON* your fly!"

-----
From: manley@optilink.UUCP (Dave Manley)
Newsgroups: comp.lang.verilog
Subject: low posting volume on comp.lang.verilog
Date: 4 Sep 92 22:41:48 GMT
Distribution: usa
Organization: DSC/Optilink Access Products

We get very few postings in this news group, one post
a day or fewer.  Is it possible I'm getting a partial
feed and not seeing everything?

If you get a substantially higher volume of postings
please email me at manley@optilink.com so that I
can get my sysadmin to fix things.

thanks,

dave
manley@optilink.com

Newsgroups: comp.lang.verilog
From: steveg@popeye.cadence.com (Steven Greenberg; x6231)
Subject: Re: Analogue modeling by Verilog
Reply-To: steveg@popeye.cadence.com (Steven Greenberg; x6231)
Organization: Cadence Design Systems, Inc.
Date: Tue, 8 Sep 1992 17:49:25 GMT

Analog modelling is not Verilog's forte, but it can be done.  In fact, if you
order the mixed-signal product with Analog Artist, you get some analog
behavioral models in Verilog.

I don't claim to be a Verilog modelling expert, but I once wrote a vco model
in Verilog to prove to some people that it could be done.

To pass an analog value into a Verilog module, you have to create a 64-bit wire
port.  You then use system functions like $bitstoreal to convert the wire at
the port to a real number inside the module.  Once you have real numbers inside
the module, you can do anything you want.

/Steve
Newsgroups: comp.lang.scheme
From: jeff@aiai.edinburgh.ac.UK (Jeff Dalton)
Subject: Re: What I learned from building Dylan/Thomas
Organization: The Internet
Date: Tue, 15 Sep 1992 17:20:02 GMT

>   sorted-applicable-methods finds the applicable methods and sorts
>     them from most- to least-specific.  We used a topological sort of
>     all of the classes in the system.  

What makes this possible?  (I don't remember enough about Dylan to
say.)  Anyway, it's not possible in CLOS.  For instance, I can define

  (defclass a (r s) ...)
  (defclass b (s r) ...)

In the class precedence list of A, R comes before S; but in the
precedence list for B, S comes before R.  Consequently, for an
instance of A, R methods are more specific than S methods; but
for an instance of B it's the other way 'round.

-- jd
From: dyer@eagle.sharebase.com (Scot Dyer)
Newsgroups: comp.lang.scheme
Subject: Re: wots going on here!?
Date: 8 Sep 92 16:22:08 GMT
Reply-To: dyer@eagle.sharebase.com (Scot Dyer)
Organization: NCR/ShareBase Corporation

%[...]bh@anarres.CS.Berkeley.EDU (Brian
%Harvey) writes:
%|> P.S.  Yes of course if an error happens inside a procedure you should be
%|> told its name.  My example was too simple, I guess.  What Logo does on
%|> an error is tell you the error, the procedure in which it happened, and
%|> the line of the procedure definition that contains the error.
%
%The problem in Scheme, as I use it, is that it is not a very interesting
%information as I use a lot of continuation passing style and what I
%call "next function passing style" (as expanders in EPS) so I have a
%lot of anonymous functions, and a lot closure coming from the same
%lambda expression.

This is a situation where treating errors as _values_ (like everything else
in scheme) would be terribly useful.  As errors cascaded as the result of
feeding unanticipated error values into functions, a complete backtrace would
be generated.

I like this idea because it is consistant with the rest of scheme.  Rather than
inventing a whole new set of functions to handle special flow of control on
exceptions and giving ourselves some big headache by insisting on non-local
control constructs, I like schemes lexical style.  I'd never go back to old
dynamically scoped lisp.

And it can be implemented just as easily with anonymous functions...  The key
is to imbed the error message in the error value, along with other 'irritants'
(including error values that might have caused this...), ergo:

    (if (car '()) 1 0)
--> #{ERROR: |if condition must be defined.  it was:|
    #{ERROR: |car can't be taken from| #!null}}

Just provide (error->list), (list->error), (error?), and the utility 'error'
such that: (define error (lambda l (list->error l)))

	-- Scot
+------------------------+-----------------------------------------------+
|Scot Dyer_Rivenburgh    | "Land of song," said the warrior bard,	 |
|dyer@eagle.sharebase.com| "Though all the world betrays thee,		 |
+------------------------+  One sword, at least, thy rights shall guard, |
|(He's right, you know.) |  One faithful harp shall praise thee."	 |
+------------------------+-----------------------------------------------+

P.S.  Perhaps calling errors 'undefined' values would be less threatening to
students and no more irritating to seasoned schemers than the errors
themselves?
From: todd@palomar.tivoli.com
Newsgroups: comp.lang.scheme
Subject: Scheme or TCL?
Date: 3 Sep 92 08:10:11 GMT
Distribution: comp
Organization: TIVOLI Systems, Inc.


I'd like some help from those more experienced with Scheme than I am.
I need a interpretable language that can be used for a portion of our
application development.  Currently, there are a number of people in
my company playing with TCL and TK.  I am more interested in using
Scheme, perhaps the Siod or Elk implementations.  Unfortunately, some
here are prejudiced against anything that looks like Lisp.  (It
probably comes from working in poor Lisp environments in school.)  Are
there any concrete points that can be raised in favor of Scheme over
TCL (or vice versa)?


--

Todd
-- 
Todd Smith                                     TIVOLI Systems, Inc.
todd@tivoli.com                                6034 West Courtyard Dr.
                                               Suite 210
(512) 794-9070 [794-0623 fax]                  Austin, TX   78730
From: avogel@eagle.wesleyan.edu
Newsgroups: comp.lang.scheme
Subject: Help:Scheme for the AMIGA???
Date: 10 Sep 92 18:59:04 GMT
Organization: Wesleyan University

Hey-
	Does anyone know of a Scheme program for the AMIGA platform?  Also
where/how it could be obtained?  Thanks.
				--AV
AVOGEL@EAGLE.WESLEYAN.EDU
From: bartlett@bartlett.pa.dec.com (Joel Bartlett)
Subject: Re: Help:Scheme for the AMIGA???
Reply-To: bartlett@decwrl.dec.com
Organization: DEC Western Research Lab
Date: Thu, 10 Sep 92 21:16:20 GMT

Scheme->C runs on the Amiga.  It's available for anonymous ftp from
'gatekeeper.dec.com' [16.1.0.2]. The Scheme->C files are in
'/pub/DEC/Scheme-to-C'.  See the README file contained in that directory for
more information.

jfb
From: yost@adobe.com (David Yost)
Newsgroups: comp.lang.scheme
Subject: Thomas, as in Dylan Thomas
Date: 14 Sep 92 23:06:26 GMT
Organization: Adobe Systems Incorporated

In article <9209120208.AA00645@peanut.crl.dec.com> JMiller@crl.dec.com writes:
>
>Subject: "Thomas" system now available
>
>Thomas compiles a language compatible with the language described in the book
>"Dylan(TM) an object-oriented dynamic language" by Apple Computer
>Eastern Research and Technology, April 1992.

I thought it would take usenet readers a while to get around to
reading your posting unless someone points out in the subject line
what it's really about.  Thus, this message.

 --dave
Newsgroups: comp.lang.scheme
From: schwartz@roke.cs.psu.edu (Scott Schwartz)
Subject: Re: Scheme or TCL?
Date: Mon, 7 Sep 1992 23:17:29 GMT

jeff@aiai.edinburgh.ac.UK (Jeff Dalton) writes:
   What is TCL/TK?

TCL is an embedded command language developed by John Ousterhout.  TK
is an X toolkit with Motif-like look and feel built using TCL.  You
can ftp it from sprite.berkeley.edu, and read about it in comp.lang.tcl.
Newsgroups: comp.lang.scheme
From: mspal@fuw.edu.pl (Michal Spalinski)
Subject: string->number in PC-Scheme
Organization: Warsaw University Physics Dept.
Distribution: comp.lang.scheme
Date: Fri, 11 Sep 1992 17:23:55 GMT


R4RS describes a function of one argument called string->number. In PC
Scheme this function exists, but when called with a single argument it
complains that it expected three. I would appreciate email from anyone who
knows what the other arguments are and how they should be specified.

Thanks,
MS.
From: schwartz@roke.cs.psu.edu (Scott Schwartz)
Subject: Re: Scheme or TCL?
Distribution: comp
Date: Sat, 5 Sep 1992 23:11:05 GMT

todd@palomar.tivoli.com writes: 
   Are there any concrete points that can be raised in favor of Scheme
   over TCL (or vice versa)?

I've been using tcl/tk for a while.  One thing that I miss in tcl
that scheme has is real-live first class functions.  A common
idiom in tk is to say something like
  .button -label "foo" -command "some_tcl_string_to_eval"
Sometimes you'd prefer to hand a closure to -command instead.

A second issue is that tcl's "lists" are really strings, and their
semantics don't match those of real lisp style lists.  This can be
confusing, and has caused a few bugs (both performance bugs and logic
bugs) in our code.

Of course, when you tell this to your colleagues they will probably
point out that even a scheme fan like me is using tcl/tk.  :-)