From: freeman@cis.stanford.edu (Martin Freeman)
Newsgroups: news.announce.conferences
Subject: HOT CHIPS SYMPOSIUM IV
Date: 29 Jul 92 00:01:23 GMT
Expires: Tue, 11 Aug 1992 07:00:00 GMT
Organization: Center for Integrated Systems, Stanford University, California


                         HOT CHIPS SYMPOSIUM IV
                  A Symposium on High-Performance Chips
                           (Advance Program)

                 Sponsored by the IEEE Computer Society
                 Technical Committee on Microprocessors

               Stanford University, Palo, Alto, California
                          Memorial Auditorium
                           August 9-11, 1992

Attend HOT Chips IV, a symposium on high-performance chips, which will bring
together researchers and developers of chips used to construct high-performance
workstations and systems. Enjoy the informal format offering interaction with
speakers. The first three HOT Chips Symposiums were huge successes and prompted
articles in four special issues of IEEE Micro magazine. This year's HOT Chips
IV will again bring you the latest developments in chip technology.

ORGANIZING COMMITTEE

General Chairman:            Glen Langdon,    UC Santa Cruz
Program Co-Chairmen:         David Patterson, UC Berkeley
                             John Mashey,     MIPS Computer
Finance Chairman:            Martin Freeman,  Philips Research
Registration Chairman:       Robert Stewart,  Stewart Research
Publication Chairman:        Nam Ling,        Santa Clara University
Publicity Chairman:          Andrew Goforth,  NASA Ames Research Center
Publicity Committee:         Elaine Grimes,   Elaine Grimes Graphics
			     Doug Marquart,   Santa Clara University
Local Arrangements Chairman: Robert Stewart,  Stewart Research
At Large:                    Hasan AlKhatib,  Santa Clara University
                             John Hennessy,   Stanford University
                             Alan Smith,      UC Berkeley


PROGRAM COMMITTEE

David Ditzel,    Sun Microsystems
Ruby Lee,        Hewlett Packard
John Mashey,     MIPS Computer (Program Co-Chair)
Teresa Meng,     Stanford University
David Patterson, UC Berkeley (Program Co-Chair)
Uri Weiser,      Intel


PROGRAM

August 10, 1992 - Memorial Auditorium

7:45-8:45     Onsite Registration

8:45-9:00     Welcome and Opening Remarks
              Glen Langdon, General Chair
              David Patterson and John Mashey, Program Co-Chairs

9:00-10:15    Session 1: High Performance Processors I
              Session Chair: David Patterson, UC Berkeley

              . DEC Alpha Architecture and 21064 Chip
	        E. McLellan, Digital Equipment Corporation

              . A 200 MFLOP HP PA-RISC Processor
                W. Jaffe, B. Miller and J. Yetter, Hewlett-Packard

10:15-10:45   BREAK

10:45-12:15   Session 2: Multiprocessor Interface Issues
              Session Chair: Ruby Lee, Hewlett-Packard

              . Multiprocessor Features in a PA-RISC Processor Interface Chip
	        T. Alexander, K. Chan, C. Hu, N. Noordeen and S. Ziai
                Hewlett-Packard

              . On-Chip Cache Hierarchy for 1000-MIPS Multi-Superscalar
                Processors
	        T. Nishimukai, M. Hanawa, O. Nishii, M. Suzuki, K. Yano and
                M. Hirak, Hitachi

              . Sparcle: Today's Micro for Tomorrow's Multiprocessor
	        A. Agarwal, J. Babb, D. Chaiken, G. D'Souza, LSI Logic
                K. Johnson, D. Kranz, J. Kubiatowicz, B.-H. Lim, G. Maa,
                K. Mackenzie, D. Nussbaum, M. Parkin, Sun Microsystems
                D. Yeung, MIT

12:15-1:45    LUNCH AT THE TENT

1:45-3:15     Session 3: Low Cost Processors
              Session Chair: John Mashey, MIPS Computers

              . Highly Integrated SPARC Processor Implementation
	        S. Joshi, Sun Microsystems

              . The LR33020 GraphX processor:  A single chip MIPS-RISC Based
                X Terminal Controller
	        S. Desai, LSI Logic Corporation

              . The ARM600 Processor and FPA
	        P. Harrod, D. Seal, A. Baum and A. Thomas
                Advanced RISC Machines Ltd.

3:15-3:45     BREAK

3:45-5:15     Session 4: Low Power Systems
              Session Chair: Dave Ditzel, Sun Microsystems

              . A VLSI Chip Set for Personal Communications System
	        R. Scavuzzo, AT&T Bell Labs

              . SPARC90 - Chipset on a Chip
	        J. Pendleton, Sun Microsystems

              . Cold Chip Design Techniques
	        R. Brodersen, A. Chandrakasan and S. Sheng, UC Berkeley

5:15-7:00     RECEPTION DINNER AT THE TENT

7:15-9:30     EVENING PANEL SESSION
              DRAM Choices for the 90s: 1 Gigabyte/Second or Bust
              Chair: Forest Baskett, Silicon Graphics


August 11, 1992 --- Memorial Auditorium

7:30          Coffee and Donuts

8:00-9:00     Onsite Registration

9:00-10:30    Session 5: Interfaces and Interrupts
              Session Chair: John Mashey, MIPS Computers

              . The SBus Goldchip
	        M. Sodos, Sun Microsystems

              . Peripheral Component Interconnect
	        D. Carson, Intel Corporation

              . Advanced Programmable Interrupt Controller (APIC)
                for MP and 32-bit Operating Systems
	        P.K. Nizar, Intel Corporation

10:30-11:00   BREAK

11:00-12:30   Session 6: Vector and Video
              Session Chair: Dave Patterson, UC Berkeley

              . The Vector Coprocessor Unit (VU) for the CM-5
	        J. Wade, Thinking Machines Corporation

              . A 289 MFLOPS Single Chip Supercomputer
	        C. Lund for H. Lino, H. Takahashi, T. Sukemura, M. Kimura,
                K. Fujita and S. Mori, Fujitsu

              . A Programmable Solution for Standard Video Compression
	        J. Fandrianto and T. Williams
                Integrated Information Technology, Inc.

12:30-2:00    LUNCH

2:00-3:30     Session 7: Electrons, Photons, and Neurons
              Session Chair: Teresa Meng, Stanford University

              . Chip Pair Creates Self-timed Network Fabric for Paragon
                Parallel Supercomputers
	        R. Traylor and D. Dunning, Intel Supercomputer Systems

              . GaAs VLSI Enhancement through Utilization of Global Optical
                Free Space 'Smart' Interconnects
	        P. Guilfoyle and F. Zeise, OptiComp Corporation

              . Silicon Based Nerve Interfaces
	        G. Kovacs, Stanford University

3:30-4:00     BREAK

4:00-5:30     Session 8: High Performance Processors II
              Session Chair: Uri Weiser, Intel

              . The Second Generation SPARCore Mbus Chip
	        R. Vegesna, Ross Technology

              . Superscalar Architecture of the P5 - X86 Next Generation
                Microprocessor
	        D. Alpert, Intel Corporation

              . The P5 Floating-Point Unit
	        D. Avnon, Intel Corporation

5:30	      Closing Remarks


SUNDAY, AUGUST 9 --- TUTORIAL: A QUANTITATIVE APPROACH TO MICROPROCESSOR
                               ARCHITECTURE
                     LECTURER: Professor Mark Hill

This four hour tutorial will review the principles of computer
architecture, emphasizing microprocessor considerations. The
presentation will be strongly based on COMPUTER ARCHITECTURE: A
QUANTITATIVE APPROACH by John Hennessy and David Patterson, and will
concentrate on caches and pipelining.  Some more recent material willbe
presented. Mark Hill is an Assistant Professor at the University
ofWisconsin, Madison, and a 1989 recipient of NSF's Presidential Young
Investigator Award. The Sunday tutorial is a new event at HOT Chips.
There will be a $10 fee for attendance.


SUNDAY, AUGUST 9 --- SCHEDULE OF EVENTS

10:00-11:00   Registration at Memorial Auditorium
10:30-11:00   Pastries and Coffee
11:00- 1:00   First Half of Tutorial: Memorial Auditorium
 1:00- 1:30   Break for Light Refreshments
 1:30- 3:30   Second Half of Tutorial: Memorial Auditorium
 3:30- 5:00   Guided Tour of Hoover Tower
 4:30- 7:30   Wine and Cheese Reception in the Dohrman
              Grove near the Hoover Tower


HOUSING INFORMATION

Housing is available on the Stanford University campus in Crothers Hall, a
short walk from Memorial Auditorium where the symposium will be held. Housing
is in student residences with central lavatory facilities and costs $40 per
night. A key deposit is required that will be refunded at checkout. Housing
arrangements on the Stanford campus must be made by July 15.

Housing is also available at numerous hotels and motels on the peninsula in
Palo Alto, Menlo Park, Mountain View, and Los Altos close to Stanford
University.

If you would like additional housing information, please check the housing
information request box on the registration form.

PARKING INFORMATION

You may park in the following Stanford University C parking lots:

      Serra Complex Parking Lot
      Galvez Athletics Lot
      Z Commuter Lot

There will be signs on campus for you to follow. These parking lots
are within range of Memorial Auditorium. Memorial Auditorium is just
across the way from Hoover Tower.

For people without permits, there will be volunteers to help you.


QUESTIONS?

For more information on registration and local arrangements contact Dr. Robert
Stewart at (415) 941-6699 or r.stewart@compmail.com.


REGISTRATION FEES
                                    Postmarked by           Subsequent
                                       July 15              Registration

IEEE Computer Society                   $170                    $240
or ACM Member

Non-Member                              $240                    $290

Full-Time Student                       $60                     $100



Instead of payment by check, registration may be charged to VISA or MasterCard.
Registration charged to a credit card may be FAXed to Dr. Robert Stewart at
(415) 941-5048.

REGISTRATION INCLUDES

* Attendance                        * Sunday afternoon wine & cheese reception
* One copy of the notes             * Monday evening reception
* Two luncheons                     * Coffee breaks
* Parking at Stanford C Parking Lots

The Sunday tutorial is not included in the registration fee. There will be
a $10 charge for the tutorial.

On-site registration is available Sunday morning before the tutorial, at the
wine and cheese reception, and each morning at the symposium.

WINE & CHEESE RECEPTION

* Sunday, August 9 --- 4:30-7:30 PM
* Dohrmann Grove near the Hoover Tower


=============================================================================


                      HOT CHIPS IV REGISTRATION FORM


Name________________________________________________________________________

Affiliation_________________________________________________________________

Address_____________________________________________________________________

City/State/Zip______________________________________________________________

Country_____________________________________________________________________

Area Code/Phone #___________________________________________________________

Email Address_______________________________________________________________

Membership:       IEEE______          ACM_______

Membership Number___________________________________________________________

Check One:

______Check drawn on a U.S. Bank                    ______MasterCard
      Make Check Payable To:
      Hot Chips Symposium                           ______VISA

Name on Credit Card_________________________________________________________

Credit Card #_______________________________________________________________

Expiration Date_____________________________________________________________

Signature___________________________________________________________________

         Registration Fee___________________________________________________

         $10 for Tutorial___________________________________________________

         Total Amount Enclosed______________________________________________

Mail To:

			Dr. Robert G. Stewart
			Stewart Research Enterprises
			1658 Belvoir Drive
			Los Altos, CA  94024


______Housing Information Requested