HDTenEightyP/NetNews huggingface dataset:
From: ccetky@nuscc.nus.sg (Tung Kwong Yeong)
Subject: Learning PV-WAVE
Organization: National University of Singapore
X-Newsreader: Tin 1.1 PL4
Date: Sat, 9 Jan 1993 04:31:09 GMT

I am trying to learn PV-WAVE.  Are there any books other than the
manuals provided by Precision Visuals/looking at the demo files? 
I am new in visualisation stuff and I am wondering how I can create
PV-WAVE applications using some of the data in the FTP sites, eg
weather images in ats.orst.edu.  Any help would be much appreciated. 

Regards,

Tung, Kwong Yeong
Analyst Programmer
National University of Singapore
Computer Centre
Internet: ccetky@nuscc.nus.sg 
Newsgroups: comp.lang.idl-pvwave
From: dit@vaxser.grumed.fu-berlin.de (K.-H. Dittberner)
Subject: Re: IDL for Mac doesn't exist?
Reply-To: dit@vaxser.grumed.fu-berlin.de
Organization: Free University of Berlin, Germany.
Date: Tue, 5 Jan 1993 23:11:51 GMT

In article <3825@tansei1.tansei.cc.u-tokyo.ac.jp>, you write:
>
>Is there a port of IDL or PVWAVE which runs on a Macintosh computer (Mac/OS or A/UX)??
>I have heard of a version for IBM-PC.  Why not one for Mac?
>
>     Kyo Akita (  kakita@solar.stanford.edu )

No. it's a pitty, there isn't one. 
But, it would be nice to have an
implementation auf IDL on the mac platforms.
I would buy such a package for my MAC Quadra-700.

Hi RSI, what's about porting IDL to the MAC's and NeXT's ?

_______________________________________________________________
Dipl.-Ing. Karl-Heinz Dittberner  |  Address: Arnimallee 22
Dept. Scientific Data Processing  |           D-1000  Berlin 33
c/o   Free University of  Berlin  |  Phone:   (+4930) 838 2531
E-Mail:    dit@vaxser.grumed.fu-berlin.de     (Internet)
From: zawodny@arbd0.larc.nasa.gov (Dr. Joseph M Zawodny)
Newsgroups: comp.lang.idl-pvwave
Subject: Re: News Release
Date: 6 Jan 1993 12:39:38 GMT
Organization: NASA Langley Research Center, Hampton, VA
NNTP-Posting-Host: arbd0.larc.nasa.gov

  Boy, if you believe the "News Release" (read commercial), you would think
that PV-Wave was developed by PVI.

  I too wonder where this leaves RSI and IMSL/IDL.  I'm also curious to hear
of the behind the scenes offers and counter offers undoubtedly made to RSI by
the IMSL folks ;-).

  I know that IDL for the Mac will also be well received here.  Hang in there.

 Joseph M. Zawodny   (KO4LW)                      NASA Langley Research Center
 zawodny@arbd0.larc.nasa.gov                      MS-475,    Hampton VA, 23681
From: apwang@waikato.ac.nz
Newsgroups: comp.lang.idl-pvwave
Subject: IDL contour
Date: 12 Jan 93 15:13:45 +1300
Organization: University of Waikato, Hamilton, New Zealand

Hi,
Does anyone know how to draw a contour graph in polar
coordinate system without changing to cartician coordinate 
by using IDL? Any help will be appreciated very much!

Thanx!

Anping Wang
Email apwang@waikato.ac.nz

Newsgroups: comp.lang.idl-pvwave
From: wagener@gown.das.bnl.gov (Richard Wagener)
Subject: HDF/CDF support from PV-Wave when?
Organization: Brookhaven National Laboratory
Date: Tue, 12 Jan 1993 21:38:24 GMT


I heard that the new version of IDL (3.0) includes support for HDF and
CDF. 

Can we expect PV-Wave to follow suit any time soon?
-- 
[nosave]
Tschuess ...rick...
_______________________________________________________________________________
Richard Wagener				|
From: bowman@csrp.tamu.edu (Kenneth P. Bowman)
Newsgroups: comp.lang.idl-pvwave
Subject: Re: IDL for Mac doesn't exist?
Followup-To: comp.lang.idl-pvwave
Date: 5 Jan 1993 15:22:06 GMT
Organization: Texas A&M University
Distribution: world
NNTP-Posting-Host: bowman.tamu.edu

In article <3825@tansei1.tansei.cc.u-tokyo.ac.jp>,
f61090@tansei.cc.u-tokyo.ac.jp (F61090) wrote:
> 
> 
> Is there a port of IDL or PVWAVE which runs on a Macintosh computer (Mac/OS or A/UX)??
> I have heard of a version for IBM-PC.  Why not one for Mac?
> 
>      Kyo Akita (  kakita@solar.stanford.edu )

I'm sure that the reason is simple - the market for a Mac version is seen
to be smaller than the market for the PC version.  I think RSI is missing
an important market, however.  Many scientists have Macs, and there is
nothing comparable available on the Mac.  Mathematica will do everthing IDL
will, and more - in principle.  In practice I find it not to be well suited
for handling large data sets, but I use it for some other kinds of tasks. 
The closest thing on the Mac is probably Matlab.

As a Mac user I would love to see a Mac version.  Now that Apple is moving
to the IBM Power PC chips (and AIX for there version of Unix), we may see a
Mac version in the future.  I hope so.

---------------------------------------------------------------------------
Dr. Kenneth P. Bowman                          409-862-4060
Climate System Research Program                409-862-4132 fax
Department of Meteorology                      bowman@csrp.tamu.edu
Texas A&M University
College Station, TX   77843-3150
From: peba1231@camillo.fb12.tu-berlin.de (Peter Bartsch)
Newsgroups: comp.lang.idl-pvwave
Subject: Re: IDL contour
Date: 12 Jan 1993 17:54:43 GMT
Organization: TU Berlin, Inst. f. Luft- und Raumfahrt, FRG
Distribution: world
Reply-To: peba1231@camillo.fb12.tu-berlin.de
NNTP-Posting-Host: camillo.fb12.tu-berlin.de

In article <1993Jan12.165204.29186@nsisrv.gsfc.nasa.gov>, 
pat@gsfc.nasa.gov (patrick m. ryan) writes:

|> 	the problem i still have is that polycontour bites.
|> if anyone has a color contouring routine which knows how
|> to handle unclosed contours, please post it.  if i'm
|> feeling inspired one of these days, i translate the NCAR
|> CONPACK routines into IDL.  they're ugly but they do
|> the job.
|> 
|> pat
|> 

Could you please send me your routine as soon as you wrote it :-)

Peter

-- 
----------------------------------------------------------------------
Peter Bartsch        |   Tel.    +49 (0)30 314 23093
TU Berlin, Sekr. F2  |   FAX:    +49 (0)30 314 22866
Marchstr. 14         |
1000 Berlin 10       |   e-mail: peba1231@camillo.fb12.tu-berlin.de
----------------------------------------------------------------------
From: eldip@lut.ac.uk (DI Patel)
Newsgroups: comp.lang.vhdl
Subject: Books, VHDL for PC's ...
Date: 11 Jan 93 14:42:56 GMT
Organization: Loughborough University, UK.

Dear all,

I am going to be doing some chip design using VHDL.  I have never used VHDL
before and am therefore looking to get hold of some good books on it.  Our
library doesn't have any books (!!!!) and i am in the process of recommending
some books for them to purchase.

Could anyone please let me know which books are good and worth getting? As a 
matter of interest, i am thinking of getting " A VHDL Primer" published by
Prentice Hall.

Also could anyone tell me if it is possible to purchase a copy of VHDL which
will run on a PC? We are going to get VHDL running on our network of SPARC's
but it won't be until next month (or even later).....

Any help would be much appreciated.

Please reply either thru the net or via email to eldip@lut.ac.uk.

Thanxs in advance.

Cheers.

Dipesh.
From: adamr@protocol.zycad.com (Adam Rosenberg - 8/10/92)
Newsgroups: comp.lang.vhdl
Subject: WAVES
Date: 12 Jan 1993 09:56:57 -0500
Organization: Protocol A Division of Zycad Corp
Distribution: world
NNTP-Posting-Host: badboy.protocol.zycad.com
Keywords: WAVES Packages and Programs


This is my second attempt to see if anyone out there has the latest copy of the
WAVES packages.  I am also trying to locate companies who have or are in the
process of developing software to ease the implementation of WAVES requirements. 
If you have any opinions on WAVES give me a scream.

		Thanks,
		adamr@protcol.zycad.com

Newsgroups: comp.lang.vhdl
From: hojjat@bmers246.uucp (Hojjat Salemi)
Subject: Verilog To VHDL translator
Organization: Bell-Northern Research, Ottawa, Canada
Date: Tue, 12 Jan 93 20:21:43 GMT

Can someone please send me a list of company names which provide
Verilog to VHDL translators? 

Thanks for your time ...
 
Hojjat Salemi
Senior Hardware Designer
*----------------------------------------------------------------*
| Mail Stop 040 - Dept. 1D12        E-mail:      hojjat@bnr.ca   |
| Bell-Northern Research Ltd.                                    |
| P.O. Box 3511 Station C,          Phone:        613-763-3489   |
| Ottawa, Ontario, CANADA K1Y 4H7   FAX:          613-765-4953   |
*----------------------------------------------------------------*
Newsgroups: comp.lang.vhdl
From: fred@sobel.u-strasbg.fr (Frederic PIERRE)
Subject: VHDL for PC's
Date: Tue, 12 Jan 1993 14:51:59 +0000

	You can buy a pretty decent VHDL compiler and environment for PC's
at Model Technologies. They have a Ms-Windows based system which is quite
a perfect copy of the Un*x version.
	The phone number of Model Tech I have is:
	(503) 690-6838
    FAX:(503) 690-2093
	(I'm not affiliated with Model Tech.!)
	
	Hope this helps.
	Fred.
 ===========================================================================
 Frederic PIERRE. ENSPS/LSIT 7 rue de l'universite F-67000 Strasbourg FRANCE 
 Tel: (33) 88 35 80 84 Fax: (33) 88 35 31 76 e-mail: fred@sobel.u-strasbg.fr
 ==========================HamRadio: FC1HFD=================================
 
Newsgroups: comp.lang.vhdl
From: r80163@cc.ee.ntu.edu.tw ()
Subject: VHDL description of MCM wanted
Organization: NTUTaiwan
Date: Thu, 7 Jan 1993 02:49:38 GMT

Hello:
  Can someone send me VHDL code of MCM (multichip module) or
tell me where to get them? I am doing a project about diagnosis
of MCM using VHDL. I need some benchmarks to test. Thanks!
					r80163@cad.ee.ntu.edu.tw
Newsgroups: comp.lang.vhdl
From: kevin@clsi.COM (Kevin Cameron)
Subject: Re: data types, vhdl
Originator: kevin@dubhe
Reply-To: kevin@clsi.com
Organization: CAD Language Systems Inc.
Date: Mon, 4 Jan 93 20:18:03 GMT


In article <C08p03.Htv@ucunix.san.uc.edu> you write:
> Hi folks,
> 
> Is there any options in the vhdl language that lets me declare types
> equivalent to the "union" in C. The brute force method that I can think of
> is to declare a record with all the possible choices in the original union
> as a strictly present field; and have integer tags to access the types: 
> 
> 	e.g.	-- pseudo vhdl code;
> 
> 	type union is record
> 		-- the tag to determine what field to use;
> 		access_type : integer;
> 		-- this is where the union starts
> 		-- list is declared earlier as an access type to a list;
> 		u1 : real;
> 		u2 : integer;
> 		u3 : list
> 		end record;
> 
> Is there any alternative to this lengthy  way of designing a data structure.
> 
> 
> thanks for any replies and comments.

Use one field of a type large enough to store each member of the union, and use
type conversion functions depending on the tag value. This is ineffecient in speed
but more efficient in storage (particularly for signals) - some type conversions
will be difficult too.

Kev.
-- 
Kevin Cameron          CLSI, Suite 100, 5457 Twin Knolls Rd., MD 21045, USA
kevin@clsi.com         Tel: (USA) (410) 992 5700 (- 5709) x224
uunet!clsi.com!kevin   Fax:       (410) 992 3536
-----------------------------------------------------------------------------
From: adamr@protocol.zycad.com (Adam Rosenberg - 8/10/92)
Newsgroups: comp.lang.vhdl
Subject: WAVES packages/tools
Date: 8 Jan 1993 11:39:04 -0500
Organization: Protocol A Division of Zycad Corp
Distribution: world
NNTP-Posting-Host: badboy.protocol.zycad.com
Keywords: WAVES


I am in search of the latest and greatest WAVES package.  I also am trying to
find out if anyone has developed or is in the process of developing a commercial
WAVES toolset.  Please reply via news or email adamr@protocol.zycad.com

Newsgroups: comp.lang.vhdl
From: Winson@cad.ee.ntu.edu.tw (Chu W.H.)
Subject: Want free VHDL source samples
Organization: EE, NTU
Date: Mon, 11 Jan 1993 06:42:58 GMT

Hi .
    I am a CAD student studying VHDL right now. Can anybody tell me where I 
could get VHDL source ( maybe by FTP ). THANKS..


Chu W.H.
EE National Taiwan University,Taiwan
email address:r81132@cs.ee.ntu.edu.tw
From: wff@icf.hrb.com (W. Figurelle)
Newsgroups: comp.lang.vhdl
Subject: Questions on I/O
Date: 8 Jan 93 14:31:50 GMT
Organization: HRB Systems, Inc.

I'm currently writing a test bench for a model and I have a couple
of questions.

1) Does VHDL have any hooks provided to take in user input during
   run time? (Ex. prompting for information)

2) If (1) is possible, is there a way to prompt the user for a
   filename, and then use this in a file object declaration?
   (Ex. FILE myfile:text IS IN input_variable_name)
   I've only seen hardcoded or generic map implementations of this.

The reason for these questions is that I want to write only one test
bench, and then use this test bench for multiple input stimulus files.
I know there are ways around this, but I want something efficient.

Thanks in advance
From: bawa@java.ibp.fr (Rajesh BAWA)
Newsgroups: comp.lang.vhdl
Subject: VHDL/PETRI
Date: 5 Jan 93 16:34:23 GMT
Organization: Laboratoire MASI, Paris, France

Hi,

I need some pointers to references on compiling  
ada and VHDL onto Petri-Nets and related works on tasking analyis.

Thank you for your help.

Greetings

Happy new year


-- 
......................................
Rajesh BAWA                        
CAO_VLSI/MASI UPMC PARIS VI            
e-mail: bawa@masi.ibp.fr
Newsgroups: comp.lang.vhdl
From: jmessenger@cix.compulink.co.uk (John Messenger)
Subject: Re: What types should one use?
Reply-To: jmessenger@cix.compulink.co.uk
Date: Tue, 5 Jan 1993 01:14:00 +0000


I think it that you should use the most abstract types which your
synthesiser can handle.  The synthesiser I use can work out the
'used' range of an INTEGER and allocate the appropriate number of
bits.  For boolean logic, I would use an MVL type and compare it to
'1' or '0' in the 'if' statement.  I would avoid the use of BOOLEAN
for things which will be synthesised.

If you are going to write structural or low-level VHDL yourself, and
look for timing glitches, then you need to use an MVL system for
almost everything.  I'm sure that VHDL is best used by writing code
at a high level or abstraction, not thinking how every gate will look
in the chip - otherwise its just a netlist in a posh accent!
        -- John Messenger, Clifton Advanced Technology,
        -- jmessenger@cix.compulink.co.uk
--
    John Messenger (jmessenger@cix.compulink.co.uk) Tel: +44 904 692700
Newsgroups: comp.lang.vhdl
From: daniel@clsi.COM (Daniel S. Barclay)
Subject: Re: data types, vhdl
Organization: CAD Language Systems Inc.
Distribution: usa
Date: 4 Jan 93 13:13:41

> Is there any options in the vhdl language that lets me declare types
> equivalent to the "union" in C. The brute force method that I can think of
> is to declare a record with all the possible choices in the original union
> as a strictly present field; and have integer tags to access the types: 
> ...

No.  There are no variant record types in VHDL.  Sorry.  

Your workaround is the best solution I know of if you need to declare signals
or constants of that type.  If you're working with variables only (e.g., in
one process), you can declare a record containing pointers to different types,
and then allocate data for only the type that's used.

--
------------------------------------------------------------------------------
Daniel S. Barclay                    --who's still searching for a good 
CAD Language Systems, Inc.           signature, not liking any of his recent
Suite 101, 5457 Twin Knolls Rd.      feeble attempts to improve on the whiny:
Columbia, MD  21045  USA             Why can't _I_ think of a good signature?

Newsgroups: comp.lang.vhdl
From: jab3@cec2.wustl.edu (John Alonzo Breen)
Subject: Deliverable VHDL - Defense contract requirements
Organization: Washington University, St. Louis MO
Distribution: usa
Date: Mon, 11 Jan 1993 19:21:42 GMT

Does anyone know the "latest & greatest" wrt VHDL deilverable models
under (U.S.) defense contracts, say, as part of a level 2 drawing
package?  Are there any standard practice documents, etc?  I have an
old copy (actually, a draft) of the DID dated March '88, and
Requirement 64 of MIL-STD-454L (Sep '87).  If there's anything more
current, I would appreciate it if someone could point me in the right
direction.

Thanks.
-- 
John A. Breen                   |
jab3@cec1.wustl.edu             | This space unintentionally left blank
Newsgroups: comp.lang.vhdl
From: jmessenger@cix.compulink.co.uk (John Messenger)
Subject: No subject 
Reply-To: jmessenger@cix.compulink.co.uk
Date: Fri, 8 Jan 1993 15:52:00 +0000

Text of VHDL-1992
Can anyone tell me where to obtain the text of VHDL-1992?  Is it
published yet?  In particular, can it be obtained (even in draft) by
FTP?  Thanks in advance,
--
    John Messenger (jmessenger@cix.compulink.co.uk) Tel: +44 904 692700
Newsgroups: comp.lang.vhdl
From: beihl@ncrcol.ColumbiaSC.NCR.COM (Gary Beihl)
Subject: Overload Resolution (Was: type conversion and configuration)
Organization: NCR E&M Columbia SC.
Date: Tue, 05 Jan 93 15:12:54 GMT

In article <1993Jan4.225957.26359@viewlogic.com> sunder@viewlogic.com (Sunder Singhani) writes:
>
>The above IS ambiguous. Explanation follows -

IMHO, there is NO ambiguity.  Sufficient information is available.
 
>-- 4    FUNCTION To_X01  ( b : BIT_VECTOR        ) RETURN  std_logic_vector;
>-- 5    FUNCTION To_X01  ( b : BIT_VECTOR        ) RETURN  std_ulogic_vector;
> 
>Of these you are choosing 4, 5 explicitly by using type qualification -
>ie bit_vector'("00"). 5 returns std_logic_vector and 4 returns std_ulogic_vector.

So far, so good.  Yes, there are two candidates with the same parameter and
result profile.

>The first one when indexed gives you an element of std_ulogic, and the latter
>gives std_logic. Now, std_logic is a subtype of std_ulogic, which implies
>both have the same base type which is std_ulogic. Hence, you end up
>with two interpretations, which is erroneous. The final type qualification

Not so fast.  Just because the parameter/result profiles match doesn't mean
the declaration is ambiguous.  According to LRM 10.5 (The Context of Overload
Resolution) there is a list of rules to be considered along with syntax and
scope/visiblity rules.  The first of these is:

  "1. Any rule that requires a name or expression to have a certain type,
      or to have the same type as another name or expression."

Since this is a constant declaration with a default expression, the following
rule for interface objects (LRM 4.3.3) seems applicable:

  "...The type of a default expression must be that of the corresponding
   interface object."

This narrows the search down to a single choice.  Unless I've missed 
something, Model Technologies appears to be doing the right thing here.

Gary Beihl (gary.beihl@columbiasc.ncr.com)

Newsgroups: comp.lang.vhdl
Newsgroups: comp.lang.vhdl
Subject: What is PowerView ?
From: mohan@jupiter.cse.utoledo.edu (---Mohan Pakkurti---)
Date: 6 Jan 93 13:26:42 EST

Hello,

Can some one tell me what "Powerview" software is?

Thanks. :)
Mohan
-- 
===============================================================================
+ Mohanakrishna Pakkurti            + mohan@jupiter.cse.utoledo.edu           +
+ HOME: 2239 University Hills Blvd #204, Toledo OH 43606. Phone:(419)536-9073 +
===============================================================================
Newsgroups: comp.lang.vhdl
From: edlefsen@waters.mcrc.etdesg.trw.com (Steven J. Edlefsen)
Subject: edif to vhdl translator
Organization: TRW, Inc., Redondo Beach...
Distribution: comp
Date: 12 Jan 93 15:38:29

I'm seeking info on an edif to vhdl translator.  Any info can also be
sent via e-mail to:

       edlefsen@mamacass.etdesg.trw.com
Newsgroups: comp.lang.vhdl
From: beihl@ncrcol.ColumbiaSC.NCR.COM (Gary Beihl)
Subject: Re: Overload Resolution (Was: type conversion and configuration)
Organization: NCR E&M Columbia SC.
Date: Fri, 08 Jan 93 16:21:00 GMT

In article <DANIEL.93Jan6115749@algol.clsi.COM> daniel@clsi.COM (Daniel S. Barclay) writes:
>would it make a difference?  Aren't Sunder's comments correct:
>
>	"The first one when indexed gives you an element of std_ulogic, and 
>	the latter gives std_logic. Now, std_logic is a subtype of std_ulogic,
>	which implies both have the same base type which is std_ulogic."
>
>What seemed to "narrow the search to a single choice"?
>

Sunder and Daniel are correct.  I had somehow (temporarily) convinced 
myself that the subtype of the default expression had to match the
subtype indication of the interface object.  After re-reading the LRM
and the previous posts, I'm now in agreement that the original code is
ambiguous. 

Gary Beihl (gary.beihl@columbiasc.ncr.com)
From: gotom@hpysoln.tky.hp.com (Masaharu Goto)
Newsgroups: comp.lang.verilog
Subject: Re: Verilog <--> VHDL translators
Date: 11 Jan 93 17:50:35 GMT
Organization: YHP Hachioji IT, Tokyo Japan


 I think you didn't miss too much. 

 The new information I've got are,

	1) VDOC-454 benchmark 
	 VDOC-454 can reasonably translate behavioral Verilog 
	description to VHDL.  There were a coule of minor bugs
	translating `define and array index. Other than those
	it seems like VDOC-454 translated very well. 

	2) About InterHDL, I haven't seen any further information. 
	The message I've got was very brief and didn't explain much of the
	details.
From: jcooley@world.std.com (John Cooley)
Newsgroups: comp.lang.verilog
Subject: Re: Verilog <--> VHDL translators
Date: 5 Jan 93 05:46:12 GMT
Organization: The E-mail Synopsys Users Group (ESNUG)

In article gotom@hpysoln.tky.hp.com (Masaharu Goto) writes:

> I have a couple of corrections to my previous responce.
>
> The cost of VDOC-454 is not $200k~$300k,  but it is $20k~$30k. I mixed up
>when I convert it from yen to $.
>
> Second. A guy from InterHDL tell me that they have only Verilog to VHDL 
>convertor. I believe somebody gave me information that they have the other
>way translator, but it may be a misunderstanding.

  Having been away on vacation for the past few weeks, it looks like I
  missed an interesting threat about Verilog <--> VHDL translators.  Could
  I trouble someone who may be at a site that has this thread archived to
  e-mail me where I could ftp to pick up these missing posts?  I run the
  E-mail Synopsys User Group (ESNUG) and know a couple of hundred Verilog/
  VHDL users who might be interested in this particular thread.

  Thank you for your time & help.

                                                - John Cooley
                                                  ESNUG Moderator


 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
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Newsgroups: comp.lang.sigplan,comp.object,comp.lang.c++,comp.lang.eiffel,comp.lang.clos,comp.lang.modula3,comp.lang.objective-c,comp.lang.smalltalk,comp.lang.visual
From: kaveh@CAM.ORG (Kaveh Kardan)
Newsgroups: comp.lang.scheme
Subject: scheme interface to Motif?
Date: 9 Jan 93 13:52:05 GMT
Organization: Communications Accessibles Montreal, Quebec Canada


I am looking for a scheme interface to Motif or some other X-based ui
system, to be used with scheme->c.

Thanks,

Kaveh
--
Kaveh Kardan                                        kaveh@mtrpls.login.qc.ca
Metropolis Graphics Ltd
Montreal Quebec Canada                              phone/fax: (514)842-6172

-- 
Kaveh Kardan                                        kaveh@mtrpls.login.qc.ca
Metropolis Graphics Ltd
Montreal Quebec Canada                              phone/fax: (514)842-6172