Newsgroups: rec.audio

> Lets pretend you are
> designing an AES/EBU decoder (the receiver on the DAC side of the
> digital link). how would you design the PLL, and how much jitter
> does it have? keep in mind you have to cope with 32kHz, 44.1kHz
> and 48kHz, and you have to capture within the 4 bit preamble.
> (i'm not trying to embarress you; it would be instructive to see
> what the answer is!)
> 
> 		andrew hume
----------
This isn't my field, but let me try:

I'd get 3 crystals that are used for CD transports (i.e.  32, 44.1 and
48 kHz) and use this to clock the data into a buffer (of course).  I'd
select the crystal with a switch or use a counter (or one shot),
precision trimmed, to determine the freq.  and then drive the crystal
select switch.  This should be able to get the freq right during the
preamble.  Now I'd use the crystal to sample the data stream until the
PLL reached lock on the data stream.  I'd then switch clocking over to
the PLL.  I'd make this a long acquisition time so that it would have
very low jitter once it is running.

If I were "really smart", I'd retime the input data with a large buffer
(several seconds worth of data) and a low jitter PLL.  This would mean that
there would be low jitter on both:
-the data entering the DAT
-the DAC word decoding itself
THe buffer would prevent loosing preamble and data while the PLL was
reaching acquisition.

I'd also do all this with one power supply and have good emi supression
such as inductors on the power leads and several capacitors (300pf and 0.1uf
across the power leads of the transformer before going to the wall socket.
This should help keep digital switching transients off the power rails of the
DAC.

The actual DAC would get its own transformer, running off the same plug
but with inductors and capacitors for emi supression again.  I'd use
optical isoaltion to get the data from the "retiming" circuit onto the
actual DAC.  This would be 18 opto isolators, two for the word clock
(differential clocking for lower jitter and less power supply noise) and
16 for the data bits.  I might run the optocouplers for the 2 clock
signals in analog mode for near zero pulse distortion and then use
latches to get the data levels suitable for the DAC.

Oh well, am I close?  My main design goals were:
-Low power supply noise on the DAC for good fidelity
-Low jitter on the word decode clock
-Reducing the jitter on the overall data stream for lower overall jitter

If possible (budget) I'd consider doing the whole thing differential since
this puts less noise on the supplies.  i.e. I'd take the input data and
turn it into differential data with my "really smart" retiming circuit.

If you use this design, I want royalties!

Copyright 1993  Kirk W. Lindstrom
all righs reserved, except transmission by USENET and other non-for-pay
services.  Keep this msg with all copies.

=> "We are what we pretend to be."  -  Kurt Vonnegut Jr.
+---------------------------------------------------------------------+
| Kirk Lindstrom - OCD Product R & D | Hewlett-Packard Co.  M/S: 91UA |
|   Engineer/Scientist, Hardware     |                                |
|------------------------------------| Optical Communication Division |
|     kirk_lindstrom@sj.hp.com       |                                |
|    Kirk Lindstrom / HP0100/UX      | 370 W. Trimble Rd.             |
| ph 408 435 6404 | fax 408 435 6286 | San Jose, CA  95131-1096       |
+---------------------------------------------------------------------+