From: ah@ztivax.zfe.siemens.de (Andreas Hohl)
Newsgroups: news.announce.conferences
Subject: VHDL-Forum, Spring '92 Meeting, Santander, Spain
Date: 13 Apr 92 18:00:35 GMT
Expires: Wed, 29 Apr 1992 07:00:00 GMT
Organization: Siemens AG in Munich, W-Germany


VHDL-Forum for CAD in Europe
SPRING '92 MEETING
April, 26 - 29, 1992, Santander, Spain

VHDL-Forum for CAD in Europe:
The VHDL-Forum for CAD in Europe is the European VHDL Users' Group
active in VHDL related Topics & Standardization Efforts and was
founded at the IFIP VLSI'89 in Munich. The members belong to an
international range of companies, institutes and universities, VHDL
users as well as VHDL vendors. The motivation and history of the
group was the European diverse experience in the field of HDLs &
related topics (description, simulation, synthesis, formal proof &
verification,...). The VHDL-Forum is related to the VHDL International
Users' Forum (US), VHDL Users' Groups in Japan and Russia, and to the
different VHDL standardization groups (DASS, European WG on VHDL
Standardization). The previous meetings Fall'89 (Munich, Germany),
Spring'90 (Grassau/Munich, Germany), Fall'90 (EUROVHDL, Marseille,
France), Spring '91 in conjunction with the IFIP CHDL '91 (Tenth
International Symposium on Computer Hardware Description Languages
and their Applications) (Marseille, France) and Fall '91  (EUROVHDL,
Stockholm, Sweden)  have shown great interest in the activities of
this group.

1992 is the year of VHDL. After 5 years, VHDL is reballoted as an IEEE
Standard. The language will be extended to cover additional fields of
application. The standard lives! This is important for the VHDL community.
The extension will be upward compatible! This is important for the
industrial application of VHDL and the number of companies using VHDL
increases steadily. In the research area VHDL is accepted as well. This
is important to put theory into practise.

These international activities reflect the importance of VHDL as a Standard
Hardware Description Language.  To show where VHDL stands now and what is
the future trend, the motto of the meeting is "Questions and Answers to the
Use of VHDL in Hardware Design". Beside the presentation sessions where very
interesting papers on various topics are shown, the panel sessions promise
hot discussions and there is plenty of time to discuss various topics within

the working groups session. In the tutorials, the attendees have the chance
to catch up additional information on the use of VHDL and the "new VHDL '92".
Vendor presentations are scheduled to report about VHDL tools. After the
general sessions on Wednesday, meetings of the DASS take place. The Spring '92
Meeting is sponsored by the International Federation for Information Processing IFIP WG 10.2/10.5.
Special thanks to Eugenio Villar. He has been the key person in the organization
of the Spring '92 Meeting of  the VHDL-Forum for CAD in Europe.

Andreas Hohl
General Chair

Organization Chair:
Eugenio Villar, University of Cantabria, Spain

Program Committee:
D. Borrione, France, A. Hohl (Chair), Germany, J. Mermet, France, G. Musgrave,  U.K., A. Postula, Sweden, F. Rammig,  Germany

Meeting Secretariat:
Viajes Yllera			Phone:  +34-42-223200
Calvo Sotelo 15, Apartado 322, 	Fax:	+34-42-223317
39009 Santander, Spain


-------------------- PROGRAM ------------------------

Sunday, April 26th, 1992

11.00 - 13.00 Registration
14.30 - 17.30 Tutorial Session
1. Behavioural Synthesis From VHDL
by Paul J. Menchini, CLSI Solutions, USA
2. System Level Modelling for Synthesis
by Ahmed A. Jerraya, IMAG, France
3. :The New VHDL:
by Stanley J. Krolikoski, IBM, USA
4. Principles of VHDL
by Wolfgang Ecker, Siemens, Germany


Monday, April 27th, 1992

Registration (8.00 - 9.00)
Introduction Session
(Chair: A. Hohl, Siemens, Germany)
Keynote Address: Applicability of Synthesis in Practise
E. Marschner, CLSI, USA

Session 1, Synthesis and Modeling Aspects
(Chair:  E. Villar, University of Cantabria, Spain)
A Graphical FSM Extractors and a Block Extractor of Optimal-For-Synthesis VHDL Descriptions, R. de Fermin, F. Reguero, Telettra Espana, Spain
VHDL-Based Synthesis and Rapid Prototyping in DSP-ASIC Application, A. Nummela, J. Nousiainen, J. Isoaho, H. Tenhunen, Tampere University of Technology, Finland
Automation of Digital Design Using VHDL, S. Parameswaran, M.F. Schulz, University of Queensland, Australia
VHDL Translated to the Sprite* Input Language - A Bridge to High Level Synthesis, W. Smits, Th. Krol,Philips, The Netherlands
Integration of VHDL Models for Standard Functions, M. Selz, R. Zavala, K.D. MHuller-Glaser, University of Erlangen-NHurnberg, Germany

Session 2, High-Performance VHDL Models for Simulation and Synthesis - a contradiction in terms?
(Chair:	John Miles, Synopsys, U.K.)
This panel session will discuss the technical and commercial issues surrounding the performance and availability of VHDL models.  Should we sacrifice model accuracy for simulation performance?  Will synthesisable models produce quality implementations.  Will model encrytion constrain useage?  A lively debate will be encouraged.

Session 3, Vendor Presentations
(Chair: Teresa Riesgo, UPM, Spain)
Cadence, CLSI, Viewlogic, Mentor, LSILogic, Synopsys, i-Logix


Tuesday, April 28th, 1992

Session 4, Design Environments
(Chair: P. Bakowski, University of Nimes, France)
Mixed-Level VHDL Simulation Using A Hardware Accelerator,
R. Vaidyanathan, S. Nayudu, G.-W. Huang, Synopsys, USA
The Use Of VHDL In The Design Of MANSE - A Hardware Accelerator For VHDL, A. Carpenter, N. Whitaker, D. Cock, C. Holmes, University of Manchester, U.K.
A Design Manager For VHDL, E. Molenkamp, University of Twente, The Netherlands

Session 5,	VHDL Applications
(Chair:  S. MHarz, Siemens, Germany)
Digital Filter Design Using VHDL, P. Scheidt, S. Carlson, Synopsys, USA
VHDL for Modelling and Synthesis; Design of the Hitachi H8/330 Microcontroller, I. Barton, G. Dixon, ED, U.K., N. Bullock, D. Southeard, Hitachi Europe, U.K.
ALNILAM: From VHDL to Silicon, a True Story, P.-Y. Thoulon, Hewlett-Packard France, France
Usage of VHDL and Verilog for a Processor Development, E. Lecha, M. More, Ll. Teres, Universitat Autonoma de Barcelona, Spain
A Methodology for the Development of High Quality Standard-Cell Models in VHDL, M. Blueml, B. Kierdorf, M. Lenzen, A. Pawlak, GMD, Project E.I.S., Germany

Session 6, Working Groups
Synthesis  (Chair: A. Postula, Swedish Institute of Microelectronics, Sweden, e-mail: adam@inmic.se)
ComponentModeling ( Chair: P. Bakowski, University of Nimes, France, A. Pawlak, GMD, Project E.I.S., Germany)
System Level Modeling (Chair: C. Oczko, CADLAB, Germany, co@cadlab.uucp)
Industrial Applications (Chair: A. Patterson, Cadence, U.K., andrewp@cadence.com)
Formal Methods (Chair: D. Borrione, IMAG/Artemis, France, borrione@imag.uucp)
VASG - Analog Extensions to VHDL (Chair: R. Cottrell, LSILogic, U.K.,  rac@dcs1.lsil.com
* For information about the WG activities, please contact the WG chairperson .


Wednesday, April 29th, 1992
Session 7, VHDL '92 Standardization and VHDL Users' Groups, (Chair:  J. Mermet, IMT, France)
6 months before the reballot of VHDL as an IEEE Standard information about the standardization process is presented. The meeting attendees have a chance to discuss the influence of the international users' groups on the standardization process and an informal vote on the new standard will reflect the users' point of view.

Session 8, Design Methodology - from System Level  to RT-Level, (Chair:  A. Hohl, Siemens, Germany)
Semaphores in HW-Design, A. Scheuer, W. Ecker, Siemens, Germany
Object Oriented VHDL Extension, R. Zippelius, University of Erlange-NHurnberg, Germany
Mapping Strategies for System Level Specification Data Structures to VHDL Implementations, L.P.M. Benders, Open Universiteit Herlen, F.P.M. Budzelaar, M.P.J. Stevens, EindhovenUniversity of Technology, The
Netherlands
Specification of Timing Constraints in the Design Process, W. Ecker, Siemens, Germany

-------------------
Wednesday Afternoon
VASG Meeting
Open Meeting of the DASS VHDL Analysis and Standardization Subcommittee