From: malaiya@CS.ColoState.EDU (Y. Malaiya)
Newsgroups: news.announce.conferences
Subject: VLSI DESIGN '93 in Bombay
Date: 19 Nov 92 01:01:57 GMT
Expires: Wed, 6 Jan 1993 08:00:00 GMT
Organization: Colorado State University, Computer Science Department


  *******************
 |  VLSI DESIGN '93  |      ADVANCE PROGRAM
  *******************

      THE SIXTH INTERNATIONAL CONFERENCE ON VLSI DESIGN
      Taj Intercontinental Hotel, Bombay, India
      January 3-6, 1993

      In Cooperation with:
              IEEE Computer Society
                  TC on Design Automation and VLSI
              IEEE CIRCUITS AND SYSTEMS SOCIETY
              ACM SIGDA
      Sponsored by:
              VLSI SOCIETY OF INDIA (VSI)
              DEPARTMENT OF ELECTRONICS (GOVT OF INDIA)

The conference is a forum for researchers  and designers  to
present  and  discuss  various   aspects of VLSI design. The
theme of this year conference will include  both  chip   and
board  design.  The four-day program will consist of regular
paper sessions, posters,  tutorials,  and   industrial   CAD
exhibits.   There   will  be  opportunities for informal ex-
change of ideas.  The  proceedings will be  published by the
IEEE Computer Society.

                      ********************
                          REGISTRATION
                      ********************

Advance registation to the conference is available at a  re-
duced rate of $150.00 before Nov. 15, 1992. Registration fee
includeds on copy of conference proceedings,  lunches,  ban-
quet, one  year complimentary membership to the VLSI Society
of  India  and  a  sight-seeing tour.  Additional copies  of
the  proceedings  can  be purchased at $35.00 each.  Advance
registration for tutorials is available at  -  one  tutorial
for  $120.00  and two tutorials for $200.00. Please fill out
the following form and send it to N. Ranganathan,  Dept.  of
Computer Science and Engineering, University of South Flori-
da (ENG 118), Tampa, FL 33620.

NAME   _____________________________________________________
ADDRESS   __________________________________________________
____________________________________________________________
____________________________________________________________
PHONE ___________________ EMAIL ____________________________

___ I would like to preregister, my payment includes $150.00.

___ I would like to register for following tutorials  (check
at most one per day). Amount $ ___________ is included in my
payment.
    Sunday, Jan 3rd: ___ T1   ___ T2  ___ T3
    Monday, Jan 4th: ___ T4   ___ T5  ___ t6

___ I would like to buy ___________ copies of the conference
proceedings (at US $35.00 each). Amount $ _______________ is
included in my payment.



                     September 5, 1992





                           - 2 -




                      **********************
                         ADVANCE PROGRAM
                      **********************





SUNDAY, JANUARY 3, 1993, PARALLEL TUTORIAL SESSIONS,  9:00AM
                                                      5:00PM
************************************************************

T1.  FIELD  PROGRAMMABLE  GATE  ARRAYS,  M.J.S. Smith, U. of
Hawaii and Compass Design Automation,  San  Jose,  CA,  USA.
This tutorial will cover the basics of FPGAs, including log-
ic cells, programming technology,  I/O  cells,  programmable
interconnect  and  programming  hardware  and software.  The
Differences between the major FPGA vendors and  the  use  of
third  party  software will be covered including a review of
current synthesis capabilities for FPGAs.  Two examples will
be  discussed.   The  first  is  a  simple UART design.  The
second example is a detailed description of a reprogrammable
hardware card designed for the Apple Macintosh.

T2. ARCHITECTURAL FEATURES OF DIGITAL SIGNAL PROCESSING  IN-
TEGRATED CIRCUITS, W.A. Gordon Jr., Texas Instruments, Staf-
ford, TX, USA.  This tutorial will cover  the  evolution  of
VLSI implementation of DSP hardware.  The discussion will be
based on the Texas Instruments TMS320  family.   Topics  in-
cluding  DSP background, algorithms and requirements, archi-
tectural evolution, implementations, data addressing  modes,
diagnostic,  analysis  and  debug, efficient use of multiple
DSP ICs, comparison of application specific, RISC  and  CISC
processors will be discussed.

T3. PHYSICAL DESIGN OF HIGH  PERFORMANCE  VLSI  SYSTEMS,  N.
Sherwani, Western Michigan U., Kalamazoo, MI, USA.  This tu-
torial will present an overview of VLSI design cycle and fa-
brication  of VLSI circuits in various MOS technologies.  It
will concentrate on various stages of VLSI  physical  design
such as partitioning, floorplanning, routing, compaction and
timing driven aspects of physical design problems.  In  par-
ticular,  algorithms  for timing driven partitioning, place-
ment and routing will be presented.  All  concepts  will  be
explained with detailed worked out examples.










                     September 5, 1992





                           - 3 -


MONDAY, JANUARY 4, 1993, PARALLEL TUTORIAL SESSIONS,  9:00AM
                                                      5:00PM
************************************************************

T4.  COMPUTER  AIDED  DESIGN  FOR MULTI-CHIP MODULES, W.W.M.
Dai, U. of California,  Santa  Cruz  and  R.  Wang,  Cadence
Design  Systems, San Jose, CA, USA.  This tutorial will pro-
vide a two-part view of multi-chip module  technology.   The
first  part  covers  modeling and analysis of VLSI intercon-
nects with an emphasis on full-wave  modeling.   The  second
part  addresses the problems encountered in propagating high
speed signals on lossy transmission lines on the  substrates
of  thin-film  MCM.   The  challenges  in layout of MCM sub-
strates including the design of  optimal  self-damped  lossy
transmission lines will be discussed.

T5. BOUNDARY SCAN TESTING: AN INTRODUCTION TO IEEE  STANDARD
1149.1, C. Maunder, British Telecom, UK.  This tutorial will
provide an introduction to ANSI/IEEE Std  1149.1,  "Standard
Test  Access  Port and Boundary Scan Architecture", and will
show how boundary-scan can be implemented and used.  It will
discuss  the use of the standard to test loaded boards, con-
centrating on pattern generation for detection and diagnosis
of  faults. The speaker will review commercial products that
support the standard.  The concluding discussion  will  also
review other IEEE standards under development.

T6. RISC MICROPROCESSORS: ARCHITECTURE AND DESIGN, R. Kumar,
Hewlett  Packard  Labs,  Palo  Alto, CA, USA.  This tutorial
covers the issues involved in the architecture and design of
a  high  performance  CMOS (BiCMOS) VLSI microprocessor. The
design of various microprocessor functional units  including
Instruction  unit,  register  files, arithmetic logic units,
instruction and data caches will be discussed.  The  speaker
will  also  explain  the  operation  of pipeline and various
trade-offs involved in optimizing the pipeline. The  discus-
sion  will  also  include the design of super-scalar, super-
pipeline and very large instruction word (VLIW) machines.







************************************************************
MONDAY,  JANUARY  4,  1993,  CONFERENCE INAUGURATION, 5:00PM
Chief Guest: N. Vittal, Dept. of Electronics, Govt. of India
************************************************************








                     September 5, 1992





                           - 4 -

****************************************************
TUESDAY, JANUARY 5, 1993,    PARALLEL PAPER SESSIONS
****************************************************


SESSION 1.  LOGIC SYNTHESIS, 9:00AM -  10:30AM
Chair:  K.S. Raghunathan, ITI, Bangalore, India
*************************************************

A HEURISTIC FOR DECOMPOSITION IN MULTI LEVEL LOGIC OPTIMIZA-
TION,  V.K.  Singh  - ASIC Tech., Bangalore and A.A. Diwan -
IIT Bombay, India.

COMBINING STATE ASSIGNMENT WITH  PLA  FOLDING,  C.R.  Mohan,
P.P. Chakrabarti and S. Ghose - IIT Kharagpur, India.

STATE ASSIGNMENT  FOR  OPTIMAL  DESIGN  OF  MONITORED  SELF-
CHECKING  SEQUENTIAL  CIRCUITS,  R.A. Parekhji, G. Venkatesh
and S.D. Sherlekar - IIT Bombay, India.

SYNTHESIS OF HAZARD-FREE ASYNCHRONOUS CIRCUITS FROM GENERAL-
IZED SIGNAL-TRANSITION GRAPHS, A.V. Yakovlev - U. of Newcas-
tle Upon Tyne, UK.


SESSION 2.  VLSI ALGORITHMS,  9.00AM  -  10:30AM
Chair: B. Courtois, IMAG/TIM3, France
************************************************

SIGMA: A VLSI CHIP FOR GALOIS FIELD GF2  BASED MUL-
TIPLICATION  AND DIVISION, M. Kovac - U. of Zagreb, Croatia,
N. Ranganathan and M. Varanasi - U. of South Florida, Tampa,
FL, USA.

A PARTITION APPROACH TO SOLVE THE LONGEST COMMON SUBSEQUENCE
PROBLEM,  C.S. Rahman and M. Lu - Texas A&M U., College Sta-
tion, TX, USA.

DESIGN OF AN ON-LINE EUCLIDIAN PROCESSOR,  R.  Bouraoui,  A.
Guyot and G. Walker - IMAG/TIM3, France.

HARDWARE ALGORITHMS FOR POLYGON MATCHING, R. Sastry  and  N.
Ranganathan  -  U.  of  South Florida, Tampa, FL, USA and H.
Bunke - U. of Bern, Switzerland.


                    COFFEE, 10:30AM - 10:45AM
                  *****************************

SESSION 3.  DESIGN FOR TESTABILITY, 10:45AM - 12:45PM
Chair: K. Kinoshita, Osaka U., Japan
*******************************************************

HEURISTICS FOR THE PLACEMENT OF FLIP-FLOPS IN  PARTIAL  SCAN
DESIGNS  AND  THE PLACEMENT OF SIGNAL BOOSTERS IN LOSSY CIR-
CUITS, D. Paik - AT&T Bell Labs, Murray Hill, NJ, S.M. Reddy
-  U.  of  Iowa, Iowa City, IA and S. Sahni - U. of Florida,
Gainesville, FL, USA.


                     September 5, 1992


                           - 5 -


A DFT TECHNIQUE TO IMPROVE ATPG  EFFICIENCY  FOR  SEQUENTIAL
CIRCUITS,  Y.  Bertrand,  F.  Bancel and M. Renovell - U. of
Montpellier, France.

STATISTICAL ANALYSIS OF CONTROLLABILITY, A.  Majumdar  -  S.
Illinois U., Carbondale, IL, USA and S. Sastry, U. of Arizo-
na, Tuscon, AZ, USA.

CACOP - A RANDOM PATTERN TESTABILITY ANALYZER, W.B.  Jone  -
New  Maxico Tech., Socorro, NM, USA and S.R. Das - U. of Ot-
tawa, Canada.

PLATO: A TOOL FOR COMPUTATION OF EXACT SIGNAL PROBABILITIES,
R. Krieger - G W Goethe U., Frankfurt, Germany.

ON THE GENERATION  OF  WEIGHTS  FOR  WEIGHTED  PSEUDO-RANDOM
TESTING, I. Pomeranz and S.M. Reddy - U. of Iowa, Iowa City,
IA, USA.


SESSION 4.  PHYSICAL DESIGN, 10:45AM - 12:45PM
Chair: P. Pal Chaudhuri, IIT Kharagpur, India
**************************************************

FLOR: A  HIERARCHICAL  FLOORPLANNER  UNDER  VCX  SYSTEM,  S.
Ahmed,  T.V.  Nagesh,  R.  Rao, B. Naveen, P.K. Fangaria and
K.S. Raghunathan - ITI Bangalore, India.

NP-COMPLETENESS OF MULTI-LAYER CHANNEL ROUTING AND AN  EFFI-
CIENT HEURISTIC, R.K. Pal, S.P. Pal, A.K. Dutta and A. Pal -
IIT Kharagpur, India.

A MULTIPLE TERMINAL  NET  ROUTING  ALGORITHM  USING  FAILURE
PREDICTION,  E.P.  Huijbregts and J.A.G. Jess - Eindhoven U.
of Tech., The Netherlands.

EUCLIDEAN SHORTEST PATH PROBLEM WITH  RECTILINEAR  BARRIERS,
J.S.  Lim, S.S. Iyengar and S.Q. Zheng - Louisiana State U.,
Baton Rouge, LA, USA.

ON  OPTIMUM  CELL  MODELS  FOR  OVER-THE-CELL  ROUTING,   S.
Bhingarde,  A.  Panyam  and N.A. Sherwani - Western Michigan
U., Kalamazoo, MI, USA.

ESTIMATING AREA EFFICIENCY OF ANTIFUSE BASED CHANNELED  FPGA
ARCHITECTURES,  M. Mehendale - Texas Instruments, Bangalore,
India and K. Roy - Texas Instruments, Dallas, TX, USA.

                 LUNCH, 12:45PM - 1:45PM
               ***************************




                     September 5, 1992





                           - 6 -

SESSION 5.  POSTER INTRODUCTIONS, 1:45PM - 2:45PM
Chair: R. Pai, ASIC Technologies, Bangalore, India
******************************************************

EFFICIENT TECHNIQUES TO REDUCE GATE EVALUATIONS AND SPEED UP
FAULT  SIMULATION,  P.R.S.  Kumar  -  HAL,  Bangalore,  M.K.
Srinivas and J. Jacob - IISc, Bangalore, India.

A PLA-BASED FSM DESIGN TECHNIQUE, S. Raman and M.M. Hasan  -
IIT Kanpur, India.

SYNTHESIS OF SELF-CHECKING SEQUENTIAL MACHINES USING  CELLU-
LAR  AUTOMATA, D. Roy Chowdhury, S. Roy and P. Pal Chaudhuri
- IIT Kharagpur, India.

A MULTILAYERED FEED FORWARD NEURAL NETWORK SUITABLE FOR VLSI
IMPLEMENTATION,  H.S. Mazumdar - Physical Res. Labs, Ahmeda-
bad, India.

VIA MINIMIZATION IN CHANNEL ROUTING BY LAYOUT  MODIFICATION,
S. Das - U. of North Bengal, Darjeeling and B.B. Bhattachar-
ya - ISI, Calcutta, India.

EXPERIENCES WITH A HIGH LEVEL DESIGN SYSTEM  -  IDEAS,  C.S.
Ajay,  M.  Balakrishnan,  D. Harikrishna, M. Karunakaran, A.
Kumar, S. Kumar, V. Mudgil and A.R. Naseer - IIT Delhi,  In-
dia.

BEST: BOND EDITOR AND TEST VECTOR TRANSLATOR,  P.  Marimuthu
and K.S. Raghunathan - ITI, Bangalore, India.

VLSI IMPLEMENTATION OF 32 BIT RISC CORE ARCHITECTURE FOR EM-
BEDDED  CONTROL, M.K. Lee, B.Y. Choi, S.H. Lee, K.Y. Lee and
S.I. Son - Yonsei U., Seoul, Korea.

A SCHEME FOR SYNTHESIZING TESTABLE VLSI DESIGNS WITH MINIMUM
AREA  OVERHEAD, B. Mitra - Texas Instruments, Bangalore, and
P. Pal Chaudhuri - IIT Kharagpur, India.

A UNIFIED APPROACH TO VLSI MULTILAYER PLANAR  ROUTING  PROB-
LEMS,  M.  Hossain  and N.A. Sherwani - Western Michigan U.,
Kalamazoo, MI, USA and J.  Cong  -  U.  of  California,  Los
Angeles, CA, USA.


SESSION 6.  VLSI EDUCATION, 2:45PM - 3:15PM
Chair: M.M. Hasan, IIT Kanpur, India
************************************************

PREPARING THE ENGINEERS FOR MEETING THE  CHALLENGES  OF  MI-
CROELECTRONICS  AND  INTEGRATED SYSTEM DESIGN THROUGH PROPER
BLENDING OF THEORY AND EXPERIMENT IN EDUCATION, K. Prasad  -
U. of Massachusetts Lowell, Lowell, MA and A. P. Goel - Mer-
rimack College, Andover, MA, USA.


                   COFFEE, 3:15PM - 3:30PM
                 ***************************


                     September 5, 1992



                           - 7 -


SESSION 7.  TESTING, 3:30PM -  5:30PM
Chair: M. Bushnell, Rutgers U., NJ, USA
***************************************************

USE OF STORAGE ELEMENTS AS PRIMITIVES FOR MODELING FAULTS IN
SEQUENTIAL  CIRCUITS,  W.K. Al-Assadi, Y.K. Malaiya and A.P.
Jayasumana - Colorado State U., Fort Collins, CO, USA.

TEST GENERATION FOR SYNCHRONOUS REALIZATIONS OF BOOLEAN  IN-
TERPRETED PETRI NETS USING COMPOSITE MULTI-VALUED NETS, I.G.
Tabakow - Inst. for Mech and Elec Eng., Sofia, Bulgaria.

A HIERARCHICAL TEST GENERATION USING HIGH LEVEL  PRIMITIVES,
D.  Crestani,  A.  Aguila,  L.  Eudeline, M.H. Gentil and C.
Durante - LIRMM, France.

FAST-SC: FAST FAULT SIMULATION IN  SEQUENTIAL  CIRCUITS,  B.
Becker and R. Krieger - G W Goethe U., Frankfurt, Germany.

A SIMULATION-BASED TEST GENERATION SCHEME USING GENETIC  AL-
GORITHMS,  M.  Srinivas  and L.M. Patnaik - IISc, Bangalore,
India.

COVERAGE OF BRIDGING FAULTS BY RANDOM TESTING IN $I sub DDQ$
TEST  ENVIRONMENT, R. Rajsuman and D.A. Penry - Case Western
Reserve U., Cleveland, OH, USA.

AUTOMATIC TEST PLAN GENERATION FOR  ANALOG  INTEGRATED  CIR-
CUITS  -  A  PRACTICAL  APPROACH,  R.  Naiknaware, G.N. Nan-
dakumar, R. Arora - Texas Instruments, Bangalore, India  and
J. Larkin - Texas Instruments, Dallas, TX, USA.


SESSION 8.   DIGITAL  SIGNAL  PROCESSING,  3:30PM  -  5:30PM
Chair: R. Brodersen, U. California, Berkeley, USA
**********************************************************

RATE-OPTIMAL DSP SYNTHESIS BY PIPELINE AND  MINIMUM  UNFOLD-
ING,  L.G.  Jeng and L.G. Chen - National Taiwan U., Taipei,
Taiwan.

GREEDY HARDWARE OPTIMIZATION FOR LINEAR DIGITAL SYSTEMS  US-
ING  REAL-NUMBER  SPLITTING  AND  REPEATED FACTORIZATION, A.
Chatterjee - GE, Schenectady, NY,  USA,  R.K.   Roy  -  NEC,
Princeton,  NJ,  USA  and  M.A. d'Abreu - Intel Co., Folsom,
USA.

A SIMPLIFIED HIGH SPEED PARALLEL INPUT CONVOLVER, L. Dadda -
Politecnico di Milano, Milano, Italy.

AN AREA EFFICIENT SYSTOLIC ARCHITECTURE FOR REAL  TIME  VLSI
FINITE  IMPULSE RESPONSE FILTERS, V. Visvanathan, N. Mohanty
and S. Ramanathan - IISc, Bangalore, India.




                     September 5, 1992





                           - 8 -


A RECONFIGURABLE ARITHMETIC PROCESSOR, A. Rajagopal, B. Kut-
tanna,  B.  Janakiraman, R. Mukherjee and J. Shetler - Texas
A&M U., College Station, TX, USA.

A METHODOLOGY FOR GENERATING APPLICATION SPECIFIC TREE  MUL-
TIPLIERS,  S.  Ramanathan,  N.  Mohanty and V. Visvanathan -
IISc, Bangalore, India.


      ************************************************
           BANQUET  SESSION,  6:30PM - 8:00PM Chair:
V.D. Agrawal, AT&T Bell Labs., Murray Hill, NJ, USA.  Awards
Keynote  Address:  ON  THE  HISTORY AND FUTURE DIRECTIONS OF
VLSI DESIGN AND CAD: A JAPANESE PERSPECTIVE,  O.  Karatsu  -
NTT, Japan.

                     DINNER, 8:00PM
      *************************************************


************************************************************
WEDNESDAY, JANUARY 6, 1993,    PARALLEL PAPER SESSIONS
************************************************************


SESSION 9.  HIGH LEVEL SYNTHESIS, 8:30AM - 10:30AM
Chair: A. Kumar, IIT Delhi, India
******************************************************

GB: A NEW GRID-BASED BINDING APPROACH  FOR  HIGH-LEVEL  SYN-
THESIS,  H.J.  Jang  and B. Pangrle - Pennsylvania State U.,
University Park, PA, USA.

SELF ORGANIZATION AND ITS APPLICATION TO BINDING, A.  Hemani
- Royal Inst of Tech., Stockholm, Sweden.

AN INTEGRATED AND ACCELERATED ILP SOLUTION  FOR  SCHEDULING,
MODULE  ALLOCATION,  AND BINDING IN DATAPATH SYNTHESIS, T.C.
Wilson, N. Mukherjee, M.K. Garg and D.K.  Banerji  -  U.  of
Guelph, Guelph, Canada.

HARMONIC  SCHEDULING:  A  TECHNIQUE  FOR  SCHEDULING  BEYOND
LOOP-CARRIED DEPENDENCIES, H. Wang, N. Dutt and A. Nicolau -
U. of California, Irvine, CA, USA.

MS 3: A MICRO-ROLL BACK AND SELF RECOVERY SYSTEM  SYN-
THESIS,  B.W.  Jeon  and  C.  Lursinsap - U. of Southwestern
Louisiana, Lafayette, LA, USA.








                     September 5, 1992






                           - 9 -

SESSION 10.  MODULE GENERATORS, 8:30AM - 10:30AM
Chair: C. Shekhar, CEERI, Pilani, India
******************************************************

GENETIC BEAM SEARCH FOR GATE MATRIX LAYOUT, K. Shahookar, W.
Khamisani,  P.  Mazumder - U. of Michigan, Ann Arbor, MI and
S.M. Reddy - U. of Iowa, Iowa City, IA, USA.

A MODULE GENERATOR DEVELOPMENT ENVIRONMENT: AREA  ESTIMATION
AND DESIGN SPACE EXPLORATION ENCAPSULATION, A. Tyagi - U. of
North Carolina, Chapel Hill, NC, USA.

AREA EFFICIENT VLSI DESIGNS WITH CELLS OF CONTROLLABLE  COM-
PLEXITY,  G.  Panneerselvam, A. Sarkar, S. Bandyopadhyay and
G.A. Jullien - U. of Windsor, Canada.

A PRACTICAL APPROACH TO LAYOUT  OPTIMIZATION,  R.  Gocindan,
M.A.  Langston  and  S. Ramachandramurthi - U. of Tennessee,
Knoxville, TN, USA.

PERFORMANCE ASPECTS OF GATE MATRIX LAYOUT, B.  Hald  and  J.
Madsen - Technical U. of Denmark, Lyngby, Denmark.

LATCHECK: A LATCHUP CHECKER FOR VLSI LAYOUTS, A.  Agrawal  -
Texas Instruments, Bangalore, India.


                 COFFEE, 10:30AM - 10:45AM
              *******************************


SESSION 11.  PARALLEL CAD, 10:45AM - 11:45PM
Chair: P. Banerjee, U. of Illinois, Urbana, IL, USA
******************************************************

A PARALLEL VLSI CIRCUIT LAYOUT  METHODOLOGY,  S.  Bapat  and
J.P. Cohoon - U. of Virginia, Charlottesville, VA, USA.

PARALLEL NETWORK PRIMAL DUAL METHOD ON A SHARED MEMORY  MUL-
TIPROCESSOR AND A UNIFIED APPROACH TO VLSI LAYOUT COMPACTION
AND WIRE BALANCING, K. Thulasiraman, R.P. Chalasani, P. Thu-
lasiraman and M.A. Comeau - Concordia U., Montreal, Canada.

ARCHITECTURE OF A MIN-MAX SIMULATOR ON  MARS,  K.N.  Lalgudi
and  D. Bhattacharya - Yale U., New Haven, CT and P. Agrawal
- AT&T Bell Labs, Murray Hill, NJ, USA.


SESSION 12.  VLSI ARCHITECTURE, 10:45AM - 11:45AM
Chair: A. Agarwal, MIT, Cambridge, MA, USA
*******************************************************

A MASSIVELY PARALLEL MICRO-GRAINED VLSI  ARCHITECTURE,  R.S.
Bajwa,  R.M.  Owen  and  M.J. Irwin - Pennsylvania State U.,
University Park, PA, USA.

MIPS-DRIVEN EARLY DESIGN AND ANALYSIS OF VLSI CPU CHIPS,  P.
Bose - IBM, Yorktown Heights, NY, USA.


                     September 5, 1992



                           - 10 -


ALGORITHM-BASED CONCURRENT ERROR DETECTION FOR FFT NETWORKS,
C.G.  Oh,  H.Y.  Youn and V.K. Raj - U. of Texas, Arlington,
TX, USA.


SESSION 13.  PANEL, 11:45AM - 12:45PM
Chair: S.D. Sherlekar - IIT Bombay, India.
EXPORT OF VLSI DESIGN AND CAD: PRESENT AND FUTURE
*****************************************************


                 LUNCH, 12:45PM - 1:45PM
             ******************************


SESSION 14.  DELAY FAULT TESTING, 1:45PM - 3:15PM
Chair: D. Bhattacharya, Yale U., New Haven, CT, USA
******************************************************

ON UNIFIED DELAY FAULT TESTING, A.K. Pramanick - IBM, Kings-
ton, NY and S.M. Reddy - U.  of Iowa, Iowa City, IA, USA.

A PATH DELAY FAULT SIMULATOR  FOR  SEQUENTIAL  CIRCUITS,  S.
Bose,  P. Agrawal and V.D. Agrawal - AT&T Bell Labs., Murray
Hill, NJ, USA.

SYNTHESIS OF SEQUENTIAL CIRCUITS FOR  COMPLETE  ROBUST  PATH
DELAY  FAULT TESTABILITY, S. Bhatia and N.K. Jha - Princeton
U., Princeton, NJ, USA.

DELAY FAULT TEST GENERATION WITH CELLULAR AUTOMATA, S.  Nan-
dy, S. Roy and P. Pal Chaudhuri - IIT Kharagpur, India.


SESSION 15.  CAD FRAMEWORKS, 1:45PM - 3:15PM
Chair: A.N. Chandorkar, IIT Bombay, India
************************************************

INTEGRATED TCAD SYSTEM FOR  PROCESS  AND  DEVICE  DESIGNERS,
K.S.V.  Gopalarao,  U.  Dasgupta and R. Jain - Texas Instru-
ments, Bangalore, India, D. Boning and P.K.  Mozumder - Tex-
as  Instruments, Dallas, TX, USA and V. Chandramouli - U. of
Texas, Austin, TX, USA.

A MECHANISM FOR FINE GRAINED CONCURRENT  SHARING  OF  DESIGN
DATA  AMONG  VLSI CAD TOOLS, P. Kist - Delft U. of Tech, The
Netherlands.

DESSERT: DESIGN SPACE EXPLORATION OF  RT  LEVEL  COMPONENTS,
M.V. Rao, M. Balakrishnan and A. Kumar - IIT Delhi, India.

CAE IN REQUIREMENTS DEFINITION AND SPECIFICATION FOR COMPLEX
MICROELECTRONIC   SYSTEMS,  K.D.M.  Glaser  -  U.  Ehlangen-
Nurenberg, Germany.



                     September 5, 1992





                           - 11 -


                  COFFEE, 3:15PM - 3:30PM
                ***************************


SESSION 16.  RTL AND LOGIC DESIGN, 3:30PM - 5:35PM
Chair: N. Rumin, McGill U., Montreal, Canada
******************************************************

OPTIMIZATIONS FOR  BEHAVIORAL/RTL  SIMULATION,  S.  Karthik,
J.A.  Abraham  -  U.   of  Texas,  Austin, TX and R. Voith -
Motorola Inc., Austin, TX, USA.

A SHARED MEMORY PARALLEL ALGORITHM FOR LOGIC SYNTHESIS, C.F.
Lim,  P. Banerjee, K. De and S. Muroga - U. of Illinois, Ur-
bana, IL, USA.

MINIMIZATION OF LOGIC FUNCTIONS  USING  ESSENTIAL  SIGNATURE
SETS, J. Sanghavi, P. McGeer, R. Brayton and A.S. Vincentel-
li - U. of California, Berkeley, CA, USA.

TOWARDS A SYMBOLIC LOGIC MINIMIZATION ALGORITHM, O.  Coudert
and J.C. Madre - Bull Corporate Res. Center, France.

A NOVEL SCHEME FOR SYNTHESIS OF EASILY TESTABLE FINITE STATE
MACHINE  USING  CELLULAR AUTOMATA, S. Misra and P. Pal Chau-
dhuri - IIT Kharagpur and B. Mitra - Texas Instruments, Ban-
galore, India.


SESSION 17.  CIRCUIT  DESIGN,  3:30PM  -  5:30PM
Chair: A. Strojwas, CMU, Pittsburgh, PA, USA
***************************************************

NPCPL: NORMAL PROCESS COMPLEMENTARY  PASS  TRANSISTOR  LOGIC
FOR  LOW  LATENCY,  HIGH  THROUGHPUT DESIGNS, D. Ghosh, S.K.
Nandy, K. Parthasarathy and V. Visvanathan - IISc Bangalore,
India.

A 230 MHZ HALF BIT LEVEL  PIPELINED  MULTIPLIER  USING  TRUE
SINGLE  PHASE CLOCKING, V. Visvanathan - IISc Bangalore, In-
dia.

FAULT TOLERANT ARBITRATION IN MULTICHIP  CROSSBAR  SWITCHES,
J.  Ghosh  and  N.  Krishnamurthy - U. of Texas, Austin, TX,
USA.

HIGH-SPEED A/D-D/A CONVERSION SYSTEM WITH  FLEXIBLE  TESTING
CAPABILITIES,  J. Vital and J.E. Franca - Instituto Superior
Tecnico, Portugal.

A CARRY SELECT ADDER WITH CONFLICT FREE BYPASS  CIRCUIT,  M.
Shamanna and S. Whitaker - U. of Idaho, Moscow, ID, USA.

NEW CMOS STRUCTURES FOR THE SYNTHESIS OF DOMINANT FUNCTIONS,
G.  Buonanno,  D.  Sciuto and R. Stefanelli - Politecnico di
Milano, Milano, Italy.



                     September 5, 1992



                           - 12 -

           *******************************************
                       PROGRAM COMMITTEE
           *******************************************

                    STEERING COMMITTEE CHAIR
                          V. D. Agrawal
                    AT&T Bell Labs., Rm 2C-476
                         600 Mountain Ave.
                    Murray Hill, NJ 07974
                        (908) 582-4349
                      va@research.att.com

                        GENERAL  CHAIRS
Y.K. Malaiya                             S.S.S.P. Rao
Dept. of Computer Science        Dept. of Comp. Sc. and Engg.
Colorado State University          Indian Institute of Technology
Fort Collins, CO 80523, USA       Powai, Bombay 400076, India
(303) 491-7031                         +91  22  578-5708
(303) 491-2293 (FAX)               +91  22  578-3480 (FAX)
malaiya@ravi.cs.colostate.edu   ssspr@cse.iiitb.ernet.in

                     ORGANIZING COMM. CHAIR
                          S. Ramadorai
                    Tata Consultancy Services
                 Air India Bldg., Nariman Point
                      Bombay 400021, India
                     ramtcs@shakti.ernet.in
                       +91 22 202-4827
                       +91 22 204-0711 (FAX)

                        PROGRAM CHAIRS
Srimat T. Chakradhar             Sunil D. Sherlekar
NEC Research Institute          Dept. of Comp. Sc. and Engg.
4 Independence Way              Indian Institute of Technology
Princeton, NJ 08540, USA      Powai, Bombay 400076, India
(609) 951-2962, x-2499 (FAX)  +91 22 578-5708, x-3480 (FAX)
chak@research.nj.nec.com      sds@cse.iiitb.ernet.in

                        PUBLICITY   CHAIRS
Rochit Rajsuman                      Vijay  Vaidya
Dept. of Comp. Engg. and Sc.   Tata Consultancy Services
Case Western Reserve Uni.      Air India Bldg., Nariman Point
Cleveland, OH 44106, USA       Bombay 400021, India
(216) 368-5510, x-2801 (FAX)   +91 22 202-4827, 204-0711 (FAX)
rajsuman@alpha.ces.cwru.edu

                        TUTORIALS CHAIRS
Ravi Apte, Cadence Inc.        G. Venkatesh, IIT Bombay
rma@cadence.com                gv@cse.iitb.ernet.in

EXHIBITS CHAIR: C.G. Ravi, Hinditron Services, Bombay, India
DESIGN CONTEST CHAIR: J. Vasi, IIT Bombay
PUBLICATION CHAIR: V. D. Agrawal, AT&T Bell Labs
ACM LIASION: Sharad Seth, Uni. of Nebraska
IEEE LIASION: N. Ranganthan, Uni. of South Florida
VSI LIASION: A. Prabhakar, ITI Bangalore
PAST CHAIRS: A. Laha, Cadence Inc. and
             L. M. Patnaik, IISc. Bangalore
-------------------------------------------------------------
Travel: Bombay is served by Air India, British Airways.  Luftansa
and  many  other major airlines. Please contact your travel agent
or Air India at 1-800-621-8231 or Skybird  Travel  at  1-800-545-
7788.  Plese book your seats early due to the holiday rush season
during Dec.-Jan.

Hotel: Conference rates at Taj Intercontinental  are  US$125  for
single  occupancy.  Please  call 1-800-I-LUV-TAJ for reservation.
Other hotels include Ambassador, Farias, Ritz, Natraj, West  End,
Grand, Sea Green, and Sea Green South which are within reasonable
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