HDTenEightyP/NetNews huggingface dataset:
From: johan@ECE.ORST.EDU (Johan. K. Reinalda)
Subject: Coprocessor performance question
Organization: ECE Dept.,OSU,Corvallis
Distribution: usa
Date: Fri, 6 Nov 1992 00:47:47 GMT

Hi all,
i am wanting to buy a math coprocessor for my notebook.
I need a 387sx25. Since the Intel, Cyrix and IIT parts are all in roughly the
same price range, I am wondering what the tradeoffs are for getting the
2 none-Intel parts. Concerns are compatibility, performance, and power
consumption...

Please mail, and i will post summary...

Thanks, 
Johan

------------------------------------------------------------------
Johan K. Reinalda, (WG7J & PA3DIS)    Internet: johan@ECE.ORST.EDU
PBBS: WG7J@WG7J.OR.USA.NA	      USPS: 420 NW 9, Corvallis, Or 97330 
************** If it ain't DUTCH, It ain't MUCH ! ****************
From: marcusj@apricot.co.uk (Marcus Jenkins)
Newsgroups: comp.sys.intel
Subject: Re: Intel is wasting too much money on ads!
Date: 12 Nov 92 09:09:05 GMT
Distribution: comp
Organization: Apricot Computers Limited

tmh@keks.first.gmd.de (Thomas Hoberg) writes:

>I live in Berlin, Germany. Walking through the streets, I see a big
>486(Intel inside) sign on every second billboard all across the city,
>that means you can hardly go anywhere and not see at least of those
>signs...
>I can not recall that any company however loosely associated with the
>computer industry has ever come close to putting up that many signs.
...[Stuff deleted]...
Yup, we've got zillions of 486 hoardings, too.  I must agree, I can't
help feeling Intel are a bit over the top on this particular campaign.
Still, I guess it's *their* money.  (Perhaps it will leave less in
their coffers to spend in the courtroom ;-)
 _ _ _
' ) ) )                         Internet: marcusj@apricot.co.uk
 / / / __.  __  _. . . _        UUCP: marcusj@apricot.uucp
/ ' (_(_/|_/ (_(__(_/_/_)_      If all else fails from US, try:  
Marcus Jenkins                  apricot!marcusj@relay.EU.net
Tel: +44 21 472 3002  Fax: +44 21 471 2935
Disclaimer:  Anything I wrote above is, of course, my own view and
             does not in any way represent my employer.
From: mkahn@hopi.sedona.intel.com (Mitch Kahn)
Newsgroups: comp.sys.intel
Subject: Re: 8096/80196 systems
Date: 12 Nov 92 17:09:08 GMT
Organization: i960(r) New Product Development, Chandler AZ

krf1061@ultb.isc.rit.edu (K.R. Flanagan) writes:

 Summary: any one have any exsperience with them?
] Keywords: NOT the 80x86 family
] Originator: krf1061@ultb
] Nntp-Posting-Host: ultb-gw.isc.rit.edu
]
]
]	 Hi I was wondering if anyone in this group had any practicle 
]     exspereince with the intel 8096 family on 16 bit micro controllers,
]     or if there was a group on this net that dealt with them. Just 
]     curious, I've been playing around with some and have been having
]     alot of head aches. Oh for those of you unfamilar with 8096 its
]     sort of a funky 99 register 8086 without all the crazy offset

8086??? Not even close!

]     registers and has several PWM (pulse width modulation) lines for
]     D/A or ac I/O, also has a built in rom. 
]	 Actually I do have a question for anyone out there that might
]     know, I've been looking over a 80196kb board by vesta the last few 
]     days and am very confused how they can get it to support 256k,
]     (128 ram, 128 rom). I'm assuming bank switching but have no clue.
]

Why would you want 128k of ROM with a 196? 

The 196 has a 64kb address space (except the newer versions which are
1 meg). If it is because you happen to have 128K memories laying around
(which is what I suspect), just tie off the address lines you don't need.

If you *really do* need 256K of memory, use some of the port pins to
do your bank switching (just tie them to the upper address lines).
Of course, you know you cant JMP or CALL (or even execute) accross
bank lines, right :-) ?.





--
|  Mitch Kahn              | "I hope you know that this will go down on |
|  mkahn@sedona.intel.com  |  your permanent record..."                 |
*************************MY OWN OPINIONS*********************************
Newsgroups: comp.sys.intel
From: news@ux1.cso.uiuc.edu (News)
Subject: Cyrix486SLC and NeXTSTEP 486
Organization: University of Illinois at Urbana
Date: Tue, 10 Nov 1992 04:16:21 GMT

I'm not an official spokeperson or anything like that, but I just picked
up the "NeXTSTEP 486 Product Questions and Answers - Sept 30th 1992" sheet
at a PC fair on campus.  It has the following statements in it:

Q: "Will NeXTSTEP 486 run on the Cyrix 486SLC?"
A: "No. The Cyrix chip is not a true 486."

    That shows there is definitely a big difference between a Cyrix 486SLC
and a Intel 486SX/DX.  Otherwise, NeXT would advertise support for the
Cyrix chip.
    The info sheet does say that NeXTSTEP 486 will support ISA/EISA 486SX,
486DX, 486DX2, and future members of the Intel x86 family.  The IBM 486SLC
is not addressed, but that's probably because NeXTSTEP 486 won't support
MicroChannel.  It clarifies by saying that NeXTSTEP 486 will run on any
TRUE 486, so AMD better do a good job or they'll be left out too.

Jeff Barcalow
From: mlm@mrcnext.cso.uiuc.edu (Michael McCool)
Subject: Re: Violent fighter review for all interested. whee!
Newsgroups: comp.sys.intel
From: news@ux1.cso.uiuc.edu (News)
Subject: Cyrix486SLC and NeXTSTEP 486
Organization: University of Illinois at Urbana
Date: Tue, 10 Nov 1992 04:16:01 GMT

I'm not an official spokeperson or anything like that, but I just picked
up the "NeXTSTEP 486 Product Questions and Answers - Sept 30th 1992" sheet
at a PC fair on campus.  It has the following statements in it:

Q: "Will NeXTSTEP 486 run on the Cyrix 486SLC?"
A: "No. The Cyrix chip is not a true 486."

    That shows there is definitely a big difference between a Cyrix 486SLC
and a Intel 486SX/DX.  Otherwise, NeXT would advertise support for the
Cyrix chip.
    The info sheet does say that NeXTSTEP 486 will support ISA/EISA 486SX,
486DX, 486DX2, and future members of the Intel x86 family.  The IBM 486SLC
is not addressed, but that's probably because NeXTSTEP 486 won't support
MicroChannel.  It clarifies by saying that NeXTSTEP 486 will run on any
TRUE 486, so AMD better do a good job or they'll be left out too.

Jeff Barcalow

From: cs225a71@dcl-nxt48.cso.uiuc.edu (cs225 student)
Newsgroups: comp.sys.intel
From: news@ux1.cso.uiuc.edu (News)
Subject: Cyrix486SLC and NeXTSTEP 486
Organization: University of Illinois at Urbana
Date: Tue, 10 Nov 1992 04:16:06 GMT

I'm not an official spokeperson or anything like that, but I just picked
up the "NeXTSTEP 486 Product Questions and Answers - Sept 30th 1992" sheet
at a PC fair on campus.  It has the following statements in it:

Q: "Will NeXTSTEP 486 run on the Cyrix 486SLC?"
A: "No. The Cyrix chip is not a true 486."

    That shows there is definitely a big difference between a Cyrix 486SLC
and a Intel 486SX/DX.  Otherwise, NeXT would advertise support for the
Cyrix chip.
    The info sheet does say that NeXTSTEP 486 will support ISA/EISA 486SX,
486DX, 486DX2, and future members of the Intel x86 family.  The IBM 486SLC
is not addressed, but that's probably because NeXTSTEP 486 won't support
MicroChannel.  It clarifies by saying that NeXTSTEP 486 will run on any
TRUE 486, so AMD better do a good job or they'll be left out too.

Jeff Barcalow

From: cs225a71@dcl-nxt48.cso.uiuc.edu (cs225 student)
Newsgroups: comp.sys.intel
From: hibanez@wam.umd.edu (raul)
Subject: 1-800 number
Organization: University of Maryland, College Park
Distribution: usa
Date: Tue, 10 Nov 1992 02:51:28 GMT

Does anyone know the 1-800 number for Intel?  Please mail
me this number.  Thanks.

hibanez@wam.umd.edu


-- 
-------------------------------------------------------------------
lars		       hibanez@wam.umd.edu
UofMD at CP	       standard disclaimer
From: 889chai@gw.wmich.edu
Newsgroups: comp.sys.intel
Subject: 486slc actually a 386sx chip?
Date: 6 Nov 92 14:42:14 EST
Organization: Western Michigan University

hi, i heard that a 486slc is actually a 386dx chip....can anyone comment me
on this?

thanks in advance

Newsgroups: comp.sys.intel
From: mostert@cs.sun.ac.za (A. Mostert)
Subject: Re: Undocumented instructions in x86 CPUs
Organization: University of Stellenbosch
Date: Sun, 8 Nov 1992 11:34:12 GMT

In article <Bx9sv5.1yo@aeon.in-berlin.de> thomas@aeon.in-berlin.de (Thomas Wolfram) writes:
>PS: What is the '386 bit string stuff'?

On early 386s there were IBTS and XBTS (Insert/eXtract Bit String) 
instructions, but they were removed in later versions. They are absent in 
all versions of the 486. I don't know the opcodes or exactly what they do.
+----------------------------------+---------------------------------------+
| A. Mostert, Stellenbosch, RSA    | "WAFTI" - GFMTHC, SLATFATF, D. Adams  |
| mostert@cs.sun.ac.za             |                                       |
|__________________________________|_______________________________________|

Newsgroups: comp.sys.intel
From: mcastle@mcs213d.cs.umr.edu (Michael R Castle)
Subject: Re: Undocumented instructions in x86 CPUs
Date: Thu, 5 Nov 1992 10:17:17 GMT
Organization: University of Missouri - Rolla

In article <mostert.51@cs.sun.ac.za> mostert@cs.sun.ac.za (A. Mostert) writes:
>
>Hi all
>
>I just became aware of an undocumented instruction that (I think) works on
>all members of the x86 family. The opcode is D4 10 and it does this:
>   AH = AL >> 4
>   AL = AL & 0xF
>Is this a well known instruction ? Does anyone know of any other instructions
>(besides LOADALL and the 386 bit string stuff) that Intel did not tell us
>about ?

hmm.... listed in my Microprocessors and Peripheral Handbook... AAM 

Also, 
AAA   37
AAS   3F
AAD   D5 10

maybe you just need better documentation   :-> 

mrc
From: zeke@fasttech.com (Bohdan Tashchuk)
Newsgroups: comp.sys.intel
Subject: Re: Slime lives: Intel's latest tactic against clones
Date: 10 Nov 92 23:19:40 GMT
Distribution: na
Organization: Fast Technology

In <mg.721407429@elan> mg@elan (Michael Golan) writes:

>rshwake@irscscm.UUCP (Ray Shwake) writes:
>>Excerpted from InfoWorld's _At_Deadline_ column (November 12, 1992):
>>	using clone chips would be affected. The proposed royalty rates
>>	would be approximately 20 percent of the cost of the clone processor
>			       ^^^^^^^^^^^

>Wow, Intel has big balls. huge. 20% for the trivial (and stupid) seg:ofs.

Yes. Actions like this give sleaze an entirely new meaning. Intel hasn't been
able to legally succeed in preventing the entry of competitors, so they are
now attempting to intimidate their customers.

Wouldn't 20% be a high but not entirely unreasonable royalty for a COMPLETE
second source license agreement?

Intel is becoming more and more irrational, paranoid, and hysterical in their
responses to any and all competition. Hmmm. Where have we seen this sort of
thing recently? Are we sure Ross Perot isn't secretly running things there?
From: rshwake@irscscm.UUCP (Ray Shwake)
Newsgroups: comp.sys.intel
Subject: Slime lives: Intel's latest tactic against clones
Date: 7 Nov 92 17:08:52 GMT
Reply-To: shwake@rsxtech.UUCP (Ray Shwake)
Distribution: na
Organization: R|S|X Technical Services, Washington, DC

Excerpted from InfoWorld's _At_Deadline_ column (November 12, 1992):

	In a move that could put more upward pressure on systems price
	increases, Intel Corp. is asserting its right to collect royalties of	
	between $15 and $25 for every system that uses an x86 clone processor.
	Cyrix Corp. last week asked a U.S. District Court, in Dallas, to put
	a stop to the practice.

	Intel acknowledged that it has approached "a half dozen companies",
	explaining that it has a system-level patent that covers memory
	management in an x86 environment. Intel denied that the attempt to
	get royalties on that patent was an effort to keep manufacturers
	from using non-Intel processors, but it admitted that only those
	using clone chips would be affected. The proposed royalty rates
	would be approximately 20 percent of the cost of the clone processor
	and would be subject to change as pricing on the processors 
	fluctuated, a company representative said.

	Cyrix, which successfully argued in federal court this summer that
	it had a license from Intel to sell x86-compatible processors, asked
	a federal judge to issue a summary motion preventing Intel from 
	seeking royalties from manufacturers using the clone chips. Cyrix
	officials described Intel's efforts to enforce a system-level patent
	as a way of keeping major manufacturers from using Cyrix's processors.
From: rshwake@irscscm.UUCP (Ray Shwake)
Newsgroups: comp.sys.intel
Subject: Re: 386 designed in Tel Aviv?
Date: 4 Nov 92 21:59:45 GMT
Reply-To: rshwake@irscscm.UUCP (Ray Shwake)
Organization: R|S|X Technical Services, Washington, DC

In article <1d3n02INNd6s@iraul1.ira.uka.de> S_JUFFA@iravcl.ira.uka.de (|S| Norbert Juffa) writes:
>> 
>I read that, too, a while back. Looking at the authors of the papers published
>on Intel's coprocessors, it is also reasonable to assume that much (if not all)
>of the work on their coprocessor was done in Israel. Don't know if they are
>based in Tel Aviv, though. Some other chip manufacturers have design centers
>there, too. E.g. NS and IBM, I think.

	Intel's been doing a log of advanced design work in Israel at
	least back to the days of their involvement with the 8087. Motorola,
	IBM and others do a lot of high-end hardware *and* software work
	there. They also source some of their x86 chips there. I recall a
	certain concern about 80386 supplies during the Gulf War in the
	event the plant were hit by a Scud. Of course, the residents had
	other concerns.
Newsgroups: comp.sys.intel
From: korte@alhena.itp.uni-hannover.de (Gerd Kortemeyer)
Subject: How to contact IIT?
Organization: Institut fuer Theoretische Physik, Uni Hannover
Date: Wed, 11 Nov 1992 13:04:15 GMT


Hi.

Does anybody have an idea how to contact Intels clone producer IIT
via Internet?

I need technical information about the IIT-387-clone, a
'Programmer's  reference' for example.

Thanks

Gerd.

Newsgroups: comp.sys.intel
From: GJAMES@HUSKY1.STMARYS.CA (GJames)
Subject: Can A 486sx use a 387
Organization: Saint Mary's University
Date: Fri, 6 Nov 1992 18:03:57 GMT

Can I put my Math Co. math coprocessor in the expansion socket of my 486sx/25
and realize a performance gain. Is it dangerous.
Newsgroups: comp.sys.intel
From: mcnab@dinsdale.nas.nasa.gov (David McNab)
Subject: Re: Plural of Pentium (was Re: Why not INTEL586?)
Organization: NAS Program, NASA Ames Research Center, Moffett Field, CA
Date: Mon, 9 Nov 92 21:36:10 GMT

steibel@venus.cs.umbc.edu (David M. Steibel) writes:
> Or is that Pentia?  Pentiae?  Assistance from people who took some Latin
> would be much appreciated. :-)

dmccart@gomez.intel.com (D. J. McCarthy) writes:
>	One Pentium.  Two Pentiums.

rskinner@mipos2.intel.com (Rod Skinner) writes:
>There is only one way to describe the Pentium (tm) processor.  If you
>want the plural form...it is Pentium processors.  ALL trademarks are
>adjectives and therefore only have ONE form.  The noun that the 
>trademark describes can be either singular or plural as you would
>normally do.
>
>Pentium (tm) CPUs
>Pentium (tm) microprocessors

Hmm.  Are you sure the plural isn't going to be "paragon"? :-)

-----------------------------
David McNab
Parallel Systems Support
NAS Program, CSC at NASA/Ames
mcnab@nas.nasa.gov
Newsgroups: comp.sys.intel
From: korte@alhena.itp.uni-hannover.de (Gerd Kortemeyer)
Subject: 387 exceptions - when are they raised?
Keywords: 387, exceptions
Organization: Institut fuer Theoretische Physik, Uni Hannover
Date: Fri, 6 Nov 1992 09:03:12 GMT

Hi.

In the Intel '387DX Programmer's reference' you will read that
387 exceptions are raised when the NEXT copro-instruction comes. Well,
okay, then this program (written in TP6.0) should work:

asm
   fdivp
end;
writeln('Still alive!');
asm
   fwait
end;

After being blown up by the emulator it looks like this:

     wait
     fdivp
     call ....
     fwait

Now 'fdivp' divides by zero and divide-by-zero is unmasked: Still the
program should (according to the manual) write 'Still alive' onto the
screen and raise the exception when it comes to the fwait (there are
NO copro-instructions inside the WRITELN-subroutine).

Well, it doesn't.

When using the debugger you see the exception is raised right while
executing the fdivp, but this might be a 'Heisenberg effect' (things
change when you measure them ...)

Strange: This program works

    fdivp
    fnclex
    call ...
    fwait

Any ideas?

Gerd Kortemeyer
From: andrew@frip.WV.TEK.COM (Andrew Klossner)
Newsgroups: comp.sys.intel
Subject: Re: Plural of Pentium (was Re: Why not INTEL586?)
Date: 11 Nov 92 22:31:42 GMT
Reply-To: andrew@frip.wv.tek.com
Organization: Tektronix Color Printers, Wilsonville, Oregon

[]

	"I don't agree that Pentium is an adjective ... People will use
	Pentium as a noun, no matter what is intended."

Under U.S. law, Intel *must* use it as an adjective or they dilute
their rights to the trademark.  The rest of us will use Pentium as a
noun, just as we use Kleenex as a noun (and Xerox as a verb), and we'll
get the occasional letter of admonishment from Intel lawyers.

	"The ending is all wrong."

In English, "all wrong" never stopped anybody.  Other adjectives with
this ending include medium and premium.

  -=- Andrew Klossner  (andrew@frip.wv.tek.com)
                       (uunet!tektronix!frip.WV.TEK!andrew)
Newsgroups: comp.sys.intel
From: root@candle.uucp (Bruce Momjian)
Subject: /bin/ksh for root shell: problems?
Organization: a consultant's basement
Date: Tue, 10 Nov 1992 06:56:19 GMT
X-Newsreader: TIN [version 1.1 PL6]


Are there any known problems with making /bin/ksh the default shell for the
root login under HP-UX 8.02 on an HP9000?  I just want to be sure it is
ok. 
-- 
Bruce Momjian                          |  830 Blythe Avenue
root%candle.uucp@bts.com               |  Drexel Hill, Pennsylvania 19026 
  +  If your life is a hard drive,     |  (215) 353-9879(w) 
  +  Christ can be your backup.        |  (215) 853-3000(h)
Newsgroups: comp.sys.intel
From: eletanjm@nuscc.nus.sg (Tan Jin Meng)
Subject: Microcontroller
Organization: National University of Singapore
Date: Wed, 11 Nov 1992 05:24:00 GMT

Does INTEL have a microcontroller (ie UART, A/D IO ports etc) that comes
with a x86 core? The x86 core should be a relatively high performance
one (386+ ?).

My reasons are this,

1) I have a requirement for a microcontroller (small board space).

2) I have extreme budget requirements.

3) (related to 2) I want to be able to use standard PC software tools
(ie compilers/assemblers).

I'm not a VLSI design guy but I shouldn't think it'd be difficult for
INTEL to produce such a chip from stock stuff. The question is - have they?

Thanks

jin meng
Newsgroups: comp.sys.intel
From: ajrooks@mansci1.UWaterloo.ca (Alan Rooks)
Subject: Re: LOADALL and the 486
Organization: University of Waterloo
Date: Thu, 5 Nov 1992 18:33:59 GMT

marcusj@apricot.co.uk (Marcus Jenkins) writes:
>I know this may be an FAQ, but I am just a little confused.  Is
>LOADALL implemented in the 486?

[more stuff about LOADALL, asks for email answers]

FAQ or no, could someone post or give references for the documented
"undocumented" instructions?  Someone else mentioned bit-string ops on
the 386.

Thanks in advance,
Alan Rooks	University of Waterloo		ajrooks@mansci1.uwaterloo.ca
From: rskinner@mipos2.intel.com (Rod Skinner)
Newsgroups: comp.sys.intel
Subject: Re: LOADALL and the 486
Date: 6 Nov 92 04:52:54 GMT
Organization: Intel Corporation, Santa Clara, CA USA

In article <Bx9A8o.I23@watserv1.uwaterloo.ca> ajrooks@mansci1.UWaterloo.ca (Alan Rooks) writes:
>marcusj@apricot.co.uk (Marcus Jenkins) writes:
>>I know this may be an FAQ, but I am just a little confused.  Is
>>LOADALL implemented in the 486?
>
>[more stuff about LOADALL, asks for email answers]
>
>FAQ or no, could someone post or give references for the documented
>"undocumented" instructions?  Someone else mentioned bit-string ops on
>the 386.
>
>Thanks in advance,
>Alan Rooks	University of Waterloo		ajrooks@mansci1.uwaterloo.ca

LOADALL is an instruction that was intended for ICE support.  The
early versions of the 80386DX had the instruction available but was 
removed as the die size was reduced.  It is still there in the chip that
accompanies each ICE product.  I have not heard differently so I would
expect that the same is true of the Intel486 CPU family.  There is 
a faster sequence of instructions that perform the same function as 
LOADALL which was provided to those using it.  

Noone uses it today other than the ICE software (if even that).

rod


Rod Skinner				I speak for myself only.
Intel Corp
3065 Bowers Avenue   MS NW1-20            PH (408) 765-4474
Santa Clara, CA 95052                     FAX (408) 765-4920
Newsgroups: comp.sys.intel
From: f91-gal@nada.kth.se (Gran Alterland)
Subject: PC-unix plea for help!
Keywords: pc, unix, info ,help
Organization: Royal Institute of Technology, Stockholm, Sweden
Date: Fri, 13 Nov 1992 09:24:10 GMT

From f91-gal Fri Nov 13 10:13:27 1992
To: esr@snark.thyrsus.com
Subject: PC-unix plea for help!

Hello Netters!

  I represent a student body that will soon spend something
like 200.000 USD on hardware. I'd really appreciate if
you could inform me about some aspects of PC unixing.
We will be buing a Sun4 and terminals to attach to it. At present it 
looks like these 'terminals' will probably be sparcstations, but 
there is a strong movement that wishes to see a PC-based solution instead.
However, our list of requirements on such a system is long and though.
We need:
1) A system that can connect up to the Sun4 as 'dummie terminals'.
2) In terminal mode It must be able to run X11R5, with Motiv, with
at least 256 colours and a resolution of 1280x1024.
3) This must go throught a fast link - screen update must be as quick 
(or only marginally slower) than a sparcstation solution (any recommendations
the link? I think a Lan/Ethernet solution would be too slow, but I don't
really know...)
4) It must also be able to run 'standalong unix'. (Is SCO the best that's
available as far as Unix is concerned?)
5) Of course, it must run Dos, Windows and OS2 as well.

Is there any hardware that's able to do this for us?
Would any 486DX50 or DX266 solution suffice or are we better off waiting
for the Pentium? Is Local Bus necessay? VESA or PCI? 
Any help at all would be much appreciated!

E-mail to: f91-gal@alv.nada.kth.se

Thanx!



Newsgroups: comp.sys.intel,comp.sys.ibm.pc.hardware
From: aarond@xibm.StorTek.com (Aaron Dailey)
Subject: 8259 PIC programming questions
Organization: StorageTek
Date: Wed, 11 Nov 1992 19:06:40 GMT

I'm programming what is essentially a PC with several peripherals
connected via 8259 programmable interrupt controller to a 386SX
running in protected mode.  There two 8259s, in the normal AT cascaded
arrangement. 

In the interrupt handler for these devices, I send a non specific end
of interrupt (0x20) to the interrupt controller as the last thing I
do.  I've looked at some source code, which sends a specific end of
interrupt command to the PIC before exiting the ISR.  Other code I've
seen uses nonspecific EOIs.  I've looked at the IBM Tech Ref for the
AT, which documents that the BIOS initiailizes the 8259 to not special
fully nested mode, which indicates to me that I should send it a
specific EOI command.  Which do I need?

Also, I've looked at some source code which, while handling IRQ9, on
the slave PIC, only sends an EOI to the master.  The Intel data sheets
for the 8259 clearly state that EOIs must be sent to the master and
slave PICs for an interrupt on a slave PIC.  What's the deal?  I
understand that IRQ9 was IRQ2 on the master PIC on PC (8088) class
machines, but doesn't the slave PIC need to be given an EOI?

--
Aaron Dailey Internet: Aaron_Dailey@stortek.com
StorageTek Corporation   Voice: (303) 673-4989, FAX: (303) 673-2570
Mail:  MS0242, 2270 South 88th Street, Louisville, C0 80028

Xref: sparky comp.sys.intel:2181 comp.sys.ibm.pc.hardware:29157 comp.benchmarks:1624