From: icsearch@cup.portal.com (Kim S Worner)
Newsgroups: misc.jobs.offered,ba.jobs.offered
Subject: CAD (IC) SW Engr's, Santa Clara, CA  Recruiter
Date: Thu, 16 Apr 92 23:16:07 PDT
Organization: The Portal System (TM)
Distribution: ba

CAD CMOS Designers

A local San Jose, CA systems house is looking to expand it's IC CAD 
organization.  Using your previous DA skills, you can broaden your
background to add some career mobility within a systems environment.  Take
a look at these opportunities and call, write or email me regarding your
interest.

CAD Positions

A challenging position providing a highly effective RTL design environment,
including high level simulation performance analysis, timing driven synthesis.
Will drive tight integration with the physical design.

Senior Position
---------------
Experience with Verilog, Synopsys tools is essential.
Experience with Mentor/Cadence Place and Route tools is desired.
Experience with timing tools is desired. 
Knowledge of relational databases (Sybase) and Unix network programming is a
  plus.
Must be proficient in defining and implementing large software projects.
Experience providing similar solution for microprocessor design would be 
  highly desired. 
Good programming skills. (C and C++)

CAD Engineer
------------
Thorough understanding of IC Design Flow essential.
Experience with Verilog, Synopsys and Place and Route tools is desired
  although not mandatory.
Must have worked on large software project.
Knowledge of relational databases (Sybase) and Unix network programming is a
  plus.
Good programming skills. (C and C++)

A challenging postion providing leadership and innovation in providing
solution for integration of Standard cell place and route, datapath, 
floorplanner, chip level place & route, timing and synthesis tools.

Senior Position
---------------
Experience with Place and Route tools / algorithms is essential.
Experience with Mentor/GDT Place and Route tools is desirable.
Understanding of circuit design issues important.
Experience with other aspects of CAD / Design is desirable.
Must be proficient in defining and implementing software project.
Experience working in providing similar solutions for microprocessor design
would be desirable.
Good programming skills. (C and C++)


Verification Positions

The verification team is looking for a number of individuals whom fall
into three general categories:

Diagnostic developer: this person will be responsible for developing new
architectural-level tests, as well as porting and converting existing ones.
Must be a capable assembly language programmer. SPARC experience preferred.

Simulation tools developer: primarily a software engineer, this is someone
who understands logic design, simulation and modelling. Strengths should
be C programming, knowledge of CAD tools, compiler technology, discrete 
event simulation, distributed application development.

Logic verification engineer: someone who knows HDL like the back of his/her
hand, this person will use common stimulus/response generation libraries to 
develop self-checking tests of stand-alone design units. Logic design skills
  also apply.

Call or write:
		Kim Worner
		ICSEARCH
		847 Alderbrook Lane
		Cupertino, CA  95014
		408 257-4729

PS, no new grads please, all qualified persons with applicable experience
and education will receive a quick response.