From: rothenbe@eecs.ucdavis.edu (Bret Rothenberg)
Newsgroups: comp.lsi.cad,comp.lsi
Subject: Frequently Asked Questions with Answers (Part 1/1)
Keywords: FAQ
Date: 6 Oct 92 19:00:49 GMT
Followup-To: comp.lsi.cad
Organization: Deptartment of Electrical and Computer Engineering, UC Davis

Welcome to comp.lsi.cad, comp.lsi, this is the biweekly posting of fre-
quently asked questions with anwers.  Before you post a question such as
"Where can I ftp spice from?", please make sure that the answer is not
already here.  If you spot an error, or if there is any information that
you think should be included, but is not, please send us a note.

  Bret Rothenberg <rothenbe@eecs.ucdavis.edu>
  Wes Hardaker <hardaker@eecs.ucdavis.edu>
  Mike Altarriba <altarrib@eecs.ucdavis.edu>

  (Please mail to clcfaq@eecs.ucdavis.edu for suggestions/comments.)

  Solid State Circuits Research Laboratory
  Electrical Engineering and Computer Science
  University of California, Davis.
  95616


----------------------------------------------------------------------

  $Id: comp.lsi.cad.FAQ.ms,v 1.28 92/10/06 11:55:27 rothenbe Exp $

  Frequently Asked Questions with Answers

    1: Mosis Users' Group (MUG)
   !2: Improved spice listing from magic.
    3: Tips and tricks for magic (Version 6.3)
    4: What can I use to do good plots from magic/CIF?
    5: What tools are used to layout verification?
    6: How are people doing netlist conversion and what about EDIF?
    7: What layout examples are available?
    8: How can I get my lsi design fabbed and how much will it cost?
    9: Archive sites for comp.lsi.cad and comp.lsi
    10: Other newsgroups that relate to comp.lsi*
    11: Simulation programs tips/tricks/bugs
    12: Getting the latest version of the FAQ
    13: Converting from/to GDSII/CIF/Magic
    14: CFI (CAD Framework Initiative Inc.)
    15: What free tools are there available, and what can they do?
   +16: What Berkeley Tools are available for anonymous ftp?
    17: Berkeley Spice (Current version 3e2)
   !18: Octtools (Current version 5.1)
    19: Lager (Current version 4.0)
    20: BLIS (Current version 2.0)
    21: ITEM
    22: PADS logic/PADS PCB
    23: Another PCB Layout Package
    24: Magic (Current version 6.3)
    25: PSpice
    26: Esim
    27: Isplice3 (Current version 2.0)
    28: Watand
    29: Caltech VLSI CAD Tools
    30: Switcap2 (Current version 1.1)
    31: Test Software based on Abramovici text
    32: Atlanta and Soprano automatic test generators
    33: Olympus Synthesis System
    34: OASIS logic synthesis
    35: CAzM, a Spice-like table-based analog circuit simulator
    36: Tanner Research Tools (Ledit and LVS) (Commercial Product)

  + : new item
  ! : changed
  ? : additional information for this subject would be appreciated.


1: Mosis Users' Group (MUG)

  (From the MUG newsletter)

  The MOSIS Users' Group (MUG) Newsletter is distributed only via elec-
  tronic means to about 1200 individuals throughout the world who have
  expressed an interest in VLSI systems design and specifically in using
  MOSIS, the Metal-Oxide Semiconductor Implementation Service, that fabri-
  cates integrated circuit prototypes inexpensively.

  We hope that you enjoy receiving this newsletter and find it useful.
  Comments and suggestions should be directed to the Editor along with any
  change in address.  If you prefer not to receive messages of this type,
  which will occur no more often than monthly, please contact the Editor.

          MUG Newsletter Editor
          Prof. Don Bouldin
          Electrical & Computer Engineering
          University of Tennessee
          Knoxville, TN 37996-2100
          Tel:  (615)-974-5444
          FAX:  (615)-974-5492
          Email:  bouldin@sun1.engr.utk.edu
          Compmail II:  D.Bouldin


  A variety of design files and CAD tools contributed by the members of the
  MOSIS Users' Group (MUG) are now available via anonymous ftp from
  "venera.isi.edu" (128.9.0.32) in directory "pub/mug".  The files "readme"
  and "index" should be retrieved first.  These files are provided "as is",
  but may prove very helpful to those using the MOSIS integrated circuit
  prototyping service.

2: Improved spice listing from magic.

  Hierarchical extractions with net names: ext2spice done by Andy Burstein
  <burstein@zabriskie.berkeley.edu>:

  This program will do hierarchial extraction using node names.  It sup-
  ports PS, PD, AS, and AD extraction as well.  It is available for ftp
  from ic.berkeley.edu in pub/spice3/ext2spice.tar.

  Poly and well resistance extraction: There are persistent rumors that
  people have this working, however, all I have seen is extracted poly
  resistor with each end shorted together, ie each end has the same node
  name/number.

  (This is the most annoying problem that I typically encounter daily.  If
  ANYONE knows a fix for this, please tell us! I wrote a real quick and
  dirty set of scripts/programs to edit the magic file.  It will break the
  poly contacts and relabel them.  This is a real hack, but all other solu-
  tions require modification of the magic code itself.  This procedure only
  works with an extractor that handles labeled nodes, i.e. ext2spice from
  above.  --WH)

  There is an upcoming release of Magic 6.45 that is supposed to have a
  greatly improved netlister.  Here is part of the annoucement:

  The AuE Magic release provides hierarchical SPICE and LSIM netlist
  extractors not available in previous Magic releases. Previously, a flat
  SPICE netlist could be obtained using a program called "ext2spice". AuE
  provides a hierarchical SPICE netlister which provides a robust set of
  SPICE parameters for every device, including transistor source/drain dif-
  fusion perimeters and areas. The extractor has also been modified to
  correctly account for the shared S/D regions on stacked devices.

  The AuE extractor supports LSIM netlists, an Hspice compatible netlist,
  and a SpiceIIG compatible netlist. The SpiceIIG format uses node numbers
  instead of node names. The AuE SPICE extractor also recognizes bipolar
  junction transistors (BJTs) in several configurations. The previous Magic
  netlist extractor does not recognize BJT devices in any form.

  A new capacitance rule has been added to the base Magic extractor to
  facilitate the extraction of accurate dielectric capacitances. The previ-
  ous verion of Magic did not handle coupling capacitances correctly and
  frequently inserted a substrate capacitor in addition to the correctly
  extracted coupling capacitor.

  The AuE Magic release also includes an updated and enhanced technology
  file.  Modifications include fixes to several MOSIS DRC rules which were
  previously improperly checked, modifications to the CIF writer to resolve
  software bugs, and updated capacitance and resistance values in the
  extraction sections of the tech file. Special extraction sections for
  more commonly used processes have also been added.

  For information on how to order this version of Magic send an E-mail
  request to magic@AuE.com or send your request in writing to the address
  given below. We will start filling orders in mid October.

3: Tips and tricks for magic (Version 6.3)

  Searching for nets:

  Yes, magic does actually let you search for node names.  Use :specialopen
  netlist.  Then click on the box underneath label, you will be prompted
  for the name of the label you want to search for.  Enter the name, and
  then press enter twice.  Click on show, and then find, magic will then
  highlight the net.

  Bulk node extraction:

  Problems with getting the bulk node to extract correctly?  Try labeling
  the well with the node name that it is connected to.

  Painting Wells:

  Supposedly :cif in magic will automatically paint in the wells correctly.
  However this is not always the case.  If you are using mosis 2u technol-
  ogy, and your wells are getting strange notches in them, you might try
  changing the grow 300 shrink 300 lines in your lambda=1.0(pwell) and
  lambda=1.0(nwell) cif sections of your tech file to grow 450 shrink 450.
  (Remember you can use :cif see CWN to see nwell, if :cifostyle is nwell,
  or :cif see CWP to see pwell if its pwell technology to preview what will
  be done with the well.  You may use :feedback clear to erase what it
  shows you.)

  Magic notes available from gatekeeper.dec.com (16.1.0.2):

  (Located in pub/DEC/magic)

  Magic note.1 - 9/14/90 - ANNOUNCEMENT:  Magic V6 is ready
  Magic note.2 - 9/19/90 - DOC:  Doc changes (fixed in releases after 9/20/90)
  Magic note.3 - 9/19/90 - GRAPHICS:  Mode problem (fixed 9/20/90)
  Magic note.4 - 9/19/90 - HPUX:  rindex macro for HPUX 7.0 and later
  Magic note.5 - 9/19/90 - GCC:  "gcc" with magic, one user's experience
  Magic note.6 - 9/19/90 - FTP:  Public FTP area for Magic notes
  Magic note.7 - 9/20/90 - RSIM:  Compiling rsim, one user's suggestions & hints
  Magic note.8 - 9/26/90 - GENERAL:  Magic tries to open bogus directories
  Magic note.9 - 9/26/90 - GRAPHICS:  Mods to X11Helper
  Magic note.10 - 10/5/90 - DOS:  Magic V4 for DOS and OS/2
  Magic note.11 - 10/11/90 - GENERAL:  reducing memory usage by 600k
  Magic note.12 - 12/19/90 - EXT2xxx:  fixes bogus resistances
  Magic note.13 - 12/19/90 - EXTRESIS:  fixed bug in resis that caused coredump.
  Magic note.14 - 12/19/90 - EXTRESIS:  new version of scmos.tech for extresis
  Magic note.15 - 12/19/90 - TECH:  documentation for contact line in tech file
  Magic note.16 - 12/19/90 - EXTRACT:  bug fix to transistor attributes
  Magic note.17 - 5/13/91 - CALMA:  Incorrect arrays in calma output
  Magic note.18 - 5/14/91 - CALMA:  Extension to calma input
  Magic note.19 - 6/28/91 - IRSIM:  Some .prm files for IRSIM
  Magic note.20 - 7/18/91 - EXTRESIS:  fixes for Magic's extresis command
  Magic note.21 - 2/7/92 - FAQ:  Frequently asked questions
  Magic note.22 - 11/6/91 - CALMA:  how to write a calma tape
  Magic note.23 - 11/4/91 - EXT2xxx:  fix for incorrect resistor extraction
  Magic note.24 - 11/8/91 - EXTRESIS:  fix 0-ohm resistors
  Magic note.25 - 11/15/91 - NEXT:  porting magic to the NeXT machine
  Magic note.26 - 11/21/91 - IRSIM:  fix for hanging :decay command
  Magic note.27 - 12/17/91 - RESIS:  fix for "Attempt to remove node ..." error
  Magic note.28 - 1/28/92 - MAGIC:  anonymous FTP now available
  Magic note.29 - 3/27/92 - PLOT:  support for Versatec 2700
  Magic note.30 - 4/8/92 - PATHS:  Have the ":source" command follow a path
  Magic note.31 - 4/10/92 - MPACK:  Mpack now works with Magic 6.3
  Magic note.32 - 3/13/92 - AED:  Using AED displays with Magic 6.3
  Magic note.33 - 3/13/92 - OPENWINDOWS:  Compilation for OpenWindows/X11
  Magic note.34 - 2/14/92 - OPENWINDOWS:  fix mouse problem


4: What can I use to do good plots from magic/CIF?

  (Thanks to Douglas Yarrington <arri@ee.eng.ohio-state.edu> and Harry
  Langenbacher <harry@neuronz.Jpl.Nasa.Gov>, for feedback here.)

  CIF:

  CIF stands for CalTech Intermediate Form. It's a graphics language which
  can be used to describe integrated circuit layouts.

  cif2ps  version 2 (Gordon W. Ross, MITRE):

  A much better version of cif2ps, extending the code of cif2ps (Marc
  Lesure, Arizona State University) and cifp (Arthur Simoneau, Aerospace
  Corp).  It features command line options for depth and formatting.  Can
  extend one plot over several pages (up to 5 by 5, or 25 pages). By
  default, uses a mixture of postscript gray fill and cross-hatching.
  Options include rotating the image, selecting the hierarchy depth to
  plot, and plotting style customization.  Plots are in B/W only.

  It was posted to comp.sources.misc, and is available by ftp from
  uunet.uu.net(192.48.96.2) as: comp.sources.misc/volume8/cif2ps.Z.

  cifplot:

  Cifplot plots CIF format files on a screen, printer or plotter.  Cifplot
  reads the .cif file, generates a b/w or color raster dump, and sends it
  to the printer.  Plots can be scaled, clipped, or rotated.  Hierarchy
  depth is selectable, as well as the choice of colormap or fill pattern.
  An option exists which will compress raster data to reduce the required
  disk space.  For those plotting to a Versatec plotter, there is also a
  printer filter/driver available called vdmp.

  cifplot (m2c version, from chiang@m2c.org <Rit Chiang>):

  The cifplot program from M2C is not in public domain.  However, we do
  provide P.D. CAD tools to university for a fee of $2500/year to cover our
  cost on distribution, telephone hotline support, documentation and
  tutorials, etc., under our CUME (Clearinghouse for Undergraduate
  Microelectronics Education) program.  This program, in the past, was sub-
  sidized by NSF.

  The cifplot program was modified by M2C to support plotting for B&W
  PostScript and color PostScript printers, besides the versatec plotters.
  We also provide plotting services for people who sent us a cif file.  The
  cost is $20/per 24" color versatec plot for University and $50 for oth-
  ers.

  For more information on the CUME program or the plotting service, please
  send e-mail to hotline@m2c.org.

  oct2ps (available as part of the octtools distribution):

  It is possible to convert your .mag file to octtools, and then you may
  use oct2ps to print it.

  Both cif2ps and oct2ps work well for conversion to postscript.  They do
  look slightly different, so pick your favorite.  Note that cif2ps can be
  converted to adobe encapsulated postscript easily by adding a bounding
  box comment.  oct2ps does convert to color postscript, which can be a
  plus for those of you with color postscript printers.

  Flea:

  Flea ([F]un [L]oveable [E]ngineering [A]rtist) is a program used to plot
  magic and cif design files to various output devices. Parameters are
  passed to flea through the flags and flag data or through .flearc files
  and tech files.  Supports: HP7580 plotter, HP7550 hpgl file output,
  HP7550 plotter lpr output, Postscript file output, Laser Writer lpr out-
  put, Versatec versaplot random output.  Options include: Does line draw-
  ings with crosshatching for postscript, versatec, and hp plotters.  Many
  options (depth, label depth, scale, path, format...)

  Available by ftp from zeus.ee.msstate.edu in pub/flea.tar.Z.

  pplot:

  Can output color PostScript from CIF files. The source is available from:
  tesla.ee.cornell.edu in /pub/cad/pplot.tar.Z. It only generates PS files
  (including color PS), and there's no support for EPS files.  It is lim-
  ited in its support of cif commands.  (Wire, roundflash, and delete are
  not supported.)  It only supports manhattan geometry (Polygons and rota-
  tions may only be in 90 degree multiples.)

  vic:

  Part of the U. of Washington's Northwest Lab, for Integrated Systems Cad
  Tool Release (previously UW/NW VLSI Consortium).  Does postscript and HP
  pen plotters.  Only available as part of the package.

  CIF/Magic -> EPS -> groff/latex

  Currently no prgram here directly generates EPS files.  It is possible to
  add an EPS bounding box (%% BoundingBox: l t b r) to the output from
  these programs to get an EPS file.  Alternatively, ps2eps or ps2epsf may
  be used.

5: What tools are used to layout verification?

  Gemini:

  This is an excellent program that was done by Carl Ebeling.  There is a
  new version that is currently in beta.  This version supports serveral
  different netlist formats.  Devices with any number of terminals are sup-
  ported.  (This could be suitable for use at digital block level LVS, for
  example.)  LVS of mosfet w/l and capacitor values is supported as well.

  Contact:

          Carl Ebeling
          Computer Science Department, FR-35
          University of Washington
          Seattle, WA  98195
          ebeling@cs.washington.edu


  Tanner LVS:

  This is a relatively inexpensive commercial product, see the section on
  Tanner tools.

  Wellchecker:

  (from MUG) ftp venera.isi.edu (128.9.0.32)

  netcmp:

  Part of the caltech tools (see the "Caltech VLSI CAD Tools" section)

6: How are people doing netlist conversion and what about EDIF?

  (From Nigel Whitaker <nigelw@computer-science.manchester.ac.uk>)

  The following are published by the Electronic Industries Association:
  The EDIF Version 2 0 0 Reference Guide (ISBN 0 -7908-0000-4)
  EIA-1 -- Introduction to EDIF (User Guide)
  EIA-2 EDIF Connectivity (User Guide)
  Using EDIF 2 0 0 for Schematic Transfer (TSC Application Note EDIF/P-1)

  and are available from:

  Electronic Industries Association
  Standard Sales Department (Attn: Cecelia Fleming)
  2001 Pennsylvania Avenue, N.W.
  Washington D.C. 20006, USA

  and

  American Technical Publishers
  27--29 Knowl Piece, Wilbury Way, Hitchin, Hertfordshire, SG4 0SX, UK
  Tel: +44 462 437933


  The University of Manchester publish a set of `Questions and Answers'.
  These are user's technical questions about EDIF answered by the EDIF
  technical committee.  There are currently 5 volumes.

  There is also a University of Manchester Technical Report which presents
  a description of the semantics of EDIF Version 2 0 0.  This includes an
  Information Model of part of EDIF Version 2 0 0 written in EXPRESS.  The
  title of this report (UMCS-6-91) is `Proposal for an Information Model
  for EDIF', by Rachel Lau.

  The Questions and Answers and the technical report are available from:
  Julie Spink
  EDIF Technical Advisory Centre, Depeartment of Computer Science
  University of Manchester, Manchester, M13 9PL, UK
  Tel: +44 61 275 6289, FAX: +44 61 275 6280, e-mail: edif-support@cs.man.ac.uk


  EDIF Version 2 0 101 was announced at the Design Automation Conference
  (DAC) on 8th June 1992.  It is a draft for Version 2 1 0 which is due out
  in September 1992 and will be the version that is officially balloted as
  an EIA standard.  From June 8th the BNF for Version 2 0 101 (as well as a
  syntax checker / parser, test files and other EDIF related sources /
  information) will be available for anonymous ftp from edif.cs.man.ac.uk
  (130.88.229.234) in subdirectories of /pub/edif, it includes:

          Version 2 0 101 BNF
          Version 2 0 0 BNF
          Example EDIF files.
          A table driven 2 0 101 Parser/Syntax checker.
          Information about conferences/workshops and EDIF related documents.


  New files are being added, as we have time.  If you have any suggestions
  for things which we should put up for FTP, please email us.

  We also need people to contribute example EDIF files, which can be made
  publically available, to our collection, again please email us.

  (email address is:  edif-support@cs.man.ac.uk)

7: What layout examples are available?

  From MUG:

  Analog neural network library of cells, 66-bit Manchester carry-skip
  adder, static ram fabricated at 2-micron, an analog op amp, ftp
  venera.isi.edu (128.9.0.32) Located in pub/mug.

8: How can I get my lsi design fabbed and how much will it cost?

  (From Mosis) Information is available from mosis for pricing and fab
  schedules through an automatic email system:

  Mail to mosis@mosis.edu with the message body as follows:

          REQUEST: INFORMATION
          TOPIC: TOPICS
          REQUEST: END


  for general information and a list of available topics.

  If you need to contact a person at mosis, you may mail to mosis@mosis.edu
  with REQUEST: ATTENTION.

  (From chiang@m2c.org <Rit Chiang>) M2C can also provide low-cost, low-
  volume prototyping fab services.  The current technology available to the
  public is the  2um NWell single-poly double-metal process.

  For pricing information and fab schedule, please send e-mail to
  hotline@m2c.org.

  (Contributed by Don Bouldin of the University of Tennessee)

  Recently, I contacted several foundries to determine  which  com- panies
  are  interested  in fabricating small to moderate lots of wafers for cus-
  tom CMOS designs.  I believe many of the readers of this  column are
  designers who wish to have fabricated only 1,000 to 20,000 parts per
  year.  There are currently several  prototyp- ing  services  (e.g. MOSIS
  and Orbit) that can produce fewer than 100 parts for about $100 each and
  there are  also  several  foun- dries  which  are willing to produce
  100,000 custom parts for $5- $20 each (depending on the die size and
  yield).  My  purpose  was to  identify  those companies filling the large
  gap between these two services.

  The prices in the table below are a result of averaging the  data sup-
  plied by four foundries.  The raw data varied by more than +/- 40% so the
  information should be used only in the early stages of budgetary  plan-
  ning.   Once  the design specifications are fairly well known, the
  designer should contact one or more foundries  to obtain  specific
  budgetary  quotes.  As the design nears comple- tion, binding quotes can
  then be obtained.

  The following assumptions were made by the foundries:

  All designs will require custom CMOS wafer  fabrication  using  a
  double-metal, single-poly process with a feature size between 2.0 and 1.2
  microns.  The designs may contain some  analog  circuitry and  some  RAM
  so the yield has been calculated pessimistically.  The dies will be pack-
  aged and tested at 1  MHz  using  a  Sentry- type digital tester for 5-10
  seconds per part.  The customer will furnish the test vectors.

          Piece Price includes Wafer Fabrication+Die Packaging+Part Testing
          Size        Package                      Quantity

                                 |1,000 | 5,000 | 10,000 | 20,000  |100,000
          -----------------------------------------------------------------
          2 mm x 2 mm; 84 PLCC:  | $ 27 | $  6  |  $  5  |  $  4   | $  3 |
          5 mm x 5 mm; 84 PLCC:  | $ 31 | $ 12  |  $  8  |  $  7   | $  6 |
          5 mm x 5 mm; 132 PGA:  | $ 49 | $ 30  |  $ 25  |  $ 22   | $ 18 |
          7 mm x 7 mm; 132 PGA:  | $ 65 | $ 44  |  $ 36  |  $ 31   | $ 27 |

          Lithography charges:  $ 20,000 - $ 40,000
          Preferred Formats:  GDS-II or  CIF Tapes
          Additional charges for Second-Poly:  $ 5,000


  (This is from MUG 19, there is also a list of foundries that these prices
  were derived from.  In the interested of saving space, I have ommitted
  the list.  The list is available from MUG's ftp site included in MUG
  newsletter #19.)

9: Archive sites for comp.lsi.cad and comp.lsi

  (None of these are comprehensive archives, rather, they have about 3
  postings each)

  comp.lsi.cad:
  cnam.cnam.fr in /pub/Archives/comp.archives/auto/comp.lsi.cad
  cs.dal.ca in /pub/comp.archives/comp.lsi.cad
  srawgw.sra.co.jp in /.a/sranha-bp/arch/arch/comp.archives/auto/comp.lsi.cad


10: Other newsgroups that relate to comp.lsi*

  alt.cad
  comp.cad.cadence
  comp.lang.verilog
  comp.lang.vhdl
  comp.sys.mentor
  sci.electronics


11: Simulation programs tips/tricks/bugs

  Berkeley spice:

  Pspice:

  Hspice:

  If your simulation won't converge for a given DC input, you can ramp the
  input and print the DC operating point and then set the nodes that way
  for future simulations.

12: Getting the latest version of the FAQ:

  Mail to clcfaq@eecs.ucdavis.edu with the subject "send faq".

13: Converting from/to GDSII/CIF/Magic

  Magic version 6.3 is capable of reading and writting to all three for-
  mats.  (From the magic man page):

  calma [option] [args]

  This command is used to read and write files in Calma GDS II Stream for-
  mat (version 3.0, corresponding to GDS II Release 5.1).  This format is
  like CIF, in that it describes physical mask layers instead of Magic
  layers.  In fact, the technology file specifies a correspondence between
  CIF and Calma layers.  The current CIF out- put style (see cif ostyle)
  controls how Calma stream layers are generated from Magic layers.

  cif [option] [args]

  Read or write files in Caltech Intermediate Form (CIF).

14: CFI (CAD Framework Initiative Inc.)

  (From Randy Kirchhof <rkk@cfi.org>)

  For those of you who may be unfamiliar with our work, The CAD Framework
  Initiative Inc. was formed in May 1988. We're located in Austin, TX,
  although we're a distributed company. We're a  not-for- profit consortium
  formed under the laws of the state of Delaware.  Our charter is to gain
  consensus from industry users, the academic community, and vendors, to
  develop guidelines for an industry acceptable CAD framework implementa-
  tion.

  A CAD framework is a software infrastructure which provides a common
  operating environment for CAD tools.  Through a framework, a user should
  be able to launch and manage tools, create, organize, and manage data,
  graphically view the entire design process and perform design management
  tasks such as configuration management, version management, etc.

  CFI is well into the final stages prior to release 1.0. We recently
  returned from the DAC convention in Anaheim, where there was an extraor-
  dinary amount of interest shown in our Pilot project demonstrations. We
  were able to demonstrate robust, working CFI-compliant software from a
  large number of member companies.  Cooperation in our ongoing effort has
  been very good from our outset.

  Also, please be aware that CFI has virtually all of our working documents
  online, available via anonymous FTP to cfi.org. (192.138.153.1) There is
  also an e-mailserver. Send an empty message to cfi-server@cfi.org. The
  mail server & FTP use the same directory.

  CFI Release 1.0 is on schedule, up for final ballot in October and will
  be formally released in December of this year. Many vendors will ini-
  tially release CFI compliant software as early as 2Q 1993.

15: What free tools are there available, and what can they do?

  (This section can be viewed as a cross reference to the detailed descrip-
  tion of software that follows.)

    Analog VLSI and Neural Systems: Caltech VLSI CAD Tools

    Automated place and route: octtools, Lager

    Lsi (polygon) schematic capture: magic, octtools(vem)

    Layout Verification: caltech tools (netcmp), gemini (Washington
    Univerity), wellchk (MUG)

    PCB auto/manual place and route: PADS pcb, PCB (Just for testing lsi
    designs, of course :)

    Simulation: irsim(comes with magic), esim, pspice, isplice3, watand,
    switcap2

    Synthisis: octtools, bliss, Lager, item

    Standard schematic capture: PADS logic, PSPICE for windows



16: What Berkeley Tools are available for anonymous ftp?

  available from ic.berkeley.edu: (pub)

  adore: switched capacitor layout generator

  bdd:

  blis:

  road: analog layout router

  sis: includes many tools including espresso, bdd

  ext2spice: enhanced ext2spice for use with magic

  available from gatekeeper.dec.com: (pub/misc)

  espresso:

17: Berkeley Spice (Current version 3e2)

  (From spice_info on ic.berkeley.edu)

  Berkeley Spice this is no longer freely distributable.  (This includes
  even old versions of spice3.)  Documentation is available on
  ic.berkeley.edu.  General information is available from
  "spice@berkeley.edu".  For more information on how to acquire Spice,
  please send your physical mailing address to "software@diva.berkeley.edu"
  or "software@eecs.berkeley.edu" and request a software catalog.  This
  will give you all of the necessary information for ordering Spice3e2 and
  other Berkeley CAD software, including an order form and use agreements.
  At last check, the cost for spice3e2 was $250.00 (this price may change
  without notice).

  Spice3e2 has been compiled on the following systems:
          DECstation/VAXstation/VAX       Ultrix 4.x      X11r4
          Sun3/Sun4                       SunOS 4.x       X11r4
          IBM RS/6000                     AIX V3          X11r3
          SGI Personal Iris               Irix 3.2
          Sequent Symmetry or Balance     Dynix 3.0       X11r4
          HP 9000/300                     HP-UX 7.0
          NextStation                     Next 2.0
          IBM PC (or compatible)          MS-DOS 3.x/Microsoft C 5.1 or later


  Spice3e2 is distributed in source form only.  The C compiler "gcc" has
  been used successfully to compile spice3e2, as well as the standard com-
  pilers for the systems listed above.  Note the the X11 interface to
  Spice3 requires the "Athena Widgets Toolkit" ("Xaw") which may be avail-
  able only in the "unsupported" portion of your vendor software.  Spice3
  displays graphs under X11, PostScript, or a graphics-terminal independent
  library, or as a crude, spice2-like line-printer plot.  On the IBM PC,
  CGA, EGA, and VGA displays are supported through the MicroSoft graphics
  library.  Note in particular that there is no Suntools interface.

  Note that for practical performance a math co-processor is required for
  an IBM PC based on the 286 processor.  A math co-processor is also recom-
  mended for the more advanced IBM PC systems.

  The Unix distribution comes on 1/2" 9-track tape in "tar" format.  The
  MS-DOS distribution comes on several 3.5" floppy diskettes (both high and
  low density) in the standard MS-DOS format.  The contents of both distri-
  butions are identical, including file names.

  Spice versions are numbered "NXM", where "N" is a number representing the
  major release (as in re-write), "X" is a letter representing a feature
  change reflected by a change in the documentation, and "M" is a number
  indicating a minor revision or bug-patch number.

  We anticipate that FUTURE distributions will also come on QIC-150 1/4"
  (a.k.a. "Sun cartridge tape" high density or 150MB 1/4" tape), and a
  compressed tar files on two 3.5" diskettes for Sun or VAX systems with
  3.5" drives.  * Note that these future formats are anticipated but not
  guaranteed and do NOT apply for Spice3e2 *.

  There is no anonymous ftp access for the Spice3 source.  The manual for
  spice3e2 (in it's troff/me format or postscript format) is available via
  anonymous ftp from "ic.berkeley.edu" in the directory "pub/spice3".
  Patches or upgrades for Spice3 are _not_ normally supplied, however we
  have made exceptions to this rule.

                  Beorn Johnson
                  Spice maintenance
                  UC Berkeley, EECS/ERL/CAD Group
                  (beorn@ic.berkeley.edu)


  Please direct inquiries to "spice@berkeley.edu" or "spice-
  bugs@berkeley.edu"

18: Octtools (Current version 5.1)

  (From the ANNOUNCE-5.1 that comes with it)

  Octtools is a collection of programs and libraries that form an
  integrated system for IC design.  The system includes tools for PLA and
  multiple-level logic synthesis, state assignment, standard-cell, gate-
  matrix and macro-cell placement and routing, custom-cell design, circuit,
  switch and logic-level simulation, and a variety of utility programs for
  manipulating schematic, symbolic, and geometric design data.  Most tools
  are integrated with the Oct data manager and the VEM user interface.

  The software requires UNIX, the window system X11R4 including the Athena
  Widget Set. The design manager VOV and a few other tools require the C++
  compiler g++.

  Octtools-5.1 have been built and tested on the following combinations of
  machines and operating systems: DECstation 3100, 5000 running Ultrix 4.1
  and 4.2; DEC VAX running Ultrix 4.1 and 4.2; Sun 3 and 4 running OS 4.0
  and Sun SparcStation running OS 4.0.  The program has been tried on the
  following machines, but is not supported: Sequent Symmetry, IBM RS/6000
  running AIX 3.1.

  To obtain a copy of Octtools 5.1 (8mm, tk50, or 1/4inch cartridge QIC150)
  and a printed copy of the documentation) for a $250 distribution charge,
  contact:

                      Industrial Liason Program Software Distribution
                      Department of Electrical Engineering and Computer Sciences
                      457 Cory Hall
                      University of California, Berkeley
                      Berkeley, CA, 94720

                      Email: ilpsoft@janus.berkeley.edu
                      Phone: (510) 643-6687


19: Lager (Current version 4.0):

  (From MUG 18)

  The LAGER system is a set of CAD tools for performing parameterized VLSI
  design with a slant towards DSP applications (but not limited to DSP
  applications).  A standard cell library, datapath library, several module
  generators and several pad libraries comprise the cell library.  These
  tools and libraries have originated from UC Berkeley, UCLA, USC, Missis-
  sippi State, and ITD.  The tool development has been funded by DARPA
  under the Rapid Prototyping Contract headed by Bob Brodersen (UC Berke-
  ley).  LAGER 3.0 was described in MUG 15.

  Send email to reese@erc.msstate.edu if you are interested in obtaining
  the toolset via FTP. If you cannot get the distribution via ftp then send
  one 1/4" 600 ft. tape OR an 8 mm tape (Exabyte compatible) to Bob Reese
  by phone at (601)-325-3670 or at one of the following addresses:

          (US Mail Address)
          P.O. Box 6176
          Mississippi State, MS 39762

          (FEDEX)
          2 Research Boulevard
          Starkville, MS 39759


  Be sure to include a return FEDEX waybill we can use to ship your tape
  back to you. Instead of sending a tape and FEDX waybill, you can also
  just send us a check for $75 and we will send you back a tape.  Make the
  check payable to Mississippi State Univ.  The tape will be written on a
  high density tape drive (150 Mb).  Older low density SUN tape drives (60
  Mb) cannot read this format so you need to have access to one of SUN's
  newer tape drives.

20: BLIS (Current version 2.0):

  (From their announcement posted here)

  BLIS (Behavior-to-Logic Interactive Synthesis) is an environment for the
  synthesis of digital circuits from high-level descriptions.  Version 2.0
  supports functional-level synthesis starting from the ELLA hardware
  description language.  Other languages can easily be supported by inter-
  facing a parser to the internal data-flow representation of BLIS.

  BLIS is distributed through the Industrial Liason's Program (ILP) Office
  of the UCB EECS department.  The cost of $250 covers media and distribu-
  tion charges.  Binaries are provided for SUN4 and DEC MIPS architectures
  but BLIS should compile on most other machines supported by the GNU C and
  C++ compilers (e.g. HP, vax, etc).  ELLA language documentation and simu-
  lator are not supplied with the BLIS distribution, but can be obtained
  from Computer General.

  Ordering information can be obtained from:

          Cindy Manly-Fields
          EECS/ILP Software Distribution
          479 Cory Hall
          University of California
          Berkeley, CA  94720
          Telephone: (510) 643-6687
          Electronic Mail Address: cindy@hera.Berkeley.edu


21: ITEM

  (Taken from the item.news file contained in the package:)


  The first public release of ITEM, UCSC's logic minimizer using if-then-
  else DAGs, was made 2 January 1991.  The system is available by anonymous
  ftp from ftp.cse.ucsc.edu, in directory pub/item as a compressed tar
  archive (item.tar.Z).  Also available are tech reports about the algo-
  rithms and data structures (88-28, 88-29, and 90-43).

  ITEM can also be found at ftp.cse.ucsc.edu in the pub/item directory.

22: PADS logic/PADS PCB:

  While this is a commercial product, they have just recently made avail-
  able a shareware version.  This version is fully functional and indenti-
  cal to their schematic capture and PCB autoplace and route software
  except that it is limited to about 50 components.  It is available for
  IBM PC/PC compatibles directly from PADS, or from anynonmous ftp at
  several sites including wuarchive.wustl.edu in
  /mirrors/msdos/cad/pads*.zip.  There is a $50 registration fee if you
  would like to get future updates from them.

23: Another PCB Layout Package:

  (from Randy Nevin <randyn@microsoft.com>:)

  I'm distributing a freely-copyable software package to do autorouting of
  (1- and 2-layer) printed circuit boards on a PC or compatible. It is
  written in C (with a little .asm), and all source code is included. There
  is an autorouter, a board viewer, a rat nest viewer, and some output
  filters which generate postscript and hp laserjet output files. There is
  no charge, but I maintain the copyright (it is not public domain). If you
  want to read about it, I published an article on autorouting algorithms
  in the sept '89 dr. dobb's journal. ega is required (for the viewing pro-
  grams). If you'd like to get the software, send me a stamped, self-
  addressed floppy mailer and a floppy. I can handle 5.25" 360K or 1.2M, or
  3.5" 1.4M, but if you send 360K there is some extra code that I won't be
  able to fit on the disk, so high density is better.

  I developed this software at home on my own time, and it is not related
  to what I do for my employer, so I will not use my employer's email
  resource to distribute it. however, it is available for anonymous ftp
  access on wsmr-simtel20.army.mil in PD1:<MSDOS.CAD>PCB.ARC, last I heard.
  I do not keep simtel up to date. But the version there is useable, and
  does include all source code.

          Randy Nevin
          24135 SE 16th PL
          Issaquah, WA 98027


24: Magic (Current version 6.3):

  This is a polygon based lsi layout editor.  It is capable of reading and
  writing magic, calma (version 3.0, corresponding to GDS II Release 5.1),
  and cif.  It is available for anonymous ftp from gatekeeper.dec.com in
  /pub/DEC/magic.

25: PSpice:

  This is a commercial product, however, they do have a student version
  that is available (limited to around 16 transistors).

          PC dos version: 5c wuarchive.wustl.edu in
                          /mirrors/msdos/education/pspice5c.zip
          PC windows3 version 5.1: WSMR-SIMTEL20.Army.Mil in
                          pd1:<msdos.windows3>
                          called PSPIC51A.ZIP and PSPIC51B.ZIP
          Mac version 5.1: wuarchive.wustl.edu in
                          /mirrors/info-mac/app/pspice-51.hqx


26: Esim:

  A new version of the switch-level simulator ESIM that can handle CMOS
  transmission gates is available through MUG, ftp venera.isi.edu
  (128.9.0.32))

27: Isplice3 (Current version 2.0):

  This is a high level simulator, I do not know much more then that.  It is
  available via anonymous ftp from uicadb.csl.uiuc.edu.

28: Watand:

  (From Phil Munro's posting <FC138001@ysub.ysu.edu>)

  Spice is not the only circuit simulator available.  There is one called
  WATAND (WATerloo ANalysis and Design) which runs on a mainframe (and some
  other workstations).  We use it here under CMS on our mainframe computer.

  Unlike Spice and its derivatives, Watand is a fully *interactive* pro-
  gram; that is, one enters an environment where analyses can be run and
  rerun, values changed and queried, options changed, and even different
  circuits can be run, all without leaving the environment.

     "WATAND Users Manual", by Dr. Phil Munro, April 1992, 233 pages,
     unbound, $7.00 plus whatever shipping charges the bookstore might ask
     of you.

     "WATAND Introduction and Examples", by Dr. P. Munro, September 1991,
     160 pages, spiral bound, incomplete edition Chapters 1 - 10.  The cost
     is $4 or $5, I think, plus shipping.

               You should write to Youngstown State University Bookstore
                               Youngstown, Ohio 44555


  Watand itself is available from Mark O'Leavey, Waterloo Engineering
  Software, 22 King St. S., Suite 302, Waterloo, Ontario, CANADA, N2L 1C6.
  Fax: (519) 746-7931 Phone: (519) 741-8097. It's currently only available
  for DECStation and Sparcstation.

29: Caltech VLSI CAD Tools:

  (From John Lazzaro <lazzaro@boom.CS.Berkeley.EDU>)

                     Caltech VLSI CAD Tool Distribution


  We are offering to the Internet community a pre-release version of the
  Caltech electronic CAD system for analog VLSI neural networks.  This dis-
  tribution contains tools for schematic capture, netlist creation, and
  analog and digital simulation (log), IC mask layout, extraction, and DRC
  (wol), simple chip compilation (wolcomp), MOSIS fabrication request gen-
  eration (mosis), netlist comparison (netcmp), data plotting (view) and
  postscript graphics editing (until). These tools were used exclusively
  for the design and test of all the integrated circuits described in
  Carver Mead's book "Analog VLSI and Neural Systems".  Until was used as
  the primary tool for figure creation for the book.  The distribution also
  contains an example of an analog VLSI chip that was designed and fabri-
  cated with these tools, and an example of an Actel field-programmable
  gate array design that was simulated and converted to Actel format with
  these tools.

  These tools are distributed under a license very similar to the GNU
  license; the minor changes protect Caltech from liability.

  To use these tools, you need:

  1) A unix workstation that runs X11r3, X11r4, or Openwindows

  2) A color screen

  3) Gcc or other ANSI-standard compiler

  Right now only Sun Sparcstations are officially supported, although
  resourceful users have the tools running on Sun 3, HP Series 300, and
  Decstations.  If don't have a Sparcstation or an HP 300, only take the
  package if you feel confident in your C/Unix abilities to do the porting
  required; someday soon we will integrate the changes back into the
  sources officially, although many "ifdef mips" are already in the code.

  If you are interested in some or all of these tools,

  1) ftp to hobiecat.cs.caltech.edu on the Internet,

  2) log in as anonymous and use your username as the password

  3) cd ~ftp/pub/chipmunk

  4) copy the file README, that contains more information.

  European researchers can access these files through anonymous ftp using
  the machine ifi.uio.no in Norway; the files are in the directory chip-
  munk.  We are unable to help users who do not have Internet ftp access.

30: Switcap2 (Current version 1.1):

  This is a switched capactor simulator.  It is available from:

                  SWITCAP Distribution centre,
                  411 Low Memorial Library,
                  New York,
                  N.Y. 10027.


31: Test Software for Abramovici Text:

  (Contributed by Mel Breuer of the Univ. of Southern California)

  Many faculty are using the text by Abramovici, Breuer, and Fried- man
  entitled  "Digital Systems Testing and Testable Design" in a class on
  testing.  They have expressed an interest to  supplement their  course
  with software tools.  At USC we have developed such a suite of tools.
  They include a  good  value  simulator,  fault simulator,  fault  col-
  lapsing  module, and D-algorithm-based ATPG module for combinational
  logic.  The software has  been  specifi- cally  designed  to  be easily
  understood, modified and enhanced.  The algorithms follow those described
  in the text.  The  software can  be  run  in many modes, such as one
  module at a time, single step, interactively or as a batch process.  Stu-
  dents can use  the software  "as  is"  to  study  the operation of the
  various algo- rithms, e.g. simulation of a latch using different delay
  models.  Also,  simple  programming  projects can be given, such as
  extend the simulator from a 3-valued system to  a  5-valued  system;  or
  change  the D-algorithm so that it only does single path sensiti- zation.
  There  are  literally  over  50  interesting   software enhancements
  that  can  be made by changing only a small part of the code.  The system
  is written in C and runs on a SUN.

  If you are currently using the Abramovici text and would  like  a copy
  of  this  software,  please  send a message to Prof. Melvin Breuer at
  mb@poisson.usc.edu.

32: Test Generation and Fault Simulation Software

  (Contributed by Dr. Dong Ha of Virginia Tech)

  Two automatic test pattern generators (ATPGs) and a fault simula- tor
  for  combinational circuits were developed at Virginia Tech, and the
  source codes of  the  tools  are  now  ready  for  public release.
  ATLANTA is an ATPG for stuck-at faults.  It is based on the FAN algorithm
  and a parallel-pattern,  single-fault  propaga- tion  technique.   It
  consists of optional sessions using random pattern testing, deterministic
  test pattern generation  and  test compaction.  SOPRANO is an ATPG for
  stuck-open faults.  The algo- rithm of SOPRANO is similar to  ATLANTA
  except  two  consecutive patterns  are  applied  to  detect a stuck-open
  fault.  FSIM is a parallel-pattern, single-fault  simulator.   All  the
  tools  are written  in  C.  The source codes are fully commented, and
  README files contain user's manuals.  Technical papers about  the  tools
  were  presented at DAC-90 and ITC-91. All three tools are free to univer-
  sities.  Companies are requested to make a contribution  of $5000  but
  will have free technical assistance.  For detailed in- formation, con-
  tact:

             Dr. Dong Ha
             Electrical Engineering
             Virginia Tech
             Blacksburg, VA 24061
             TEL: 703-231-4942
             FAX: 703-231-3362
             dsha@vtvm1.cc.vt.edu


33: Olympus Synthesis System

  (From Rajesh K. Gupta <rgupta@sirius.Stanford.EDU>)

  Recently there have been several enquiries about the Olympus Synthesis
  System. Here are answers to some commonly asked questions. For details
  please send mail to "synthesis@chronos.stanford.edu".

  1. What is Olympus Synthesis System?

  Olympus is a result of a continuing project on synthesis of digital cir-
  cuits here at Stanford University. Currently, Olympus synthesis system
  consists of a set of programs that perform synthesis tasks for synchro-
  nous, non-pipelined circuits starting from a description in a hardware
  description language, HardwareC.

  The output of synthesis is a technology independent netlist of gates.
  This netlist can be input to logic synthesis and technology mapping tools
  within Olympus or to UC Berkeley's mis/sis. Current technology mapping in
  Olympus is targeted for LSI logic standard cells and a set of PGA archi-
  tectures: Actel and Xilinx.

  2. How is Olympus distributed?

  The source code and documentation for Olympus is distributed via ftp.

  3. What are the system requirements for Olympus?

  Olympus has been tested on following hardware platforms: mips, sparc,
  hp9000s300, hp9000s800, hp9000s700, vax.  All the programs in Olympus
  come with a default menu-driven ASCII interface. There is also a graphi-
  cal user interface, called "olympus", provided with the distribution.
  This interface is written using Motif procedures.

  You would need about 40 MBytes of disk space to extract and compile the
  system.

  4. How can I obtain a copy of Olympus?

  Olympus is distributed free of charge by Stanford University.  However,
  it is not available via anonymous ftp. In order to obtain a copy please
  send a mail to "olympus@chronos.stanford.edu" where an automatic-reply
  mailer would send instructions for obtaining Olympus software.

34: OASIS logic synthesis

  (From William R. Richards Jr. <richards@mcnc.org>)

  OASIS is a complete logic synthesis system based on the Logic3 HDL
  develped at MCNC (unfortunately neither VHDL or Verilog compatible).
  kk@mcnc.org is the person responsible for it. OASIS is available to US
  universities for $500 and non-US universities for $600. Industrial
  license is $3000.

35: CAzM, a Spice-like table-based analog circuit simulator

  (From William R. Richards Jr. <richards@mcnc.org>)

  Second is CAzM, a Spice-like table-based analog circuit simulator. It
  offers significant performance advantages over other Berkeley Spice
  derivatives. It is used fairly extensively in our design community.  US
  university license is $175, non-US $250. Commercial license is $800. It
  comes with an X11- based signal viewing tool Sigview which is public
  domain and may be anonymous ftp'd from mcnc.org. I am the primary contact
  for CAzM at MCNC.

36: Tanner Research Tools (Ledit and LVS)

  (From Bhusan Gupta <bgupta@micro.caltech.edu>)

  There is a "low" cost tool from Tanner Research (Pasadena, Ca) called LVS
  that will compare two spice decks.  It is a pretty decent tool that is
  still evolving and is sortof flexible, but it can be a lifesaver if you
  have to compare spice decks. It is much much better than netcmp/netcomp
  (the caltech VLSI tools). I realize that this is a commercial tool for $,
  but the only reason I suggest it is that it isn't as expensive as a tool
  from Cadence for example.  (University pricing is around $245 for the PC
  version, and $995 for the commercial version.)

  Tanner also has a layout mask editor (polygon pusher) called Ledit which
  they sell for the PC, Sun, Hp, Mac. It has a DRC tool, extract to spice,
  a cross-section viewer, etc for additional money.  The cross-section
  viewer is fairly neat gadget in that given some of your design, it will
  show what the vertical cross-section looks like.  Demo versions may be
  available.
Newsgroups: comp.lsi.cad