Organisation: European Space Technology Centre (E.S.T.E.C)
Date: Thursday, 8 Oct 1992 14:40:36 CET
From: <PSINANDE@ESTEC.BITNET>
Newsgroups: comp.lang.vhdl
Subject: Re: info on VHDL simulators requested

> I would like to hear about the experiences of
> users of Model Technology VHDL simulator and
> those who use Mentor Graphics VHDL simulator.

I have been using and evaluating several VHDL tools for input, simulation
and synthesis. I'll summarize some of the simulator experiences.

To select a VHDL simulator, it is important to define the selection
criteria; these differ for every user. No single tool is the best choice
for everybody. Some criteria are simulation speed vs. analysis
speed, simulation speed for batch simulation vs. for simulation with
waveforms and debugging capabilities, working with RT or gate level models.
Synergy with other (existing) tools is important.

Our criteria are:
-  We will receive VHDL code from different sources; full VHDL and n
   language bugs are absolutely necessary
-  In our working environment, we have often to stop working with the tools
   for up to a couple of weeks. Therefore, ease-of-use is important.
-  We mainly create prototype code, and mostly simulate with debug + waves.
-  We don't simulate at the gate level, and can normally run longer
   simulations overnight.

An overview of some VHDL simulators, using the above criteria:

Mentor Quicksim plus System-1076:
I evaluated a Beta (in reality more like Alpha) release in 1990, on a
Apollo 4500. At that time, it was quite horrible, but I expect that it
has improved a lot since then. Full VHDL is still not supported, e.g.
RECORDs are missing, but Mentor has promised to have full VHDL 1993. I
assume that it will take a year or so before all bugs are out. I will
run our benchmark suite on a Sparc-based Mentor system in November.

Vantage:
I evaluated version 3.110 on a Sparc about one year ago. That version
had a bit awkward user interface, and sometimes crashed the station.
Vantage compiles VHDL to C, and then compiles the C and links it, which
gives long analysis times. This results in fast execution time, but the
difference is not so big when using debug and waveforms. Release 4.0
is said to have improved both analysis and simulation speed. Some language
bugs were found, in TextIO and in the elaboration, but this is
supposedly fixed in release 4. The waveform display was OK.

Synopsys VSS 2.2:
We have it since last year, and are quite happy with ease-of-use and
the debugger. The waveform display is barely acceptable, though, and I
really hope this will be improved in v 3.0 (1993). Synopsys are the
only one providing a make facility, which makes your life
easier when dealing with many design units. There is also a code
coverage utility. The Synopsys simulator is interpreting, which gives
very good analysis speed, but also reasonable simulation speed. We
have only found one (very trivial) bug so far.

Modelling Technology VSystem/SPARC 2.0Beta (NOT THE PC VERSION)
I tested this system last moth, and think it offers good value for the
money. VSystem is interpreting, and offers very good analysis speed
together with good simulation speed. It allows optimization for
1164 Standard_Logic, but is fast even without optimization. Nice
user interface and waveform display, and has a good debugger. Some
problems were found with the windowing interface, and it only runs
using OpenWindows 2 (crashes with MIT X). We found one language bug,
for ARRAY index calculation (unusual case though), but I assume
that it will be fixed.

I hope this info can be to some help.
Regards,

Peter Sinander           Fax: +31-1719-84295    email: psi@wd.estec.esa.nl
ESTEC WDN                European Space Agency Technology Centre

Newsgroups: comp.lang.vhdl,comp.lang.verilog