From: jjsmith@nyx.cs.du.edu (Jonathan J. Smith)
Subject: Re: cisc -vs- risc
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Date: Sat, 10 Oct 92 22:23:56 GMT

In article <smcgerty.718240429@unix1.tcd.ie> smcgerty@unix1.tcd.ie (Stephen John McGerty) writes:
>In <1992Oct3.1124.12923@channel1> jeff.ruck@channel1.com (jeff ruck) writes:
>
>>I'm not overly familiar with '040 performance, but here are a few facts:
>>Second-generation RISC processors (R3000, etc ...) *completed* one
>>instruction every 1.2-1.6 clock cycles.  The latest third-generation
>>RISC processors (R4000SC, Alpha, etc) *issue* as many as two
>>instructions per clock cycle and *complete* 1.2-1.3 instructions per
>>clock cycle via superpipelining or superscalar designs.  If an '040 can
>>*complete* an instruction in 1. clock cycles then I'm impressed.
>
Just for the record some like the super sparc and some of the i960 chips can do as many as 3 instructions per cycle.

>For the average to be 1.3 cycles per instruction, the effective
>through-put of some must be 1 cycle. Maths I reckon.
>
>In reality, every instruction goes through 6 stages: 
>instrution prefetch, decode, effective address calculation, 
>operand fetch, execution and writeback.
>The stages work concurrently, with dual prefetch circuits
>to cope with conditional branching (Both options covered).
>
>>> Er...I thought the fastest RISC chips actually executed *several*
>>> instructions per cycle?
>
>>Simply, superscalar designs initiate pipelines in parallel,
>>and superpipelining is pipelining several smaller pipelines.  This is
>>what allows the processors to *initiate* more than one instruction per
>>clock cycle.  Theorectically, completely 1 insturction per clock cycle
>>is ideal, but very difficult to implement.
>
completing more than one instruction per cycle is not actually that difficult 
to acheive,  NOW doing that _ALL_ the time is very difficult.
ONe is always going to run into data dependantcies and so on.
>In other words, there are two pipeline circuits, both able to execute 
>the whole instruction set? Assuming the two instructions don't
>rely on one another, two instructions are completed (effectively)
>in one cycle? Rather neat, if I take your meaning.  
>
this depends on the chip your talking about.  some like the 88110
do indeed have two completely seperate and identical integer pipelines
note the word integer.  so within the integer instruction set
as long as you have no data dependancies (like both asking for data
from the same register) you can execute any integer instructions
at the same tiem, with a few exceptions.

Others, such as the supersparc, have a much more stringent list of
rules that you must follow to have instruction executing at the same time
.  Often these will be more along the lines of a fetch, and integer instruction.
and a condition code check.

>>Jeff
>>jeff.ruck@channel1.com
>>--
>>Channel 1 (R)   Cambridge, MA
>
>Stephen.


Jonathan Smith.
Newsgroups: comp.sys.amiga.hardware