HDTenEightyP/NetNews huggingface dataset:
From: veit@du9ds3.uni-duisburg.de (Holger Veit)
Newsgroups: comp.lang.vhdl
Subject: Re: Random number generation in VHDL
Date: 12 Oct 92 07:47:28 GMT
Organization: Uni-Duisburg FB9 Datenverarbeitung
Reply-To: veit@du9ds3.uni-duisburg.de
NNTP-Posting-Host: du9ds3.uni-duisburg.de

In <1992Oct9.080434.16985@kum.kaist.ac.kr> jinsoo@snucom.snu.ac.kr (Jinsoo Kim) writes:


>Hi,

>  Is there any pre-built libraries that generate random numbers in VHDL?
>Or is there anyone who know the algorithm taht can be easily programmed
>in VHDL?  Any suggestion will be welcome.
>  Thanks in advance.

>  Best regards,

>	- Jinsoo Kim

>          Dept. of computer engineering,
>	  Seoul National University,
>          Phone:  (+82)-2-880-7299
>	  Fax:    (+82)-2-886-7589
>	  E-mail: jinsoo@snucom.snu.ac.kr

There is a random generator package by
G. Swaminathan which was posted some time ago.
It is available e.g. from ftp.uni-duisburg.de (134.91.4.132) in
/pub/cad/random.pkg.Z

Hope that helps

Holger

-- 
|  |   / Dr. Holger Veit         | INTERNET: veit@du9ds3.uni-duisburg.de
|__|  /  University of Duisburg  | "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
|  | /   Dept. of Electr. Eng.   |   Sorry, the above really good fortune has
|  |/    Inst. f. Dataprocessing |      been CENSORED because of obscenity"
Newsgroups: comp.lang.vhdl
From: jinsoo@snucom.snu.ac.kr (Jinsoo Kim)
Subject: Random number generation in VHDL
Organization: Dept. of Computer Engineering, SNU.
Date: Fri, 9 Oct 92 08:04:34 GMT


Hi,

  Is there any pre-built libraries that generate random numbers in VHDL?
Or is there anyone who know the algorithm taht can be easily programmed
in VHDL?  Any suggestion will be welcome.
  Thanks in advance.

  Best regards,

	- Jinsoo Kim

          Dept. of computer engineering,
	  Seoul National University,
          Phone:  (+82)-2-880-7299
	  Fax:    (+82)-2-886-7589
	  E-mail: jinsoo@snucom.snu.ac.kr
Newsgroups: comp.lang.verilog
From: ovi@netcom.com (OVI)
Subject: Looking for Verilog Success Stories
Organization: Netcom - Online Communication Services  (408 241-9760 guest) 
Distribution: na
Date: Wed, 14 Oct 1992 18:30:11 GMT

Open Verilog International is looking for Verilog success stories
to publish, promote and publicize.  We'd like to include your
quotes, comments and stories in future editions of the newsletter
or other promotional media.

- Tell us about your Verilog design successes
- Tell us what products were designed with Verilog
- Tell us about your company's success as a Verilog
  product and service supplier
- Tell us about your designs, products and design team and
  why you chose Verilog

Please send information and news about your Verilog HDL designs
and product successes to Open Verilog International,
Attn: OpenExchange/Success Stories or call Georgia Marszalek
at (415)345-7477 or send email to ovi@netcom.com.
From: hendrix@haber.Eng.Sun.COM
Newsgroups: comp.lang.verilog
Subject: Re: Does verilint exist?
Date: 12 Oct 92 18:02:39 GMT
Reply-To: hendrix@haber.Eng.Sun.COM
Organization: Sun Microsystems, Inc.
NNTP-Posting-Host: haber


 Yes There is a Verilint available from "InterHDL" it is prity good
These are the same guys who publised the book "designing with Verilog"
Call them at 

(408) 749 8823
Newsgroups: comp.lang.verilog
From: yount@fox.ece.cmu.edu (Charles Robert Yount)
Subject: Re: legality of force? (answer)
Organization: Electrical and Computer Engineering, Carnegie Mellon
Distribution: comp
Date: Wed, 7 Oct 1992 20:03:54 GMT


The answer is to use the "scalared" attribute on the wire declaration.

Thanks to all who responded!

Chuck
From: grc@stl.stc.co.uk (Gary Cook)
Newsgroups: comp.lang.verilog
Subject: Verilog help required.
Date: 16 Oct 92 12:58:32 GMT
Organization: STC Technology Ltd., London Road, Harlow, UK.


We are very new users of verilog and are having trouble with a few
things .. any experts out there can help ???

1. We *had* this kind of code :-

   module mod_name (in,control,data) ;
   input in,control ;
   inout data ;

   reg out_buf ;

   assign data = (control) out_buf ? 1'bz ;

   out_buf = ......

And so on. Data was a bi-directional port used both as an input and an
output. This compiles OK.

NOW ... we tried to use a specify block to set module delays ...and
tried something like ...

   module mod_name (in,control,data) ;
   input in,control ;
   inout data ;

   reg out_buf ;

   bufif1 b1 (data,out_buf,control) ; 

   out_buf = ......
  
  specify
    (in *> data) = (x,y,z etc.) ;
  endspecify

When I try to compile this it gives an error indicating that 'data'
has to be acceleratable ...... 

Isn't "inout" acceleratable ????? Or is it something to do with bufif1
??  I've done as similar thing using data as an output with a norma
buf and that works OK. How do I get round this ???


2) Related to the above scenario. If I want to output buffer a bus how
do I do it without needing to buffer each individal bit ?

ie    1-bit ... buf(out,in)

but   n-bit     buf(out[n-1],in[n-1])
                buf(out[n-2],in[n-2])
                  ...
                  ...
                buf(out[0],in[0])

Thanks in advance for any advice.

Gary Cook.

ps. Exuse the .signature .... I normally only submit to rec.sport.soccer !

--
  Gary Cook,                  LL      UU   UU   FFFFFF   CCCCCC             
  BNR Europe Limited.          LL      UU   UU   FF       CC   
  Harlow,                       LL      UU   UU   FFFFFF   CC                
  England.                       LL      UU   UU   FF       CC               
  E-Mail : grc@bnr.co.uk          LLLLL   UUUUUUU   FF       CCCCCC
From: elliot@Wellspring.COM (Elliot H. Mednick)
Newsgroups: comp.lang.verilog
Subject: Concantenation Problems
Distribution: world
Date: Sat, 10 Oct 92 15:03:46 GMT
Organization: Wellspring Solutions, Sutton, MA.
Reply-To: elliot@Wellspring.COM

In article <1992Oct9.185221.10612@tamsun.tamu.edu> kuttanna@eemips.tamu.edu writes:
 > I have been trying to model the shift right/left operations wherein I
 > shift a register by a variable amount (specified within the instruction).
 > [...]
 >  result = {{`SHAMT{op2[WIDTH-1]}},temp[WIDTH - `SHAMT - 1:0]};
 > 
 > I keep getting the following error message :
 > 
 > Error!    Non-constant part-select index                    [Verilog-NCPSI]
 >           "r2k.v", 560: temp[WIDTH - IR[10 : 6] - 1:0]
 > 
 > The manual says that you cannot concantenate with non-constant widths.

It not just that -- you can't have a variable part select _anywhere_.

Left shift:
result = op2 << `SHAMT;

Right shift with fill:
result = ({{`WIDTH {op2[`WIDTH - 1]}}, op2} >> `SHAMT);
//         ^^^^^^^^^^^^^^^^^^^^^^^^^ prepend lots of high bits before the shift

The is or may not Do The Right Thing in synthesis, but you get the idea.
--
Elliot H. Mednick                                        P.O. Box 150
Wellspring Solutions                                     Sutton, MA. 01590
elliot@Wellspring.com                                    +1 508 865 7271
Newsgroups: comp.lang.verilog
From: jeffc@eng.hou.compaq.com (Jeff Carlson)
Subject: Verilog mode for emacs?
Organization: Compaq Computer Corporation
Distribution: comp
Date: Thu, 15 Oct 1992 14:35:08 GMT

Could someone post or email me the verilog mode for emacs?
Thanks,
JC
--
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
| jeffc@gadget.eng.hou.compaq.com |  "Duct tape is like The Force. It has |
| Compaq Computer Corporation     |  a light side and a dark side, and it |
| Houston, TX  (713) 374-9141     |  holds the universe together."        |
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
From: hanson@henson.cc.wwu.edu (Ken Hanson)
Newsgroups: comp.lang.verilog
Subject: Implicit type conversion
Summary: Implicit type conversion in verilog?
Keywords: verilog, types, expressions
Date: 13 Oct 92 16:34:35 GMT
Article-I.D.: henson.1992Oct13.163435.118
Organization: Western Washington University

The Verilog manuals don't go into much detail regarding type conversion, except
regarding reg vectors and signed values.  What are the rules regarding implicit
type conversion.  As far as I can tell whenever a reg is involved in an
expression, the evaluation is in unsigned arithmetic, regardless of the other
operands type.  What about real types?  Are they always converted to unsigned
ints?  Any answers to the above questions would be much appreciated!


		-- Ken  (hanson@henson.cc.wwu.edu)
From: hendrix@haber.Eng.Sun.COM (George Haber)
Newsgroups: comp.lang.verilog
Subject: Re: Does verilint exist?
Date: 16 Oct 92 17:18:04 GMT
Reply-To: hendrix@haber.Eng.Sun.COM
Organization: Sun Microsystems, Inc.
NNTP-Posting-Host: haber

Inter-HDL 
 Voice ==> (408) 749-8775
 Fax   ==> (408) 749 8823


In article 19220001@otter.hpl.hp.com, dmb@otter.hpl.hp.com (David Banks) writes:
=>>  Yes There is a Verilint available from "InterHDL" it is prity good
=>> These are the same guys who publised the book "designing with Verilog"
=>> Call them at
=>> 
=>> (408) 749 8823
=>
=>This appears to be a fax number.
=>
=>Could you post their phone number please?
=>
=>regards
=>
=>Dave Banks
=>
=>=====================================================
=>David Banks             
=> dmb@hplb.hpl.hp.com    
=> Hewlett Packard Labs,  
=> Bristol, England.      
=> +44 272 228244
=>=====================================================
From: jeffc@eng.hou.compaq.com (Jeff Carlson)
Newsgroups: comp.lang.verilog
Subject: Verilog mode for emacs?
Date: 14 Oct 92 19:57:37 GMT
Article-I.D.: gadget.JEFFC.92Oct14145737
Distribution: usa
Organization: Compaq Computer Corporation

Could someone post or email me the verilog mode for emacs?
Thanks,
JC
--
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
| jeffc@gadget.eng.hou.compaq.com |  "Duct tape is like The Force. It has |
| Compaq Computer Corporation     |  a light side and a dark side, and it |
| Houston, TX  (713) 374-9141     |  holds the universe together."        |
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
From: ralf@chpc.org (Ralph Valentino)
Newsgroups: comp.lang.verilog
Subject: `timescale
Keywords: PLI
Date: 14 Oct 92 21:45:21 GMT
Organization: Center For High Performance Computing

If I use `timescale at all in a verilog file, the tf_gettime() call
seems to die (always returns 0 even after simulation time passes).
Has anyone seen similar effects or have an alternate method of accessing
simulation time?

I'm using verilog 1.6b-beta, but I've witnessed this in earlier revs
as well.  Unfortunately, my most recent copy of the PLI reference
manual is 1.5a - it doesn't seem to help.

Wild and crazy ideas accepted,
-Ralph
===============
Ralph Valentino   (ralf@chpc.org)  (ralf@wpi.wpi.edu)
Hardware Engineer,  Worcester  Polytechnic  Institute
Center for High Performance Computing, Marlborough MA
Newsgroups: comp.lang.verilog,comp.cad.cadence
From: schumach@apollo.HP.COM (dan schumacher)
Subject: Help with VerilogIn please
Date: Fri, 9 Oct 1992 20:45:54 GMT
Organization: Hewlett-Packard Company, Chelmsford, MA

I have been trying to use "verilogIn" within
Opus 4.2.  I have run into many problems with this,
and have run out of work around potentials.

The netlist that I am trying to read is fairly large (20K gates),
but not huge.

When running VerilogIn, get the error:
 "File vo.c, Line 91, Function noname *FATAL*failed
     to get the current working directory: 12."
Memory fault(coredump)

I am running on an HP9000/700 with v8.07.

Can anyone suggest the cause of the problem, or a
potential work around.

All that I am really trying to do is get a Verilog gate-level netlist into
Framework II.  I don't need a pretty schematic.

Does anyone know of a verilog netlist reader?

Any assistance would be greatly appreciated.  Thanks in advance.


				 desperately yours,

						Dan Schumacher
						Advanced Systems Division
						Hewllett-Packard
From: kuttanna@eemips.tamu.edu (Belliappa Kuttanna)
Newsgroups: comp.lang.verilog
Subject: Concantenation Problems
Date: 9 Oct 92 18:48:21 GMT
Article-I.D.: tamsun.1992Oct9.184821.9945
Organization: Texas A&M University

I have been trying to model the shift right/left operations wherein I
shift a register by a variable amount (specified within the instruction).

This is the way I tried to do it:

parameter WIDTH = 32;
`define SHAMT IR[10 : 6] 
reg [WIDTH - 1 : 0] op2,temp,result,IR;
.
.
.
.
 result = {{`SHAMT{op2[WIDTH-1]}},temp[WIDTH - `SHAMT - 1:0]};

I keep getting the following error message :

Error!    Non-constant part-select index                    [Verilog-NCPSI]
          "r2k.v", 560: temp[WIDTH - IR[10 : 6] - 1:0]

The manual says that you cannot concantenate with non-constant widths.

Any ideas on how to get around this problem ?

Thanks in advance.
Belliappa Kuttanna  kuttanna@ee.tamu.edu
Newsgroups: comp.lang.verilog
From: kuttanna@eemips.tamu.edu (Belliappa Kuttanna)
Subject: Concantenation Problems
Organization: Texas A&M University
Date: Fri, 9 Oct 1992 18:52:21 GMT

I have been trying to model the shift right/left operations wherein I
shift a register by a variable amount (specified within the instruction).

This is the way I tried to do it:

parameter WIDTH = 32;
`define SHAMT IR[10 : 6] 
reg [WIDTH - 1 : 0] op2,temp,result,IR;
.
.
.
.
 result = {{`SHAMT{op2[WIDTH-1]}},temp[WIDTH - `SHAMT - 1:0]};

I keep getting the following error message :

Error!    Non-constant part-select index                    [Verilog-NCPSI]
          "r2k.v", 560: temp[WIDTH - IR[10 : 6] - 1:0]

The manual says that you cannot concantenate with non-constant widths.

Any ideas on how to get around this problem ?

Thanks in advance.
Belliappa Kuttanna  kuttanna@ee.tamu.edu
Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.lang.mentor
From: uds@parvathi.cs.wayne.edu (Seetamraju)
Subject: Re: Help!! regarding gate delays!!!!
Organization: Wayne State University, Detroit, MI
Date: Fri, 16 Oct 1992 22:23:21 GMT


I feel your question is : how does the delays get `WORSE' after the
modules are interconnected...

When I tried it , I did the following.  In my verilog model I calculated
(By intuitive reasoning, thats the best students can do), the fan out of
each gate in the circuit.  90 % of the gates have fanout less than 2, especially
for me.  Unless you have a bus-oriented circuit.

Well, I then defined units for the fanout.  Using MAGIC, I approximated that
a fanout-load going into a three-input AND gate was like two NOT_gate_fanout.  etc...
All gates were `labelled' in NOT-gate-fanout-units.  Then for each
simple atomic unit, I simulated the performance for different # of NOT gates..

eg: I simulated IN MAGIC, the dalays when a two input AND gate drives 1, 2 , 4, 6 & 8
and 16 NOT gates.  Similarly, for NOT gates themselves, and OR / XOR, etc...

use the MAGIC results in verilog as the delay parameters.

This was the only solution for me.  I couldnt get hold of accurate
`foundry-data' -- that was impossible for me.  All we had a basic verilog simulator
and Public-Domain MAGIC...


Seetamraju Udaya Bhaskar Sarma
(email : seetam @ ece7 . eng . wayne . edu)

From: dmb@otter.hpl.hp.com (David Banks)
Date: Wed, 14 Oct 1992 17:25:51 GMT
Subject: Re: Does verilint exist?
Organization: Hewlett-Packard Laboratories, Bristol, UK.
Newsgroups: comp.lang.verilog

>  Yes There is a Verilint available from "InterHDL" it is prity good
> These are the same guys who publised the book "designing with Verilog"
> Call them at
> 
> (408) 749 8823

This appears to be a fax number.

Could you post their phone number please?

regards

Dave Banks

=====================================================
David Banks             
 dmb@hplb.hpl.hp.com    
 Hewlett Packard Labs,  
 Bristol, England.      
 +44 272 228244
=====================================================
From: msprague@seqp4.sequoia.com (Mark Sprague)
Newsgroups: comp.lang.verilog
Subject: Does verilint exist?
Date: 9 Oct 92 20:56:30 GMT
Article-I.D.: seqp4.1615
Organization: Sequoia Systems Inc., Marlboro, Mass.


Does anyone know of a `lint' type program for verilog?  

Thanks in advance for any help.

		Mark Sprague
		msprague@sequoia.com
Newsgroups: comp.lang.verilog
From: cranston@ayn.cadence.com (W. Scott Cranston)
Subject: Re: Accessing command line arguments
Organization: Cadence Design Systems, Lowell MA, United States of America
Distribution: usa
Date: Wed, 30 Sep 1992 02:34:06 GMT

In article <90432@netnews.upenn.edu> ekenberg@down.hep.upenn.edu 
(Tor L. Ekenberg) writes:
 
> Sorry if this a FAQ, but how can I access the command line arguments I started
> verilog with?
> 
> Thanks in advance,
> 
> 				- tor
> 

My answer is in two parts:

1) From the HDL, you can only get the plusargs, using the predefined
system task $scan$plusargs.  This returns true or false depending on
whether the specifed plusarg is on the command line.  For example:


yourhost> verilog -axs +plusarg1value +plusarg2ref file.v

And in your description you put

reg r;
r = $scan$plusargs("plusarg1"); //r will be 1
r = $scan$plusargs("plusarg3"); //r will be 0

2) Using the PLI, you can also access the plusargs using the function
mc_scan_plusargs().  This will give the remainder of the argument.
Using the same command line as above:

char *arg = mc_scan_plusargs("plusarg1"); 

will set arg to "value."

There is currently no way to get all the arguments.  In the future
there may be hooks in the PLI to get argc and argv, but not currently.


Enjoy,
 WSC


--
+---------^>        "The Spirit of Massachusetts is the Spirit of America"
|        <                    -Massachusetts Division of Tourism
+-------. \   7     "Right..."
         \_\_/                -cranston@cadence.com
Newsgroups: comp.lang.verilog
From: eversole@acae037.cadence.com (Richard Eversole; x6239)
Subject: Re: emacs verilog-mode bug report
Reply-To: eversole@acae037.cadence.com (Richard Eversole; x6239)
Organization: Cadence Design Systems, Inc.
Date: Mon, 12 Oct 1992 13:22:31 GMT

In article <1992Sep25.204723.11454@oakhill.sps.mot.com>, johnw@oakhill.sps.mot.com (John Waite) writes:
|> I have tried to indent lines with an "else" on them but
|> verilog-mode gets confused and hangs up.
|> 
|> There may also be a problem with too many levels of 
|> "begin/end"'s; there comes a point where verilog mode
|> does not find the previous level (or something like
|> that) and aligns the "end" with the previous "begin".
|>

How many levels of else ?
I got the patches for indent mode from Michio Hayakawa and
applied them but have not had time to fully check them out.
You are using my verilog mode ?
Current version is 3.1

In any event, the bug has been noted and when I get a chance to get
back to working on it I'll look at it more carefully.
 
|> Cheers,
|> -- 
|> John Waite             		AMCU Modular Microcontrollers
|> Motorola, Inc.			Systems Design
|> Mail Stop OE-320		
|> 6501 William Cannon Dr. West	

-- 
  
  =====================================================================

    eversole@cadence.com
  
    Live long and prosper !

Newsgroups: comp.lang.verilog
From: cranston@ayn.cadence.com (W. Scott Cranston)
Subject: Re: Variable width assignments?
Followup-To: comp.lang.verilog
Organization: Cadence Design Systems, Lowell MA, United States of America
Date: Sat, 26 Sep 1992 23:09:50 GMT

In article <rfall-240992171955@andrich.mv.us.adobe.com>rfall@mv.us.adobe.com (Richard Fall) 
writes:
> 
> Does anyone know if there's an easy way of doing the following
> in Verilog?
> 
>     I would like to be able assign a fixed value (say, zero),
>     declared as a single parameter ("zero") in assignment
>     statements where the variable on the LHS of the statements
>     may be of different bit width.
>     
>     That is, if I have the following:
>     
>         reg [1:0] foo;
>         reg [2:0] foolong;
>         
>     I would like to be able to say:
>      
>          foo = zero;
>          foolong = zero;
>          
>     and have the correct assignment take place.
>      
>     
>     Before you rush to tell me that Verilog already does that
> by zero-extending the RHS side to fit the LHS side, I'll point
> out that I may want to do the same thing with a parameter in
> which zero-extending is not the correct behavior.  For
> example, I may want the value "5555...." to be assigned to
> registers that may be any multiple of 4 bits wide.
> 
>     If there were a "sizeof" operator, this would be easy
> to do by using it in conjunction with repeated concatenation
> to produce the desired effect, but no such operator appears to
> exist.
> 
>     Am I missing something, or is there a clever way to do this?
> 
> 

You could make a max length integer which consists of the specified
integer repeated and assign it to the LHS.  Verilog will truncate to
the correct size.  For instance:

	reg [3:0] foo;
	reg [15:0] foolong;

	parameter rhs = (1E6{4'h5}};
	foo = rhs;
	foolong =  rhs;



foo will be 4'h5 and foolong will be 16'h5555.


Of course, 1E6 is too big, but use whatever you need.

Good Luck,
  Scott Cranston
  Cadence Design Systems




--
+---------^>        "The Spirit of Massachusetts is the Spirit of America"
|        <                    -Massachusetts Division of Tourism
+-------. \   7     "Right..."
         \_\_/                -cranston@cadence.com
Xref: sparky comp.lang.verilog:388 comp.lang.vhdl:489
From: deepak@konark.njit.edu (Albatross)
Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.lang.mentor
Subject: Help!! regarding gate delays!!!!
Date: 16 Oct 92 18:53:59 GMT
Article-I.D.: njitgw.1992Oct16.185359.24132
Distribution: usa
Organization: New Jersey Institute of Technology, Newark, N.J.

This goes out to anyone who has used HDL for digital design. I am
trying to build the structural model of a hypothetical instruction set
processor (ISP). 

Now my question is; When one is into structural modelling, & one
describes a component for example an AND gate. One describes the inputs,
the output, and the initial delay, rise time & fall time. These values
of tr, tf are very important. I am led to believe that if one uses 0ns
delay then we still end up with unit delays for each time the module is
used in a higher level. What do commercial designers use for these
values of tr & tf. 

In the industry if you are doing a structural model of some device &
your device uses about lets say '50 gates'(Example). What would be the
delays one would specify for the gates. What is it based upon

For example the project that I'm working on has about 20 odd registers,
2 source buses, 1 destination bus, an ALU , and an Address bus in the
Datapath. It also has a control unit, which gives the necessary control
signals to work the Datapath. Now since the entire processor is being
built hierarchically using lower level modules, what should I base my
delays on in the lower level models. Also how do I consider Bus delays.

I hope someone out there can really provide an answer to my question.
This is with regards to my M.S. thesis & I really need some advice on
this matter. If someone is willing to help , please reply by email & I
will explain my question again if necessary.

Thanks in advance,

-Deepak Kakadasam                             deepak@konark.njit.edu


--
VLSI:=> "Getting High On Low Voltage"       ** 
E15WNJTPXE15x280WXR1TL21NXL4TL17NXR10TL->    **    Those who can, DO
You can tune a guitar, but you cant tuna fish.**    Those who cant, TEACH.
*******************************************************************************
Newsgroups: comp.lang.scheme