From: weaver@jetsun.weitek.COM (Michael Gordon Weaver)
Newsgroups: comp.arch
Subject: Re: Why very big clock for Alpha
Date: 9 Oct 92 00:40:48 GMT
Organization: WEITEK Corporation, Sunnyvale CA

In article <1992Oct1.150242.20275@ntuix.ntu.ac.sg> eoahmad@ntuix.ntu.ac.sg (Othman Ahmad) writes:
>Looking at the July Spectrum, I noticed that the clock of the alpha chip
>takes as much area as the data cache.
>	Is this a reasonable price to pay for having single phase clock
>input? Isn't it better to have the mulit-phase clock generated
>externally?
>	If clock distribution is the major problem, why isn't it more
>economical to have more clock pads, like the power pads?
>
The problem is not clock distribution. The problem is clock skew,
the difference in time between the arrival of the clock edge at 
one point in the chip and the time of arrival of the same edge
at another point in the chip. 

A chip like Alpha contains many thousands of latches with logic gates
in between them. The latches are transparent (transmit data) on one
phase of the clock, and hold data on the other phase. About half of the
latches are transparent when the clock is high (call them phase one),
and about half are transparent when the clock is low (call them phase
two). Usually, the input of a phase one latch depends only on the
outputs of phase two latches and vice-versa.  This ensures that signals
don't race through the circuit at full speed, but rather they 'stop' to
resynchronize when a latch goes from transparent to holding.

There are two sorts of failures that happen when the clock skew is
gets out of hand: setup violations and hold violations.

Imagine a string of four latches with logic between them, alternating
phase one latch, logic, phase two latch, logic, phase one latch, logic,
phase two latch.

If the falling edge of a clock arrives late at the third latch relative
to the second latch, and the delay on data from the first latch to the 
third latch is too great, then the third latch may start holding before
the data on its input is ready. This is a setup violation. It will only
occur when the clock cycle is less than a certain amount, determined
by the delays and the clock skew.

If the rising edge of a clock arrives late at the second latch,
relative to when it arrives at the third latch, the third latch may
become transparent while the second is still transparent. If the delay
between the latch one and latch three is small enough, data may go all
the way from the first latch to the fourth latch without stopping for
the clock. This is a hold violation. It does not depend on the clock cycle.

Hold violations will cause your chip not to work as designed, even if
you slow down the clock, and so they are very serious. Setup violations
will determine the maximum cycle time at which the chip will operate
properly.  Bringing all clock skews to near zero will reduce the
chances of hold violations, and make the cycle time equal to the
longest data delay between latches.

The designers of Alpha chose a 'brute force' approach to minimizing
clock skew, by using only one electrical node to drive all clock
inputs, and putting the driver for that node in the center of the chip.
This requires that phase one and phase two latches use different
circuits.  

Transistors keep getting smaller and faster, while chip sizes slowly
get larger. So the time to propagate a signal across the chip is going
up relative to the cycle time for a given circuit. So I expect that
clock skew control to be of increasing interest for the next few years.
After a while we won't be able to pretend that one clock edge occurs at
the same time in all places, and we'll likely have local clocking and
global clocking.

Michael Weaver.
Xref: sparky comp.arch:9968 comp.lang.misc:3255