From: paul@eros.Berkeley.EDU (Paul Cohen)
Newsgroups: comp.lsi.cad
Subject: 1993 IEEE/CS VLSI Workshop
Date: 13 Jan 1993 01:14:44 GMT
Organization: University of California at Berkeley
Distribution: world
NNTP-Posting-Host: eros.berkeley.edu

                      IEEE Computer Society
 	            VLSI Technical Committee
                    1993 Winter VLSI Workshop
                        Tentative Program

                       February 7-10, 1993
                   Asilomar Conference Center,
                        Pacific Grove, CA

   (Includes Workshop and Conference Center registration forms)

***************************************************************************
Space at the 1993 VLSI Workshop is very limited. If you would like to attend,
please send the registration forms as quickly as possible.
***************************************************************************

Purpose:

The purpose of this workshop is to provide a forum for 
presentation and discussion of the progress and problems of 
current interest in VLSI.  This annual workshop is sponsored by 
the IEEE Computer Society Technical Committee on VLSI. 

Participation:

All presentations will be given by speakers that the Program 
Committee has invited. There will be no proceedings so that the 
speakers will be able to present their most recent results and 
ideas. Speakers may distribute abstracts on a voluntary basis. 
Attendance at the workshop is limited to 80 persons to encourage 
interaction. 

Workshop and Conference Center Registration:

The workshop registration fee is $175 for IEEE or Computer 
Society members, $225 for non members. A separate registration 
form is provided for the Asilomar Conference Center. Asilomar 
registration includes 3 nights lodging (Sunday, Monday, and 
Tuesday), as well as all meals from Sunday Dinner through 
Wednesday lunch. This form should be completed separately, and 
send directly to the conference center. 

Additional Information:

Questions regarding the 1993 VLSI Workshop should be directed to:

Paul B. Cohen
Advanced Hardware Architectures
P.O. Box 9669
Moscow, ID 83843

paul@aha.com, paul@ic.berkeley.edu
(208) 883-8000 (voice), (208) 883-8001 (fax)

Patrick McGeer 
Department of Electrical Engineering and Computer Sciences,
205 Cory Hall,
University of California, Berkeley
Berkeley, CA, 94720

mcgeer@ic.berkeley.edu
(510) 642-6256 (voice)  (510) 643-5052 (fax)
     
Sunday night, February 7: Reception & cocktails

    
    Keynote: 
         Bob Brodersen, UC Berkeley:
               New Drivers for VLSI Research
    

Monday, February 8:  
    8:30 - 10:00 New Applications for BDDs

         Ed Clarke, CMU: 
              Multi-terminal BDD's: a new Matrix Data Structure
 
         Rick McGeer, UC-Berkeley: 
              MTBDD's: Theoretical Results and Operations

         Randal Bryant: 
              A New Programming System based on MTBDD's 

         Fabio Somenzi, CU-Boulder: 
              Linear Programming Applications of MTBDDs
    
    
    10:30-12 Transportation Applications
    
         Pravin Varaiya, UC-Berkeley: 
              The PATH Project

         Jitendra Malik, UC-Berkeley: 
              Vision Systems for Intelligent Vehicles

         Ed Frank, Sun Labs:  
              Consumers just wanna have fun: UI and application
              issues for Everywhere Electronics
    
    
    2-3:30  High Level Synthesis
              
          Mike Mcfarland, Boston College: 
              CPA and its Applications

          Alex Orailoglu, UCSD:
              High Level Synthesis of Fault Tolerant ICs

          Phil Windley: U of Idaho
              Denotational Semantics and Its Application to hardware

          Kel Winters  U of Idaho
              DLX: A RISC Architecture Case Study
    
    6-8   Dinner, Asilomar
    
    
    8-10  Panel: 
          Future of VLSI Research
          Panelists: (Partial List)
              John Conover (SMOS Systems)
              Bernie Chern (NSF)
              Rick McGeer (UC-Berkeley)


Tuesday, February 9: High-Speed Computing Day

    8:30-10 High-Performance Processors 
    
         Robert Owens, Penn State: 
              Micro-grain array processor

         John Wawryznek, UCB: 
              High-Performance Processor Core

         Mike Bolotski, MIT:
              An SIMD computer for vision and image processing

         Mark Horowitz, Stanford:
              Clocking in High Performance Processors
    
    
    10:30-12 The DEC Alpha Chip: Architecture, Technology, and CAD 
    
          Dobberpuhl,  McLellan,  and Grundman, DEC:
    
    
    2-3:30 Asynchronous Systems


         Steven Burns, University of Washington
            TBA

         Steven Nowick, Columbia University
            TBA
                   
                   
    4-6:   Voluntary IEEE TC/VLSI Business Session
    
    
    6-10: Banquet
    
    

Wednesday, February 10:

     8:30-10: Optical Computing
       
         Sadik C. Esener, UCSD: 
              Progress in Optoelectronic Device Technology and 
              Its impact on Computing     

         Vince Huering, CU-Boulder: 
              Time of Flight, Latchless Architectures:
              Computing at the Speed of Light

         Steven Levitan, Pitt: Reconfigurable Optoelectronic
              Interconnection Networks 
       
       
       
     10:30-12: Abstraction/Verification
       
         Alex Saldanha, UC-Berkeley: 
              Abstraction in Processor Verification

         Ed Clarke, CMU:

         Don Herbert, SRI Cambridge: 
               The SAMOS Project: Simultaneous
               Verification of Processor and Compiler
       
       
    2-3:30 Logic Synthesis
       
         K-C Chen, Fujitsu America: 
              FPGA Synthesis

         Bill Lin, IMEC:
              Synchronous Restructuring Algorithms for 
              Optimizing Synchronous Circuits

         Ted Stanion, University of Washington
             TBA

Workshop  Registration:

                     IEEE  Computer  Society
                     1993  Workshop  on  VLSI

                        Registration Form


Name: ___________________________________________________________________



Title: __________________________________________________________________



University or Firm: _____________________________________________________



Dept. or Street Address: ________________________________________________



City, State and Zip Code: _______________________________________________



Phone Number:  __________________________________________________________



Electronic Mail Address:  _______________________________________________



IEEE Member Number:  ____________________________________________________


Make checks payable for $175 (IEEE or CS members) or $225 (non-
members) to the IEEE Computer Society VLSI Workshop. 

Mail this form to:

        Paul B. Cohen
        Advanced Hardware Architectures
        P.O. Box 9669
        Moscow, ID 83843

        (208) 883-8000 (voice)
        (208) 883-8001 (fax)

                ASILOMAR HOUSING REGISTRATION FORM
     IEEE VLSI WORKSHOP (C3479) Arrive 2/7 di - 2/10 lu/1993

           (Please type or print - one form per person)

LAST NAME_____________________________FIRST NAME__________________

ADDRESS______________________CITY____________STATE_______ZIP_____

BUSINESS PHONE (____)______________HOME PHONE (____)______________

Rates are 3 nights-per person 3 P.M. check-in and 12:00 noon 
departure. Includes all meals - beginning with dinner on the 
first day and ending with lunch on the day of departure. 

                           HOUSING RATE

HOUSING       SINGLE         YOUTH
              $306.00        CALL FOR RATE       

____ I will share a room with ____________________________
____ Please assign a roomate for me.
____ Smoker*____Non-Smoker____Male____Female____Vegetarian
____ Disability access reqiured - Disability_______________________
*if unable to assign a smoker roomate, we will place with non-
smoker and request no smoking in the room. 


         (Reservations accepted on space available basis)

Send this form and FULL PAYMENT (check or money order) to:
ASILOMAR CONFERENCE CENTER, P.O. BOX 537, PACIFIC GROVE, CA 93950

TELEPHONE RESERVATIONS AND CREDIT CARDS NOT ACCEPTED

ASILOMAR POLICIES:
1.     All reates are for full time participation and include housing, 
       tax and meals.
2.     Only a limited number of single rooms are available, and will be
       assigned on a first come, first served basis.
3.     Cancellation received in writing after 12/31/92 is subject 
       to a $25.00 cancellation fee. Cancellation notice after 1/7/93 is 
       subject to forfeiture of all fees if space is not sold.
4.     Any charges accrued with the processing of foreign checks will be the
       responsibility of the conferee concerned.
5.     For additional information regarding housing, please call (408) 
       372-8016. Ask for Betty Forbes or Pat Kauffman.

-- 
Paul B. Cohen				| paul@aha.com
Advanced Hardware Architectures, Inc.	| paul@ic.berkeley.edu
P.O Box 9669				| (208) 883-8000 (v)
Moscow, ID 83843			| (208) 883-8001 (f)