From: bill@solaria (Bill Neisius)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Re: 3-chip-simm look good on Chip+Techn 8230 chipset
Date: 8 Oct 92 14:09:06 GMT
Reply-To: bill@solaria.hac.com
X-Newsreader: TIN [version 1.1 PL6]

DXB132@psuvm.psu.edu wrote:
: In article <23530@hacgate.SCG.HAC.COM>, bill@solaria (Bill Neisius) says:
: >Reinhard Kirchner (kirchner@uklira.informatik.uni-kl.de) wrote:
: I suppose this is a FAQ, but would someone explain what the problem is with a
: "3 chip SIMM". I would guess it refers to a 1MBx9 SIMM built with 2 1MBx4
: chips and another for parity. I see no compatibility problem with replacing
: 8 1MBx1 with 2 1MBx4, so is the problem with the added chip for parity?
: Please only answer if you really know. :-)

The following articles seem to sum it up pretty well:

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From: veit@du9ds3.uni-duisburg.de (Holger Veit)
Newsgroups: comp.sys.ibm.pc.hardware,comp.os.os2.misc
Subject: Re: Can I mix 70ns SIMMS with 80ns SIMMS
Date: 29 Jul 92 10:54:08 GMT
Reply-To: veit@du9ds3.uni-duisburg.de
Organization: Uni-Duisburg FB9 Datenverarbeitung

In <l7cno9INN6v7@tokio.cs.utexas.edu> graham@cs.utexas.edu (Ralph Arnold Graham) writes:

>In article <1992Jul28.172146.21250@njitgw.njit.edu> dic5340@hertz.njit.edu (David Charlap) writes:
>>Dave Arnold writes:
>>>I am upgrading to OS/2 2.0, and so I need 8 megabytes of RAM.
>>>Can I safely mix 80ns chips with 70ns chips
>>>for use with OS/2?  I was told that OS/2 is very sesitive to memory.
>>
>>I don't think you'll have a problem, but get a warantee, anyhow.

>I have successfully mixed four 1MBx9 60 ns SIMMs and four 1MBx3 70 ns SIMMs
>in my 386-20 and have had no problems running OS/2 2.0...

The problem is not really the different access time, as long as the slowest
chipset is at least as fast as it should be for the processor clock
frequency (e.g. 70ns for 386/33 with 1 wait state, 60 for 0 WS).

It is usually the above combination of 1MBx9 and 1MBx3 that may or may not work
depending on the chipset your 386 board uses. Some older chipsets are not 
designed for 4MB SIMMs and will accept 1MBx3 SIMMs in DOS applications,
but not under OS/2 or other protected mode OSes. 
This is because the 3 chip SIMM has 4 Meg chips on it (two 1Mbit x 4 and one
1Mbit x 1). 4Meg chips have an additional refresh line which is not serviced
by older chip sets. Thus, you use the 3-chip SIMM outside of the specification,
which is critical in particular in OS/2.

Conclusion: look into your motherboard's manual. If it accepts a configuration
with 4 Megabyte SIMMs/SIPs (not 4 x 1MByte in a bank, but 16 MByte in a bank),
then you are safe to use 3-chip sets. Otherwise use 9-chip sets.

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From: renebi@idt.unit.no (Olaf Rene Birkeland)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Re: What Is Difference: 3-chip SIMMs and 9-chip SIMMs?
Date: 5 Aug 92 12:05:38 GMT
Reply-To: renebi@idt.unit.no
Organization: The Norwegian Institute of Technology

In article <1992Aug5.025219.18868@mlb.semi.harris.com>, sonny@charybdis.harris-atd.com (Bob Davis) writes:
|> 	Is there any fundamental difference between ? x 9 SIMMs which have
|> 3 chips and those which have 9 chips?
|> 
|> 	Is the 3-chip variety made of two 4-bit wide RAMs and one 1-bit
|> wide RAM?

Exactly!!

|> 
|> 	Is the 9-chip variety made of nine 1-bit wide RAMs?
|> 
|> 	If there is no basic difference between the 3-chippers and the
|> 9-chippers, why do I see postings specifically requesting one type
|> rather than the other?


There *is* a difference. The 4-bit wide RAMs are of the new 4-Mbit
generation. Since chips have become denser, newer testing methods have
been developed (PRODUCTION TESTING!!!). The former 1-Mbit chips had a
special test pin to enter test mode by applying >7.5V, i.e. more than
would occur in a normal 5V-design.

As the 4-Mbit chips demands more pins for data and/or adress lines,
this pin has disappeared to avoid large housings. Instead the test
mode is entered by applying a CAS-before-RAS (CBR) refresh cycle (one of
several ways to refresh the RAM) simultaniously with holding WE
asserted (active low).

A normal CBR resfresh cycle should be done with WE inactive (high).

The problem is that the 1-Mbit specified a don't care condition for
the WE during CBR refresh. Thus, memory controllers not designed for
the 4-Mbit chips and using CBR refresh (very usual) *might* have the
wrong polarity of WE causing test mode to be entered, which will cause
most systems to crash.

The fact that preliminary data sheets for the 4-Mbit often didn't
describe this difference/feature/bug, doesn't make it any easier.

Conclusion:

9x1-Mbit will always work

2x4-Mbit + 1x1-Mbit should work in most newer systems, and is often
cheaper! 

*NEVER* completely trust a salesperon who claims "compatible". :-)


Newsgroups: comp.sys.ibm.pc.hardware