From: wallacen@ColoState.EDU (nathan wallace)
Subject: Re: Opcodes for New Processor
Date: Mon, 04 Jan 1993 19:47:45 GMT
Reply-To: wallacen@ColoState.EDU
Organization: Colorado State University -=- Computer Science Dept.


ATTENTION ASSEMBLY LANGUAGE PROGRAMMERS:


Here are the OPCODES for the new "Walrus 158000" Microprocessor. Please
be sure to use them correctly when programming for this chip:

BBI  Branch on Burned-out Indicator
BPO  Branch on Power Off
RPB  Reverse Parity and Branch
RWT  Read/Write while Stretching Tape
SRZ  Subtract and Reset to Zero
SSW  Scramble Status Word
RCS  Read Card and Scramble Data
SSD  Stacker Select Disk
RCR  Rewind Card Reader
EJD  Eject Hard Disk
BSD  Backspace Hard Disk
EIO  Execute Invalid Opcode
EXO  Execute Operator
ECP  Erase Card Punch
RNR  Read Noise Record
DMP  Destroy Memory Protect Key
MLR  Move and Lose Record
DIA  Develop Ineffective Address
SCP  Scatter Printer
PBC  Print and Break Chain
JLP  Jump and Lose Pointer
RDI  Rewind Hard Disk Immediate
BRL  Branch and Leak
SWT  Select Wrong Terminal
EXP  Execute Programmer
DIH  Disable Interrupts and Hang
VMA  Violate Maintenance Agreement
DFA  Disable Fans
EAL  Enable AC to Logic Rack
EAO  Enable AC to Operator
DIG  Disable Gravity
ESP  Enable Sprinkler System
JOB  Jump on Beaver
NCW  Notch Carriage and Way
DIE  Disable Everything
AAR  Alter At Random
CMD  Compare Meaningless Data
ENF  Emit Noxious Fumes
ISC  Insert Sarcastic Comments
PEHC Punch Extra Holes in Cards
WNAM We Need A Miracle
BRH  Branch and Hang
ING  Inquire and Ignore
DOV  Divide and Overflow
ARZ  Add and Reset to Zero
PIC  Print Invalid Character
SSJ  Select Stacker and Jam
FSR  Form Skip and Runaway
WWR  Write Wrong Record
RWD  Rewind Hard Disk
PCD  Punch Hard Disk
FCJ  Feed Card and Jam
TRD  Transfer and Drop Bit
RIG  Read Inter-record Gap
ERS  Erase Read-only Storage
UER  Update and Erase Record
MWC  Move and Wrap Core
HCF  Halt and Catch Fire
RTP  Reduce Throughput
LRB  Lose Record and Branch
RST  Rewind and Stretch Tape
JLR  Jump and Lose Return
UCM  Uncouple Comm lines and Branch
SSM  Stacker Select Memory
EXE  Execute Engineer
RWC  Rewind and Crash Heads
DIF  Disable Fuses
BRO  Branch and Overheat
MMF  Melt Main Frame
ENG  Enable Gravity
LUM  Lubricate Memory
BSI  Back up Sewer Immediate
SSP  Seek Spindle
ENA  Enable Everything
LTS  Loop Till Smokes
AIB  Attack Innocent Bystanders
DDC  Dally During Calculations
FLI  Flash Lights Impressively
LAP  Laugh At Programmer
SAI  Skip All Instructions
RPM  Read Programmer's Mind

As this chip is still in development, other useful opcodes are solicited...
:):):):)

+----------------------------------------------+------------------------+
|                                              |              __        |
|                                              |             / /\       |
|  Nathan F. Wallace                           |      ______/ /_/___    |
|  email: wallacen@beethoven.cs.colostate.edu  |     / ____  ______ \   |
+----------------------------------------------+    / /\__/ /\____|\/|  |
|                                              |   | |\/ / / /     \|/  |
|  Disclaimer: My opinions are my own, and are |   | || / /_/_____      |
|              not those of any other person,  |   | ||/_______  /\     |
|              organization, or supreme being. |   | ||\______/ / /     |
|                                              |   | ||      / / /      |
+----------------------------------------------+    \ \_____/ /_/__/\   |
|  "War is the art of deception."              |     \_____  _______/|  |
|                                 Sun Tzu      |      \___/ /\______|/  |
|                                              |          \_\/          |
|                                              |                        |
+----------------------------------------------+------------------------+