From: kgermann@zeos.com (Ken Germann)
Subject: Re: No VL-BUS for 486/50 Mhz?
Organization: Zeos International, Ltd
Date: Wed, 07 Oct 1992 15:39:00 GMT

In article <qolmnr8@zola.esd.sgi.com> blean@rwb.esd.sgi.com (Bob Blean) writes:
>In article <K6z-D#=@engin.umich.edu>, chyang@exemplum.engin.umich.edu (Chung Hsiung Yang) writes:
>|> 
>|> 	Someone posted earlier that since the VESA defines their clock
>|> speed only up to 40 Mhz, therefore using a processor above that speed 
>|> would be useless.  Is that true???

The specification states that the max speed for a VL-Bus Card is 40Mhz due
to electrical limitations. You can place a VL-Bus Device directly on
the motherboard, attach it to the VL-Bus, and access the VL-Bus device
that is surface mounted to the motherboard at up to 66 Mhz. 


The piece that is important about the VL-Bus is they made the spec compatible
with a 64-bit BUS. VL-Cards are backwards and forward compatible. i.e. You
can put a VL-Card that is 32-bit in a future 64 bit Vl-Bus connector and
it will work. You can put a VL-Bus card that is 64-bit in a 32-bit VL-Bus
connector it will work.


			ZEOS International, LTD. 
			  October 1st, 1992.

ZEOS is providing the summary of the VESA Local Bus specification to the 
users of the Internet to help answer some questions that have been recently
posted to several USENET News groups. This should help answer some of the
comparisions between the EISA and VESA specifications. Please contact VESA
at 408-435-0333 to get the complete VL-BUS 1.0 Standard. VL-Bus is a 
registered trademark of VESA.
 

		  Summary of the VESA Local BUS Specification


Number of VL-Bus Slots
	
	The VL-Bus design is capable of operating zero to three VL-Bus slots.
A slotless VL-Bus device would physically reside directly on the motherboard.
Regardless of the number of slots, the maximum number of devices supported is
three. Loading requirements allow some VL-Bus implementations to connect to the
CPU bus without buffering address, data, and control signals. Optionally, the
VL-Bus may buffer address, data, and control signals to meet the loading 
requirements of full three-slot implementations.

Maximum Number of VL-Bus Masters.

	A maximum of three bus masters are supported on the VL-Bus. The maximum 
number of bus masters on the system I/O bus is specified by that system I/O bus.

VL-Bus Connector Type and Location

The VL-Bus connector type is a standard 16-bit Micro Channel type connector.
The VL-Bus connector is located inline with a system I/O bus connector. This
layout allows full use of all system I/O bus slots if the VL-Bus board is not
occupying a slot. This arrangement also allows the VL-Bus add-in board access
to all system I/O features. A board may, for example, have a VL-Bus based 
video controller and a system I/O bus based parallel port on the same board.
Or if the VL-Bus board wants access to a feature such as the System I/O bus
REFRESH signal, it is free to use that feature on the system I/O bus. Use
any signals on the in-line system I/O bus connector is optional, as the 
VL-Bus connector has all the signals needed to fully support a VL-Bus device.

Host CPU

Design is optimized for single host CPU systems. The VL-Bus supports 386SX,
386DX, and 486-type host CPUs. Other types of host CPUs can be used if that
CPU's native control signals are converted into one of the supported CPU types.
Multiple-host systems should appear as single host systems to the VL-Bus 
controller.

Types of VL-Bus Devices

The VL-Bus' main objective is to support high speed video controllers. Other 
peripherals, such as hard disk controllers, LAN adapters, etc. can benefit
from the high-speed interface may also use the VL-Bus.

Interface Speeds

The VL-Bus operates up to 66MHz. Electrical characteristics of the Physical
VL-Bus connector limit the speed of a VL-Bus device operating across the 
connector (i.e, an add in board) to 40 MHz. The VL-Bus clock operates at
the same frequency and phase with the CPU clock. CPU's using double speed
clocks (386-type CPUs for example), must divide down the CPU clock before
driving the VL-Bus clock. Systems that dynamically swithc CPU speeds 
(such as portables) are supported. The system may also stop the CPU
clock entirely, provided that no DMA activity occurs during the time the
CPU clock is stopped.

Wait States

Assuming the maximum 20 ns address decode time, interface timing allows for
zero-wait-state write and one-wait-state read transfers up to 33 MHz. 
One-wait-state read and write transfers are supported from 40 MHz to 66 MHz.
The VL-Bus target may add additional wait states beyond these minimums by 
simply delaying the assertion of the end-of-cycle signal.

Interface Speed Dependancy

Interface Protocol depends on CPU speed, but the protocol selection and 
switching is invisible to all add-in boards, all software, and end users.
The BIOS may optionally have knowledge of the presence of the VL-Bus and
manipulate registers accordingly, but the VL-Bus always remains totally
transparent to all application software.

Future Compatibility

If an older technology VL-Bus video board is placed in a newer technology
VL-Bus backplane, the computer will continue to operate. A newer technology
VL-Bus board should operate in an older VL-Bus backplane transparently.

Future Write-Back Cache support

Provisions have been made to allow future support of advanced write-back cache
systems. A future revision of the VL-Bus specification will contain a full 
description of the protocol needed for VL-Bus targets and VL-Bus masters
to work with the host CPU containing a write-back cache. Boards designed
to the current revision of the VL-Bus will work properly in the systems
designed for the future revision.

16-Bit Support

Optimum data bus width is 32 bits. VL-Bus target bus sizing to 16 bits is 
supported. A 16-Bit CPU, such as the 386SX, is also supported. 16-bit 
peripherals are responsible for steering data to the CPU on the proper
style byte lanes when using 16-bit feature on the VL-Bus.

64-Bit expansion

The VL-Bus allows for a future expansion to 64-bit bus. The current versions
reserves the physical space necessary to allow such expansion. A 64-bit VL-Bus
board will operate in a 32-bit VL-Bus slot as a 32-bit device. A 32-bit VL-Bus
board will operate in a future 64-bit slot as a 32-bit device.

Identifying VL-Bus Cycles

A VL-Bus slave must always identify its own cycles. If an intelligent VL-Bus
controller knows (possibly via a BIOS setup routine) that cycle will be 
claimed by a VL-Bus target, it may identify the cycle as claimed by the VL-Bus
device before actually receiving the signal from that device.

DMA

Any VL-Bus target may be a DMA target to the motherboard DMA or system
I/O bus master. DMA slaves are not supported on the VL-Bus. For a VL-Bus 
device to initiate a DMA transfer, it must contain full bus master 
capibilities.

BUS Masters

Bus mastering on both the VL-Bus or system I/O bus are fully supported. An
active bus master and the target can both sit on the VL-Bus and transfer
to each other.

Software Compatibility

The VL-Bus is totally transparent to any BIOS or application software. 
Configuration of the interface is controlled entirely by hardware. 
Configuration of the VL-Bus device itself is accomplished in the
same manner as if that device were a system I/O device.

Please contact VESA if you have any questions about their specification
for the VESA Local Bus. VESA can be contacted by calling 408-435-0333
voice, and 408-435-8225 fax. 

 


>
>I know someone said so -- I noticed it too.  But everything else I've
>read says that the VL-bus is spec'd to work up to 66 mhz.
>
>
>-- Bob
>("Our life is frittered away by detail.  Simplify, simplify."  H.D. Thoreau)


-- 
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