From: pries@mips.com (Paul Ries)
Newsgroups: comp.arch
Subject: Re: MIPS R2000/R3000 cache design
Date: 16 Nov 92 08:24:43 GMT
Organization: Mips Technologies, Inc.
Distribution: world
NNTP-Posting-Host: meter.mti.sgi.com

uhe@cs.tu-berlin.de (Ulrich Hertlein) writes:


>Hi netlanders,

> I'm preparing a short introduction to the design of the R2000/R3000 CPUs and
>am having a little trouble with the design of the caches.

>The book I bought says that the cache size for the R2000 is variable from
>4 KB to 64 KB but doesn't state how the different cache size is handled by the
>cache controller.  Obviously, the tag memory for a 64 KB cache has got to be
>larger than for a 4 KB cache.  Does that mean that the CPU already has the
>tag memory for the entire 64 KB (or 256 KB in the R3000)?

> And how are the cache lines addressed?  The cache-controller has to know the 
>size of the available cache memory and again my book doesn't help.

> Is there anyone around that has knowledge of this?  Please respond asap, this
>is kind of urgent ...

>thanks a lot!

>desperately,
>-ulli
Well the R2000/R3000 primary caches are direct mapped.  The AdrLo pins are
used to index the primary cache.  The choice of cache size is made by deciding 
how many of the pins to hook up to the caches. Each word (32-bits of data plus 
8-bits of parity) of cache has a unique tag, so the tag array and the data array
are addressed the same way.  The tag array is external just like the data array
so adding additional data entries requires adding additional tag entries.  The 
width of the tag is what determines the minimum cache size.  There is no need 
for the processor to know the size of the cache.  The processor provides an 
index and is returned a tag.  The tag width is what determines the minimum cache
size.  If a larger cache size than the minimum is used then the tag will return
redundant information.  If number of cache rams were really critical the cache 
size could be used to ignore certain bits of tags allowing different tag widths
for different cache sizes...the R2000/R3000 does not support this.  The full
width of the tag is always required.

Anyway, the processor forms a physical address for each reference.  The lower 
bits of this address are put on AdrLo, which picks a location in the cache, 
which returns data and a tag.  The tag is compared against the upper physical 
bits and the data is used if the tag matches, otherwise a miss occurs.  
The sum of the number of lower bits used to index the cache, the number of 
address bits in a single word of the cache (4 bytes are two bits of address)
and the number of address bits in the tag must be at least the size of the
physical address space.  In the R2000/R3000 the tag has 20 address bits and the
physical address space is 32 bits (including user and kernel spaces), so
32-20-2=10.  So you must use at least 10 of the AdrLo bits, which address
2^10 words or 4 Kbytes.  The width of AdrLo determines the maximum size.
AdrLo width in the R3000 is 18, which includes byte address bits that are never
connected to the cache, so the maximum cache size is 2^18 or 256 Kbytes.

Hope this helps...if not, try constructing a small example, say a 5 bit address
space, with 4 bits of AdrLo and 3 bits of Tag.  This would allow caches of
size 1, 2 or 4 locations (since the bottom two bits are used for byte addressing
mainmemory only).

-- 
-Paul Ries DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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