From: raster@mystix.cs.uoregon.edu (Radek Aster)
Newsgroups: misc.jobs.resumes
Subject: MSCS+4yrs. SCSI,IPI,UNIX,Distributed Systems,Compilers
Date: 14 Oct 92 00:28:48 GMT
Article-I.D.: cs.1992Oct14.002848.28553
Organization: University of Oregon Computer and Information Sciences Dept.

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			     RADEK ASTER
			   815 Almaden St.
			   Eugene  OR 97402
				   
			Phone  (503) 686-1288
				   
		    Email : raster@cs.uoregon.edu
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Education History	
-----------------

M.Sc. Computer Science - Univ. of Oregon, 1992
B.A. Physics - Univ. of California Santa Cruz, 1986 - Highest Honors
B.A. Computer Science - Univ. of California Santa Cruz, 1986 - Highest Honors

Employment History
------------------

*	University of Oregon - Sept. '90 to June '92

	Graduate Teaching Fellow/Instructor

*	Pyramid Technology Corp. Mnt. View, CA - Sept. '88 to Aug. '90

	Hardware/Firmware Design Engineer

	Designed and implemented firmware for Dual-Port, High Performance IPI-2
	controller. Time sliced, triple-sequencer, bit-sliced hardware, which 
	was the engine for proprietary multi-threading kernel under which 
	controller processes executed. Real-time kernel orchestrated three 
	processors on top of shared memory architecture; shared memory 
	synchronization with spin-locks; dynamic memory management with bit 
	tables and fast bit-XOR memory de-fragmentation; interrupt initiated 
	non-preemptive multi-threading.

	Designed and implemented debugging platform, debugger and utility 
	software for IPI controller; UNIX platform. Bare-bones UNIX device 
	driver allowing access to low-level register manipulation machine 
	instructions was required to access controller IO registers. Debugger 
	allowed microcode download from external file system, manipulation of 
	controller registers and memory, execution of higher level controller 
	functions, error injection, multiple IO transfer operations through 
	UNIX process forking and completion polling.

	Debugged the prototype of IPI controller hardware. Major problems 
	included underestimated worst case IO buffer memory timing and random 
	asynchronous control signal glitch.

* 	Data Technology Corp., Santa Clara, CA - Aug. '87 to Sept. '88

	Firmware/Software Design Engineer

	Implemented firmware for full-SCSI bridge controller capable of 
	controlling two ST-506 disk drives. Single threaded 8085 processor; 
	allowing for overlapping seeks by SCSI connect-disconnect protocol.

	Designed an ICE (In-Circuit-Emulator) and assembler for a DTC 
	proprietary RISC and R/W channel processor chip. ICE included functions
	similar to those of the previously mentioned IPI debugger.

	Wrote firmware for high-speed POSTSCRIPT compatible printer. Multi-
	threaded non-preemptive kernel running on a single processor WEITEK 
	RISC architecture. Essential functions included real-time image 
	rendering, and Appletalk and RS-232 port management. Code written in C
	and assembly.

	Wrote the software for a SCSI level debugging tool. Manual or 
	automatic command packet construction; SCSI protocol driver; 
	Connect/Disconnect capability. Platform hardware was 80286 system with 
	interrupting SCSI host adapter.

* 	Spectra Logic Corp., Mnt. View, CA - Nov. '86 to Aug. '87

	Continuation Engineer

	Sustained and provided customer modifications to the hardware and 
	firmware of high performance, emulating SMD Disk and PERTEC Tape 
	controllers. UNIBUS and Q-BUS host bus architectures

Practical Academic Experience
------------------------------

Parallel Architectures  Coded an LU decomposition algorithm on the HYPERCUBE,
                        a message passing architecture. Studied cache coherence
                        aspects of distributed shared memory systems.

Distributed Systems	Wrote a client-server application using BSD sockets, 
                        utilizing UNIX forking and child management mechanism. 
                        Written in C and scheme. Application was a distributed
                        BAMming program. Also implemented Ricart and Agrawala's
                        distributed mutual exclusion algorithm.

Compilers		Wrote an optimizing compiler for an advanced Scheme-
			like, garbage-collected language. Target was the SPARC.
			Register, Let, Calls-to-Known-Procedures and some 
			peephole optimization implemented. Compiler written in
			Scheme. 


Other achievements
------------------

Completed a cross-country bicycle tour, from Raleigh, NC to Eugene, OR in 10 
weeks, covering 4000 miles.
Completed a bicycle tour from Anchorage, AK to Eugene, OR in 11 weeks, covering
3700 miles.

References available upon request
---------------------------------