From: cprice@mips.com (Charlie Price)
Newsgroups: comp.arch
Subject: Re: Multiplication on your favorite CPU (summary)
Date: 30 Sep 92 21:55:10 GMT
Organization: MIPS Technologies, Inc
NNTP-Posting-Host: lloyd.mti.sgi.com

In article <martin.717857097@bert> martin@math.rwth-aachen.de (  Martin Schoenert) writes:
>A while ago I asked for information about the multiplication instructions
>of various CPUs.   Here is my summary.  In the following 'latency'  means
>the number  of cycles from the issue of the multiplication instruction to
>the first instruction that can access the result.  'pipelined' means that
>several multiply instructions can  work their way through the pipeline at
>once.  'independent' means that other instructions can be issued  while a
>multiplication instruction is running.
>
>Points where I still don't have the information or where I am not certain
>are  marked with  '???'.  I would appreciate if someone could  fill those
>holes.  Of course corrections would also be very wellcome.
>
>MIPS R[23]000:
>
>  32x32 -> 64:      MULU
>    source:         <register> x <register>
>    destination:    lo-register (low) & hi-register (high)
>    latency:        12 cycles
>                    +2 cycles to move results from lo-hi-registers
>    pipelined:      no
>    independent:    yes
>    comment:        the maximal bandwidth is not one product every 14 cycles
>                    but one product every 16 cycles because the 2 instructions
>                    after 'mflo' and 'mfhi' must not be 'mulu'.

The reason that the two instructions preceeding a mflo or mfhi instructions
cannot be a multiply is related to the implementation.
The integer multiplier is an independent unit and once started it
runs to completion.
Consider the sequence
a:	mflo	r2	# get the low part from LO register
b:	mult	r3,r4	# r3 * r4, results into HI and LO

The pipeline looks like:
a:mflo	Ifetch	Reg	ALU	Mem	Wrtback
b:mult		I	R	A	M	W
c:			I	R	A	M	W
d:				I	R	A	M	W


If an exeption occurs between the Mem and Writeback stages of
the mflo instruction the multiply will already have been
started up.  It can't be stopped so it will overwrite the
contents of HI and LO.
To protect HI and LO contents, another multiply can't enter
the ALU stage until after the mflo/mfhi instructions have
completed their writeback stage.
This is another case where MIPS chose not to provide an interlock
in the R2000/R3000.



>MIPS R4000:
>
>  ???
>

I *knew* there was some news article that I lost needed to reply to
that I had lost.

MIPS R4000
  32x32 -> 64:      MULT/MULTU
    source:         <register> x <register>
    destination:    lo-register (low) & hi-register (high)
    latency:        12 cycles
                    +2 cycles to move results from lo-hi-registers
    pipelined:      no
    independent:    yes
    comment:        the maximum repeat rate is not 14 cycles
                    but is 16 cycles because the 2 instructions
                    after 'mflo' and 'mfhi' must not be a multiply.
  64x64 -> 128:	    DMULT/DMULTU
    source:         <register> x <register>
    destination:    lo-register (low) & hi-register (high)
    latency:        20 cycles
                    +2 cycles to move results from lo-hi-registers
    pipelined:      no
    independent:    yes
    comment:        the maximum repeat rate is not 22 cycles
                    but 24 cycles because the 2 instructions
                    after 'mflo' and 'mfhi' must not be a multiply.


-- 
Charlie Price    cprice@mti.sgi.com        (415) 390-4457
SGI (MTI) / MS 10U-178 / 2011 N. Shoreline Blvd / Mountain View, CA   94043   
Xref: sparky comp.arch:9654 comp.lang.misc:3176