From: lamaster@viking.arc.nasa.gov (Hugh LaMaster -- RCS)
Newsgroups: comp.arch
Subject: Re: Who will have the next killer micro?
Date: 8 Apr 92 16:32:04 GMT
Organization: NASA Ames Research Center, Moffett Field, CA


In article <1992Apr5.233338.2635@morrow.stanford.edu>, dow@nova2.stanford.edu (Keith Dow) writes:
|> Does anybody have a guess how much a Rambus interface will speed up
|> different microprocessors?

:

|> Also, how much would HP, the R4000 and DEC Alpha be sped up?  How
|> much is the bandwidth of a Rambus microprocessor compared to the
|> latest Cray?  Maybe the CM-6 will be based on chips with a Rambus
|> interface.


Funny, I was just wondering the same thing.  John McCalpin did a nice
summary a while back on long vector sustainable performance.  Looking
at vector add (most data moved/MFLOPS), we see the following (just a
small sample of the data he collected):



Cray Y-MP C90 - 16 CPU              4239.0
Cray Y-MP C90 -  1 CPU               390.8
Cray Y-MP     -  1 CPU               143.9
Convex  C3220 -  2 CPU                14.1
IBM RS6000/950                         8.2
IBM RS6000/320                         2.5
HP 9000/730                            2.3
SGI 4D/35                              2.0
Sun SS2                                1.2
DEC 5000/200                           1.0
:


While I don't have internal bus throughput on all systems, a range
of approximately 75-90% of the theoretical speed appears to be the
norm.  Extrapolating to a RAMbus-based system:

500 MB/sec/(8 bytes/word)/(3 Words/FLOP) = 20 MB/sec.
.75-.90 * 20. MB/sec = 15.6 - 18.75.  So, the back-of-envelope
calculation for a RAMbus-based system would put the expected
performance on this test at ~15-20 MFLOPS.

Now, the top HP and IBM systems already have the floating
point speed to use this bandwidth, as do MIPS R4000 systems
(I'm not sure about Sun's new chip - but I would guess that it
does, also.)  As will the DEC alpha, I'm sure.  So, I would
guess that most or all of the major microprocessors will be
able to profit from the increased memory bandwidth.  Assuming
that there is some reasonable way to interface with the
existing cache.

Conclusion:  These workstations, which were formerly memory-bandwidth
limited to a small fraction of the potential sustained vector performance, 
now *may* have the ability to achieve their true potential, at least for
the current crop of microprocessors, if this technology pans out.

The memory bandwidth available in something like the RAMbus chip is
about what is needed to actually give a user a "Cray 1 on a desktop".
It may turn some of the "world's fastest toy computers" into very
formidable systems.  While 15-20 MFLOPS is still a couple of orders of
magnitude away from a Cray Y-MP C90, it sure makes the middle ground
between workstation and supercomputer even more treacherous.  And,
if you believe that the RAMbus system will add little (or nothing, if
it eliminates the need for a second level cache) to the cost
of the system, it would put microprocessor-based CPUs in direct
price/performance competition with the largest systems, including
Cray.  Of course, it is still pretty difficult to make 200 workstations
act like a Cray, as has been discussed previously at length.  The
difference here is that the economy of scale associated with big
systems seems to be changing for real this time.

Anyway, those killer micros won't be able to do anything about I/O,
will they?  ;-)



P.S. on RAMbus:  Is there any speculation on how one might use RAMbus
to build a 4-8 CPU, plus IOPs, shared memory system with 4-8 GBytes/sec
total memory throughput?  Is RAMbus just a single-CPU solution, or can
it be used to produce a multiple-CPU server with high internal bandwidth?


--
  Hugh LaMaster, M/S 233-9,     UUCP:      ames!lamaster
  NASA Ames Research Center     Internet:  lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035-1000  Or:        lamaster@george.arc.nasa.gov
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