From: wyle@synopsys.com (Mitch Wyle)
Newsgroups: biz.comp.software
Subject: (May 4) SYNOPSYS INTRODUCES TEST COMPILER PLUS
Date: 24 Jul 92 02:28:24 GMT
Organization: Synopsys Inc.

Broadens test synthesis options to include JTAG, full scan and
constraint-driven partial scan, combinational and sequential ATPG.

MOUNTAIN VIEW, Calif.  May 4, 1992  Synopsys Inc. today announced Test
Compiler Plus*, a new product that incorporates Synopsys' recently
announced constraint-driven partial scan technology and sequential
automatic test pattern generation (ATPG).  The new product also includes
boundary scan synthesis, which automatically synthesizes Joint Test Action
Group (JTAG) standard 1149.1 test specifications and test patterns in
the 1149.1 protocol.

With Test Compiler Plus, designers can optimize for area, performance,
and testability by specifying fault coverage as an additional constraint.
Test Compiler Plus automatically selects the scan architecture optimal to
obtaining the target fault coverage without breaking area or performance
constraints.  The capability saves considerable ASIC design time because
the designer does not have to spend time selecting which sequential
elements to scan for optimal results.

"Test solutions that only provide high fault coverage are not enough,"
said Kelly Gomes, marketing manager for test synthesis products at
Synopsys.  "To be effective, a test solution must also automatically
minimize the area, speed, and cost impact on a design and provide
predictable results.

Test Compiler Plus, with its constraint-driven partial scan, gives
designers all these benefits."  Test Compiler Plus is part of the
family of test synthesis tools from Synopsys which also includes Test
Compiler*, the full scan test synthesis product that has been shipping
since March 1991.  Test Compiler Plus includes all the capabilities
of Test Compiler, and is compatible with the company's full range of
high-level design tools.


Boundary Scan Made Easy

Boundary scan test synthesis makes it easy and efficient for designers
to incorporate boundary scan into their designs without requiring
in-depth knowledge of the 1149.1 standard.  Using this capability of
the Test Compiler family, designers are able to synthesize the Test
Access Port (TAP) controller, control circuitry and boundary I/O pads,
and automatically connect JTAG to the design.  Designers may use the
capability to add 1149.1-compliant JTAG to designs without any manual
intervention.  Alternatively, if designers want to customize the boundary
scan synthesis to fit into a particular application, they can control
such parameters as the following:

	 connection to internal scan chains
	 inclusion of reset or ID register
	 instruction set to be used
	 boundary scan register order

Certified Libraries and Vector Formats

Test Compiler Plus uses the same interfaces and libraries as Test
Compiler, making it easy for designers to leverage the existing base of
certified libraries and vector formats.  Certified libraries are available
from numerous ASIC vendors, including Texas Instruments, Motorola, NCR,
Oki Semiconductor, and Toshiba.

Price and Availability

Test Compiler Plus runs on industry-standard platforms including:
Sun, HP/Apollo, and DEC.  The company currently anticipates shipping
the product in the fourth calendar quarter of 1992.  U.S. pricing for
Test Compiler Plus starts at $95,000; and for Test Compiler at $50,000.
Synopsys Inc. develops, markets and supports high-level design automation
(HLDA) software for designers of integrated circuits and electronic
systems.  The Company currently offers a comprehensive set of synthesis,
simulation and test tools, which are supported on the most widely used
UNIX workstations.

Test Compiler and Test Compiler Plus are trademarks, and Synopsys is
a registered trademark, of Synopsys Inc.  All other brands or products
are trademarks or registered trademarks of their respective holders and
should be treated as such.

For more information, contact:

Lois DuBois                    lois@synopsys.com
Synopsys Inc                   (415) 694 4255
700 E. Middlefield Rd.         (415) 965 8637 (fax)
Mountain View, CA  94043-4033  (800) 843 5669 x4255