HDTenEightyP/NetNews huggingface dataset:
From: hatay@spot.Colorado.EDU (Ferhat F. Hatay)
Subject: Re: problems with FFT cross spectra and other floating point operations
Organization: University of Colorado, Boulder
Date: Thu, 17 Dec 1992 17:33:44 GMT

In article <1992Dec17.030946.4899@news.media.mit.edu>   steve@media.mit.edu (Steve Mann) writes:
.
.
.
>  
>  I also noticed that when I subtract the DC from an image, and then do
>  an FFT, the element af(0,0) is not always zero.  In fact, as the image
>  gets bigger, I get values further and further from zero.  For a 256 by 265
>  image, the DC spike in the Fourier domain is so high that I can't see 
>  anything else in shade_surf,abs(af) or tvscl,abs(af).
>  
>  I wrote this little script which shows the accumulation of excess DC:
>  --------------------------------------------------------------------------
>  ; when I set N=91 or less, I get zero as expected.
>  ; when I set N=92 or more, I get a non-zero DC value in fft.
>  
>  N = 100;  size of square array
>  q=findgen(N)#findgen(N); create some arbitrary square array
>  ;Subtract the DC component
>  w=float(q)-norm(q,/one)/float((size(q))(1))/float((size(q))(2))
>  wf = fft(w,1);      Fourier transform of w
>  print,wf(0,0);      The DC component should be zero now.
>  ;I dont know why it is not zero.


I was under the impression that the FFT routines in IDL and WAVE
are basically one-dimensional-complex FFT routines. Please, forward me
info if this is wrong. 

I have played with one-d arrays of size 100-500 on IDL.  here is the script:

IdlMaster>  N=100
IdlMaster>  q = findgen(N)  
IdlMaster>  w = q-total(q)/float(N)
IdlMaster>  wf=fft(w,1)
IdlMaster>  print,wf(0,0)
(      0.00000,      0.00000)
IdlMaster>  print,total(w),total(q)
      0.00000      4950.00

IdlMaster>  N=500
IdlMaster>  q = findgen(N)
IdlMaster>  w = q-total(q)/float(N)
IdlMaster>  wf=fft(w,1)  
IdlMaster>  print,wf(0,0)
(      0.00000,      0.00000)
IdlMaster>  print,total(w),total(q)
      0.00000      124750.

-- 
Ferhat F. Hatay                        || Disclamer: |||||||||||||||||
Aerospace Engineering Sciences         || I speak for myself unless || 
University of Colorado, Boulder        || otherwise indicated.      ||
e-mail: hatay@spot.colorado.edu        |||||||||||||||||||||||||||||||
Newsgroups: comp.lang.idl-pvwave
From: turgeon@nereid.sal.ists.ca (Benoit Turgeon)
Subject: IDL base widget question.
Organization: Space Astrophysics Laboratory, ISTS, Toronto, Canada
Date: Mon, 14 Dec 92 06:31:44 GMT


Greetings,

	I am currently writing IDL widget applications.  RSI does not
recomment to use the keywords XSIZE, YSIZE, XOFFSET and YOFFSET when
used with a standard base widget since they are inflexible from 
platform to platform.  

	However, the use of these keywords is sometimes very useful.  For
instance, when you wish to confirm an option after the user presses
a button in a typical application.  Under X, the confirmation widget
would appear near the pressed button; the precise location is determined
by the programmer through the XtTranslateCoords(toplevel) and the NtXx
and NtNy values of the XtVaSetValues(child).  By setting the NtNx and NtNy
values, one can position the child close to the parent.

	In IDL, however, I don't know how to do this.  How can you retrieve
the pointer position of widget types other than WIDGET_DRAW ?  For instance,
how do you retrieve the pointer location after a BUTTON event is returned,
so that you can realize the child at NtNx and NtNy ?

	Finally, how do you get rid of the TITLE on a base widget ?  Setting 
the keyowrd TITLE to "" when declaring a base widget produces a title 
like "idl"...  Setting TITLE to " " still gives you a title bar...

	Thanks in advance,

	- Ben

P.S. I am running IDL V2.3.1 with SunOS 4.1.2 on a SPARC with X11R4 and TWM.
Newsgroups: comp.lang.idl-pvwave,comp.lang.idl
From: scowen@wfpc3.la.asu.edu (Paul A. Scowen)
Subject: Re: Postscript dump to a Laserwriter
Organization: Dept. of Physics & Astronomy, Arizona State University
Date: Fri, 18 Dec 1992 20:16:41 GMT

Hello all,

well this is a summary of the solution provided by Alan Youngblood at RSI to
the problems I pointed out in my original post.  Many thanks go to the
numerous individuals who replied.

1.  The problem of tvrd() not grabbing the entire window when the window was
scrollbarred, or off-screen.  This can be solved by setting the keyword
RETAIN to 2 in the widget_draw call.  It appears to work quite nicely.

2.  Producing b/w output in the PS environment from either a rolled color or
b/w window image.  Use bits_per_pixel=8, and use the following translation 
from tvlct:

	bwtable=bytscl(.3*r + .59*g + .11*b)
and then:
	tv, bwtable(image)

this does produce a convincing b/w output that a Laserwriter can handle, from
either rolled b/w or color.

3.  The use of both of these solutions appears to circumvent the CONTOUR
color problem before, since we don't need to use tvscl anymore.  

This does appear to solve all the issues that were plaguing me.  Thanks to
all who contributed.  I have been told by Youngblood (for all RSI-IDL users
out there) that RSI does NOT receive a newsfeed, and so all questions should
be emailed directly to them as well as being posted here.  Summaries of
solutions, such as this, would appear logical.

-- 
-------------------------------------------------------------------------------
Paul A. Scowen				INTERNET: scowen@wfpc3.la.asu.edu
Department of Physics & Astronomy		  uk1@spacsun.rice.edu
Arizona State University		Tel:      (602) 965-0938
Tempe, AZ 85287-1504			FAX:      (602) 965-7954
-------------------------------------------------------------------------------
Newsgroups: comp.lang.idl-pvwave
From: thompson@stars.gsfc.nasa.gov (William Thompson, code 682.1, x2040)
Subject: Re: Postscript dump to a Laserwriter
News-Software: VAX/VMS VNEWS 1.4-b1  
Organization: NASA/GSFC-Laboratory for Astronomy and Solar Physics
Date: Fri, 18 Dec 1992 18:00:00 GMT

In article <18DEC199211000500@stars.gsfc.nasa.gov>, I accidently left an
important command out of an example.  It should have read

	IMAGE = TVRD(0,0,!D.X_SIZE,!D.Y_SIZE)
	TVLCT,RED,GREEN,BLUE,/GET
	SET_PLOT,'PS'

	DEVICE, /COLOR, BITS_PER_PIXEL=8	;<--- Line left out.

	TV, IMAGE		;Note:  Not TVSCL
	TVLCT,RED,GREEN,BLUE
	SET_PLOT,'X'

Bill Thompson
Newsgroups: comp.lang.idl-pvwave
From: steve@media.mit.edu (Steve Mann)
Subject: Mapping and registering images with IDL
Organization: MIT Media Laboratory
Date: Sat, 12 Dec 1992 08:02:35 GMT

We have recently obtained a free 30 day trial version of IMSL/IDL, and
are trying to see if it will be useful for our image processing
requirements.  One of the things that we are trying to do is to
register multiple images that were taken from different camera angles
(but from the same viewpoint), into a 360 degree panorama.  We are
interested in texture mapping them onto a cylinder or onto a sphere,
or just simply doing a 3-D coordinate transformation.  While IDL
supports polywarp, what we want is really an exact perspective
resampling and not a bilinear approximation.  We see that tv claims to
support 3D coordinate transformations, which would allow us to tv an
image and then use tvrd to get it back again, if we could display it
obliquely so that it would go to an arbitrary quadrilateral.
tvscl,dist(100),/T3D appears to just display the image in a
rectangular manner.  How does one display it as an arbitrary
quadrilateral.  The file show3.pro does sort of what we want but it
calls polywarp which is not a true perspective transformation (e.g.
polywarp does not map straight lines to straight lines -- there is a
little curvature when there is large perspective involoved).

If anyone has used IDL to map an image onto a plane of arbitrary
orientation or onto an arbitrary conic, please let me know so we can
compare our implementations.  We've implemented these mappings in IDL,
in a crude sort of way, but it seems that IDL would support them
internally, as it does have the capability (e.g. shaded surface plots
with the shading set to the image bitmap shows that it can nicely
resample and texture-map images).

Similarly, if anyone's implemented a bicubic or biharmonic spline that
will work over arbitrary sampling (not just the tensor splines like
bsinterp) I would also be interested in hearing about it.

Lastly, given our applications, would anyone be able to suggest which
of {IMSL/IDL, RSI/IDL, PV-Wave} would be most suitable?

Thanks
steve@media.mit.edu
Newsgroups: comp.lang.idl-pvwave
From: thompson@stars.gsfc.nasa.gov (William Thompson, code 682.1, x2040)
Subject: Re: Postscript dump to a Laserwriter
News-Software: VAX/VMS VNEWS 1.4-b1  
Organization: NASA/GSFC-Laboratory for Astronomy and Solar Physics
Date: Fri, 18 Dec 1992 21:30:00 GMT

In article <1992Dec18.174615.4416@ennews.eas.asu.edu>, scowen@wfpc3.la.asu.edu (Paul A. Scowen) writes...
>In article <18DEC199211000500@stars.gsfc.nasa.gov>, thompson@stars.gsfc.nasa.gov (William Thompson, code 682.1, x2040) writes:
> 
>|> I don't understand this part.  I have trouble seeing how the internal commands
>|> like CONTOUR, TVRD, TVLCT, etc. can affect the values stored in the COLORS
>|> common block.
> 
>Well, so do I - but try it.  It does exactly that - completely forgetting the
>stretch you've set.

I guess I still don't know what you mean exactly.  Does it change the arrays
stored in the common block, or does it just change the color tables on the
display?  Could you give me a concrete example?

> 
>|> >1.  Given a color strectched image with contours overlaid, how can I produce
>|> >*either* color or laserwriter PS from a tvrd() call (ignoring the screen-
>|> >dump bugaboo)?
>|> 
>|> You can do a dump of a window with exactly the same colors that appear on the
>|> screen by using TVLCT,/GET to get the current (stretched) color table.  For
>|> example,
>|> 
>|> 	IMAGE = TVRD(0,0,!D.X_SIZE,!D.Y_SIZE)
>|> 	TVLCT,RED,GREEN,BLUE,/GET
>|> 	SET_PLOT,'PS'
>|> 	TV, IMAGE		!Note:  Not TVSCL
>|> 	TVLCT,RED,GREEN,BLUE
>|> 	SET_PLOT,'X'
> 
>Unfortunately, Bill, this does *not* work.  I've just tried it several times,
>with several different stretches, and the resulting PS file looks execatly
>the same for all versions.  It uses the default setting of b/w linear in the
>4bit mode, which is of no use to me.  This is my whole point.

This may be because I left out the following command:

	DEVICE,/COLOR,BITS_PER_PIXEL=8

which is crucial.  Sorry about that.  (I also forgot the DEVICE,/CLOSE at the
end.)

	(remainder of previous message deleted).

Bill Thompson
From: fang@bobcat.ent.ohiou.edu ( Xuefeng Fang ECE )
Newsgroups: comp.lang.vhdl
Subject: help required
Date: 12 Dec 92 21:04:41 GMT
Organization: College of Engg. & Tech., Ohio University, Athens, Ohio
Originator: fang@bobcat.ent.ohiou.edu

Hi, netters,

I am a beginer for the VHDL. I am using the Valid VHDL package.
After I finished analysis, I tried to make mg, however, I always
got such message "too many ('s" and mg was failed. I realy have
no idea what's wrong because I used the example given in the manual
provided by Valid Inc. and followed excatly the instructions step
by step.
Would anyone please help me to figure out this problem?
Thanks advanced.
From: gsingh@eng.wayne.edu (Gautam Singh, Graduate Student (ECE), 577-4725)
Subject: Re: Conversion of Verilog timing checks to VHDL?
Reply-To: gsingh@eng.wayne.edu
Organization: College of Engineering, Wayne State University, Detroit Michigan, USA
Date: Fri, 18 Dec 1992 10:27:41 GMT

I don't believe there are standard functions for doing this. However, you can quickly 
write your own functions (they will be typically constitute of a line or two) using the
signal attributes such as SIGNAL'DELAY, SIGNAL'ACTIVE, SIGNAL'EVENT,
and similar other attributes. If you have trouble doing that, contact me through 
e-mail, and I can mail back these functions to you.


Newsgroups: comp.lang.vhdl
From: koba@isl.Stanford.EDU (Fuminori Kobayashi)
Subject: user of VHDL from Univ. of Manitoba wanted
Organization: Stanford University
Date: Tue, 15 Dec 92 00:43:58 GMT

I got and installed VHDL from Univ. of Manitoba, but I have some
difficulties in using it:

  1."use components;" is not correctly identified.

  2.How to use the Xilinx library is not clear.

Is anyone using that package?

F. Kobayashi
Kyushu Inst. of Tech., Japan
visiting scholar, Stanford Univ.

--
koba@isl.stanford.edu
Newsgroups: comp.lang.vhdl
From: hugh@netcom.com (John Ivermost)
Subject: MVL usage survey
Organization: Netcom Online Communications Services (408-241-9760 login: guest)
Date: Wed, 16 Dec 1992 21:50:36 GMT

I am interested in determining how often various multi-valued logic types
and operations are used in VHDL designs.  If you are a design engineer,
or someone else with data on this subject, I'd like to know:

	1) which MVL types do you use regularly?
	2) do you use them primarily as scalar values or in vectors of values
	of that type?
	3) what vector operations (if any) do you regularly use on vectors
	of MVL types?

Please response BY EMAIL to hugh@netcom.com; if there is sufficient interest
expressed in email I will post the results.

Thanks in advance


Newsgroups: comp.lang.idl
From: strebel@spot.Colorado.EDU (STREBEL STEPHEN CURT)
Subject: look for code to define characters as symbols for a plot
Organization: University of Colorado, Boulder
Distribution: usa
Date: Sat, 19 Dec 1992 23:37:32 GMT

I am trying to find some code that will allow the user to easily define
ploting symbols.  (yes I do know about usersym)  What I have in mind is
some code that I could pass an ascii string, or a single character
and it would create a symbol of that character (without me having to create
all the vertices needed to make the character)

	If you have code that might do this, or something similar, please
send me email.

	-thanks
		stephen		(strebel@spot.colorado.edu)
From: cliffc@tekeda.PEN.TEK.COM (Clifford E Cummings)
Newsgroups: comp.lang.verilog
Subject: Re: execution of always blocks
Date: 18 Dec 92 23:57:08 GMT
Organization: Tektronix, Inc., Beaverton,  OR.

In article <1992Dec18.200153.25828@twisto.eng.hou.compaq.com> ehlers@tiktok.eng.hou.compaq.com (Steve Ehlers) writes:
>In article <1992Dec18.174451.11544@newsgate.sps.mot.com> rajesh@chdasic.sps.mot.com writes:
>>manley@optilink.COM (Terry Manley) writes:
>>
>>> always @(posedge Clk) c = b;
>>> always @(posedge Clk) b = a;
>>
>>If you have to use two always blocks, you could put
>>a #0 delay before the procedural assignment that you want
>>done last. That will make VerilogXL schedule that event
>>for processing at the end of that timestamp.
>
>Which is fine if you only care about which ONE is last.  If you have 
>three (or more) registers, you'll still have problems.  Using the
>non-blocking assignment operator ( <= ) will give you the behavior you want:
>
> always @(posedge Clk) c <= b;
> always @(posedge Clk) b <= a;

Intra-assignment timing provides another alternative
(The following example can be run as is).

/* Example of "intra-assignment" timing control across */
/* procedural blocks. Placing timing control on the    */
/* right-hand side (RHS) of the "=" causes temporary   */
/* storage of the RHS variable, and schedules future   */
/* assignment using the stored RHS value.              */
/*                                                     */
/* Cliff Cummings - 12/18/92                           */

`timescale 1ns /100ps
module Qintra;
  reg [3:0] a, b;
  reg clk;

  // Wait 1 time unit to allow initial assignment of "b"
  always #1 a = @(posedge clk) b;

  // Wait 1 time unit to allow initial assignment of "a"
  always #1 b = @(posedge clk) a;

  initial begin
      clk = 0;
      forever #10 clk = ~clk;
    end

  initial begin
      $timeformat(-9, 2, "ns", 10);
      #1 $monitor($time, ": a = %h,  b = %h", a, b);
    end

  initial begin
      a=4'h5; b=4'ha;
      #100 $stop;
      #100 $finish;
    end
      
endmodule
Newsgroups: comp.lang.verilog
From: ehlers@tiktok.eng.hou.compaq.com (Steve Ehlers)
Subject: Re: execution of always blocks
Organization: Compaq Computer Corp.
Date: Fri, 18 Dec 1992 20:01:53 GMT

In article <1992Dec18.174451.11544@newsgate.sps.mot.com> rajesh@chdasic.sps.mot.com writes:
>manley@optilink.COM (Terry Manley) writes:
>
>> always @(posedge Clk) c = b;
>> always @(posedge Clk) b = a;
>
>If you have to use two always blocks, you could put
>a #0 delay before the procedural assignment that you want
>done last. That will make VerilogXL schedule that event
>for processing at the end of that timestamp.

Which is fine if you only care about which ONE is last.  If you have 
three (or more) registers, you'll still have problems.  Using the
non-blocking assignment operator ( <= ) will give you the behavior you want:

 always @(posedge Clk) c <= b;
 always @(posedge Clk) b <= a;
Newsgroups: comp.lang.verilog
From: llagos@renoir.die.udec.cl (Leonardo LAGOS M)
Subject: Re: execution of always blocks
Date: Sat, 19 Dec 92 12:43:45 GMT
Organization: Universidad de Concepcion, Concepcion - Chile
X-Newsreader: TIN [version 1.1 PL7]

Alan Bair (abair@parsons.sps.mot.com) wrote:
: In article <13665@optilink.COM> manley@optilink.COM (Terry Manley) writes:
:>   More specifically why doesn't the following work:
:>
:>   reg a,b,c;
:>
:>   always @(posedge Clk) c = b;
:>   always @(posedge Clk) b = a;
:>
:>	always @(posedge Clk)
:>	  fork
:>		c = b;
:>		b = a;
:>	  join
:>
: However, this has the same problem as the two always blocks, there is no
: control over which will take place first. I can't remember the exact syntax,
: but there is a way to specify that the values of b & a are first saved and
: then the assignments take place. This allows them to occur in any order, but
: get the results you are after.
: 
 What you want to do is something like this :
    always @(posedge Clk) c <= #1 b;
    always @(posedge Clk) b <= #1 a;

 This code means " evaluate b at posedge of Clk, save this value, and assign
 it to c 1 time later."
 This syntax is also called "non-blocking assignment" (or similar).
 Idem for the second always.

:>   --
:>   dave
:>   manley@optilink.com
:>
: --
: Alan Bair             		AMCU DSCS
: Motorola, Inc.            	    (Design Software &
: Mail Stop OE-320		     Computer Services)
: 6501 William Cannon Dr. West	
: Austin, TX  78735-8598          abair@parsons.sps.mot.com

Hope this can help you,

Leo

--
            .                  e-mail : llagos@renoir.die.udec.cl
         |\ | /                cc     : llagos@halcon.dpi.udec.cl
     ----| >|<-----
         |/ | \               Departamento de Ingenieria Electrica
         '     `                   Universidad de Concepcion
Newsgroups: comp.lang.verilog
From: tpham@engin.umich.edu (Tony Pham)
Subject: Verilog <--> VHDL translators
Date: Thu, 17 Dec 92 21:46:18 EST
Organization: University of Michigan Engineering, Ann Arbor
Distribution: usa

Does anyone know of any good verilog to vhdl or
vhdl to verilog translators?  It would be quite
helpful for my school work at this point.  Any available
public domain tools would be a big plus since my budget
is limited.  Appreciate any replies.  Thanks.
Newsgroups: comp.lang.verilog
From: gord%jericho.uucp (Gord Wait)
Subject: Ignore this dumb test message!
Organization: S-MOS Systems, Inc. (Vancouver Design Center)
Date: Tue, 15 Dec 1992 18:55:44 GMT


Sorry for the test message.

Hi Carly!
-- 
Gord Wait 	SMOS Systems Vancouver Design Centre
uunet!jericho!gord
gord%jericho@uunet.uu.net

Newsgroups: comp.lang.verilog
From: abair@parsons.sps.mot.com (Alan Bair)
Subject: Re: execution of always blocks
Organization: AMCU, Motorola Inc., Austin, Texas.
Date: Fri, 18 Dec 1992 09:07:26 GMT

In article <13665@optilink.COM> manley@optilink.COM (Terry Manley) writes:

   Ok, I've got a 'newbie' question.

   What's the story with this language?

Since I just took a class on Verilog, I'll try to answer your question.
It's a good test to see if I learned anything :) I am sure I will be
corrected if I am wrong.

   More specifically why doesn't the following work:

   reg a,b,c;

   always @(posedge Clk) c = b;
   always @(posedge Clk) b = a;

The assignments occur on the posedge of the Clk, but there is nothing in
this structure that says which should occur first. In theory they should
occur at the same time, but this setup does not guarantee this. If you
want that you should use the fork ... join construct.

   When the following does:

   always @(posedge Clk)
     begin
	   c = b;
	   b = a;
     end

In this case, the action will start on the posedge of Clk. Then, because
you used a begin ... end block, versus the fork ... join, the assignments
will take place sequentially. 

	c gets the value of b
	b gets the value of a

This all takes place in zero time. To have these occur in parallel, you
could use:

	always @(posedge Clk)
	  fork
		c = b;
		b = a;
	  join

However, this has the same problem as the two always blocks, there is no
control over which will take place first. I can't remember the exact syntax,
but there is a way to specify that the values of b & a are first saved and
then the assignments take place. This allows them to occur in any order, but
get the results you are after.

   In the first case for some reason verilog may perform the "b = a"
   assignment first, thereby throwing away the expected value that c was
   going to get.  We've even seen cases where in a given simulation
   sometimes it works correctly, sometimes it doesn't.

   Ideally one would want the data transfer at the posedge of the clock
   to behave like digital logic, that is it would, in this case behave
   like a shift register.  Instead we get what looks like a shift
   register with a bad hold time problem. 

   So what is the story with multiple always blocks?
   Is this something to worry about between modules?
   How about between modules in different files?

If the actions occur within separate modules, you need to have event controls
to ensure the actions take place in the order you want if that matters.


   --
   dave
   manley@optilink.com

--
Alan Bair             		AMCU DSCS
Motorola, Inc.            	    (Design Software &
Mail Stop OE-320		     Computer Services)
6501 William Cannon Dr. West	
Austin, TX  78735-8598          abair@parsons.sps.mot.com
Newsgroups: comp.lang.verilog
From: jcooley@world.std.com (John Cooley)
Subject: Re: verilog and synthesis
Organization: The World Public Access UNIX, Brookline, MA
Date: Sun, 13 Dec 1992 04:08:16 GMT

From: ekenberg@down.hep.upenn.edu (Tor L. Ekenberg)

> I am looking for information about using Verilog for synthesis. I guess
> something about what constructs are prefered, if there are some
> companies that provide tools, etc. I am completely new to the field
> of synthesizable Verilog so any information will be useful.

Tor, you may wish to join the E-mail Synopsys User Group (ESNUG) if
your company already owns a copy of Synopsys.  You'll find we discuss
issues just like you're asking.  To join, all you have to do is send
me e-mail expressing an interest in subscribing.

                                               - John Cooley
                                                 ESNUG Moderator


 ===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how others dealt
 with it ?  Join the E-Mail Synopsys Users Group!  To join, E-mail me today! 
 ===========================================================================
      !!!     "It's not a BUG,    | Preferred Address: jcooley@world.std.com
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Newsgroups: comp.lang.verilog,comp.lang.vhdl