HDTenEightyP/NetNews huggingface dataset:
From: rob@wzv.win.tue.nl (Rob J. Nauta)
Newsgroups: comp.security.misc
Subject: Re: Summary: Re: Disabling telnetd and ftpd etc
Date: 2 Sep 92 20:51:00 GMT
Organization: Sex, UNIX & Rock 'n Roll

daniel@vcp1.vcp.monash.edu.au writes:

>So the upshot is: -
 
>* Don't run PC-NFS
>* Don't run YP or NFS
>* disable telnetd, ftpd, tftpd and r*d daemons and any others not needed
>* get the router set up to disallow any packets for the Iris from outside
>  the subnet to reach it.
 
>and the system will be as secure as the lock on the door of its room.
 
Yes, but also not as useable. For instance, if you block all traffic to
your network, why bother connecting ? Just cancel your Internet
subscription. If you deny everything, you won't receive any mail nor
news, is that what you want ?

Furthermore, it's ok to run NIS and NFS (although with one machine it's not
needed), if you set up your router to block access to ports 111
and 2049/UDP (last one for NFS).

Rob
-- 
/-----------------------------------------------\	Never		   ,==.
| Rob J. Nauta, UNIX computer security expert.	| 	 Apologize,	  /@  |
| rob@wzv.win.tue.nl, Phone: +31-40-837549	| 	  Never		 /_  <
| Feel free to email me for free advice		|	   Explain.	=" `g'
Newsgroups: comp.lsi
From: hl@cypress.com (Hank Lim)
Subject: How to obtain source for "Bisim"
Originator: hl@as07
Keywords: bicmos, ecl
Organization: Aspen Semiconductor, San Jose, CA
Date: Fri, 28 Aug 1992 16:37:49 GMT


The 1988 ICCAD has a paper on "Bisim: A Simulator for Custom
ECL Circuits" by Kao et. al.  The authors mention in the summary
that they plan to immplement their algorithms to support BiCMOS
circuits.  Anyone have any further references.  Also, is this
simulator available through Stanford U. or is it DEC proprietary?
They mention in the paper that it is implemented in 3300 lines
of C++ and was used in the DEC Titan project.

Premature Thanks,
Hank

Newsgroups: comp.lsi
From: yooho@ursula.ic.cmc.ca (Yoo Ho Cho)
Subject: Re: Question regarding probe pads
Keywords: probe pads
Organization: Canadian Microelectronics Corporation
Distribution: can
Date: Fri, 4 Sep 1992 19:56:10 GMT

I think probe pads should be kept out of the core if possible. In some 
cases, such as automatic placed and routed systems, it is more convenient
to use a probe pad cell and let the cell be routed by the P&R tool.

If you are doing a hand layout, put the pads outside the core. Make them 
50x50 or slightly larger. The size really depends on how much practice
you have probing etc. I prefer the pads to be outside the core and 
somewhere in the 70 - 100 microns square range. This way I have quite
a bit of space to work with and I'm not worried about destroying something 
while moving the probes.

Yoo Ho Cho
From: jack@tequila.vlsi.auc.dk (Jack Bukholdt Andersen)
Newsgroups: comp.lsi
Subject: Re: PIPELINED IIR(RECURSIVE) STRUCTURE?
Date: 28 Aug 92 12:45:12 GMT
Reply-To: jack@tequila.vlsi.auc.dk
Organization: Aalborg University Center, Denmark

Show me yours - and I'll show you mine !

Jack...
Newsgroups: comp.lsi,comp.lsi.cad
From: sridevan@elec.uq.oz.au (Sri Parameswaran)
Subject: E-mail address of Mitchell Mlinar
Keywords: Email address
Organization: Prentice Centre, University of Queensland
Date: Sun, 30 Aug 1992 09:49:25 GMT

Could some one out there provide me with Prof Mitchell J. Mlinar's
email address. I think he is or was attached to the Dept of Electrical
Engineering, University of Southern California.


Thanks

-- 
Sri
Sri Parameswaran Dept. of Electrical & Computer Engineering, 
University of Queensland, Australia. 
Phone:+61-7-365-4190 Fax:+61-7-365-4999 INTERNET: sridevan@s1.elec.uq.oz.au
--
Sri
Sri Parameswaran Dept. of Electrical & Computer Engineering, 
University of Queensland, Australia. 
Phone:+61-7-365-4190 Fax:+61-7-365-4999 INTERNET: sridevan@s1.elec.uq.oz.au
Newsgroups: comp.lsi
From: aranake@cse.uta.edu (Sandeep Suresh Aranake)
Subject: Does IRSIM under-estimate chip performance ?
Organization: Computer Science & Engineering, Univ. of Texas at Arlington
Distribution: usa
Date: Thu, 3 Sep 1992 19:52:35 GMT

I am posting this query on behalf of my friend. Please send your replies
directly to fernande@csr.uta.edu

--

Hi,
	I have designed a floating point adder to work at 62.5MHz. My
Irsim simulation runs at 61.7MHz but I have heard that Irsim is heavily 
loaded against these designs and hence my actual fabricated chip should
run at least at the same speed, if not faster.

Does anyone have any experience in this regards ie. has anyone had a
chip fabricated whose simulation was done using Irsim and if so, what
was the factor of speed improvement ?

Denzil Fernandes
fernande@csr.uta.edu

Newsgroups: comp.lsi.cad
From: hagerman@ece.cmu.edu (John Hagerman)
Subject: Re: How to measure regularity in CDFGs ? Help !!
Organization: Carnegie Mellon University
Distribution: usa
Date: Wed, 26 Aug 1992 17:08:39 GMT

In article <1992Aug25.173351.7393@cse.uta.edu> aranake@cse.uta.edu (Sandeep Suresh Aranake) writes:

   Can someone suggest a metric to represent the regularity
   in digital systems described using CDFGs? 

A few references from a quick look through the '92 DAC proceedings:


"Time Constrained Allocation and Assignment Techniques for High
Throughput Signal Processing", W. Geurts, F. Catthoor, H. De Man.

"Partitioning by Regularity Extraction", D. Rao, F. Kurdahi.

"Functional Synthesis Using Area and Delay Optimization", E.
Rundensteiner, D. Gajski.


These may not answer your question (if I understand it correctly), but
they may at least point toward an answer.

- John
--
hagerman@ece.cmu.edu
Newsgroups: comp.lsi.cad
From: fred@mcnc.org (Robert Heaton)
Subject: Public Domain Verilog Parser
Keywords:  Verilog parser
Organization: MCNC Center for Microelectronics, RTP, NC
Distribution: usa
Date: Fri, 4 Sep 1992 18:26:46 GMT

I am looking for a public domain verilog parser so that I can interface
an existing simulator to Verilog HDL.  Does anyone know where I can find
one?  Is it available through anonymous ftp?   Thanks!!
							Fred Heaton


Newsgroups: comp.lsi.cad
From: libove@server.alf.dec.com (Jay Vassos-Libove)
Subject: "Magic" router software assistance?
Organization: Digital Equipment Corporation, Atlanta Customer Support Center
Date: Thu, 27 Aug 1992 14:00:30 GMT

POSTED FOR A FRIEND. PLEASE REPLY DIRECTLY TO HIM at
ACDC018@SAUPM00.BITNET

=============================================================================

Hi:

I wanted some help on the Magic router.

We have a circuit with 126 gates placed on the layout floor using a placement
program. We are using the maze router of MAGIC (:route command) to route
the interconnections. The connections are specified by a Netlist file
generated automatically.
The router fails to get past the "Global Routing" stage after running for about
45 min. It just keeps on swapping, using very little cpu. Then it aborts
saying that the system is out of "swap space" although we have 64Mb swap.

It does not even route a 2-point net, if the terminals are far apart in the
presence of all 126 gates,  although
it routes the Vdd and GND nets for the entire circuit in a few minutes.
If we make smaller windows then it does route the nets inside it.
We have tried with both small and large separation between cells.
We have used the router with another, albiet regular structure, circuit
with about 600 gates and had no PROBLEMS !, in a max of 10min ( no swapping ).

We would be grateful for any hints on how to overcome this !

With Thanks,
Asjad Mumtaz
Acdc018@Saupm00.Bitnet

___________________________________________________________________________
Asjad M.T.Khan           |  Department of Computer Engineering
KFUPM #606               |  King Fahd University of Petroleum and Minerals
Dhahran 31261            |  Dhahran, Saudi Arabia
Saudi Arabia             |
E-mail:Acdc018@SAUPM00   |
_________________________|_______________________________________________
--

Jay Vassos-Libove                  libove@alf.dec.com
Digital Equipment Corporation      decwrl!alf.dec.com!libove
Atlanta Customer Support Center    Opinions? They're mine, mine, all mine!
Alpharetta, Georgia                and D.E.C. Can't have 'em!
From: arrigo@cube.sublink.org (Arrigo Benedetti)
Newsgroups: comp.lsi.cad
Subject: Node voltages limiting techniques in circuit simulators
Date: 1 Sep 92 09:29:21 GMT
Reply-To: arrigo@cube.sublink.org
Organization: Arrigo Benedetti


I'm designing an experimental multilevel MOS circuit simulator and I have
a few questions about Spice3 node voltages limiting techniques.
Spice3 limits the iteration change of MOS terminal voltages with an
algorithm coded in the DEVlimvds(), DEVpnjlim() and DEVfetlim() functions
in the devsup.c file. I studied the code contained in these routines,
and, apart from the DEVpnjlim function, which seems to me a new version
of the Colon algorithm as described by Nagel, I didn't find any reference
to the algorithms implemented by DEVlimvds(), DEVfetlim().
Is there any paper describing the theory behind these routines, or, as I
am suspecting, are they just heuristic ?
This question is important to me, as I found that the Newton algorithm
applied to the circuit equations rarely converges if not used with
some damping strategy.
How does the Spice3 damping strategy compare to the one used by
simulators of the first 70's, i.e. ECAP II, etc.?
I am referring to the damping strategy where the full iteration
update is multiplied by a scalar in the (0,1] interval which is chosen
to minimize some norm of the nonlinear equations vector.

	Arrigo Benedetti

I will summarize any reply to the net, if there is enough interest
-- 
Arrigo Benedetti             e-mail: arrigo@cube.sublink.org (preferred)
University of Bologna                benedett@deis01.cineca.it
undergraduate student (EECS)         
Via S. Agata, 11               Tel:  (home)   +39 59 224929
41100 Modena - Italy                 (office) +39 59 216688 (fax) +39 59 220727
Newsgroups: comp.lsi.cad
From: rgupta@sirius.Stanford.EDU (Rajesh K. Gupta)
Subject: Re: How to measure regularity in CDFGs ? Help !!
Keywords: High-level Synthesis,allocation etc.
Reply-To: rgupta@sirius.Stanford.EDU (Rajesh K. Gupta)
Organization: Stanford University
Distribution: usa
Date: Tue, 25 Aug 92 21:29:43 GMT

> 
> Can someone suggest a metric to represent the regularity
> in digital systems described using CDFGs? 
> 
> I have allocation program which scans input data-flow graph,
> extracts operator-operator interaction and uses this
> information during allocation. I want to plot a graph of
> some metric representative of regularity in DFG and
> the quality of the allocation. I tried few tricks but
> none gave me a unique quantity to describe regularity.
> Your help and/or pointer to info will be greatly
> appreciated.
> 
> sandeep
> 

If you haven't already done so, you may want to check out
notions of "operator similarity" metrices used by McFarland
(dac 83, I think).
I believe he refined it in his bottom-up design (BUD) system
that was published in Trans. CAD sometime last year. 

There was also a paper from somebody from UC Irvine (Kurdahi?)
in DAC92 on regularity extraction from DF graphs.

Sorry, couldn't be any more specific for now.



Rajesh

725-1776 CSL Modulars I				rgupta@sirius.stanford.edu
From: lld@concept.de (Lothar Linhard)
Newsgroups: comp.lsi.cad
Subject: EDIF viewer Demo at EURO-DAC
Keywords: EDIF schematic
Date: 28 Aug 92 10:51:48 GMT
Organization: concept engineering GmbH, D-7800 Freiburg, Germany



At the EURO-DAC '92 we will introduce a new product called:

	ceBox EDIF viewer.

It is an easy-to-use tool to comfortably analyse any EDIF 2.0.0 file.
Supported EDIF views are SCHEMATIC, GRAPHIC and NETLIST.

Especially engineers who are not fully familiar with EDIF, will
find it easy to browse through both, the EDIF data structures and
the design hierarchy.

The tool is entirely coded in C++ and runs on SPARCstations. An
optional "EDIF++" interface will enable any programmer to adapt
customer specific interface software - e.g. for mapping or similar tasks.

If you are interested, please come and have a demonstation and
ask for more information. You will find us at the EURO-DAC
at the booth of:

	SUN Microsystems (booth 5207).


Some features of the viewer:
	- multible examination windows
	- design hierarchy navigator
	- graphic window displays schematics and symbols
	- select-and-info mechanism
	- EDIF source code view of selected objects
	- connectivity analyses
	- postscript output

Lothar Linhard

================================================================================
Lothar Linhard                         |  Tel.:  ..49-761-473099
concept engineering GmbH               |  Fax.:  ..49-761-441063
Burkheimer Str. 10                     |  
D-7800 Freiburg (Germany West)         |  
--------------------------------------------------------------------------------
Email:                       lld@concept.de
   or: (uucp domain)         lld@concept.uucp
   or: (uucp notation)       ...!unido!concept!lld
================================================================================
Newsgroups: comp.lsi.cad
From: cyc@z.eecs.umich.edu (Yi-Chieh Chang)
Subject: Printing magic files
Organization: University of Michigan EECS Dept., Ann Arbor, MI
Date: Thu, 3 Sep 1992 17:23:57 GMT

I have posted a request for printing Magic design files and I got
the flea ([F]un [L]oveable [E]ngineering [A]rtist) program. 
Somehow, whe I tried to compile it, I got the following error
message:

ld: Can't open -dp
ld: No such file or directory
*** Error code 1

The error comes from this command
 ld -dc -dp -e start  -X -o flea /usr/lib/crt0.o main.o buildbox.o
outpu.o readtech.o readmagic.o readcif.o cifobjs.o tilde.o
devices.o PLdevice.o PSdeice.o  -lm -lc -ltermcap

Any body has any idea how to get rid of this problem ?
And also is -X correct, or should it be -X11 ?

Yi-Chieh
Newsgroups: comp.lsi.cad
From: peter@sun.math.usfca.edu (Peter Pacheco)
Subject: busnet
Organization: University of San Francisco
Date: Sun, 30 Aug 1992 20:05:32 GMT
X-Posted-From: sun.math.usfca.edu
X-Posted-Through: sol.ctr.columbia.edu

I'm trying to find out about a program called "busnet".  I've been told that 
it uses the method of conjugate gradients to solve the linear systems 
corresponding to circuits that contain only resistors and voltage or current 
sources.  If this is the case, do they use any preconditioners?  If so, 
which one(s)?  Any additional information will be much appreciated.  Please 
reply by email.  Thanks very much.

					Peter Pacheco
					peter@sun.math.usfca.edu
Xref: sparky comp.lsi.cad:911 comp.lsi:566 comp.lsi.testing:193
From: gs@mi.diab.se (Greger Sernemar)
Newsgroups: comp.lsi.cad
Subject: AutoCad
Date: 28 Aug 92 14:54:49 GMT
Distribution: comp
Organization: Diab Data AB, Sweden.

Is there any news group about autocad ?

I use it on an Zenit PC and just started to use it, I have an old version, 2.5,
but it works fine for my needs.

I wonder if it's possible to get hold on defined block-symbols for IC-circuits
and other electronic symbols somewhere on the net ?

Thanks.

Greger Sernemar
--
-----------------------------------------------------------------------------
Greger Sernemar,  Diab Data AB   ####                    ####
SNAIL:  Box 2029                 #   # ###   #   ####    #   #   #  #####  #
        S-183 02 Taby, Sweden    #   #  #   # #  #   #   #   #  # #   #   # #
ANALOG: +46 8 638 94 00          #   #  #  #   # ####    #   # #   #  #  #   #
FAX:    +46 8 792 05 61          #   #  #  ##### #   #   #   # #####  #  #####
EMAIL:   gs@diab.se or           #   #  #  #   # #   #   #   # #   #  #  #   #
        mcvax!sunic!diab!gs      ####  ### #   # ####    ####  #   #  #  #   #
X400:  C=SE  ADMD=TeDe  PRMD=Diab  S=Sernemar   G=Greger
-----------------------------------------------------------------------------
Newsgroups: comp.lsi.cad
From: hagerman@ece.cmu.edu (John Hagerman)
Subject: Re: How to measure regularity in CDFGs ? Help !!
Organization: Carnegie Mellon University
Distribution: usa
Date: Tue, 25 Aug 1992 20:11:24 GMT

In article <1992Aug25.173351.7393@cse.uta.edu> aranake@cse.uta.edu (Sandeep Suresh Aranake) writes:

> Can someone suggest a metric to represent the regularity
> in digital systems described using CDFGs? 

What do you mean by "regularity"?

- John
--
hagerman@ece.cmu.edu
Newsgroups: comp.lsi.cad
From: mm@hela.iti.org (Michael McFarland)
Subject: Info please (from CAD vendors)
Followup-To: mm@iti.org
Summary: CAD software info wanted
Organization: Industrial Technology Institute
Date: Fri, 4 Sep 1992 17:51:48 GMT




I am working on a project at the Industrial Technology Institute to
develop a test system (or suite of testing tools) for use in the
development of CAD and CAE software.  In particular, the test system is
for software that will use the forthcoming Standard for the Exchange of
Product Model Data (STEP).  We would like to learn about software
development and testing that is done on CAD and CAE software products.

If you are directly involved in the development or testing of CAD or
CAE software, we would appreciate it if you would answer the following
questions.  In return for your input, we will send you a write-up of
our findings if you so request.

Please include your name, your company name, your email address,
telephone number and physical mail address.

(In case the return address on this message is garbled, please respond
to mm@iti.org)

1.  What sorts of methods and tools do you use for software
development?  (Such as use of a software life-cycle model; a method
like Yourdon, DeMarco, Ward/Mellor, Object-oriented, Gane/Sarson,
Jackson SA/SD, Bachman data model diagrams, etc.; things like code
generators, configuration control systems, debuggers; and CASE
environments such as Softbench, PCTE, STP, etc.)

2.  What is your development platform(s)? (h/w and o/s and environment)
	. Unix, OS/2, DOS, MVS, VMS,  ...
	. GUI builders

3.  What is your opinion about your development environment?  Is it
helpful or a hindrance?

4.  What sorts of methods and tools do you use for testing software?
Do you have a formal, documented procedure or is it ad hoc?  How do you
develop test cases?  Are the people responsible for testing the same
people who develop the software?

5.  How is your testing program integrated with your software
development methodology (i.e. CASE tool)?

6.  Have you ever developed software that had to read or write files
that conform to a standard such as IGES or DXF?  If so, how did you
verify the correctness of your software?


Newsgroups: comp.lsi.cad
From: engp1261@nuscc.nus.sg (Teng-Kiat Lee)
Subject: ICCAD 92 dates?
Reply-To: engp1261@nuscc.nus.sg
Organization: Dept. of EE, National Univ. of Singapore
Date: Wed, 26 Aug 1992 05:53:15 GMT


Hello folks. Can some one tell me the dates for ICCAD 92? The
Call-for-paper clearly stated Nov 8-12, but the recent announcement
in Circuits and Devices mag says it's from Nov 10-14. Which is the
right one?

Regards,
----------------
Teng-Kiat Lee                        VLSI CAD & Design Lab
Internet: engp1261@nuscc.nus.sg      Microelectronics Div.
Bitnet:   eleleetk@nusvm.bitnet or   Dept. of Electrical Engineering
          ltk@nuseev.bitnet          National University of Singapore
Voice:    (065)-772-6319             10 Kent Ridge Crescent
          (065)-467-1518             Singapore 0511
----------------------------------------------------------------------          
Newsgroups: comp.lsi.cad,comp.lsi
From: burman@sol.cs.wmich.edu (SURENDRA BURMAN)
Subject: Info on MCM Books
Keywords: MCMs
Organization: Western Michigan Univ. Comp. Sci. Dept.
Date: Sat, 29 Aug 1992 03:08:06 GMT

I am looking for the references of books on Multichip
Modules (MCMs), published or to be published in near
future. If needed, a summary of the responses will be
posted on the net.

Thanks in advance.

-- Burman

Surendra Burman
Department of Computer Science
Western Michigan University
Kalamazoo, MI 49008 
Phone: 616-387-5645
Email: burman@cs.wmich.edu
Newsgroups: comp.lsi.cad
From: dow@nova2.stanford.edu (Keith Dow)
Subject: Re: Chip design times
Organization: Stanford University
Date: Sat, 29 Aug 1992 04:20:29 GMT

>I am currently trying to find information on current chip design times verses
>complexity.
>
>Thanks in advance

There are several types.  For instance full custom, custom, standard
cell and sea of gates are several examples.  Each takes its own time. 
 
Also some big designs take years and after first silicon, a year to remove
the last few bugs.  Of course some never have all the bugs removed.

Lastly, some companies are on a learning curve and take a long time to
get their first complex chip out.  

If you can be more specific, I can help you since I work at a design
house.

One other thing to think about is that some designs are just modifications
to existing chips, for example embedded controlers based on risc cpu
processors.

Good luck
From: jam@hplred.HP.COM (Merban Jam)
Date: Thu, 27 Aug 1992 23:31:32 GMT
Subject: SPICE ftp site?
Organization: Hewlett Packard Labs, Palo Alto CA
Newsgroups: comp.lsi.cad

Would you please let me know where is the ftp site for UCB SPICE?

Thanks,
Mehrban Jam

Newsgroups: comp.lsi.cad
From: beorn@elk.Berkeley.EDU (Beorn Johnson)
Newsgroups: comp.lsi.cad
Subject: Re: SPICE ftp site?
Date: 3 Sep 1992 02:50:11 GMT
Organization: UC Berkeley
Distribution: world
Reply-To: beorn@berkeley.edu
NNTP-Posting-Host: elk.berkeley.edu

In article <1992Sep1.161346.10245@newsgate.sps.mot.com>, dichter@chdasic.sps.mot.com (Carl Dichter) writes:
|> 
|> From the FAQ:
 [ ... ]
|>                      . . .  For more information on how to acquire Spice,
|>   please send your physical mailing address to "cindy@janus.berkeley.edu"
|>   and request a software catalog.


Please note that for the Industrial Liaison Program software (which we are
talking about here) the email address "cindy@janus.berkeley.edu" has been
superceded by "software@diva.berkeley.edu".  It _should_ (also) be
"software@eecs.berkeley.edu", but I just checked and it hasn't been set up
yet.

	Beorn Johnson
	Spice maintenance
	UC Berkeley, EECS/ERL/CAD Group
	(beorn@ic.berkeley.edu)

Please direct inquiries to "spice@berkeley.edu" or "spice-bugs@berkeley.edu"