From: tony@microware.co.uk (Tony Mountifield)
Newsgroups: comp.sys.atari.st
Subject: Re: More Falcon news...
Date: 23 Nov 92 13:01:39 GMT
Organization: Microware Systems (UK) Ltd., Winchester, UK.

In article <1992Nov19.213205.86@uoft02.utoledo.edu> jsteiner@anwsun.phya.utoledo.edu (jason 'Think!' steiner) writes:
> undermind!Steve_Johnson@overmind.mind.org writes:
> > The Falcon030's 68030 has a 24-bit address/16-bit data bus.  It 
> > get's a little confusing, though, because the COMBEL (the system 
> > controller) has a 32-bit bus to RAM and to the VIDEL (the video 
> > controller).  The machine on the whole, though, isn't a 'TRUE' 32-
> > bit machine (kinda like the Mac LC II/Performa 400).  The PDS 
> > (processor-direct slot) is also 24-bit address/16-bit data.  There 
> > is some hope, though, that a third party will be able to 'fix' this 
> > (there will, most definitely, be a 32-bit FAST RAM expansion for 
> > the Falcon030 that will allow more RAM, at least, from what I've 
> > heard). 
> 
> this is -really- strange. i was under the impression that all 68k
> processors after the '020 were 32 bit all the way 'round. can someone
> post a 'family tree' of the 68k series & what is what? going to
> 24/16 for a 32 bit processor sounds like something Intel would do,
> not Motorola.
> 
> i realize that Motorola doesn't have a lot to do with the bus design,
> but it seems to me that trying to fit a 32 bit external processor
> on a 24/16 bus would be a lot more hairy than just making it 32 bits
> in the first place.

The 68020 and 68030 both have a feature called Dynamic Bus Sizing. This
means that instead of a single DTACK to acknowledge the bus cycle, there
is a pair of DSACK lines - DSACK0 and DSACK1. When the CPU wants to do a
longword (32-bit) access, it places the data on all 32 data lines. The
address decoding then determines whether the addressed device or memory
can listen to all 32 or just 16 or 8. It then responds to the bus cycle
with some combination of the DSACK lines to indicate whether 32, 16 or 8
bits of data have been accepted. In the case of 32 the access is
complete. Otherwise the data gets shifted over so the unaccepted part is
on the part of the data bus that the accepted part was on, and another
bus cycle is run. This keeps happening until all the data has been
accepted (i.e. twice for a 16-bit port, and four times for an 8-bit
port). Since the address decoding decides which DSACK lines will be used
to acknowledge the cycle, it can have different addresses with different
bus widths, e.g. 8-bit peripherals, 16-bit ROM, 32-bit RAM, etc.

The 68008, 68000, 68010 and 68070 don't have this facility, and neither
does the 68040 (don't ask me why!).


Tony.

-- 
Tony Mountifield     (G4CJO)       | Microware Systems (UK) Ltd.
-----------------------------------| Leylands Farm, Nobs Crook,
Email:  tony@microware.co.uk       | Colden Common, WINCHESTER, SO21 1TH.
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** Any opinions are mine, not Microware's - but you knew that anyway. **
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