HDTenEightyP/NetNews huggingface dataset:
From: hansm@cs.kun.nl (Hans Mulder)
Newsgroups: comp.editors
Subject: Re: Paragraphs and vi
Date: 5 Oct 92 14:29:57 GMT
Organization: University of Nijmegen, The Netherlands

In <1992Oct4.050951.2469@ils.nwu.edu> eric@ils.nwu.edu (Eric Goldstein) writes:
>In vi, fmt can be invoked for the paragraph in question by
>using the !}fmt command.

>In my case, this just about works (but not quite).  The 
>paragraph does get formated, but the system then inserts
>a message directly into my text.  Using the example I gave
>earlier:
>------------------------------------------------------------------
>stty: TCGETS: Operation not supported on socket

Oh well, at least stty mentions it's name in the message you get.
Biff just says "Where are you?", giving you no clue whatsoever.

This is essentially question 2.7 in the FAQ for comp.unix.questions.
The answer is that it is a problem with your .cshrc file (or equivalent
for whatever shell you use.)
That file contains a line with an stty command, maybe:

	stty erase ^H		# or whatever

If your shell is a C shell or compatible, change that to read:

	if ($?prompt)
		stty erase ^H		# or whatever
	endif

Or, if it's a Bourne shell compatible, make that:

	if	[ ${PS1+x} = x ]
	then	stty erase ^H		# or whatever
	fi

Oh, if there is a line starting with:

	set prompt=
or
	PS1=

respectively, put that line between the if/endif pair c.q. then/fi
pair as well.

--
Hope this helps,

Hans Mulder				hansm@cs.kun.nl
From: tim@crash.canon.co.uk
Newsgroups: comp.editors
Subject: Re: Vi Formating without using fmt
Date: 6 Oct 92 17:08:31 GMT
Organization: me myself and i

rliles@spuds.mlb.semi.harris.com (Ray Liles) asks:

|1. How do you insert text into an existing paragraph AND reformat/fill that
|   paragraph so that all text observes the wrapmargin, without part of a word
|   on one line and the rest of the word on the next?

Insert the text and {!}fmt^M. Oops. I used fmt. What about {!}notfmt^M
and ln -s /usr/ucb/fmt /usr/local/bin/notfmt? Why do you hate fmt so?
What has it ever done to you?

|2. How do you justify text for both the left AND right margins without running
|   through fmt?

nroff?

Tx. [are these trick questions]
-- 
Tim F O'Donoghue <tim@crash.canon.co.uk> <uunet!canon!tim>
Newsgroups: comp.editors
From: bt@irfu.se (Bo Thide')
Subject: Re: vi help
Date: Fri, 2 Oct 1992 12:57:21 GMT
Organization: Swedish Institute of Space Physics, Uppsala, Sweden

In article <9227622.3723@mulga.cs.mu.OZ.AU> gleeson@mundil.cs.mu.OZ.AU (Red Mountain) writes:
>In <1992Oct1.200327.19080@msuinfo.cl.msu.edu> cassidy@cps.msu.edu (John J Cassidy) writes:
>>	Also linefeeds kind of bug me, is there a way
>>to append the line following onto the end of the current 
>>line?  In other words, delete the line feed/carraige 
>>return.
>
>There must be a better way than this, but:
>move to the beginning of the line after the offending linefeed, then
>d$k$p
>(delete to EOL, back up a line, go to EOL, put the buffer after EOL)


What's wrong wiht "J" (to Join two consecutive lines, separated by EOL)?


Bo
-- 
   ^   Bo Thide'--------------------------------------------------------------
  |I|        Swedish Institute of Space Physics, S-755 91 Uppsala, Sweden
  |R|      Phone: (+46) 18-303671.  Fax: (+46) 18-403100.  IP: 130.238.30.23
 /|F|\          INTERNET: bt@irfu.se      UUCP: ...!mcvax!sunic!irfu!bt  
 ~~U~~ ----------------------------------------------------------------sm5dfw-
Newsgroups: comp.editors
From: gleeson@mundil.cs.mu.OZ.AU (Red Mountain)
Subject: Re: vi help
Organization: Computer Science, University of Melbourne, Australia
Date: Fri, 2 Oct 1992 12:24:35 GMT

In <1992Oct1.200327.19080@msuinfo.cl.msu.edu> cassidy@cps.msu.edu (John J Cassidy) writes:
>	Is there any way in vi to read in an additional
>file to the one you are working on?

:r <filename>

>	Also linefeeds kind of bug me, is there a way
>to append the line following onto the end of the current 
>line?  In other words, delete the line feed/carraige 
>return.

There must be a better way than this, but:
move to the beginning of the line after the offending linefeed, then
d$k$p
(delete to EOL, back up a line, go to EOL, put the buffer after EOL)

>	Oh yes, and you can tell me I should have read`
>the manual, but I have read the manual on our system, and
>it simply does not cover inside commands, only command-line
>ones.

Most don't. You should try the VI & EX archives listed in the FAQ. Heaps
of great info.

Marty.
---------------------=============***O***=============-------------------------
Martin J. Gleeson  | Computer Science, Melbourne Uni, Oz |    ...  __o    Outta
gleeson@mundil.cs.mu.oz.au |     E Pluribus Unix         |  ...   -\<,       my
"We gladly feast on those who would subdue us." - Addams |  ....(_)/(_)..  way!
 "I can't give you brains, but I can give you a diploma." - The Wizard of Oz
---------------------=============***O***=============-------------------------
From: koslowj@math.ksu.edu (Juergen Koslowski)
Newsgroups: comp.editors
Subject: using demacs with tex-mode
Date: 4 Oct 1992 16:55:54 -0500
Organization: Dept. of Mathematics, Kansas State University
Distribution: inet
NNTP-Posting-Host: hilbert.math.ksu.edu
Summary: need help with TeX-mode under demacs
Keywords: demacs, TeX-mode

I recently installed demacs on my i386SL notebook. Since a TeX-mode was not
supplied, I tried to use the one from out unix system at school. But that
doesn't quite work:

When calling demacs with a *.tex file, I get (below the status line)

	File mode specification error: (invalid-function 4)

Some of the TeX-mode command are available, though.

When editing a non-TeX file with demacs, and trying to load TeX-mode, I get

	Stack overflow in byte code (byte compiler bug), pc = 16

Any suggestions are appreciated!

Before I forget it, one more question: Is it possible to change the cursor
from the underline character to a larger box? For my taste the underline cursor
is difficult to find on the screen.

-- J"urgen
-- 
J"urgen Koslowski         | If I don't see you no more in this world
Department of Mathematics | I meet you in the next world
Kansas State University   | and don't be late!
koslowj@math.ksu.edu      |                         Jimi Hendrix (Voodoo Chile)
Newsgroups: comp.editors
From: hamjavar@carina.unm.edu (Farid Hamjavar)
Subject: UNIX COMMAND IN VI SESSION.
Date: Thu, 01 Oct 92 21:45:21 GMT
Organization: University of New Mexico, Albuquerque


Hello : 				OCT-01-92

VI allows you to execute UNIX commands in a VI session.
How can I enter AT THE CURSER, the output of the  UNIX's  "date" command ?



ThankS a lot.
Farid Hamjavar
hamjavar@carina.unm.edu
From: takefuji@donald.EEAP.CWRU.Edu (Yoshiyasu Takefuji)
Newsgroups: comp.internet.library
Subject: IP address in Spain
Date: 3 Oct 1992 00:58:32 GMT
Organization: Dept. of Electrical Engineering, CWRU, Cleve. OH
NNTP-Posting-Host: donald.eeap.cwru.edu

From mgk1761@sjfc.edu Fri Oct  2 13:21 EDT 1992
Received: from sjfc.edu by donald.EEAP.CWRU.Edu with SMTP
        (15.11/15.6) id AA26942; Fri, 2 Oct 92 13:21:44 edt
Return-Path: <mgk1761@sjfc.edu>
Date: Fri, 2 Oct 92 13:26:14 -0400
From: mgk1761@sjfc.edu (Matthew Kopcienski)
Received: by sjfc.edu (5.61/3.1.090690-St. John Fisher 
College)
        id AA15915; Fri, 2 Oct 92 13:26:14 -0400
Message-Id: <9210021726.AA15915@sjfc.edu>
To: takefuji@donald.EEAP.CWRU.Edu
Status: R

I am looking for the internet address for the University of 
Granada
in Spain.  If they aren't on the internet, how about a mail 
address.
Hopefully you could post this to comp.internet.library if 
you can't
get an answer.

-=Matt=-
From: supnik@human.enet.dec.com (Bob Supnik)
Newsgroups: comp.arch
Subject: Re: No special branch/jump formats?
Summary: Comments
Keywords: PC as GPR
Date: 26 Sep 92 20:14:21 GMT
Organization: Digital Equipment Corporation

Sorry to omit the originals, but some comments on the whole thread:

1. PC as general register in VAX's.  While the architecture spec says that
   direct references to PC are 'unpredictable', the preferred implementation
   is to fault on such references.  If a fault was not generated, the
   implementation would produce a garbage value on read, and throw a write
   into the bit bucket.  This is because the PC could not be kept in the
   main register file; it had to be implemented with special incrementing
   hardware somewhere in the main instruction decoder.  A read or write
   to 'R15' would access the 16th register in the register block, typically
   a microcode temporary of no redeeming social importance.

2. PC as general register in RISC processors.  With heavy pipelining,
   and concurrent issue, producing an 'accurate' PC for the addressing
   unit to use is rather costly.  The PC (and its pipeline) is maintained
   in the instruction fetch and decode unit, not in the load/store unit
   or integer execution unit; the paths to move it there take up valuable
   chip real estate and are likely slow.  The only PC-relative calculations
   are branches, which are done in the instruction unit where the PC
   pipeline lives.

Bob Supnik	>Supnik@human.enet.dec.com
		>All opinions expressed are those of a hardline microcoder
		>and do not reflect those of Digital Equipment Corporation
Newsgroups: comp.arch
From: shil@nasser.eecs.nwu.edu (Lei Shi)
Subject: instr-sched.c for DEC Alpha  
Organization: EECS Department, Northwestern University
Date: Fri, 2 Oct 1992 18:30:51 GMT

Hi: 

	I am a graduate student in the Electrical Engineering and Computer
Science Department in Northwestern University.  Currently I am working on 
a study of DEC Alpha chip.  I got a copy of instr-sched.c from gatekeeper.
dec.com.  However, when I am trying to compile the instr-sched.c on a 
Sun IPX, it failed at the compile step because of syntax error.  
Has anyone been using this program successfully?  If so, could you send me
a working copy?

	Also, I have another question:  For the DECChip 21064 chip, when we 
applying the dual-issue rule (Table 2-2, on page 2-16 of the Preliminary 
Data Sheet), can we just pick one instruction from the classes in the left
column and issue it with another instruction from the classes in the right
column?  

	Not a native English speaker, it may be difficult to understand 
the above.  Sorry about that.  Thanks a lot in advance.  My Email address
is shil@eecs.nwu.edu.  Please send me e-mail.  



	- Lei Shi. 
 

From: slo@otter.hpl.hp.com (Steve Loughran)
Date: Thu, 1 Oct 1992 13:43:28 GMT
Subject: Re: Power consumption
Organization: Hewlett-Packard Laboratories, Bristol, UK.
Newsgroups: comp.arch

In comp.arch, badri@rags.rutgers.edu (Br Badrinath) writes:

 We intend to consider power management as a research issue in the
design of OS for palmtops, PDA's etc.

>1. How much power is needed to transmit a packet of data over wireless
>as a function of distance of transmission, modulation technique,
>receiver strength etc?

	Power consumption is sort of proportional to bandwidth and range.
	I think.

> 2. How much power is necessary to support a CD ROM disk?

	The main drain on CD Roms, hard disks and floppies is in the motor
	needed to spin them...more efficient motors and smaller, lighter
	disks may make this easier. (1.3 inch HDDs, Sony's minature CD &c)
	(or give the user a handle to turn the disk round)

> 3. How much power is consumed by an average read from
> the CD disk, from floppy disk, from flash memory, any
> other memory?

	No figures here either I'm afraid. An interesting point is that of
power consumption while the machine is "off"...for DRAM storage you'll need
regular refresh and SRAM does consume some power (+costs more). Who knows,
maybe we'll all go back to Core or Bubble memory :-)

> 4. What is the power consumption for remote session operations such as file
> transfer, receiving a data packet (Mwatts/byte??)

	Driving an  RS232 line takes a fair bit of power...this is not
too much of a problem if you have a PSU at your "home base".

> 5. What is the power consumption of the CPU (per n cycles or so)?

	Well, that's going to vary with the CPU isn't it. A smaller  CPU 
and any ability to switch unneeded bits off gives low consumption.

> 6. What is the average lifetime of AA batteries (and under
> what usage)?

I find 3 weeks on an HP palmtop, tho' to avoid losing all my data when 
left unattended too long I've taken to leaving it plugged in.
NiCds last about half the time but then can be recharged (if you have 2 sets)


Other important issues:
	Display consumption -active matrix LCDs burn too much power, as do 
		backlit ones.
	Requirements of input devices -keyboard, mice and pens...

> --Badri
	-Steve

disclaimer : I only write code for palmtops, not build them.
From: mpourzan@ens-lyon.fr (Makan Pourzandi)
Newsgroups: comp.arch
Subject: Re: Fully associative cache
Date: 30 Sep 92 12:23:07 GMT
Reply-To: mpourzan@ens-lyon.fr
Organization: Ecole Normale Superieure de Lyon

In article 92Sep23094848@athene.rice.edu, cliffc@rice.edu (Cliff Click) writes:
>In article <1992Sep23.083717.20050@inmos.co.uk> roger@gimli.inmos.co.uk (Roger Shepherd) writes:
>
>> The T9000 transputer has a quad-banked memory system, each bank of which
>> incorporates a 4k byte fully associative cache, giving 16 kbytes of on-chip
>> cache memory in total. Each 4k byte bank of cache is organised as 256 lines
>> of 4 words. 
>
>I was taught to believe that a fully associative cache was very expensive.
>
>Does a "quad-bank memory system" with a "4k byte" cache translate to a
>16K 4-way set associative cache?
>
>Or does the T9000 have a really butch cache?
>
>And if so, what was the transistor & die area cost, 
>relative to a 32K 4-way set associative cache?
>
>I'm curious because of the work done at Rice re blocking numerical loops
>for cache in the compiler.  One of the big unanswered questions is how much
>set associativity is enough.
>
>Thanx,
>Cliff
>
>P.S.  Did the transputer guys think about using ABMRU* instead of random
>replacement?
>
>*ABMRU (Anything But the Most Recently Used)
>--
>The Sparc ABI had the most brain-damaged calling convention I've ever seen.
>It's probably better now but reminiscing gives me something to complain about.
>Cliff Click (cliffc@cs.rice.edu)  |  Disclaimer:  My lawyer made me say it.
Xref: sparky comp.arch:9845 comp.periphs:1350 comp.sys.ibm.pc:653
From: mikem@hitwr.hauppaugeNY.NCR.COM (mikem)
Newsgroups: comp.arch,comp.periphs,comp.sys.ibm.pc,comp.unix.i386
Subject: SCO hard disk drivers
Date: 3 Oct 92 15:22:10 GMT
Reply-To: mikem@hitwr.hauppaugeNY.NCR.COM ()
Organization: Applied Digital Data Systems

I need to know what hard disk controllers are supported by SCO Unix Sys V rel
3.2.4 using ST 506 RLL drives. SCO has told me 'any' controllers will work, but
in real life they are wrong. I was also told WD controllers will work, but WD
has been out of the controller business for two years. I need to know which
controllers are supported by ISA 386 PC's using RLL drives.

Please mail me all and any response you think may be of use to me.  

						Thanx.
							Mike M.
From: brzezins@hplred.HP.COM (Dennis Brzezinski)
Date: Tue, 29 Sep 1992 00:24:04 GMT
Subject: Re: Which is the Best RISC Arcitecture ?
Organization: Hewlett Packard Labs, Palo Alto CA
Newsgroups: comp.arch

HP's Circuit Technology Group does market our internal PA-RISC processor chips
and CPU/Cache modules.  The 7100 CPU chip has a 200MFLOP IEEE754 compliant
64-bit floating point unit on chip. It outperforms the DEC Alpha by 30-50%,
based upon the benchmark(the 7100 has a multiply, add instruction that allows
a separate multiply and add to start every cycle and complete in 2 cycles).
The single CPU/Cache module has a snoopy memory controller as well as a 256KB I,
256KByte D direct mapped caches.  There is also a 2 CPU module that shares the
cache and memory controller.  In our systems the Spec89 is over 130.  The 
module runs at 96Mhz worst case(110C, 4.5V, worst case process).  The module is
a 2 sided PCB, about 3.5"- 4" on a side.  Like most worksation suppiers, a 
40%-50% increase in system performance per year can be expected from future
designs.  If I remember correctly, the HP-PRO team that manages the evolution 
of the PA-RISC architecture represents companies like HP, Hitachi, Toshiba,
OKI, Convex with over $70B in total sales.
 
 I can put you in touch with a sales engineer if you are interested.

 Dennis Brzezinski
 HP Labs,  Palo Alto

 I speak only for myself, not HP.  This is not a sales pitch, just a answer to
 a net question
Newsgroups: comp.arch
From: rf@cl.cam.ac.uk (Robin Fairbairns)
Subject: Re: Multi uP P5 systems
Reply-To: rf@cl.cam.ac.uk (Robin Fairbairns)
Organization: U of Cambridge, England
Date: Tue, 6 Oct 1992 14:54:37 GMT


In article <1992Oct6.133255.2382@crd.ge.com>, davidsen@ariel.crd.GE.COM
(william E Davidsen) writes:
|> [of VMS]
|>   I sure hope so. Any o/s which puts file types in the o/s instead of
|> the program is really creating problems for the user, and I find that
|> more of a problem than the user interface. If programs really want a "$
|> delimited left handed nybble swapped hexadecimal" file type, let it be
|> done in the program or shared library, and not at a level when all
|> user-written file transfer and backup programs have to deal with it. As
|> my youngest says "yucky-poo!"

I don't get this.  Where in the operating system does VMS put the file
type?  My reading of it is that the operating provides support for a
library (RMS) supplied by DEC that uses space in the file header to
record the file structure that RMS has written.  VMS offers user-level
space within the file header to record this stuff.  What's improper
aabout that?

What _may_ be bad is that the choice of file types provided by RMS is
curious, of course...
--
Robin (dump Brian Kay) Fairbairns                    rf@cl.cam.ac.uk
U of Cambridge Computer Lab, Pembroke St, Cambridge  CB2 3QG, UK
Newsgroups: comp.arch
From: lindsay+@cs.cmu.edu (Donald Lindsay)
Subject: Re: ASTs
Followup-To: comp.os.misc
Organization: School of Computer Science, Carnegie Mellon
Date: Sun, 27 Sep 1992 01:07:48 GMT

Note the Followup-To.

In article <1248@falcon.is> brb@falcon.is (Bjorn R. Bjornsson) writes:
>Much as I like Unix, I would kill to have a decent signaling system
>(known as ASTs - Asynchronous System Traps in RSX-11 and VMS) instead
>of the rotten kludges everyone has to put up with in the (various)
>Unix systems.  I've been gnashing my teeth for ten years over the fact
>that there was a chance to put this right when BSD was implemented.

What BSD should have done, is what Mach has done. Multiple threads
are allowed in a single address space. If a single-threaded program
traps, then a second thread is created, and told about the sins of
the first one. (Etc)

The reason this is Right is that there are standard tools and
techniques for getting multiple threads to cooperate. The error
thread is just a thread, a peer to the other threads. Contrast this
with the usual rule for interrupt routines: don't call anything,
and don't print, because nothing useful is reentrant.
-- 
Don		D.C.Lindsay 	Carnegie Mellon Computer Science
Newsgroups: comp.arch
From: picano@en.ecn.purdue.edu (Silvio Picano)
Subject: Re: Best Grad Schools for Computer Engineering?
Organization: Purdue University Engineering Computer Network
Date: Tue, 29 Sep 92 14:39:50 GMT

There is a directory of info on universities, research 
projects, and contacts kept by the moderator of 
comp.parallel.  Anonymous ftp to "hubcap.clemson.edu"
and look in the "pub/parallel/schools" directory.  [Do 
not know how exhaustive or up-to-date the files are?]

Silvio
Newsgroups: comp.arch
From: sarr@sinshan.citi.umich.edu (Sarr J. Blumson)
Subject: Re: What was the intended advantage of using 36bits CPU?
Organization: University of Michigan, CITI
Date: Mon, 5 Oct 1992 14:17:06 GMT

In article <869@felix.Sublink.Org> eb@felix.Sublink.Org (Enrico
Badella) writes: 
>Recently I came hold of and old paper that described the TENEX Operating 
>System for old DEC Systems 10 and 20; I never used or saw such beasts but 
>I was wondering what was the advantage of having 36 bits instead of 32 
>or other 8*n (n>4) architecture.  
>Was is just a hardware problem because 48 bits was to difficult to
>manufacture at that time.  
> 
>On the DEC Systems 10 and 20 subject, why did they fade away in those 
>days when nobody news what Open Systems were?  

The 10 and 20 had 36 bits because the IBM 704 (1955 or so) did.  Back
then everybody thought 6 bit characters were plenty; 36 was a
reasonable hardware compromise for roughly the same reasons 32 is.  18
and 24 bit machines were also common, and there were some 30s.

The 10/20 faded away because DEC killed them.  Whether this was
stupidity on their part or a sensible response to the realization that
they were competing against themselves (the VAX) is the subject of one
of the world's most endearing, and enduring, flame wars.


(Sarr Blumson)
Newsgroups: comp.arch
From: ldm@texhrc.uucp (Lyle Meier)
Subject: Re: Which is the Best RISC Arcitecture ?
Organization: Texaco EPTD
Date: Fri, 25 Sep 1992 19:46:19 GMT

In article <1992Sep25.082119.1341@odin.diku.dk> torbenm@diku.dk (Torben AEgidius Mogensen) writes:
>mjohnson@netcom.Netcom.COM (Mark Johnson) writes:
>
>>In article <1992Sep24.180118.1392@sun1.ruf.uni-freiburg.de> wolf@sun1.ruf.uni-freiburg.de (Klaus H.Wolf) writes:
>>    > (I know SPARC, MIPS, 88k, POWER, DSP96002)
>
>
>>To those, add
>>     Clipper    (Intergraph)
>>     Precision  (Hewlett Packard)
>>     Swordfish  (National Semiconductor)
>>     i860       (Intel)
>>     i960       (Intel)
>>     ARM        (Acorn / VLSI Technology)
>>     Regulus    (Computer Consoles Inc)
>>     Lightning  (Metaflow / LSI Logic)
>>     Pinnacle   (Ross Tech / Cypress)
>>     Ice        (NEC / MIPS)
>
>
>HP precision architecture may not be available outside HP.


	This may already have been said, but convex is building
	an mpp system based upon the HPPA, so it is at least
	sort of open.
Newsgroups: comp.arch
From: davew@willow03.cray.com (Dave Wagner)
Subject: Re: Roger Ross quote about Alpha being the only 64-bit micro?
Originator: davew@willow03
Organization: Cray Research, Inc.
Date: 28 Sep 92 15:56:55 CDT


In article <1992Sep28.201033.24532@csrd.uiuc.edu>, grout@sp90.csrd.uiuc.edu (John R. Grout) writes:
> davew@willow03.cray.com (Dave Wagner) writes:
> 
> >Check address spaces in Alpha though.  Alpha (21064) has only a 43-bit virtual
> >space, and a 34-bit physical space.  I think a 'real' 64 bit processor should
> >provide more (64bits) of both.
> 
> It depends on how you define 'real'... the Alpha ISA requires the use of
> 64-bit virtual and physical addresses, which means that any unimplemented
> high-order bits on a given processor are reserved for future expansion and
> must be zero (and this is _enforced_).  Given this, an ISA subset on a
> specific Alpha processor chip (e.g., the 21064) can be a win (a valid
> cost-benefit tradeoff) without being a first-implementation artifact which
> loses the ability to compatibly implement full 64-bit physical or virtual
> addresses later.

That's why I specified the 21064 processor of the Alpha 'family'.  One point
though, the high order bits should not be 0 on the 21064, they need to be
the sign extension of bit42.  Also the SPE_x bits in the ABOX control register
puts some further limitation on the physical address space.  I agree, though,
that as far as 64 bit operations, data, etc. (64x64 multiply), the Alpha is
certainly a good 64bit processor.
-- 
Dave Wagner                                     Cray Research, Inc
davew@cray.com , uunet!cray!davew               655F Lone Oak Drive
(612) 683-5393                                  Eagan, MN  55121
Newsgroups: comp.arch,comp.arch.storage,alt.sys.sun