HDTenEightyP/NetNews huggingface dataset:
From: jon@alpha.ee.ufl.edu (Jon Mellott)
Subject: Re: prints from caeds on rs6000 to hp Paintjet prt
Organization: EE Dept at UF
Date: Wed, 19 Aug 92 17:22:01 GMT

In article <1992Aug19.131300.4179@seas.gwu.edu>, sohrab@seas.gwu.edu (Sohrab Aidun) writes:
|> 
|> Hello:
|> 
|> 	We have a(n) HP Paintjet XL 300  with a(n) hpgl2 cartridge
|> connected to our IBM RISC 6000's.  We use the Paintjet to get
|> color prints of objects created with the CAEDS cad package.
|> The problem is that the quality of the prints is no where close
|> to what it should be.  When we talk to the IBM people they tell 
|> us "HP has to make the proper driver for it", when we talk to 
|> the HP people we get "IBM should make the driver".
|> 	Presently we are using the xwd command to create screen dumps.
|> Converting the xwd format to hpgl format with the help of the pbmplus
|> package, and then send it to the printer.  This makes life hard
|> on users for they have to change the background color to white, and
|> by doing this they will not be able to read the numbers off of the
|> print.
|> 
I think that the low print quality can be attributed to your use of screen 
dumps. You are dumping at screen resolution and then doing some gymnastics 
to get your hardcopy. Can your program print to an HP7475? With a little 
filtering you should be able to send it to the HPGL/2 equiped PaintJet. 
We've got the Valid (Cadence) EDA software and use an HP PaintJet XL with 
the HPGL/2 cartridge for printing B size schematics. Our platform is Sun.
We've tell our software to plot to an HP7475 plotter which is then 
filtered and sent to the PaintJet. The filter simply sets the pen width and 
sends a sequence to ensure that the PaintJet is in HPGL/2 mode and not 
PCL mode. Simple enough. I've plotted D-size schematics to B-size paper 
with the PaintJet XL and had nice, readable results. Plus it goes a helluva 
lot faster than our HP DraftPro DXL. I suspect that the results will be 
even nicer for you since the PaintJet XL300 is 300 dpi instead of 180dpi.

Good luck,
Jon Mellott
High Speed Digital Architecture Laboratory
University of Florida
(jon@alpha.ee.ufl.edu)
From: bhoughto@sedona.intel.com (Blair P. Houghton)
Newsgroups: comp.lsi.cad
Subject: Re: 13m
Date: 12 Aug 92 17:21:15 GMT
Organization: Intel Corp., Chandler, Arizona

YOU SUNK MY BATTLESHIP!!

				--Blair
				  "Dang."
Newsgroups: comp.lsi.cad,comp.lsi
From: burman@sol.cs.wmich.edu (SURENDRA BURMAN)
Subject: Non-American MCM Companies
Keywords: Non-American, Multichip Modules
Organization: Western Michigan Univ. Comp. Sci. Dept.
Date: Sat, 22 Aug 1992 18:18:26 GMT

I am looking for addresses of non-American Companies in Multichip 
Modules (MCMs) business. In particular, I would be interested 
in Japanese, European based firms. If anyone has such list, partial
or complete, I would be thankful if he/she can email me. If needed,
I will post a summary of the responses on the net.

Thanks in advance.

-- Burman

Surendra Burman
Department of Computer Science
Western Michihan University
Kalamazoo, MI 49008
Phone: 616-387-5645
Fax:   616-387-3999
Email: burman@cs.wmich.edu
Newsgroups: comp.lsi.cad
From: R2NVK@VM1.CC.UAKRON.EDU
Subject: programs for schematic capture.
Organization: The University of Akron
Date: Fri, 21 Aug 1992 20:38:47 GMT

I wanted to know if there are any programs for schematic capture. I am trying t
o develop a logic circuit simulation package on windows 3.0
Thanking you in advance.
                                 nagesh
 
Newsgroups: comp.lsi.cad
From: sohrab@seas.gwu.edu (Sohrab Aidun)
Subject: prints from caeds on rs6000 to hp Paintjet prt
Originator: sohrab@seas.gwu.edu
Organization: George Washington University
Date: Wed, 19 Aug 1992 13:13:00 GMT


Hello:

	We have a(n) HP Paintjet XL 300  with a(n) hpgl2 cartridge
connected to our IBM RISC 6000's.  We use the Paintjet to get
color prints of objects created with the CAEDS cad package.
The problem is that the quality of the prints is no where close
to what it should be.  When we talk to the IBM people they tell 
us "HP has to make the proper driver for it", when we talk to 
the HP people we get "IBM should make the driver".
	Presently we are using the xwd command to create screen dumps.
Converting the xwd format to hpgl format with the help of the pbmplus
package, and then send it to the printer.  This makes life hard
on users for they have to change the background color to white, and
by doing this they will not be able to read the numbers off of the
print.

	Can anybody out there help us to get better quality prints?

*****************************************************************************
*  Sohrab Aidun  	George Washington University     SEAS Computing     *
*  sohrab@seas.gwu.edu				  	 (202) 994-6853	    *
*****************************************************************************
From: gat@concept.uucp (Gerhard Angst)
Newsgroups: comp.lsi.cad
Subject: Netlist 2 Graphic conversion
Keywords: EDIF NETLIST-DATA SCHEMATIC-DATA
Date: 17 Aug 92 08:48:14 GMT
Organization: concept engineering GmbH, D-7800 Freiburg, Germany


Hello,

   we are actually working on a project, where we have to generate
   schematic drawings (graphics) from EDIF netlists. Some weeks ago
   i have heard from a tool called "TGIF" or so. The tool was probably
   developed at Berkely University. 

   0) Has anyone information about "TGIF" or other netlist2graphic tools
    
   1) Is "TGIF" a public domain tool ?

   2) How can i obtain a copy of "TGIF" ?

   Any guidance will be greatly appreciated.
   I will summarize here in 'comp.lsi.cad'

   - Gerhard Angst

   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   .  +-------+                             .                            .
   .  |       |   concept engineering GmbH  . Tel  : +49 (0)761-473099   .
   .  |       |        Gerhard Angst        . Tel  : +49 (0)761-441063   . 
   .  |       |                             . gat@concept.de             .
   .  |       |      Burkheimer Str. 10     .                            .
   .  |concept|       W-7800 Freiburg       . Our Products:              .
   .  +-------+          Germany            .     Graphical EDIF Viewer  . 
   . engineering                            .     C++ EDIF Toolbox       .
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Newsgroups: comp.lsi.cad
From: shoham@enel.ucalgary.ca (Idan Shoham)
Subject: Gate Level Simulation Benchmarks
Date: Sat, 22 Aug 92 06:28:18 GMT
Organization: ECE Department, U. of Calgary, Calgary, Alberta, Canada

Hi all,

We've developed a gate- (and higher-) level circuit simulator at
the University here, and would like to gauge its performance against
other simulators.  I've been able to translate the ISCAS'85
circuits to our netlist format, and run the circuits with random
test vectors.  I'd like to know if anyone out there has done the
same with any other simulators (their own or otherwise), and what
sort of timing figures they get, on what machines.  So far, we've
compared performance against Verilog (from Cadence), with 
favourable results.

Thanks for any help,

Idan
---------------------------------------------------------------------------
shoham@enel.ucalgary.ca
From: padma@cirrus.com (Padma Akkiraju)
Newsgroups: comp.lsi.cad
Subject: Simulation of mixed block (analog and Digital)
Date: 18 Aug 92 17:13:48 GMT
Organization: Cirrus Logic Inc.  Fremont, California
Originator: padma@ss119

I am intersted in knowing about simulation tools,
methodologies that are used in the Industry 
for simulating  ASICS with on chip Analog blocks.

I am also interested in modelling techniques used for behavioural
modeling of Analog blocks. 

Thanks in Advance

padma






-- 
padma@cirrus.com
Newsgroups: comp.lsi.cad
From: gld@cunixb.cc.columbia.edu (Gary L Dare)
Subject: Re: Magic on an RS6000
Reply-To: gld@cunixb.cc.columbia.edu (Gary L Dare)
Organization: Curious Goods (formerly Louis Vendredi Antiques)
Date: Fri, 14 Aug 1992 04:54:39 GMT


Even by installing Magic on SunOS 4.1.1, there were changes from the
standard configuration generated for SunOS 4.0 by the front-end menu.
I contributed a note on this, and the only thing I have to add if you
are installing this on an IBM or MIPS or SGI or HP, etc. as well as a
Sun is to check the system directories listed in all makefiles, and
make sure that they conform to the file structure in your UNIX OS.
The openwin file path was changed for 4.1.1, and the X11 structure
on other machines might be different as well.

gld
--
~~~~~~~~~~~~~~~~~~~~~~~~ Je me souviens ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Gary L. Dare				Elections 1992-93:
> gld@cunixB.cc.columbia.EDU		* Jean Chretien (Canada)
> gld@cunixc.BITNET			* Perot^H^H^H^H^H Elvis! (USA)
Newsgroups: comp.lsi.cad
From: rs@inst.inst.bnl.gov (Richard Squires)
Subject: Dod CmosnLib
Keywords: cmos 
Reply-To: rs@inst.inst.bnl.gov (Richard Squires)
Organization: Brookhaven Lab
Date: Thu, 20 Aug 1992 18:39:48 GMT

I'm trying to generate cmos ram cells using the Dod CMOSN Standard Cell 
Library version 2.0A_GDS. It appears ramgen looks for a nonexistant file:

Initializing RAMGEN
ReadGDS: can't open '/home1/rs/Cmos_ramc2x2.gds'No such file or directory

I'd appreciate any clues. Thanks.
	
Richard Squires
Brookhaven Laboratory,Upton,NY 11973
rs@bnl.gov:voice516-282-7185:fax516-282-5773
Newsgroups: comp.lsi.cad
From: kk@mcnc.org (Krzysztof A. Kozminski)
Subject: Re: From where can I get CaZM ?
Organization: MCNC Center for Microelectronics, RTP, NC
Date: Wed, 12 Aug 1992 15:09:16 GMT

In regard to recent messages posted here about CAzM source: please DO NOT
call Jeri Williams at MCNC, she moved on to another position and is no longer
responsible for software distribution.

If interested in MCNC's software, pls send e-mail to 'oasis@mcnc.org' -
this will guarantee that the message will reach the person currently
handling software distribution (at this time: Linda Smith, lbs@mcnc.org).

The current technical contact for CAzM is Bill Richards (richards@mcnc.org).

Written mail should be directed to:

	Software Distribution
	MCNC Center for Microelectronic Systems Technologies
	PO Box 12889
	Research Triangle Park, NC 27709-2889
	Fax : 919-248-1455

KK
-- 
"Legalize freedom.  Vote libertarian"
From: hai@hpfcso.FC.HP.COM (Hai Vo-Ba)
Date: Fri, 21 Aug 1992 14:17:42 GMT
Subject: Verilog to TEGAS translator
Organization: Hewlett-Packard, Fort Collins, CO, USA
Newsgroups: comp.lsi.cad

	Hi,

	We're looking for a PD netlist translator that can map a hierarchical
    structural Verilog netlist into TEGAS. Any pointer is much appreciated.

----
Hai  Vo-Ba                              (303)229-3874
ESL  MS55              			hai@hpeshai.fc.hp.com
Hewlett Packard Co.
3404 E. Harmony Rd.
Fort Collins, Colorado 80525-9599
From: tk@ai.mit.edu (Tom Knight)
Newsgroups: comp.lsi.cad
Subject: Re: Help-Spice
Date: 18 Aug 92 01:38:40 GMT
Organization: MIT Artificial Intelligence Lab
In-reply-to: obiliset@mccoy.ecs.umass.edu's message of 12 Aug 92 20:11:30 GMT

In article <1992Aug12.201130.12208@risky.ecs.umass.edu> obiliset@mccoy.ecs.umass.edu (Sashi V Obilisetty) writes:
   From: obiliset@mccoy.ecs.umass.edu (Sashi V Obilisetty)

   Could somebody please post the name of the book which
   talks about Numerical Device modeling in Spice?

I'd strongly recommend the review "Circuit Simulation" by A. Sangiovanni-Vincentelli
in Computer Design Aids for VLSI Circuits, P. Antognetti et al. eds., Nijhoff, 1986
(Nato ASI series) as being by far the clearest explanation.

Newsgroups: comp.lsi.cad
From: obiliset@mccoy.ecs.umass.edu (Sashi V Obilisetty)
Subject: Help-Spice 
Organization: University of Massachusetts, Amherst
Date: Wed, 12 Aug 1992 20:11:30 GMT


Could somebody please post the name of the book which
talks about Numerical Device modeling in Spice?

Also, I would like to know if there is a newsgroup 
exclusively for Spice problems.

Thanks,

Sashi Obilisetty
From: vasub@zinger.sps.mot.com (Vasu Bibikar)
Newsgroups: comp.lsi.cad
Subject: Re: schematic capture pgm for MS Windows?
Date: 19 Aug 92 15:50:33 GMT
Reply-To: vasub@zinger.sps.mot.com
Organization: Motorola Semiconductor

In article 6cfH03qw62kJ00@amdahl.uts.amdahl.com, iggy@uts.amdahl.com (Igor Braslavsky) writes:
>Does anyone know if there is(are) schematic capture programs 
>made for MS Windows.  
>
>If so, which company (ies) make them.
>
>thanks,
>
>- igor

I have used E.C.S.(Engineering Capture System) schematic capture program for MS 
windows version 3.  The company name is Engineering Capture Systems, CA.

-Vasu.
------------------------------------------------------
Standard disclaimer: These are MY opinions and NOT my employer's.
I am no way connected to Engineering Capture Systems.
Newsgroups: comp.lsi.cad
From: stevens@madvlsi.columbia.edu (Andy Stevens)
Subject: Anybody ever simulate a tunnel diode with SPICE?
Organization: Columbia University
Date: Thu, 13 Aug 1992 23:16:49 GMT
X-Posted-From: britain.madvlsi.columbia.edu
X-Posted-Through: sol.ctr.columbia.edu

I would like to know if anybody out there has ever simulated a tunnel
diode with SPICE.  Did you write a custom model and add it to the
SPICE2 or SPICE3 source code?  Did you make a .subckt macro model?
Did you use the level 2 diode model in hspice?

Thanks,

--Andy Stevens
Columbia U.
From: Mike.McManus@FtCollins.NCR.com (Mike McManus)
Newsgroups: comp.lsi.cad
Subject: Re: Question about Lsim simulator of GDT
Date: 11 Aug 92 21:25:21 GMT
Organization: NCR Microelectronic Products, Ft. Collins, CO
In-reply-to: tra@cs.tut.fi's message of 8 Aug 92 14:51:57 GMT

In article <TRA.92Aug8165157@naakka.cs.tut.fi> tra@cs.tut.fi (Tommi Raita-aho) writes:
>   In switch simulation everything works fine, command: "high probe" sets
>   probe to 3.0 volts. But in adept simulation, the same command sets
>   probe to default value 5.0 volts, although Vdd is 3.0 volts.

I've seen the same problem.  Our fix is to use the pwl command.  If you want to
get fancy, build a pair of aliases:

alias hi "pwl $1 3.0,0"
alias lo "pwl $1 0.0,0"

In this way, you can even have a non-zero rise/fall times in your sim.  The
aliases can be used just like the built-in high/low functions (hi probeA; lo
probeB, etc.).  BTW, be sure to change the Logic_High value when using VDD=3V
in switch level.  Good luck!

--
Disclaimer: All spelling and/or grammar in this document are guaranteed to be
            correct; any exseptions is the is wurk uv intter-net deemuns,.

Mike McManus                      Mike.McManus@FtCollinsCo.NCR.COM, or
NCR Microelectronics              ncr-mpd!mikemc@ncr-sd.sandiego.ncr.com, or
2001 Danfield Ct.                 uunet!ncrlnk!ncr-mpd!propwash!mustang!mikemc
Ft. Collins,  Colorado              
(303) 223-5100   Ext. 378
From: drolet@cco.caltech.edu (Jean-Jacques P. Drolet)
Subject: Magic for MS-DOS?
Organization: California Institute of Technology, Pasadena
Date: Sun, 23 Aug 1992 01:40:50 GMT

I seem to remember reading that Magic (the VLSI CAD program) has been
ported to MS-DOS. If this is true, does anybody know whether it is
available by anonymous ftp?

Many thanks!

Jacques

Newsgroups: comp.lsi.cad
From: jabarby@sun5.vlsi.uwaterloo.ca (J.A. Barby)
Subject: Re: Simulation of mixed block (analog and Digital)
Organization: University of Waterloo
Date: Sun, 23 Aug 1992 02:34:47 GMT

In article <1992Aug18.171348.21243@cirrus.com>, padma@cirrus.com (Padma Akkiraju) writes:
> I am intersted in knowing about simulation tools,
> methodologies that are used in the Industry 
> for simulating  ASICS with on chip Analog blocks.
> 
> I am also interested in modelling techniques used for behavioural
> modeling of Analog blocks. 
> 
> Thanks in Advance
> padma
> 
> -- 
> padma@cirrus.com

I recently got the following when inquiring about similar questions.
I have requested the list of models from Mark and will post them when
they arrive.
Jim Barby

=======================================================================

	This message found its way to me.

We now offer an extensive library of behavioral models for functional ASIC
cells. As you know Jim, we have always had many of these cell models (e.g.
A/D convertor, comparator, opamp ...).

We recently did a survey of different ASIC vendors and found what were the
most popular ASIC cell models.  From this information we discovered that by
adding approximately 20 more models, we would consistly have model coverage
for more than 90% of an ASIC vender's cells. I will gladly send you a
listing of these models if you wish.

Speaking of ASIC simulation, we have also developed a new business package
for mixed-signal ASIC vendors and designers.  It is called the "ASIC
Simulation Partner Program" (ASPP).  This is a complete package which will
give the ASIC vendor or designer a jump start on simulating mixed-signal
ASICs.  I can also send out more info about this.

Thanks for the inquiry.

        Mark Chadwick
        mjc@analogy.com
        503-520-2734

--
Mark J. Chadwick        	       	       	            mjc@analogy.com   
Analogy Inc.                             
P.O. Box 1669                                            Phone: (503) 626-9700
Beaverton, Oregon 97075                                  Fax:   (503) 643-3361
-- 
 Jim Barby  <jabarby@vlsi.UWaterloo.ca>
 VLSI Group, University of Waterloo, Waterloo, Ontario, Canada, N2L 3G1
 519-885-1211x3995, FAX 519-746-5195
From: amcooke@waikato.ac.nz
Newsgroups: comp.lsi.cad
Subject: Magic on an RS6000
Date: 14 Aug 92 14:43:35 +1200
Organization: University of Waikato, Hamilton, New Zealand



I'm a neophite in UNIX, C and RS6000's and the job has come to me as the
technician, to get Magic going on the RS6000.  


Yeah, I know its going to be rough, but we're not rich and we can get access to
an RS6000.

Anybody done it?

Anybody got any helpful suggestions?


HELP

I'm not panicing,    yet!!

Alastair Cooke,
Physics Department,
University of Waikato,
New Zealand.
Newsgroups: comp.lsi.cad
From: rll@frieda.mitre.org (Roberto L. Landrau)
Subject: Re: Anybody ever simulate a tunnel diode with SPICE?
Organization: Research Computer Facility, MITRE Corporation, Bedford, MA
Date: Fri, 14 Aug 1992 10:45:21 GMT

In article <1992Aug13.231649.9094@ctr.columbia.edu> stevens@madvlsi.columbia.edu (Andy Stevens) writes:
>I would like to know if anybody out there has ever simulated a tunnel
>diode with SPICE.

Yes (PSPICE).

>Did you write a custom model and add it to the
>SPICE2 or SPICE3 source code?

I modified the code for the ``d'' model.  I added another ``level''.

>Did you make a .subckt macro model?

No.

>Did you use the level 2 diode model in hspice?

I didn't have access to HSPICE at the time.

>
>Thanks,
>
>--Andy Stevens
>Columbia U.

Another option is to use a nonlinear dependent voltage source and do
some curve fitting.

--
The opinions stated above are not necessarily my employer's.
----------------------------------------------------------------
Roberto L. Landrau    KC1YP    landrau@mitre.org  rll@linus.mitre.org
The MITRE Corporation  Bedford, MA 01730          rll@linus.UUCP
Newsgroups: comp.lsi.cad
From: burman@sol.cs.wmich.edu (SURENDRA BURMAN)
Subject: Electronic Packaging/Multichip Modules
Keywords: MCM, Ceramic
Organization: Western Michigan Univ. Comp. Sci. Dept.
Date: Tue, 18 Aug 1992 17:18:12 GMT

 I am looking for an article titled "ELECTRICAL DESIGN TECHNOLOGY
 FOR LOW DIELECTRIC CONSTANT MULTILAYER CERAMIC SUBSTRATE" authored
 by Akihiro Sasaki and Yuzo Shimada. This article appeared in one of
 the recent journals which I don't remember. Any pointers in this
 direction will be highly appreciated.


 Thanks in advance.

 -- Burman
 Email: burman@cs.wmich.edu
Newsgroups: comp.lsi.cad
From: eleleetk@nusunix2.nus.sg (Mr Lee Teng Kiat)
Subject: Example circuits for iSPLICE3
Reply-To: eleleetk@nusunix2.nus.sg
Organization: Dept. of EE, National Univ. of Singapore
Date: Sat, 15 Aug 1992 01:54:55 GMT


Hello again, I just wonder if anyone of you out there has relatively
*big* example circuits to test the mixed-mode capability of iSPLICE3.
I am particularly interested in getting the circuits (static RAM,
PLL, and ADC) mentioned the book 'Mixed-mode simulation' by Prof Saleh
and Prof Newton.

iSPLICE3 has implementations of MOS level 1 and 3 models but not the
level 2. Could this be a reason for the very much improved simulation
time even when full electrical simulation is done on some of the
example circuits?

Thanks for any help.

Regards

----------------
Teng-Kiat Lee                        VLSI CAD & Design Lab
Internet: eleleetk@nusunix2.nus.sg   Microelectronics Div.
Bitnet:   eleleetk@nusvm.bitnet or   Dept. of Electrical Engineering
          ltk@nuseev.bitnet          National University of Singapore
Voice:    (065)-772-6319             10 Kent Ridge Crescent
          (065)-467-1518             Singapore 0511
----------------------------------------------------------------------
From: iggy@uts.amdahl.com (Igor Braslavsky)
Newsgroups: comp.lsi.cad,comp.windows.ms
Subject: schematic capture pgm for MS Windows?
Keywords: logic design, netlist generation
Date: 18 Aug 92 20:09:09 GMT
Followup-To: poster
Organization: Amdahl Corporation, Sunnyvale CA

Does anyone know if there is(are) schematic capture programs 
made for MS Windows.  

If so, which company (ies) make them.

thanks,

- igor
From: scott@hpcvccl.cv.hp.com (Scott Linn)
Newsgroups: comp.lsi
Subject: Re: Die aspect ratio.
Date: 14 Aug 92 18:47:22 GMT
Article-I.D.: hpcvca.1992Aug14.184722.1883
Organization: Hewlett-Packard Company, Corvallis, Oregon USA

krste@ICSI.Berkeley.EDU (Krste Asanovic) writes:
: 
: Rectangular die give more perimeter per unit area if a design is pad
: limited. What's the largest sensible/known aspect ratio? (We've done
: one processor die with an aspect ratio of 2.3:1).

We have some die over 3.5:1 (not processors).

Check out some of the large Drams; they are typically long & narrow.

Scott Linn
scott@hpcvccl.cv.hp.com
Xref: sparky comp.lsi:524 comp.lsi.cad:868 comp.lsi.testing:178
From: lazzaro@boom.CS.Berkeley.EDU (John Lazzaro)
Newsgroups: comp.lsi,comp.lsi.cad,comp.lsi.testing
Subject: Re: High Voltage CMOS -- Prototyping ?
Date: 13 Aug 1992 18:11:47 GMT
Organization: University of California at Berkeley
Distribution: inet
NNTP-Posting-Host: boom.cs.berkeley.edu
Keywords: CMOS, Prototyping

In article <24794@castle.ed.ac.uk> gaa@castle.ed.ac.uk (G Allan) writes:
>High Voltage CMOS -- Prototyping ?
>
>I'm looking for  silicon foundries  that provide a low volume
>prototyping service for high voltage (>= 10 Volts) CMOS. 
>

There's a TR out from Lincoln Labs (TR 824, Floating Gate Circuits in MOSIS,
J.R. Mann) that describes techniques for doing high-voltage NFETs and PFETs
in the Mosis low-noise analog process. I have fabbed the circuits from this
TR and they have worked very well, providing 0-5V input levels, 0-25V output
levels, with no static current consumption. I have also made bipolar drivers
in this process, using a floating NPN transistor and a well resistor pullup,
that worked well at 60V, but of course had considerable static current in
one state.
From: joel@ce.ucsc.edu
Newsgroups: comp.lsi
Subject: Re: Large IO Packages
Date: 17 Aug 1992 17:57:30 GMT
Organization: Computer Engineering, UC Santa Cruz
Distribution: usa
NNTP-Posting-Host: arapaho.ucsc.edu
Originator: joel@arapaho

In my ealier post, the device dimensions should be measured in
millimeters, not centimeters.

joel

Newsgroups: comp.lsi,comp.lsi.cad