From: johnson@vixvax.mgi.com
Newsgroups: comp.os.os2.misc
Subject: Re: OS2 SIMM Question
Date: 16 Apr 92 12:59:32 GMT
Article-I.D.: vixvax.1992Apr16.075932.1779
Organization: Management Graphics, Inc.

In article <43TaJB2w164w@ersys.edmonton.ab.ca>, ersys!bking@agchem.redwater.iol.ca (Barry King) writes:
> jpollard@silver.ucs.indiana.edu writes:
> 
>> The mixing of 3 and 9 chip SIMMs is not recommended, but can I expect
>> it to work ?
>> 
> 
> It certainly didn't work for me...I have a machine that (now) has 8 Mb of 
> 1 Mbx9 SIMMS (4 are 80 ns and 4 are 70 ns -- I couldn't get 80's!!!).  
> [stuff deleted] 
> What I find very strange is that electrically, the 3 chip SIMMs should be 
> (have to be ???) electrically tthe same as the 1Mbx9 units.  I'd love to 
> hear a technical explaination of this phenomenon from some 
> elctrical/electronic engineer type person.  I suspect that it must be the 
> fault of the motherboard...
> [stuff deleted]
>
> Barry King              bking@ersys.edmonton.ab.ca
> Edmonton Remote Systems:  Celebrating 10 years of service to Northern Alberta

The biggest difference between a 9 vs 3 chip (1Mbx9 SIMM) is the capacitive
load the memories present to the address drivers.

A little explanation first.  A SIMM module is just a small PC board with a
number of DRAM chips, in this case configured for 1Mx9.  The most popular
way of creating this configuartion is to use 9 1Mbx1 DRAM chips.  That is
changing now that 4M DRAMs are common; 2 1Mbx4 and 1Mbx1 DRAM chips can
create the same configuration.

Now assuming that the board driving these memories has been desinged correctly,
the two variations of the same configuration should work.  From experience,
I can tell you that that is no easy feat.  I'll attempt to explain the
biggest challenge (warning, this could be boring for some!).

Each DRAM storage area is basically a very small capacitor.  The more DRAM,
the more capacitance.  But the capacitance is related to the size of the
storage area.  Thus a 4Mx4 chip will pose less capacitive load than 4 1Mx1
chips due to downsizing of each indivual storage area.

Here some capacitance values (from a MICRON data book):
				1Mx9 (9 chip)	1Mx9 (3 chip)
In Cap: A0-A8		cI1	45pF,max	15pF,max
In Cap: RAS,CAS,WE	cI2	63pF,max	21pF,max
In Cap: D		cI3	7pF,max		7pF,max
I/O Cap: DQ		cIO	12pF,max	7pF,max
Out Cap: Q		cO	7pF,max		7pF,max

On the motherboard, only the capacitive loads of cI1 and cI2 cause any
problems.  That is because an address line must go to every DRAM chip,
data lines only need to go to the chips constituting their respective
bits.  RAS and CAS lines have a similar load to address lines, thoug
less pronounced.

All this capacitive load creates a challenge in maintaining valid
digital signals to interface to the memory.  You need lots of drive
current to overcome the capacitive loads.  The designers has to provide
for the load of a fully loaded board.  Think of a truck engine that must
have enough power to pull a loaded semi.  If the load is lightened 
(less memory) there can be too much power.  In this case the semi
spins its wheels when starting, screeches to a halt when stopping.
In the digital world, that corresponds to overshoot and undershoot
as well as ringing.  The solution?  series resistors.  When you
change your memory configuration you usually change (remove, add)
series resistors (those small skinny packs with 9 or ten pins).

Anyways, getting back to your original problem, you probably have a
case of too much drive with your 3 chip DRAM modules.  You need
to limit that drive through the appropriate series resistors.  Did
you remove any resistors, are there any present to install, are
there any value recommendations in your manual or on the motherboard?

Hope this helps, feel free to ask for further explanations.
-- 
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