HDTenEightyP/NetNews huggingface dataset:
From: rainer@spot.Colorado.EDU (Rainer Malzbender)
Newsgroups: comp.sys.m68k
Subject: Re: MC68681 DUART help
Date: 8 Apr 92 18:04:56 GMT
Article-I.D.: ucsu.1992Apr8.180456.25022
Organization: University of Colorado, Boulder

I think some misinformation has been given out here: there is a big
difference between disabling the transmitter and disabling the transmitter
interrupts. The latter is all that is required in the case referred to by
the original poster.

-- 
Rainer Malzbender 
Post-doc, Physics
U. of Colorado, Boulder (303)492-1366              rainer@shelley.colorado.edu
From: mjs@hpfcso.FC.HP.COM (Marc Sabatella)
Date: Mon, 6 Apr 1992 17:45:26 GMT
Subject: Re: MIPS/MFLOPS ratings
Organization: Hewlett-Packard, Fort Collins, CO, USA
Newsgroups: comp.sys.m68k

In comp.sys.m68k, rh2y+@andrew.cmu.edu (Russell E. Hoffman, II) writes:

> Oh, and for any interested parties, I have heard tell of a 68040 OS9/68000
> box doing just over 26,000 dhrystones/sec.

With sufficiently good global optimization on 1.1, a 25 Mhz 68040 can report
almost 40,000 even running Unix - and even 2.1 can report well over 30,000.
With interprocedural optimizations, the 1.1 number can more than double.  This
is why Dhrystones are not particularly interesting.

--------------
Marc Sabatella (marc@hpmonk.fc.hp.com)
Disclaimers:
	2 + 2 = 3, for suitably small values of 2
	Bill (H.) and Dave (P.) may not always agree with me
From: jfw@ksr.com (John F. Woods)
Newsgroups: comp.sys.m68k
Subject: Re: Pure Segmentation on 68K's
Date: 15 Apr 92 11:49:50 EDT

dnichols@ceilidh.beartrack.com (Don Nichols (DoN.)) writes:
>In article <11399@ksr.com> jfw@ksr.com (John F. Woods) writes:
>>icsu8209@cs.montana.edu (Glassy) writes:
>>>A beginner question on the 680[234]0 architecture:
>>>Does Motorolla make any MMU chips that do or can use pure segmentation
>>>for managing memory?
>	[ ... ]
>>>I've heard of the 68451 (is that the #?) MMU, but thought it was a
>>>paging-oriented unit.
>>I'm pretty sure '451 is the number of the segmented MMU ('851 is the PMMU).
>>It was never too popular, and I wouldn't be surprised if Moto wasn't making
>>it any more (in fact, I wouldn't be too surprised if the architect hadn't been
>>taken out into the parking lot and machine-gunned... :-).
>	[ ... ]
>>The '451 required segments to be a power-of-two length, and you got a fairly
>>small number of them.
>>[My apologies to the architect of the '451, who almost certainly wasn't
>>machine-gunned and no doubt had very good reasons for why it came out the
>>way it did.]
>	Well, before he was "fired" :-), the 68451 found its way into the
>COSMOS CMS16/UNX (a 68000-vanilla computer in Intel multibus).  It ran a
>UniSoft port of v7 unix, and the cpu couldn't handle page faults (that
>didn't come till the 68010), so a paging MMU wouldn't be of any use.

I've had one complaint that I may be mistaken on the capabilities of the
'451, and I can't find a handy data book with that part in it (it has been
a long time since I participated in the decision not to use whatever 68000
MMU it was that we rejected).  Could someone with the data sheet post a
genuine description of the part so I know whether or not to buy some machine
gun bullets :-) ?
From: green@eniac.seas.upenn.edu (Bradley Green )
Newsgroups: comp.sys.m68k
Subject: 680x0 vs 80x86
Date: 8 Apr 92 17:59:24 GMT
Organization: University of Pennsylvania

I am trying to decide between the Motorola and Intel processor series
for a project.  I much prefer working with the Motorola systems, but 
wonder about comparative performance.  My project involved mostly integer
computations, so FPU performance is not very important.  Have any of you
seen a valid-looking comparison between these processors?

Brad
From: kdarling@garfield.catt.ncsu.edu (Kevin Darling)
Newsgroups: comp.sys.m68k
Subject: Re: m68k compatible single chip computer
Date: 15 Apr 92 23:20:20 GMT
Organization: North Carolina State University

Malte Uhl writes:
> I'd like to know if there is a single chip version integrating a 680x0,
> DMA, a 68[48]51 MMU, timers and serial ports [..]

The Philips/Signetics 68070 is a CMOS 68010-ish clone, with a small MMU,
two DMA channels, 16-bit timer/counter, two 16-bit match/count/capture
registers, one UART and an I2C bus.  Ask for the hard&software manuals.
Signetics,  811 E. Arques Ave,  P.O. Box 3409, Sunnyvale, CA. 94088-3409
(408) 991-2000
 
If you also need an OS, both OS-9 and UniFlex are available, I believe.
Microware (OS-9) is 515-224-1929; I don't have TSC's (UniFlex) # handy,
but they're still in Chapel Hill, NC.... company name may be UniFlex now.

> If there is, are there already small, battery powered portables
 
Haven't heard of any, altho there are at least two commercial OS-9/68070
systems with onboard NTSC color video/DRAM controllers available.  Haven't
tried running them off a battery yet, and both are about 5" disk-sized.

kevin <kdarling@catt.ncsu.edu>
From: drchip@cup.portal.com (MYRON A LIEBERMAN)
Newsgroups: comp.sys.m68k
Subject: Re: Underdriving a 68882-50
Date: Mon, 13 Apr 92 21:21:36 PDT
Organization: The Portal System (TM)

Are there any problems with underdriving a 50 MHz 68882 at 25 or 33 MHz?
From: jgp@fct.unl.pt (Jose Goncalo Pedro)
Newsgroups: comp.sys.m68k
Subject: Re: fast reversal of a bit field
Date: 9 Apr 92 15:41:20 GMT
Organization: Universidade Nova de Lisboa -- Lisbon, Portugal

In article <4084@sumax.seattleu.edu> joberreu@sumax.seattleu.edu (Jesse Oberreuter) writes:
   In article <bnell.702662114@ferrari> bnell@ferrari.siemens.com (Bill Nell) writes:
   >Does anyone know a fast way of reversing the bits in a 16 or 32 bit
   >number?  What I mean is if you start of with 011010 (for example)
   >to change it to 010110.  Right know I am just doing a simple rol.l
   >checking the carry flag and setting a bit in a temporary register
   >					Thanks,
   >					Bill

	I haven't done any 68000 yet (waiting for the rest of my MM/1), but
   (pulling out my 68000 Moto manuals), why not do it the 6809 way:

   ROL a bit out of one number and ROR it into another, or ROR , ROL.

	The carry holds the bit being shifted between rotates.  Instead of
   sending the bit into the next var the opposite way it came out, send it
   in from the same direction, reversing the bit order.  Be sure to shift all
   8/16/32 bits (size of vars)!

					     Jesse Oberreuter
					     joberreu@seattleu.edu

   Or, you can setup an array of 256 bytes with the mapping
array[i] = reverse(i) and then, for each 8 bits of the number you
index into the array an get the reversed number. You only need to do
this 4 times for 32 bits as opposed to 32 times for (rol.l, ror.l). I
am not versed in 68000 language, so I cannot give you code details...

   For setting up the array, you can either hard-code it in the source
file, or compute it before needed with the ror.b, rol.b instructions.

bye
-jgp
--
Jose Goncalo Pedro                    BITNET/Internet: jgp@fct.unl.pt
 +---------------------------------+               UUCP: jgp@unl.uucp
 |   Departamento de Informatica   +----------------------------------+
 |   Universidade Nova de Lisboa      2825 Monte Caparica, PORTUGAL   |
 +--------------------------------------------------------------------+
From: dnichols@ceilidh.beartrack.com (Don Nichols (DoN.))
Newsgroups: comp.sys.m68k
Subject: Re: Pure Segmentation on 68K's
Date: 14 Apr 92 02:18:42 GMT
Organization: D and D Data, Vienna Virginia

In article <11399@ksr.com> jfw@ksr.com (John F. Woods) writes:
>icsu8209@cs.montana.edu (Glassy) writes:
>>A beginner question on the 680[234]0 architecture:
>>Does Motorolla make any MMU chips that do or can use pure segmentation
>>for managing memory?

	[ ... ]

>>I've heard of the 68451 (is that the #?) MMU, but thought it was a
>>paging-oriented unit.
>
>I'm pretty sure '451 is the number of the segmented MMU ('851 is the PMMU).
>It was never too popular, and I wouldn't be surprised if Moto wasn't making
>it any more (in fact, I wouldn't be too surprised if the architect hadn't been
>taken out into the parking lot and machine-gunned... :-).

	[ ... ]

>The '451 required segments to be a power-of-two length, and you got a fairly
>small number of them.
>
>[My apologies to the architect of the '451, who almost certainly wasn't
>machine-gunned and no doubt had very good reasons for why it came out the
>way it did.]

	Well, before he was "fired" :-), the 68451 found its way into the
COSMOS CMS16/UNX (a 68000-vanilla computer in Intel multibus).  It ran a
UniSoft port of v7 unix, and the cpu couldn't handle page faults (that
didn't come till the 68010), so a paging MMU wouldn't be of any use.  The
CPU and MMU were on a small daughter board which plugged into the CPU socket
on the CPU board.

	I've still got the machine, and it still works, it just uses more
power/computron than any three other systems in the house, so it is usually
powered down, except when I need to use it to read a 9-track tape, or when
the winter is very cold.

-- 
Donald Nichols (DoN.)     | Voice (Days): (703) 704-2020 (Eves): (703) 938-4564
D&D Data                  |  Email: <dnichols@ceilidh.beartrack.com>
I said it - no one else   |         <dnichols@ceilidh.aes.com>
	--- Black Holes are where God is dividing by zero ---
From: tom@afthree.as.arizona.edu (Thomas J. Trebisky)
Newsgroups: comp.sys.m68k
Subject: Re: Underdriving a 68882-50
Date: 14 Apr 92 21:26:18 GMT
Organization: University of Arizona, Tucson, AZ

drchip@cup.portal.com (MYRON A LIEBERMAN) writes:
>Are there any problems with underdriving a 50 MHz 68882 at 25 or 33 MHz?

The MC68000 Family Reference indicates the min clock speed for a 50Mhz
part is 25 Mhz, so that would be fine.

This kind of thing suprised me at first, but someone explained that parts
like this (and the 68020, 030, ...) use DRAM cells internally and that if
run at too slow of clock speeds they in essense don't get refreshed.

Wanna trade for a 68882RC25 ?

:-)
--
	Tom Trebisky	ttrebisky@as.arizona.edu
Newsgroups: comp.sys.m68k
From: bruce@heather.pooh.com (Bruce Robertson)
Newsgroups: comp.sys.m68k
Subject: Re: MC68681 DUART help
Date: 8 Apr 92 03:24:10 GMT
Organization: Hundred Acre Consulting, Reno, NV
In-reply-to: sritchie@cs.ubc.ca's message of 6 Apr 92 07:46:28 GMT

In article <1992Apr6.074628.25008@cs.ubc.ca> sritchie@cs.ubc.ca (Stuart Ritchie) writes:

>   I'm writing an interrupt driver for the MC68681 DUART (residing
>   on a MVME188 Hypermodule).
>
>   It looks like the TxRDY interrupt is constantly asserted (my
>   interrupt handler is being constantly invoked with this
>   condition).  I cannot seem to ack this interrupt and cause
>   it to cease.  Reading the interrupt status register does
>   not seem to acknowledge the interrupt.  Surely I don't need
>   to disable the transmitter when I have nothing to transmit,
>   do I?

When you get the interrupt after the last character to be transmitted,
you must disable the transmitter with the Disable Transmitter command.
I don't have my 68681 data sheet handy to point you at a page, but
I've determined by looking at my driver for the chip that the Command
register is at offset 2 from the base of each DUART, and the Disable
Transmitter command is 0x08.  I hope this helps!
--
Bruce Robertson			bruce@pooh.com		Phone: +1-702-329-9333
Hundred Acre Consulting		1280 Terminal Way #26	Reno, NV 89502-3243
From: bruce@heather.pooh.com (Bruce Robertson)
Newsgroups: comp.sys.m68k
Subject: Re: MC68681 DUART help
Date: 9 Apr 92 20:15:45 GMT
	<1992Apr8.180456.25022@ucsu.Colorado.EDU>
Organization: Hundred Acre Consulting, Reno, NV
In-reply-to: rainer@spot.Colorado.EDU's message of 8 Apr 92 18:04:56 GMT

In article <1992Apr8.180456.25022@ucsu.Colorado.EDU> rainer@spot.Colorado.EDU (Rainer Malzbender) writes:
>   I think some misinformation has been given out here: 

There's no misinformation, just two ways of doing the same thing.

>   there is a big
>   difference between disabling the transmitter and disabling the transmitter
>   interrupts. The latter is all that is required in the case referred to by
>   the original poster.

That's all that's *required*, but my point is that disabling the
transmitter does the same thing, is much faster, and works no matter
how you have the interrupts wired up.

Sample code in use since 1984 is available, if anyone is interested.
--
Bruce Robertson			bruce@pooh.com		Phone: +1-702-329-9333
Hundred Acre Consulting		1280 Terminal Way #26	Reno, NV 89502-3243

Newsgroups: comp.sys.m68k
From: gudjm@uniwa.uwa.edu.au (D John McKenna)
Subject: Re: 8 Mhz. proc. at 4 MHz. ??
Organization: University of Western Australia
Date: Wed, 15 Apr 1992 05:24:59 GMT

>Hi, I am building a very simple 68000 based system. The design uses a 4 Mhz.
>processor however, I have a couple of 8 MHz. chips available. To save cost :-)
>is it possible to run the processor at 4 MHz. ? What sort of problems am I
>likely to encounter ?

I just had a look in my 68000 book, and it says that an 8MHz part will
run perfectly happily at 4MHz (but not slower). The first 68k system I
built ran at 4MHz, and I didn't have any problems with it. (Then I stuck
a 16MHz into an 8MHz board, and it ran fine too. I think this is a
general trend - you can run these beasties at half their rated speed,
but not much slower)

John West
-- 
gudjm@uniwa.uwa.edu.au  For the humour impaired: insert a :-) every 3 words
From: gcall@phx.mcd.mot.com (Glen Call)
Newsgroups: comp.sys.m68k
Subject: Re: MC68681 DUART help
Date: 8 Apr 92 22:28:46 GMT
Organization: Motorola Computer Group, Tempe, Az.

In article <1992Apr6.132622.10098@cc.gatech.edu> byron@cc.gatech.edu (Byron A Jeff) writes:
>[ I'm posting because I think other folks might be interested it this... ]
>
>In article <1992Apr6.074628.25008@cs.ubc.ca> sritchie@cs.ubc.ca (Stuart Ritchie) writes:
>>I'm writing an interrupt driver for the MC68681 DUART (residing
>>on a MVME188 Hypermodule).
>>
>>It looks like the TxRDY interrupt is constantly asserted ... [stuff deleted]
>
>Not exactly. Once the transmitter has sent the last character it is ready
>for another. So it asserts TxRDY indicating it's willingness to accept
>another character. To get TxRDY to unassert would require transmitting
>another character (i.e. transmitting another character acks the interrupt).
>But that's not what is needed. Until another character is transmitted the
>interrupt (not the transmitter) needs to be disabled. This can be done by
>setting the TxRDY bit in the interrupt mask register (IMR) to 0. The 
>transmitter will still be ready (and enabled) but the DUART will not
>generate anymore interrupts on that condition until the mask bit is
>reset to a 1.

This works, but be advised it requires that the driver keeps track of the
last value written to this register (write-only!).  This little tidbit
would need to be shared between channels - which is incompatible with
some people's I/O systems.  A work around is to disable the transmitter
itself, re-enabling it when there are characters to send.  The advantage
to this is that this bit is in a register that is unique to each channel -
not shared.  This approach is not as straight-forward, but eliminates
the need to share information between channels.  Your milage may vary, etc.

>[other comments deleted, too]
>>
>>Stuart
>
>BAJ
>---
>Another random extraction from the mental bit stream of...
>Byron A. Jeff - PhD student operating in parallel!
>Georgia Tech, Atlanta GA 30332   Internet: byron@cc.gatech.edu

Glen

------------------------------------------------------------------------------
Glen Call, Firmware Development engineer
Motorola Technical Systems Division,  2900 S Diablo Wy, Tempe, AZ   85282
Voice:  602-438-3438                      UUCP: ...!{asuvax,uunet}!mcdphx!gcall
Domain: gcall@phx.mcd.mot.com             CAUSE: Preserve the 2nd amendment
DISCLAIMER: I don't speak for Motorola.  Everything herein, heretofore, and
hereafter is purely my opinion.
From: hyw@philabs.philips.com (Huay-Yong Wang)
Newsgroups: comp.sys.m68k
Subject: FAQ: 040 user manual
Date: 6 Apr 92 15:29:14 GMT
Distribution: na
Organization: Philips Laboratories, Briarcliff, New York


Where can I get the Motorola 68040's User Manual?
Thanks

Regards,
Huay-Yong
Newsgroups: comp.sys.m68k
From: alanr@liszt.media-lab.media.mit.edu (Alan Ruttenberg)
Subject: bit reversal
Organization: MIT Media Laboratory Music and Cognition Group
Date: Wed, 8 Apr 1992 17:02:43 GMT

In article <bnell.702662114@ferrari> bnell@ferrari.siemens.com (Bill Nell) writes:

   From: bnell@ferrari.siemens.com (Bill Nell)

   Does anyone know a fast way of reversing the bits in a 16 or 32 bit
   number?  What I mean is if you start of with 011010 (for example)
   to change it to 010110.  Right know I am just doing a simple rol.l
   checking the carry flag and setting a bit in a temporary register
   with bset if the carry is set.  I'd like to know if anybody knows
   a faster way to do this (on a 68000).
					   Thanks,
					   Bill

If you have space to space, then the fastest way is with a lookup
table. Use 8 or 16 bits as an index into a precomputed table of bit
reversed values computed any old way.

table[i]=bit-reverse(i)


-alan
Newsgroups: comp.sys.m68k
From: icsu8209@cs.montana.edu (Glassy)
Subject: Pure Segmentation on 68K's
Summary: are MMU's avail. that do pure segmentation?
Organization: Montana State University, Bozeman, MT USA 59715
Date: Sat, 11 Apr 1992 05:55:06 GMT

A beginner question on the 680[234]0 architecture:

Does Motorolla make any MMU chips that do or can use pure segmentation
for managing memory?

I don't mean the restricted form of segmentation used in Intel's
earlier products, nor do I mean "segmentation with paging", the common
modern approach where a segment is made of fixed-size pages.

I've heard of the 68451 (is that the #?) MMU, but thought it was a
paging-oriented unit.

----------------------------

What motivates the queston, is that I'd like do some fiddling with pure
segmentation (segments of arbitrary size) and OS's...  If I can put an
entire data structure (an array, say, or a pointer collection a la
Euclid) in a single segment, I can trap any errant accesses to that
structure via a hardware-provided segment-access mechanism.

This means every such variable reference is secure (or trips an
interrupt).  I know Moto & other architectures have range-checking
instructions available to the programmer, but these provide only
"manual" protection; what I'd like is for that protection to be
"automatic", and non-optional.

Thanks in advance,

Lou.
-- 
               "Open the pod bay doors, Hal."

            icsu8209@cs.montana.edu :: Lou Glassy  
Newsgroups: comp.sys.m68k
From: lydic@ka8lvz.uucp (lydic)
Subject: Re: RS-422 in 68000 system
Organization: organization
Date: Thu, 16 Apr 1992 03:40:43 GMT

In article <73157@netnews.upenn.edu> green@eniac.seas.upenn.edu (Bradley Green ) writes:
>Newsgroups: comp.sys.68K
>Subject: RS-422 on 68000
>Followup-To: 
>Distribution: world
>Organization: University of Pennsylvania
>Keywords: 
>
>I'm trying to build an extremely inexpensive (to produce) single-board
>computer based on an 8 mHz 68000.  I need to get an RS-422 serial interface
>into this system, running at ~232Kbaud (AppleTalk speed, for interfacing with
>Mac's).  My question is this: What hardware (UART chip) will most easily
>work in this system, with the least amount of 'glue' chips?  Also, if
>anyone knows of a site where I could get a pre-rolled interrupt-service
>routine for this interface, it would be very helpful.
>
>Thank all you you very much.
>
>BTW - all of you at Motorola, when are some new 680x0 chips coming out?
>      I don't want to see Intel (yech!) get ahead of you.
>
>Brad

   The 68562 DUSCC works fine in the synchronous modes, however unless you
   want to 'dedicate' the processor to transferring data, you might consider
   using DMA.  At 230,400 bps (standard rate) the character time is about
   35 us.  Even with multi-level fifo, this doesn't get much better.  You might
   also look at the 68300 series (68302 will do it all but is pretty pricey).
   I have a standard interprocessor link using the 68450(DMA)/68562(DUSCC)
   running at 230,400 using an X.25 subset which work fine.

   -.. .

   John W. Lydic Jr              lydic@ka8lvz OR osu-cis!n8emr!ka8lvz!lydic
                                 jwl@ka8lvz   OR osu-cis!n8emr!ka8lvz!jwl
   ... -.-
Newsgroups: comp.sys.m68k
From: james@ee.uts.edu.au (A. James Boswell)
Subject: Motorola Freeware BBS
Organization: University of Technology, Sydney, Australia
Date: Tue, 14 Apr 1992 05:27:17 GMT
Summary: Does anyone know if Motorola's freeware BBS is on the net ?
Keywords: BBS, Motorola

Hi,
does anyone know if the motorola freeware BBS ((512) 891-3733) is
available via telnet (ie on the net) ? If so can you give me the ip #
or the correct machine name ?

Failing that, how about a email address at Motorola ?

Thanks,


James.

A. James Boswell                              _--_|\        PO BOX 123
Senior Technical Officer                     /      \       BROADWAY NSW
Computer Systems Group                       \_.--._*       AUSTRALIA 2007
School of Electrical Engineering                   v        FAX: 61 2 330-2435
UNIVERSITY OF TECHNOLOGY, SYDNEY                            PH:  61 2 330-2382
Newsgroups: comp.sys.m68k
From: joes@gvls2.gvl.unisys.com (Joe Schulingkamp)
Subject: Re: Motorola in Arizona
Organization: Paramax Systems Corporation, Great Valley Labs, Paoli, Pa
Date: Mon, 13 Apr 1992 22:21:06 GMT

In article <1992Apr13.051100.19050@bert.eecs.uic.edu> spiff@iti.org (Jason Leigh) writes:
>Hi,
>	does anyone know where Motorola is in Arizona?  I.e. the city, and/or
>county?  Or perhaps an email address to them.
>
>Please reply to: spiff@bert.eecs.uic.edu
>Thanks.
>
>Jason Leigh

This is what I have on Motorola in Tempe, Arizona:

Motorola Field Service 1-800-528-1908


It's been a while, so someone update me if my info is stale.

Joe Schulingkamp,                | STRESS:   The confusion that is created when
joes@gvls2.GVL.Unisys.COM <-NEW! | one's mind overrides the body's basic desire
PARAMAX (UNISYS Defense Systems) | to choke the living SH-T out of some a--hole
Valley Forge Labs                | who desperately needs it.
From: louis@asterix.drev.dnd.ca (Louis Demers)
Newsgroups: comp.sys.m68k
Subject: Re: Modular 680x0's
Date: 15 Apr 92 19:48:00 GMT
Article-I.D.: asterix.1992Apr15.194800.11015
Organization: Defence Research Establishment Valcartier

In <74098@netnews.upenn.edu> green@eniac.seas.upenn.edu (Bradley Green ) writes:

>This is in response to the question about an integrated 680x0 with a
>serial controller and MMU:

>There are also the 68302 and the 68332; I'm not quite sure what is in these, 
>but they one of them my have a MMU.

Nope,  the 68302 has serial controllers (3 ?) which can run async or sync 
protocols.  It also has a DMA for automatic buffer management and a
SIM (System Integration Module).

The 68332 is also based on a 68K kernel with improvements (a table lookup
instruction among others) 16 sophisticated timers, 1 async serial port,
1 sync serial port (SPI) and a SIM and 2 Kb of RAM.

	Neither of those have MMU's integrated !

	Louis

-- 
| Louis Demers              | DREV, Defence Research Establishment,Valcartier |
| louis@asterix.drev.dnd.ca | POBox 8800, Courcelette,Quebec, CANADA, G0A 1R0 |
|            (131.132.48.2) | Office: (418) 844-4424       fax (418) 844-4511 |
+---------------------------+-------------------------------------------------+
Newsgroups: comp.sys.m68k
From: nap42487@uxa.cso.uiuc.edu (Nishith A. Patel)
Subject: the 040 and 486
Summary: 040 and 486
Keywords: 040
Organization: University of Illinois at Urbana
Date: Wed, 15 Apr 1992 06:00:47 GMT

Any advocacy people reading this?


I'll bet you were expecting more enlightening information on processors here.



Newsgroups: comp.sys.m68k