Newsgroups: comp.arch
From: thompson@aust.inmos.co.uk ()
Subject: ESPRIT Project Info
Reply-To: thompson@aust.inmos.co.uk ()
Organization: INMOS Architecture Group
Date: Mon, 11 Jan 93 14:48:39 GMT

Following the recent discussion about the COMPAQ I/O architecture and the
request for information about the HOLICS project, I thought this might be
of interest:

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            OMI/HIC - Open Microprocessor systems Initiative: 
        High Performance Heterogeneous Interprocessor Communication

The Commission of the EC has given its approval for the ESPRIT-funded OMI/HIC
project (ESPRIT 7252) which will develop the high performance communications
for the Open Microprocessor systems Initiative. The project is concerned with
the development of high performance serial communications for microprocessor
and computer interconnect for use between chips, between boards, between
cabinets and between rooms. This will satisfy the needs for both
processor-to-processor interconnect and processor-to-peripheral interconnect
(possibly employing routing chips for larger systems). Target communication
speeds are 200 Mbits/sec, 1 Gigabit/sec and 2 to 3 Gigabit/sec.

OMI/HIC is a collaborative venture between INMOS (VLSI components and routing
technology), Bull SA (gigabit links), Thomson RCM (optic communcations),
Bull SpA (computer systems), and Thomson-SINTRA ASM (sonar applications),
with associate partners Dolphin SCI Technology AS and the University of Paris
VI. The project is part of the Open Microprocessor systems Initiative which
aims to provide the infrastructure for a complete European microprocessor
capability over the next five years.

The implementation technologies will be CMOS (for lowest cost) and Bi-CMOS
(for highest performance). Implementations for both copper and optic
technologies will be developed. A major goal of the project is to minimise
the cost/performance ratio for both copper and optic interconnect and to
achieve a high level of integration of the communications link drivers.
Within these constraints, designs will be optimised for power-efficiency.

The results of the project will be exploited both in the form of VLSI
components (interfaces, routers, etc) and in the form of macrocell designs
for inclusion in other VLSI chips. As a key enabling technology, the OMI/HIC
interconnect will be used in the construction of Asynchronous Transfer Mode
(ATM) switches, multi-microprocessor systems addressing the full range of
embedded systems applications, next generation mainframe computer systems,
peripherals (eg disk arrays), graphics supercomputers, workstations,
massively parallel supercomputers, consumer electronics (eg HDTV), etc.

Background

High performance information processing in all application areas is rapidly
outstripping the bandwidth and cost- effectiveness of current generation
interconnection systems, and providing a demand for system bandwidth which
scales with system size. In addressing these requirements, a key objective of
the OMI/HIC project is to achieve a high level of integration of interconnect
in VLSI systems. This is critical to the development of high-valency dynamic
routing switches (for scalability and low latency) and dictates the use of
serial interconnect. The OMI/HIC project aims to minimise technological risk
so that its results will be exploited in easy-to-use products that will
provide excellent cost-effectiveness.

Foreseen Market Applications

As a key enabling technology, the OMI/HIC interconnect will be used in the
construction of ATM switches, multi-microprocessor systems addressing the
full range of embeddded systems applications, next generation mainframe
computer systems, peripherals (eg disk arrays), graphics supercomputers,
workstations, massively parallel supercomputers, telecommunications
applications and satellite communications, consumer electronics (eg HDTV),
etc. Whilst the OMI/HIC protocols will support the OMI high level protocols,
the project plans to demonstrate the use of OMI/HIC technology for efficient
low-cost implementations of standards such as the SCI (Scalable Coherent
Interface, IEEE std. 1596-1992) and  Fibre Channel (ANSI X3T9.3).

Results To Date

The project is building on achievements in previous ESPRIT projects (PUMA,
for routing technology, and OLIVES, for optical interconnect). The INMOS
DS-links are being upgraded to operate at 200 Mbits/sec, and the routing
technology is being exploited in the IMS C104 dynamic packet switch chip,
which integrates 32 DS-links onto a single CMOS chip. The demonstration at
the ESPRIT '92 Conference in November 1992 (Brussels) was developed by Bull
at its laboratories in Les Clayes-sous-Bois, near Paris, and shows the
capability of generating signals in the GigaHertz frequency range with a
standard Bi-CMOS technology, thus improving the cost/performance  ratio of 
communication links by two orders of magnitude.

Coordinating Contractor

INMOS (Bristol, UK), a member of the SGS-THOMSON Microelectronics group,
designs and manufactures transputers and a range of modular transputer-based
systems builders' components for the embedded systems and general purpose and
high performance computing markets. The transputer is the world's number two
32-bit RISC processor (according to Dataquest), to which the T9000 adds a
powerful new generation.

Project Manager:
Colin Whitby-Strevens
(colinws@isnet.inmos.co.uk)
(direct line: +44 454 611500)

INMOS                              Tel: +44 454 616616
1000, Aztec West                   Fax: +44 454 617910
Almondsbury
Bristol, BS12 4SQ, UK

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--
Peter Thompson              JANET:    thompson@uk.co.inmos
INMOS Ltd                   UUCP:     ukc!inmos!thompson
1000 Aztec West             INTERNET: thompson@inmos.co.uk
Bristol BS12 4SQ, U.K.      Telephone: +44 454 616616