HDTenEightyP/NetNews huggingface dataset:
From: cwp@idtg.uucp (Chuck Phillips)
Newsgroups: comp.cad.cadence
Subject: BACUP Meeting Agenda
Date: 6 Nov 92 21:46:55 GMT
Organization: Integrated Device Technology, Santa Clara

BACUP (Bay Area Cadence User People) is holding a meeting November 18, 1992.
Below is the agenda for the meeting. I am posting it 1) so that users
interested in attending are aware of the meeting (some people did not
get the snail-mail notice) and 2) so that users outside the bay area can
be informed as to what we are doing in case they would like more details
about specific agenda topics.


===========================================================================
Dear fellow users:

It is time for another BACUP meeting. Since our last meeting 
there has been lots of activity. We have had the International 
Cadence User Group Conference where new officers were 
elected and a formal set of by-laws were adopted. There was also 
a lot of discussion between Cadence and the users regarding user 
concerns. There have also been many things happening within 
Cadence that are of interest to users in general. To help spread 
the word and keep as many people as possible informed about 
these issues I have included time in the agenda for some of these 
issues and activities.

The rest of the agenda will be dedicated to break-out sessions. 
We will again have Cadence technical staff available for these 
break-outs.

I look forward to seeing everyone at the meeting.



Sincerely,
Chuck Phillips
BACUP Chair



AGENDA BACUP Meeting, 11/18/92

Date:	November 18, 1992
Time:	12:00 noon to 4:00 pm
Location:	Tech-Mart


Following is the tentative meeting agenda:

12:00 - 12:30		Welcome/Lunch*

12:30 - 1:00		International Cadence User Group Update
			Chuck Phillips, IDT

1:00 - 1:30		Cadence Communications Update
			Denise Jiminez, Cadence

1:30 - 2:15		SOURCEnet - Cadence's new BBS system
			Jeff Angwin, Cadence & Chuck Phillips, IDT

2:15 - 2:30		Break

2:30 - 4:00		Break-out Sessions:

			* Framework and Skill
			* Place and Route
			* Schematic Capture - Front End Tools

Please RSVP to Chuck Phillips at (408)944-2052 by Monday, 
November 16, 1992. If you need further directions please call 
(408)944-7204.

* Bring your own or buy it there.

===================================================
|Chuck Phillips                                   |                          
|Integrated Device Technology, Inc                |
|2670 Seeley Ave                                  |
|San Jose, CA 95134                               |
|(408)944-2052                                    |
|(408)944-2195 (FAX)                              |
|uunet.uu.net!idtg!cwp                            |
|International Cadence User Group - Co-Chair      |
|Bay Area Cadence User People, BACUP, Chair       |
===================================================
Newsgroups: comp.cad.cadence
From: pas@jupitercmc.ca (Peter Stokes)
Subject: Re: Design Framework II 4.2a Configuration
Reply-To: pas@jupiter.ic.cmc.ca
Organization: Canadian Microelectronics Corporation
Date: Mon, 9 Nov 1992 18:32:54 GMT

In article <1992Nov9.153215.20240@ips.cs.tu-bs.de>, hannken@eis.cs.tu-bs.de (Juergen Hannken-Illjes) writes:
|> To install one seat of Design Framework II 4.2a, I have to select one of our
|> Sparc 4/65 and 4/370. To decide this question, I need to know, if it is
|> possible to install and license (our license will be node locked!!)
|> DFW II on a machine without any graphics and use DFW II on remote X-Terminals
|> or Sparcs running an X11 server?
|> Regards,
|> Juergen Hannken-Illjes - hannken@eis.cs.tu-bs.de - TU Braunschweig (W Germany)

This client-server scenario works for me.   The remote machine
happens to be a graphics 4/470 and my graphics desktop Sparc2 is 
used to display (as in SETENV DISPLAY hostname) the Cadence 
software.  There is no need to have the software disks or
directories or license files visible/mounted on the Sparc2.   

Peter

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Peter A. Stokes ~~~~~~~~ pas@jupiter.ic.cmc.ca ~~~~~~~ (613) 545-2923 ~~~~~
Canadian Microelectronics Corporation ~~~~~~~~~~~ Kingston, Ontario, Canada
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
From: mjohnson@netcom.Netcom.COM (Mark Johnson)
Newsgroups: comp.cad.cadence
Subject: Re: MOS threshold voltage ...
Date: 12 Nov 92 23:20:56 GMT
Organization: Netcom Online Communications Service

In article <1992Nov11.211230.4289@newstand.syr.edu> yegna@cat.syr.edu (Yegnashankar Parasuram) writes:
   What is the lowest threshold voltage that most
   fabrication processes can achieve ? Can it be
   reduced to say 0.3 volts ...
   Are there any disadvantages in reducing it ???


This is a question for your fab vendor to answer.  And
therefore, since Cadence is not a fab vendor, this query
is misdirected.

Nevertheless.

In essence your question asks the fab vendors to modify their
process.  That's not something they normally do; it fouls
up their standard production every-batch-done-the-same-way
methodology.

**Technically speaking** you can set VT to whatever value you
like.  It will cost an extra masking step (implant blocker)
and it will require another processing operation in the fab.

More transistor characteristics besides threshold VT will
change; to name 3 of them: mobility, drain induced barrier
lowering, and subthreshold leakage will all be affected
by additional VT implants.  But your fab vendor can give
you separate SPICE modeling parameters for this new
transistor, once s/he builds some test wafers and measures
the resulting physical transistors on real wafers.

Are there any disadvantages?  Yes.  This will severely
reduce the number of vendors that will take your business,
and it will greatly lengthen the throughput time of your
wafer-lots in fab (because yours is a Special).
Newsgroups: comp.cad.cadence
From: toma@baritone (Thomas Arneberg)
Subject: Re: DIVA extraction of 2-terminal MOS (SIMPLE SOLUTION)
Organization: Cray Research, Inc.
Date: 12 Nov 92 08:45:18 CST

In article <1992Nov11.192130.16923@bcrka451.bnr.ca> why@bnr.ca (Graeme Boyd) writes:
>
>In article <1992Nov11.105929.11702@walter.cray.com>, toma@baritone (Thomas Arneberg) writes:
>> We have encountered a "feature" of DIVA that is driving us crazy.
>> 
>> Sometimes we tie together the drain and source nodes of an NMOS or PMOS 
>> device, to make it into a capacitor. But then DIVA layout extraction 
>> considers it some new two-terminal device, and will not extract it as a 
>> regular MOS device with two terminals tied together.
>> 
>> [....]
>
>This same "feature" is in PDV of EDGE, in both cases one solution is:
>
>        [....]
>
>Hence you require one additional symbol with 3 nodes. Then use the
>netlister(s) to create shorted MOS gates or capacitors depending on
>what the requirements are.
>==========
>Graeme Boyd                      B.N.R. Ltd
>why@bnr.ca                       Ottawa, Canada

Thanks for the suggestion; others have also emailed suggestions to just 
create a new device with fewer terminals.

However, we wanted to avoid this, since it would increase the size and
complexity of our parameterized device library on the schematic side.
Besides, it works fine in Dracula and HSPICE to tie together the drain and
source of a MOS device without having to define a new device! Why should we
jump through hoops just to satisfy DIVA?

SIMPLE SOLUTION (thanks to Steve Hazen)
---------------
We simply changed from the extractDevice() command to the extractMOS()
command in DIVA. The latter command has the smarts to know that the thing
is still a MOS device, even if two terminals are tied together. (It also
has the advantage of automatically getting the length and width, but the
disadvantage of not understanding weird-shaped devices [non-90 degree].)

Thanks to all who responded. (I love this newsgroup!)
  - Tom A.
---------------------------------------------+------------------------------
;-) I'd rather be ____  Thomas R. Arneberg   | Inet: toma@cray.com
:-) singing in a |____| Senior IC Design Eng.| UUCP: ...!uunet!cray!toma
:-) Barbershop  _|   _| Cray Research, Inc.  | CLAIM TO FAME: Loni Anderson 
:-) Quartet!   (_)  (_) Chippewa Falls, Wisc.|   went to my high school 
---------------------------------------------+------------------------------
Newsgroups: comp.cad.cadence
From: hannken@eis.cs.tu-bs.de (Juergen Hannken-Illjes)
Subject: Design Framework II 4.2a Configuration
Organization: TU Braunschweig,Informatik,EIS,West Germany
Date: Mon, 9 Nov 1992 15:32:15 GMT

To install one seat of Design Framework II 4.2a, I have to select one of our
Sparc 4/65 and 4/370. To decide this question, I need to know, if it is
possible to install and license (our license will be node locked!!)
DFW II on a machine without any graphics and use DFW II on remote X-Terminals
or Sparcs running an X11 server?

Regards,
-- 
Juergen Hannken-Illjes - hannken@eis.cs.tu-bs.de - TU Braunschweig (W Germany)
Newsgroups: comp.cad.cadence
From: yegna@cat.syr.edu (Yegnashankar Parasuram)
Subject: MOS threshold voltage ...
Organization: CASE Center, Syracuse University
Date: Wed, 11 Nov 92 21:12:29 EST

Hi,

I understand the threshold voltage of the P and N MOSFETs can be varied
during the fabrication process. 
   
For an NMOS FET  Vt = 0.809 volts (SPICE model)

What is the lowest threshold voltage that most fabrication processes
can achieve ? Can it be reduced to say 0.3 volts ...
Are there any disadvantages in reducing it ???

Thanks,

-Yegna

#########################################################################

The contents of this article are the author's own views - they do not 
represent the view of any organisation such as the CASE centre or 
Syracuse University.

#########################################################################
# Yegnashankar Parasuram.						#
# Graduate Student at CE Department of Syracuse University.		#
# Office  : 2-128, Centre for Science & Technology.			#
# email   : yegna@cat.syr.edu.						#
#########################################################################

"THERE IS NOTHING THAT CANNOT BE DONE, UNLESS YOU THINK IT CAN'T BE DONE"

Newsgroups: comp.cad.cadence
From: reb@cypress.com (Risto Bell/CAD)
Subject: Re: DIVA extraction of 2-terminal MOS
Organization: Cypress Semiconductor Southeast Design Center
	<1992Nov11.192130.16923@bcrka451.bnr.ca>
Date: Thu, 12 Nov 1992 18:58:37 GMT

In article <1992Nov11.192130.16923@bcrka451.bnr.ca> why@bnr.ca (Graeme Boyd) writes:

>  In article <1992Nov11.105929.11702@walter.cray.com>, toma@baritone (Thomas Arneberg) writes:
>  > Sometimes we tie together the drain and source nodes of an NMOS or PMOS 
>  > device, to make it into a capacitor. But then DIVA layout extraction 
>  > considers it some new two-terminal device, and will not extract it as a 
>  > regular MOS device with two terminals tied together.
...
>  This same "feature" is in PDV of EDGE, in both cases one solution is:
>      extractDevice( ngate (gate "G") (ndiff "S" "D") (pwell "B") "nmos4" )
>      extractDevice( ngate (gate "G") (ndiff "D") (pwell "B") "cap3" )
...
>  Hence you require one additional symbol with 3 nodes. Then use the
>  netlister(s) to create shorted MOS gates or capacitors depending on
>  what the requirements are.

We go ahead and maintain the cap form library elements, in part because they
can reduce schematic clutter, but also due to this long-standing Cadence
limitation of basing terminals on logically distinct nets rather than
geometrically distinct terminal connections.

Theoretically you could use multiple device statements as in the following
rough example (sorry its in Edge syntax and its for a resistor not a
transistor):

	dmyterm = or resterm;
	connect ... resterm, dmyterm, by ...;
	...
	dmyres = or resdev;
	device( resdev, resterm = 2 "r0"|"r1", M = "rp" );
	device( resdev, resterm = 1,           no_error );
	device( dmyres, resterm = 2,      dmyterm = 2,      no_error );
	device( dmyres, resterm = 1 "r0", dmyterm = 1 "r1", M = "rp" );

Creation of appropriate dummy copies of device and terminal layers can be
extended to more than two terminals, but at the cost of an exponential number
of device statements.  And your measure statements still have just one
terminal to contend with in the shorted case.

(Diva equivalent to the pdverify no_error option is specify nil for the model
name.)
--
-Risto        reb@cypress.com          "Have you got a 27B stroke 6?"
Xref: sparky comp.cad.cadence:476 eunet.esprit.eurochip:13
From: martin@essex.ac.uk (Colley M J)
Newsgroups: comp.cad.cadence,eunet.esprit.eurochip
Subject: ES2 2030 libraries and Cadence EDGE
Date: 11 Nov 92 12:47:48 GMT
Reply-To: martin@.essex.ac.uk (Colley M J)
Organization: University of Essex, Colchester, UK

HELP!

We have a problem routing standard cell designs, our
configuration is as follows:

Library: ES2 2030 ecpd15 (installed with the FAST design kit)
ECAD:    Cadence EDGE 2.1.f2

When we DRC check a routed design produced by these software systems
it reports 'off-grid' errors on some (not all) of the vias. These occur
mainly on (but not confined to) large tracks where multiple vias are used.
The errors have also been reported on track overlaps that occur at channel
boundaries.

The design consists mainly of standard cells from the ecpd15 library plus a
small number of macro cells (PLAs) generated with the ES2 cell generators.

Has anyone else experienced this problem, and know of a fix/workaround (that
doesn't involve manually placed the vias back 'on-grid').

Thanx in advance.


Martin Colley

Department of Computer Science
University of Essex

email: martin@uk.ac.essex
From: he@tde.lth.se (Shoushen He)
Newsgroups: comp.cad.cadence
Subject: edifin/edifout problem
Date: 6 Nov 92 16:12:48 GMT
Distribution: comp.cad.cadence
Organization: Applied Electronics, Lund University, Lund, Sweden

Hi,

I am a novice user of cadence tools, we are trying to port a library
into the sytem. But it seems to me the edifin /edifout doesn't work
properly. I tried it this way:

Edit a cell layout in cadence, edifout it, and then edifin it again. The
edifin/out all completed without errors pop up. The problem is that all
the pin layers, (metal1 or metal2 with "P" purpose) are gone. They are
replaced with a P_wire layer.

Has any one a fix for this problem?

Thanx a lot!

/Shousheng
--
+-------------------------------------------------------------------+
|  /______~___/_   |   ORi,  Still remember the "Old River" ?       |
|  / o_/ // _%_    |   Tel: +46-(0)46-109469(o); Fax: +46-46129948  |
+-------------------------------------------------------------------+
From: nmartin@cadev6.intel.com (Nancy Martin -iNTEL recruiter)
Newsgroups: comp.cad.cadence
Subject: Job Opening with Intel:  CAD/Simulation Engr., Hillsboro OR
Date: 14 Nov 92 04:09:57 GMT
Reply-To: rcanary@az.intel.com
Distribution: usa
Organization: Intel Corporation, Santa Clara, CA USA


 
Intel Corporation has an opening for a CAD/Simulation Engineer in
Portland, Oregon.  We are posting it in this newsgroup hoping to reach
those of you who might not glance at misc.jobs.offered.  (Comments and
questions are welcome!)
 
This position is for a CAD/CAE Systems Engineer and Administrator in
the Architecture Development Lab's Platform Engineering organization. 
Responsibilities are to provide simulation and modeling support to the
platform development teams and systems administration support for SUN
networked-based workstations running the Cadence Composer CAE tool
suite.  This task includes the definition and the implementation of
appropriate tool usage methodologies in cooperation with the design
teams, modeling support, regular hardware maintenance, and OS and tool
upgrade installations.  In addition, the candidate is expected to
interface with external CAD/CAE tool vendors and other internal design
services and CAD groups; resolve tool problems as they arise in a
timely manner; and define internal training needs and future tool
requirements.
 
Requires BS/MS in CS with emphasis in CAD/CAE plus a MINIMUM of two
years of experience in CAD/CAE tools and system administration. 
Proficiency in C or other high-level modeling languages such as
Verilog or VHDL also required, as well as fami8liarity with basic
CAD/CAE tool usage, top-down design and verification methodology for
board and ASIC design, and familiarity with hardware and SW modeling
techniques.  A strong understanding of UNIX in a SUN network-based
workstation environment is a must.  Hands-on experience in developing
behavioral and RTL models using Verilog or VHDL is highly desirable.  
 
For immediate consideration, email or FAX you resume to:
 
                     Becky Canary
                     Intel Corporation
                     FAX:    (602) 496-0123
                     Phone:  (800) 522-6835
                     email:  rcanary@az.intel.com
 
Newsgroups: comp.cad.cadence
From: pas@jupitercmc.ca (Peter Stokes)
Subject: platforms, operating systems
Reply-To: pas@jupiter.ic.cmc.ca
Organization: Canadian Microelectronics Corporation
Date: Tue, 10 Nov 1992 16:31:51 GMT

I faxed a bunch of questions to our local Cadence office 
and didn't get satisfactory replies on the list appended. 
I haven't tried the CRC on them.  There is considerable 
knowledge on the net and thus this posting.   Any direction 
or comments are appreciated.

Thanks,
Peter

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Peter A. Stokes ~~~~~~~~ pas@jupiter.ic.cmc.ca ~~~~~~~ (613) 545-2923 ~~~~~
Canadian Microelectronics Corporation ~~~~~~~~~~~ Kingston, Ontario, Canada
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


1.  Will Edge run under Solaris 2.0 based SunOS?

2.  Will Cadence 4.2.X run under Solaris 2.0-based SunOS?

3.  Will Edge run on a SparcStation 10 model 41?   Is it
    a supported configuration by the CRC?

4.  Will Cadence 4.2.1 run on a SparcStation 10 model 41?

5.  A SparcStation 10 model 41 has an enhanced pipeline 
    that requires source recompilation.   Does this impact
    Cadence Edge or Cadence 4.2.X?

6.  When will 4.2.1 be available for Silicon Graphics h/w?

7.  Does Edge 2.1f{2,3} take advantage of the GX of a Sun?
    Is this not relevant for 4.2 since 4.2 does not contain
    any graphics drivers (they are built in X windows) ?

8.  What is 4.2.1 release date for Sun platform?
From: toma@baritone (Thomas Arneberg)
Newsgroups: comp.cad.cadence
Subject: DIVA extraction of 2-terminal MOS
Date: 11 Nov 92 16:59:29 GMT
Organization: Cray Research Inc.

We have encountered a "feature" of DIVA that is driving us crazy.

Sometimes we tie together the drain and source nodes of an NMOS or PMOS 
device, to make it into a capacitor. But then DIVA layout extraction 
considers it some new two-terminal device, and will not extract it as a 
regular MOS device with two terminals tied together.

Is there some way to get DIVA extraction to recognize this as a good ol'
MOS device, or do we need to create a brand new custom two-terminal device?

(Sorry if this is a novice question...)

Thanks,
  - Tom A.
---------------------------------------------+------------------------------
;-) I'd rather be ____  Thomas R. Arneberg   | Inet: toma@cray.com
:-) singing in a |____| Senior IC Design Eng.| UUCP: ...!uunet!cray!toma
:-) Barbershop  _|   _| Cray Research, Inc.  | CLAIM TO FAME: Loni Anderson 
:-) Quartet!   (_)  (_) Chippewa Falls, Wisc.|   went to my high school 
---------------------------------------------+------------------------------
From: schludermann@sscvx1.ssc.gov
Newsgroups: comp.cad.cadence
Subject: RFI:Info on 80's GE CALMA displays
Date: 9 Nov 92 15:48:36 GMT
Organization: Superconducting Super Collider Laboratory


  I need any information on the displays that were used on the General electric
CAD system Calma in the later 80's. Things like analog/digital display, 
frequency, input impeadance .. If you know who serviced the that would be
excellent to. I am hoping to install these 21" monitors on my personal cad
system.

Kris
From: cwp@idtinc.UUCP (Chuck Phillips)
Newsgroups: comp.cad.cadence
Subject: Re: RFI:Info on 80's GE CALMA displays
Date: 9 Nov 92 16:41:28 GMT
Organization: Integrated Device Technology, Santa Clara

In article <1992Nov9.094836.1@sscvx1.ssc.gov> schludermann@sscvx1.ssc.gov writes:
>
>  I need any information on the displays that were used on the General electric
>CAD system Calma in the later 80's. Things like analog/digital display, 
>frequency, input impeadance .. If you know who serviced the that would be
>excellent to. I am hoping to install these 21" monitors on my personal cad
>system.
>
>Kris

We still have one or two systems here at IDT. We use them as a backup
for old designs. (Sometimes we need to massage the database before
translation.) I could probably dig up the manuals if you do not get the
info you are looking for.

There were several companies that serviced them. The biggest were G.E.
Computer Services, ASJ, and Ostari. I could also dig up the phone
numbers of at least ASJ and Ostari if I looked real hard. Let me know if
you  need them.

Just curious, WHY? are you looking to use display monitors that are no
longer being built, thus hard to find and hard to maintain? As I
remember, they were ALWAYS burning out parts. In fact, when we had 5
Calma systems on site (at another company) we made sure we had at least
one complete monitor available to use as a backup.

===================================================
|Chuck Phillips                                   |                          
|Integrated Device Technology, Inc                |
|2670 Seeley Ave                                  |
|San Jose, CA 95134                               |
|(408)944-2052                                    |
|(408)944-2195 (FAX)                              |
|uunet.uu.net!idtg!cwp                            |
|International Cadence User Group - Co-Chair      |
|Bay Area Cadence User People, BACUP, Chair       |
===================================================
Newsgroups: comp.cad.cadence
From: hughm@brwah.inmos.co.uk (Hugh McIntyre)
Subject: Re: MOS threshold voltage ...
Organization: INMOS Limited, Bristol, UK
Date: Fri, 13 Nov 1992 16:39:15 GMT

In article <1992Nov11.211230.4289@newstand.syr.edu>, yegna@cat.syr.edu (Yegnashankar Parasuram) writes:
|> Hi,
|> 
|> I understand the threshold voltage of the P and N MOSFETs can be varied
|> during the fabrication process. 
|>    
|> For an NMOS FET  Vt = 0.809 volts (SPICE model)
|>
|> What is the lowest threshold voltage that most fabrication processes
|> can achieve ? Can it be reduced to say 0.3 volts ...

I'm not sure what you are asking here.  Is it:

    a)  The unavoidable variation due to manufacturing tolerances.
or  b)  A deliberate change to get different circuit performance.

If (a):

This depends on how well controlled the process is.  A rough guess might be
+- 100mV (+-0.5V is unlikely!).  Note that all the other transistor parameters
also vary, not just VT.  Whoever gave you the transistor models should be able
to give you proper "corners" rather than this guess.

If (b):

In some cases the VT can be reduced into depletion (less than 0).  NMOS chips
used this.

|> Are there any disadvantages in reducing it ???

The main problem with low VTs is leakage (the transistors may not turn
off very well).  Most chips have a leakage spec (Icc standby, eg 100uA) which
acts as one constraint on VTs.  Lower VTs give more leakage (this is the Ids
for a transistor with Vgs=0 and Vds=VCC).  Conversely, lower VTs give a faster
circuit.

Also, if you want to have more than one VT on the same chip you need an extra
mask, which adds cost.



Hugh McIntyre.
Memory Design, INMOS Ltd, Bristol, UK.
Xref: sparky comp.cad.cadence:464 comp.lsi:683 comp.lsi.cad:1118