From: ishii@mayet.ics.uci.edu (Tadatoshi Ishii)
Subject: Sixth International Workshop on High-Level Synthesis
Newsgroups: fj.meetings
Organization: UC Irvine Department of ICS
Date: 28 Sep 92 18:09:33 GMT
Distribution: fj


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					$B!!!!!!(BFadi J. Kurdahi

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			Fadi J. Kurdahi, Organization Chair
			Dept. of Electrical & Computer Engineering
			University of California at Irvine
			Irvine, CA 92717

			PHONE:	+1 (714) 856-8104
			FAX:	+1 (714) 856-4152
			E-MAIL:	kurdahi@uci.edu, KURDAHI@UCI.BITNET

-----------------------------Cut Here---------------------------------


             Sixth International Workshop on High-Level Synthesis

             Dana Point Resort, Laguna Niguel, California, U.S.A.

                             November 4-6, 1992



      	      Co-sponsored by the ACM/SIGDA and IEEE/DATC

               in cooperation with IFIP/WG 10.2 and 10.5

         and the Irvine Research Unit on Computer Systems Design

 _____________________________________________________________________
|                                                                     |
|                       CALL FOR PARTICIPATION                        |
|_____________________________________________________________________|



This Workshop is sixth in a series of high quality technical interna-
tional workshops.  The workshop is oriented towards design automation
professionals  and presents the latests results in high level synthe-
sis especially  concentrating on system level design and system level
design tools,  synthesis and optimization algorithms, synthesis envi-
ronments, as well as on specification and verification issues.  Addi-
tional  panels will  discuss  today's high level synthesis  situation
with  respect to real  needs and real tools as well as concentrate on
the future of high level synthesis.

The Program Committee selected 35 papers out of 70 submissions. Papers
will be  presented in 8 sessions of  two hours each,  starting with 15
minute  verbal presentations,   followed by a poster discussion during
which refreshments will be served.



 _____________________________________________________________________
|                                                                     |
|                            STEERING COMMITTEE                       |
|_____________________________________________________________________|


                   Workshop Chairperson

                   Wolfgang Rosenstiel
	           FZI and University of Tuebingen
                   Fakultaet fuer Informatik
                   D-7400 Tuebingen, Germany
                   Phone: (721) 9654-402 or (7071) 29-5482
                   FAX:   (721) 9654-409 or (7071) 29-5958
                   rosenstiel@peanuts.informatik.uni-tuebingen.de


                   Technical Program Chairperson

                   Daniel D. Gajski
                   Department of Computer Science
                   University of California
                   Irvine, CA 92717, U.S.A.
                   Phone: (714) 856-4155
                   FAX:   (714) 856-4056
                   gajski@ics.uci.edu


                   Benchmark Coordinator

                   Nikil Dutt
                   Department of Computer Science
                   University of California
                   Irvine, CA 92717, U.S.A.
                   Phone: (714) 856-7219
                   FAX:   (714) 856-4056
                   dutt@ics.uci.edu


                   Local Arrangements

                   Fadi J. Kurdahi
                   Department of Electrical & Computer Engineering
                   University of California
                   Irvine, CA 92717, U.S.A.
                   Phone: (714) 856-8104
                   FAX:   (714) 856-4152
                   kurdahi@balboa.eng.uci.edu



 _____________________________________________________________________
|                                                                     |
|                      TECHNICAL PROGRAM COMMITTEE                    |
|_____________________________________________________________________|


                   Robert K. Brayton, UC Berkeley, U.S.A.
                   Robert Brodersen, UC Berkeley, U.S.A.
                   Raul Camposano, GMD/EIS, Germany
                   Francky Catthoor, IMEC, Belgium
                   Giovanni De Micheli, Stanford Univ., U.S.A.
                   Mohamed I. Elmasry, Univ. of Waterloo, Canada
                   Emil F. Girczyc, Synopsys, U.S.A.
                   Satoshi Goto, NEC, Japan
                   Steve Y-L Lin, Tsing Hua Univ., Taiwan
                   Lev Markov, Recal Redac, U.S.A.
                   Michael McFarland, Boston College, U.S.A.
                   Yukihiro Nakamura, NTT, Japan
                   Alice C. Parker, Univ. of Southern CA, U.S.A.
                   Pierre G. Paulin, BNR, Canada
                   Gabriele Saucier, INPG/CSI, France
                   Donald E. Thomas, CMU, U.S.A.
                   Wayne Wolf, Princeton Univ., U.S.A.




------------------------------------------------------------------


				PROGRAM
				=======



 		       TUESDAY, NOVEMBER 3, 1992


6:00 pm - 8:00 pm	Registration



		      WEDNESDAY, NOVEMBER 4, 1992

8:00 a.m. 	Breakfast

8:30 a.m.  	Session 1
         System and Systems Tools
		(Chair: W. Rosentstiel)

On the Application of Architectural Synthesis in the Design
of High volume Production ICs for Consumer Applications
R. Rosa, J. Biester and J.V. Meerbergen - Philips,
The Netherlands

Integration of Signal Processing Systems on Heterogeneous
IC Architectures
G. Goossens, F. Catthoor, D. Lanneer and H. De Man - IMEC,
Belgium

A Methodology for Production Use of High-Level Synthesis
R. Bergamaschi, A. Kuehlmann, S.Wu, V.Venkataraman,
D. Reischauer and D. Neumann - IBM, USA

The Siemens High-Level Synthesis System CALLAS
J. Biesenack, M. Koster, T. Langmaier, S. Ledeux,
M. Payer, M. Pilsl, S. Rumler, H. Soukup, A. Stoll,
N. Wehn and P. Duzy - Siemens, Germany

DSP Design Tool Requirements for the Nineties:
An  Industrial  Perspective
P. Paulin - BNR, Canada

10:30 a.m.	Session 2
 Control, Datapath, and Interface Synthesis
   	(Chair:  L. Markov -  Racal Redac, USA)

Multiplexer Assignment After Scheduling and Allocation Steps
H. Sekigawa, Y. Nakamura, K. Oguri, A. Nagoya,M. Yukishita  - NTT, Japan

Control Path Synthesis in the ADAM System
J-P Weng and A. Parker - USC, USA

Communication Driven Interconnect Synthesis
C. Monahan and F. Brewer - UCSB, USA

Exploiting Scheduling Freedom in Controller Synthesis
J. Nestor and V. Tamas - IIT, USA

Achilles:  A High-Level Synthesis System for
Asynchronous Circuits
J. Cortadella, R. Badia, E. Pastor and
A. Pardo - Poletecnica de Catalunya, Spain


12:30	Lunch
	Welcoming Remarks:  W. Rosensteil

2:30 p.m.   Session 3
	HLS Benchmarking

HLSW92 Benchmarks
N. Dutt - UCI, USA

Synthesizing Behavioral Benchmarks in VHDL into Standard Cell layouts
M. Pilsl - Siemens, Germany
S. Bhattacharya - Duke U., USA
F. Brglez - MCNC, USA

4:00 p.m.  Panel discussion

                  Real needs and Real Tools
                  (Moderator:  P. Paulin - BNR, Canada)



		   THURSDAY, NOVEMBER 5, 1992


8:00 a.m.  Breakfast

8:30 a.m.  Session 4
             HLS Algorithms
    	(Chair:  S. Lin - NTHU, Taiwan)

Scheduling Cyclic Data-Flow Graphs by Retiming
with  Resource Constraints
L-F. Chao and A. LaPaugh - Princeton, USA

A VHDL-Based Scheduling Algorithm for
Control-Flow Dominated Circuits
K. O'Brien, M. Rahmouni, A. Jerraya - IM3/INPG, France

Some Experiments with Low-Level Speculative
Computation Based on Multiple Branch Productions
U. Holtmann and R. Ernst - Braunschwieg, Germany

Synthesis of Rate-Optimal DSP Algorithms by
Pipeline and Minimum Unfolding
L-G. Jeng and L-G. Chen - NTU, Taiwan

Scheduling Constraint Generation for  Communicating Processes
A. Takach and W. Wolf - Princeton, USA

10:30 a.m.  Break and poster discussion

10:30 a.m.  Session 5
  Transformations, Optimization, and Retiming
	  	(Chair:  E. Girczyc - Synopsys, USA)

Process Transformation for System Level Synthesis
J. Hagerman and D. Thomas - CMU, USA

High-Level Transformations Using Assignment Decision Diagrams
V. Chaiyakul, D. Gajski and L. Ramachandran - UC Irvine, USA

Retiming and High-Level Synthesis
R. Camposano and P. G. Ploger - GMD/SET, Germany

Interface Optimization for Concurrent Systems
under Timing Constraints Using Interface Matching
D. Ku, D. Filo, C. Coelho and G. De Micheli - Stanford, USA

Don't Care Schedules and Behavioral Redundancy
W. Wolf - Princeton, USA

12:30  Lunch

2:30  Session 6
        Specification and Modeling
	(Chair:  K. Wakabayashi - NEC, Japan)

ESP:  An Executable Specification Language for
Mixed Timing Control Circuits
T-A. Chu, H.T.Cao and C. Leung - Cirrus Logic, USA

Modeling Piece-wise Linear and Data Dependent
Signal Indexing for Multi-dimensional Signal Processing
F. Franssen, M. van Swaaij, F. Catthoor and
H. De Man - IMEC, Belgium

Modeling Periodicity by PHIDEO Streams
F. Verhaegh, P. Lippeus, E. Aarts, J. Korst, J. van Meerbergen,
A. van der Werf - Philips, The Netherlands

System Modeling for HLS Using Regularity Extraction
D.S. Rao and F. Kurdahi - UC Irvine, USA

An Application of a Synchronous Reactive
Semantics to the VHDL Language
W.C. Baker and A. R. Newton  -  UC Berkeley, USA

7:30 p.m. Banquet & round table discussion:
	 Beyond High Level Synthesis
		(Host:  D. Gajski - UCI, USA)




		     FRIDAY, NOVEMBER 6, 1992


8:00 a.m. Breakfast

8:30 a.m. Session 7
       Environments and Estimation
		   	(Chair:  P. Duzy - Siemens, Germany)

Towards Optimal System-Level Design
W. Birmingham and M. Haworth -  U of Michigan, USA

Utilizing Meta-Design Information in a Framework Supporting
the Synthesis of Very Large Scale Integrated Circuits
A. Gadient and D. Thomas - CMU, USA

SYLVER:  A System Level VLSI Design Environment
L. Arnstein and D. Thomas - CMU, USA

Rapid Estimation for Parameterized Components
in High-Level Synthesis
P. Jha and N. Dutt - UC Irvine, USA

A Two Level Layout Model for High-Level
Synthesis Based on Superscalar Architecture
Y-C. Hsu and F-Sh. Tsai - UC Riverside, USA

10:30 a.m. Session 8
	Verification and Testing
  		(Chair: TBA)

A Practical RTL Support for High-End  Processor Designs
M. Fujita and T. Matsunaga - Fujitsu, Japan

Formal Verification of High-Level
Synthesis by Means of SFG-Tracing
L. Claesen, M. Genoe, E. Verlind,
F. Proesmans and H. De Man - IMEC, Belgium

Symbolic Verification of Sequential Circuits
Synthesized with Callas
M. Payer, T. Filkorn and P. Warkentin - Siemens, Germany

Synthesis of VHDL Test Environments out
of Temporal Logic Specifications
F. Korf - Oldenburg Univ., Germany

Transformations and Resynthesis for
Testability from RTL Specifications
S. Bhattacharaya - Duke University, USA
F. Brglez  - MCNC, USA, S. Dey - NEC, USA

12:30  Future directions:  W. Rosenstiel

------------------------------------------------------------------------


			Travel Information
			==================

Air travel information:

You can fly into either: John Wayne/Orange County Int'l Airport (SNA),
			 or Los Angeles International Airport (LAX).
			 Both have direct flights from Japan.


Ground travel information:

1. Driving:  From SNA or LAX:
		Take 405 South (merges into 5 South)
		to Pacific Coast Highway Exit, right
		to Dana Point Harbor (2nd traffic light), left
		to Park Lantern (1st traffic light), right
		hotel is at the top of the hill

	    Driving time: From SNA: 30 minutes
			  From LAX: 1-1.25 hours.

2. Shuttle transportation: can be arranged with the Dana Point Resort
   Hotel concierge at the time of reservation.

	    Approximate shuttle cost:     From LAX: $50
			          	  From SNA: $25

------------------------------------------------------------------------


 IEEE/ACM Sixth International Workshop on High Level Synthesis
 =============================================================


		Workshop Registration Form



Name_________________________________________________

Company______________________________________________

Address________________________________________________

City________________State____________ ZIP________________

Membership Status  IEEE-CS____________   ACM_______________

Member Number_________________________________________




FEES (Please circle one)

Advance Registration 		   On-Site Registration
--------------------		   --------------------
Student	  US $120.00		Student 	US $120.00

Member	  US $210.00		Member		US $250.00

Nonmember US $260.00		Nonmember	US $310.00


Fees include: admission to all sessions, Wednesday and Thursday's
lunches, Thursday's banquet, daily refreshments, and one copy of
the handouts.

Advance Registration deadline is Oct. 4, 1992
				 ============

Cash and Checks are available. Sorry, NO credit card is available.
Checks must be in US funds ONLY.  Make checks payable to:

			ACM/IEEE 6th HLSW

Mail checks to:

Fadi J. Kurdahi
Department of ECE
University of California
Irvine, CA  92717 USA

For information call:  +1 (714) 856-8104
or email:  kurdahi@uci.edu

---------------------------------------------------------------------

		Hotel Registration Form
		-----------------------


 		  IEEE Computer Society
 			ACM/SIGDA

 Sixth International Workshop on High Level Synthesis
 ====================================================



Name__________________________________________

Company_______________________________________

Address________________________________________

City_________________State_________Zip___________

Country__________________Phone__________________

Arrival Date_________________Time__________________

Departure Date________________Time_________________

__Single  _____Double:  US $100/day (Please check one)

___Visa _____MasterCard  ___American Express

____  Diner's Club  ___   Carte Blanche

Card Number _______________________________

Expiration Date_______________________________


Signature_____________________________________


Send Registration DIRECTLY to the Hotel
		  ========


Dana Point Resort Hotel
25135 Park Lantern
Dana Point, CA  92629 USA


Or call (Credit Card Reservations ONLY):

Phone:	 +1 (800) 545-7483 (US only)

	 +1 (714) 661-5000 (Overseas)

FAX Reservations:  +1 (714) 661-3688

A deposit to cover your first night stay plus 8% city room tax is
required to confirm and guarantee your reservation.  The deposit is
refundable if the reservation is cancelled 72 hours prior to arrival.
If paying by check, please make the check in US $ payable to the "Dana
Point Resort Hotel" and mail to the address above.  Reservations
received after October 4, 1992 will be on a space available basis
only.  If accommodation requested is not available, a similar
accommodation will be assigned.

-----------------------------------------------------------------------

--
Tadatoshi Ishii
TEL:(714)856-8059;FAX:856-4054	 | When you have eliminated the improbable,
Information and Computer Science,| whatever is left, however impossible,
University of California, Irvine | must be the answer.