From: storm@cs.mcgill.ca (Marc WANDSCHNEIDER)
Subject: Re: 80X86 Architecture Differences
Organization: McGill University, Montreal, Canada
Date: Tue, 15 Sep 1992 15:17:34 GMT

In article <01GOSKLYJ07S000FY4@DRYCAS.CLUB.CC.CMU.EDU> MORRO@DRYCAS.CLUB.CC.CMU.EDU ("John K. Duchowski") writes:
>Hello Everyone,
>
>	Could someone please explain to me in clear, plain English the
>differences between architecture of different 80X86 chips ?  I have a bet
>with a friend of mine who says that in the 80486 the math coprocessor
>is built in ONLY in the chips with clock speeds of 33 MHz and above.  This
>seems odd to me as then what would be the difference between a 25 MHz
>80386 (not SX) and 80486 ?  I would very much appreciate it if the
>explanation would also include few words on the SX, DX, etc variants.
>Thank you.

8086:	16 bit internal registers, 16bit external bus... crappy chip with
	crappy instruction set.  Requires 8087 for floating point

8088:	8 bit external bus, 16bit internal registers, same otherwise -- still
	crappy.  Requires 8087 for floating point

80186:	Not quite sure, but it's supposedly got a few more instructions than
	the 8086.

80286:	16bit chip with full funcitonality of the 8086 + newer 16bit
	protected mode with 24bit addressing for total address space of 
	16MB.  Requires 80287 for floating point.  Available in 6, 8, 10, 12
	16, 20, and 25Mhz clock speeds (not exhaustive list)

80386SX:32bit internal registers, 16bit data bus, 24bit addressing to outside
	world meaning 16MB of addressable memory.  Each 32bit word access
	takes two reads.  Well suited to 16bit nightmares like DOS.
	Instructions take quite a few cycles to execute, and 2 to be issued.
	Requires 387SX for Floating point.  Currently available in 16,
	20, 25, and 33Mhz versions.

80386SLC: Intels laptop chip.  Much the same as the SX with static registers
	and other 'innovative' power saving features.  Don't really know
	much about it.

80386DX:32bit internal registers, 32bit addressing, 32bit external data bus.
	Otherwise, has the same instruction set as the SX, requies 387DX for
	floating point activity.  No caching or buffering really (I believe
	there is some sort of 8byte instruction cache or something like that,
	but nothing to start creaming over.)	Available in 16, 20, 25,
	33 and 40Mhz versions.

80486SX:A marketing move to kill the 386.  It's a 486 chip without the floating
	point unit enabled.  Otherwise it's the same as the 486DX.  Available 
	currently in clock speeds of 16, 20, and 25Mhz

80486DX:One step up from the 386.  Includes floating point unit ('487') built
	in, and has an 8k read cache (NOTE: It is NOT write back, which means
	that systems are still going to need an external cache)
	Instructions take 1 cycle to issue, and typically take a little less
	time than the 386 to execute (although there are exceptions)
	Generally a lot faster.  I've heard some rumors of a 5 stage pipeline
	in this machine, but I have never verified it.  Currently available
	in 25, 33, and 50Mhz versions.


80486DX2:Basically, this chip has a clock speed with which it communicates
	with the rest of the computer, and an internal clock rate which is
	twice as fast.  Although touted as truly innovative by Intel, this
	has been used by Motorola for quite some time now, as well as other
	companies.  Ie.  a 50Mhz DX2 will have a bus speed of 25Mhz but
	will work internally at 50Mhz.

P5:	Intels latest chip coming out this year.  Intel claims that it will
	do 100MIPS (ie 1 instruction 1 = NOP) and the list of features told
	by people are wildly variant.
	Most rumors point to it having a (finally) useful register set without
	any stupid dependancies (which the 386/486 have in Protected mode
	only) and some serious integer and floating point hardware, as well
	as certain superscalar features.  Not quite sure how realistic all
	this is though.
	The name has also been varying wildly from 586 to "the ULTIMATE CISC
	Chip..."


If I have goofed, please don't hesitate to correct me or add something.


Toodlepip!
Marc 'em.


-- 
  storm@cs.mcgill.ca           McGill University         C program run.  Run  
  Marc Wandschneider           Montreal, CANADA          Program run! PLEASE!
      "When 900 years old you reach, look as good you will not." - Yoda
				"Ow!" -J.F.K.~
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