From: neighorn@qiclab.scn.rain.com (Steven C. Neighorn)
Newsgroups: or.general,pdx.computing
Subject: January WV/ACM meeting
Date: 11 Jan 93 17:44:24 GMT
Article-I.D.: qiclab.1993Jan11.174424.5084
Distribution: or
Organization: SCN Research/Qic Laboratories of Tigard, Oregon.

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           ACM Oregon Chapter January "State-of-the-Art" Seminar
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			     VHDL: Fact or Fiction
		      Alan Coppola, Cypress Semiconductor

		    7:00 PM, Wednesday, January 20, 1993

		      Symmetry/Balance Conference Rooms,
			     Deschutes Building
			  Sequent Computer Systems,
			   1450, SW Koll Parkway
				Beaverton, OR. 



Abstract:

VHDL (VHSIC Hardware Description Language) is an IEEE standards language that 
can be used for synthesis, modeling and simulation of digital systems.  At its
heart, it is a parallel language which allows hardware description in a 
portable device and vendor independent manner.  The language is strongly typed,
including hierarchy, functions, libraries, and operator overloading for
for multi-level design.  It also includes a strong and detailed version of 
timing for detailed modeling of digital systems.

The talk will first discuss VHDL and its current commercial acceptance,
followed by technical topics involved in synthesizing the VHDL language into
a Register Transfer Level representation, followed by a Technology Mapping
stage.

We will look at example designs from the PLD/FPGA design arenas, including
finite state machines in synthesizable VHDL, giving instances of VHDL as a
productivity enhancement technique.

After the talk, there will be an informal demonstration of the Cypress Warp
(tm) VHDL logic synthesis compiler.


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				The Speaker

Dr. Alan Coppola has been involved in logic synthesis work for the last eight 
years. At Intel, he was involved in the development of internal finite state 
machine tools and commercial programmable logic device synthesis tools. Then
at Mentor Graphics, he worked on a graphical modeling editor which generated
VHDL code, and on ASIC synthesis tools. For the last three years, he has worked
on a VHDL logic synthesis compiler which supports the Cypress programmable
logic device product line.
 
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		About ACM's State-of-the-Art Seminar Series

ACM Oregon Chapter holds a "State-of-the-Art" seminar each month (usually on
the third Wednesday of the month). Speakers are chosen for their leading-edge
work in their topic. They are also chosen for their ability to present 
their knowledge and experience. Previous speakers include Dr. Ajay
Luthra, Dr. Philip Todd and Dr. Ragu Raghavan.
 
If you are interested in giving a seminar, or know of someone who would fit 
these qualifications, please contact the ACM officers (see below).
 
ACM seminars also feature Coffee and Cookies!!

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Directions:

Sequent is located on the corner of Walker Rd. and 158th in Beaverton.
When you enter the campus, look for signs to the Deschutes Building. The
seminar is in the Balance/Symmetry conference rooms in the Deschutes Building.
 
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ACM Contacts:

Niranjan Ramakrishnan, Chairman (503) 646-6578. E-mail: niranjan@xzact.com
Pat Noziska, Secretary	(503) 228-1400
Steve Neighorn, Treasurer, (503) 524-7348. E-mail: neighorn@qiclab.scn.rain.COM
Michael Witt, Membership Chair, (503) 650-9629.   E-mail: uunet!arts.com!mike

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ACM State-of-the-Art Seminars: Look, Listen, Learn & Leverage!!
-- 
Steven C. Neighorn        neighorn@qiclab.scn.rain.com/neighorn@cse.ogi.edu
SCN Research              "Where we train the Star Fighters who defend the
10635 S.W. 127th Court       frontier against Xur and the Ko-dan Armada"
Tigard, Oregon 97223-1964               home: (503) 524-7348