From: mks@cbmvax.commodore.com (Michael Sinz)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: cisc -vs- risc
Date: 5 Oct 92 16:06:21 GMT
Reply-To: mks@cbmvax.commodore.com (Michael Sinz)
Organization: Commodore, West Chester, PA

"jeff ruck" <jeff.ruck@channel1.com> writes:
>-> And you get all the nice instructions as well.  Just about any
>-> architectural
>-> tricks they can pull in a risc chip for speed can be done in a cisc
>-> chip as
>
>I disagree.  RISC designs, take the R4000SC for example, is designed
>with a nice secondary cache, I just don't think CISC chip developers can
>pack the added "features" of third-generation RISC processors on their
>chips.

This is generally the problem.  A RISC chip tends to be smaller at the
core than the CISC chips.  This makes it easier to build and cheaper to
make.  However, you do get what you pay for...

>-> well.  The 040 averages an instruction every 1.3 clock cycles, which
>-> is how
>-> they get 19.2 mips out of one at 25Mhz.  A good risc chip today gets
>-> 1 per
>-> clock cycle.  They're not that far behind.
>
>I'm not overly familiar with '040 performance, but here are a few facts:
>Second-generation RISC processors (R3000, etc ...) *completed* one
>instruction every 1.2-1.6 clock cycles.  The latest third-generation
>RISC processors (R4000SC, Alpha, etc) *issue* as many as two
>instructions per clock cycle and *complete* 1.2-1.3 instructions per
>clock cycle via superpipelining or superscalar designs.  If an '040 can
>*complete* an instruction in 1. clock cycles then I'm impressed.

The 68040 will *complete* a number of instructions in just 1 clock.  It
will also issue instructions internally as fast as 1 per clock.  The
average of 1.3 cycles per instruction is *completed* instructions.
Now, in a floating point benchmark, this usually is not the case and
it also does not take into account DRAM waitstates.  (The 68040
does have 2 4K internal caches)

>-> Er...I thought the fastest RISC chips actually executed *several*
>-> instructions per cycle?
>
>It's not a matter of how "fast" (i.e. internal clock speed) the RISC
>chip is.  It's more important to note the type of design the RISC chip
>implements.  Simply, superscalar designs initiate pipelines in parallel,
>and superpipelining is pipelining several smaller pipelines.  This is
>what allows the processors to *initiate* more than one instruction per
>clock cycle.  Theorectically, completely 1 insturction per clock cycle
>is ideal, but very difficult to implement.

Actually, with the internal caches of the advanced processor designs,
it may well get to the point where more than 1 instruction per clock
cycle is completed (due to the pipeline).  One instruction can not usually
be done in only 1 clock but you usually don't do just 1 instruction.
Also, depending on how you count clocks, things may either look faster
or slower.  Internally, processors have sub-divided clocks as things
move from one point to another.  These are not allways done as clocks but
are many times done as just simple prop-delays to latch in the next stage of
information.

Watch for future processors in both CISC and RISC that can do more
than one instruction per cycle.  (both issue and complete)  The only
reason they will not be able to always do this is due to the need for
the external bus.  (For example, in the 680x0 family, you can add two
memory locations together and store the result in memory.  With no caches,
this means 4 clocks minimum since the instruction needs to be loaded,
two values need to be read from memory and one value needs to be written.
In a RISC enviroment with no caches, you have 7 cycles since you need to
read the load instruction for the first memory value, read that memory value,
read the next instruction and the next memory value, read and do the add
instruction, and then read the store instruction and store the data.
With caches, all of this gets much different and with the right type of
caches, a CISC system could do it all in 1 cycle as it is one instruction
and all of the data was in the cache)

/----------------------------------------------------------------------\
|      /// Michael Sinz  -  Senior Amiga Systems Engineer              |
|     ///                   Operating System Development Group         |
|    ///   BIX:  msinz      UUNET:  mks@cbmvax.commodore.com           |
|\\\///                                                                |
| \XX/                      Eloquence is vehement simplicity           |
\----------------------------------------------------------------------/