HDTenEightyP/NetNews huggingface dataset:
From: dmccart@gomez.intel.com (D. J. McCarthy)
Newsgroups: comp.sys.intel
Subject: Re: Intel is wasting too much money on ads!
Date: 12 Nov 92 02:20:15 GMT
Distribution: comp
Organization: Intel ASTG, Santa Clara, CA
X-Newsreader: TIN [version 1.1 PL6]

Most of this reply is philosophical, and as always, not indicative of
Intel's real policies.

Thomas Hoberg (tmh@keks.first.gmd.de) wrote:
> I live in Berlin, Germany. Walking through the streets, I see a big
> 486(Intel inside) sign on every second billboard all across the city [....]
> I can not recall that any company however loosely associated with the
> computer industry has ever come close to putting up that many signs.

	I, too, find it unusual to see a computer company advertising so
much in so many different types of media.  (Do the television ads get
broadcast over there?)  But, after all, it's for the same reason that
anyone else advertises: to spread the company name around and get
people to recognize it.


> I've always paid dearly for my Intel CPUs. I used to think that it was
> because they had high R&D costs and low yields. I'm getting my doubts.
> I'd prefer it if Intel were to use it's money pile to make their CPUs
> cheaper not to pay for ads or lawyers to sue the socks off AMD or
> Cyrix. They could just keep on being better instead of trying to rape
> the industry and the computer user.

	I don't know if this is true in Europe, but the prices on most
Intel CPUs here in America have substantially *decreased* since the
trials and the big-time ads have started.

	Ads, trials, and price reductions all stem from a common cause:
competition.  How ads and price reductions stem from competition is fairly
obvious.  How trials stem from competition is something best explained by
someone with more legal experience than I have.


> If this trend continues, I see it
> as my duty as a citizen, to boycott Intel, just as I would (and have)
> boycott a political tyrant.

	You would boycott a company because they spend some money on
advertising?  I think that would make you a very uncommon individual.

	Anyway, if you have gotten this far and you still feel that
Intel is "trying to rape the industry" by advertising, send me e-mail
and we can discuss this philosophy further.



--
| D. J. McCarthy                                         Just an Intel employee
| dmccart@gomez.intel.com                       that happens to have Net access.
| ...!intelhf!mipos3!modl01!dmccart              Not a policy-maker or anything.
Newsgroups: comp.sys.intel
From: jpl@antares.fct.unl.pt (Joao Prospero Luis [ps])
Subject: Re: LOADALL and the 486
Organization: Universidade Nova de Lisboa, PORTUGAL
X-Newsreader: TIN [version 1.1 PL6]
Date: Mon, 9 Nov 1992 11:55:20 GMT

Marcus Jenkins (marcusj@apricot.co.uk) wrote:
: I know this may be an FAQ, but I am just a little confused.  Is
: LOADALL implemented in the 486?  PC Magazine said that it is
: in all processors from 2-486.  It also said that Microsoft use
: the instruction in HIMEM.SYS, SMARTDRV.SYS and RAMDRIVE.SYS in
: MS-DOS.  On the other hand, an instructor from Intel (while lecturing
: on an i386/486 programming and architecture course) alleged that
: LOADALL is only there on 286 and earlier steps of the 386.  Does
: anybody know the REAL answer?  Is there commercial software out
: there that does use this reserved instruction.  This enquiry is
: out of curiosity only - I have no intention of putting LOADALL
: into any of my programs!

	As far as I know (it isnt that much) LOADALL isnt implemented in
the 386, but is simulated by some BIOSes. When it traps an invalid opcode
it goes to check if it is a LOADALL, if it is it is simulated otherwise
it does something else (in fact I think it tests some other invalid opcode
first but I dont remember which). This was confirmed with my AMI BIOS.

	JPL

--
Joao Prospero Luis                 |
Universidade Nova de Lisboa        | Internet: jpl@fct.unl.pt
Faculdade de Ciencias e Tecnologia |
Departamento de Informatica        | Fax:   (+351) (1) 295-5641
2825 Monte Caparica, PORTUGAL      | Phone: (+351) (1) 295-4464
Newsgroups: comp.sys.intel
From: eburk@sfsuvax1.sfsu.edu (Eli Burk)
Subject: windows+intel == video, etc
Originator: eburk@sfsuvax1.sfsu.edu
Organization: San Francisco State University
Date: Wed, 11 Nov 1992 08:32:14 GMT

1) anyone have the press release for intel-windows video announcement?
2) what hardware not discussed in #1 *might* be needed to fully use
   video on a pc.
3) any guesses when the clone makers will have plug and play window 
   video machines?
4) what i read didn't discuss storage at all -- is some kind of 
   compress built-in?
5) will windows+video plus all the coming new intel o/s's cause
   a radical new storage solution? if not -- where is all this
   storage supposed to come from?

** email preferred **

-- 
Basic training in the techniques of cheerleading, including arm motions, cheer-
leading rountines, voice projection, double stunts, pyramid design, along with
a development of safety guidelines, crowd control and teamwork. [class at UNLV]
eburk@futon.sfsu.edu -or- eburk@sutro.sfsu.edu -or- eburk@sfsuvax1.sfsu.edu
From: dmccart@gomez.intel.com (D. J. McCarthy)
Newsgroups: comp.sys.intel
Subject: Plural of Pentium (was Re: Why not INTEL586?)
Date: 7 Nov 92 01:22:45 GMT
Organization: Intel ASTG, Santa Clara, CA
X-Newsreader: TIN [version 1.1 PL6]

I'm not speaking for Intel in any official manner whatsoever.

James Jones (jejones@microware.com) wrote:
> steibel@venus.cs.umbc.edu (David M. Steibel) writes:
>> Therefore, with the Pentium increasing performance through the roof,
>> people will be buying an awful lot of Pentiums.

> Or is that Pentia?  Pentiae?  Assistance from people who took some Latin
> would be much appreciated. :-)


	I just came across this pluralized-Pentium(tm) question earlier
today.  Basically I think it boils down to this:  Pentium is not a
Latin word.  If anything, it's an English word.  It should therefore
follow standard English pluralization rules.

	One Pentium.  Two Pentiums.


--
| D. J. McCarthy                         The moving walkway is now ending;
| dmccart@gomez.intel.com                                please look down.
| ...!intelhf!mipos3!modl01!dmccart
Newsgroups: comp.sys.intel,comp.sys.ibm.pc.hardware,comp.benchmarks
From: clc5q@hemlock.cs.Virginia.EDU (Clark L. Coleman)
Subject: Re: ATI Ultra PRO 24-bit?
Organization: University of Virginia Computer Science Department
Date: Thu, 5 Nov 1992 16:35:21 GMT


Please remove comp.benchmarks from this thread. These postings have nothing
to do with benchmarks.

Thank you.

-- 
--------------------------------------------------------------------------
"It is seldom that any liberty is lost all at once." David Hume
|||  clc5q@virginia.edu (Clark L. Coleman)
Newsgroups: comp.sys.intel
From: gideony@microsoft.com (Gideon Yuval)
Subject: Re: 1-800 number
Date: 10 Nov 92 18:16:10 GMT
Organization: Microsoft Corporation
Distribution: usa

In article <1992Nov10.025128.4363@wam.umd.edu> hibanez@wam.umd.edu (raul) writes:
>Does anyone know the 1-800 number for Intel?  Please mail

555-1212
(the derivation is obvious)
-- 
Gideon Yuval, gideony@microsoft.com, 206-882-8080 (fax:-883-8101;TWX:160520)
From: dmccart@gomez.intel.com (D. J. McCarthy)
Newsgroups: comp.sys.intel
Subject: Re: Plural of Pentium (was Re: Why not INTEL586?)
Date: 9 Nov 92 17:36:38 GMT
Organization: Intel ASTG, Santa Clara, CA
X-Newsreader: TIN [version 1.1 PL6]

Rod Skinner (rskinner@mipos2.intel.com) wrote:
> dmccart@gomez.intel.com (D. J. McCarthy) writes:

\> 	One Pentium.  Two Pentiums.
\ 
\ There is only one way to describe the Pentium (tm) processor.  If you
\ want the plural form...it is Pentium processors.  ALL trademarks are
\ adjectives and therefore only have ONE form.
> 
/ Pentium (tm) CPUs
/ Pentium (tm) microprocessors
/ 
/ Rod Skinner				I speak for myself only.
/ Intel Corp

	Rod is right; I was wrong.  Pentium is indeed an adjective.
I stand corrected.


--
| D. J. McCarthy
| dmccart@gomez.intel.com
| ...!intelhf!mipos3!modl01!dmccart
Newsgroups: comp.sys.intel
From: pfk@rz.uni-jena.de (Frank Klemm)
Subject: Re: Undocumented instructions in x86 CPUs
Reply-To: pfk@rz.uni-jena.de (Frank Klemm)
Organization: Friedrich-Schiller-University Jena, Germany
Date: Mon, 09 Nov 1992 16:29:20 GMT


In article <15341@auspex-gw.auspex.com>, guy@Auspex.COM (Guy Harris) writes:
|> 
|> In addition, AAM is claimed to take 17 cycles in the table on page E-5,
|> and an unsigned divide is claimed to take - surprise, surprise - 14 to
|> 17 cycles with a one-byte operand.
|> 
|> Sounds as if AAM was - at least in the implementations on which you
|> tried it - really the "divide AL by a one-byte immediate operand,
|> stuffing the quotient into AH and remainder in AL" instruction....
|> 
|> 10 hex is 16 decimal, and if D4 10 does a base-16 AAM, then it would be
|> 
|> 	AH = AL >> 4
|> 	AL = AL & 0xF
|> 
|> Try it with hex 11, and see if it does
|> 
|> 	AH = AL / 17
|> 	AL = AL MOD 17
|> 
|> Note, though, that they may have cut corners in future implementations,
|> such as the 586^H^H^HPentium, so that hex A is the only operand that
|> works correctly.
|> 
|> The same, of course, may well apply to *other* undocumented
|> instructions; programmer, beware!  (What's Latin for "programmer"? :-))
|> I've heard a claim that the bit-field instructions didn't completely
|> work, even on the 386; I've no idea whether there's any truth to that
|> claim or not.
|>
This instruction must be supported in future development. Reason is that Borland
uses this trick in it libraries. If this instruction is not supported, many program
do not run. I think I'm right.

Frank

examples: printf, scanf ...
Newsgroups: comp.sys.intel
From: fineberg@win31.nas.nasa.gov (Samuel A. Fineberg)
Subject: re: Intel internet addresses
Organization: CSC, NASA Ames Research Center, NAS Division
Date: Fri, 13 Nov 92 22:17:53 GMT
Reply-To: fineberg@nas.nasa.gov

In article <1e0muoINNcja@usenet.INS.CWRU.Edu>, rrn@po.cwru.edu writes:
|> 
|> When is the latest word from the money grubbers at intel as to when
|> the P5 is due out?
|> 
|> Thanks
|> BOB
Never.  However, the Pentium (TM) CPU is due some time next year (after
their 486DX2-66 sales start to flatten out).

Sam
Newsgroups: comp.sys.intel
From: mkd@mtung.lincroftnj.ncr.com (Mark Darby)
Subject: CAS assembler for 8051-like uCs
Date: Tue, 10 Nov 1992 21:57:04 GMT
Distribution: usa
Organization: AT&T Bell Labs - Middletown, NJ

Hello:

I'm not sure whether it was this news group or not, but...

someone in the past posted an article describing a full featured
assembler package for 8051-ish microcontrollers.  If I remember
correctly, its posted somewhere on a server accessible via FTP.

Could someone please tell me where it is?

Thanks in advance,
Mark Darby
mkd@mtung.att.com / mkd@mtung.lincroftnj.ncr.com
Xref: sparky comp.sys.intel:2215 comp.sys.ibm.pc.hardware:29495 comp.benchmarks:1643
From: tmh@keks.first.gmd.de (Thomas Hoberg)
Newsgroups: comp.sys.intel,comp.sys.ibm.pc.hardware,comp.benchmarks
Subject: Re: ATI Ultra PRO 24-bit?
Date: 11 Nov 92 03:24:30 GMT
	<1992Nov3.060642.21412@cc.umontreal.ca>
	<smithbm.720819736@craft.camp.clarkson.edu>
	<1992Nov05.121925.29865@rz.uni-jena.de>
	<smithbm.721061471@craft.camp.clarkson.edu>
	<1992Nov0
Followup-To: comp.sys.intel
Organization: GMD-FIRST, Berlin
In-reply-to: pfk@rz.uni-jena.de's message of 9 Nov 92 16:18:17 GMT


   |> pfk@rz.uni-jena.de (Frank Klemm) writes:
   |> >Why do this card not support 1152x900x64k and 960x720x16M ???
It might, actually. But you may not want to use that resolution...:-)
For X (and for most other window systems) you may want to reserve some
off-screen storage to cache fonts and small pixmaps. If you go to
1152x900x64k on a 2MB frame buffer, you have nothing left over, which
means blitting characters over the ISA bus. The best theoretical
performance would then be that of a passive monochrome frame buffer on
the ISA bus. With font caching you transfer META information, which is
independent for example of the font size (unless you run out of
off-screen area).
---
Thomas M. Hoberg   | Internet: tmh@first.gmd.de
1000 Berlin 41     |           tmh@cs.tu-berlin.de
Wielandstr. 4      |
Germany            | BITNET:   tmh@tub.bitnet 
+49-30-851-50-21   |

Newsgroups: comp.sys.intel
From: karhinen@klaava.Helsinki.FI (Anssi Karhinen)
Newsgroups: comp.sys.intel
Subject: Re: P24T
Date: 6 Nov 92 06:56:23 GMT
Organization: University of Helsinki
X-Newsreader: TIN [version 1.1 PL6]

Edward McClanahan (edwardm@hpcuhe.cup.hp.com) wrote:
> 
> I imagine that the P24T is to the P5 what the 386SX is to the 386DX (if it
> ever is built).  I.E. while both 386's were 32-bit chips, the SX had a 16-bit
> external data path (but still a 32-bit address path).  I imagine the P24T
> would internally be a 64-bit chip but externally have "only" a 32-bit data
> path.  I wonder about the size of the address path (in either the P24T or P5).

Does the SX really have a 32-bit address bus? I thought it was
only 24 bits. Just 16 MB of memory like on the '286.

Tsup, Anssi
From: terra@diku.dk (Morten Welinder)
Newsgroups: comp.sys.intel
Subject: Re: Undocumented instructions in x86 CPUs
Date: 7 Nov 92 15:45:08 GMT
Organization: Department of Computer Science, U of Copenhagen

mostert@cs.sun.ac.za (A. Mostert) writes:

>In article <1992Nov5.101717.26632@umr.edu> mcastle@mcs213d.cs.umr.edu (Michael R Castle) writes:
>>In article <mostert.51@cs.sun.ac.za> mostert@cs.sun.ac.za (A. Mostert) writes:
>>>I just became aware of an undocumented instruction that (I think) works on
>>>all members of the x86 family. The opcode is D4 10 and it does this:
>                           		         ^^^^
>>>   AH = AL >> 4
>>>   AL = AL & 0xF

>>hmm.... listed in my Microprocessors and Peripheral Handbook... AAM 

>AAM is opcode D4 0A
>AAD is opcode D5 0A

>The second byte is actually a number specifying the base, as various people
>pointed out to me since my original posting. However, only the form with 0A
>as base is officialy documented by Intel. 

>Can anyone tell me if this works on the NEC v20/V30 processors ?

>A. Mostert
>mostert@cs.sun.ac.za

From memory: AAM does, AAD does not.

Morten Welinder
terra@diku.dk
-- 
-----------------------------------------------------------
Signature file under construction -- please drive carefully
-----------------------------------------------------------
                             Morten Welinder, terra@diku.dk
From: guy@Auspex.COM (Guy Harris)
Newsgroups: comp.sys.intel
Subject: Re: Undocumented instructions in x86 CPUs
Date: 9 Nov 92 19:56:38 GMT
Organization: Auspex Systems, Santa Clara

> This instruction must be supported in future development.  Reason is
> that Borland uses this trick in it libraries.

I.e., the trick of using a radix other than 10 in AAM?

AAM with a radix of 10 should, presumably, be supported, given that it's
documented.
From: S_JUFFA@iravcl.ira.uka.de (|S| Norbert Juffa)
Newsgroups: comp.sys.intel
Subject: Re: LOADALL and the 486
Date: 11 Nov 1992 10:50:03 GMT
Organization: University of Karlsruhe (FRG) - Informatik Rechnerabt.
Distribution: world
NNTP-Posting-Host: irav1.ira.uka.de
X-News-Reader: VMS NEWS 1.23

In <veit.721473830@du9ds3> veit@du9ds3.uni-duisburg.de writes:

> In <1992Nov9.115520.5893@fct.unl.pt> jpl@antares.fct.unl.pt (Joao Prospero Luis [ps]) writes:
> 
> >Marcus Jenkins (marcusj@apricot.co.uk) wrote:
> >: I know this may be an FAQ, but I am just a little confused.  Is
> >: LOADALL implemented in the 486?  PC Magazine said that it is
> >: in all processors from 2-486.  It also said that Microsoft use
> >: the instruction in HIMEM.SYS, SMARTDRV.SYS and RAMDRIVE.SYS in
> >: MS-DOS.  On the other hand, an instructor from Intel (while lecturing
> >: on an i386/486 programming and architecture course) alleged that
> >: LOADALL is only there on 286 and earlier steps of the 386.  Does
> >: anybody know the REAL answer?  Is there commercial software out
> >: there that does use this reserved instruction.  This enquiry is
> >: out of curiosity only - I have no intention of putting LOADALL
> >: into any of my programs!
> 
> >	As far as I know (it isnt that much) LOADALL isnt implemented in
> >the 386, but is simulated by some BIOSes. When it traps an invalid opcode
> 
> Actually, LOADALL is two different instructions for 286 and 386.
> It seems that at least the d0/d1 version of the 386DX has the LOADALL386
> instruction. See /pub/pc/infos/loadall*.txt at ftp.uni-duisburg.de for
> information on loadall286 and loadall386.
> Many 386 BIOSes versions emulate the loadall286 instruction, because it
> is used occasionally in some programs (HIMEM uses it, but only when a
> 286 is detected; there is seperate code for 386 which is used if one is
> detected. The loadall386 is by far not so well known.
> 
> >it goes to check if it is a LOADALL, if it is it is simulated otherwise
> >it does something else (in fact I think it tests some other invalid opcode
> >first but I dont remember which). This was confirmed with my AMI BIOS.
> 
> >	JPL
> 
> >--

LOADALL286 is not only used by HIMEM, but by Microsoft's SMARTDRV and RAMDRIVE
programs as well. Various DOS versions had provisions for use of LOADALL286 by
not using the LOADALL parameter area at address 800h. If you want to know what
other programs use LOADALL286, just check the code with a debugger (Turbo
Debugger and CodeView will correctly disassemble the LOADALL286 opcode, 0F05h
I think). LOADALL386 (opcode 0F07h ?) is not widely used. The German computer
magazine c't carried an article about LOADALL386 some time ago, with sample source
code how to use it. They claimed LOADALL386 was used by a Taiwanese VMM
manager.

Norbert
-------------------------------------------------------------------------------
Norbert Juffa         email: S_JUFFA@IRAVCL.IRA.UKA.DE       Live and let live!
From: rskinner@mipos2.intel.com (Rod Skinner)
Newsgroups: comp.sys.intel
Subject: Re: Plural of Pentium (was Re: Why not INTEL586?)
Date: 7 Nov 92 07:10:42 GMT
Organization: Intel Corporation, Santa Clara, CA USA

In article <BxBnty.4Gn@inews.Intel.COM> dmccart@gomez.intel.com (D. J. McCarthy) writes:
>I'm not speaking for Intel in any official manner whatsoever.
>
>James Jones (jejones@microware.com) wrote:
>> steibel@venus.cs.umbc.edu (David M. Steibel) writes:
>>> Therefore, with the Pentium increasing performance through the roof,
>>> people will be buying an awful lot of Pentiums.
>
>> Or is that Pentia?  Pentiae?  Assistance from people who took some Latin
>> would be much appreciated. :-)
>
>
>	I just came across this pluralized-Pentium(tm) question earlier
>today.  Basically I think it boils down to this:  Pentium is not a
>Latin word.  If anything, it's an English word.  It should therefore
>follow standard English pluralization rules.
>
>	One Pentium.  Two Pentiums.

There is only one way to describe the Pentium (tm) processor.  If you
want the plural form...it is Pentium processors.  ALL trademarks are
adjectives and therefore only have ONE form.  The noun that the 
trademark describes can be either singular or plural as you would
normally do.

Pentium (tm) CPUs
Pentium (tm) microprocessors



>
>
>--
>| D. J. McCarthy                         The moving walkway is now ending;
>| dmccart@gomez.intel.com                                please look down.
>| ...!intelhf!mipos3!modl01!dmccart


Rod Skinner				I speak for myself only.
Intel Corp
3065 Bowers Avenue   MS NW1-20            PH (408) 765-4474
Santa Clara, CA 95052                     FAX (408) 765-4920
Newsgroups: comp.sys.intel
From: kevinm@meadow.uucp (Kevin MacDonald)
Subject: P24 = 486DX2-66 ??
Reply-To: kevinm@meadow.UUCP (Kevin MacDonald)
Organization: Amdahl Canada Ltd., Software Development Center
Date: Wed, 11 Nov 92 23:14:29 GMT

A computer that was said to be a 486DX2-66 had the following printed on
the chip: A80-P24-66. I haven't benchmarked the computer, so I am unaware
if it operates faster than a 486-66 should. The computer with this odd-named	
chip arrived about two months ago.

kevin macdonald
Newsgroups: comp.sys.intel
From: hoyt@isus.UUCP (Hoyt A. Stearns jr.)
Subject: Re: 8096/80196 systems
Followup-To: comp.sys.intel
Keywords: NOT the 80x86 family
Organization: International Society of Unified Science
Date: Thu, 12 Nov 1992 03:06:59 GMT

In article <1992Nov10.012021.23524@ultb.isc.rit.edu> krf1061@ultb.isc.rit.edu (K.R. Flanagan) writes:
>
>	Hi I was wondering if anyone in this group had any practicle 
>    exspereince with the intel 8096 family on 16 bit micro controllers,
>    or if there was a group on this net that dealt with them. Just 
>	Actually I do have a question for anyone out there that might
>    know, I've been looking over a 80196kb board by vesta the last few 
>    days and am very confused how they can get it to support 256k,
>    (128 ram, 128 rom). I'm assuming bank switching but have no clue.
>

It has been a couple of years, but--

I've used it on several occasions, quite a nice processor, unlike the 86
series (more motorola like, regular ).  To extend the address range,
I used the code/data status line (I don't remember what it's called) as
another address line.  Works fine.  That doubles the address space from
64K to 128K.  I don't know how they doubled it again.  Perhaps a port bit,
or could be the newest versions have added address lines, since I used it.

The event capture and PWM stuff is really nifty--great for servo systems,
speed measurement, etc.

I wrote on on-board forth interpretea/compiler for it. It's instruction set
is very well suited for forth.

-- 
Hoyt A. Stearns jr.|hoyt@          | International Society of Unified Science|
4131 E. Cannon Dr. |isus.tnet.com -| Advancing Dewey B. Larson's Reciprocal  |
Phoenix, AZ. 85028 |ncar!enuucp!   | System- a unified physical theory.      |
voice_602_996_1717 telesys!isus!hoyt The Universe in two postulates__________|
Newsgroups: comp.sys.intel
From: smackinla@cc.curtin.edu.au (Pat Mackinlay)
Subject: 386SX has a 24 bit address bus
Organization: Curtin University of Technology
Date: Tue, 10 Nov 1992 10:19:37 GMT


>> ever is built).  I.E. while both 386's were 32-bit chips, the SX had a 16-bit
>> external data path (but still a 32-bit address path).  I imagine the P24T
> 
> Does the SX really have a 32-bit address bus? I thought it was
> only 24 bits. Just 16 MB of memory like on the '286.

You are quite correct. The 386SX parts have a 24 bit address bus. Like the
data bus, it is 32 bit internally, but only 24 bits are brought out. This is
the processor that most closely matches the MC68000 <grin> although it was
brought out years later.

Pat -- Have a day!
Newsgroups: comp.sys.intel
From: jmv@minerva.inesc.pt (Jose Velez)
Subject: Re: Invalid Instruction Sequences on i486 Query
Organization: INESC, Lisboa, Portugal
Date: Fri, 6 Nov 1992 16:41:51 GMT



   Ok, let's hear some interesting stuff...


   Jose'Velez