HDTenEightyP/NetNews huggingface dataset:
From: george@ole.cdac.com (George Lippincott)
Subject: wire primitives in VHDL
Organization: Cascade Design Automation
Date: Tue, 22 Dec 1992 01:45:51 GMT


I am trying to figure out a way in VHDL to merge two bidirectional
signals into one signal.  This is something that most of the major
logic simulators let you do but which as far as I can tell is
impossible in VHDL. 

This situation comes up when an entity is implemented in such a way 
that two bidirectional ports connect to the same signal.  What I
would like to do is have some way to "short" these two signals together.
Ideally the resolution function would see all of the drivers for
both signals and calculate a value for both nets.

This can be done in Verilog like this:
		module wire(w,w)
		inout w;
		endmodule;

I haven't been able to figure out a way to do the same thing in VHDL.
If I use the code:
		a <= b;
		b <= a;

Then a driver is added to both signals and the value gets stuck at 'U'
due to the nature of the resolution function in the IEEE 1167 package.

Does anyone have any idea on how to work around this?

---------------------------------------------------------------------------
George Lippincott               | UUCP:      uunet!ole!george
Cascade Design Automation Corp. | Internet:  george@ole.cdac.com
3650 131st Ave SE, #650         | TEL:       (206)-649-7661
Bellevue, WA  98006             | FAX:       (206)-649-7600
From: wdb@vhdl (William D. Billowitch)
Newsgroups: comp.lang.vhdl
Subject: RE: Conversion of Verilog timing checks to VHDL?
Keywords: VHDL
Date: 18 Dec 92 20:06:14 GMT
Organization: The VHDL Technology Group


In article <dank.724653378@blacks.jpl.nasa.gov>, dank@blacks.jpl.nasa.gov (Daniel R. Kegel) writes:
> Hi all,
> is there an accepted idiom for expressing the sort of timing checks
> supported in Verilog, i.e.
>     $width(negedge x, t0);
>     $setup(x, posedge y, t0);
>     $hold(posedge x, y, t0);
> in VHDL?
> 
> I'm thinking about converting a PD program that generates Verilog
> to also generate VHDL.
> - Dan Kegel (dank@blacks.jpl.nasa.gov)


----- News saved at 18 Dec 92 19:53:13 GMT

The VHDL Technology Group offers a set of VHDL packages
called the Std_DevelopersKit which provides a set of
equivalent timing check routines as provided by Verilog.
In addition, it also provides equivalent mathematical routines
and hundreds of additional functions which VHDL model developers
may need.

Anyone having interest in the Std_DevelopersKit should send
their request (including postal address and phone number) to
the address below and we will be happy to send you a brochure.


Sincerely,

-------------------------------------------------------------
William Billowitch                   e-mail: uunet!vhdl!wdb
The VHDL Technology Group                    vhdl!wdb@uunet.uu.net (internet)
100 Brodhead Road, Suite 140         Phone : 215-882-3130
Bethlehem, PA 18017                  Fax   : 215-882-3133
From: manley@optilink.COM (Terry Manley)
Newsgroups: comp.lang.verilog
Subject: Summary : execution of always blocks
Date: 21 Dec 92 23:57:00 GMT
Organization: DSC/Optilink Access Products

Thanks for all the responses.  I got a lot of great answers.

To summarize:

(Please let me know if I've screwed this up)

The following verilog code:

always @(posedge Clk) c = b;
always @(posedge Clk) b = a;

should not be written since the order of execution of the assignments
is not specified as part of the verilog language - as a side issue it
is important to note that different vendors simulators may behave
differently as a result. 

Solution 1:

I described:

    always @(posedge Clk)
      begin 
        c = b;
        b = a;
      end

Note that here order of execution is specified.
This however forces these assignments into the same always block. 

Solution 2:

Use intra assignment delays:

    always @(posedge Clk) c = #1 b;
    always @(posedge Clk) b = #1 a;

This effectively creates temp variables:

at posedge clock:
	tempb = b
	tempa = a

1 time unit later:
	c = tempb
	b = tempa

Now it doesn't matter which order the always statements execute.
(You can also use #0 if you don't want the delay)

It was also pointed out that in this simple case only a single
delay is necessary on the assignment you want to execute last, ie:

    always @(posedge Clk) c = b;
    always @(posedge Clk) b = #0 a;


Solution 3:

Use non-blocking assignments:

    always @(posedge Clk) c <= b;
    always @(posedge Clk) b <= a;

This works because verilog evaluates (and stores) the right hand side
of each assignment before performing the assignment.  Others have
suggested using a delay here:

    always @(posedge Clk) c <= #1 b;
    always @(posedge Clk) b <= #1 a;

This works, but is unnecessary, and may add the undesired delay
(You could use #0, to avoid the delay, but since you don't need
it why put it in at all?)

Comment: My end goal is to write code to be synthesized using
synopsys.  To my mind it seems 'dirty' to have to include delay
statements in the verilog to get the behavioral code to run properly.
Synopsys has no problem generating the right logic for the original
hunk of code but as we all know it doesn't simulate.  From the
responses I've received it looks like Solution 3 is the best from the
standpoint of not requiring delays.

Thanks again,

dave
manley@optilink.com
Newsgroups: comp.lang.verilog
From: jwest@jake (Jeff West)
Subject: Re: New question - lint like verilog checker
X-Newsreader: Tin 1.1 PL3
Date: 22 Dec 92 09:53:22 CST

manley@optilink.COM (Terry Manley) writes:
: In using the verilog language I've noticed the language
: will allow you to do many things you don't necessarily
: want to do.  Like the C language it is very flexible, 
: unfortunately unlike C there isn't a program verifier
: like lint.  I can think of many things I'd like to be
: checked, things that if checked would eliminate some
: of the debugging phase. (My recent post on execution
: of always blocks is one example, another is missing
: event triggers for always blocks, or declared but 
: unreferenced reg or wire variables, or ....)
: 
: Anybody heard of a tool like this?
: 
: dave
: manley@optilink.com

There is a tool called Verilint from the Veritools company.  I have
no experience with it though.

Jeff

---------------------------------------------------------------------
It's not denial.  I'm just very selective about the reality I accept.

    - Calvin & Hobbs
From: jlodman@cs.ucsd.edu (Michael Lodman)
Newsgroups: comp.lang.verilog
Subject: Re: execution of always blocks
Date: 22 Dec 92 02:11:54 GMT
Organization: CSE Department, UC San Diego

In article <1992Dec18.200153.25828@twisto.eng.hou.compaq.com> ehlers@tiktok.eng.hou.compaq.com (Steve Ehlers) writes:
>Which is fine if you only care about which ONE is last.  If you have 
>three (or more) registers, you'll still have problems.  Using the
>non-blocking assignment operator ( <= ) will give you the behavior you want:
>
> always @(posedge Clk) c <= b;
> always @(posedge Clk) b <= a;

I've always wondered why Verilog, an HDL, had a blocking assignment as
the default to begin with. Early Verilog designs were excessively verbose,
with the creation of non-existant "registers" and wire delay terms to
get around this problem. The recent introduction of the non-blocking
assignemnt seems to me long overdue on the part of the language designers.

With the non-blocking assignemnt, what used to be somewhat tedious is now
a breeze as the model works exactly like I expect the hardware to.

-- 
Michael Lodman	Department of Computer Science Engineering
	University of California, San Diego
jlodman@cs.ucsd.edu		      (619) 455-1500 x2627
From: gotom@hpysoln.tky.hp.com (Masaharu Goto)
Date: Tue, 22 Dec 1992 23:46:10 GMT
Subject: Re: Verilog <--> VHDL translators
Organization: YHP Hachioji IT, Tokyo Japan
Newsgroups: comp.lang.verilog


 I have a couple of corrections to my previous responce.

 The cost of VDOC-454 is not $200k~$300k,  but it is $20k~$30k. I mixed up
when I convert it from yen to $.

 Second. A guy from InterHDL tell me that they have only Verilog to VHDL 
convertor. I believe somebody gave me information that they have the other
way translator, but it may be a misunderstanding.
Newsgroups: comp.lang.verilog
From: george@ole.cdac.com (George Lippincott)
Subject: Re: Verilog <--> VHDL translators
Organization: Cascade Design Automation
Date: Tue, 22 Dec 1992 23:42:51 GMT

gotom@hpysoln.tky.hp.com (Masaharu Goto) writes:



>Commercial availability of the Verilog <-> VHDL translators 

>	Cadence	VDOC-454	Verilog to VHDL translator
>		 Cadence is the originator of the Verilog-HDL and it seems
>		like VDOC-454 has a quite good coverage on Verilog to VHDL
>		translation.  It costs $200k~300k.
>		 It translates User Defined Primitives and architectural
>		description very good.  Now, I am giving my benchmark example 
>		to see how good it translates behavioral Verilog description 
>		to VHDL. I will let you know when their benchmark comes out.
>		 I am not sure if they have VHDL to Verilog translator.

   Does anyone know what this tool does with the "tran" primitive?  I am
having difficulty finding a way to model this in VHDL.

--
George Lippincott
From: gotom@hpysoln.tky.hp.com (Masaharu Goto)
Date: Mon, 21 Dec 1992 18:07:02 GMT
Subject: Re: Verilog <--> VHDL translators
Organization: YHP Hachioji IT, Tokyo Japan
Newsgroups: comp.lang.verilog


 I posted the same question a couple of months ago and got some information.
I am very interested in the same issue. I would appreciate if you would share
me the information you would get too.

 So far, what I get to know are

Commercial availability of the Verilog <-> VHDL translators 

	Cadence	VDOC-454	Verilog to VHDL translator
		 Cadence is the originator of the Verilog-HDL and it seems
		like VDOC-454 has a quite good coverage on Verilog to VHDL
		translation.  It costs $200k~300k.
		 It translates User Defined Primitives and architectural
		description very good.  Now, I am giving my benchmark example 
		to see how good it translates behavioral Verilog description 
		to VHDL. I will let you know when their benchmark comes out.
		 I am not sure if they have VHDL to Verilog translator.

	InterHDL	Verilog <-> VHDL translator
		 A company called InterHDL has Verilog to VHDL and VHDL to 
		Verilog translator. I don't have any further information
		about their products now.

	Synopsys
		 If the Verilog or VHDL description is logic synthesizable
		(means written in Register Transfer Level), Synopsys can do 
		the job too.  It means it can only translate subset of the
		language.


 I didn't get any information about public domain Verilog <-> VHDL translator
so far. I imagine there are no such things because there are very  few
people in this planet who has an access to both Verilog and VHDL based 
simulator at this moment.

 My own observation and comment about the issue is, language definition of 
the Verilog-HDL is closely related to implementation of the Verilog-XL 
simulator. And some of its' features are not essential to describe Hardware
but essential to speed up simulation throughput. On the other hand, VHDL
is more pure for describing Hardware. I think somebody needs to work out
to accumurate those differences to make a good translator.
 I am not sure if this is very realistic but it would be very nice that 
somebody in the world defines subset of those language for portability of 
the HDL description.

Newsgroups: comp.lang.verilog
From: eli@netcom.com (Interpretive Systems)
Subject: Re: New question - lint like verilog checker
Summary: Verilint is available
Organization: Netcom - Online Communication Services (408 241-9760 guest)
Date: Tue, 22 Dec 1992 22:40:57 GMT


InterHDL has a program which does what you just wanted. Verilint is a
lint program (syntax/semantics checker) for Verilog. It is available for
beta sites on PC, HP and Sun workstations. For more info send mail directly to me.

Eli Sternheim
interHDL Design Corp.
1270 Oakmead Pkwy #209
Sunnyvale, CA 94086
(408) 749-8775
FAX (408) 749-8823
eli@netcom.com
From: manley@optilink.COM (Terry Manley)
Newsgroups: comp.lang.verilog
Subject: New question - lint like verilog checker
Date: 22 Dec 92 00:17:07 GMT
Organization: DSC/Optilink Access Products

In using the verilog language I've noticed the language
will allow you to do many things you don't necessarily
want to do.  Like the C language it is very flexible, 
unfortunately unlike C there isn't a program verifier
like lint.  I can think of many things I'd like to be
checked, things that if checked would eliminate some
of the debugging phase. (My recent post on execution
of always blocks is one example, another is missing
event triggers for always blocks, or declared but 
unreferenced reg or wire variables, or ....)

Anybody heard of a tool like this?

dave
manley@optilink.com
From: dsharoni@adobe.com (Dan Sharoni)
Newsgroups: comp.lang.verilog
Subject: Re: Verilog Syntax/Semantics Checker
Keywords: Verilog
Date: 22 Dec 92 17:37:46 GMT
Followup-To: dsharoni@adobe.com
Distribution: comp.lang.verilog
Organization: Adobe Systems Incorporated

------------------------------------------------------------------------------

I am looking for a linter (syntax/semantics checker) for Verilog. Does
anybody knows about a company with such a tool. Please let me know.

------------------------------------------------------------------------------
Xref: sparky comp.lang.scheme:2854 comp.lang.c:19150
From: gjr@zurich.ai.mit.edu (Guillermo J. Rozas)
Newsgroups: comp.lang.scheme,comp.lang.c
Subject: Re: applying or
Date: 3 Jan 93 08:25:03
Organization: M.I.T. Artificial Intelligence Lab.
Reply-To: gjr@zurich.ai.mit.edu
NNTP-Posting-Host: chamartin.ai.mit.edu
In-reply-to: gjr@zurich.ai.mit.edu's message of 2 Jan 93 08:09:47

In article <GJR.93Jan2080947@chamarti.ai.mit.edu> gjr@zurich.ai.mit.edu (Guillermo J. Rozas) writes:

|   The issue here is whether the order of execution of expressions can be
|   changed by the compiler with respect to the one specified by the
|   semantics.  In general compilers are allowed to do this if they can
|   prove that the effect is the same, in other words, that the user can't
|   tell what order things were done in.

I meant to say that the compiler can reorder as long as the user
cannot tell from the behavior of the resulting code that the
expressions were not done in the order that the semantics specifies.

Newsgroups: comp.lang.scheme
From: clu@malihh.hanse.de (Carsten Lutz)
Subject: applying or
Organization: malihh, Hamburg, Germany
Date: Fri, 25 Dec 1992 14:10:29 GMT

Moin !

I tried to write a little procedure which implements an "or"-function but
additionally checks if it's arguments are booleans. My approach was the
following:

 (define (b-or . oplist)
   (if (boollist? oplist)
       (apply or oplist)
       'not-a-bool))
  
Looks simple, but unfortunately 'or' is a syntactic keyword and hence can't 
be passed to apply as a variable. So evaluating the above results in:

;syntactic keyword referenced as variable or
;Abort!

Two questions arise for me:

1. How can I pass a list of arguments to "or" ? apply doesn't work and I don't
   see another way.

2. Which where the criteria for choosing syntactic keywords. E.g. why are
   "or" and "and" syntactic keywords but "+" or "-" are not ?

greetings,
		Carsten


I should mention my version of scheme:

Scheme Microcode Version 11.59
MIT Scheme running under NeXT

Scheme saved on Friday December 13, 1991 at 9:19:31 AM
  Release 7.1.3
  Microcode 11.59
  Runtime 14.104
  Schematik 1.1

-- 
* Carsten Lutz, Rellingen, FRG / clu@malihh.hanse.de ( NeXTmail accepted )  *
*   Voice : +49 4101 512493  Fax: +49 4101 27757  Traily : +49 4101 22306   *
Newsgroups: comp.lang.scheme
From: clu@malihh.hanse.de (Carsten Lutz)
Subject: Re: applying or
Organization: malihh, Hamburg, Germany
Date: Fri, 25 Dec 1992 14:26:53 GMT

In <BztJDI.1J1@malihh.hanse.de>, I write:
>I tried to write a little procedure which implements an "or"-function but
>additionally checks if it's arguments are booleans. My approach was the
>following:
>
> (define (b-or . oplist)
>   (if (boollist? oplist)
>       (apply or oplist)
>       'not-a-bool))
I forgot about two things:

First to give the procedure boollist?, which is pretty trivial:

  (define (boollist? list)
    (cond ((null? list) #t)
          ((boolean? (car list)) (boollist? (cdr list)))
          (else #f)))
        
And second of course I know a way to write my procedure b-or:

(define (b-or . oplist)
  (cond ((null? oplist) #f)
        ((not (boolean? (car oplist))) 'not-a-bool)
        ((eq? (car oplist) #t))
        (else (apply b-or (cdr oplist)))))

I'm only interested in this apply/syntactic keyword-problem 'cause it
doesn't make sense to me that I can't apply an or.

greetings,
		Carsten


-- 
* Carsten Lutz, Rellingen, FRG / clu@malihh.hanse.de ( NeXTmail accepted )  *
*   Voice : +49 4101 512493  Fax: +49 4101 27757  Traily : +49 4101 22306   *
Newsgroups: comp.lang.scheme
From: schwartz@roke.cs.psu.edu (Scott Schwartz)
Subject: scheme niches (Was: Are interpreters now as fast as compiled code used to be?)
	<JAFFER.92Dec23012204@camelot.ai.mit.edu>
	<JAFFER.92Dec23115358@camelot.ai.mit.edu>
	<1992Dec23.233727.24184@cs.brown.edu>
Date: Thu, 24 Dec 1992 04:46:56 GMT

mj@cs.brown.edu (Mark Johnson) writes:
   [Niches for scheme.] Any comments?

Here's another, somewhat hypothetical one: Shell scripts and
lightweight systems programming.  

Currently people wind up writing large programs in languages that are
basically not up to the task.  You've all seen those multi-thousand
line csh scripts, awk scripts, perl scripts, rexx scripts, tcl
scripts, etc, that run too slowly, can't represent the data structures
they really need, and have unknown semantics.  With a few hooks to
libc and a regexp library scheme can probably do much better.

There are a few ways in which scheme will have problems, though.  In
the application domain I'm thinking of, you really need a decent IO
library, a package system for namespace control, and some way to deal
with "separate compilation."  (Autoloading seems like the way to do the
latter in the world of interpreters, so it would be nice if load did
the right thing with respect to environments.)

The local systems type people I've mentioned this idea to have been
mostly in favor, but quality of implementation is more than an
academic issue for them.  An example of the kind of engineering that
is required came up in a discussion with Aubrey Jaffer about
augmenting scm.  I had provided hooks for Unix system calls: read,
write, open, close, etc.  He wanted me to augment ports with whatever
functionality I wanted instead.  But the functionality I wanted was to
not have to deal with ports at all.  Ports have lots of semantics
associated with them, and I wanted unadulterated access to the
operating system.  Even in C, standard io gets in the way sometimes,
and ports in scheme are not even as capable as stdio is.
From: jaffer@zurich.ai.mit.edu (Aubrey Jaffer)
Newsgroups: comp.lang.scheme
Subject: jacal1a0 computer algebra system available
Date: 24 Dec 92 01:50:22
Organization: M.I.T. Artificial Intelligence Lab.
NNTP-Posting-Host: camelot.ai.mit.edu

This message announces the availability of JACAL release jacal1a0.
See sci.math.symbolic for future announcements about JACAL.

JACAL is a symbolic mathematics system for the simplification and
manipulation of equations and single and multiple valued algebraic
expressions constructed of numbers, variables, radicals, and algebraic
functions, differential, and holonomic functions.  In addition,
vectors and matrices of the above objects are included.

JACAL is written in Scheme.  A version of Scheme (IEEE P1178 and R4RS
compliant) written in C is available with JACAL.  SCM runs on Amiga,
Atari-ST, MacOS, MS-DOS, OS/2, NOS/VE, VMS, Unix and similar systems.

JACAL source is available via FTP (detailed instructions follow) from:
altdorf.ai.mit.edu:archive/scm/jacal1a0.tar.Z (or later revision).

SLIB is a portable scheme library which JACAL requires:
altdorf.ai.mit.edu:archive/scm/slib1c3.tar.Z

SCM is a small Scheme implementation under which JACAL will run.
altdorf.ai.mit.edu:archive/scm/scm4a15.tar.Z

  ftp altdorf.ai.mit.edu [18.43.0.246] (anonymous)
  bin
  cd archive/scm
  get jacal1a0.tar.Z
  get slib1c3.tar.Z
  get scm4a15.tar.Z

`jacal1a0.tar.Z' is a compressed tar file of the JACAL Scheme code.
`slib1c3.tar.Z' is a compressed tar file of a Scheme Library.
`scm4a15.tar.Z' is a compressed tar file of the C code distribution.

Remember to use binary mode when transferring the files.
Be sure to get and read the GNU General Public License (COPYING).
It is included in scm4a15.tar.Z and jacal1a0.tar.Z.
From: adrian@romulus.rutgers.edu (Adrian Rodriguez)
Newsgroups: comp.lang.scheme
Subject: Re: applying or
Date: 28 Dec 92 04:02:00 GMT
Organization: Rutgers Univ., New Brunswick, N.J.
Cc: adrian

> Another reason is just efficiency.  If you see an expression like

> 	(or (= 2 (+ 1 1)) (prime? 184893479827823480745907830796137))

> you can save a lot of time by noticing that the first clause is true.

oaklisp> (/ 184893479827823480745907830796137 3)
61631159942607826915302610265379

Well, maybe not on *this* particular expression, but generally, yes.


Regards,

adrian
From: ark@alice.att.com (Andrew Koenig)
Newsgroups: comp.lang.scheme
Subject: Re: applying or
Date: 30 Dec 92 18:38:15 GMT
Article-I.D.: alice.24517
Reply-To: ark@alice.UUCP ()
Organization: AT&T Bell Laboratories, Murray Hill NJ

In article <1hsiocINN2v6@columbia.cs.ubc.ca> manis@cs.ubc.ca (Vincent Manis) writes:

> People insist on thinking of `and' as a procedure, no doubt because many
> computers have an AND instruction. `and' is a control operation, just as
> are `if' and `cond'. 

Of course, in lazy languages, there's no difference.
So perhaps people who can't tell them apart are guilty of lazy thinking?
-- 
				--Andrew Koenig
				  ark@europa.att.com
Newsgroups: comp.lang.scheme
From: ward@math.psu.edu (Brian Ward)
Subject: Re: applying or
Organization: The Bill and Ted Society of Computer Science
Date: Fri, 25 Dec 1992 19:34:41 GMT

clu@malihh.hanse.de (Carsten Lutz) writes:
|1. How can I pass a list of arguments to "or" ? apply doesn't work and I don't
|   see another way.

I had this problem once. (define a-or
				 (lambda x (cond
					    ((null? x) ())
					    ((or (car x)) #t)
					    (#t (apply a-or (cdr x))))))
worked ok for what I had to do with it, at least, but that's from memory
and I didn't test the above, so I don't know it it's right or not.
(a-or = applyable-or) seems slow, though.

-brian

Newsgroups: comp.lang.scheme