Page type: faculty

Guri Sohi's Home Page; Gurindar S. Sohi (sohi@cs.wisc.edu);Associate Professor of;Computer Sciences and;Electrical and Computer Engineering; Addresses; Education; Research Interests and Summary; Current Graduate Students; Recent Talks; Recent Publications; Recent Ph.D Graduates;Addresses:;Department of Computer Sciences;University of Wisconsin - Madison;1210 West Dayton Street;Madison, WI 53706 USA;sohi@cs.wisc.edu;Phone: 608-262-7985;Departmental Office: 608-262-1204;Fax: 608-262-9777;Education:; Ph.D. (Computer Science) University of Illinois - Urbana, 1985; M.S. (Electical Engineering) University of Illinois - Urbana, 1983; B.E. (Electrical and Electronics Engineering) Birla Institute of Technology and Science - Pilani, India, 1981;Research Interests:; Instruction-level parallel (ILP) processing; Compiling for ILP architectures; Shared memory multiprocessors; Memory Systems; Research Summary;My current research focuses on the design of the;highest performance uniprocessors of a current generation.;Currently we are investigating the architecture of;a circa 2000 processor. With plenty of transistors available;on a chip, the challenge is to use these resources to get;the highest possible performance when executing a sequential program.;A target that we have set for ourselves is to sustain the execution of;over 10 instructions per cycle,;for ordinary non-numeric application programs.;My research group is investigating several issues that need;to be resolved before our goals can be achieved.;We are studying and characterizing the;nature of instruction-level parallelism in non-numeric;application programs in order to understand the available parallelism and;how it could be exploited.;The bulk of my group's research effort is expended in continuing the;development of the; Multiscalar processing model,;a novel paradigm for exploiting ILP.;Currently we are developing the Multiscalar compiler, and;carrying out detailed simulation studies to assess;the potential of the Multiscalar concept.;Current Graduate Students; Todd Austin; Scott Breach; Andreas Moshovos; T.N. Vijaykumar;Recent Talks;Will Instruction Sets be Important in Future Processors?;given at the RISC in 1995 Symposium held at IBM T. J. Watson Research;Center, Yorktown Heights, NY, November 7-8, 1995.;File is compressed postscript, generated by Framemaker.;Multiscalar Processors.;The generic Multiscalar talk, given at several places.;File is compressed postscript, generated by Framemaker.;Recent Publications;High-Bandwidth Address Translation for Multiple-Issue Processors,;T. M. Austin and G. S. Sohi, to appear in;23rd Annual International Symposium on Computer Architecture, May 1996.;An appendix of;detailed results;is also available.);Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency;T. M. Austin and G. S. Sohi,;28th Annual International Symposium on Microarchitecture (MICRO-28), 1995.;The Microarchitecture of Superscalar Processors;J. E. Smith and G. S. Sohi,;in Proceedings of the IEEE, December 1995.;A Hardware Mechanism for Dynamic Reordering of Memory References;M. Franklin and G. S. Sohi,;to appear in IEEE Transactions on Computers.;Multiscalar Processors,;G. S. Sohi, S. Breach, and T. N. Vijaykumar,;22th International Symposium on Computer Architecture, 1995.;Streamlining Data Cache Access with Fast Address Calculation,;T. M. Austin, D. N. Pnevmatikatos, and G. S. Sohi,;22th International Symposium on Computer Architecture, 1995.;The Anatomy of the Register File in a Multiscalar Processor,;S. Breach, T. N. Vijaykumar, and G. S. Sohi,;27th Annual International Symposium on Microarchitecture (MICRO-27), 1994.;Request Combining in Multiprocessors with Arbitrary Interconnection Networks,;A. Lebeck and G. S. Sohi,;in IEEE Transactions on Parallel and Distributed Systems, 1994.;Efficient Detection of All Pointer and Array Access Errors,;T. M. Austin, S. E. Breach and G. S. Sohi,;SIGPLAN '94 Conference on Programming Language Design and Implementation, 1994.;Guarded Execution and Branch Prediction in Dynamic ILP Processors,;D. Pnevmatikatos and G. S. Sohi, 21th International Symposium on Computer Architecture, 1994.;Memory Systems,;J. R. Goodman and G. S. Sohi, The Handbook of Electrical Engineering, CRC Press, 1993.;Control Flow Prediction for Dynamic ILP Processors,;D. Pnevmatikatos, M. Franklin and G. S. Sohi,;26th Annual International Symposium on Microarchitecture (MICRO-26), 1993.;Register Traffic Analysis for Streamlining Inter-operation Communication;in Fine-Grain Parallel Processors,;M. Franklin and G. S. Sohi, 25th Annual International Symposium on Microarchitecture;(MICRO-25), 1992.;The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism,;M. Franklin and G. S. Sohi, 19th International Symposium on Computer Architecture, 1992.;Dynamic Dependency Analysis of Ordinary Programs,;T.M. Austin and G. S. Sohi, 19th International Symposium on Computer Architecture, 1992.;Efficient Detection of All Pointer and Array Access Errors;T.M. Austin, S. E. Breach and G. S. Sohi,;Technical Report #1197, Computer Sciences Department, University of Wisconsin-Madison, December 1993.;Guarded Execution and Branch Prediction in Dynamic ILP Processors;D. N. Pnevmatikatos and G. S. Sohi,;Technical Report #1193, Computer Sciences Department, University of Wisconsin-Madison, November 1993.;Knapsack: A Zero-Cycle Memory Hierarchy Component;T. M. Austin, T. N. Vijaykumar, and G. S. Sohi,;Technical Report #1189, Computer Sciences Department, University of Wisconsin-Madison, November 1993.;Tetra: Evaluation of Serial Program Performance on Fine-Grain Parallel Processors;T. M. Austin and G. S. Sohi,;Technical Report #1162, Computer Sciences Department, University of Wisconsin-Madison, July 1993.;Recent Ph.D Grads;Todd Austin,;Ph.D., April 1996,;Hardware and Software Mechanisms for Reducing Load Latency;Dionisios Pnevmatikatos,;Ph.D., December 1995,;Incorporating Guarded Execution into Existing Instruction Sets;Manoj Franklin,;Ph.D., December 1993,;The Multiscalar Architecture;Mark Friedman,;Ph.D., January 1992,;An Architectural Characterization of Prolog Execution;Sriram Vajapeyam,;Ph.D., December 1991,;Instruction Level Characterization of the Cray Y-MP Processor;Men-Chow Chiang,;Ph.D., September 1991,;Memory System Design for Bus Based Multiprocessors; Last Updated: 5 April 1996;