Graph-COM/Text-Attributed-Graphs huggingface dataset:
Page type: project

UW Cecil/Vortex Project;UW Cecil/Vortex Project;Welcome to the home page for the Cecil and Vortex projects at UW CSE. We conduct research on programming language design and implementation, with an emphasis on these issues for object-oriented languages.;Cecil is a purely object-oriented language intended to support rapid;construction of high-quality, extensible software. Cecil incorporates;multi-methods, a simple prototype-based object model, a mechanism to;support a structured form of computed inheritance, module-based;encapsulation, and a flexible static type system which allows;statically- and dynamically-typed code to mix freely.;Vortex is an optimizing compiler infrastructure for;object-oriented and other high-level languages. It targets both pure;object-oriented languages like Cecil and hybrid object-oriented;languages like C++, Modula-3, and Java. Vortex currently incorporates;high-level optimizations such as static class analysis, class hierachy;analysis, profile-guided receiver class prediction, profile-guided;selective procedure specialization, intraprocedural message splitting,;automatic inlining, and static closure analyses. It also includes a;collection of standard intraprocedural analyses such as common;subexpression elimination and dead assignment elimination. The Vortex;compiler is written entirely in Cecil.;An initial beta release of the Cecil/Vortex system is currently;available for SPARCs running either SunOS 4 or SunOS 5 (Solaris).;Send mail to cecil-interest-request with a message body of subscribe if you'd like to subscribe to a list of;interested parties and get more information on how to obtain the;Beta release.;We've recently finished a technical report that describes much of our implementation research.;More Information; Project Overview; A more detailed overview of the project's goals and direction. A postscript version is also available.; Project members; Current and past project members; Papers; Papers we've written; Sample Projects; A list of some sample research projects (available to people from UW;CSE); Internal Documentation; Project internal documentation (available to people from UW CSE); Support; This page lists some of the sources of support for our project; Some related projects; Pointers to a few other object-oriented language implementation projects;Last updated August 25, 1996.;cecil@cs.washington.edu;
Page type: project

GRAIL: Graphics and Imaging Laboratory;Welcome to the home page of GRAIL, the Graphics and Imaging Laboratory of the;University of Washington's Department of Computer Science and Engineering.;Information;People;Courses;Research Projects;Publications;Theses;Software and Data;Cool Images; Our Neighborhood; ; Department of Computer Science; and Engineering; University of Washington; Seattle;Local Interest;GRAIL disk usage policy; ;Comments to; mtwong@cs.washington.edu;23 July 1996;
Page type: project

The Chaotic Routing Project;; The Chaotic Routing Project;Computer Science & Engineering Department;University of Washington,; Box 352350;Seattle, WA 98195-2350 USA;; Chaos is a friend of mine.; -Bob Dylan;; Chaotic People;All sorts of people work on the Chaotic Routing project.; Research Papers and Technical Reports;A repository of all of the research papers;and technical reports of the Chaotic;Routing project is available.; Chaos Router Chip;The;Chaos Router Chip is an implementation of the chaos routing algorithm in hardware. It;has been built and tested in 1.2 micron CMOS, and redesigned in a 0.8 micron process for;better performance.; Simulator;The;Chaos Router Simulator is a powerful simulator which can simulate all;sorts of networks and routing algorithms. It includes a very nice graphical;front end!; Standards for Presentation of Results;At PCRCW '94, we discussed the presentation;of simulation results for routing algorithms. We were able to come up;with some guidelines; for presentation of results.; Other Research Groups;We're building a list of all research groups that;have webs describing research in routing and/or interconnection networks.; Parallel Computer Routing and Communication Workshop (PCRCW) '94;PCRCW '94 was held at the Univeristy of Washington in Seattle in May;1994. Proceedings are available now.;The University of Washington CSE home Page;kwb@cs.washington.edu;
Page type: project

Emerald; The Emerald Project;Ideally, the development phase of a new FPGA architecture would make;use of a reliable set of mapping tools to produce accurate performance;evaluations of proposed designs. Unfortunately, given the quick;production time frames faced by most developers, tool construction is;often postponed until after many architectural features have been;frozen. To satisfy the need for fast tool prototyping, we have;designed Emerald, a powerful architecture-driven system for quick;development of FPGA tools. At its heart Emerald provides the basic;features needed in all FPGA systems -- logic block analysis, synthesis;and technology mapping, global placement and partitioning, and;detailed placement and routing. Its CAD environment provides an;efficient way to thoroughly specify an FPGA's routing and logic block;architectures, as well as architecture-specific metrics to tailor;placement and routing. Moreover, Emerald's parameterized schematic;specifications allow architectural variations to be quickly captured;and evaluated.;Emerald Publications; Any documents contained in this page are included by;the contributing authors as a means to ensure timely dissemination of;scholarly and technical work on a non-commercial basis. Copyright and;all rights therein are maintained by the authors or by other copyright;holders, notwithstanding that they have offered their works here;electronically. It is understood that all persons copying this;information will adhere to the terms and constraints invoked by each;author's copyright. These works may not be reposted without the;explicit permission of the copyright holder.;The Definitive Emerald Paper; Darren C. Cronquist and Larry McMurchie.;"Emerald - An Architecture-Driven Tool Compiler for FPGAs",;To appear in Proceedings of the 1996 ACM/SIGDA Fourth International;Symposium on Field-Programmable Gate Arrays , February 1996.;The Router used in Emerald;Larry McMurchie and Carl Ebeling,;"PathFinder: A Negotiation-Based;Performance-Driven Router for FPGAs",;Proceedings of the 1995 ACM; Third International Symposium on Field-Programmable Gate Arrays;Aided Design , pp. 111-117, February 1995.;Researchers; Darren Cronquist; Carl Ebeling; Larry McMurchie;
Page type: project

Northwest Laboratory for Integrated Systems;; Northwest Laboratory for Integrated Systems;; Department of Computer Science & Engineering;University of Washington,; Box 352350;Seattle, WA 98195-2350 USA;The Department of Computer Science and Engineering at the University of;Washington has been engaged in Very Large Scale Integration (VLSI) and;Computer-Aided Design (CAD) research, development, and education since;the late 1970s. Today, the Northwest Laboratory for Integrated Systems;is the focus of a wide variety of VLSI architectures, embedded sytems,;and CAD research.;Current Research Projects;Asynchronous Circuits and Verification;Time Separation of Events:; Specification, synthesis, and verification of timed asynchronous; circuits.; Asynchronous Circuits:; Survey of current asynchronous design methodologies, as; well as the first FPGA for asynchronous circuits.;FPGAs and Rapid-Prototyping;Triptych/Montage FPGA Architectures:; Development of the Triptych and Montage FPGA; architectures, architectures with improved densities over current; commercial FPGAs.;Multi-FPGA Systems & Rapid-Prototyping:; Development of the Springbok Rapid-Prototyping System for; Board-Level Designs, as well as partitioning, pin assignment,; and routing topology work for general multi-FPGA systems.;Emerald - An Architecture-Adaptive Toolset for FPGAs:; A complete set of mapping, placement and routing tools;can be generated automatically from a description of an FPGA;architecture. Architecture-specific metrics can be incorporated;into the various tools to improve the results.;Embedded Systems;The Chinook Project:; A Hardware/Software Co-design, Co-synthesis, and Co-simulation; system for embedded applications.;Performance Optimization of Synchronous Circuits;Retiming Level-Clocked Circuits:; Efficient algorithms for retiming circuits that use;level-sensitive latches to improve performance, reduce cost, and;increase tolerance to clock skew.;Architectural Retiming:; Methods for improving the performance of synchronous;circuits that have latency or feedback contraints.;Network Router;The Chaotic;Routing Project;Self-Tuned Systems;Self-tuned systems are directed by Ted Kehl;Previous Research Projects;; Gemini; Validating layout by comparing the specification circuit to the; implemented circuit.;;MacTester; A low-cost digital functional tester for chips and circuits; with TTL or CMOS voltage levels.;
Page type: project

Software Safety at the University of Washington; Software is playing an increasingly important role in systems such; as nuclear reactors, aircraft, defence and space systems, chemical; plants, and medical equipment. Because of the consequences of a; malfunction, these safety-critical systems must pass rigorous tests; and reviews before they may be used. Although system safety engineering; techniques have existed for decades, most do not apply to systems that; contain digital computers and software.; The goal of the University of Washington Safety Project is to develop; a theoretical foundation for safety and a methodology for building; safety-critical systems built upon that foundation.; In Safeware: System Safety and; Computers, Nancy Leveson summarizes the issues involved and; lays the foundation for the methodology. We are now working on safety; analysis techniques to support the methodology and a set of; prototype tools to be used to validate the specification and analysis; techniques.;University of Washington |; UW Computer Science;UW Software Engineering |; Other Safety Links;
Page type: project

The Internet Softbot;Internet Softbot;The Softbot was one of the 5;finalists in the 1995 Discover;Awards for Technological Innovation in Computer Software.; Building autonomous agents that interact with real-world software;environments such as operating systems or databases is a pragmatically;convenient yet intellectually challenging substrate for AI research.;To support this claim, we are utilizing planning and machine-learning;techniques to develop an Internet softbot (software robot), a;customizable and (moderately) intelligent assistant for Internet;access. The softbot accepts goals in a high-level language, generates;and executes plans to achieve these goals, and learns from its;experience. The softbot enables a human user to state what;he or she wants accomplished. The softbot disambiguates the request;and dynamically determines how and where to satisfy;it. The softbot uses a UNIX shell and the World-Wide Web to interact;with a wide range of internet resources.; Take a tour of the softbot's;graphical user interface.;Principal Investigators:;Oren Etzioni,;Daniel Weld.; Also, check out the;MetaCrawler Softbot --- a fielded Web service that enables you to;search multiple Web Indices in parallel, and provides sophisticated;pruning options. Try it!; For further information, contact: Oren Etzioni;(etzioni@cs.washington.edu);An accessible introduction to the Softbot project can be found here:; A Softbot-Based Interface to the Internet.; CACM, July 1994.;Methodological motivation for the project can be found here:; Intelligence without Robots (A Reply to Brooks).; AI Magazine, December 1993.;Technical softbot papers can be found;here.;A cartoon;representation of the Internet softbot taken from the L.G.;Blanchard article that appeared in the December 1994 issue of;Columns, the University of Washington alumni magazine.;The softbots research group is currently:;Developing a graphical user interface to;the softbot to allow the user to easily specify high level goals.;Extending and maintaining the XII;planner;(Keith Golden).; Working on graphical specification of search control;(Keith Golden).; Implementing an advanced plan space browser to debug planner control;(Dave Christianson).; Comparing rule-based versus procedural search control (Sujay Parekh); ILA;learns how to use information resources on the net; Designing a protocol for multi-softbot collaboration and negotiation;(Ying Sun).; Experimenting on reactive system in software domain;(C. T. Kwok and T.J. Goan).; Building an optimized agent Ingram for information gathering reactive system on the Internet.;(C. T. Kwok).; The Softbot-hackers info web (local access only);; Back to AI Home Page;; Back to CSE Home Page;Mike Perkowitz (map@cs.washington.edu);
Page type: project

UW Dynamic Compilation Project;The UW Dynamic Compilation Project;More Information; Our Dynamic Compiler; Project Members; Papers; Related Projects;UW-Only Sections; Student Projects; Group Web;Dynamic compilation enables optimizations based on the values of;invariant data computed at run-time. Using the values of these;run-time constants, a dynamic compiler can eliminate their memory;loads, perform constant propagation and folding, remove branches they;determine, and fully unroll loops they bound. However, the performance;benefits of the more efficient, dynamically-compiled code are offset;by the run-time cost of the dynamic compile. Our approach to dynamic;compilation strives for both fast dynamic compilation and high-quality;dynamically-compiled code: the programmer annotates regions of the;programs that should be compiled dynamically; a static, optimizing;compiler automatically produces pre-optimized machine-code templates,;using a pair of dataflow analyses that identify which variables will;be constant at run-time; and a simple, dynamic compiler copies the;templates, patching in the computed values of the run-time constants,;to produce optimized, executable code. Our work targets general-;purpose, imperative programming languages, initially C. Initial;experiments applying dynamic compilation to C programs have produced;speedups ranging from 1.2 to 1.8.;We are part of the SPIN;project. Eventually, our system will be used to dynamically;compile code in the SPIN kernel, for example the SPIN;event dispatcher. However, we are also actively exploring other;possible applications of dynamic compilation, such as in;virtual-machine interpreters.;Our prototype dynamic-compilation system;is described in our PLDI paper. We are;now starting to design and build our second-generation system. We;will release more details on it soon.;Last updated August 6, 1996.;grant@cs.washington.edu;
Page type: project

The ZPL Project;;;The ZPL Project; Department of Computer Science &;Engineering; University of;Washington; Box 352350; Seattle,;WA; 98195-2350 USA; zpl-info@cs.washington.edu;ZPL is a new array-based programming language suitable for most;computations that would previously have been written in Fortran 77:; ZPL programs run fast on sequential AND parallel computers,; without modifications, and without special directives.; ZPL is machine-independent, so recompilation is all that is; necessary to run a ZPL program on a new machine.; ZPL's higher level concepts like arrays, borders, etc. eliminate most; of the error-prone indexing and tedious looping typical of F77, C,; etc.; ZPL programs are shorter, more easily written, and more easily; understood and modified.; Computer scientists will find new concepts in ZPL: regions,; directions, borders, shattered control-flow, etc.;Conclusion: ZPL is ideal for new engineering and scientific programs.;Walk-through a small ZPL program, or write-compile-run a program from your;machine!;Scientific programmers in the area should;consider enrolling in CSE 590ZP;this autumn.;If you have programmed in ZPL before, check out the recent changes in the language.; Project Overview; A high-level overview of ZPL.; Program Walk-Through; A 10 minute introduction to the language.; Web-based ZPL Compiler; Compile ZPL programs via your web browser right now!; Papers; Papers and manuals about or related to ZPL.; ZPL Details; On-line information and sample programs.; People; Project members.; On the Horizon; A description of the group's direction and future projects.; Acknowledgments; A list of those who have helped support our work.;;[;ZPL |;UW CSE |;UW;];zpl-info@cs.washington.edu;
Page type: project

Simultaneous Multithreading home page;Simultaneous Multithreading Project;Overview;People;Publications; Overview;The crucial problem facing today's high-speed microprocessors is maintaining;high processor utilization in the face of long instruction and memory;latencies. To;alleviate this problem, modern processors issue multiple instructions per;cycle (i.e., superscalars), or interleave the execution of different;threads in different cycles (multithreaded processors). Ultimately, though,;both techniques are limited by the amount of parallelism available within a;single thread in a single cycle.; Simultaneous multithreading (SMT) is a technique that permits multiple;independent threads to issue instructions to a superscalar's functional;units in a single cycle. SMT combines the multiple-instruction-issue;features of wide superscalar processors with the latency-hiding ability;of multithreaded architectures. On an SMT processor, all hardware contexts;are active simultaneously, competing each cycle for all available resources.;This dynamic sharing of processor resources enables SMT to exploit;thread-level and instruction-level parallelism interchangeably; both forms;of parallelism can be effectively used to increase processor utilization.;Our studies have;demonstrated that simultaneous multithreading significantly improves;processor throughput and performance on both multiprogrammed and parallel;workloads. We have shown that these performance gains can be achieved;in an architecture with only minimal extensions to modern out-of-order;superscalar processors.;Our current and future work includes investigations of fast synchronization;techniques enabled by SMT. We are also conducting research in other;architectural and compiler issues for simultaneous multithreading.; People;Faculty; Susan Eggers; Hank Levy;Graduate students; Jack Lo; Dean Tullsen;Industrial collaborators (Digital Equipment Corporation); Joel S. Emer; Rebecca L. Stamm; Publications; Converting Thread-Level Parallelism Into Instruction-Level Parallelism via Simultaneous Multithreading (Abstract, Postscript);J.L. Lo,;S.J. Eggers,;J.S. Emer,;H.M. Levy,;R.L. Stamm, and;D.M. Tullsen;Submitted for publication, July 1996.; Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor (Abstract, Postscript);D.M. Tullsen,;S.J. Eggers,;J.S. Emer,;H.M. Levy,;J.L. Lo,;and R.L. Stamm;;Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, May 1996.; Compilation Issues for a Simultaneous Multithreading Processor;(Postscript);J.L. Lo,;S.J. Eggers,;H.M. Levy, and;D.M. Tullsen;Proceedings of the First SUIF Compiler Workshop, Stanford, CA, January 1996, p. 146-7.; Simultaneous Multithreading: Maximizing On-Chip Parallelism (Abstract, Postscript);D.M. Tullsen,;S.J. Eggers, and;H.M. Levy,; Proceedings of the 22rd Annual International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, June 1995.; UW students:;Check the list of research projects still to do;on the student-affairs page.;This page maintained by Jack Lo;jlo@cs.washington.edu;