Page type: project

Memory Systems Research at the University of Washington;Memory Systems Research;Department of Computer Science & Engineering;University of Washington, FR-35;Seattle, WA 98195;Welcome to the home page for Memory Systems Research at UW CSE.;Description;Our research group is investigating techniques that use the operating;system to improve memory system performance. All of our work shares;the following features:; We rely a combination of simple hardware support and operating; system modifications to monitor the dynamic behavior of applications.; These monitoring mechanisms incur a small overhead at runtime, but the; information they collect can be used to identify sources of memory; system delays such as cache misses and TLB misses.; By identifying and resolving these bottlenecks, we not only pay for; the overhead of the monitoring mechanisms, but also significantly; improve overall system performance.;In our most recent project, we explored policies that monitor;application memory reference patterns in order to identify and resolve;TLB performance problems. Poor TLB performance results when the TLB;is too small to cover the current application's working set. Several;modern architectures support superpages: pages whose size is a;multiple of the system's base page size. On such systems TLB;performance can be improved by using larger pages, but at the cost of;wasted memory due to internal fragmentation.;We simulated several policies that adapt the page size dynamically to;different regions of an application's address space, constructing;superpages by copying the component pages to a contiguous region of;memory. We developed a policy that monitors TLB misses, and balances;the potential benefit of having a superpage (a reduction in future TLB;misses) against the cost of constructing the superpage (an in-memory;copy). By constructing superpages only when and where TLB miss;patterns warrant, this policy attains the TLB performance of large;pages without their internal fragmentation.;For more details on this project, see our paper; Reducing TLB and Memory Overhead Using Online Superpage Promotion; (ISCA '95, to appear).;We're looking for someone to implement these algorithms -- this would make;a good quals or masters project.;Project Description.;People;Faculty:; Brian Bershad (bershad@cs.washington.edu); Anna Karlin (karlin@cs.washington.edu);Current Students:; Dennis Lee (dlee@cs.washington.edu); Wayne Ohlrich (ohlrich@cs.washington.edu); Ted Romer (romer@cs.washington.edu); Wayne Wong (waynew@cs.washington.edu);Papers; Reducing TLB and Memory Overhead Using Online Superpage Promotion .; Romer, Ohlrich, Karlin, and Bershad. ISCA '95, to appear.; Dynamic Page Mapping Policies for Cache Conflict Resolution on; Standard Hardware .; Romer, Lee, Bershad, and Chen. OSDI , pp. 255-266.; Avoiding Conflict Misses Dynamically in Large Direct-Mapped Caches .; Bershad, Lee, Romer, and Chen. ASPLOS VI, pp. 158-170.; A Comparison of the Memory Performance of the MIPS R3000 and DEC; Alpha 21064. Wong. Ph. D. Quals Project Report, University of; Washington.; Instruction Cache Effects of Different Code Reordering Algorithms.; Lee. Ph. D. Quals Project Report, University of Washington.; Memory Systems Bibliography;Ted Romer (romer@cs.washington.edu);