Reference number : GC-2017-Q4-01583, amendment number : , agreement type : G, recipient legal name : Sachdev, Manoj (University of Waterloo), recipient country : CA, recipient province : nan, recipient city : Ontario, recipient postal code : nan, program name english : DND/NSERC Discovery Grant Supplement, program name french : Supplément aux subventions à la découverte MDN-CRSNG, program purpose english : Impact of transistor scaling are evident everywhere. Often small as possible transistors are used to reduce the power, energy consumption, and to increase the packing density. Transistors with smaller dimensions exhibit a higher susceptibility to process variation. As a result, realization of robust, reliable circuit design becomes a challenge. In particular, SRAM circuits, and low-power, low-voltage digital circuits show higher degree of variation owing to smallest possible transistor dimensions, and low-supply voltage requirements. In this research, we will investigate variability-aware design of digital and SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) &ndash; power, energy, yield, quality, and reliability are influenced by SRAMs. This research proposal has two major components &ndash; (i) SRAMs, and (ii) Logic circuits. Key research objectives for the SRAM are: (a) lower SRAM power consumption with architectural, circuit innovation to realize a reliable, ultra-low-voltage SRAMs. In particular, devise circuit techniques to alleviate the impact of process variations on important SRAM blocks such as sense amplifiers, SRAM cells, and (b) mitigate the impact of soft errors and weak failures through hardened by design and efficient implementation Error Correcting Codes (ECC) which may further improve low-voltage SRAM operation. The key research objective for logic circuits is ultra-low-voltage, energy efficient logic family and to realize ultra-low-voltage digital building blocks. The long term (5 years) objective of this research is to put all these ideas together in silicon to (a) fabricate fully functional ultra-low-voltage; low-power SRAMs in 28 nm CMOS technology; (b) design and fabricate soft error robust low-power SRAMs; (c) design and fabricate a low-power, low-voltage digital circuits such as 32/64b adder capable of working at 100 mV. In all instances, test chips will be manufactured, and measurements will be carried out., program purpose french : Impact of transistor scaling are evident everywhere. Often small as possible transistors are used to reduce the power, energy consumption, and to increase the packing density. Transistors with smaller dimensions exhibit a higher susceptibility to process variation. As a result, realization of robust, reliable circuit design becomes a challenge. In particular, SRAM circuits, and low-power, low-voltage digital circuits show higher degree of variation owing to smallest possible transistor dimensions, and low-supply voltage requirements. In this research, we will investigate variability-aware design of digital and SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) &ndash; power, energy, yield, quality, and reliability are influenced by SRAMs. This research proposal has two major components &ndash; (i) SRAMs, and (ii) Logic circuits. Key research objectives for the SRAM are: (a) lower SRAM power consumption with architectural, circuit innovation to realize a reliable, ultra-low-voltage SRAMs. In particular, devise circuit techniques to alleviate the impact of process variations on important SRAM blocks such as sense amplifiers, SRAM cells, and (b) mitigate the impact of soft errors and weak failures through hardened by design and efficient implementation Error Correcting Codes (ECC) which may further improve low-voltage SRAM operation. The key research objective for logic circuits is ultra-low-voltage, energy efficient logic family and to realize ultra-low-voltage digital building blocks. The long term (5 years) objective of this research is to put all these ideas together in silicon to (a) fabricate fully functional ultra-low-voltage; low-power SRAMs in 28 nm CMOS technology; (b) design and fabricate soft error robust low-power SRAMs; (c) design and fabricate a low-power, low-voltage digital circuits such as 32/64b adder capable of working at 100 mV. In all instances, test chips will be manufactured, and measurements will be carried out., agreement title english : Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware, agreement title french : Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware, agreement number : DGDND, agreement value : 120000.0, agreement start date : 2018-01-10, agreement end date : nan, description english : nan, description french : nan, expected results english : nan, expected results french : nan, additional information english : Grant or Award spanning more than one fiscal year (2017-2018 to 2020-2021)., additional information french : Subvention ou bourse octroyée s'appliquant à plus d'un exercice financier (2017-2018 à 2020-2021)., owner organization : nserc-crsng, owner organization title : Natural Sciences and Engineering Research Council of Canada | Conseil de recherches en sciences naturelles et en génie du Canada