Reference number : GC-2017-Q3-00398, amendment number : , agreement type : G, recipient legal name : Plett, Calvin (Carleton University), recipient country : CA, recipient province : nan, recipient city : Ontario, recipient postal code : nan, program name english : Collaborative Research and Development Grants - Project, program name french : Subventions de recherche et développement coopérative - projet, program purpose english : This research project involves the exploration of advanced frequency synthesis techniques, while also considering applications in timing recovery circuits for broadband data communications systems. The trend recently has been to move away from analog and towards all digital phase-locked loops (ADPLLs), due to their small area, better immunity to external noise, simplicity of design, and scalability with process technology. The main challenge to be addressed in this proposal is the improvement in phase noise of the ADPLL. Noise performance of the ADPLL is determined by phase granularity and resolution, determined by the loop characteristics, non-linearity in the loop, and non-idealities of the loop components such as the phase detector and the oscillator. At the system level, studies will be undertaken to ensure that requirement of frequency bands and lock range, noise, settling time, phase resolution and power consumption are met and will fit in with the objectives of the industrial collaborators. In addition to noise, unwanted signals (spurs) which are often the result of nonlinearity and mismatch will have to be minimized to reduce interference with desired signals. At the component level, each sub-block circuit will be designed to reduce non-idealities such as noise and nonlinearity. The research will build on previous work done both at the system level and at the component level. Continuing to work closely with our industrial partner will ensure that our design is practical and will fit in with their larger scale project. Having an improved ADPLL with applications to both frequency synthesizers and clock and data recovery circuits in their portfolio will strengthen their position as a world leader in this field. This is expected to have an impact on their portion of the global market share in this area, and by the successful introduction of related products, will potentially lead to more employment opportunities in Canada. Through publication of the technological advancements in this project, knowledge will be distributed throughout the academic community leading to international recognition for Carleton University and for the researchers involved, advancing the state-of-the-art of the design techniques used in this field._x000D_, program purpose french : This research project involves the exploration of advanced frequency synthesis techniques, while also considering applications in timing recovery circuits for broadband data communications systems. The trend recently has been to move away from analog and towards all digital phase-locked loops (ADPLLs), due to their small area, better immunity to external noise, simplicity of design, and scalability with process technology. The main challenge to be addressed in this proposal is the improvement in phase noise of the ADPLL. Noise performance of the ADPLL is determined by phase granularity and resolution, determined by the loop characteristics, non-linearity in the loop, and non-idealities of the loop components such as the phase detector and the oscillator. At the system level, studies will be undertaken to ensure that requirement of frequency bands and lock range, noise, settling time, phase resolution and power consumption are met and will fit in with the objectives of the industrial collaborators. In addition to noise, unwanted signals (spurs) which are often the result of nonlinearity and mismatch will have to be minimized to reduce interference with desired signals. At the component level, each sub-block circuit will be designed to reduce non-idealities such as noise and nonlinearity. The research will build on previous work done both at the system level and at the component level. Continuing to work closely with our industrial partner will ensure that our design is practical and will fit in with their larger scale project. Having an improved ADPLL with applications to both frequency synthesizers and clock and data recovery circuits in their portfolio will strengthen their position as a world leader in this field. This is expected to have an impact on their portion of the global market share in this area, and by the successful introduction of related products, will potentially lead to more employment opportunities in Canada. Through publication of the technological advancements in this project, knowledge will be distributed throughout the academic community leading to international recognition for Carleton University and for the researchers involved, advancing the state-of-the-art of the design techniques used in this field._x000D_, agreement title english : Advanced frequency synthesizer design, agreement title french : Advanced frequency synthesizer design, agreement number : CRDPJ, agreement value : 93750.0, agreement start date : 2017-11-08, agreement end date : nan, description english : nan, description french : nan, expected results english : nan, expected results french : nan, additional information english : Grant or Award spanning more than one fiscal year (2017-2018 to 2020-2021)., additional information french : Subvention ou bourse octroyée s'appliquant à plus d'un exercice financier (2017-2018 à 2020-2021)., owner organization : nserc-crsng, owner organization title : Natural Sciences and Engineering Research Council of Canada | Conseil de recherches en sciences naturelles et en génie du Canada