Reference number : GC-2017-Q2-04326, amendment number : , agreement type : G, recipient legal name : Areibi, Shawki (University of Guelph), recipient country : CA, recipient province : nan, recipient city : Ontario, recipient postal code : nan, program name english : Engage Grants for Universities, program name french : Subventions d'engagement partenarial pour les universités, program purpose english : In recent times the ability to securely store and transfer critical data and sensitive information has proved a_x000D_
critical factor in success of business. In this age of universal electronic connectivity, of hackers, Trojans,_x000D_
viruses and electronic fraud, there is an important need for security and encryption._x000D_
The most widely used symmetric encryption algorithms are 3DES, RC4, Twofish and AES._x000D_
Examples of algorithms used in Asymmetric encryption are RSA, XTR and Diffie-Hellman._x000D_
All the above mentioned algorithms can be implemented in either software or hardware. Hardware acceleration_x000D_
is the use of hardware to perform a task more efficiently than is possible in software. In order to achieve higher_x000D_
performance in today's heavily loaded communication networks, utilization of hardware accelerators for_x000D_
cryptography algorithms is more efficient. These hardware accelerators tend to offload the most computing_x000D_
intensive operations of encryption algorithms from the main processor._x000D_
Reconfigurable logic allows the definition of new functions to be defined in hardware units, combining_x000D_
hardware speed and efficiency, with ability to adapt and cope in a cost effective way with expanding_x000D_
functionality, changing environmental requirements, improvements in system features, changing protocols and_x000D_
data-coding standards._x000D_
This proposal will perform architecture exploration to find efficient architectures for encryption algorithms._x000D_
During the exploration phase, several architectures will be generated and evaluated to estimate the conflicting_x000D_
constraints and objectives such as area, performance, power consumption and flexibility., program purpose french : In recent times the ability to securely store and transfer critical data and sensitive information has proved a_x000D_
critical factor in success of business. In this age of universal electronic connectivity, of hackers, Trojans,_x000D_
viruses and electronic fraud, there is an important need for security and encryption._x000D_
The most widely used symmetric encryption algorithms are 3DES, RC4, Twofish and AES._x000D_
Examples of algorithms used in Asymmetric encryption are RSA, XTR and Diffie-Hellman._x000D_
All the above mentioned algorithms can be implemented in either software or hardware. Hardware acceleration_x000D_
is the use of hardware to perform a task more efficiently than is possible in software. In order to achieve higher_x000D_
performance in today's heavily loaded communication networks, utilization of hardware accelerators for_x000D_
cryptography algorithms is more efficient. These hardware accelerators tend to offload the most computing_x000D_
intensive operations of encryption algorithms from the main processor._x000D_
Reconfigurable logic allows the definition of new functions to be defined in hardware units, combining_x000D_
hardware speed and efficiency, with ability to adapt and cope in a cost effective way with expanding_x000D_
functionality, changing environmental requirements, improvements in system features, changing protocols and_x000D_
data-coding standards._x000D_
This proposal will perform architecture exploration to find efficient architectures for encryption algorithms._x000D_
During the exploration phase, several architectures will be generated and evaluated to estimate the conflicting_x000D_
constraints and objectives such as area, performance, power consumption and flexibility., agreement title english : Hardware Implementation of Cryptographic Algorithms on FPGAs and ASICs, agreement title french : Hardware Implementation of Cryptographic Algorithms on FPGAs and ASICs, agreement number : EGP, agreement value : 25000.0, agreement start date : 2017-09-20, agreement end date : nan, description english : nan, description french : nan, expected results english : nan, expected results french : nan, additional information english : Grant or Award spanning more than one fiscal year (2017-2018 to 2018-2019)., additional information french : Subvention ou bourse octroyée s'appliquant à plus d'un exercice financier (2017-2018 à 2018-2019)., owner organization : nserc-crsng, owner organization title : Natural Sciences and Engineering Research Council of Canada | Conseil de recherches en sciences naturelles et en génie du Canada