Reference number : GC-2017-Q4-01962, amendment number : , agreement type : G, recipient legal name : Yuan, Fei (Ryerson University), recipient country : CA, recipient province : nan, recipient city : Ontario, recipient postal code : nan, program name english : Engage Grants for universities, program name french : Subventions d'engagement partenarial pour les universités, program purpose english : Analog-to-digital converters (ADCs) play a critical role in almost every aspect of our life. Various architectures_x000D_
of ADCs are available. Among them, flash, delta-sigma, and successive approximation register (SAR) ADCs_x000D_
emerged as dominant architectures. Flash ADCs offer the highest conversion rate and are widely popular in_x000D_
applications such as high-speed data communications over wire and optical channels. The exponentially rising_x000D_
silicon area and power consumption with bit resolution and difficulties in combating comparator mismatch_x000D_
limit their resolution to no more than 6 bits. Delta-sigma ADCs achieve the highest resolution by means of_x000D_
oversampling and noise-shaping. These ADCs are effective if signal bandwidth is small. SAR ADCs,_x000D_
introduced in 1950s and sat its debut in CMOS in 1970s, has played a significant role in advancing the_x000D_
state-of-the-art in ADCs since their inception. Although popular in telephony and low-speed instruments prior_x000D_
to the turning of 20th century, SAR ADCs have re-established themselves as the most promising ADC_x000D_
architecture inherently crafted for modern CMOS technologies with emerging applications ranging from_x000D_
biomedical implants where power consumption is most critical to high-speed data links where conversion rate_x000D_
is pivotal, accredited to their compatibility with technology scaling. The key functional block of SAR ADCs is_x000D_
a digital-to-analog converter realized using capacitor arrays. At high conversion rates, the dynamic power_x000D_
consumption of the capacitor arrays becomes prohibitively large. The silicon area needed to realize capacitor_x000D_
arrays also rises exponentially with bit resolution. Recently the feasibility of deploying time-mode techniques_x000D_
in SAR ADCs was explored. As compared with SAR ADCs with binary-weighted capacitor arrays, time-mode_x000D_
SAR ADCs offer the possibility of eliminating capacitor arrays so as to drastically lower power consumption_x000D_
and silicon area. The objective of this project is to develop and prototype an 8-bit 1 GS/s SAR ADC using a_x000D_
time-mode approach., program purpose french : Analog-to-digital converters (ADCs) play a critical role in almost every aspect of our life. Various architectures_x000D_
of ADCs are available. Among them, flash, delta-sigma, and successive approximation register (SAR) ADCs_x000D_
emerged as dominant architectures. Flash ADCs offer the highest conversion rate and are widely popular in_x000D_
applications such as high-speed data communications over wire and optical channels. The exponentially rising_x000D_
silicon area and power consumption with bit resolution and difficulties in combating comparator mismatch_x000D_
limit their resolution to no more than 6 bits. Delta-sigma ADCs achieve the highest resolution by means of_x000D_
oversampling and noise-shaping. These ADCs are effective if signal bandwidth is small. SAR ADCs,_x000D_
introduced in 1950s and sat its debut in CMOS in 1970s, has played a significant role in advancing the_x000D_
state-of-the-art in ADCs since their inception. Although popular in telephony and low-speed instruments prior_x000D_
to the turning of 20th century, SAR ADCs have re-established themselves as the most promising ADC_x000D_
architecture inherently crafted for modern CMOS technologies with emerging applications ranging from_x000D_
biomedical implants where power consumption is most critical to high-speed data links where conversion rate_x000D_
is pivotal, accredited to their compatibility with technology scaling. The key functional block of SAR ADCs is_x000D_
a digital-to-analog converter realized using capacitor arrays. At high conversion rates, the dynamic power_x000D_
consumption of the capacitor arrays becomes prohibitively large. The silicon area needed to realize capacitor_x000D_
arrays also rises exponentially with bit resolution. Recently the feasibility of deploying time-mode techniques_x000D_
in SAR ADCs was explored. As compared with SAR ADCs with binary-weighted capacitor arrays, time-mode_x000D_
SAR ADCs offer the possibility of eliminating capacitor arrays so as to drastically lower power consumption_x000D_
and silicon area. The objective of this project is to develop and prototype an 8-bit 1 GS/s SAR ADC using a_x000D_
time-mode approach., agreement title english : The Development of Successive Approximation Register Analog-to-Digital Converter Using Time-Mode Approaches, agreement title french : The Development of Successive Approximation Register Analog-to-Digital Converter Using Time-Mode Approaches, agreement number : EGP, agreement value : 25000.0, agreement start date : 2018-01-10, agreement end date : nan, description english : nan, description french : nan, expected results english : nan, expected results french : nan, additional information english : Grant or Award spanning more than one fiscal year (2017-2018 to 2018-2019)., additional information french : Subvention ou bourse octroyée s'appliquant à plus d'un exercice financier (2017-2018 à 2018-2019)., owner organization : nserc-crsng, owner organization title : Natural Sciences and Engineering Research Council of Canada | Conseil de recherches en sciences naturelles et en génie du Canada