Before revision: The simplest way to understand SIMT is to imagine a multi-core system, where each core has its own register file, own ALUs and its own data cache, but that unlike a standard multi-core system which has multiple independent instruction caches and decoders, the instructions are broadcast to all SIMT cores from a single unit with a single instruction cache and a single instruction decoder .
After revision: as well as multiple independent Program Counter registers,which reads instructions using a single Program CounterThe simplest way to understand SIMT is to imagine a multi-core system, where each core has its own register file, own ALUs and its own data cache, but that unlike a standard multi-core system which has multiple independent instruction caches and decoders, the instructions are broadcast to all SIMT cores from a single unit with a single instruction cache and a single instruction decoder .