Before revision:  For the L2 cache controller and the DRAM controller components of OpenSPARC T2, our new technique reduces the probability that an application run results in an erroneous outcome due to soft errors by more than 100x with only 3.13\% and 5.69 \% chip-level area and power impact, respectively.
After revision:  For the L2 cache controller and the DRAM controller components of OpenSPARC T2, our new technique reduces the probability that an application run results in an erroneous outcome due to soft errors by more than 100x with 3.32\% and 6.09 \% chip-level area and power impact, respectively.