Before revision: When used as cache, the latency of a miss accessing both the MCDRAM and the DIMM is significantly higher than going directly to the DIMM , and so applications may need to be tuned to avoid excessive cache misses.
After revision: When used as cache, the latency of a miss accessing both the MCDRAM and DDR is slightly higher than going directly to DDR , and so applications may need to be tuned to avoid excessive cache misses.