Before revision: Among the components created by OpenCores contributors are: OpenRISC – a highly configurable RISC central processing unit Amber (processor core) – an ARM-compatible RISC central processing unit A Zilog Z80 clone USB 2.0 controller Tri Ethernet controller, 10/100/1000 Mbit Encryption units, for example DES, AES and RSA HyperTransport Tunnel A PIC16F84 corerisc16f84 URL Zet – an x86 compatible corezet86 URL OpenRISC ASIC In April 2011 OpenCores opened donationsCall for OpenRISC ASIC donations, 30 April 2011 for a new project to develop a complete system on a chip design based on the OpenRISC processor and implement it into an ASIC-component.
After revision: Among the components created by OpenCores contributors are: OpenRISC – a highly configurable RISC central processing unit Amber (processor core) – an ARM-compatible RISC central processing unit A Zilog Z80 clone USB 2.0 controller Tri Ethernet controller, 10/100/1000 Mbit Encryption units, for example DES, AES and RSA HyperTransport Tunnel A PIC16F84 core<ref>risc16f84 URL Zet – an x86 compatible corezet86 URL OpenRISC ASIC In April 2011 OpenCores opened donationsCall for OpenRISC ASIC donations, 30 April 2011 for a new project to develop a complete system on a chip design based on the OpenRISC processor and implement it into an ASIC-component.