Before revision:  We present how the two memory abstractions can be realized with small extensions to existing OS and hardware architecture . In particular, we show the potential benefits of our approach in the context of shared cache management, by presenting a deterministic memory-aware cache architecture and its manage- ment scheme. We evaluate the effectiveness of the deterministic memory-aware cache management approach compared with a conventional way-based cache partitioning approach , using a set of synthetic and real benchmarks.
After revision:  We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results , using a set of synthetic and real benchmarks.