Before revision: The total normalised path delay D can be expressed in terms of an overall path effort, F, and the path parasitic delay P (which is the sum of the individual parasitic delays): The path effort is expressed in terms of the path logical effort G (the product of the individual logical efforts of the gates), and the path electrical effort H (the ratio of the load of the path to its input capacitance).
After revision: The total normalized path delay D can be expressed in terms of an overall path effort, F, and the path parasitic delay P (which is the sum of the individual parasitic delays): The path effort is expressed in terms of the path logical effort G (the product of the individual logical efforts of the gates), and the path electrical effort H (the ratio of the load of the path to its input capacitance).