Before revision:  In this paper, we propose a very low overhead and portable analysis for exposing the hidden latency of each individual instruction executing in the pipeline and different access latencies of the various memory hierarchies at the microarchitecture level. We also show the impact of the possible optimizations a CUDA compiler have over the various latencies.
After revision:  In this paper, we propose a very low overhead and portable analysis for exposing the hidden latency of each individual instruction executing in the pipeline and different access latencies of the various memory hierarchies found in GPUs at the micro-architecture level. Furthermore, we show the impact of the possible optimizations a CUDA compiler have over the various latencies.