Before revision: Recent implementation models 387x387px|Cache organization of Intel Nehalem microarchitecture Intel Broadwell microarchitecture (2014) L1 cache (instruction and data) – 64 per core L2 cache – 256 kB per core L3 cache – 2 to 6 MB shared L4 cache – 128 MB of eDRAM (Iris Pro models only) Intel Kaby Lake microarchitecture (2016) L1 cache (instruction and data) – 64 kB per core L2 cache – 256 kB per core L3 cache – 2 MB to 8 MB shared AMD Zen microarchitecture (2017) L1 cache – 32 kB data & 64 kB instruction per core, 4-way L2 cache – 512 kB per core, 4-way inclusive L3 cache – 4 MB local & remote per 4-core CCX, 2 CCXs per chiplet, 16-way non-inclusive.
After revision: Xeon Emerald Rapids (2024) Up 64 core: L1 cache - 80 per core L2 cache - 2 per core L3 cache - 5 per core (i.e., up to 320 total)AMD EPYC 9684X (2023) 96 core: L1 cache - 64 per core L2 cache - 1 per core L3 cache - 1152 sharedIntelRecent implementation models 387x387px|Cache organization of Intel Nehalem microarchitecture Intel Broadwell microarchitecture (2014) L1 cache (instruction and data) – 64 per core L2 cache – 256 kB per core L3 cache – 2 to 6 MB shared L4 cache – 128 MB of eDRAM (Iris Pro models only) Intel Kaby Lake microarchitecture (2016) L1 cache (instruction and data) – 64 kB per core L2 cache – 256 kB per core L3 cache – 2 MB to 8 MB shared AMD Zen microarchitecture (2017) L1 cache – 32 kB data & 64 kB instruction per core, 4-way L2 cache – 512 kB per core, 4-way inclusive L3 cache – 4 MB local & remote per 4-core CCX, 2 CCXs per chiplet, 16-way non-inclusive.