Before revision: Architecture + Motorola 68881/68882 series registers 79 ... 63 ... 00 (bit position) Floating point registers ± exponent mantissa FP0 ± exponent mantissa FP1 ± exponent mantissa FP2 ± exponent mantissa FP3 ± exponent mantissa FP4 ± exponent mantissa FP5 ± exponent mantissa FP6 ± exponent mantissa FP7 31 ... 23 ... 15 ... 07 ... 00 (bit position) Control register 0 0 Exception Enable Mode Control FPCR Status register Condition Quotient Exception Status Accrued Exception FPSR Instruction address register 32 Bit Address FPIAR The 68881 has eight 80-bit data registers 2 3 (a 64-bit mantissa plus a sign bit, and a 15-bit signed exponent).
After revision: Architecture + Motorola 68881/6888 series registers 79 ... 6 ... 00 (bit position) Floating point registers ± exponent mantissa FP0 ± exponent mantissa FP1 ± exponent mantissa FP2 ± exponent mantissa FP3 ± exponent mantissa FP4 ± exponent mantissa FP5 ± exponent mantissa FP6 ± exponent mantissa FP7 31 ... 23 ... 15 ... 07 ... 00 (bit position) Control register 0 0 Exception Enable Mode Control FPCR Status register Condition Quotient Exception Status Accrued Exception FPSR Instruction address register 32 Bit Address FPIAR The 68881 has eight 80-bit data registers 2 3 (a 64-bit mantissa plus a sign bit, and a 15-bit signed exponent).