Before revision: SPI operates in the following way: The master determines an appropriate CPOL & CPHA value The master pulls down the slave select (SS) line for a specific slave chip The master clocks SCK at a specific frequency During each of the 8 clock cycles the transfer is full duplex: The master writes on the MOSI line and reads the MISO line The slave writes on the MISO line and reads the MOSI line When finished the master can continue with another byte transfer or pull SS high to end the transfer When a slave's SS line is high then both of its MISO and MOSI line should be high impedance so to avoid disrupting a transfer to a different slave.
After revision: weinershellopewepSPI operates in the following way: The master determines an appropriate CPOL & CPHA value The master pulls down the slave select (SS) line for a specific slave chip The master clocks SCK at a specific frequency During each of the 8 clock cycles the transfer is full duplex: The master writes on the MOSI line and reads the MISO line The slave writes on the MISO line and reads the MOSI line When finished the master can continue with another byte transfer or pull SS high to end the transfer When a slave's SS line is high then both of its MISO and MOSI line should be high impedance so to avoid disrupting a transfer to a different slave.