Before revision: Archi-tecture Bits Version Intro-duced Max #operands Type Design Registers(excluding FP/vector) Instruction encoding Branch evaluation Endian-ness Extensions Open Royaltyfree 6502 8 1975 1 Register–Memory CISC 3 Variable (8- to 24-bit) Condition register Little 6800 8 1974 1 Register–Memory CISC 3 Variable (8- to 32-bit ) Condition register Big 6809 8 1978 1 Register–Memory CISC 3 Variable (8- to 32-bit) Condition register Big 680x0 32 1979 2 Register–Memory CISC 8 data and 8 address Variable Condition register Big 8080 8 1974 2 Register–Memory CISC 7 Variable (8 to 24 bits) Condition register Little 8051 32 (8→32) 1977?
After revision: Archi-tecture Bits Version Intro-duced Max #operands Type Design Registers(excluding FP/vector) Instruction encoding Branch evaluation Endian-ness Extensions Open Royaltyfree 6502 8 1975 1 Register–Memory CISC 3 Variable (8- to 24-bit) Condition register Little 6800 8 1974 1 Register–Memory CISC 3 Variable (8- to 24-bit ) Condition register Big 6809 8 1978 1 Register–Memory CISC 5 Variable (8- to 32-bit) Condition register Big 680x0 32 1979 2 Register–Memory CISC 8 data and 8 address Variable Condition register Big 8080 8 1974 2 Register–Memory CISC 7 Variable (8 to 24 bits) Condition register Little 8051 32 (8→32) 1977?