Before revision: References [1] Rusu, S.; Tam, S.; Muljono, H.; Ayers, D.; Chang, J.; Cherkauer, B.; Stinson, J.; Benoit, J.; Varada, R.; Leung, J.; Limaye, R. D.; Vora, S.; "A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache," Solid-State Circuits, IEEE Journal of , vol.42, no.1, pp.17- 25, Jan. 2007, URL [2] Gammie, G.; Wang, A.; Mair, H.; Lagerquist, R.; Minh Chau; Royannez, P.; Gururajarao, S.; Uming Ko; "SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors," Proceedings of the IEEE , vol.98, no.2, pp.144-159, Feb. 2010 40-nm FPGA Power Management and Advantages.
After revision: 3References [1] Rusu, S.; Tam, S.; Muljono, H.; Ayers, D.; Chang, J.; Cherkauer, B.; Stinson, J.; Benoit, J.; Varada, R.; Leung, J.; Limaye, R. D.; Vora, S.; "A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache," Solid-State Circuits, IEEE Journal of , vol.42, no.1, pp.17- 25, Jan. 2007, URL [2] Gammie, G.; Wang, A.; Mair, H.; Lagerquist, R.; Minh Chau; Royannez, P.; Gururajarao, S.; Uming Ko; "SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors," Proceedings of the IEEE , vol.98, no.2, pp.144-159, Feb. 2010 40-nm FPGA Power Management and Advantages.