Before revision: Any of these GNU inline assembler statements forbids the GCC compiler to reorder read and write commands around it:GCC compiler-gcc.h asm volatile("" ::: "memory"); __asm__ __volatile__ ("" ::: "memory"); This C11/C++11 function forbids the compiler to reorder read and write commands around it: atomic_signal_fence(memory_order_acq_rel); Intel ICC compiler uses "full compiler fence" intrinsics:ECC compiler-intel.h Intel(R) C++ Compiler Intrinsics Reference __memory_barrier() Microsoft Visual C++ Compiler: Visual C++ Language Reference _ReadWriteBarrier _R eadWriteBarrier() Combined barriers In many programming languages different types of barriers can be combined with other operations (like load, store, atomic increment, atomic compare and swap), so no extra memory barrier is needed before or after it (or both).
After revision: Any of these GNU inline assembler statements forbids the GCC compiler to reorder read and write commands around it:GCC compiler-gcc.h asm volatile("" ::: "memory"); __asm__ __volatile__ ("" ::: "memory"); This C11/C++11 function forbids the compiler to reorder read and write commands around it: atomic_signal_fence(memory_order_acq_rel); Intel C++ Compiler (ICC/ICL) uses "full compiler fence" intrinsics:ECC compiler-intel.h Intel(R) C++ Compiler Intrinsics Reference __memory_barrier() Microsoft Visual C++ compiler (MSVC) supports some intrinsics only for x86/x64 (all of these are deprecated):eadBarrier() _WriteBarrier() _R _R eadWriteBarrier() Combined barriers In many programming languages different types of barriers can be combined with other operations (like load, store, atomic increment, atomic compare and swap), so no extra memory barrier is needed before or after it (or both).