Before revision: This technique has been used for microprocessor front-side busses, Ultra-3 SCSI, expansion buses (AGP, PCI-X), graphics memory (GDDR), main memory (both RDRAM and DDR1 through DDR4 ), and the HyperTransport bus on AMD's Athlon 64 processors.
After revision: This technique has been used for microprocessor front-side busses, Ultra-3 SCSI, expansion buses (AGP, PCI-X), graphics memory (GDDR), main memory (both RDRAM and DDR1 through DDR5 ), and the HyperTransport bus on AMD's Athlon 64 processors.