Before revision:  In this paper, we propose a very low overhead and portable analysis for exposing the hidden latency of each individual instruction executing in the pipeline and different access latencies of the various memory hierarchies at the microarchitecture level.
After revision:  In this paper, we propose a very low overhead and portable analysis for exposing the latency of each individual instruction executing in the pipeline and different access latencies of the various memory hierarchies at the microarchitecture level.