Before revision:  We analytically derive the criteria for which the reduction in the number of CNOT gates due to the DFS based technique can provide lower error probability even with some increased depth, and show that all graphs conform to this criteria, making this technique universal. We further show that this proposed optimization holds even in the post transpilation stage of the circuit , which is actually executed in the IBM Quantum hardware .
After revision:  We analytically derive the criteria for which the reduction in the number of CNOT gates due to the DFS based technique can provide lower error probability even with some increased depth, and the error probability of the circuit , which is actually executed in the IBM Quantum hardware .