Before revision: Date Name Developer Clock Process Transistors(millions) Cores per die /Dies per module Threadsper core 2010 POWER7 IBM 3–4.14 GHz 45 nm 1200 4, 6, 8 / 1, 4 4 2010 Itanium "Tukwila" Intel 2 GHz 65 nm 2000 2, 4 / 1 2 2010 Opteron "Magny-cours" AMD 1.7–2.4 GHz 45 nm 1810 4, 6 / 2 1 2010 Xeon "Nehalem-EX" Intel 1.73–2.66 GHz 45 nm 2300 4, 6, 8 / 1 2 2010 z196 IBM 3.8–5.2 GHz 45 nm 1400 4 / 1, 6 1 2010 SPARC T3 Sun 1.6 GHz 45 nm 2000 16 / 1 8 2010 SPARC64 VII+ Fujitsu 2.66–3.0 GHz 45 nm ?
After revision: Date Name Developer Clock Process 2010 POWER7 IBM 3–4.14 GHz 45 nm 1200 4, 6, 8 / 1, 4 4 2010 Itanium "Tukwila" Intel 2 GHz 65 nm 2000 2, 4 / 1 2 2010 Opteron "Magny-cours" AMD 1.7–2.4 GHz 45 nm 1810 4, 6 / 2 1 2010 Xeon "Nehalem-EX" Intel 1.73–2.66 GHz 45 nm 2300 4, 6, 8 / 1 2 2010 z196 IBM 3.8–5.2 GHz 45 nm 1400 4 / 1, 6 1 2010 SPARC T3 Sun 1.6 GHz 45 nm 2000 16 / 1 8 2010 SPARC64 VII+ Fujitsu 2.66–3.0 GHz 45 nm ?