Before revision: Therefore the total normalised delay of an inverter driving an equivalent inverter is Delay in NAND and NOR gates The logical effort of a two-input NAND gate is calculated to be g = 4/3 because a NAND gate with input capacitance 4 can drive the same current as the inverter can, with input capacitance 3.
After revision: ,Therefore the total normalised delay of an inverter driving an equivalent inverter is Delay in NAND and NOR gates The logical effort of a two-input NAND gate is calculated to be g = 4/3 because a NAND gate with input capacitance 4 can drive the same current as the inverter can, with input capacitance 3.