Before revision:  A detailed evaluation using the VTA hardware accelerator with the Baidu DeepBench inference benchmark suite shows that our approach can automatically generate code competitive to reference implementations , and furthermore that memory layout flexibilty can be beneficial for overall performance. While the reference implementation achieves very low hardware utilization due to its fixed embedding strategy, we achieve a geomean speedup of up to x2 .49, while individual operators can improve as much as x238 .
After revision:  A detailed evaluation using the VTA hardware accelerator with the Baidu DeepBench inference benchmark suite shows that our approach can automatically generate code competitive to reference implementations . Further, we show that dynamically determining the data layoutbased on intrinsic and workload is beneficial for hardware utilization and performance. In cases where the reference implementationhas low hardware utilization due to its fixed embedding strategy, we achieve a geomean speedup of up to x2 .49, while individual operators can improve as much as x238 .