SummarySkilled at analyzing design specifications and applying verification techniques in Verilog Vhdl. Over 4 years of experience working on FPGA Design Verification, Synthesis, Place Route using Synopsys Synplify-Pro Libero Soc Xilinx-ISE, C programming for ARM Freescale CPUs, Writing Digital Core Test plans for Interfaces, SI testing with Hyperlynx Pspice Simulators. HighlightsHardware Description Languages Verilog, SystemVerilog for Design Assertion,VHDL Programming Languages C, Tcl Perl Scripting, C , 8051 Freescale ARM Assembly Tools Modelsim Simulators, Synopsys Synplify Pro, Microsemi Actel Libero Soc 11.7, SmartTime (Static Timing Analysis tool), Xilinx ISE, Synopsys Design IC compiler, Primetime (STA), Hyperlynx LT Pspice Simulators, Orcad Schematic Capture Layout Experience04 2012toCurrentSenior Electrical EngineerHdr, Inc. Raleigh,,Design, Debug and Verification of source code written in Verilog for Microsemi FPGAs.Worked with 2 FPGA designs at the same time, handling both design and verification.Simulation using Modelsim and verifying the quality of testbench with Code Coverage.Writing timing constraints and build scripts for FPGA image release process using TCL.Wrote SystemVerilog Assertions OVL assertions for Asynchronous FIFO verification.Redesigned Finite State Machines (FSM) to meet max delay (setup time) timing goals.Fixed clock domain crossing timing problems using SmartTime Static Timing Analyzer.Reduced the overall resource utilization (area) of an existing FPGA design by about 10 .Writing Digital Core Test Plan for Interfaces of FPGA and Freescale CPUs (MPC5644).Used Hyperlynx Simulation for Signal Integrity testing and directed 2 Lab Technicians.10 2011to01 2012Test Systems Electrical Engineer Intern ,CO,Analog Digital Circuit Design, Motor Control using TI DSP and Semiconductor Testing.PCB (Orcad) Capture Layout and Design of Test fixtures in C and Labview Programs.Designing in Verilog HDL Verification using Test Benches (Modelsim) for FPGAs.01 2011to09 2011Research Assistant ,,Worked on Low Power Optimization of FPGA and ASIC using Design and IC compiler.Role was to write scripts (Tcl), apply design constraints, perform power timing analysis.Included RTL Synthesis, Place and Route, STA, Test Bench Verification using Verilog.07 2008to07 2009Embedded EngineerUniversity Of North Carolina Greensboro City,,IndiaDesigning and Debugging in Embedded C C Assembly for 8051 8086 ARM CPUs.Worked with Robotics team on controlling the movement of Robot using ARM9 MCU.Used Stepper motors, Serial interfaces, Embedded Web Server Linux Windows OS.Jessica Claire PROJECTS UNDERTAKEN Electronics Injection Ignition Driver Control and Diagnostics (at Woodward Inc.) FPGA provides the control logic for the Power Electronics which in turn drives the injector and ignition coils.FPGA also monitors and provides the Diagnostics (open fault, short to gnd -, short to battery -) for each output coil and sends this information to CPU via SPI.Apart from providing Diagnostics information, FPGA also protects the hardware instantly when some kind of critical fault is encountered.Time to reach peak current was also reported by the FPGA for diagnostics purposes for each output coil (kV detection).Trigger and Discrete Outputs Control and Diagnostics (at Woodward Inc.) FPGA provides the control logic for Power Electronics which in turn drives the Trigger and Discrete Outputs (High Side, Low Side and Push-Pull Totem Pole Output).FPGA also monitors and provides the Diagnostics (open fault, short to gnd, short to battery) for each output and sends this information to CPU via SPI.Apart from providing Diagnostics information, FPGA also protects the hardware instantly when some kind of critical fault is encountered.Power optimization in FPGA ASIC design using Synopsys Design and IC compiler tools.A 32-bit ALU designed using Verilog HDL using bottom up approach and horizontal vertical partitioning techniques was taken as the design example.This project involved completing a Low Power ASIC design flow in 45 nm technology using Synopsys Design Compiler and IC compiler in order to generate the gate level net list, perform placement, routing, clock tree synthesis and then optimize the power, area and timing of the design.Implementation and Design of Dice Game Controller using Xilinx Spartan 3E FPGA.This project involved implementing and designing the dice game controller using Finite State Machine (FSM) in VHDL and running the dice game on the Spartan 3E FPGA board.It mainly consisted of 2 counters, one adder to add the outputs of the 2 counters, a comparator to compare the sum and the point, register to store the point, control logic to find if the player wins or loses. EducationExpected inMay 2011totoMaster of Science (MS) Electrical EngineeringCalifornia State University-,GPA Electrical EngineeringExpected inJune 2008totoBachelor of Engineering Electronics and CommunicationAtria Institute of Technology (VTU)-,GPA Electronics and Communication Skillsapproach, ASIC, C, C , Circuit Design, Hardware, Controller, CPU, Debugging, Designing, DSP, Electronics, Embedded C, image, Labview, Layout and Design, Layout, Linux, logic, max, Windows OS, monitors, Optimization, Orcad, peak, Perl Scripting, Programming, Pspice, quality, Robotics, routing, scripts, Simulation, TCL, Verilog, VHDL, Web Server, written  SEP  Our Client, an Innovative Company, has spent the past decade focused on the design and development of advanced technology for commercial applications. As they prepare for the next phase of their journey, they are in search of an accomplished and skilled Electrical Engineering Manager to join their team. In the role of Electrical Manager Director, you will play a pivotal part in overseeing comprehensive electrical systems architecture. Your responsibilities will encompass providing expert technical guidance for product design elements, fostering collaboration with various teams, and seamlessly integrating components into a unified system. Reporting directly to the Electrical Engineering Director, you will be instrumental in devising engineering strategies, initiating new projects, and ensuring the effective utilization of technology and resources to fulfill customer demands. This is an opportunity to work in a dynamic startup environment, where your contributions will make a tangible impact. Our Client values individuals who are eager to take on challenges, voice their ideas, and be accountable for their results. If you have experience working in Electrical Architecture with specific experience in DFMEA, Lean Engineering Principles, Power Electronics, High Voltage Systems, ISO26262 Compliance, and ASPICE framework, we would like to hear from you. Responsibilities Shape complete electrical systems architecture, ensuring a robust vehicle network strategy.Develop and refine engineering strategies and processes.Provide technical direction and guidance for comprehensive product design, particularly focusing on electrical architecture.Identify emerging opportunities and spearhead new projects.Contribute to the company s core activities through a solid understanding of principles and applications.Offer leadership and accountability to ensure successful execution. Requirements Bachelor s degree in Engineering required Master s degree preferred.A minimum of 10 years of experience in electrical system development and design, including electrical component development, validation, and launch.Strong analytical and decision-making skills.Experience in electrical engineering within an automotive context, with a minimum of 8 years of experience.Proven leadership abilities with excellent communication and interpersonal skills.Familiarity with problem-solving methodologies like DFMEA, six sigma design, and lean engineering.Experience with various automotive electrical systems.Understanding of ISO26262 and ASPICE processes.Awareness of cyber security risks and solutions.Capacity to develop innovative electrical architecture solutions.Occasional travel flexibility. Location Troy, Michigan (Onsite)Term Full-time, PermanentRate 130,000 - 150,000 - Negotiable on ExperienceBenefits 15 Target Bonus Program, excellent PTO and Holiday calendar, 401K Matching, Strong Healthcare More! If you meet the above qualifications and are excited about the prospect of joining our team, please submit your resume and cover letter for consideration. We look forward to hearing from you! At Human Capital Ventures, we are committed to promoting equality and diversity in all aspects of our business. We believe in creating supportive and inclusive environments where everyone can thrive, regardless of their race, ethnicity, gender, sexual orientation, religion, age, or ability. We strongly encourage applicants from diverse backgrounds to apply for our positions.

ATS compatibility score: 53.1 (Potential Fit)