Time-predictable Multi-Core Architecture for Embedded Systems (T-CREST)

Framework: FP7 — Cooperation
Programme: Information and Communication Technologies
Destination: Alternative Paths to Components and Systems
Action type: Collaborative project
Countries involved: United Kingdom,Denmark,Germany,Austria,Netherlands,United Kingdom,Portugal,Italy
Call:  (FP7-ICT-2011-7, 2011)
Start date: 2011-09-01
End date: 2014-08-31
Duration (months): 36.0
Total project cost (EUR): 3652541.0
EU funding (EUR): 2650000.0
Participants: 9
Project status: CLOSED

Safety-critical systems are important parts of our daily life. Those systems are also called dependable systems, as our lives can depend on them. Examples are controllers in an airplane, breaking controller in a car, or a train control system. Those safety-critical systems need to be certified and the maximum execution time needs to be bounded and known so that response times can be assured when critical actions are needed. Even with high performance processors in our desktop PCs we notice once in a while that the PC is “frozen” for a few seconds. For a safety-critical system such a “pause” can result in a catastrophic failure. The mission of T-CREST is to develop tools and build a system that prevents pauses by identifying and addressing the causes for possible pauses. The T-CREST time-predictable system will simplify the safety argument with respect to maximum execution time striving to double performance for 4 cores and to be 4 times faster for 16 cores than a standard processor in the same technology (e.g., FPGA). Thus the T-CREST system will result in lower costs for safety relevant applications reducing system complexity and at the same time faster time-predictable execution. Standard computer architecture is driven by the following paradigm: make the common case fast and the uncommon case correct. This design approach leads to architectures where the average-case execution time is optimized at the expense of the worst-case execution time (WCET). Modelling the dynamic features of current processors, memories, and interconnects for WCET analysis often results in computationally infeasible problems. The bounds calculated by the analysis are thus overly conservative. We need a sea change and we shall take the constructive approach by designing computer architectures where predictable timing is a first-order design factor. For real-time systems we propose to design architectures with a new paradigm: make the worst-case fast and the whole system easy to analyse. Despite the advantages of analysable system resources, only a few research projects exist in the field of hardware optimized for the WCET. Within the project we will propose novel solutions for time-predictable multi-core and many-core system architectures. The resulting time-predictable resources (processor, interconnect, memories, etc.) will be a good target for WCET analysis and the WCET performance will be outstanding compared to current processors. Time-predictable caching and time-predictable chip-multiprocessing (CMP) will provide a solution for the need of more processing power in the real-time domain. Next to the hardware (processor, interconnect, memories), a compiler infrastructure will be developed in the project. WCET aware optimization methods will be developed along with detailed timing models such that the compiler benefits from the known behaviour of the hardware. The WCET analysis tool aiT will be adapted to support the developed hardware and guide the compilation.

Keywords: wcet,time-predictable,multi-core,many-core,chip-multiprocessing,vliw processor,real-time