Data-Gouv-ML/pcri-informations-sur-les-projets-laureats huggingface dataset:
Identification of new molecules able to bypass the cell wall compensatory pathways in the pathogenic fungus Aspergillus fumigatus (CELLWALLPATH)

Framework: FP7 — People
Programme: Marie-Curie Actions
Theme: Marie Skłodowska-Curie
Destination: European Re-integration Grants
Action type: Support for training and career development of researchers (Marie Curie)
Countries involved: Germany
Call:  (FP7-PEOPLE-2009-RG, 2009)
Start date: 2010-03-01
End date: 2013-02-28
Duration (months): 36.0
Total project cost (EUR): 45000.0
EU funding (EUR): 45000.0
Participants: 1
Project status: CLOSED

Aspergillus fumigatus is the most important air-borne fungal pathogen, causing severe infections with invasive growth in immunocompromised patients. For growth in all habitats, the fungus needs to be able to sense environmental stimuli and to transduce signals via specific signalling cascades. Calmodulin/calcineurin, Ras/cAMP, mTOR and general Mitogen-activated protein kinase (MAPK) signalling pathways are involved in the regulation of various cellular responses in eukaryotes. Previous studies revealed that the central core of the MAPK cell wall integrity signalling pathway in A. fumigatus is composed of three protein kinases. Deletion of these genes resulted in severe sensitivity of the mutants against cell wall-disturbing compounds and drastic alterations of the fungal morphology. Nevertheless, the mutants were still virulent in a murine infection model. Even more, therapeutic treatment with medical commercial cell wall-acting compounds, like echinocandins and azoles, did not result in effective treatment against aspergillosis, indicating the importance of cell wall assembling pathways compensating the inhibition caused by cell wall-disturbing compounds. Protein kinase activation requires phosphorylation. This process is reversible even in the continued presence of activating stimuli. The importance of protein phosphatases for signalling pathways and cross talk interactions is emerging. Ontology classification analysis revealed that the A. fumigatus genome contains 24 genes coding for putative protein phosphatases. A comprehensive and extensive study on protein phosphatases in filamentous fungi has never been attempted so far. Here, we propose to study protein phosphatase families in A. fumigatus. Mutant strains will be used to investigate cell wall compensatory pathways in order to identify new molecules for therapeutic intervention against aspergillosis.

Keywords: health sciences,aspergillus fumigatus,signal transduction,cell wall integrity,protein phosphatases,compensatory mechanisms,antifungal drugs
IntEgrated ModelliNg and Synthesis tOol flow for Embedded SYStems Design (ENOSYS) (ENOSYS)

Framework: FP7 — Cooperation
Programme: Information and Communication Technologies
Destination: Components, systems, engineering
Action type: Collaborative project
Countries involved: France,Greece,France,United Kingdom,United Kingdom
Call:  (FP7-ICT-2009-4, 2009)
Start date: 2010-01-01
End date: 2012-12-31
Duration (months): 36.0
Total project cost (EUR): 3971409.0
EU funding (EUR): 2595657.0
Participants: 6
Project status: CLOSED

The main objectives of the ENOSYS project are to shorten time to market and reduce design costs in the development of new electronic products. This is of prime importance to European companies seeking to increase their share of the competitive consumer electronics market, where the flexibility to move quickly to add distinguishing features, such as faster operation, lower power consumption or miniaturization, is paramount. ENOSYS intends to achieve this by allowing designers to work at a high level of abstraction and removing the need to concentrate on the time-consuming details of the design. ENOSYS proposes a seamless tool flow for embedded systems modeling and synthesis and addresses the integration and enhancement of existing tools from European SME vendors (SOFTEAM and Axilica) to build a common extendable design environment. This will be delivered through: (a) the development of approaches for embedded system specification on different abstraction layers; (b) the development of efficient techniques for the exploration of the hardware/software design space and (c) the automatic synthesis of efficient descriptions for both hardware (synthesizable HDL) and embedded software (C/C++) components of the targeted system from models based on UML MARTE profile. To evaluate and to bring the proposed concepts to industrial application ENOSYS performs two complementary case studies (INTRACOM Telecom and THALES) covering wireless and/or multimedia application representing the future system complexity. Loughborough University and University of Peloponnese will deliver important new enhancements to improve performance and general applicability. Through active participation in the OMG standardization activities, results will be exploited both during the project and will persist long after completion. The partners will have the opportunity to transfer their actual design needs, stemming from real world cases studies in highly demanding application areas to emerging standards.

Keywords: marte,co-design,hdl,synthesis,design space exploration
The Geometry of Severi varieties on toric surfaces (GSV)

Framework: FP7 — People
Programme: Marie-Curie Actions
Theme: Marie Skłodowska-Curie
Destination: International Re-integration Grants
Action type: Support for training and career development of researchers (Marie Curie)
Countries involved: Israel
Call:  (FP7-PEOPLE-2009-RG, 2009)
Start date: 2009-10-01
End date: 2013-09-30
Duration (months): 48.0
Total project cost (EUR): 100000.0
EU funding (EUR): 100000.0
Participants: 1
Project status: CLOSED

I propose to study the geometry of Severi varieties. Roughly speaking, Severi varieties parameterize (irreducible) curves of a given geometric genus in a linear system on an algebraic surface. Introduced by Severi in the 1920s, Severi varieties have been intensively studied (mostly in the plane case and in characteristic zero) by many algebraic geometers, such as Zariski, Fulton, Harris, Ran, Kontsevich, Caporaso, Vakil, and Mikhalkin. Despite this intensive study of Severi varieties, many questions have remained open, e.g., the case of positive characteristic, for which neither the dimension nor the irreducibility is known and for which enumerative formulas are also not known. In characteristic zero, the irreducibility property is not known for any surfaces other than the projective plane and Hirzebruch surfaces. (The irreducibility property is, however, known for rational curves in some cases.) In this study, I propose to investigate the geometry of Severi varieties on toric surfaces. In positive characteristic, I intend to: prove dimension formula; construct examples of toric surfaces admitting reducible Severi varieties and classify all such surfaces; describe the geometry of a general curve of a given geometric genus on a toric surface (note that as opposed to the case in characteristic zero, such a curve need not be nodal, and the description of its geometry will include the classification of its singularities); and generalize Mikhalkin&apos;s tropical enumerative formulas to this case (it should be emphasized that Severi varieties are not defined over the integers, and their degrees depend on the characteristic). In characteristic zero, I intend to prove the irreducibility property for Severi varieties on toric surfaces. The main tools that will be developed and applied in this research are drawn from deformation theory of schemes, morphisms, and stacks; and from toric and tropical geometries (see part B of the proposal for details).

Keywords: algebraic geometry,toric geometry,tropical geometry,severi varieties,families of curve on surfaces
WIDE spectral band & WIDE dynamics multifunctional imaging SENSor Enabling safer car transportation (2WIDE_SENSE)

Framework: FP7 — Cooperation
Programme: Information and Communication Technologies
Destination: ICT for mobility, environmental sustainability and energy efficiency
Action type: Collaborative project
Countries involved: France,Italy,Italy,United Kingdom,Italy,Germany
Call:  (FP7-ICT-2009-4, 2009)
Start date: 2010-01-01
End date: 2012-12-31
Duration (months): 36.0
Total project cost (EUR): 5022526.0
EU funding (EUR): 3200000.0
Participants: 7
Project status: CLOSED

The White Paper on EU Transport Policy for 2010 states a key objective: 50% reduction of casualties due to road accidents by the end of 2010. Improvements on road safety are achievable increasing the EU market penetration of eSafety systems, currently limited by performance and cost of sensor technologies. According to ICT-2009.6.1, 2WIDE_SENSE addresses research challenges in the area of “Intelligent Vehicle Systems for further improving road safety … This includes advanced in-vehicle safety systems with improved performance and reduced costs”. The project aims at providing European automotive industry with the next generation of imaging sensors beyond the current CMOS imagers. The core sensing technology is a cost-effective InGaAs focal plane array with wide spectral response (VIS-NIR-SWIR) and wide dynamic range (120dB). The benefits deriving from the additional SWIR bandwidth allow enhancing preventive safety functions and car energy efficiency. The specific objectives are: ?- implementation of the paradigm of ‘application independent’ multifunctional camera; ?- hybridisation of InGaAs detector on silicon read out circuits; ?- deposition of low cost interferential bandpass optical filters at pixel level; ?- design of AR coatings and plastic lenses; ?- development of multi-spectral wide dynamic range camera engine; ?- algorithm development for predictive road status monitoring; ?- sensor validation adapting existing ADAS software platforms (LDW, NV, HBA, TSR, VRU); ?- synergies and complementary actions with on-going and new projects in FP7 on road safety. The innovations claimed are: ?- wide dynamic range and wide spectral response InGaAs focal plane array; ?- collective process for hybridisation, including the substrate removal step, of InGaAs arrays on silicon read-out circuit; -? use of wide spectral band cameras in safety applications; ?- cost-effective large spectrum plastic lenses; ?- road status monitoring for preventive and active safety

Keywords: road status monitoring,multifunctional sensors,infra-red imaging
Access to ICT Investors (ACCESS-ICT)

Framework: FP7 — Cooperation
Programme: Information and Communication Technologies
Destination: Horizontal support actions
Action type: Coordination and support actions
Countries involved: Belgium,United Kingdom,United Kingdom
Call:  (FP7-ICT-2009-4, 2009)
Start date: 2010-02-01
End date: 2012-06-30
Duration (months): 29.0
Total project cost (EUR): 440000.0
EU funding (EUR): 397750.0
Participants: 3
Project status: CLOSED

ACCESS-ICT will address the current challenges related to access to finance for ICT SMEs involved in Framework programmes by providing a sustainable platform offering access to awareness raising solutions through to case by case introductions of SMEs to investment opportunities across Europe. This will be achieved by way of both investment readiness and access to finance tools tailored to the needs of theses SMEs. This platform is driven by the investment community, aiming to involve representatives from the financing world during the development of the tools and delivery of hands on mentoring support and in directly funding investment ready companies. The project will act as a hub between SMEs looking for access to investment and early stage and later stage investors (comprising business angels, venture capital firms and corporate investors) interested in the great potential represented by those SMEs with a strong R&amp;D focus and beneficiaries of European public support. The objective of ACCESS-ICT is to build a sustainable pan-European network of ICT investors, which will be linked both to representatives of SMEs but also of research organisations and various stakeholders who operate across Europe in favour of the development of R&amp;D and commercialisation of R&amp;D for ICT SMEs. At the end of the project, this platform will consist of a live network of various investors, supported by an online web-platform including tools and solutions for those to have sustainable access to information about SME companies from Framework Programme projects. While access to finance will be the ultimate objective for the most promising companies, ACCESS-ICT through a mapping exercise conducted at the outset of the project will be able to implement both awareness raising activities for relevant SMEs representative groups as well as provide investment readiness to those companies who satisfy different investors criteria in terms of product, market, growth potential, and funding needs.

Keywords: access to finance - interface - capacity building - investment readiness - network of ict investors.
Nanoscale Silicon-Aware Network-on-Chip Design Platform (NANOC)

Framework: FP7 — Cooperation
Programme: Information and Communication Technologies
Destination: Components, systems, engineering
Action type: Collaborative project
Countries involved: Spain,Italy,Germany,Norway,Denmark,Switzerland
Call:  (FP7-ICT-2009-4, 2009)
Start date: 2010-01-01
End date: 2012-12-31
Duration (months): 36.0
Total project cost (EUR): 4117601.0
EU funding (EUR): 2925000.0
Participants: 8
Project status: CLOSED

The NaNoC project aims at developing an innovative design platform for future Network-on-Chip (NoC) based multi-core systems. This NaNoC design platform intends to master the design complexity of advanced microelectronic systems by enabling strict component oriented architectural design. A compositional approach to NoC design in future multi-core chips is out of the reach of current design methods and tools due to new design constraints. Requirements for co-design with high-level platform management frameworks facilitates a need for enhanced dynamism and flexibility in NoC composition (e.g., virtualization, power management, thermal management, application management). On the other hand, a higher degree of uncertainty originating from nanoscale IC fabrication technologies raises the need to build reliable systems out of unreliable components. The NaNoC design platform provides design methods and prototype tools to cope with both challenges and to make NoCs a mainstream interconnect backbone for effective system integration. The platform enables NoC component assembly at each layer of the design hierarchy. Therefore, design for manufacturability techniques and tools are developed to preserve yield in the presence of manufacturing defects and circuit performance/power variability. Above all, the NaNoC design platform fosters the tight cooperation between system research, circuit design and process development by means of a silicon-aware decision making at each layer of the design hierarchy. In this direction, NaNoC not only provides a cross-layer approach to tackle composability challenges (e.g., physical design techniques for enhanced reliability combined with architecture-level techniques for fault containment), but also defines an exchange format for interoperability between design tools for cross-layer optimization. Interoperability between developed NoC design methods/prototype tools and mainstream design toolflows will also be pursued.

Keywords: networks-on-chip,design platform,multi-core systems,system integration,fault-tolerance,virtualization
Rendering FPGAs to Multi-Core Embedded Computing (REFLECT)

Framework: FP7 — Cooperation
Programme: Information and Communication Technologies
Destination: Components, systems, engineering
Action type: Collaborative project
Countries involved: Czechia,Portugal,Netherlands,Germany,United Kingdom,Netherlands
Call:  (FP7-ICT-2009-4, 2009)
Start date: 2010-01-01
End date: 2012-12-31
Duration (months): 36.0
Total project cost (EUR): 3703578.0
EU funding (EUR): 2719999.0
Participants: 9
Project status: CLOSED

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) makes them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved at an unreasonably high effort. This project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented (AO) Specifications to covey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development and portability. We leverage AO specifications and a set of transformations to generate an intermediate representation using an extensible mapping language (LARA). LARA specifications will allow the exploration of alternative architectures and run-time adaptive strategies enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio/video processing and real-time avionics. We expect the technology developed here to be integrated by our industrial partners, a leading compilation tool supplier for reconfigurable systems and a worldwide solution supplier of embedded high-performance systems. The academic partners will promote human resources with technical excellence in the area of architectures and software development thus enabling the sustainability of a vibrant information technology European fabric.

Keywords: reconfigurable computing systems,multi-core architectures,application-specific architectures,fpgas,reconfigurable hardware,compilers,aspect-oriented specifications
Exploring the use of subjective attributes in PIM systems design (PIM)

Framework: FP7 — People
Programme: Marie-Curie Actions
Theme: Marie Skłodowska-Curie
Destination: European Re-integration Grants
Action type: Support for training and career development of researchers (Marie Curie)
Countries involved: Israel
Call:  (FP7-PEOPLE-2009-RG, 2009)
Start date: 2010-01-01
End date: 2012-12-31
Duration (months): 36.0
Total project cost (EUR): 45000.0
EU funding (EUR): 45000.0
Participants: 1
Project status: CLOSED

Personal Information Management (PIM) is an activity whereby people store their personal information to retrieve it later. Many millions of computer users retrieve their files several times a day, so improving this process will significantly improve personal and corporate productivity. Prior work by Dr. Bergman in his initial Marie Curie Fellowship indicates users often have poor organizational strategies for personal information making retrieval difficult. This will not be addressed by improvements in desktop search, as that work revealed a strong preference for navigational access strategies using folders rather than search. However the precise relation between organization and retrieval in PIM has not been systematically studied to date. This project will therefore study the relation between organization and retrieval in PIM, to improve both. This will be achieved by performing 3 studies that move from a conceptual understanding to proposing and evaluating concrete designs that improve retrieval: The Naturalistic Study will gather large-scale quantitative data on the effects of folder structure (e.g. depth and size) on retrieval success by videoing participants navigating to their files. The Tags Study examines the effect of tag vs. folder organizational structures on retrieval, comparing organization and retrieval behavior in both environments. The User-Subjective Study tests designs to improve retrieval by evaluating prototypes which implement the user-subjective approach developed by Dr. Bergman. One of its implementations was already successfully evaluated in the initial Marie Curie Fellowship. Dr. Bergman will lead in cooperation with Prof. Bar-Ilan (Head of Information Science at the host organization), Prof. Whittaker (Head of the initial Marie Curie Fellowship, who will also audit the project) and other EU researchers. These collaborative activities will lead to community building as Dr. Bergman will propose the first EU PIM workshop at INTERACT 2012.

Keywords: human-computer interaction,personal information management,information systems,user-subjective,files,emails,favorites
Exploiting dataflow parallelism in Teradevice Computing (TERAFLUX)

Framework: FP7 — Cooperation
Programme: Information and Communication Technologies
Destination: Future and emerging technologies
Action type: Collaborative project
Countries involved: Italy,Spain,France,Spain,France,Israel,France,Germany,United Kingdom,Cyprus,United States
Call:  (FP7-ICT-2009-4, 2009)
Start date: 2010-01-01
End date: 2014-03-31
Duration (months): 51.0
Total project cost (EUR): 8207282.0
EU funding (EUR): 6120000.0
Participants: 11
Project status: CLOSED

Dataflow parallelism is key to reach power efficiency, reliability, efficient parallel programmability, scalability, data bandwidth. In this project we propose dataflow both at task level and inside the threads, to offload and manage accelerated codes, to localize the computation, for managing the fault information with appropriate protocols, to easily migrate code to the available/working components and to respect the power/performance/temperature/reliability envelope, to efficiently handle the parallelism and have an easy and powerful execution model, to produce a more predictable behavior. While parallel systems have been around for many years, they were usually programmed and tuned by experts. In the future large scale systems will be widely available and therefore exploiting efficiently the available parallelism will have to be easy enough to be accessible by the common user. Traditional programming models are either not very efficient for every application (message passing) or difficult to scale (shared memory). In order to address the programmability challenge we propose the use of a compiler directive based model to support an underlying dataflow-based thread execution that is known to exploit well the available parallelism and to efficiently move around large amounts of data. In particular we propose to use a model that offers dataflow scheduling of parallel execution threads. Combining multithreading with dataflow allows to exploit the available parallelism without the overheads of the original dataflow techniques. The multithreading dataflow model is expected to perform well for a number of classes of applications. An important contribution is provided by prof. Gao's team, who has been developing dataflow concepts for decades and has joined the TERAFLUX project after its initial phase. TERAFLUX is now bringing together top experts in dataflow in both continents Europe and Americas, with the aim to reach the higher goal of demonstrating for the first time the efficiency dataflow concept for the Exascale parallel computers of the 2020 and beyond.

Keywords: multicore,multithreading,execution model