A Highly Efficient Adaptive Multi-processor Framework (HEAP)

Framework: FP7 — Cooperation
Programme: Information and Communication Technologies
Destination: Components, systems, engineering
Action type: Collaborative project
Countries involved: Italy,Greece,France,Netherlands,Italy,Italy,Sweden,Netherlands
Call:  (FP7-ICT-2009-4, 2009)
Start date: 2010-02-01
End date: 2013-01-31
Duration (months): 36.0
Total project cost (EUR): 3319323.0
EU funding (EUR): 2216069.0
Participants: 11
Project status: CLOSED

Writing parallel programs has traditionally been considered a difficult task, even when parallelism is taken into account from the beginning. Moreover there is an urgent need to parallelize the massive amounts of legacy sequential code so as to increase its performance on processors and systems that refocus from single-thread acceleration to increasing the overall throughput. At the same time, memory (in particular cache) performance is essential to achieve the full gain from a parallelized application. However, while processor architecture tends to be relatively standard across applications within a domain, huge performance and power improvements can be achieved by tailoring the cache architecture to the application at hand, and not just to an entire domain. The HEAP project faces these challenges directly, by developing: 1. An innovative toolset that helps software developers profile and parallelize existing sequential implementations by exploiting top-level pipeline-style parallelism. 2. A highly configurable cache architecture that can be tailored to an application by using the same profiling data as those that were used for parallelization, in order to fully exploit the available computing power. In particular, the HEAP project will provide 1. a novel SMP multicore platform supporting a group of novel cache coherence protocols; each application will be profiled so as to select and tune the most appropriate cache coherency mechanism. 2. an innovative toolflow that complements this architecture; this tool will ease and/or automate the parallelisation of sequential C-code based on an analysis of the dataflow while it will provide configuration and tuning data (e.g. in terms of which variables are local, and which are mostly written or mostly read by a thread) to the cache coherency mechanisms so as to optimize them for the given application In order to increase the exploitability of the end-results, the toolflow (an incarnation of which will be also distributed in an open source manner) will be implemented in such a way that it will be able to perform sequential-to-multicore migration for any multicore architecture (not only the HEAP one). Moreover, the architecture will be capable of running multithreaded code compiled by any compiler/toolset (not only the one implemented by HEAP). However, in order to take full advantage of the HEAP results, the combined toolset and architecture should be utilized. We innovate in the first domain by using both pessimistic and optimistic estimates of the available parallelism, by refining those estimates using metric-driven verification techniques, and by supporting dynamic recovery of excessively optimistic parallelization.

Keywords: parallelizing tools,cache coherency protocols,multi-core,compilers,homogeneous systems