Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration (FASTER)

Framework: FP7 — Cooperation
Programme: Information and Communication Technologies
Destination: Alternative Paths to Components and Systems
Action type: Collaborative project
Countries involved: Greece,Sweden,United Kingdom,Italy,Belgium,Greece
Call:  (FP7-ICT-2011-7, 2011)
Start date: 2011-09-01
End date: 2014-11-30
Duration (months): 39.0
Total project cost (EUR): 3693261.0
EU funding (EUR): 2800000.0
Participants: 8
Project status: CLOSED

Extending product functionality and improving their lifetime requires additional features to satisfy the growing customer’s needs as well as new market and technology trends. For example, a network Intrusion Detection System needs to scan all incoming network packets for suspicious content. The scanning has to be at “line-speed” so that the monitored communication links are not slowed down, while the list of threats to check for is extended and updated on a daily basis. Reconfigurable logic allows the definition of new functions to be implemented and dynamically instantiated in hardware units combining hardware speed and efficiency with the ability to adapt and cope in a cost effective way with expanding functionality. For the Intrusion Detection System example, the new rules can be hardcoded into the reconfigurable logic, thus retaining the high performance, while providing the necessary adaptability and extensibility to new threats. FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) will implement a complete methodology to allow designers to easily implement and verify a system specification on a platform that includes one or more general purpose processor(s) combined with multiple acceleration modules implemented on one or multiple reconfigurable devices. To demonstrate the effectiveness of the FASTER tool chain, we will use three complex applications from different domains: (a) Reverse Time Migration (RTM), a computational seismography algorithm, (b) Global Illumination and Image Analysis, and (c) an intrusion detection system. We expect the Intrusion Detection system implemented within FASTER to be 60%-75% cheaper than the solutions offering the exact same level of performance in 2015. Similarly, the Global Illumination and Image Analysis system is expected to be more than 2x faster than the existing solutions with the same cost and/or power consumption in 3-years time, while the RTM system implemented by the FASTER tool is projected to be 50% less expensive than the offering in 3 years’ time when both, the initial purchase as well as the operating costs are taken into account. The participation of ST Microelectronics, the world’s fifth largest semiconductor company, and of Maxeler and Synelixis, two high-potential SMEs ensure that the FASTER tool flow will be designed, tested and evaluated in a close collaboration with the engineers that will eventually use it. The results of the project will strengthen the competitiveness of the project industrial beneficiaries as they will be able to deploy advanced market solutions with improved cost/performance, and due to the adaptability will have extended lifetime. The research performed by the academic beneficiaries will disseminate project results within their educational and research programs and in high-impact conferences and journals, advancing European excellence in education and research.

Keywords: customization,reconfigurable computing,multicore,fpga,cad tools,application acceleration