Venue: ICLR 2017 conference

Reviews:

final_score: rating: 5: Marginally below acceptance threshold
review_content: Summary:

The paper describes how the DaDianNao (DaDN) DNN accelerator can be improved by employing bit serial arithmetic.  They replace the bit-parallel multipliers in DaDN with multipliers that accept the weights in parallel but the activations serially (serial x parallel multipliers).  They increase the number of units keeping the total number of adders constant.  This enables them to tailor the time and energy consumed to the number of bits used to represent activations.  They show how their configuration can be used to process both fully-connected and convolutional layers of DNNs.

Strengths:

Using variable precision for each layer of the network is useful - but was previously reported in Judd (2015)

Good evaluation including synthesis - but not place and route - of the units.  Also this evaluation is identical to that in Judd (2016b)

Weaknesses:

The idea of combining bit-serial arithmetic with the DaDN architecture is a small one.

The authors have already published almost everything that is in this paper at Micro 2016 in Judd (2016b).  The increment here is the analysis of the architecture on fully-connected layers.  Everything else is in the previous publication.

The energy gains are small - because the additional flip-flop energy of shifting the activations in almost offsets the energy saved on reducing the precision of the arithmetic.

The authors don’t compare to more conventional approaches to variable precision - using bit-parallel arithmetic units but data gating the LSBs so that only the relevant portion of the arithmetic units toggle.  This would not provide any speedup, but would likely provide better energy gains than the bit-serial x bit-parallel approach.

Overall:

The Tartan and Stripes architectures are interesting but the incremental contribution of this paper (adding support for fully-connected layers) over the three previous publications on this topic, and in particular Judd (2016b) is very small.  This idea is worth one good paper, not four.
review_title: Stripes and Tartan are interesting architectures but the contribution over the three previous publications on this idea is extremely small

final_score: rating: 4: Ok but not good enough - rejection
review_content: This paper proposed a hardware accelerator for DNN. It utilized the fact that DNN are very tolerant to low precision inference and outperforms a state-of-the-art bit-parallel accelerator by 1.90x without any loss in accuracy while it is 1.17x more energy efficient. TRT requires no network retraining. It achieved super linear scales of performance with area.

The first concern is that this paper doesn't seem very well-suited to ICLR. The circuit diagrams makes it more interesting for the hardware or circuit design community. 

The second concern is the "take-away for machine learning community", seeing from the response, the take-away is using low-precision to make inference cheaper. This is not novel enough. In last year's ICLR, there were at least 4 papers discussing using low precision to make DNN more efficient. These ideas have also been explored in the authors' previous papers. 

review_title: consider a better venue for submission

final_score: rating: 6: Marginally above acceptance threshold
review_content: This seems like a reasonable study, though it's not my area of expertise. I found no fault with the work or presentation, but did not follow the details or know the comparable literature. 

There seem to be real gains to be had through this technique, though they are only in terms of efficiency in hardware, not changing accuracy on a task. The tasks chosen (Alexnet / VGG) seem reasonable. The results are in simulation rather than in actual hardware.

The topic seems a little specialized for ICLR, since it does not describe any new advances in learning or representations, albeit that the CFP includes "hardware".  I think the appeal among attendees will be rather limited. 

Please learn to use parenthetical references correctly. As is your references make reading harder. 
review_title: Improving inference speed and energy-efficiency in (simulated) hardware implementations by exploiting per-layer differences in numerical precision requirements.

final_score: rating: 5: Marginally below acceptance threshold
review_content: The authors present TARTAN, a derivative of the previously published DNN accelerator architecture: “DaDianNao”. The key difference is that TARTAN’s compute units are bit-serial and unroll MAC operation over several cycles. This enables the units to better exploit any reduction in precision of the input activations for improvement in performance and energy efficiency.

Comments:

1. I second the earlier review requesting the authors to be present more details on the methodology used for estimating energy numbers for TARTAN. It is claimed that TARTAN gives only a 17% improvement in energy efficiency. However, I suspect that this small improvement is clearly within the margin of error ij energy estimation.  

2. TARTAN is a derivative of DaDianNao, and it heavily relies the overall architecture of DaDianNao. The only novel aspect of this contribution is the introduction of the bit-serial compute unit, which (unfortunately) turns out to incur a severe area overhead (of nearly 3x over DaDianNao's compute units).

3. Nonetheless, the idea of bit-serial computation is certainly quite interesting. I am of the opinion that it would be better appreciated (and perhaps be even more relevant) in a circuit design / architecture focused venue.
review_title: Incremental, perhaps better suited for an architecture conference (ISCA/ ASPLOS)

final_score: rating: null
review_content: The paper provides insights into hardware and circuit design. My question is what is the take-away for the machine learning community? How to train such low precision networks that work well on the specialized hardware? Is there any plan to open source the modified caffe framework?

On the hardware perspective, how to justify the 1.40× increase in area to trade-off for 1.90× speedup and 1.17× energy efficiency? The energy efficiency improvement looks marginal. Does this gain come from low precision model or come from specailzied hardware?
review_title: take-away for machine learning community; source of gain

final_score: rating: null
review_content: In Section 4.1 how exactly do you determine energy?  Did you capture toggle counts for each node during simulation?  On what workload?    Did you perform place and route?  If not, how were wire loads estimated?  and how was timing closed at 980MHz without accurate wire loads?  What process corner(s) were used for timing closure and energy estimation?
review_title: Provide details of power estimation

final_score: rating: null
review_content: The paper is closely related to Judd et al 2016. How does it compare in terms of efficiency ? That comparison seems to be missing. 
The main novelty over Judd et al seems to be handling fully connected layers but recent networks have basically just convolutional layers (googlenet, resnet, etc.). Any comments on that ?
review_title: Comparison with Stripes (Judd et al 2016)

final_score: rating: 4: Ok but not good enough - rejection
review_content: I do not feel very qualified to review this paper. I studied digital logic back in university, that was it. I think the work deserves a reviewer with far more sophisticated background in this area. It certainly seems useful. My advice is also to submit it another venue.
review_title: My thoughts too

Meta-review: This metareview is written based on the reviews of the two expert reviewers (scores of 5(5), 5(5)),
 given the wide disparity of reviewer expertise, and the relevance of hardware expertise to this particular paper.
 
 Quality, Clarity: The paper is clearly written. It does require hardware expertise to read and appreciate the ideas, methodology, and the results. There was a request to post a clear "take home" message for ML research, and the authors did post a clear statement in this regard.
 
 Originality: The size of the contribution is the major point of contention for this paper. The expert reviewers believe it to be an incremental/small idea, particularly in relation to the prior work of the authors. The authors provide rebut that while the implementation builds on their previous work, it can be seen as a general concept that could be applied to other architectures, and that this work targets the important case of fully-connected architectures, vs the case of convolutional architectures that were the case where the prior work did well.
 
 Overall: I have asked the expert reviewers for further input. In the absence of further information, updated scores, or some reasonably strong indication of excitement about the ideas from the expert reviewers, there is little choice but to currently lean towards "reject" in terms of this being an inspirational paper for ICLR.
Decision: Reject