Venue: NeurIPS 2022 Conference

Reviews:

final_score: rating: 6: Weak Accept: Technically solid, moderate-to-high impact paper, with no major concerns with respect to evaluation, resources, reproducibility, ethical considerations.
review_content: summary: This paper proposed a novel graph representation: Circuit Graph, integrating the heterogeneous circuit information from logic synthesis and placement to facilitate the EDA design process. The proposed graph structure considers both topological (cell connection in the netlist) and geometric information (positioning of the standard cells on the layout). A corresponding graph neural network (GNN) structure is proposed for extracting circuit representation for various downstream tasks. The experimental results demonstrated the effectiveness of the graph in congestion and net wirelength prediction tasks with efficient NN computation.
strengths_and_weaknesses: Strengths:
1. Heterogeneous information fusion across multiple EDA design stages. Typically, circuit designs are divided into multiple phases. Each phase may have its own unique representation for the same underlying circuit. The proposed circuit graph brings two representations (netlist and cell placement) into a unified graph representation, which provided a more informative data structure embedding knowledge from multiple EDA design phases.
1. The proposed circuit graph is general enough to be extended to inspire future work. The paper only touches on congestion and net wirelength prediction tasks for detailed routing, and the graph featurization contains only related basic topology information and simple geometric information. The reviewer believes the proposed graph can inspire more work in EDA areas. For example, by adding standard cell delay as one new feature in the cell node, the proposed graph may also help with the timing analysis of the circuit.
1. The overall GNN structure follows the design of the circuit graph, which sounds promising. The topological and geometric message passing structures preserve the structure of the original circuit graph, 

Weaknesses:
1. The paper didn't touch on how representative the extracted GNN features are. The two tasks (congestion prediction and net wirelength prediction) in the paper are experimented independently. Although these two tasks have different readouts, they shared the same input graph features and extract GNN feature representation. It would be interesting to check if the knowledge can be transferred from one task to another using the proposed GNN.
1. Although the overall GNN structure sounds promising, some detailed formulation or design choice of GNN needs to be further justified. Detailed comments are made in the questions.
questions: 1. The reviewer wonders if the authors can make comments about how transferrable the proposed GNN features are.
1. The authors claimed the proposed GNN is very efficient in terms of computation. To be used in practical cases, the time consumed in training and inference of GNN should be compared with the traditional EDA routing tool. Some simple statistics over this can help justify the actual impact of the usage in EDA.
1. Detailed GNN formulation question 1): In equation 5, a matrix $W_{\varepsilon^T\rightarrow\mathcal{U}}$ is used in topological message passing, and in equation 7, a vector $a$ is used in the geometric message passing. What is the consideration underneath the difference here?
1. Detailed GNN formulation question 2): To fuse the topological and geometrical messages, maxpooling is used (equation 3). What is the underlying thought process to use maxpooling for fusion, and what may be the effect of other fusion methods (e.g. adding, concatenation, averagepooling)?
1. Detailed GNN formulation question 3): The readout for cell and net also include the raw features. The reviewer wonders how important those raw features are. If excluding them from the readout results in significant performance drops, the usefulness of the extracted GNN representation should be questioned. 
limitations: The paper mentioned that one limitation is to test the proposed method under commercial products and more complex scenarios. The reviewer appreciate that the authors bring up this and understand the difficulty behind it.
review_title: null

final_score: rating: 6: Weak Accept: Technically solid, moderate-to-high impact paper, with no major concerns with respect to evaluation, resources, reproducibility, ethical considerations.
review_content: summary: This work constructs a modeling framework that aims to solve various problems in the circuit design process. This work incorporates 
1. A novel circuit graph that is able to jointly integrate the topological and geometrical information and is claimed to be the first unified circuit representation approach that can be easily compatible across EDA tasks and stage.
2. A novel message-passing paradigm, CircuitGNN, that is tailored towards the aforementioned graph dataset structure. The structure can conduct message-passing on both topological and geometrical edges distinctively and then fuse the messages to update cells and nets representations
3. Extensive experiments validates the merits of the proposed methods in terms of both the task accuracy and execution speeds.
strengths_and_weaknesses: Strength:
1. This work does a good job on analyzing and illustrating the tasks and problems of circuit EDA in light of the machine learning methods.
2. The methodology is described in much detailed but straight-forward way.
3. Overall this work provides decent improvements over the existing methods. Just per the results alone, it is impressive.
4. The code provided in the supplementary materials is certainly a plus, contributing to the transparency and reproduction of the works in the fields.

Weakness:
1. Apart from the improvements on the message passing methods, one of the key contributions of this work is to be able to jointly integrate the topo and geom information in one model. However, I do not see clearly the motivation for this point from both the application and results perspectives. For actual application, is there a significant disadvantage of simply using two sets of models or even methods respectively for logical synthesis and place-and-routing? One of the reasons, I would perceive, is that a joint model may yield a better task performance due to the complementary information. However, as Table 2 suggests, the joint model's improvements against the proposed method with only geom message passing.
questions: 1. Would be great to provide more summarized details on the proposed models and the baselines in terms of the number of parameters and operations and their types.
limitations: Yes, it's addressed.
review_title: null

final_score: rating: 6: Weak Accept: Technically solid, moderate-to-high impact paper, with no major concerns with respect to evaluation, resources, reproducibility, ethical considerations.
review_content: summary: The authors propose a unified way to construct graphs in different phases of EDA flow, and develop a general GNN model for downstream EDA tasks. Specifically, the proposed approach first constructs a heterogeneous graph by incorporating cell-cell connections (geometrical information) and cell-net connections (topological information). The node and edge features are generated based on physical properties of cells, pins, and nets. Then, a circuit GNN model is proposed to apply message passing on cell-cell and cell-net connections separately, which produces the representations of cells and nets for downstream tasks. The experimental results show that the proposed method increases 16.7% accuracy on congestion prediction and reduces 16.9% error on wirelength prediction.
strengths_and_weaknesses: **Key Strength**

  - The paper is clearly written. All the technical steps are easy to follow.
  - The proposed method can be used to solve multi-stage EDA tasks.
  

**Key Weakness**

Although the proposed circuit graph construction and GNN model are all reasonable, they lack some technical significance. For example,
  - For circuit graph construction, it is straightforward to construct a bipartite graph based on cell-net connections from netlist, in order to produce representations of cells and nets for downstream tasks. Hence, the contribution is limited for the graph construction, especially in logic synthesis stage where placement information is not available.
  - For GNN model, it is a common way to apply message passing individually per edge type for handling heterogeneous graphs (e.g., [2]). Thus, the novelty of the proposed model is limited.
  

Although the experiments show promising accuracy gains for downstream EDA tasks, further clarification could make the improvements more convincing:
  - Missing strong GNN baselines: The chosen baselines (i.e., GCN, GraphSAGE, and GAT) only consider node features. Since edge features are important in this paper, authors should compare the proposed model against stronger baselines (e.g., MPNN[1]) that incorporate edge features, on the same input graph. Without a stronger baseline, the contribution of the proposed GNN model is unclear.
  - Not tuning hyperparameters for baselines: Authors choose the default hyperparameters for baselines from their original papers. Since the datasets used in those papers (e.g., [3]) are different from this paper, hyperparameter tuning is necessary.
  - Not comparing against DREAMPlace: The purpose of wirelength prediction is to speedup EDA design closure. Nonetheless, there are no results of the runtime comparison between the proposed model and the placement method DREAMPlace, which is a very fast placement method by exploiting GPUs. Without this comparison, it's unclear about the motivation of wirelength prediction in placement.

[1]: Gilmer et al. "Neural message passing for quantum chemistry." ICML'17. \
[2]: Zhang et al. "Heterogeneous graph neural network." KDD'19. \
[3]: Xie et al. "Pre-Placement Net Length and Timing Estimation by Customized Graph Neural Network." TCAD'22.
questions:   - For the wirelength prediction task in placement stage, authors use DREAMPlace to generate both the ground truth and node/edge features. If the ground truth is already known, why does it even need to generate features for GNN?
  - Is there any reason/insight why two different message-passing functions are used for topo-edges (Equation 5) and geom-edges (Equation 7)?
  - Apart from logic synthesis and placement, how does the proposed work incorporate graphs in other EDA stages (e.g., data-flow graph in high-level synthesis)?
  - Is it necessary to have geom-edges? Can we encode the cell positions into node feature vectors instead?
limitations: Thanks authors for mentioning potential limitations of this work. One key challenge of deploying ML models into commercial EDA tools is the model generalizability. Authors can evaluate the trained model on more unseen designs to see if it is truly generalizable.
review_title: null

Meta-review: metareview: This paper proposes a GNN approach to EDA using the construction of a circuit graph that combines geometric and topological information, as well as features generated from physical properties of circuit components. While reviewers have raised certain concerns (some addressed already in rebuttal), they all settled (post rebuttal) on recommending weak accept of the paper. I agree with them and think the NeurIPS audience would benefit from the inclusion of this work in the program, and therefore I recommend acceptance. I would like to encourage the authors to take into account the comments and discussion with the reviewers, as well as incorporate materials presented in their responses, when preparing the camera ready version.
confidence: Certain
Decision: Accept