A COMBINED APPROACH TO CREATING MODELS FOR H-TYPE TRANSISTORS MADE USING 0.18 MICRON SOI TECHNOLOGY
Journal: International Forum “Microelectronics – 2020”. Joung Scientists Scholarship “Microelectronics – 2020”. XIII International conference «Silicon – 2020». XII young scientists scholarship for silicon nanostructures and devices physics, material science, process and analysis
Year: 2020

A technique has been developed for extracting the parameters of a compact H-transistor model based on BSIMSOI 4.5, taking into account parasitic capacitances, and also using the binning approach to take into account the non-standard dependence of the I–V characteristic on the geometrical dimensions of the transistor.