title: Iselin Solheim

text: Iselin Løken Solheim was born in Naustdal, located in Sogn og Fjordane, Norway and started singing at a young age. In 2007 she participated in the Norwegian version of Pop Idol named "Idol - Jakten på en superstjerne", where she placed in the top 40. In 2009, after high school she attended kiringssal Folkehøgskule in Sandefjord, where she mainly studied music and then began writing her own songs. In 2010, she attended The Institute for Performing Arts in Liverpool, where she studied "Popularize Music & Sound Technology". Here she developed as an artist and performer, starting with new projects and cultivating her own sounds.


title: Iselin Solheim

text: After returning to Norway from the United Kingdom, Bisi Music signed her immediately. She then released her well-received debut single "What's Happening", which received wide airplay and was selected "Song of the Week" for the national radio station Radio Norge. At that time Solheim met Jesper Borgen together with her former manager Hilde Wahl from Bisi Music to test out a new partnership. They later on wrote the text, melody and produced the song "The Wizard of Us" and "Oracle" together in 2013. Her next single "Giants" was released in 2015.


title: Iselin Solheim

text: In late 2015 and early 2016, she lent uncredited vocals on Alan Walker's songs "Faded" and "Sing Me to Sleep".


title: Iselin Solheim

text: She then released her next single "Lost" in September and an acoustic version in October 2018. "Anyone Out There" was released in February 2019.


title: Iselin Solheim

text: Felix Cartal's single "Walking By" (2018), Gryffin's single "Just for a Moment" (2018) and 3LAU & Justin Caruso's single "Better With You" (2019) all featured Solheim.


title: Iselin Solheim

text: Solheim has also co-written songs for, among others, R3hab, Matoma, SKAAR, Inna, Broiler, James Carter, and Martin Tungevaag.


title: Floating production storage and offloading

text: A floating production storage and offloading (FPSO) unit is a floating vessel used by the offshore oil and gas industry for the production and processing of hydrocarbons, and for the storage of oil. An FPSO vessel is designed to receive hydrocarbons produced by itself or from nearby platforms or subsea template, process them, and store oil until it can be offloaded onto a tanker or, less frequently, transported through a pipeline. FPSOs are preferred in frontier offshore regions as they are easy to install, and do not require a local pipeline infrastructure to export oil. FPSOs can be a conversion of an oil tanker (like the "Seawise Giant") or can be a vessel built specially for the application. A vessel used only to store oil (without processing it) is referred to as a floating storage and offloading (FSO) vessel.


text: A floating storage and offloading unit (FSO) is essentially a FPSO without the capability for oil or gas processing. Most FSOs are converted single hull supertankers. An example is "Knock Nevis", ex "Seawise Giant", which for many years was the world's largest ship. It was converted into an FSO for offshore use before being scrapped.


text: At the other end of the LNG logistics chain, where the natural gas is brought back to ambient temperature and pressure, a specially modified ship may also be used as a floating storage and regasification unit (FSRU). A LNG floating storage and regasification unit receives liquefied natural gas (LNG) from offloading LNG carriers, and the onboard regasification system provides natural gas exported to shore through risers and pipelines. , there are 33 FSRUs in the world, of which some relocate to higher-priced areas.


text: Oil has been produced from offshore locations since the late 1940s. Originally, all oil platforms sat on the seabed, but as exploration moved to deeper waters and more distant locations in the 1970s, floating production systems came to be used.


text: The first oil FPSO was built in 1977 on the Shell Castellon field, located in the Spanish Mediterranean. Today, over 270 vessels are deployed worldwide as oil FPSOs.


text: On July 29, 2009, Shell and Samsung announced an agreement to build up to 10 LNG FPSOs, at the same Samsung Yard. Flex LNG appeared to construct smaller units.


text: On May 20, 2011, Royal Dutch Shell announced the planned development of a 488 m long and 74 m wide floating liquefied natural gas facility (FLNG), called Prelude, which is to be situated 200 km off the coast of Western Australia and is due for completion in around 2016. It will be the largest vessel ever built. Royal Dutch Shell (2013), LNG FPSO (Liquefied Natural Gas Floating production Storage and Offloading), Samsung Heavy Industries at a cost of $12 Billion.


text: In June 2012, Petronas made a contract of procurement engineering, construction, installation and commissioning, with the Technip and DSME consortium, for what is expected to be the world's first floating liquefaction unit when completed in 2015. The unit is destined for the Kanowit gas field off Sarawak, Malaysia.


text: At the opposite (discharge and regasification) end of the LNG chain, the first ever conversion of an LNG carrier, Golar LNG owned Moss type LNG carrier into an LNG floating storage and regasification unit was carried out in 2007 by Keppel shipyard in Singapore.


text: Oil produced from offshore production platforms can be transported to the mainland either by pipeline or by tanker. When a tanker is chosen to transport the oil, it is necessary to accumulate oil in some form of storage tank, such that the oil tanker is not continuously occupied during oil production, and is only needed once sufficient oil has been produced to fill the tanker.


text: Floating production, storage and offloading vessels are particularly effective in remote or deep water locations, where seabed pipelines are not cost effective. FPSOs eliminate the need to lay expensive long-distance pipelines from the processing facility to an onshore terminal. This can provide an economically attractive solution for smaller oil fields, which can be exhausted in a few years and do not justify the expense of installing a pipeline. Once the field is depleted, the FPSO can be moved to a new location.


text: New build FPSOs have a high initial cost (up to USD1 billion), but require limited maintenance. In addition, the ability to reposition/repurpose them means they can outlast the life of the production facility by decades. A cheaper alternative for smaller platforms is to convert an oil tanker or similar vessel at a cost below USD100 million.


text: The FPSO operating in the deepest waters is the FPSO "BW Pioneer", built and operated by BW Offshore on behalf of Petrobras Americas INC. The FPSO is moored at a depth of 2,600 m in Block 249 Walker Ridge in the US Gulf of Mexico and is rated for . The EPCI contract was awarded in October 2007 and production started in early 2012. The FPSO conversion was carried out at "MMHE Shipyard Pasir Gudang" in Malaysia, while the topsides were fabricated in modules at various international vendor locations. The FPSO has a disconnectable turret (APL) The vessel can disconnect in advance of hurricanes and reconnect with minimal down time. A contract for an FPSO to operate in even deeper waters (2,900 m) for Shell's Stones field in the US Gulf of Mexico was awarded to SBM Offshore in July 2013.


text: One of the world's largest FPSO is the "Kizomba A", with a storage capacity of . Built at a cost of over US$ 800 million by Hyundai Heavy Industries in Ulsan, Korea, it is operated by Esso Exploration Angola (ExxonMobil). Located in 1200 meters (3,940 ft) of water at Deep water block 200 statute miles (320 km) offshore from Angola, Central Africa in the Atlantic Ocean, it weighs 81,000 tonnes and is 285 meters long, 63 meters wide, and 32 meters high (935 ft by 207 ft by 105 ft).


text: The first FSO in the Gulf of Mexico, The FSO "Ta'Kuntah", has been in operation since August 1998. The FSO, owned and operated by MODEC, is under a service agreement with "PEMEX" Exploration and Production. The vessel was installed as part of the Cantarell Field Development. The field is located in the Bay of Campeche, offshore Mexico's Yucatán peninsula. It is a converted ULCC tanker with a SOFEC external turret mooring system, two flexible risers connected in a lazy-S configuration between the turret and a pipeline end manifold (PLEM) on the seabed, and an offloading system that allows up to two tankers at a time to moor and load, in tandem or side by side. The FSO is designed to handle with no allowance for downtime.


text: The Skarv FPSO, developed and engineered by "Aker Solutions" for "BP Norge", is one of the most advanced and largest FPSO deployed in the Norwegian Sea, offshore Mid Norway. "Skarv" is a gas condensate and oil field development. The development ties in five sub-sea templates, and the FPSO has capacity to include several smaller wells nearby in the future. The process plant on the vessel can handle about of gas and of oil. An 80 km gas export pipe ties into Åsgard transport system. "Aker Solutions" (formerly Aker Kvaerner) developed the front-end design for the floating production facility as well as the overall system design for the field and preparation for procurement and project management of the total field development. The hull is an Aker Solutions proprietary "Tentech975" design. BP also selected Aker Solutions to perform the detail engineering, procurement and construction management assistance (EPcma) for the Skarv field development. The "EPcma" contract covers detail engineering and procurement work for the FPSO topsides as well as construction management assistance to BP including hull and topside facilities. The production started in field in August 2011. BP awarded the contract for fabrication of the "Skarv" FPSO hull to "Samsung Heavy Industries" in South Korea and the Turret contract to SBM. The FPSO has a length of 292 m, beam of 50.6 m and is 29 m deep, accommodates about 100 people in single cabins. The hull is delivered in January 2010.


title: Moustapha Akkad

text: Moustapha Al Akkad (; July 1, 1930 – November 11, 2005) was a Syrian-American film producer and director, best known for producing the original series of "Halloween" films and directing "The Message" and "Lion of the Desert". He was killed along with his daughter Rima Al Akkad Monla in the 2005 Amman bombings.


title: Moustapha Akkad

text: Al Akkad was born on July 1, 1930 in Aleppo in the French Mandate for Syria and the Lebanon. He received his high school degree from the Aleppo American College. His father, then a customs officer, gave him $200 and a copy of the Quran before he left for the United States to study film direction and production at the University of California, Los Angeles (UCLA). Akkad spent a further three years studying for a Master's degree at the University of Southern California (USC), where he met the director Sam Peckinpah. Peckinpah became Akkad's mentor in Hollywood and hired him as a consultant for a film about the Algerian War that never made it to the big screen, but he continued to encourage him until he found a job as a producer at CBS.


title: Moustapha Akkad

text: In 1976, he produced and directed "Mohammad, Messenger of God" (released as "The Message" in 1977 in the United States), starring Anthony Quinn and Irene Papas. Akkad faced resistance from Hollywood, which forced him to make the film in Morocco.


title: Moustapha Akkad

text: While creating "Muhammad, Messenger of God", he consulted Islamic clerics, he wanted and tried to be respectful towards Islam and its views on portraying Muhammad. He got the Approval from Al-Azhar University in Egypt but was rejected by the Muslim World League in Mecca, Saudi Arabia. The Governments of Kuwait, Libya and Morocco promised to support the film financially, and when it was rejected by the Muslim World League, Kuwait kept its financial support but stopped other kinds of supports. King Hassan II of Morocco gave his full support for the production of the film. The production took one year, Akkad filmed for 6 months in Morocco, but had to stop when the Saudi Government exerted great pressure on the government of Morocco to stop the production. Akkad went to Muammar Gaddafi of Libya for support in order to complete the project, Gaddafi allowed him to move the filming to Libya for the remaining 6 months until the film was finalized.


title: Moustapha Akkad

text: Akkad saw the film as a way to bridge the gap between the Western and Muslim worlds, stating in a 1976 interview:


title: Moustapha Akkad

text: In 1978, he helped make low-budget film history when he produced "Halloween". Akkad became best known for his key involvement in the first eight "Halloween" films, as an executive producer (the only producer to participate in all of these films). The series was highly profitable and hugely influential to subsequent horror films.


title: Moustapha Akkad

text: In 1980 he directed "Lion of the Desert", in which Quinn and Irene Papas were joined by Oliver Reed, Rod Steiger, and John Gielgud. It was about the real-life Bedouin leader Omar Mukhtar (Quinn), who fought Benito Mussolini's Italian troops in the deserts of Libya. The movie is now critically acclaimed, after initially receiving negative publicity in the West for being partially funded by Libya's Muammar Gaddafi, who invested $35 million in the movie. This negative publicity may have been the cause of its relatively poor performance at the box office. Clint Morris describes the movie as: "A grand epic adventure that'll stand as a highpoint in the producing career of Moustapha Akkad." In 1985, his production company Trancas International Films had inked an agreement with Galaxy International releasing in order to release films for a seven-picture agreement worldwide.


title: Moustapha Akkad

text: In the United Kingdom, Akkad once tried to buy Pinewood Studios from The Rank Organisation and also had a studio at Twickenham. At the time of his death, he was in the process of producing an $80 million movie featuring Sean Connery about Saladin and the Crusades, for which he already had the script, that would be filmed in Jordan. Speaking of the film, he said:


title: Moustapha Akkad

text: Akkad and his 34-year-old daughter, Rima Akkad Monla, were killed in the 2005 Amman bombings. They were both in the lobby at the Grand Hyatt Amman on 9 November when a bomb exploded; his daughter died instantly, and Akkad died of his injuries two days later in a hospital. He is buried in the Al-Jadidah Cemetery in Aleppo in Syria.


title: Moustapha Akkad

text: Akkad was survived by his former wife, Patricia Al Akkad and their sons, Taric and Malek, who helped produce most of the "Halloween" movies, as well as his widow, Suha Ascha Akkad, and their son Zade.


title: Moustapha Akkad

text: He was honoured by his native city of Aleppo, and the Aleppo City Council has renamed a school and a street after Moustapha Akkad. In 2008, a street in downtown Beirut was renamed after Moustapha Akkad. The 2007 remake of "Halloween" was dedicated to Moustapha Akkad. The 2018 film "Halloween", a direct sequel to the 1978 original film, also features a dedication to Akkad in the end credits.


title: Jeff Beck discography

text: This is the discography for Jeff Beck, an English rock guitarist who has played with multiple groups including: the Yardbirds, the Jeff Beck Group and Beck, Bogert & Appice. Beck has released numerous studio, live, compilation, video and soundtrack albums during his career, as well as over twenty singles.


Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.


title: Synchronous dynamic random-access memory

text: DRAM integrated circuits (ICs) produced from the early 1970s to early 1990s used an "asynchronous" interface, in which input control signals have a direct effect on internal functions only delayed by the trip across its semiconductor pathways. SDRAM has a "synchronous" interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by JEDEC, the clock signal controls the stepping of an internal finite-state machine that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called "banks", allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an interleaved fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.


text: Pipelining means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.


text: The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.


text: The first commercial SDRAM was the Samsung KM48SL2000 memory chip, which had a capacity of 16Mbit. It was manufactured by Samsung Electronics using a CMOS (complementary metal–oxide–semiconductor) fabrication process in 1992, and mass-produced in 1993. By 2000, SDRAM had replaced virtually all other types of DRAM in modern computers, because of its greater performance.


text: SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous burst EDO DRAM due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective bandwidth.


text: Today, virtually all SDRAM is manufactured in compliance with standards established by JEDEC, an electronics industry association that adopts open standards to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for DDR, DDR2 and DDR3 SDRAM.


text: Double data rate SDRAM, known as DDR SDRAM, was first demonstrated by Samsung in 1997. Samsung released the first commercial DDR SDRAM chip (64Mbit) in June 1998, followed soon after by Hyundai Electronics (now SK Hynix) the same year.


text: SDRAM is also available in registered varieties, for systems that require greater scalability such as servers and workstations.


text: Today, the world's largest manufacturers of SDRAM include: Samsung Electronics, SK Hynix, Micron Technology, and Nanya Technology.


text: There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM (1 MHz = formula_1 Hz) to 5 ns for DDR-400, but has remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.


text: Another limit is the CAS latency, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.


text: In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.


text: SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 - although the actual meaning of the numbers has changed).


text: All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly active low, which are sampled on the rising edge of the clock:


text: SDRAM devices are internally divided into either two, four or eight independent internal data banks. One to three bank address inputs (BA0, BA1 and BA2) are used to select which bank a command is directed toward.


text: Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.


text: For example, a '512 MB' SDRAM DIMM (which contains 512 MB), might be made of eight or nine SDRAM chips, each containing 512 Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM "chip" internally contains four independent 16 MB memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (2048 8-bit columns). A bank is either idle, active, or changing from one to the other.


text: The "active" command activates an idle bank. It presents a two-bit bank address (BA0–BA1) and a 13-bit row address (A0–A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of refreshing the dynamic (capacitive) memory storage cells of that row.


text: Once the row has been activated or "opened", "read" and "write" commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or t before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an "active" command, and a "read" or "write" command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.


text: Both "read" and "write" commands require a column address. Because each chip accesses eight bits of data at a time, there are 2,048 possible column addresses thus requiring only 11 address lines (A0–A9, A11).


text: When a "read" command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock a few clock cycles later, depending on the configured CAS latency. Subsequent words of the burst will be produced in time for subsequent rising clock edges.


text: A "write" command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines. This can be done by waiting until a read burst has finished, by terminating a read burst, or by using the DQM control line.


text: When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, t, which must elapse before that row is fully "closed" and so the bank is idle in order to receive another activate command on that bank.


text: Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time t delay between an "active" command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance.


text: The no operation command is always permitted, while the load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect. The auto refresh command also requires that all banks be idle, and takes a refresh cycle time t to return the chip to the idle state. (This time is usually equal to t+t.) The only other command that is permitted on an idle bank is the active command. This takes, as mentioned above, t before the row is fully open and can accept read and write commands.


text: When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge. Read and write commands begin bursts, which can be interrupted by following commands.


text: A read, burst terminate, or precharge command may be issued at any time after a read command, and will interrupt the read burst after the configured CAS latency. So if a read command is issued on cycle 0, another read command is issued on cycle 2, and the CAS latency is 3, then the first read command will begin bursting data out during cycles 3 and 4, then the results from the second read command will appear beginning with cycle 5.


text: If the command issued on cycle 2 were burst terminate, or a precharge of the active bank, then no output would be generated during cycle 5.


text: Although the interrupting read may be to any active bank, a precharge command will only interrupt the read burst if it is to the same bank or all banks; a precharge command to a different bank will not interrupt a read burst.


text: Interrupting a read burst by a write command is possible, but more difficult. It can be done if the DQM signal is used to suppress output from the SDRAM so that the memory controller may drive data over the DQ lines to the SDRAM in time for the write operation. Because the effects of DQM on read data are delayed by two cycles, but the effects of DQM on write data are immediate, DQM must be raised (to mask the read data) beginning at least two cycles before write command but must be lowered for the cycle of the write command (assuming the write command is intended to have an effect).


text: Doing this in only two clock cycles requires careful coordination between the time the SDRAM takes to turn off its output on a clock edge and the time the data must be supplied as input to the SDRAM for the write on the following clock edge. If the clock frequency is too high to allow sufficient time, three cycles may be required.


text: If the read command includes auto-precharge, the precharge begins the same cycle as the interrupting command.


text: A modern microprocessor with a cache will generally access memory in units of cache lines. To transfer a 64-byte cache line requires eight consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by configuring the SDRAM chips, using the mode register, to perform eight-word bursts. A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first. ("Word" here refers to the width of the SDRAM chip or DIMM, which is 64 bits for a typical DIMM.) SDRAM chips support two possible conventions for the ordering of the remaining words in the cache line.


text: Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a four-word burst access to any column address from four to seven will return words four to seven. The ordering, however, depends on the requested address, and the configured burst type option: sequential or interleaved. Typically, a memory controller will require one or the other. When the burst length is one or two, the burst type does not matter. For a burst length of one, the requested word is the only word accessed. For a burst length of two, the requested word is accessed first, and the other word in the aligned block is accessed second. This is the following word if an even address was specified, and the previous word if an odd address was specified.


text: For the sequential burst mode, later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of four, and a requested column address of five, the words would be accessed in the order 5-6-7-4. If the burst length were eight, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length. The interleaved burst mode computes the address using an exclusive or operation between the counter and the address. Using the same starting address of five, a four-word burst would return words in the order 5-4-7-6. An eight-word burst would be 5-4-7-6-1-0-3-2. Although more confusing to humans, this can be easier to implement in hardware, and is preferred by Intel for its microprocessors.


text: If the requested column address is at the start of a block, both burst modes (sequential and interleaved) return data in the same sequential sequence 0-1-2-3-4-5-6-7. The difference only matters if fetching a cache line from memory in critical-word-first order.


text: Single data rate SDRAM has a single 10-bit programmable mode register. Later double-data-rate SDRAM standards add additional mode registers, addressed using the bank address pins. For SDR SDRAM, the bank address pins and address lines A10 and above are ignored, but should be zero during a mode register write.


text: The bits are M9 through M0, presented on address lines A9 through A0 during a load mode register cycle.


text: Later (double data rate) SDRAM standards use more mode register bits, and provide additional mode registers called "extended mode registers". The register number is encoded on the bank address pins during the load mode register command. For example, DDR2 SDRAM has a 13-bit mode register, a 13-bit extended mode register No. 1 (EMR1), and a 5-bit extended mode register No. 2 (EMR2).


text: It is possible to refresh a RAM chip by opening and closing (activating and precharging) each row in each bank. However, to simplify the memory controller, SDRAM chips support an "auto refresh" command, which performs these operations to one row in each bank simultaneously. The SDRAM also maintains an internal counter, which iterates over all possible rows. The memory controller must simply issue a sufficient number of auto refresh commands (one per row, 8192 in the example we have been using) every refresh interval (t = 64 ms is a common value). All banks must be idle (closed, precharged) when this command is issued.


text: As mentioned, the clock enable (CKE) input can be used to effectively stop the clock to an SDRAM. The CKE input is sampled each rising edge of the clock, and if it is low, the following rising edge of the clock is ignored for all purposes other than checking CKE. As long as CKE is low, it is permissible to change the clock rate, or even stop the clock entirely.


text: If CKE is lowered while the SDRAM is performing operations, it simply "freezes" in place until CKE is raised again.


text: If the SDRAM is idle (all banks precharged, no commands in progress) when CKE is lowered, the SDRAM automatically enters power-down mode, consuming minimal power until CKE is raised again. This must not last longer than the maximum refresh interval t, or memory contents may be lost. It is legal to stop the clock entirely during this time for additional power savings.


text: Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference.


text: SDRAM designed for battery-powered devices offers some additional power-saving options. One is temperature-dependent refresh; an on-chip temperature sensor reduces the refresh rate at lower temperatures, rather than always running it at the worst-case rate. Another is selective refresh, which limits self-refresh to a portion of the DRAM array. The fraction which is refreshed is configured using an extended mode register. The third, implemented in Mobile DDR (LPDDR) and LPDDR2 is "deep power down" mode, which invalidates the memory and requires a full reinitialization to exit from. This is activated by sending a "burst terminate" command while lowering CKE.


text: DDR SDRAM employs prefetch architecture to allow quick and easy access to multiple data words located on a common physical row in the memory.


text: The prefetch architecture takes advantage of the specific characteristics of memory accesses to DRAM. Typical DRAM memory operations involve three phases: bitline precharge, row access, column access. Row access is the heart of a read operation, as it involves the careful sensing of the tiny signals in DRAM memory cells; it is the slowest phase of memory operation. However, once a row is read, subsequent column accesses to that same row can be very quick, as the sense amplifiers also act as latches. For reference, a row of a 1 Gbit DDR3 device is 2,048 bits wide, so internally 2,048 bits are read into 2,048 separate sense amplifiers during the row access phase. Row accesses might take 50 ns, depending on the speed of the DRAM, whereas column accesses off an open row are less than 10 ns.


text: Traditional DRAM architectures have long supported fast column access to bits on an open row. For an 8-bit-wide memory chip with a 2,048 bit wide row, accesses to any of the 256 datawords (2048/8) on the row can be very quick, provided no intervening accesses to other rows occur.


text: The drawback of the older fast column access method was that a new column address had to be sent for each additional dataword on the row. The address bus had to operate at the same frequency as the data bus. Prefetch architecture simplifies this process by allowing a single address request to result in multiple data words.


text: In a prefetch buffer architecture, when a memory access occurs to a row the buffer grabs a set of adjacent data words on the row and reads them out ("bursts" them) in rapid-fire sequence on the IO pins, without the need for individual column address requests. This assumes the CPU wants adjacent datawords in memory, which in practice is very often the case. For instance, in DDR1, two adjacent data words will be read from each chip in the same clock cycle and placed in the pre-fetch buffer. Each word will then be transmitted on consecutive rising and falling edges of the clock cycle. Similarly, in DDR2 with a 4n pre-fetch buffer, four consecutive data words are read and placed in buffer while a clock, which is twice faster than the internal clock of DDR, transmits each of the word in consecutive rising and falling edge of the faster external clock


text: The prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency. In an 8n prefetch architecture (such as DDR3), the IOs will operate 8 times faster than the memory core (each memory access results in a burst of 8 datawords on the IOs). Thus a 200 MHz memory core is combined with IOs that each operate eight times faster (1600 megabits per second). If the memory has 16 IOs, the total read bandwidth would be 200 MHz x 8 datawords/access x 16 IOs = 25.6 gigabits per second (Gbit/s) or 3.2 gigabytes per second (GB/s). Modules with multiple DRAM chips can provide correspondingly higher bandwidth.


text: Originally simply known as "SDRAM", single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin DIMMs that read or write 64 (non-ECC) or 72 (ECC) bits at a time.


text: Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time.


text: Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns), respectively denoted PC66, PC100, and PC133. Clock rates up to 200 MHz were available. It operates at a voltage of 3.3 V.


text: This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate). But this type is also faster than its predecessors extended data out DRAM (EDO-RAM) and fast page mode DRAM (FPM-RAM) which took typically two or three clocks to transfer one word of data.


text: PC66 refers to internal removable computer memory standard defined by the JEDEC. PC66 is Synchronous DRAM operating at a clock frequency of 66.66 MHz, on a 64-bit bus, at a voltage of 3.3 V. PC66 is available in 168-pin DIMM and 144-pin SO-DIMM form factors. The theoretical bandwidth is 533 MB/s. (1 MB/s = one million bytes per second)


text: This standard was used by Intel Pentium and AMD K6-based PCs. It also features in the Beige Power Mac G3, early iBooks and PowerBook G3s. It is also used in many early Intel Celeron systems with a 66 MHz FSB. It was superseded by the PC100 and PC133 standards.


text: PC100 is a standard for internal removable computer random-access memory, defined by the JEDEC. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin DIMM and 144-pin SO-DIMM form factors. PC100 is backward compatible with PC66 and was superseded by the PC133 standard.


text: A module built out of 100 MHz SDRAM chips is not necessarily capable of operating at 100 MHz. The PC100 standard specifies the capabilities of the memory module as a whole.


text: PC100 is used in many older computers; PCs around the late 1990s were the most common computers with PC100 memory.


text: PC133 is a computer memory standard defined by the JEDEC. PC133 refers to SDR SDRAM operating at a clock frequency of 133 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC133 is available in 168-pin DIMM and 144-pin SO-DIMM form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1.066 GB per second ([133.33 MHz * 64/8]=1.066 GB/s). (1 GB/s = one billion bytes per second) PC133 is backward compatible with PC100 and PC66.


text: While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a double data rate interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. The DDR interface accomplishes this by reading and writing data on both the rising and falling edges of the clock signal. In addition, some minor changes to the SDR interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5 V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM.


text: DDR SDRAM (sometimes called "DDR1" for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.


text: Typical DDR SDRAM clock rates are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMs are known as PC-2100, PC-2700 and PC-3200. Performance up to DDR-550 (PC-4400) is available.


text: DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to four consecutive words. The bus protocol was also simplified to allow higher performance operation. (In particular, the "burst terminate" command is deleted.) This allows the bus rate of the SDRAM to be doubled without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units four times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow eight banks on large RAM chips.


text: Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400 MHz (periods of 5, 3.75, 3 and 2.5 ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25 ns). Corresponding 240-pin DIMMs are known as PC2-3200 through PC2-6400. DDR2 SDRAM is now available at a clock rate of 533 MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available.


text: Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100 MHz) has somewhat higher latency than DDR-400 (internal clock rate 200 MHz).


text: DDR3 continues the trend, doubling the minimum read or write unit to eight consecutive words. This allows another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. To maintain 800–1600 M transfers/s (both edges of a 400–800 MHz clock), the internal RAM array has to perform 100–200 M fetches per second.


text: Again, with every doubling, the downside is the increased latency. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a CAS latency of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).


text: DDR3 memory chips are being made commercially, and computer systems using them were available from the second half of 2007, with significant usage from 2008 onwards. Initial clock rates were 400 and 533 MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800 MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common. Performance up to DDR3-2800 (PC3 22400 modules) are available.


text: DDR4 SDRAM is the successor to DDR3 SDRAM. It was revealed at the Intel Developer Forum in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development - it was originally expected to be released in 2012, and later (during 2010) expected to be released in 2015, before samples were announced in early 2011 and manufacturers began to announce that commercial production and release to market was anticipated in 2012. DDR4 reached mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2.


text: The DDR4 chips run at 1.2 V or less, compared to the 1.5 V of DDR3 chips, and have in excess of 2 billion data transfers per second. They were expected to be introduced at frequency rates of 2133 MHz, estimated to rise to a potential 4266 MHz and lowered voltage of 1.05 V by 2013.


text: DDR4 did "not" double the internal prefetch width again, but uses the same 8"n" prefetch as DDR3. Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.


text: In February 2009, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since, as of 2009, current DRAM chips were only beginning to migrate to a 50 nm process. In January 2011, Samsung announced the completion and release for testing of a 30 nm 2048 MB DDR4 DRAM module. It has a maximum bandwidth of 2.13 Gbit/s at 1.2 V, uses pseudo open drain technology and draws 40% less power than an equivalent DDR3 module.


text: In March 2017, JEDEC announced a DDR5 standard is under development, but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.


text: RDRAM was a proprietary technology that competed against DDR. Its relatively high price and disappointing performance (resulting from high latencies and a narrow 16-bit data channel versus DDR's 64 bit channel) caused it to lose the race to succeed SDR DRAM.


text: SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its name to Advanced Memory International, Inc.). SLDRAM was an open standard and did not require licensing fees. The specifications called for a 64-bit bus running at a 200, 300 or 400 MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like DDR SDRAM, SLDRAM uses a double-pumped bus, giving it an effective speed of 400, 600, or 800 MT/s. (1 MT/s = 1000^2 transfers per second)


text: SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#). Unlike SDRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the command contained the ID of the chip that should process it. Data was transferred in 4- or 8-word bursts across an 18-bit (per chip) data bus, using one of two differential data clocks (DCLK0/DCLK0# and DCLK1/DCLK1#). Unlike standard SDRAM, the clock was generated by the data source (the SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, greatly reducing data skew. To avoid the need for a pause when the source of the DCLK changes, each command specified which DCLK pair it would use.


text: Individual devices had 8-bit IDs. The 9th bit of the ID sent in commands was used to address multiple devices. Any aligned power-of-2 sized group could be addressed. If the transmitted msbit was set, all least-significant bits up to and including the least-significant 0 bit of the transmitted address were ignored for "is this addressed to me?" purposes. (If the ID8 bit is actually considered less significant than ID0, the unicast address matching becomes a special case of this pattern.)


text: A notable omission from the specification was per-byte write enables; it was designed for systems with caches and ECC memory, which always write in multiples of a cache line.


text: Additional commands (with CMD5 set) opened and closed rows without a data transfer, performed refresh operations, read or wrote configuration registers, and performed other maintenance operations. Most of these commands supported an additional 4-bit sub-ID (sent as 5 bits, using the same multiple-destination encoding as the primary ID) which could be used to distinguish devices that were assigned the same primary ID because they were connected in parallel and always read/written at the same time.


text: There were a number of 8-bit control registers and 32-bit status registers to control various device timing parameters.


text: VCM was a proprietary type of SDRAM that was designed by NEC, but released as an open standard with no licensing fees. It is pin-compatible with standard SDRAM, but the commands are different. The technology was a potential competitor of RDRAM because VCM was not nearly as expensive as RDRAM was. A Virtual Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, so support for both depends only on the capabilities of the memory controller. In the late 1990s, a number of PC northbridge chipsets (such as the popular VIA KX133 and KT133) included VCSDRAM support.


text: VCM inserts an SRAM cache of 16 "channel" buffers, each 1/4 row "segment" in size, between DRAM banks' sense amplifier rows and the data I/O pins. "Prefetch" and "restore" commands, unique to VCSDRAM, copy data between the DRAM's sense amplifier row and the channel buffers, while the equivalent of SDRAM's read and write commands specify a channel number to access. Reads and writes may thus be performed independent of the currently active state of the DRAM array, with the equivalent of four full DRAM rows being "open" for access at a time. This is an improvement over the two open rows possible in a standard two-bank SDRAM. (There is actually a 17th "dummy channel" used for some operations.)


text: To read from VCSDRAM, after the active command, a "prefetch" command is required to copy data from the sense amplifier array to the channel SDRAM. This command specifies a bank, two bits of column address (to select the segment of the row), and four bits of channel number. Once this is performed, the DRAM array may be precharged while read commands to the channel buffer continue. To write, first the data is written to a channel buffer (typically previous initialized using a Prefetch command), then a restore command, with the same parameters as the prefetch command, copies a segment of data from the channel to the sense amplifier array.


text: Unlike a normal SDRAM write, which must be performed to an active (open) row, the VCSDRAM bank must be precharged (closed) when the restore command is issued. An active command immediately after the restore command specifies the DRAM row completes the write to the DRAM array. There is, in addition, a 17th "dummy channel" which allows writes to the currently open row. It may not be read from, but may be prefetched to, written to, and restored to the sense amplifier array.


text: Although normally a segment is restored to the same memory address as it was prefetched from, the channel buffers may also be used for very efficient copying or clearing of large, aligned memory blocks. (The use of quarter-row segments is driven by the fact that DRAM cells are narrower than SRAM cells. The SRAM bits are designed to be four DRAM bits wide, and are conveniently connected to one of the four DRAM bits they straddle.) Additional commands prefetch a pair of segments to a pair of channels, and an optional command combines prefetch, read, and precharge to reduce the overhead of random reads.


text: The above are the JEDEC-standardized commands. Earlier chips did not support the dummy channel or pair prefetch, and use a different encoding for precharge.


text: A 13-bit address bus, as illustrated here, is suitable for a device up to 128 Mbit. It has two banks, each containing 8,192 rows and 8,192 columns. Thus, row addresses are 13 bits, segment addresses are two bits, and eight column address bits are required to select one byte from the 2,048 bits (256 bytes) in a segment.


text: Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics adaptors. It is designed for graphics-related tasks such as texture memory and framebuffers, found on video cards. It adds functions such as bit masking (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike VRAM and WRAM, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other video RAM technologies.


text: The earliest known SGRAM memory are 8Mbit chips dating back to 1994: the Hitachi HM5283206, introduced in November 1994, and the NEC μPD481850, introduced in December 1994. The earliest known commercial device to use SGRAM is Sony's PlayStation (PS) video game console, starting with the Japanese SCPH-5000 model released in December 1995, using the NEC μPD481850 chip.


text: Graphics double data rate SDRAM (GDDR SDRAM) is a type of specialized DDR SDRAM designed to be used as the main memory of graphics processing units (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2018, there are six successive generations of GDDR: GDDR2, GDDR3, GDDR4, GDDR5, and GDDR5X, GDDR6.


text: GDDR was initially known as DDR SGRAM. It was commercially introduced as a 16Mbit memory chip by Samsung Electronics in 1998.


text: High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stacked SDRAM from Samsung, AMD and SK Hynix. It is designed to be used in conjunction with high-performance graphics accelerators and network devices. The first HBM memory chip was produced by SK Hynix in 2013.


title: Supercritical carbon dioxide

text: Supercritical carbon dioxide (s) is a fluid state of carbon dioxide where it is held at or above its critical temperature and critical pressure.


title: Supercritical carbon dioxide

text: Carbon dioxide usually behaves as a gas in air at standard temperature and pressure (STP), or as a solid called dry ice when cooled and/or pressurised sufficiently. If the temperature and pressure are both increased from STP to be at or above the critical point for carbon dioxide, it can adopt properties midway between a gas and a liquid. More specifically, it behaves as a supercritical fluid above its critical temperature () and critical pressure (), expanding to fill its container like a gas but with a density like that of a liquid.


title: Supercritical carbon dioxide

text: Supercritical is becoming an important commercial and industrial solvent due to its role in chemical extraction in addition to its relatively low toxicity and environmental impact. The relatively low temperature of the process and the stability of also allows most compounds to be extracted with little damage or denaturing. In addition, the solubility of many extracted compounds in varies with pressure, permitting selective extractions.


title: Supercritical carbon dioxide

text: Carbon dioxide is gaining popularity among coffee manufacturers looking to move away from classic decaffeinating solvents. s is forced through the green coffee beans which are then sprayed with water at high pressure to remove the caffeine. The caffeine can then be isolated for resale (e.g. to the pharmaceutical or beverage manufacturers) by passing the water through activated charcoal filters or by distillation, crystallization or reverse osmosis. Supercritical carbon dioxide is used to remove organochloride pesticides and metals from agricultural crops without adulterating the desired constituents from the plant matter in the herbal supplement industry.


title: Supercritical carbon dioxide

text: Supercritical carbon dioxide can be used as a more environmentally friendly solvent for dry cleaning over traditional solvents such as chlorocarbons, including perchloroethylene.


title: Supercritical carbon dioxide

text: Supercritical carbon dioxide is used as the extraction solvent for creation of essential oils and other herbal distillates. Its main advantages over solvents such as hexane and acetone in this process are that it is non-flammable and does not leave toxic residue. Furthermore, separation of the reaction components from the starting material is much simpler than with traditional organic solvents. The can evaporate into the air or be recycled by condensation into a cold recovery vessel. Its advantage over steam distillation is that it operates at a lower temperature, which can separate the plant waxes from the oils.


title: Supercritical carbon dioxide

text: In laboratories, s is used as an extraction solvent, for example for determining total recoverable hydrocarbons from soils, sediments, fly-ash and other media, and determination of polycyclic aromatic hydrocarbons in soil and solid wastes. Supercritical fluid extraction has been used in determining hydrocarbon components in water.


title: Supercritical carbon dioxide

text: Processes that use s to produce micro and nano scale particles, often for pharmaceutical uses, are under development. The gas antisolvent process, rapid expansion of supercritical solutions and supercritical antisolvent precipitation (as well as several related methods) process a variety of substances into particles.


title: Supercritical carbon dioxide

text: Due to its ability to selectively dissolve organic compounds and assist the functioning of enzymes, s has been suggested as a potential solvent to support biological activity on Venus- or super-Earth-type planets.


title: Supercritical carbon dioxide

text: Environmentally beneficial, low-cost substitutes for rigid thermoplastic and fired ceramic are made using s as a chemical reagent. The s in these processes is reacted with the alkaline components of fully hardened hydraulic cement or gypsum plaster to form various carbonates. The primary byproduct is water.


title: Supercritical carbon dioxide

text: Supercritical carbon dioxide is used in the foaming of polymers. Supercritical carbon dioxide can saturate the polymer with solvent. Upon depressurization and heating the carbon dioxide rapidly expands, causing voids within the polymer matrix, i.e., creating a foam. Research is also ongoing at many universities in the production of microcellular foams using s.


title: Supercritical carbon dioxide

text: Supercritical is chemically stable, reliable, low-cost, non-flammable and readily available, making it a desirable candidate working fluid for transcritical cycles.


title: Supercritical carbon dioxide

text: Supercritical is used as the working fluid in high efficiency domestic water heat pumps. Manufactured and widely used, heat pumps are also commercially available for domestic and business heating and cooling. While some of the more common domestic water heat pumps remove heat from the space in which they are located, such as a basement or garage, the heat pump water heaters are typically located outside, where they remove heat from the outside air.


title: Supercritical carbon dioxide

text: The unique properties of s present advantages for closed-loop power generation and can be applied to various power generation applications. Power generation systems that use traditional air Brayton and steam Rankine cycles can be upgraded to s to increase efficiency and power output.


title: Supercritical carbon dioxide

text: The relatively new Allam power cycle uses s as the working fluid in combination with fuel and pure oxygen. The produced by combustion mixes with the s working fluid and a corresponding amount of pure must be removed from the process (for industrial use or sequestration). This process reduces atmospheric emissions to zero.


title: Supercritical carbon dioxide

text: It presents interesting properties that promise substantial improvements in system efficiency. Due to its high fluid density, s enables extremely compact and highly efficient turbomachinery. It can use simpler, single casing body designs while steam turbines require multiple turbine stages and associated casings, as well as additional inlet and outlet piping. The high density allows for highly compact, microchannel-based heat exchanger technology.


title: Supercritical carbon dioxide

text: In 2016, General Electric announced a super-critical based turbine that enabled a 50% efficiency of converting heat energy to electrical energy. In it the is heated to 700 °C. It requires less compression and allows heat transfer. It reaches full power in 2 minutes, whereas steam turbines need at least 30 minutes. The prototype generated 10 MW and is approximately 10% the size of a comparable steam turbine.


title: Supercritical carbon dioxide

text: Further, due to its superior thermal stability and non-flammability, direct heat exchange from high temperature sources is possible, permitting higher working fluid temperatures and therefore higher cycle efficiency. Unlike two-phase flow, the single-phase nature of s eliminates the necessity of a heat input for phase change that is required for the water to steam conversion, thereby also eliminating associated thermal fatigue and corrosion.


title: Supercritical carbon dioxide

text: Despite the promise of substantially higher efficiency and lower capital costs, the use of s presents corrosion engineering, material selection and design issues. Materials in power generation components must display resistance to damage caused by high-temperature, oxidation and creep. Candidate materials that meet these property and performance goals include incumbent alloys in power generation, such as nickel-based superalloys for turbomachinery components and austenitic stainless steels for piping. Components within s Brayton loops suffer from corrosion and erosion, specifically erosion in turbomachinery and recuperative heat exchanger components and intergranular corrosion and pitting in the piping.


title: Supercritical carbon dioxide

text: Testing has been conducted on candidate Ni-based alloys, austenitic steels, ferritic steels and ceramics for corrosion resistance in s cycles. The interest in these materials derive from their formation of protective surface oxide layers in the presence of carbon dioxide, however in most cases further evaluation of the reaction mechanics and corrosion/erosion kinetics and mechanisms is required, as none of the materials meet the necessary goals.


title: Supercritical carbon dioxide

text: Work is underway to develop a s closed-cycle gas turbine to operate at temperatures near 550 °C. This would have implications for bulk thermal and nuclear generation of electricity, because the supercritical properties of carbon dioxide at above 500 °C and 20 MPa enable thermal efficiencies approaching 45 percent. This could increase the electrical power produced per unit of fuel required by 40 percent or more. Given the volume of carbon fuels used in producing electricity, the environmental impact of cycle efficiency increases would be significant.


title: Supercritical carbon dioxide

text: Supercritical is an emerging natural refrigerant, used in new, low carbon solutions for domestic heat pumps. Supercritical heat pumps are commercially marketed in Asia. EcoCute systems from Japan, developed by Mayekawa, develop high temperature domestic water with small inputs of electric power by moving heat into the system from the surroundings.


title: Supercritical carbon dioxide

text: "Clean coal" technologies are emerging that could combine such enhanced recovery methods with carbon sequestration. Using gasifiers instead of conventional furnaces, coal and water is reduced to hydrogen gas, carbon dioxide and ash. This hydrogen gas can be used to produce electrical power In combined cycle gas turbines, is captured, compressed to the supercritical state and injected into geological storage, possibly into existing oil fields to improve yields. The unique properties of s ensure that it remains out of the atmosphere.


title: Supercritical carbon dioxide

text: Supercritical can be used as a working fluid for geothermal electricity generation in both enhanced geothermal systems and sedimentary geothermal systems (so-called Plume Geothermal). EGS systems utilize an artificially fractured reservoir in basement rock while CPG systems utilize shallower naturally-permeable sedimentary reservoirs. Possible advantages of using in a geologic reservoir, compared to water, include higher energy yield resulting from its lower viscosity, better chemical interaction, and permanent storage as the reservoir must be filled with large masses of . As of 2011, the concept had not been tested in the field.


title: Supercritical carbon dioxide

text: Supercritical carbon dioxide is used in the production of silica, carbon and metal based aerogels. For example, silicon dioxide gel is formed and then exposed to s. When the goes supercritical, all surface tension is removed, allowing the liquid to leave the aerogel and produce nanometer sized pores.


title: Supercritical carbon dioxide

text: Supercritical is an alternative for thermal sterilization of biological materials and medical devices with combination of the additive peracetic acid (PAA). Supercritical does not sterilize the media, because it does not kill the spores of microorganisms. Moreover, this process is gentle, as the morphology, ultrastructure and protein profiles of inactivated microbes are preserved.


title: Chlorophyta

text: Chlorophyta or Prasinophyta is a taxon of green algae informally called chlorophytes. The name is used in two very different senses, so care is needed to determine the use by a particular author. In older classification systems, it refers to a highly paraphyletic group of "all" the green algae within the green plants (Viridiplantae) and thus includes about 7,000 species of mostly aquatic photosynthetic eukaryotic organisms. In newer classifications, it refers to the sister clade of the streptophytes/charophytes. The clade Streptophyta consists of the Charophyta in which the Embryophyta (land plants) emerged. In this latter sense the Chlorophyta includes only about 4,300 species. About 90% of all known species live in freshwater.


title: Chlorophyta

text: Like the land plants (embryophytes: bryophytes and tracheophytes), green algae (chlorophytes and charophytes besides embryophytes) contain chlorophyll a and chlorophyll b and store food as starch in their plastids.


title: Chlorophyta

text: With the exception of Palmophyllophyceae, Trebouxiophyceae, Ulvophyceae and Chlorophyceae, which show various degrees of multicellularity, all the Chlorophyta lineages are unicellular. Some members of the group form symbiotic relationships with protozoa, sponges, and cnidarians. Others form symbiotic relationships with fungi to form lichens, but the majority of species are free-living. Some conduct sexual reproduction, which is oogamous or isogamous. All members of the clade have motile flagellated swimming cells. While most species live in freshwater habitats and a large number in marine habitats, other species are adapted to a wide range of land environments. For example, "Chlamydomonas nivalis", which causes Watermelon snow, lives on summer alpine snowfields. Others, such as "Trentepohlia" species, live attached to rocks or woody parts of trees. "Monostroma kuroshiense", an edible green alga cultivated worldwide and most expensive among green algae, belongs to this group.


title: Chlorophyta

text: Species of Chlorophyta (treated as what is now considered one of the two main clades of Viridiplantae) are common inhabitants of marine, freshwater and terrestrial environments. Several species have adapted to specialised and extreme environments, such as deserts, arctic environments, hypersaline habitats, marine deep waters, deep-sea hydrothermal vents and habitats that experiences extreme changes in temperature, light and salinity. Some groups, such as the Trentepohliales are exclusively found on land. Several species of Chlorophyta live in symbiosis with a diverse range of eukaryotes, including fungi (to form lichens), ciliates, forams, cnidarians and molluscs.


title: Chlorophyta

text: Characteristics used for the classification of Chlorophyta are: type of zoid, mitosis (karyokynesis), cytokinesis, organization level, life cycle, type of gametes, cell wall polysaccharides and more recently genetic data.


title: Chlorophyta

text: A newer proposed classification follows Leliaert et al. 2011 and modified with Silar 2016, Leliaert 2016 and Lopes dos Santos et al. 2017 for the green algal clades and Novíkov & Barabaš-Krasni 2015 for the land plants clade. Sánchez-Baracaldo et al. is followed for the basal clades.


title: Chlorophyta

text: A 2020 paper places the "Prasinodermophyta" (i.e. Prasinodermophyceae + Palmophyllophyceae) as the basal Viridiplantae clade.


title: Chlorophyta

text: Simplified phylogeny of the Chlorophyta, according to Leliaert "et al". 2012. Note that many algae previously classified in Chlorophyta are placed here in Streptophyta.


title: Chlorophyta

text: A possible classification when Chlorophyta refers to one of the two clades of the Viridiplantae is shown below.


title: Chlorophyta

text: Classification of the Chlorophyta, treated as all green algae, according to Hoek, Mann and Jahns 1995.


title: Chlorophyta

text: In a note added in proof, an alternative classification is presented for the algae of the class Chlorophyceae:


title: Chlorophyta

text: In February 2020, the fossilized remains of green algae, named "Proterocladus antiquus" were discovered in the northern province of Liaoning, China. At around a billion years old, it is believed to be one of the oldest examples of a multicellular chlorophyte.


title: Serenoa

text: Serenoa repens, commonly known as saw palmetto, is the sole species currently classified in the genus Serenoa. It is a small palm, growing to a maximum height around . It is endemic to the subtropical and tropical Southeastern United States, most commonly along the south Atlantic and Gulf Coastal plains and sand hills. It grows in clumps or dense thickets in sandy coastal areas, and as undergrowth in pine woods or hardwood hammocks.


title: Serenoa

text: Erect stems or trunks are rarely produced, but are found in some populations. It is a hardy plant; extremely slow-growing, and long-lived, with some plants (especially in Florida) possibly being as old as 500–700 years.


title: Serenoa

text: Saw palmetto is a fan palm, with the leaves that have a bare petiole terminating in a rounded fan of about 20 leaflets. The petiole is armed with fine, sharp teeth or spines that give the species its common name. The teeth or spines are easily capable of breaking the skin, and protection should be worn when working around a saw palmetto. The leaves are light green inland, and silvery-white in coastal regions. The leaves are 1–2 m in length, the leaflets 50–100 cm long. They are similar to the leaves of the palmettos of genus "Sabal". The flowers are yellowish-white, about 5 mm across, produced in dense compound panicles up to 60 cm long.


title: Serenoa

text: The fruit is a large reddish-black drupe and is an important food source for wildlife and historically for humans. The plant is used as a food plant by the larvae of some Lepidoptera species such as "Batrachedra decoctor", which feeds exclusively on the plant.


title: Serenoa

text: Saw palmetto extract has been studied as a possible treatment for people with prostate cancer and for men with lower urinary tract symptoms associated with benign prostatic hyperplasia (BPH). As of 2018, there is insufficient scientific evidence that saw palmetto extract is effective for treating cancer or BPH and its symptoms.


title: Serenoa

text: One 2016 review of clinical studies with a standardized extract of saw palmetto (called "Permixon") found that the extract was safe and may be effective for relieving BPH-induced urinary symptoms compared against a placebo.


title: Serenoa

text: Indigenous names are reported to include: "tala" or "talimushi" ("palmetto's uncle") in Choctaw; "cani" (Timucua); "ta ́:la" (Koasati); "taalachoba" ("big palm", Alabama); "ta:laɬ a ́ kko" ("big palm", Creek); "talco ́:bˆı "("big palm", Mikasuki); and "guana "(Taino, possibly). Saw palmetto fibers have been found among materials from indigenous people as far north as Wisconsin and New York, strongly suggesting this material was widely traded prior to European contact. The leaves are used for thatching by several indigenous groups, so commonly that a location in Alachua County, Florida, is named Kanapaha ("palm house"). The fruit may have been used to treat an unclear form of fish poisoning by the Seminoles and Bahamians.


title: Disney Infinity 3.0

text: Disney Infinity 3.0 (also known as Disney Infinity: Star Wars) is an action-adventure sandbox video game published by Disney Interactive Studios (the last game to be published by the company before their closure) for Microsoft Windows, PlayStation 3, PlayStation 4, Wii U, Xbox 360, Xbox One and Apple TV, and is the third and final installment in the toys-to-life "Disney Infinity" series. It was developed by Avalanche Software, with additional help from Ninja Theory, Studio Gobo, Sumo Digital, and United Front Games. In contrast to how "Disney Infinity 2.0" focused on Marvel characters and playsets, "3.0" has a focus on the "Star Wars" franchise. The game was announced on May 5, 2015, and was released on August 28, 2015 in Europe and on August 30, 2015 in North America.


title: Disney Infinity 3.0

text: "Disney Infinity 3.0" features similar gameplay mechanics to "Disney Infinity" and "Disney Infinity 2.0". Although sharing many key elements, the game's combat system has been redesigned to become more in-depth and complex. The game's combat system is influenced by the "" and , "Kingdom Hearts" and most of the Spider-Man's aerial combat-themed video game series (except "Ultimate Spider-Man"). Lightsabers have been integrated into combat, due to the inclusion of "Star Wars" characters. Characters who use lightsabers in combat can utilize additional weapons. For instance, playable character Luke Skywalker has the ability to use a blaster and a lightsaber, which used together can juggle enemies in the air. Full combos have been integrated, which allows the player to pause mid-combo and branch off into another variation of the combo. Playable characters with the ability to use the Force, in "Star Wars" mythology, have the ability to push and pull enemies during combat. Special attacks, which were introduced in "Disney Infinity: Marvel Super Heroes", have returned. Only the bearer of a close-ranged weapon (such as lightsabers and other blade or staff weapons), including the characters who have their own primary close-ranged weapons (like Mulan, whose primary weapon is a staff, similar to the Jedi and Sith's own primary lightsaber), and characters who can fly are able to perform an aerial combo. Instead of waiting for a progress bar to fill up for a special attack to be performed, a new feature allows the attack to be released early, but the effects of the attack are not as strong. Auto-lock when firing ranged weapons at targets has been enhanced, so players no longer have to move closer to enemies in order to auto-lock on their positions.


title: Disney Infinity 3.0

text: The "Twilight of the Republic" Playset storyline is based on the era of the "Star Wars" prequel trilogy. Set during the events of "", Obi-Wan Kenobi, Anakin Skywalker, Yoda and Ahsoka Tano discover a reactivated Droid factory on the planet Geonosis. The four Jedi then decide to find out who is the mastermind behind the newly minted droid army. As the story progresses, the pair cross paths with General Grievous, Jabba the Hutt, Cad Bane, Mace Windu, Sebulba, Padme Amidala and the main antagonist Darth Maul, and travel to planets Coruscant, Naboo, Geonosis and Tatooine.


title: Disney Infinity 3.0

text: The "Rise Against the Empire" Playset storyline is based on the events of the original "Star Wars" trilogy, with some differences. The playset revolves around Luke Skywalker, his sister Leia, Han Solo and Chewbacca finding themselves locked in battle with Darth Vader.


title: Disney Infinity 3.0

text: A playset based on "" was announced at the 2015 D23 Expo and released in December of that year; it features Finn, Rey, Kylo Ren, and Poe Dameron as playable characters.


title: Disney Infinity 3.0

text: In the "Inside Out" playset, Riley falls asleep watching a horror movie and chaos ensues in her subconscious. This scatters some of Riley's memories all over Imagination Land and the emotions must find and return them to headquarters before Riley awakens.


title: Disney Infinity 3.0

text: In the Marvel Battlegrounds playset, Loki teams up with Ultron to manipulate all of the universe's heroes into fighting each other using robot duplicates while they steal one of the six Infinity Stones from the Asgardian vault. All Marvel characters from "Disney Infinity 2.0" are playable in this playset, along with new characters introduced in 3.0. This is the first and only "Disney Infinity" play set to utilize four-player local gameplay.


title: Disney Infinity 3.0

text: In the "Finding Dory" playset, Dory learns of a flood at the Marine Life Institute that has washed the littlest fish into all the wrong tanks. Together with Nemo, Marlin, Hank, Bailey and Destiny, she returns to rescue them and lead them out to safety. Along the way, she makes new fish friends and customizes a new reef area as a sanctuary for the rescued fish.


title: Disney Infinity 3.0

text: The Toy Box Takeover expansion game begins with Mickey summoning his friends. When Syndrome gets his hands on Merlin and Mickey's Wand he teams up with all the other villains for control of the Toy Box. Toy Box Takeover features six dungeon crawler-style levels that can be accessed by any playable character, except for any characters the game considers a car. The player must take down Syndrome's minions before confronting him in his protected base.


title: Disney Infinity 3.0

text: The Toy Box Speedway expansion game is a battle racing game, similar to the races in the Cars Play Set from the original "Disney Infinity" and the "Mario Kart" game series. Like its dungeon-crawler counterpart, Toy Box Takeover, any playable character may enter it.


title: Disney Infinity 3.0

text: Since "Disney Infinity", there have been hints of "Star Wars" joining the line of games. The "ultimate unlocks" in the first two "Infinity" games were a lightsaber and a landspeeder, respectively. Prior to the release of "Disney Infinity 2.0" in 2014, series producer John Vignocchi hinted that a future installment could have characters from Lucasfilm. The title's existence was first revealed following a leak from Chinese retailer Taobao showing potential character and figure designs for the third installment. German retailer Saturn would later leak images of the game's Starter Pack featuring the characters of Anakin Skywalker and Ahsoka Tano from "". The game was officially revealed by "Game Informer" on May 5, 2015.


title: Disney Infinity 3.0

text: Studio Gobo, Ninja Theory and United Front Games were among development groups that worked on the game's Playsets. In order to create a more complex combat system, compared to the first two installments, Disney decided to also have Ninja Theory revamp the game's combat, after LucasArts had expressed interest in working with the company. United Front Games was chosen for their combat experience on Sleeping Dogs to develop the Marvel Battlegrounds playset.


title: Disney Infinity 3.0

text: "Disney Infinity 3.0" was released on August 30, 2015 in North America. The Starter Pack, which includes the game disc, Anakin Skywalker and Ahsoka Tano character figurines, one playset piece (Twilight of the Republic), one web card and the Disney Infinity Base, was released on the game's launch. The game also received a digital download release. Exclusively in Europe, "Disney Infinity 3.0" had a game disc-only release without the figurines, web cards and Disney Infinity Base, that are included in the Starter Pack.


title: Disney Infinity 3.0

text: A Saga Bundle Starter Pack was available at launch for the PS3 and PS4. It contains the basic starter pack, Rise Against the Empire playset, and Boba Fett figure. Boba Fett was a timed exclusive to this pack and was released on his own in March 2016.


title: Disney Infinity 3.0

text: Power Disc Packs, which unlock additional content in the game, are no longer sold in blind packs, contrary to the use of blind packs in the previous two games. Instead, power discs were released in identifiable packaging.


title: Disney Infinity 3.0

text: A special Power Disc based on Mickey Mouse's "Kingdom Hearts" role was given out at Disney's 2015 D23 Expo. Controversially, it is an expo exclusive and was not sold in stores. Despite this, it does not affect a player's chance to get 100% completion.


title: Disney Infinity 3.0

text: "Disney Infinity 3.0" received very positive reviews from video game critics who praised the refinements to the Toy Box, Play Sets, combat, and reduced bugs.


title: Disney Infinity 3.0

text: Between the March 2016 releases of the "Marvel Battlegrounds" Play Set and the then-new Marvel and Baloo figures, and the cancellation of the "Disney Infinity" series, players of the Windows, mobile and Apple TV versions noticed that the game was not updated for those platforms to support the new figures or Play Set. The "Disney Infinity" account confirmed that the new content would be available on consoles.


title: Disney Infinity 3.0

text: Due to Disney's decision to shut down Avalanche Software and end its toys-to-life business, Disney began to gradually retire the "Disney Infinity" franchise, leaving it as a trilogy. On July 29, 2016, the in-game purchase system was completely removed for the Windows (except the Steam version), iOS, Android, and Apple TV versions of the game. Before they did, Disney closed its game without letting anyone know. On September 30, 2016, the Windows (standalone launcher version), Apple TV, Google, and Amazon versions of the game were removed from their respective online stores (and became unplayable), and new toybox submissions ceased to be accepted. The Steam versions of "2.0" and "3.0" were also taken down with Disney Interactive announcing that "Gold Editions" of all installments of the trilogy would be provided to allow continued use of the full games and all their content after the online servers are shut down. Anyone who purchased downloadable content for those versions in-game or via Steam received the "Gold Editions" for free, and any webcodes that were redeemed still apply. Disney released the "Gold Editions" of all three "Disney Infinity" games—including the first game, which was previously never released either on Steam or in a full version (with playsets) on PC—on December 9, 2016 via Steam. The original Steam releases of the second and third games were completely delisted and disabled. On January 3, 2017, in-game purchases in the Windows 8/10 versions (from the Windows Store) were disabled as well. On the morning of March 3, 2017, in addition to the discontinuation of all aforementioned online services, Disney also shut down all officially related websites, including Online Profiles linked to Disney Accounts and the official forums. Apple TV and Windows 8/10 versions were unplayable as well on that day.


title: Disney Infinity 3.0

text: In October 2017, Disney quietly announced a series of action figures entitled "Toy Box" exclusive to Disney Store locations. The line consists of characters from Pixar, "Star Wars", and Marvel properties in their "Disney Infinity" designs.


title: Mario Winans

text: Mario Mendell Winans ( Brown; born August 29, 1974) is an American singer, songwriter, and record producer best known for his 2004 song "I Don't Wanna Know", which reached number 2 in the United States and number 1 in the United Kingdom. Winans also won a Grammy Award for Best Gospel Performance for co-writing CeCe Winans's song "Pray".


title: Mario Winans

text: Mario Winans recorded his second album "Hurt No More" in 2001, 2002, and 2003 in between working with other artists. The album is based on stories of love and betrayal.


title: Mario Winans

text: The first single "I Don't Wanna Know" was based on a sample of the Fugees' 1996 hit single "Ready or Not", which itself was based on a slowed-down sample of the instrumental track "Boadicea" by Enya from her 1987 self-titled album. Enya and her representatives said yes to Winans and P. Diddy for her approval of the sample. She even re-recorded Boadicea for the song, although Winans had no idea that the Fugees sample he had used was a sample itself. They even gave Enya herself credit for the single as "Mario Winans featuring P. Diddy and Enya". The song features a rap by P. Diddy. The song was released as the single in early 2004 and became a worldwide hit, reaching number 1 in Germany and the United Kingdom and on the rhythmic top 40 radio chart in the United States; to number 2 on the "Billboard" Hot 100 and the US R&B/Hip-Hop singles chart; and to number 3 on both the Australian and Norwegian singles charts. It also reached the top ten on a composite European singles chart.


title: Mario Winans

text: "Hurt No More" was released on April 20, 2004, in the US and by early June 2004 had reached number 1 on the Billboard R&B/Hip-Hop Albums chart, number 2 on the "Billboard" 200, and number 3 on the UK Albums Chart.


title: Mario Winans

text: The album's second single, "Never Really Was", used a sample of the orchestrated beginning of Madonna's 1986 hit "Papa Don't Preach" as its background music. However, the song failed to chart in America. A remix version was released as a single featuring rapper Lil Flip.


title: Mario Winans

text: The song "This Is the Thanks I Get" was stated to be the album's third and final single but no official release was set. The song went on to peak on the "Billboard" Bubbling Under R&B chart at number 12.


title: Public housing in the United Kingdom

text: Public housing in the United Kingdom, also known as council estates, council housing, or social housing, provided the majority of rented accommodation until 2011 when the number of households in private rental housing surpassed the number in social housing. Houses and flats built for public or social housing use are built by or for local authorities and known as council houses, though since the 1980s the role of non-profit housing associations became more important and subsequently the term "social housing" became more widely used, as technically council housing only refers to housing owned by a local authority, though the terms are largely used interchangeably. Before 1865, housing for the poor was provided solely by the private sector. Council houses were built on council estates, known as schemes in Scotland, where other amenities, like schools and shops, were often also provided. From the 1950s, blocks of flats and three-or-four-storey blocks of maisonettes were widely built, alongside large developments of terraced housing, while the 1960s and to some degree the 1970s saw construction of many high-rise tower blocks. Flats and houses were also built in mixed estates.


title: Public housing in the United Kingdom

text: Council homes were built to supply uncrowded, well-built homes on secure tenancies at reasonable rents to primarily working-class people. Council housing in the mid-20th century included many large suburban council estates, featuring terraced and semi-detached houses, where other amenities like schools and shops were often also provided. By the late 1970s, almost a third of UK households lived in social housing: some of these developments did not live up to the hopes of their supporters, and now suffer from urban blight, while others became desirable locations.


title: Public housing in the United Kingdom

text: Since 1979, the role of council housing has changed. Housing stock has been sold under Right to Buy legislation, and new social housing has mainly been developed and managed by housing associations. A substantial part of the UK population still lives in council housing; in 2010, about 17% of UK households. Approximately 55% of the country's social housing stock is owned by local authorities, of which 15% is managed on a day-to-day basis by arms-length management organisations rather than the authority, and 45% by housing associations.


title: Public housing in the United Kingdom

text: The history of public housing is the history of the housing of the poor. Even that statement is controversial, as before 1890 the state was not involved in housing policy. Public housing became needed to provide "homes fit for heroes" in 1919, then to enable slum clearance. Standards were set to ensure high-quality homes. Aneurin Bevan, a Labour politician, passionately believed that council houses should be provided for all, while the Conservative politician Harold Macmillan saw council housing "as a stepping stone to home ownership". The Conservative government of Margaret Thatcher introduced Right to Buy in 1979, with the millionth council house being sold within seven years. In time, the transfer of public housing stock to private ownership reached the point where councils had to rent back their own houses to house the homeless.


title: Public housing in the United Kingdom

text: Even in the stable medieval model of landowner and peasant, where estate workers lived at the landowner's whim in a tied cottage, the aged and infirm needed provision from their former employer, the church or the state.


title: Public housing in the United Kingdom

text: The documented history of social housing in Britain starts with almshouses, which were established from the 10th century, to provide a place of residence for "poor, old and distressed folk". The first recorded almshouse was founded in York by King Æthelstan; the oldest still in existence is the Hospital of St. Cross in Winchester, dating to 1133.


title: Public housing in the United Kingdom

text: The public workhouse was the final fallback solution for the destitute. Rural poverty had been greatly increased by the Inclosure Acts leaving many in need of assistance. This was divided into outside relief, or handouts to keep the family together, and inside relief, which meant submitting to the workhouse. The workhouse provided for two groups of people – the transient population roaming the country looking for seasonal work, and the long-term residents. The two were kept separate where possible. The long-term residents included single elderly men incapable of further labour, and young women with their children—often women who had been abandoned by their husbands, single mothers and servant-girls who had been dismissed from residential positions.


title: Public housing in the United Kingdom

text: The pressure for decent housing was increased by overcrowding in the large cities during the Industrial Revolution of the 19th century; many social commentators (such as Octavia Hill) reported on the squalor, sickness and immorality that arose. Some industrialists and independent organisations provided housing in tenement blocks, while some philanthropist factory owners built entire villages for their workers, such as Saltaire (1853), Bournville (1879) and Port Sunlight (1888).


title: Public housing in the United Kingdom

text: The City of London Corporation built tenements in Farringdon Road in 1865, but this was an isolated instance. The first council to build housing as an integrated policy was Liverpool Corporation, starting with St Martin's Cottages in Ashfield Street, Vauxhall, completed in 1869. The Corporation then built Victoria Square Dwellings, opened by Home Secretary Sir Richard Cross in 1885.


title: Public housing in the United Kingdom

text: That year, a Royal Commission was held, as the state had taken an interest in housing and housing policy. This led to the Housing of the Working Classes Act 1890, which encouraged the London authority to improve the housing in their areas. It also gave them the power to acquire land and to build tenements and houses (cottages). As a consequence, London County Council opened the Boundary Estate in 1900, a 'block dwelling estate' of tenements in Tower Hamlets. The Housing of the Working Classes Act 1900 extended these power to all local councils, which then began building tenements and houses.


title: Public housing in the United Kingdom

text: In 1912, Raymond Unwin published a pamphlet "Nothing gained by Overcrowding". He worked on the influential Tudor Walters Report of 1918, which recommended housing in short terraces, spaced apart at a density of . The First World War indirectly provided a new impetus, when the poor physical health and condition of many urban recruits to the army was noted with alarm. This led to a campaign under the slogan "Homes fit for heroes". In 1919, the Government first required councils to provide housing, built to the Tudor Walters standards, under the Housing, Town Planning, &c. Act 1919 (Addison Act), helping them to do so through the provision of subsidies. London County Council embraced these freedoms and planned eight 'cottage estates' in the peripheries of London: Becontree, St Helier, Downham for example; seven further followed including Bellingham. Houses were built on green field land on the peripheries of the urban area. The war had caused house building costs to rise enormously: Sir Ernest Simon reported to the Manchester Housing Committee in 1910 that "houses that had cost £250 to build pre war were then costing £1,250, so the economic rent was 30/- a week but had to be let at 12/6d".


title: Public housing in the United Kingdom

text: The provision of local authority housing varied throughout the UK; in the period 1919–39 67% of the houses built in Scotland were in the public sector, compared to 26% in England.


title: Public housing in the United Kingdom

text: The Addison Act provided subsidies solely to local authorities and not to private builders. Many houses were built over the next few years in 'cottage estates'. The Housing, &c. Act 1923 (Chamberlain Act) of 1923 stopped subsidies going to council houses but extended the subsidies to private builders. Following the line of the railways, predominantly private estates were built on cheap agricultural land; building houses that the professional classes with an income of £300- £500 a year were able to afford. These pattern-book houses, put up speculatively by companies such as Wimpey, Costain, Laing and Taylor Woodrow, were mocked by Osbert Lancaster as "By-pass Variegated".


title: Public housing in the United Kingdom

text: Large council estates following the line of the radial roads. This marked a further movement out of the city, first by the middle classes and then the blue-collar workers, leaving just the poorest layer of society living in the urban area.


title: Public housing in the United Kingdom

text: The first Labour government was returned in 1924. The Wheatley Act of 1924 restored subsidies to municipal housing but at a lower level, it failed to make any provision for lower paid, who were living in the worse conditions, and could not afford to pay the higher rents of the new houses, or travel to or from them to work. They continued in substandard housing circling the urban core; in Manchester, for example, this 'slum belt' was about half a mile wide.


title: Public housing in the United Kingdom

text: While new council housing had been built, little had been done to resolve the problem of inner-city slums, which could also be found in many smaller towns. This was to change with the Housing Act 1930 (Greenwood Act), which required councils to prepare slum clearance plans, and some progress was made before the Second World War intervened.


title: Public housing in the United Kingdom

text: During the Second World War almost four million British homes were destroyed or damaged, and afterwards there was a major boom in council house construction. The bomb damage from the war only worsened the condition of Britain's housing stock, which was in poor condition before its outbreak. Before the war many social housing projects, such as the Quarry Hill Flats in Leeds were built. However, the bomb damage meant that much greater progress had to be made with slum clearance projects. In heavily bombed cities like London, Coventry and Kingston upon Hull, the redevelopment schemes were often larger and more radical.


title: Public housing in the United Kingdom

text: In the immediate post-war years, and well into the 1950s, council house provision was shaped by the New Towns Act 1946 and the Town and Country Planning Act 1947 of the 1945–51 Labour government. Simultaneously, this government introduced housing legislation that removed explicit references to housing for the working class and introduced the concept of "general needs" construction (i.e., that council housing should aim to fill the needs of a wide range of society). In particular, Aneurin Bevan, the Minister for Health and Housing, promoted a vision of new estates where "the working man, the doctor and the clergyman will live in close proximity to each other".


title: Public housing in the United Kingdom

text: While a number of large cities tentatively erected their first high-rise developments (e.g., Aston Cross in Birmingham, Churchill Gardens in Westminster), in England and Wales homes were typically semi-detached or in small terraces. A three-bedroom semi-detached council house was typically built on a square grid on the side, with a maximum density of houses of no more than , that is to say around per house. As a result, most houses had generous space around them. The new towns and many existing towns had countless estates built to this basic model. In Scotland, the tradition of tenement living meant that most homes of this period were built in low-rise (3–4) storey blocks of flats.


title: Public housing in the United Kingdom

text: For many working-class people, this housing model provided their first experience of private indoor toilets, private bathrooms and hot running water, as well as gardens and electric lighting. For tenants in England and Wales it also usually provided the first experience of private garden space (usually front and rear). The quality of these houses, and in particular the existence of small gardens in England and Wales, compared very favourably with social housing being built on the European continent in this period.


title: Public housing in the United Kingdom

text: The 1951 Conservative government began to re-direct the building programme back from "general needs" towards "welfare accommodation for low income earners" The principal focus was on inner-city slum clearance, completing the job that was started in the 1930s.


title: Public housing in the United Kingdom

text: Harold Macmillan's task, as Minister for Housing, was to deliver 300,000 houses a year. These were , 20% smaller than a Tudor Walters Bevan house, usually built as a two-bedroom terrace called "The Peoples House".