Instruction cycle - wikipedia Instruction cycle This article needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. ( October 2009 ) A diagram of the instruction cycle. An instruction cycle ( also known as the fetch -- decode -- execute cycle or the fetch - execute cycle ) is the basic operational process of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction dictates, and carries out those actions. This cycle is repeated continuously by a computer 's central processing unit ( CPU ), from boot - up to when the computer is shut down. In simpler CPUs the instruction cycle is executed sequentially, each instruction being processed before the next one is started. In most modern CPUs the instruction cycles are instead executed concurrently, and often in parallel, through an instruction pipeline : the next instruction starts being processed before the previous instruction has finished, which is possible because the cycle is broken up into separate steps. Contents 1 Components 2 Steps 2.1 Initiating the cycle 2.2 Fetch step 2.3 Decode step 2.4 Reading the effective address 2.5 Execute step 3 See also 4 References Components This article is in a list format that may be better presented using prose. You can help by converting this article to prose, if appropriate. Editing help is available. ( January 2018 ) Program counter ( PC ) An incrementing counter that keeps track of the memory address of the instruction that is to be executed next or in other words, holds the address of the instruction to be executed next. Memory address register ( MAR ) Holds the address of a block of memory for reading from or writing to. Memory data register ( MDR ) A two - way register that holds data fetched from memory ( and ready for the CPU to process ) or data waiting to be stored in memory. ( This is also known as the memory buffer register ( MBR ). ) Instruction register ( IR ) A temporary holding ground for the instruction that has just been fetched from memory. Control unit ( CU ) Decodes the program instruction in the IR, selecting machine resources, such as a data source register and a particular arithmetic operation, and coordinates activation of those resources. Arithmetic logic unit ( ALU ) Performs mathematical and logical operations. Floating - point unit ( FPU ) Performs floating - point operations. Steps Each computer 's CPU can have different cycles based on different instruction sets, but will be similar to the following cycle : Fetch the instruction : The next instruction is fetched from the memory address that is currently stored in the program counter and stored into the instruction register. At the end of the fetch operation, the PC points to the next instruction that will be read at the next cycle. Decode the instruction : During this cycle the encoded instruction present in the instruction register is interpreted by the decoder. Read the effective address : In the case of a memory instruction ( direct or indirect ) the execution phase will be during the next clock pulse. If the instruction has an indirect address, the effective address is read from main memory, and any required data is fetched from main memory to be processed and then placed into data registers ( clock pulse : T ). If the instruction is direct, nothing is done during this clock pulse. If this is an I / O instruction or a register instruction, the operation is performed during the clock pulse. Execute the instruction : The control unit of the CPU passes the decoded information as a sequence of control signals to the relevant function units of the CPU to perform the actions required by the instruction such as reading values from registers, passing them to the ALU to perform mathematical or logic functions on them, and writing the result back to a register. If the ALU is involved, it sends a condition signal back to the CU. The result generated by the operation is stored in the main memory or sent to an output device. Based on the feedback from the ALU, the PC may be updated to a different address from which the next instruction will be fetched. The cycle is then repeated. Initiating the cycle The cycle begins as soon as power is applied to the system, with an initial PC value that is predefined by the system 's architecture ( for instance, in Intel IA - 32 CPUs, the predefined PC value is 0xfffffff0 ). Typically this address points to a set of instructions in read - only memory ( ROM ), which begins the process of loading ( or booting ) the operating system. Fetch step The fetch step is the same for each instruction : The CPU sends the contents of the PC to the MAR and sends a read command on the address bus In response to the read command ( with address equal to PC ), the memory returns the data stored at the memory location indicated by PC on the data bus The CPU copies the data from the data bus into its MDR ( also known as MBR, see section Components above ) A fraction of a second later, the CPU copies the data from the MDR to the instruction register for instruction decoding The PC is incremented so that it points to the next instruction. This step prepares the CPU for the next cycle. The control unit fetches the instruction 's address from the memory unit. Decode step The decoding process allows the CPU to determine what instruction is to be performed so that the CPU can tell how many operands it needs to fetch in order to perform the instruction. The opcode fetched from the memory is decoded for the next steps and moved to the appropriate registers. The decoding is done by the CPU 's Control Unit. Reading the effective address This step evaluates which type of operation is to be performed. If it is a memory operation, the computer checks whether it 's a direct or indirect memory operation : Direct memory operation - Nothing is done. Indirect memory operation - The effective address is read from memory. If it is an I / O or register instruction, the computer checks its type and executes the instruction. Execute step The function of the instruction is performed. If the instruction involves arithmetic or logic, the ALU is utilized. This is the only stage of the instruction cycle that is useful from the perspective of the end user. Everything else is overhead required to make the execute step happen. See also Time slice, unit of operating system scheduling Classic RISC pipeline Cycles per instruction References Jump up ^ Bosky Agarwal ( 2004 ). `` Instruction Fetch Execute Cycle '' ( PDF ). Archived from the original ( PDF ) on June 11, 2009. Retrieved 2012 - 10 - 14. hide CPU technologies Architecture Turing machine Post -- Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite - state machine Queue automaton Von Neumann Harvard ( modified ) Dataflow TTA Cellular Artificial neural network Machine learning Deep learning Neural processing unit ( NPU ) Convolutional neural network Load / store architecture Register memory architecture Endianness FIFO Zero - copy NUMA HUMA HSA Mobile computing Surface computing Wearable computing Heterogeneous computing Parallel computing Concurrent computing Distributed computing Cloud computing Amorphous computing Ubiquitous computing Fabric computing Cognitive computing Unconventional computing Hypercomputation Quantum computing Adiabatic quantum computing Linear optical quantum computing Reversible computing Reverse computation Reconfigurable computing Optical computing Ternary computer Analogous computing Mechanical computing Hybrid computing Digital computing DNA computing Peptide computing Chemical computing Organic computing Wetware computing Neuromorphic computing Symmetric multiprocessing ( SMP ) Asymmetric multiprocessing ( AMP ) Cache hierarchy Memory hierarchy ISA types ASIP CISC RISC EDGE ( TRIPS ) VLIW ( EPIC ) MISC OISC NISC ZISC Comparison ISAs x86 z / Architecture ARM MIPS Power Architecture ( PowerPC ) SPARC Mill Itanium ( IA - 64 ) Alpha Prism SuperH V850 Clipper VAX Unicore PA - RISC MicroBlaze RISC - V Word size ( Special cases : 1 - bit, 2 - bit, 4 - bit ) 8 - bit 9 - bit 10 - bit 12 - bit 15 - bit 16 - bit 18 - bit 22 - bit 24 - bit 25 - bit 26 - bit 27 - bit 31 - bit 32 - bit 33 - bit 34 - bit 36 - bit 39 - bit 40 - bit 48 - bit 50 - bit 60 - bit 64 - bit 128 - bit 256 - bit 512 - bit Variable Execution Instruction pipelining Bubble Operand forwarding Out - of - order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards Parallelism level Bit Bit - serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Multithreading Temporal Simultaneous ( SMT ) ( Hyper - threading ) Speculative ( SpMT ) Preemptive Cooperative Clustered Multi-Thread ( CMT ) Hardware scout Flynn 's taxonomy SISD SIMD ( SWAR ) SIMT MISD MIMD SPMD Addressing mode CPU performance Transistor count Instructions per second ( IPS ) Instructions per clock ( IPC ) Cycles per instruction ( CPI ) Floating - point operations per second ( FLOPS ) Transactions per second ( TPS ) Synaptic Updates Per Second ( SUPS ) Performance per watt Orders of magnitude ( computing ) Cache performance measurement and metric CORDIC ( FPU emulation ) Core count Single - core processor Multi-core processor Manycore processor Types Central processing unit ( CPU ) GPGPU AI accelerator Vision processing unit ( VPU ) Vector processor Barrel processor Stream processor Digital signal processor ( DSP ) I / O processor / DMA controller Network processor Baseband processor Physics processing unit ( PPU ) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low - voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module ( MCM ) Chip stack multi-chip modules System on a chip ( SoC ) Multiprocessor system - on - chip ( MPSoC ) Programmable System - on - Chip ( PSoC ) Network on a chip ( NoC ) Components Execution unit ( EU ) Arithmetic logic unit ( ALU ) Address generation unit ( AGU ) Floating - point unit ( FPU ) Load - store unit ( LSU ) Branch predictor Unified Reservation Station Barrel shifter Uncore Sum addressed decoder ( SAD ) Front - side bus Back - side bus Northbridge ( computing ) Southbridge ( computing ) Adder ( electronics ) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit ( MMU ) Input -- output memory management unit ( IOMMU ) Integrated Memory Controller ( IMC ) Power Management Unit ( PMU ) Translation lookaside buffer ( TLB ) Stack engine Register file Processor register Hardware register Memory buffer register ( MBR ) Program counter Microcode ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three - dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed - signal integrated circuit Power management integrated circuit Quantum circuit Logic gate Combinational logic Sequential logic Emitter - coupled logic ( ECL ) Transistor -- transistor logic ( TTL ) Glue logic Quantum gate Gate array Counter ( digital ) Bus ( computing ) Semiconductor device Clock rate CPU multiplier Vision chip Memristor Power management APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating Hardware security Non-executable memory ( NX bit ) Memory Protection Extensions ( Intel MPX ) Intel Secure Key Hardware restriction ( firmware ) Software Guard Extensions ( Intel SGX ) Trusted Execution Technology Trusted Platform Module ( TPM ) Secure cryptoprocessor Hardware security module Hengzhi chip Related History of general - purpose CPUs Microprocessor chronology Processor design Retrieved from `` https://en.wikipedia.org/w/index.php?title=Instruction_cycle&oldid=844649722 '' Categories : Instruction processing Hidden categories : Articles needing additional references from October 2009 All articles needing additional references Articles needing cleanup from January 2018 All pages needing cleanup Articles with sections that need to be turned into prose from January 2018 Talk Contents About Wikipedia Azərbaycanca Čeština Deutsch Español 한국어 Italiano עברית Português Српски / srpski Українська 中文 4 more Edit links This page was last edited on 6 June 2018, at 06 : 45. About Wikipedia

Question: what executes the sequencing of instructions in the cpu
Answer: An instruction cycle