Multi-core processor - wikipedia Multi-core processor `` Dual Core '' redirects here. For the nerdcore duo, see Dual Core ( hip hop duo ). Diagram of a generic dual - core processor with CPU - local level - 1 caches and a shared, on - die level - 2 cache. An Intel Core 2 Duo E6750 dual - core processor. An AMD Athlon X2 6400 + dual - core processor. A multi-core processor is a single computing component with two or more independent processing units called cores, which read and execute program instructions. The instructions are ordinary CPU instructions ( such as add, move data, and branch ) but the single processor can run multiple instructions on separate cores at the same time, increasing overall speed for programs amenable to parallel computing. Manufacturers typically integrate the cores onto a single integrated circuit die ( known as a chip multiprocessor or CMP ) or onto multiple dies in a single chip package. The microprocessors currently used in almost all personal computers are multi-core. A multi-core processor implements multiprocessing in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share caches, and they may implement message passing or shared - memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two - dimensional mesh, and crossbar. Homogeneous multi-core systems include only identical cores ; heterogeneous multi-core systems have cores that are not identical ( e.g. big. LITTLE have heterogeneous cores that share the same instruction set, while AMD Accelerated Processing Units have cores that do n't even share the same instruction set ). Just as with single - processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, vector, or multithreading. Multi-core processors are widely used across many application domains, including general - purpose, embedded, network, digital signal processing ( DSP ), and graphics ( GPU ). The improvement in performance gained by the use of a multi-core processor depends very much on the software algorithms used and their implementation. In particular, possible gains are limited by the fraction of the software that can run in parallel simultaneously on multiple cores ; this effect is described by Amdahl 's law. In the best case, so - called embarrassingly parallel problems may realize speedup factors near the number of cores, or even more if the problem is split up enough to fit within each core 's cache ( s ), avoiding use of much slower main - system memory. Most applications, however, are not accelerated so much unless programmers invest a prohibitive amount of effort in re-factoring the whole problem. The parallelization of software is a significant ongoing topic of research. Contents 1 Terminology 2 Development 2.1 Commercial incentives 2.2 Technical factors 2.3 Advantages 2.4 Disadvantages 3 Hardware 3.1 Trends 3.2 Architecture 4 Software effects 4.1 Licensing 5 Embedded applications 6 Hardware examples 6.1 Commercial 6.2 Free 6.3 Academic 7 Benchmarks 8 Notes 9 See also 10 References 11 Further reading 12 External links Terminology The terms multi-core and dual - core most commonly refer to some sort of central processing unit ( CPU ), but are sometimes also applied to digital signal processors ( DSP ) and system on a chip ( SoC ). The terms are generally used only to refer to multi-core microprocessors that are manufactured on the same integrated circuit die ; separate microprocessor dies in the same package are generally referred to by another name, such as multi-chip module. This article uses the terms `` multi-core '' and `` dual - core '' for CPUs manufactured on the same integrated circuit, unless otherwise noted. In contrast to multi-core systems, the term multi-CPU refers to multiple physically separate processing - units ( which often contain special circuitry to facilitate communication between each other ). The terms many - core and massively multi-core are sometimes used to describe multi-core architectures with an especially high number of cores ( tens or hundreds ). Some systems use many soft microprocessor cores placed on a single FPGA. Each `` core '' can be considered a `` semiconductor intellectual property core '' as well as a CPU core. Development While manufacturing technology improves, reducing the size of individual gates, physical limits of semiconductor - based microelectronics have become a major design concern. These physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance. Some instruction - level parallelism ( ILP ) methods such as superscalar pipelining are suitable for many applications, but are inefficient for others that contain difficult - to - predict code. Many applications are better suited to thread - level parallelism ( TLP ) methods, and multiple independent CPUs are commonly used to increase a system 's overall TLP. A combination of increased available space ( due to refined manufacturing processes ) and the demand for increased TLP led to the development of multi-core CPUs. Commercial incentives Several business motives drive the development of multi-core architectures. For decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit ( IC ), which reduced the cost per device on the IC. Alternatively, for the same circuit area, more transistors could be used in the design, which increased functionality, especially for complex instruction set computing ( CISC ) architectures. Clock rates also increased by orders of magnitude in the decades of the late 20th century, from several megahertz in the 1980s to several gigahertz in the early 2000s. As the rate of clock speed improvements slowed, increased use of parallel computing in the form of multi-core processors has been pursued to improve overall processing performance. Multiple cores were used on the same CPU chip, which could then lead to better sales of CPU chips with two or more cores. For example, Intel has produced a 48 - core processor for research in cloud computing ; each core has an x86 architecture. Technical factors Since computer manufacturers have long implemented symmetric multiprocessing ( SMP ) designs using discrete CPUs, the issues regarding implementing multi-core processor architecture and supporting it with software are well known. Additionally : Using a proven processing - core design without architectural changes reduces design risk significantly. For general - purpose processors, much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the operating frequency. This is due to three primary factors : The memory wall ; the increasing gap between processor and memory speeds. This, in effect, pushes for cache sizes to be larger in order to mask the latency of memory. This helps only to the extent that memory bandwidth is not the bottleneck in performance. The ILP wall ; the increasing difficulty of finding enough parallelism in a single instruction stream to keep a high - performance single - core processor busy. The power wall ; the trend of consuming exponentially increasing power ( and thus also generating exponentially increasing heat ) with each factorial increase of operating frequency. This increase can be mitigated by `` shrinking '' the processor by using smaller traces for the same logic. The power wall poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the memory wall and ILP wall. In order to continue delivering regular performance improvements for general - purpose processors, manufacturers such as Intel and AMD have turned to multi-core designs, sacrificing lower manufacturing - costs for higher performance in some applications and systems. Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is the further integration of peripheral functions into the chip. Advantages The proximity of multiple CPU cores on the same die allows the cache coherency circuitry to operate at a much higher clock rate than what is possible if the signals have to travel off - chip. Combining equivalent CPUs on a single die significantly improves the performance of cache snoop ( alternative : Bus snooping ) operations. Put simply, this means that signals between different CPUs travel shorter distances, and therefore those signals degrade less. These higher - quality signals allow more data to be sent in a given time period, since individual signals can be shorter and do not need to be repeated as often. Assuming that the die can physically fit into the package, multi-core CPU designs require much less printed circuit board ( PCB ) space than do multi-chip SMP designs. Also, a dual - core processor uses slightly less power than two coupled single - core processors, principally because of the decreased power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the front - side bus ( FSB ). In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider - core design. Also, adding more cache suffers from diminishing returns. Multi-core chips also allow higher performance at lower energy. This can be a big factor in mobile devices that operate on batteries. Since each core in a multi-core CPU is generally more energy - efficient, the chip becomes more efficient than having a single large monolithic core. This allows higher performance with less energy. A challenge in this, however, is the additional overhead of writing parallel code. Disadvantages Maximizing the usage of the computing resources provided by multi-core processors requires adjustments both to the operating system ( OS ) support and to existing application software. Also, the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications. Integration of a multi-core chip can lower the chip production yields. They are also more difficult to manage thermally than lower - density single - core designs. Intel has partially countered this first problem by creating its quad - core designs by combining two dual - core ones on a single die with a unified cache, hence any two working dual - core dies can be used, as opposed to producing four cores on a single die and requiring all four to work to produce a quad - core CPU. From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence. Finally, raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real - world performance advantage. In a 2009 report, Dr Jun Ni showed that if a single core is close to being memory - bandwidth limited, then going to dual - core might give 30 % to 70 % improvement ; if memory bandwidth is not a problem, then a 90 % improvement can be expected ; however, Amdahl 's law makes this claim dubious. It would be possible for an application that used two CPUs to end up running faster on a single - core one if communication between the CPUs was the limiting factor, which would count as more than 100 % improvement. Hardware Trends The trend in processor development has been towards an ever - increasing number of cores, as processors with hundreds or even thousands of cores become theoretically possible. In addition, multi-core chips mixed with simultaneous multithreading, memory - on - chip, and special - purpose `` heterogeneous '' ( or asymmetric ) cores promise further performance and efficiency gains, especially in processing multimedia, recognition and networking applications. For example, a big. LITTLE core includes a high - performance core ( called ' big ' ) and a low - power core ( called ' LITTLE ' ). There is also a trend towards improving energy - efficiency by focusing on performance - per - watt with advanced fine - grain or ultra fine - grain power management and dynamic voltage and frequency scaling ( i.e. laptop computers and portable media players ). Chips designed from the outset for a large number of cores ( rather than having evolved from single core designs ) are sometimes referred to as manycore designs, emphasising qualitative differences. Architecture The composition and balance of the cores in multi-core architecture show great variety. Some architectures use one core design repeated consistently ( `` homogeneous '' ), while others use a mixture of different cores, each optimized for a different, `` heterogeneous '' role. The article `` CPU designers debate multi-core future '' by Rick Merritt, EE Times 2008, includes these comments : Chuck Moore (... ) suggested computers should be like cellphones, using a variety of specialty cores to run modular software scheduled by a high - level applications programming interface. (... ) Atsushi Hasegawa, a senior chief engineer at Renesas, generally agreed. He suggested the cellphone 's use of many specialty cores working in concert is a good model for future multi-core designs. (... ) Anant Agarwal, founder and chief executive of startup Tilera, took the opposing view. He said multi-core chips need to be homogeneous collections of general - purpose cores to keep the software model simple. Software effects An outdated version of an anti-virus application may create a new thread for a scan process, while its GUI thread waits for commands from the user ( e.g. cancel the scan ). In such cases, a multi-core architecture is of little benefit for the application itself due to the single thread doing all the heavy lifting and the inability to balance the work evenly across multiple cores. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult - to - find bugs due to the interweaving of processing on data shared between threads ( see thread - safety ). Consequently, such code is much more difficult to debug than single - threaded code when it breaks. There has been a perceived lack of motivation for writing consumer - level threaded applications because of the relative rarity of consumer - level demand for maximum use of computer hardware. Although threaded applications incur little additional performance penalty on single - processor machines, the extra overhead of development has been difficult to justify due to the preponderance of single - processor machines. Also, serial tasks like decoding the entropy encoding algorithms used in video codecs are impossible to parallelize because each result generated is used to help create the next result of the entropy decoding algorithm. Given the increasing emphasis on multi-core chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling. The telecommunications market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple - core processors for the datapath and the control plane. These MPUs are going to replace the traditional Network Processors that were based on proprietary microcode or picocode. Parallel programming techniques can benefit from multiple cores directly. Some existing parallel programming models such as Cilk Plus, OpenMP, OpenHMPP, FastFlow, Skandium, MPI, and Erlang can be used on multi-core platforms. Intel introduced a new abstraction for C++ parallelism called TBB. Other research efforts include the Codeplay Sieve System, Cray 's Chapel, Sun 's Fortress, and IBM 's X10. Multi-core processing has also affected the ability of modern computational software development. Developers programming in newer languages might find that their modern languages do not support multi-core functionality. This then requires the use of numerical libraries to access code written in languages like C and Fortran, which perform math computations faster than newer languages like C#. Intel 's MKL and AMD 's ACML are written in these native languages and take advantage of multi-core processing. Balancing the application workload across processors can be problematic, especially if they have different performance characteristics. There are different conceptual models to deal with the problem, for example using a coordination language and program building blocks ( programming libraries or higher - order functions ). Each block can have a different native implementation for each processor type. Users simply program using these abstractions and an intelligent compiler chooses the best implementation based on the context. Managing concurrency acquires a central role in developing parallel applications. The basic steps in designing parallel applications are : Partitioning The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield what is termed a fine - grained decomposition of a problem. Communication The tasks generated by a partition are intended to execute concurrently but can not, in general, execute independently. The computation to be performed in one task will typically require data associated with another task. Data must then be transferred between tasks so as to allow computation to proceed. This information flow is specified in the communication phase of a design. Agglomeration In the third stage, development moves from the abstract toward the concrete. Developers revisit decisions made in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. In particular, developers consider whether it is useful to combine, or agglomerate, tasks identified by the partitioning phase, so as to provide a smaller number of tasks, each of greater size. They also determine whether it is worthwhile to replicate data and computation. Mapping In the fourth and final stage of the design of parallel algorithms, the developers specify where each task is to execute. This mapping problem does not arise on uniprocessors or on shared - memory computers that provide automatic task scheduling. On the other hand, on the server side, multi-core processors are ideal because they allow many users to connect to a site simultaneously and have independent threads of execution. This allows for Web servers and application servers that have much better throughput. Licensing Vendors may license some software `` per processor ''. This can give rise to ambiguity, because a `` processor '' may consist either of a single core or of a combination of cores. Initially, for some of its enterprise software, Microsoft continued to use a per - socket licensing system. However, for some software such as BizTalk Server 2013, SQL Server 2014, and Windows Server 2016, Microsoft has shifted to per - core licensing. Oracle Corporation counts an AMD X2 or an Intel dual - core CPU as a single processor but uses other metrics for other types, especially for processors with more than two cores. Embedded applications Embedded computing operates in an area of processor technology distinct from that of `` mainstream '' PCs. The same technological drives towards multi-core apply here too. Indeed, in many cases the application is a `` natural '' fit for multi-core technologies, if the task can easily be partitioned between the different processors. In addition, embedded software is typically developed for a specific hardware release, making issues of software portability, legacy code or supporting independent developers less critical than is the case for PC or enterprise computing. As a result, it is easier for developers to adopt new technologies and as a result there is a greater variety of multi-core processing architectures and suppliers. As of 2010, multi-core network processing devices have become mainstream, with companies such as Freescale Semiconductor, Cavium Networks, Wintegra and Broadcom all manufacturing products with eight processors. For the system developer, a key challenge is how to exploit all the cores in these devices to achieve maximum networking performance at the system level, despite the performance limitations inherent in an SMP operating system. To address this issue, companies such as 6WIND provide portable packet processing software designed so that the networking data plane runs in a fast path environment outside the OS. In digital signal processing the same trend applies : Texas Instruments has the three - core TMS320C6488 and four - core TMS320C5441, Freescale the four - core MSC8144 and six - core MSC8156 ( and both have stated they are working on eight - core successors ). Newer entries include the Storm - 1 family from Stream Processors, Inc with 40 and 80 general purpose ALUs per chip, all programmable in C as a SIMD engine and Picochip with three - hundred processors on a single die, focused on communication applications. As of 2016 heterogeneous multi-core solutions are becoming more common : Xilinx Zynq UltraScale+ MPSoC has Quad - core ARM Cortex - A53 and Dual - core ARM Cortex - R5. Software solutions such as OpenAMP are being used to help with inter processor communication. Hardware examples This article may contain indiscriminate, excessive, or irrelevant examples. Please improve the article by adding more descriptive text and removing less pertinent examples. See Wikipedia 's guide to writing better articles for further suggestions. ( July 2016 ) Commercial Adapteva Epiphany, a many - core processor architecture which allows up to 4096 processors on - chip, although only a 16 core version has been commercially produced. Aeroflex Gaisler LEON3, a multi-core SPARC that also exists in a fault - tolerant version. Ageia PhysX, a multi-core physics processing unit. Ambric Am2045, a 336 - core Massively Parallel Processor Array ( MPPA ) AMD A-Series, dual -, triple -, and quad - core of Accelerated Processor Units ( APU ). Athlon 64, Athlon 64 FX and Athlon 64 X2 family, dual - core desktop processors. Athlon II, dual -, triple -, and quad - core desktop processors. FX - Series, quad -, 6 -, and 8 - core desktop processors. Opteron, dual -, quad -, 6 -, 8 -, 12 -, and 16 - core server / workstation processors. Phenom, dual -, triple -, and quad - core processors. Phenom II, dual -, triple -, quad -, and 6 - core desktop processors. Sempron X2, dual - core entry level processors. Turion 64 X2, dual - core laptop processors. Ryzen, quad -, 6 -, 8 -, 12 -, and 16 - core desktop processors Epyc, 8 -, 16 -, 24 -, and 32 - core server processors Radeon and FireStream multi-core GPU / GPGPU ( 10 cores, 16 5 - issue wide superscalar stream processors per core ) Analog Devices Blackfin BF561, a symmetrical dual - core processor ARM MPCore is a fully synthesizable multi-core container for ARM11 MPCore and ARM Cortex - A9 MPCore processor cores, intended for high - performance embedded and entertainment applications. ASOCS ModemX, up to 128 cores, wireless applications. Azul Systems Vega 1, a 24 - core processor, released in 2005. Vega 2, a 48 - core processor, released in 2006. Vega 3, a 54 - core processor, released in 2008. Broadcom SiByte SB1250, SB1255, SB1455 ; BCM 2836 quad - core ARM SoC ( designed for the Raspberry Pi 2 ) ClearSpeed CSX700, 192 - core processor, released in 2008 ( 32 / 64 - bit floating point ; Integer ALU ) Cradle Technologies CT3400 and CT3600, both multi-core DSPs. Cavium Networks Octeon, a 32 - core MIPS MPU. Coherent Logix hx3100 Processor, a 100 - core DSP / GPP processor Freescale Semiconductor QorIQ series processors, up to 8 cores, Power Architecture MPU. Hewlett - Packard PA - 8800 and PA - 8900, dual core PA - RISC processors. IBM POWER4, a dual - core PowerPC processor, released in 2001. POWER5, a dual - core PowerPC processor, released in 2004. POWER6, a dual - core PowerPC processor, released in 2007. POWER7, a 4, 6, 8 - core PowerPC processor, released in 2010. POWER8, a 12 - core PowerPC processor, released in 2013. PowerPC 970 MP, a dual - core PowerPC processor, used in the Apple Power Mac G5. Xenon, a triple - core, SMT - capable, PowerPC microprocessor used in the Microsoft Xbox 360 game console. z10, a quad - core z / Architecture processor, released in 2008 z196, a quad - core z / Architecture processor, released in 2010 zEC12, a six - core z / Architecture processor, released in 2012 z13, an eight - core z / Architecture processor, released in 2015 Infineon AURIX Danube, a dual - core, MIPS - based, home gateway processor. Intel Atom, single, dual - core and quad - core processors for netbook, tablets and smartphones systems. Celeron Dual - Core, the first dual - core processor for the budget / entry - level market. Core Duo, a dual - core processor. Core 2 Duo, a dual - core processor. Core 2 Quad, 2 dual - core dies packaged in a multi-chip module. Core i3, Core i5, Core i7 and Core i9 a family of dual -, quad -, 6 -, 8 -, 10 -, 12 -, 16 -, and 18 - core processors, the successor of the Core 2 Duo and the Core 2 Quad. Itanium 2, a dual - core processor. Pentium D, 2 single - core dies packaged in a multi-chip module. Pentium Extreme Edition, 2 single - core dies packaged in a multi-chip module. Pentium Dual - Core, a dual - core processor. Teraflops Research Chip ( Polaris ), a 3.16 GHz, 80 - core processor prototype, which the company originally stated would be released by 2011. Xeon dual -, quad -, 6 -, 8 -, 10 -, 12 -, 14 -, 15 -, 16 -, 18 -, 22 -, and 24 - core processors. Xeon Phi 57 - core, 60 - core and 61 - core processors. IntellaSys SEAforth 40C18, a 40 - core processor SEAforth24, a 24 - core processor designed by Charles H. Moore Kalray MPPA - 256, 256 - core processor, released 2012 ( 256 usable VLIW cores, Network - on - Chip ( NoC ), 32 / 64 - bit IEEE 754 compliant FPU ) NetLogic Microsystems XLP, a 32 - core, quad - threaded MIPS64 processor XLR, an eight - core, quad - threaded MIPS64 processor XLS, an eight - core, quad - threaded MIPS64 processor Nvidia GeForce 9 multi-core GPU ( 8 cores, 16 scalar stream processors per core ) GeForce 200 multi-core GPU ( 10 cores, 24 scalar stream processors per core ) Tesla multi-core GPGPU ( 10 cores, 24 scalar stream processors per core ) Parallax Propeller P8X32, an eight - core microcontroller. picoChip PC200 series 200 -- 300 cores per device for DSP & wireless Plurality HAL series tightly coupled 16 - 256 cores, L1 shared memory, hardware synchronized processor. Rapport Kilocore KC256, a 257 - core microcontroller with a PowerPC core and 256 8 - bit `` processing elements ''. SiCortex `` SiCortex node '' has six MIPS64 cores on a single chip. Sony / IBM / Toshiba 's Cell processor, a nine - core processor with one general purpose PowerPC core and eight specialized SPUs ( Synergystic Processing Unit ) optimized for vector operations used in the Sony PlayStation 3 Sun Microsystems MAJC 5200, two - core VLIW processor UltraSPARC IV and UltraSPARC IV+, dual - core processors. UltraSPARC T1, an eight - core, 32 - thread processor. UltraSPARC T2, an eight - core, 64 - concurrent - thread processor. UltraSPARC T3, a sixteen - core, 128 - concurrent - thread processor. SPARC T4, an eight - core, 64 - concurrent - thread processor. SPARC T5, a sixteen - core, 128 - concurrent - thread processor. Texas Instruments TMS320C80 MVP, a five - core multimedia video processor. TMS320TMS320C66, 2, 4, 8 core dsp. Tilera TILE64, a 64 - core 32 - bit processor TILE - Gx, a 72 - core 64 - bit processor XMOS Software Defined Silicon quad - core XS1 - G4 Free OpenSPARC Academic MIT, 16 - core RAW processor University of California, Davis, Asynchronous array of simple processors ( AsAP ) 36 - core 610 MHz AsAP 167 - core 1.2 GHz AsAP2 University of Washington, Wavescalar processor University of Texas, Austin, TRIPS processor Linköping University, Sweden, ePUMA processor UC Davis, KiloCore, a 1000 core 1.78 GHz processor on a 32 nm IBM process Benchmarks The research and development of multicore processors often compares many options, and benchmarks are developed to help such evaluations. Existing benchmarks include SPLASH - 2, PARSEC, and COSMIC for heterogeneous systems. Notes ^ Digital signal processors ( DSPs ) have used multi-core architectures for much longer than high - end general - purpose processors. A typical example of a DSP - specific implementation would be a combination of a RISC CPU and a DSP MPU. This allows for the design of products that require a general - purpose processor for user interfaces and a DSP for real - time data processing ; this type of design is common in mobile phones. In other applications, a growing number of companies have developed multi-core DSPs with very large numbers of processors. ^ Two types of operating systems are able to use a dual - CPU multiprocessor : partitioned multiprocessing and symmetric multiprocessing ( SMP ). In a partitioned architecture, each CPU boots into separate segments of physical memory and operate independently ; in an SMP OS, processors work in a shared space, executing threads within the OS independently. See also Race condition Multicore Association Manycore Hyper - threading Multitasking Parallel random access machine Partitioned global address space ( PGAS ) Thread CPU shielding GPGPU CUDA OpenCL ( Open Computing Language ) -- a framework for heterogeneous execution References Jump up ^ Margaret Rouse ( March 27, 2007 ). `` Definition : multi-core processor ''. TechTarget. Archived from the original on August 5, 2010. Retrieved March 6, 2013. Jump up ^ Bryan Schauer. `` Multicore Processors - A Necessity '' ( PDF ). Archived from the original ( PDF ) on 2011 - 11 - 25. Jump up ^ Aater Suleman ( May 20, 2011 ). `` What makes parallel programming hard ? ''. FutureChips. Archived from the original on May 29, 2011. Retrieved March 6, 2013. Jump up ^ András Vajda. Programming Many - Core Chips. Springer. p. 3. ISBN 978 - 1 - 4419 - 9739 - 5. Jump up ^ Ryan Shrout ( December 2, 2009 ). `` Intel Shows 48 - core x86 Processor as Single - chip Cloud Computer ''. Archived from the original on January 5, 2016. Retrieved May 17, 2015. Jump up ^ `` Intel unveils 48 - core cloud computing silicon chip ''. BBC. December 3, 2009. Archived from the original on December 6, 2012. Retrieved March 6, 2013. Jump up ^ Patterson, David A. `` Future of computer architecture. '' Berkeley EECS Annual Research Symposium ( BEARS ), College of Engineering, UC Berkeley, US. 2006. Jump up ^ Aater Suleman ( May 19, 2011 ). `` Q & A : Do multicores save energy ? Not really ''. Archived from the original on December 16, 2012. Retrieved March 6, 2013. Jump up ^ Ni, Jun. `` Enabling Technology of Multi-core Computing for Medical Imaging '' ( PDF ). Archived from the original ( PDF ) on 2010 - 07 - 05. Retrieved 17 February 2013. Jump up ^ Clark, Jack. `` Intel : Why a 1,000 - core chip is feasible ''. ZDNet. Archived from the original on 6 August 2015. Retrieved 6 August 2015. Jump up ^ Sparsh Mittal ( February 2016 ). `` A Survey Of Techniques for Architecting and Managing Asymmetric Multicore Processors ''. ACM Computing Surveys. 48 ( 3 ). doi : 10.1145 / 2856125. Archived from the original on 2017 - 06 - 18. Jump up ^ Rick Merritt ( February 6, 2008 ). `` CPU designers debate multi-core future ''. EE Times. Archived from the original on November 14, 2012. Retrieved March 6, 2013. Jump up ^ `` Multicore Packet Processing Forum ''. Archived from the original on 2009 - 12 - 21. Jump up ^ John Darlinton ; Moustafa Ghanem ; Yike Guo ; Hing Wing To ( 1996 ). `` Guided Resource Organisation in Heterogeneous Parallel Computing ''. Journal of High Performance Computing. 4 ( 1 ) : 13 -- 23. Archived from the original on 2013 - 06 - 08. Jump up ^ Bright, Peter ( 4 December 2015 ). `` Windows Server 2016 moving to per core, not per socket, licensing ''. Ars Technica. Condé Nast. Archived from the original on 4 December 2015. Retrieved 5 December 2015. Jump up ^ Compare : `` The Licensing Of Oracle Technology Products ''. OMT - CO Operations Management Technology Consulting GmbH. Archived from the original on 2014 - 03 - 21. Retrieved 2014 - 03 - 04. Jump up ^ `` 6WINDGATE Software : Network Optimization Software - SDN Software - Control Plane Software 6WIND ''. Jump up ^ Mike Zazaian ( September 26, 2006 ). `` Intel : 80 Cores by 2011 ''. Archived from the original on 2006 - 11 - 09. Jump up ^ Cyril Kowaliski ( February 18, 2014 ). `` Intel releases 15 - core Xeon E7 v2 processor ''. Archived from the original on 2014 - 10 - 11. Jump up ^ `` Intel Xeon Processor E7 v3 Family ''. Intel. Archived from the original on 2015 - 07 - 07. Jump up ^ `` Intel Xeon Processor E7 v2 Family ''. Intel. Archived from the original on 2015 - 07 - 07. Jump up ^ `` Intel Xeon Processor E3 v2 Family ''. Intel. Archived from the original on 2015 - 07 - 07. Jump up ^ Bernard Cole ( September 24, 2008 ). `` 40 - core processor with Forth - based IDE tools unveiled ''. Jump up ^ Brad Chacos ( June 20, 2016 ). `` Meet KiloCore, a 1,000 - core processor so efficient it could run on a AA battery ''. PC World. Archived from the original on June 23, 2016. Jump up ^ `` COSMIC Heterogeneous Multiprocessor Benchmark Suite ''. Archived from the original on 2015 - 07 - 03. Further reading Khondker S. Hasan, John Antonio, Sridhar Radhakrishnan. A New Composite CPU / Memory Model for Predicting Efficiency of Multi-core Processing. The 20th IEEE International Conference on High Performance Computer Architecture ( HPCA - 14 ) workshop. Orlando, FL, USA. doi : 10.13140 / RG. 2.1. 3051.9207. CS1 maint : Uses authors parameter ( link ) Khondker S. Hasan, Nicolas G. Grounds, John K. Antonio ( July 2011 ). Predicting CPU Availability of a Multi-core Processor Executing Concurrent Java Threads. 17th International Conference on Parallel and Distributed Processing Techniques and Applications ( PDPTA - 11 ). Las Vegas, Nevada, USA. pp. 551 -- 557. CS1 maint : Uses authors parameter ( link ) External links What Is A Processor Core ? Embedded moves to multicore Multicore News blog IEEE : Multicore Is Bad News For Supercomputers Architecting solutions for the Manycore future, published on Feb 19, 2010 ( more than one dead link in the slide ) CPU technologies Architecture Turing machine Post -- Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite - state machine Queue automaton Von Neumann Harvard ( modified ) Dataflow TTA Cellular Artificial neural network Machine learning Deep learning Neural processing unit ( NPU ) Convolutional neural network Load / store architecture Register memory architecture Endianness FIFO Zero - copy NUMA HUMA HSA Mobile computing Surface computing Wearable computing Heterogeneous computing Parallel computing Concurrent computing Distributed computing Cloud computing Amorphous computing Ubiquitous computing Fabric computing Cognitive computing Unconventional computing Hypercomputation Quantum computing Adiabatic quantum computing Linear optical quantum computing Reversible computing Reverse computation Reconfigurable computing Optical computing Ternary computer Analogous computing Mechanical computing Hybrid computing Digital computing DNA computing Peptide computing Chemical computing Organic computing Wetware computing Neuromorphic computing Symmetric multiprocessing ( SMP ) Asymmetric multiprocessing ( AMP ) Cache hierarchy Memory hierarchy ISA types ASIP CISC RISC EDGE ( TRIPS ) VLIW ( EPIC ) MISC OISC NISC ZISC Comparison ISAs x86 z / Architecture ARM MIPS Power Architecture ( PowerPC ) SPARC Mill Itanium ( IA - 64 ) Alpha Prism SuperH V850 Clipper VAX Unicore PA - RISC MicroBlaze RISC - V Word size 1 - bit 2 - bit 4 - bit 8 - bit 9 - bit 10 - bit 12 - bit 15 - bit 16 - bit 18 - bit 22 - bit 24 - bit 25 - bit 26 - bit 27 - bit 31 - bit 32 - bit 33 - bit 34 - bit 36 - bit 39 - bit 40 - bit 48 - bit 50 - bit 60 - bit 64 - bit 128 - bit 256 - bit 512 - bit Variable Execution Instruction pipelining Bubble Operand forwarding Out - of - order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards Parallel level Bit Bit - serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Multithreading Temporal Simultaneous ( SMT ) ( Hyper - threading ) Speculative ( SpMT ) Preemptive Cooperative Clustered Multi-Thread ( CMT ) Hardware scout Flynn 's taxonomy SISD SIMD ( SWAR ) SIMT MISD MIMD SPMD Addressing mode CPU performance Instructions per second ( IPS ) Instructions per clock ( IPC ) Cycles per instruction ( CPI ) Floating - point operations per second ( FLOPS ) Transactions per second ( TPS ) Synaptic Updates Per Second ( SUPS ) Performance per watt Orders of magnitude ( computing ) Cache performance measurement and metric Core count Single - core processor Multi-core processor Manycore processor Types Central processing unit ( CPU ) GPGPU AI accelerator Vision processing unit ( VPU ) Vector processor Barrel processor Stream processor Digital signal processor ( DSP ) I / O processor / DMA controller Network processor Baseband processor Physics processing unit ( PPU ) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low - voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module ( MCM ) Chip stack multi-chip modules System on a chip ( SoC ) Multiprocessor system - on - chip ( MPSoC ) Programmable System - on - Chip ( PSoC ) Network on a chip ( NoC ) Components Execution unit ( EU ) Arithmetic logic unit ( ALU ) Address generation unit ( AGU ) Floating - point unit ( FPU ) Load - store unit ( LSU ) Branch predictor Unified Reservation Station Barrel shifter Uncore Sum addressed decoder ( SAD ) Front - side bus Back - side bus Northbridge ( computing ) Southbridge ( computing ) Adder ( electronics ) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit ( MMU ) Input -- output memory management unit ( IOMMU ) Integrated Memory Controller ( IMC ) Power Management Unit ( PMU ) Translation lookaside buffer ( TLB ) Stack engine Register file Processor register Hardware register Memory buffer register ( MBR ) Program counter Microcode ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three - dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed - signal integrated circuit Power management integrated circuit Quantum circuit Logic gate Combinational logic Sequential logic Emitter - coupled logic ( ECL ) Transistor -- transistor logic ( TTL ) Glue logic Quantum gate Gate array Counter ( digital ) Bus ( computing ) Semiconductor device Clock rate CPU multiplier Vision chip Memristor Power management APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating Hardware security Non-executable memory ( NX bit ) Memory Protection Extensions ( Intel MPX ) Intel Secure Key Hardware restriction ( firmware ) Software Guard Extensions ( Intel SGX ) Trusted Execution Technology Trusted Platform Module ( TPM ) Secure cryptoprocessor Hardware security module Hengzhi chip Related History of general - purpose CPUs Parallel computing General Distributed computing Parallel computing Massively parallel Cloud computing High - performance computing Multiprocessing Manycore processor GPGPU Computer network Systolic array Levels Bit Instruction Thread Task Data Memory Loop Pipeline Multithreading Temporal Simultaneous ( SMT ) Speculative ( SpMT ) Preemptive Cooperative Clustered Multi-Thread ( CMT ) Hardware scout Theory PRAM model Analysis of parallel algorithms Amdahl 's law Gustafson 's law Cost efficiency Karp -- Flatt metric Slowdown Speedup Elements Process Thread Fiber Instruction window Coordination Multiprocessing Memory coherency Cache coherency Cache invalidation Barrier Synchronization Application checkpointing Programming Stream processing Dataflow programming Models Implicit parallelism Explicit parallelism Concurrency Non-blocking algorithm Hardware Flynn 's taxonomy SISD SIMD SIMT MISD MIMD Dataflow architecture Pipelined processor Superscalar processor Vector processor Multiprocessor symmetric asymmetric Memory shared distributed distributed shared UMA NUMA COMA Massively parallel computer Computer cluster Grid computer APIs Ateji PX Boost. Thread Chapel Charm++ Cilk Coarray Fortran CUDA Dryad C++ AMP Global Arrays MPI OpenMP OpenCL OpenHMPP OpenACC TPL PLINQ PVM POSIX Threads RaftLib UPC TBB ZPL Problems Deadlock Livelock Deterministic algorithm Embarrassingly parallel Parallel slowdown Race condition Software lockout Scalability Starvation Category : parallel computing Media related to Parallel computing at Wikimedia Commons GND : 7598578 - 0 Retrieved from `` https://en.wikipedia.org/w/index.php?title=Multi-core_processor&oldid=829856649 '' Categories : Computer architecture Digital signal processing Microprocessors Parallel computing Flynn 's taxonomy Hidden categories : All articles with unsourced statements Articles with unsourced statements from February 2011 Articles with unsourced statements from March 2015 Articles containing potentially dated statements from 2010 All articles containing potentially dated statements Articles containing potentially dated statements from 2016 Articles with too many examples Pages using div col with deprecated parameters CS1 maint : Uses authors parameter Wikipedia articles with GND identifiers Talk Contents About Wikipedia Български Català Čeština Dansk Deutsch Eesti Español فارسی Français 한국어 Hrvatski Italiano Қазақша Македонски Nederlands 日本 語 Norsk Polski Português Română Русский Simple English Српски / srpski Suomi ไทย Türkçe Українська Tiếng Việt 中文 21 more Edit links This page was last edited on 11 March 2018, at 05 : 48. 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Question: what is the function of core in processor
Answer: which read and execute program instructions