Control unit - wikipedia Control unit This article is about the component of a computer 's CPU. For other uses, see Control unit ( disambiguation ). The control unit ( CU ) is a component of a computer 's central processing unit ( CPU ) that directs the operation of the processor. It tells the computer 's memory, arithmetic / logic unit and input and output devices how to respond to a program 's instructions. It directs the operation of the other units by providing timing and control signals. Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. John von Neumann included the control unit as part of the von Neumann architecture. In modern computer designs, the control unit is typically an internal part of the CPU with its overall role and operation unchanged since its introduction. Contents 1 Functions of the control unit 2 Hardwired control unit 3 Microprogram control unit 4 See also 5 References Functions of the control unit The Control Unit ( CU ) is digital circuitry contained within the processor that coordinates the sequence of data movements into, out of, and between a processor 's many sub-units. The result of these routed data movements through various digital circuits ( sub-units ) within the processor produces the manipulated data expected by a software instruction ( loaded earlier, likely from memory ). It controls ( conducts ) data flow inside the processor and additionally provides several external control signals to the rest of the computer to further direct data and instructions to / from processor external destinations ( i.e. memory ). Examples of devices that require a CU are CPUs and graphics processing units ( GPUs ). The CU receives external instructions or commands which it converts into a sequence of control signals that the CU applies to the data path to implement a sequence of register - transfer level operations. More precisely, the Control Unit ( CU ) is generally a sizable collection of complex digital circuitry interconnecting and controlling the many execution units ( i.e. ALU, data buffers, registers ) contained within a CPU. The CU is normally the first CPU unit to accept from an externally stored computer program, a single instruction ( based on the CPU 's instruction set ). The CU then decodes this individual instruction into several sequential steps ( fetching addresses / data from registers / memory, managing execution ( i.e. data sent to the ALU or I / O ), and storing the resulting data back into registers / memory ) that controls and coordinates the CPU 's inner works to properly manipulate the data. The design of these sequential steps are based on the needs of each instruction and can range in number of steps, the order of execution, and which units are enabled. Thus by only using a program of set instructions in memory, the CU will configure all the CPU 's data flows as needed to manipulate the data correctly between instructions. This results in a computer that could run a complete program and require no human intervention to make hardware changes between instructions ( as had to be done when using only punch cards for computations before stored programmed computers with CUs where invented ). These detailed steps from the CU dictate which of the CPU 's interconnecting hardware control signals to enable / disable or which CPU units are selected / de-selected and the unit 's proper order of execution as required by the instruction 's operation to produce the desired manipulated data. Additionally, the CU 's orderly hardware coordination properly sequences these control signals then configures the many hardware units comprising the CPU, directing how data should also be moved, changed, and stored outside the CPU ( i.e. memory ) according to the instruction 's objective. Depending on the type of instruction entering the CU, the order and number of sequential steps produced by the CU could vary the selection and configuration of which parts of the CPU 's hardware are utilized to achieve the instruction 's objective ( mainly moving, storing, and modifying data within the CPU ). This one feature, that efficiently uses just software instructions to control / select / configure a computer 's CPU hardware ( via the CU ) and eventually manipulates a program 's data, is a significant reason most modern computers are flexible and universal when running various programs. As compared to some 1930s or 1940s computers without a proper CU, they often required rewiring their hardware when changing programs. This CU instruction decode process is then repeated when the Program Counter is incremented to the next stored program address and the new instruction enters the CU from that address, and so on till the programs end. Other more advanced forms of Control Units manage the translation of instructions ( but not the data containing portion ) into several micro-instructions and the CU manages the scheduling of the micro-instructions between the selected execution units to which the data is then channeled and changed according to the execution unit 's function ( i.e., ALU contains several functions ). On some processors, the Control Unit may be further broken down into additional units, such as an instruction unit or scheduling unit to handle scheduling, or a retirement unit to deal with results coming from the instruction pipeline. Again, the Control Unit orchestrates the main functions of the CPU : carrying out stored instructions in the software program then directing the flow of data throughout the computer based upon these instructions ( roughly likened to how traffic lights will systematically control the flow of cars ( containing data ) to different locations within the traffic grid ( CPU ) until it parks at the desired parking spot ( memory address / register ). The car occupants ( data ) then go into the building ( execution unit ) and comes back changed in some way then get back into the car and returns to another location via the controlled traffic grid ). Hardwired control unit Hardwired control units are implemented through use of combinational logic units, featuring a finite number of gates that can generate specific results based on the instructions that were used to invoke those responses. Hardwired control units are generally faster than microprogrammed designs. Their design uses a fixed architecture -- it requires changes in the wiring if the instruction set is modified or changed. This architecture is preferred in reduced instruction set computers ( RISC ) as they use a simpler instruction set. A controller that uses this approach can operate at high speed ; however, it has little flexibility, and the complexity of the instruction set it can implement is limited. The hardwired approach has become less popular as computers have evolved. Previously, control units for CPUs used ad - hoc logic, and they were difficult to design. Microprogram control unit Main article : Microcode The idea of microprogramming was introduced by Maurice Wilkes in 1951 as an intermediate level to execute computer program instructions. Microprograms were organized as a sequence of microinstructions and stored in special control memory. The algorithm for the microprogram control unit is usually specified by flowchart description. The main advantage of the microprogram control unit is the simplicity of its structure. Outputs of the controller are organized in microinstructions and they can be easily replaced. See also CPU design Computer architecture Richards controller Controller ( computing ) References Jump up ^ Patterson, David ; Hennessy, John ( 2012 ). Computer Organization and Design : The Hardware / Software Interface, 4th ed., revised. Morgan Kaufmann. ISBN 978 - 0 - 12 - 374750 - 1. Jump up ^ von Neumann, John ( 1945 ), First Draft of a Report on the EDVAC ( PDF ), Moore School of Electrical Engineering, University of Pennsylvania, archived from the original ( PDF ) on March 14, 2013 Jump up ^ Englander, Irv ( 2009 ). The Architecture of Computer Hardware, Systems Software, & Networking, 4th Ed. Hoboken : John Wiley & Sons, Inc. Jump up ^ `` MICRO-PROGRAMMED VERSUS HARDWIRED CONTROL UNITS ; ''. www.cs.binghamton.edu. Retrieved 2017 - 02 - 17. Jump up ^ Barkalov, Alexander ( 2009 ). Logic synthesis for FSM based control units / Alexander Barkalov and Larysa Titarenko. Berlin : Springer. ISBN 978 - 3 - 642 - 04308 - 6. Jump up ^ Wiśniewski, Remigiusz ( 2009 ). Synthesis of compositional microprogram control units for programmable devices. Zielona Góra : University of Zielona Góra. p. 153. ISBN 978 - 83 - 7481 - 293 - 1. CPU technologies Architecture Turing machine Post -- Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite - state machine Queue automaton Von Neumann Harvard ( modified ) HIVE ( Hierarchical Identify Verify Exploit ) Dataflow TTA Cellular Artificial neural network Machine learning Deep learning Neural processing unit ( NPU ) Convolutional neural network Load / store architecture Register memory architecture Register register architecture Endianness FIFO Zero - copy NUMA HUMA HSA Mobile computing Surface computing Wearable computing Heterogeneous computing Parallel computing Concurrent computing Distributed computing Cloud computing Amorphous computing Ubiquitous computing Fabric computing Reconfigurable computing Cognitive computing Analogous computing Mechanical computing Electric computing Hybrid computing Digital computing DNA computing Peptide computing Chemical computing Organic computing Wetware computing Quantum computing Neuromorphic computing Optical computing Reversible computing Unconventional computing Hypercomputation Ternary computer Symmetric multiprocessing ( SMP ) Asymmetric multiprocessing ( AMP ) Cache hierarchy Memory hierarchy ISA types ASIP CISC RISC EDGE ( TRIPS ) VLIW ( EPIC ) MISC OISC NISC ZISC Comparison ISAs x86 z / Architecture ARM MIPS Power Architecture ( PowerPC ) SPARC VISC Mill Itanium ( IA - 64 ) Alpha Prism SuperH Clipper VAX Unicore PA - RISC MicroBlaze Word size 1 - bit 2 - bit 4 - bit 8 - bit 9 - bit 10 - bit 12 - bit 15 - bit 16 - bit 18 - bit 22 - bit 24 - bit 25 - bit 26 - bit 27 - bit 31 - bit 32 - bit 33 - bit 34 - bit 36 - bit 39 - bit 40 - bit 48 - bit 50 - bit 60 - bit 64 - bit 128 - bit 256 - bit 512 - bit Variable Execution Instruction pipelining Bubble Operand forwarding Out - of - order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards Parallel level Bit Bit - serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Multithreading Temporal Simultaneous ( SMT ) ( Hyper - threading ) Speculative ( SpMT ) Preemptive Cooperative Clustered Multi-Thread ( CMT ) Hardware scout Flynn 's taxonomy SISD SIMD ( SWAR ) SIMT MISD MIMD SPMD Addressing mode CPU performance Instructions per second ( IPS ) Instructions per clock ( IPC ) Cycles per instruction ( CPI ) Floating - point operations per second ( FLOPS ) Transactions per second ( TPS ) Synaptic Updates Per Second ( SUPS ) Performance per watt Orders of magnitude ( computing ) Cache performance measurement and metric Core count Single - core processor Multi-core processor Manycore processor Types Central processing unit ( CPU ) GPGPU AI accelerator Vision processing unit ( VPU ) Vector processor Barrel processor Stream processor Digital signal processor ( DSP ) I / O processor / DMA controller Network processor Baseband processor Physics processing unit ( PPU ) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low - voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module ( MCM ) Chip stack multi-chip modules System on a chip ( SoC ) Multiprocessor system - on - chip ( MPSoC ) Programmable System - on - Chip ( PSoC ) Network on a chip ( NoC ) Components Execution unit ( EU ) Arithmetic logic unit ( ALU ) Address generation unit ( AGU ) Floating - point unit ( FPU ) Load - store unit ( LSU ) Fixed - point unit ( FXU ) Vector unit ( VU ) Branch predictor Branch execution unit ( BEU ) Instruction Decoder Instruction Scheduler Instruction Fetch Unit Instruction Dispatch Unit Instruction Sequencing Unit Unified Reservation Station Barrel shifter Uncore Sum addressed decoder ( SAD ) Front - side bus Back - side bus Northbridge ( computing ) Southbridge ( computing ) Adder ( electronics ) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit ( MMU ) Input -- output memory management unit ( IOMMU ) Integrated Memory Controller ( IMC ) Power Management Unit ( PMU ) Translation lookaside buffer ( TLB ) Stack engine Register file Processor register Hardware register Memory buffer register ( MBR ) Program counter Microcode ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three - dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed - signal integrated circuit Power management integrated circuit Quantum circuit Logic gate Combinational logic Sequential logic Emitter - coupled logic ( ECL ) Transistor -- transistor logic ( TTL ) Glue logic Quantum gate Gate array Counter ( digital ) Bus ( computing ) Semiconductor device Clock rate CPU multiplier Vision chip Memristor Power management APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating Hardware security Non-executable memory ( NX bit ) Memory Protection Extensions ( Intel MPX ) Intel Secure Key Hardware restriction ( firmware ) Software Guard Extensions ( Intel SGX ) Trusted Execution Technology OmniShield Trusted Platform Module ( TPM ) Secure cryptoprocessor Hardware security module Hengzhi chip Related History of general - purpose CPUs Retrieved from `` https://en.wikipedia.org/w/index.php?title=Control_unit&oldid=813174009 '' Categories : Central processing unit Digital electronics Hidden categories : All articles with unsourced statements Articles with unsourced statements from July 2014 Talk Contents About Wikipedia Català Čeština Deutsch Español Esperanto Euskara فارسی Français Galego 한국어 Hrvatski Bahasa Indonesia Italiano עברית Македонски Nederlands 日本 語 ਪੰਜਾਬੀ Português Русский Simple English Српски / srpski Svenska Українська اردو 中文 Edit links This page was last edited on 2 December 2017, at 06 : 18. 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Question: where do the control units instructions come from
Answer: a program