Intel Core (microarchitecture)
Steppings using 65 nm process

Intel Core (microarchitecture)

Section Title: Steppings using 65 nm process
Table Section Text: None

Mobile (Merom)	Desktop (Conroe)	Desktop (Kentsfield)	Server (Woodcrest, Clovertown, Tigerton)

Stepping	Released	Area	CPUID	L2 cache	Max. clock	Celeron	Pentium	Core 2	Celeron	Pentium	Core 2	Xeon	Core 2	Xeon	Xeon

B2	Jul 2006	143 mm²	06F6	4 MiB	2.93 GHz	M5xx	T5000 T7000 L7000	E6000 X6000	3000	5100

B3	Nov 2006	143 mm²	06F7	4 MiB	3.00 GHz	Q6000 QX6000	3200	5300

L2	Jan 2007	111 mm²	06F2	2 MiB	2.13 GHz	T5000 U7000	E2000	E4000 E6000	3000

E1	May 2007	143 mm²	06FA	4 MiB	2.80 GHz	M5xx	T7000 L7000 X7000

G0	Apr 2007	143 mm²	06FB	4 MiB	3.00 GHz	M5xx	T7000 L7000 X7000	E2000	E4000 E6000	3000	Q6000 QX6000	3200	5100 5300 7200 7300

G2	Mar 2009	143 mm²	06FB	4 MiB	2.16 GHz	M5xx	T5000 T7000 L7000

M0	Jul 2007	111 mm²	06FD	2 MiB	2.40 GHz	5xx T1000	T2000 T3000	T5000 T7000 U7000	E1000	E2000	E4000

A1	Jun 2007	81 mm²	10661	1 MiB	2.20 GHz	M5xx	U2000	220 4x0

Sentence(s)

The Intel Core is stepping A1 of cpuid 10661h, with 1 MiB L2 cache.

final_sentence: The Intel Core is stepping A1 of cpuid 10661h, with 1 MiB L2 cache.