Itanium
Released processors

Itanium

Section Title: Released processors
Table Section Text: None

Codename	process	Released	Clock	L2 Cache/ core	L3 Cache/ processor	Bus	dies/ dev.	cores/ die	watts/ dev.	Comments

Itanium

Merced	180 nm	2001-06	733 MHz	96 KB	none	266 MHz	1	1	116	2 MB off-die L3 cache

800 MHz	130	4 MB off-die L3 cache

Itanium 2

McKinley	180 nm	2002-07-08	900 MHz	256 KB	1.5 MB	400 MHz	1	1	130	HW branchlong

1 GHz	3 MB	130

Madison	130 nm	2003-06-30	1.3 GHz	3 MB	130

1.4 GHz	4 MB	130

1.5 GHz	6 MB	130

2003-09-08	1.4 GHz	1.5 MB	130

2004-04	1.4 GHz	3 MB	130

1.6 GHz

Deerfield	2003-09-08	1.0 GHz	1.5 MB	62	Low voltage

Hondo	2004-Q1	1.1 GHz	4 MB	400 MHz	2	1	260	32 MB L4

Fanwood	2004-11-08	1.6 GHz	3 MB	533 MHz	1	1	130

1.3 GHz	400 MHz	62?	Low voltage

Madison	2004-11-08	1.6 GHz	9 MB	400 MHz	130

2005-07-05	1.67 GHz	6 MB	667 MHz	130

2005-07-18	1.67 GHz	9 MB	667 MHz	130

Itanium 2 9000 series

Montecito	90 nm	2006-07-18	1.4 GHz	256 KB (D)+ 1 MB (I)	6–24 MB	400 MHz	1	2	104	Virtualization, Multithread, no HW IA-32

1.6 GHz	533 MHz

Itanium 2 9100 series

Montvale	90 nm	2007-10-31	1.42– 1.66 GHz	256 KB (D)+ 1 MB (I)	8–24 MB	400– 667 MHz	1	1–2	75–104	Core-level lockstep, demand-based switching

Itanium 9300 series

Tukwila	65 nm	2010-02-08	1.33– 1.73 GHz	256 KB (D)+ 512 KB (I)	10–24 MB	QPI with 4.8 GT/s	1	2–4	130–185	A new point-to-point processor interconnect, the QPI, replacing the FSB. Turbo Boost

Itanium 9500 series

Poulson	32 nm	2012-11-08	1.73– 2.53 GHz	256 KB (D)+ 512 KB (I)	20–32 MB	QPI with 6.4 GT/s	1	4–8	130–170	Doubled issue width (from 6 to 12 instructions per cycle), Instruction Replay technology, Dual-domain hyperthreading

Itanium 9700 series

Kittson	32 nm	2017-05-11	1.73– 2.66 GHz	256 KB (D)+ 512 KB (I)	20–32 MB	QPI with 6.4 GT/s	1	4–8	130–170	No architectural improvements over Poulson, 5 % higher clock for the top model

Codename	process	Released	Clock	L2 Cache/ core	L3 Cache/ processor	Bus	dies/ dev.	cores/ die	watts/ dev.	Comments

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