领域：学术论文 · 应用学科

In recent years, with the rapid development of technologies such as artificial intelligence (AI), the Internet of Things (IoT), and 5G communication, a new wave of information technology revolution has emerged. AI technology, serving as the "central brain" that powers smart manufacturing, smart cities, and the metaverse, plays a pivotal role in the digital era. It is widely acknowledged that algorithms, data, and computational power (chips) are the three core elements driving AI development, with chips forming the foundation for the practical implementation of AI.
As research on large models such as ChatGPT and GPT-4 continues to progress, model structures are becoming increasingly complex, and the demand for data and computational resources is growing exponentially. Simultaneously, the gradual diminishing of Moore’s Law has slowed the evolution of chip manufacturing processes. The disparity between algorithm development and hardware advancement poses a significant challenge: how to efficiently process massive datasets using complex algorithms has become a pressing issue in the AI domain.
The root cause of this challenge lies in the limitations of chips, which are currently constrained by the "von Neumann architecture bottleneck." In von Neumann architecture, data storage and processing are separated, and data is transferred between memory and processors through buses. Frequent data transfers incur substantial time and energy costs, leading to what is termed the "memory wall" and the "power wall." Moreover, as device sizes approach physical limits, the traditional approach of improving chip performance solely through process advancements faces increasing obstacles, resulting in the so-called "process wall."
To address these challenges, academia and industry worldwide have conducted extensive research from multiple dimensions, including architecture, process, and integration, to explore new-generation chip technologies for the post-Moore era. For instance, dataflow architecture chips enable streaming computation, achieving significantly higher throughput than von Neumann architecture for large-scale AI data processing; reconfigurable chips provide high flexibility and energy-efficient computation through software-defined hardware circuit structures; wafer-scale chips expand chip area using advanced process technologies to enhance computational power; and 3D chips stack multiple chips vertically using 3D integration packaging technology to achieve high bandwidth and computational power. Among these, in-memory computing chips stand out by integrating storage and computation through collaborative innovation across devices, architectures, circuits, and processes, fundamentally overcoming the von Neumann architecture bottleneck.
In-memory computing chips have architectural features that significantly reduce data transfer overhead, addressing the "memory wall" and "power wall." Additionally, their highly parallel computing capabilities enable performance comparable to that of advanced processes, even with relatively mature process nodes, thereby alleviating the pressure of process miniaturization. Furthermore, in-memory computing technology seamlessly integrates with other advanced technologies, such as reconfigurable chips, wafer-scale chips, and 3D integration, making it one of the most promising directions in post-Moore era chip technology.
The concept of in-memory computing can be traced back to the 1970s when Kautz from the Stanford Research Institute first proposed the idea. The core principle is to perform computation directly within memory, reducing the overhead of data transfer between memory and processors. Subsequent research has focused on chip circuit structures, computational architectures, and system applications. However, due to the complexity of circuit design and the difficulty of implementation, most of the early research effectively realized "near-memory computing." The main distinction between near-memory and in-memory computing is that the former still requires data to be read out of memory for computation, with the results then stored back into memory. Current industry-standard solutions for near-memory computing include techniques such as 3D packaging and high-bandwidth memory (HBM) to shorten the distance between memory and processors and increase data bandwidth. These technologies are relatively mature and have been scaled into mass production.
Leading semiconductor companies such as AMD, Intel, Samsung, and SK Hynix have introduced near-memory computing chips based on HBM and 2.5D/3D packaging technologies. For example, Samsung’s latest HBM3 Icebolt technology employs a near-memory computing architecture, utilizing 12 layers of 10nm-class dynamic random-access memory (DRAM) to achieve processing speeds of up to 6.4 Gbps and bandwidths of up to 819 GB/s.
However, near-memory computing still adheres to the von Neumann architecture, which fundamentally separates storage and computation. While it reduces data transfer overhead to some extent, it cannot entirely eliminate the von Neumann bottleneck. In recent years, in-memory computing architectures that integrate storage and computation into a unified framework have become a hotspot in academia and industry.
In-memory computing chips can be broadly categorized into analog and digital paradigms:
1.	Analog in-memory computing: Signals within or near the storage array are processed as analog signals. Operations such as matrix multiplications leverage the intrinsic physical behavior of the storage array, often relying on digital-to-analog and analog-to-digital converters for signal conversion. Analog computation typically utilizes Ohm’s law and Kirchhoff’s law to achieve high energy efficiency but may suffer from lower precision and reliability.
2.	Digital in-memory computing: Signals within or near the storage array are processed as digital signals, typically using techniques like adder trees and shifters. Digital in-memory computing achieves arbitrary precision but has relatively lower energy efficiency and higher cost per unit area.
Research on in-memory computing chips spans various storage media. Chips based on traditional media like SRAM and NOR Flash are relatively mature and have entered small-scale production. Meanwhile, chips leveraging emerging non-volatile storage media, such as magnetic random-access memory (MRAM), resistive random-access memory (RRAM), phase-change random-access memory (PCRAM), and ferroelectric field-effect transistors (FeFET), are transitioning from foundational research to industrialization. Research institutions and companies from the United States, China, and South Korea have made significant advances in this field, with notable contributions from IBM, Stanford University, Princeton University, SK Hynix, Samsung, Tsinghua University, Peking University, and the Chinese Academy of Sciences Institute of Microelectronics.
Despite these advancements, effective chip design relies heavily on EDA (Electronic Design Automation) tools, which remain in the early stages for in-memory computing. Current academic efforts have produced simple single-point tools for simulation modeling and automated synthesis, but no comprehensive EDA tool platform akin to those for digital circuit design has been established, making it challenging to support large-scale automated design of in-memory computing chips.
Current research on in-memory computing chips is primarily focused on single-point technologies, with many technical challenges remaining in areas such as devices, circuits, architectures, EDA tools, and system applications. The future development of in-memory computing chips is expected to focus on the following four trends:
1.	Shifting Toward the Perception End for Ultra-Low Power Consumption: Targeting edge markets like wearable devices and IoT, ultra-low power and low-cost solutions will be developed. Current perception chips rely on analog-to-digital converters to process data, which is slow and energy-intensive. By integrating in-memory computing chips with perception modules and developing efficient mixed-signal processing methods, it will be possible to achieve a fully integrated perception-storage-computation solution, drastically reducing overhead and achieving ultra-low power consumption.
2.	Shifting Toward the Edge/Cloud for Extreme Computational Power: For applications like edge/cloud servers, data centers, and autonomous driving, in-memory computing chips can offer massive parallel computing capabilities. Current edge/cloud processors, typically based on GPUs, face significant data communication overheads, limiting their actual computational efficiency. In-memory computing chips, optimized for large-scale matrix operations such as those in Transformer-based models, can greatly reduce bandwidth requirements and enhance computational power.
3.	Co-Design of Heterogeneous Architectures and Integration: Combining different computational architectures and hardware units can maximize their strengths while compensating for their weaknesses. For example, integrating analog and digital in-memory computing architectures can strike a balance between precision, energy efficiency, area, and cost. Advanced packaging technologies like 2.5D/3D integration and chiplets can be leveraged to integrate CPUs, GPUs, and in-memory computing chips fabricated at different process nodes, fully realizing the advantages of heterogeneous architectures.
4.	Development of EDA and Application Toolchains: As in-memory computing chips move from proof-of-concept to large-scale production, the development of automated EDA tools and application toolchains becomes critical. These tools can simplify chip design, reduce development costs, and accelerate deployment. A robust ecosystem of open-source and standardized platforms will drive mass production and widespread adoption of in-memory computing chips.
To date, in-memory computing chip technology has garnered significant attention from academia and industry, achieving a series of breakthroughs. However, before large-scale industrialization can be realized, several critical scientific issues need to be addressed in areas such as low-power mixed-signal circuits, high-density in-memory computing media, automated EDA tools, and methods/standards/processes for heterogeneous integration.
At the terminal end, the core challenge lies in the ultra-low-power processing of multi-modal information. Existing solutions for perception-storage-computing chips primarily focus on single-modality signal processing (e.g., auditory, visual, or tactile), while intelligent systems often require comprehensive analysis of multi-modal data to perceive and interpret their environment. Designing a multi-modal perception-storage-computing architecture and its associated low-power mixed-signal circuits is a critical scientific problem in achieving "ultra-low power" integration. This research spans multiple disciplines, including devices, processes, chips, algorithms, and applications, necessitating cross-layer collaborative optimization. Key questions include improving existing devices or fabricating new ones, optimizing processing technology for reliability and precision, designing efficient multi-modal mixed-signal circuits, creating algorithms tailored to hardware, and establishing user-friendly application ecosystems.
At the edge/cloud level, the primary challenges are computational power, precision, and bandwidth. Leveraging the massive parallel computing capabilities of in-memory computing chips becomes particularly critical for large-scale model applications, which impose stringent demands on scale, precision, and computational power. For instance, large-scale models require single arrays exceeding 10k × 10k, total memory capacities reaching gigabit levels, and single-chip computational performance (8-bit fixed-point numbers) of at least 100 TOPS (tera operations per second). Furthermore, increasing integration scales bring challenges like error propagation, non-uniformity, and reliability issues. Overcoming these requires breakthroughs in fundamental principles, device technologies, and theoretical models for defect and error propagation.

翻译考点：
考点1：“memory wall” 必须译为 “存储墙”。
考点2：“process wall” 必须译为 “制程墙”。
考点3：“High‑Bandwidth Memory (HBM)” 必须译为 “高带宽内存（HBM）”。
考点4：“analog in‑memory computing” 必须译为 “模拟存内计算”。
考点5：“digital in‑memory computing” 必须译为 “数字存内计算”。
考点6：“SRAM / NOR Flash” 必须译为 “静态随机存取存储器 / NOR型闪存”。
考点7：“MRAM / RRAM / PCRAM / FeFET” 必须译为 “磁阻存储器 / 阻变存储器 / 相变存储器 / 铁电场效应晶体管”。
考点8：“chiplets / 2.5D/3D integration” 必须译为 “芯粒 / 2.5D/3D集成”。
考点9：“dynamic random‑access memory (DRAM)” 必须译为 “动态随机存取存储器（DRAM）”。
考点10：“TOPS (8-bit fixed-point)”推荐译为“万亿次每秒（8位定点，TOPS）”