The very reason why there are only 52 bits used for addressing in PAE mode is that the very first 8086 processor using segmentation to address physical memory, where segment register such as CS is 16bit but referring 20-bit long segments after shifting 4 bits to the left. Keeping this schema, if there were 32bit real mode, then 20 bits (used for referring segments) + 32 bits (base address) = 52 bits (for logical addresses). But this is not the truth, but just a guide to draw the reason why. In Intel64 and IA-32 Architectures Software Developer's Manual, it says M is an abbreviation for MAXPHYADDR, which is at most 52, where M is used in PDE, PTE and PPDE without further explanation. But I don't believe, for AMD64 architecture, that would be the extreme limit for the physical addressing. If further AMD64 processor gets rid of legacy mode completely, then there would potentially 63bits for addressing physical memory rather than 52bits, like it in Itanium architecture. That might be wrong, but just put a stop to end this topic.