28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications
A CMOS-compatible boosted transistor having >2× drive current and low leakage current
Modeling and yield estimation of SRAM sub-system for different capacities subjected to parametric variations
Practical electrical parameter aware methodology for analog designers with emphasis on LDE aware for devices
A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation