A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS
Timing Recovery in Digital Synchronous Data Receivers
A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS
A fully integrated multi-CPU, GPU and memory controller 32nm processor
100GbE PHY and MAC layer implementations
A 22nm IA multi-CPU and GPU System-on-Chip