Design of CMOS inverter-based output buffers adapting the cherry-hooper broadbanding technique
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process
A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS
Automatic design of low power CMOS buffer-chain circuit using differential evolutionary algorithm and particle swarm optimization
A compact 0.3–10 GHz broadband stacked amplifier in 65nm standard CMOS