ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q
CDM peak current variations and impact upon CDM performance thresholds
CDM protection design for CMOS applications using RC-triggered rail clamps
Field effect diode for effective CDM ESD protection in 45 nm SOI technology