Novel Deep Trench Buried-Body-Contact (DBBC) of 4F2 cell for sub 30nm DRAM technology
High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond
The novel stress simulation method for contemporary DRAM capacitor arrays
Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs
A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology
A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies