A novel architecture of the 3D stacked MRAM L2 cache for CMPs
CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture
DFSTT-MRAM: Dual Functional STT-MRAM Cell Structure for Reliability Enhancement and 3-D MLC Functionality
An overview of the HDF5 technology suite and its applications
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)