SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS
A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS
Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Comparative performance analysis (accuracy, speed, and power)
Approximate SRAMs With Dynamic Energy-Quality Management
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement