Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights
A General Framework for Sparsity Regularized Feature Selection via Iteratively Reweighted Least Square Minimization
Sparse FIR Filter Design Based on Interpolation Technique
A survey of FPGA-based accelerators for convolutional neural networks
Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA
Optimal Least-Squares Design of Sparse FIR Filters for Big-Data Signal Processing