A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS
5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS
6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation
A phase-adjustable Delay-Locked Loop utilizing embedded phase interpolation