A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator
Analysis and modeling of bang-bang clock and data recovery circuits
Digitally Controlled Oscillator ( DCO )-Based Architecture for RF Frequency Synthesis in a Deep-Submicrometer CMOS Process
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy
All-digital PLL and transmitter for mobile phones
Analysis of charge-pump phase-locked loops