A novel zero weight/activation-aware hardware architecture of convolutional neural network
An Efficient Kernel Transformation Architecture for Binary- and Ternary-Weight Neural Network Inference
A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth
Streaming Architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform
A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets
SCNN: An accelerator for compressed-sparse convolutional neural networks