Design of a D-PHY chip for mobile display interface supporting MIPI standard
Design of a D-PHY chip for mobile display interface supporting MIPI standard
A low-swing differential signalling scheme for on-chip global interconnects
An inductive peaking technology for high-speed MIPI receiver bandwidth expanding in a 90 nm CMOS process
Fast switch bootstrapping for GS/s high-resolution analog-to-digital converter
Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect