Ultra Low Power Capless Low-Dropout Voltage Regulator ( Master Thesis Extended Abstract )
Capless LDO Regulator Achieving −76 dB PSR and 96.3 fs FOM
A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection
A 1.66 mV FOM Output Cap-Less LDO With Current-Reused Dynamic Biasing and 20 ns Settling Time
An enhancement transient response of capless LDO with improved dynamic biasing control for SoC applications
Multiple-Loop Design Technique for High-Performance Low-Dropout Regulator