A low-power, high-performance approximate multiplier with configurable partial error recovery
High Speed Speculative Multipliers Based on Speculative Carry-Save Tree
Modeling and Design of Multilevel Bang–Bang CDRs in the Presence of ISI and Noise
A 40 Gb/s clock and data recovery circuit in 0.18 μm CMOS technology
Digital clock and data recovery circuit design: Challenges and tradeoffs
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation