Full-System Simulation of Java Workloads with RISC-V and the Jikes Research Virtual Machine
RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks
Exploring many-core architecture design space for parallel discrete event simulation
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor
Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance
Hot Row Identification of DRAM Memory in a Multicore System