SAR ADC architecture with 98 % reduction in switching energy over conventional scheme
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
A 0.5 V 1.28-MS/s 4.68-fJ/Conversion-Step SAR ADC With Energy-Efficient DAC and Trilevel Switching Scheme
A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction
An energy-efficient charge recycling approach for a SAR converter with capacitive DAC
A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS