Wafer-level bonding/stacking technology for 3D integration
Reliability characterization of Chip-on-Wafer-on-Substrate (CoWoS) 3D IC integration technology
Effects of Bonding Parameters on the Reliability of Fine-Pitch Cu/Ni/SnAg Micro-Bump Chip-to-Chip Interconnection for Three-Dimensional Chip Stacking
Progress in digital integrated electronics [Technical literaiture, Copyright 1975 IEEE. Reprinted, with permission. Technical Digest. International Electron Devices Meeting, IEEE, 1975, pp. 11-13.]
Wafer-level Cu-Cu bonding technology
Design and Reliability in Wafer Level Packaging