Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges
Transformation of multiple fault models to a unified model for ATPG efficiency enhancement
A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems
3D-IC test architecture for TSVs with different impact ranges of crosstalk faults
Self-Test and Diagnosis for Self-Aware Systems
Autonomous Testing for 3D-ICs with IEEE Std. 1687