[en] L-band signals transmitted by the Global Navigation Satellites Systems (GNSS) from its reflection off the Earth's surface allow for the inference of some of its geophysical properties. This concept is named GNSS-Reflectometry (GNSS-R), or PAassive Reflectometry and Interferometry System (PARIS). The collected signals are processed by specialized GNSS-R receivers. This dissertation focusses on system design, which is primarily able to post-process the received GNSS-R data, with the purpose of reducing the sustained data throughput of the instrument, which is in the order of several Mbytes/sec. This amount of data poses very stringent requirements on GNSS-R designers . In our study, we have taken as an example of GNSS-R receiver design, the GPS Open-Loop Differential Real Time Receiver (GOLD-RTR), which was designed, developed and built at the ICE (IEEC-CSIC). The problem that we faced could be stated thus: we have a system which produces 12.8 Mb/s in a sustained manner, and we need to reduce this rate by three orders of magnitude by applying suitable integration algorithms, to be discussed later. The work towards my PhD has focused on one broad subject and applied this to the actual hardware design platform in order to study and address it. The subject was parallelism provision for the GNSS-R post-processing system, with special focus on the integration algorithms. The subject of parallelism provision is considered a multilayer problem, the most discussed issues are related to the task-level and memorylevel design. The Symmetric Multi-Leon3 On Linux (SMLOL) platform, was developed to address the timing issues for the GNSS-R application. This subject was the parallelism provision for the task-level system, with special focus on the conventional Symmetric MultiProcessing (SMP) scheme. As a multi-task problem, we used to assess the computational load, system performance and infer the system bottlenecks. However the unbalanced workload in the hardware design (among processors, cache, memory and bus) can not be fundamentally resolved through software methodology. The Heterogeneous Transmission and Parallel Computing Platform (HTPCP) was later developed in order to balance the transmission and computing workload. This subject was the parallelism provision for the memory-level system. According to the simulations results arrived at by MPARM emulator, we built and optimized the memory hierarchy system, in order to remove the bus busy ratio and memory access time between cache and main memory. Moreover, dealing with the bus congestion issue, we implemented two types of element: Transmission Elements (TEs) and Processing Elements (PEs), as well as several interface designs: Massage Passing Interface (MPI) and Fast Simplex Link (FSL) in HTPCP. The intended solution was to design, build and test a system with capacity to reduce the data flow three orders of magnitude by performing autonomous postprocessing algorithms.

[es] Las se˜nales de banda trasmitidas por los sistemas de navegaci´on global por sat´elite (GNSS, Global Navigation Satellites Systems) permiten averiguar algunas de las propiedades geof´ısicas de la Tierra al reflejarse en su superficie. Este concepto se llama reflectometr´ıa GNSS (GNSS-R) o sistema de interferometr´ıa y reflectometr´ıa pasivo (PARIS, Passive Reflectometry and Interferometry System). Una serie de receptores GNSS-R especializados se encargan de procesar las se˜nales recogidas. Esta tesis se centra en el dise˜no de dichos receptores, que permite principalmente procesar a posteriori los datos GNSS-R obtenidos, con el objetivo de reducir la tasa de transferencia de datos sostenida (sustained data throughput) del dispositivo, que es de alrededor de varios MB/s. Dicha cantidad de datos afecta enormemente al dise˜no de receptores GNSS-R. En nuestro trabajo, hemos tomado como ejemplo de dise˜no de receptores GNSSR el receptor GOLD-RTR (GPS Open-Loop Differential Real Time Receiver), dise˜nado, desarrollado y construido en el ICE (IEEC-CSIC). El problema al que nos enfrentamos es el siguiente: disponemos de un sistema que produce 12.8 Mb/s de forma sostenida y necesitamos reducir su magnitud tres veces mediante la aplicaci´on de algoritmos de integraci´on adecuados, que discutimos m´as adelante. Las investigaciones realizadas durante mi doctorado, centradas en un tema muy amplio, las he aplicado al estudio y tratamiento de la plataforma de dise˜no del hardware correspondiente. El tema desarrollado fue el uso del paralelismo para el sistema de post-procesamiento GNSS-R, con especial atenci´on a los algoritmos de integraci´on. El tema del paralelismo se considera un aspecto problem´ atico de m´ultiples dimensiones, siendo las m´as tratadas la del dise˜no de tareas y de memoria. Se desarroll ´o una plataforma SMLOL (Symmetric Multi-Leon3 On Linux) para tratar los problemas de sincronizaci´on de la aplicaci´on GNSS-R. Aqu´ı se trat´o el uso del paralelismo para el sistema de tareas, con especial atenci´on al esquema SMP (Symmetric MultiProcessing) convencional. Como problema multitarea, evaluamos la carga computacional y el rendimiento del sistema y comprobamos las congestiones del sistema. Sin embargo, el desequilibrio en la carga de trabajo del dise˜no del hardware(en procesadores, memoria cach´e, memoria principal y buses) no se puede solucionar fundamentalmente mediante una metodolog´ıa aplicada al software. Posteriormente se desarroll ´o la plataforma HTPCP (Heterogeneous Transmission and Parallel Computing Platform) para equilibrar la carga de trabajo de transmisi´on y computacional. En este caso, se trat´o el uso del paralelismo con relaci´on a la memoria del sistema. Segu´n los resultados de simulacio´n obtenidos con el emulador MPARM, construimos y optimizamos el sistema de jerarqu´ıa de memoria, para eliminar la tasa de ocupaci´on del bus y el tiempo de acceso a la memoria entre la memoria cach´e y la memoria principal. Asimismo, en relaci´on con el problema de congesti´on en el bus, implementamos dos tipos de elementos: elementos de transmisi´on (TEs) y elementos de procesamiento (PEs), as´ı como varios dise˜nos de interfaces: interfaz MPI (Massage Passing Interface) e interfaz FSL (Fast Simplex Link) en HTPCP. La soluci´on deseada era dise˜nar, construir y probar un sistema con capacidad para reducir tres veces la magnitud del flujo de informaci´on mediante algoritmos de post-procesamiento aut´onomos.