[en] The continuous social development and technological advancement has generated a strong and growing need to develop more and more complex hardware systems, which can adjust to the characteristics of one or more systems within the industry and are capable of providing all the features that such systems require. Thanks to Field Programmable Gate Arrays devices or FPGAs, hardware designers are able to program, test, correct and expand their designs, even before being manufactured and commissioned, which in turn provides greater security and guarantee of correct operation. To facilitate the task of designers, the suppliers of these devices have not only developed various software tools through which programming and debugging of the design can be carried out, but also they have designed several development boards, on which tests and trials can be carried out, both of a hardware design and a Software design. One of the most used tools when performing such tests on FPGAs devices are the Integrated logic Analyzer, or ILA. These logic analyzers allow you to create a connection with a control system to perform the monitoring and debugging of the internal signals of the design. The connection with this control system is made through the JTAG Boundary Scan interface of the FPGA device. This serial communication interface has a short-range and requires short distances between development boards and control systems. This is a big problem within the needs of nowadays society, since it prevents designers from carrying out tests and trials remotely from anywhere in the world and also limits them in aspects such as time or resources. Based on this panorama, this project seeks to eliminate these problems by adding an Ethernet interface within an FPGA design, which can connect to the ILA debugger and collecting and transmitting the acquired data to a control system remotely. For this purpose, an analysis and investigation of the debugging tools available in the current market has been carried out, emphasizing mainly those offered by the supplier Xilinx: the debugging cores LogiCore IP ILA and LogiCore IP Debug Bridge and the software application xvcServer within the Petalinux tools. Their characteristics and limitations, functionalities, necessary configurations and requirements have been studied in order to later combine them in such a way that a simple FPGA design capable of fulfilling the need to monitor and debug the system remotely can be created. From the design obtained, three connection tests have been carried out in different environments: Direct connection through Ethernet cable, remote connection by Wi-Fi in the same local area network and remote connection through a Virtual Private Network, VPN, by Internet. Several debugging tests have been made to observe and compare the main differences of each environment, considering above all, the stability of the connection, the speed of data transmission and the different possible problems that may occur within each network.

[eu] Etengabeko garapen sozialak eta aurrerapen teknologikoak hardware sistema gero eta konplexuagoak garatzeko premia gero eta handiagoa sortu dute, industria barruko sistema berrien ezaugarrietara egokituko direnak eta sistema horiek eskatzen dituzten prestazio guztiak emateko gai izango direnak. FPGA (Field Programmable Gate Arrays) gailuei esker, hardware diseinatzaileak gai dira beren diseinuak programatu, probatu, zuzendu eta zabaltzeko, fabrikatu eta martxan jarri aurretik, eta horrek, aldi berean, segurtasun eta berme handiagoa ematen du behar bezala funtzionatzeko. Diseinatzaileen lana errazteko, gailu horien hornitzaileek software-tresna bat baino gehiago garatu dituzte, eta horien bidez, diseinua programatu eta araztu daiteke. Horrez gain, hainbat garapen-plaka diseinatu dituzte, eta horien gainean egin daitezke probak eta saiakuntzak, bai hardware-diseinu zein software-diseinu batean. Proba horiek FPGAetan egiteko gehien erabiltzen diren tresnetako bat; analizatzaile logiko txertatuak edo ILA (Integrated logic Analizer) dira. Analizatzaile logiko horiei esker, konexio bat sor daiteke kontrol-sistema batekin, diseinuaren barne-seinaleak monitorizatzeko eta arazteko. Kontrol-sistema horrekiko konexioa FPGA gailuaren JTAG Boundary Scan interfazearen bidez egiten da. Serieko komunikazio-interfaze hori irismen laburrekoa da, eta garapen-plaken eta kontrol-sistemen arteko konexioak distantzia laburrak eskatzen ditu. Hori arazo handia da gaur egungo gizartearen premien barruan, diseinatzaileei munduko edozein leku urrunetik probak eta saiakuntzak egitea eragozten dielako, eta denbora eta baliabide aldetik ere mugatzen dituelako. Egoera horretatik abiatuz, proiektu honetan arazo horiek ezabatu nahi dira Ethernet interfazea gehituz FPGAko diseinu baten barruan, ILA araztegira konektatzeko eta eskuratutako datuak bildu eta urrutiko kontrol-sistema batera transmititzeko gai izan dadin. Horretarako, gaur egungo merkatuan dauden arazketa-tresnak ikertu eta aztertu dira: ezaugarriak, mugak, funtzionalitateak, beharrezko konfigurazioak, eskakizunak, eta abar. Horrela, FPGAn diseinu erraz bat sortu ahal izango da, sistema urrutitik monitorizatzeko eta arazteko beharra betetzeko gai izango dena. Lortutako diseinutik hiru konexio-proba egin dira ingurune desberdinetan: zuzeneko konexioa, Ethernet kablearen bidez; wifi bidezko urruneko konexioa, eremu lokaleko sare berean eta urruneko konexioa, Internet bidezko VPN sare baten bidez (Virtual Private Network). Proba bakoitzetik hainbat arazketa egin dira ingurune bakoitzaren desberdintasun nagusiak behatzeko eta alderatzeko, batez ere kontuan hartuta konexioaren egonkortasuna, datuak transmititzeko abiadurak eta gerta daitezkeen arazoak.