[ca] L'LHCb és un dels quatre grans experiments del Gran Col·lisionador d'Hadrons al CERN. En aquest moment, l'experiment LHCb ja ha profunditzat en el seu programa de presa de dades, però, per tal de realitzar estudis destinats a distingir entre models de nova física es pretén actualitzar el detector el 2019 per tal d'operar amb una lluminositat uns deu cops superior a l'actual. L'objectiu de la present Tesi és el desenvolupament d'una solució integrada pel processat del senyal analògic en la actualització i millora de l'electrònica del Calorímetre, sub-detector de l'LHCb. Aquest processat es durà a terme a les plaques d'electrònica front-end (FE) mitjançant un ASIC que rep polsos que venen de tubs fotomultiplicadors (PM) a través de 12 m de cable coaxial de 50 Ohms. Els principals requeriments del FE analògic del Calorímetre inclouen una calibració de 4.5fc/2.5MeV per compte d'ADC, un rang dinàmic de 12 bits, un soroll menor a 1 compte d'ADC, un nivell de cua residual menor que 1% i una desviació de la linearitat menor que 1%. La implementació de l'ASIC inclou quatre canals analògics amb valors programables, una línia de retard (DLL) i una interfase digital utilitzant protocol SPI. El canal analògic disposa d'un amplificador d'entrada que inclou una terminació de línia activa. Desprès, un sistema de dos subcanals diferencials commutats permet la integració del senyal sense temps morts entre esdeveniments consecutius. Cada subcanal inclou un filtre de pol-zero, un integrador commutat, un Track-and-Hold i un multiplexor. Finalment, la DLL proporciona els senyals de rellotge per sincronitzar els canals. La pròpia resistència a la radiació que assegura el fet de fer servir la tecnologia escollida (AMS 0.35um BICMOS) i l'ús de tècniques específiques permet una tolerància del circuit integrat a SEUs, SETs i SELs, als nivells esperats al detector. El disseny ha estat verificat en diferents proves per un total de 30 prototips de la versió final del xip: primer, al laboratori, utilitzant un senyal obtingut amb un oscil·loscopi al detector; amb feixos d'electrons i canals del detector, a zones dedicades al CERN; i, la resistència a la radiació s'ha verificat al CRC a Louvain la Neuve, Bèlgica.

[en] LHCb is one of the four large experiments of the Large Hadron Collider (LHC) based at CERN. The LHCb experiment is taking data at its nominal design luminosity. However, in order to distinguish among models of new physics, higher luminosity is needed. So the LHCb collaboration intends to upgrade the detector during the planned long LHC shutdown in 2019 in order to be able to operate at a luminosity about 10 times the nominal one. The objective the present thesis is the development of an integrated solution for the analog signal processing in the electronic and hadronic calorimeters of the LHCb. The analogue signal processing will be performed by a shaper ASIC in the calorimeters Front End (FE) boards. The signal pulse from a photomultiplier tube is clipped at its base and, then, is transmitted through a 12m 50Ω coaxial cable to the FE board located in the crates at the calorimeter platform. In order to reduce the PMT ageing after the increase in luminosity, the gain has to be decreased by a factor 5 with respect to the present operation in order to keep the same average current. Therefore, the preamplifier input noise must be decreased accordingly so that the total input referred noise voltage is smaller than 1nV/√Hz. Consequently, a 50Ω termination resistor is not acceptable. The main requirements for the analogue FE of the calorimeter system include a cali- bration of 4fC/2.5MeV per ADC count; a dynamic range of 12 bits; noise lower than 1 ADC cnt (ENC < 4 fC); and a spill-over residue level ±1% a linearity: < 1%. The implementation of the ASIC includes: four analog channels with programmable values to control the key parameters and compensate for process variations; a dedicated Delay Locked Loop (DLL) to synchronize each channel signal phase and a digital interface using SPI protocol. The analog channel is designed with an input amplifier that includes an electronically cooled termination input stage. A passive line termination would induce too large a noise and is avoided. Afterwards an alternated switched differential signal paths scheme permits the integration of the signal with no dead time between consecutive events. Each path includes a pole-zero filter in order to compensate for cable effects, a switched integrator with capacitive feedback, a Track-and-Hold for a 12-bit ADC and a MUX to select the correct sub-channel output signal. A fully differential signal processing is adopted in order to minimize the impact of common mode noise, which is important in a switched system. Each analog channel includes a delay line based on a DLL so the user can set a delay to compensate the delay introduced by PMT voltage settings, cable lengths or particle time of flight from the interaction point to the calorimeter cells. The DLL is adjusted by means of two control voltages to ensure that systematic process or environmental variations will not affect the channel time tuning. The radiation hardness expected from the selected technology (0.35µm AMS SiGe BiCMOS) is enough, but design techniques are used to ensure being able to tolerate SEUs, SETs and SELs. The design has been checked at different tests of a total of 30 pieces of the final pro- totype: at the laboratory using a signal obtained with a scope, with electron beams and ECAL channels in a dedicated facility at CERN, and its radiation hardness at Centre de Resources du Cyclotron at Louvain la Neuve. Dedicated boards were developed and the results are positive.