[ca] La dissertació aborda la investigació per millorar la previsibilitat temporal i el rendiment en Critical Real-Time Embedded Systems (CRTES), centrada en Multi-Processor Systems on Chip (MPSoCs). Els CRTES són essencials en àmbits crítics com l'automoció i l'aeronàutica, on es requereixen funcionalitats complexes i alt rendiment per a tasques com la intel·ligència artificial i el processament de dades multisensor. Tanmateix, els MPSoCs enfronten grans reptes de verification and validation (V&V) temporal, especialment en recursos compartits com caches i interconnexions, que generen retards imprevisibles. Aquesta tesi se centra en tres àrees clau per millorar la previsibilitat en CRTES: coherència de les cache, predictibilitat en interconnexions i rendiment d'aplicacions mitjançant vector extensions. Coherència de les Cache: Als MPSoCs, els protocols de coherència garanteixen la consistència de dades entre nuclis, però les caches compartides generen contenció que afecta la previsibilitat. Modificar protocols sol ser costós i complex. Aquesta tesi proposa l'ús de hardware event monitors (HEMs) per observar la contenció en caches, proporcionant dades clau per a la V&V temporal sense modificar els protocols existents. Aquesta metodologia s'aplica a MPSoCs comercials com NXP T1040 i T2080. També s'introdueix el mètode Remote Protocol-Contention Tracking (RPCT) per a un seguiment detallat dels retards causats per la contenció inter-core, oferint informació clau per optimitzar el programari. A més, el mètode Multiple HEM Validation (MHV) millora la precisió validant les relacions entre HEMs, mitigant errors coneguts en les mesures individuals. Interconnexions: Els MPSoCs depenen de protocols com AXI4 per transferir dades entre nuclis, però l'estàndard AXI no inclou restriccions temporals, fent imprevisible el seu ús en temps real. Per abordar-ho, es proposa AXI4 Real-Time (AXI4RT), una extensió del protocol AXI que defineix paràmetres temporals per controlar la durada de les transaccions entre interfícies. Això assegura una comunicació previsible i millora la fiabilitat per a aplicacions en temps real. A més, es presenten passos inicials per rastrejar la contenció en interconnexions AXI5 utilitzant HEMs actuals i es proposen nous HEMs per millorar aquest seguiment. Rendiment d'aplicacions amb Vector Extensions: Per satisfer les demandes de rendiment en CRTES, els MPSoCs usen GPUs i acceleradors personalitzats, que presenten reptes de certificació per la seva complexitat i temps imprevisible. Aquesta tesi explora vector extensions (VExt) com a alternativa. Les Single Instruction Multiple Data (SIMD) units, presents en molts processadors incrustats, fan operacions paral·leles en múltiples elements de dades, millorant la velocitat de processament. A diferència de les GPUs, les VExt estan integrades en els processadors i compleixen amb estàndards d'alta integritat com MISRA-C, facilitant-ne la certificació. L'anàlisi de les VExt en processadors COTS com NVIDIA AGX Xavier mostra el seu potencial per millorar el rendiment sense comprometre la certificació. En resum, aquesta tesi presenta avenços en la previsibilitat dels CRTES, oferint solucions per garantir temps fiables en sistemes incrustats complexos. En abordar cache coherence, interconnexions i altres millores de rendiment d'aplicacions, aquesta tesi proporciona eines i metodologies que milloren l'anàlisi temporal, i això permet als MPSoCs complir garanties en temps real.

[en] The dissertation, research on enhancing timing predictability and performance for Critical Real-Time Embedded Systems (CRTES), focusing on Multi-Processor Systems on Chip (MPSoCs). CRTES are essential in critical domains like automotive and avionics, where complex functionalities and high performance are increasingly required for operations such as AI and multi-sensor data processing. However, MPSoCs face significant timing verification and validation (V&V) challenges, especially related to shared resources like caches and interconnects, which can introduce unpredictable delays. This thesis addresses three core areas to improve CRTES predictability: cache coherence, interconnection predictability, and application performance through vector extensions. Cache Coherence: In MPSoCs, cache coherence protocols ensure consistent data across multiple cores, but shared caches introduce contention that affects timing predictability. Traditional approaches to improving coherence often involve modifying protocols, a costly and complex task. This thesis takes an alternative approach by leveraging hardware event monitors (HEMs) to observe cache contention, providing valuable data for timing V&V without altering existing protocols. This methodology is applied to commercial MPSoCs like the NXP T1040 and T2080, which are widely used in real-time domains.On another note, the Remote Protocol-Contention Tracking (RPCT) method is proposed, which enables fine-grained tracking of delays due to inter-core contention, offering insights into cache coherence impacts on software predictability and informing developers on optimization strategies. Additionally, the thesis proposes a novel Multiple HEM Validation (MHV) method to improve the accuracy of contention measurements by validating HEM reliability through inter-HEM relationships, mitigating known issues with single-event HEM inaccuracies. Interconnections: MPSoCs rely on point-to-point (P2P) communication protocols like AXI4 for data transfer between cores, but the standard AXI protocol lacks timing constraints, making it unpredictable under real-time requirements. Addressing this, this thesis introduces AXI4 Real-Time (AXI4RT), an extension to the AXI protocol that specifies timing parameters to control the duration of transactions between manager and subordinate interfaces. By defining timing guarantees directly within the protocol, AXI4RT ensures predictable communication, enhancing system reliability for real-time applications. Additionally, this thesis provides some initial steps for contention tracking on modern AXI5 interconnects by doing an in-depth analysis how can contention be tracked with currently available HEMs and proposing some HEMs that could improve this tracking. Application Performance with Vector Extensions: To meet growing performance demands in CRTES, MPSoCs often use GPUs and custom accelerators, but these present certification challenges due to their complexity and unpredictable timing. This thesis explores using vector extensions (VExt) as an alternative. Single Instruction Multiple Data (SIMD) processing units are already available in many embedded processors, which perform parallel operations on multiple data elements, effectively improving data processing speeds. Unlike GPUs, VExt are integrated within processors and comply with high-integrity system standards, making them easier to certify. The thesis provides an analysis of VExt in COTS processors like NVIDIA's AGX Xavier and show their potential to enhance performance while maintaining compliance with standards such as MISRA-C. In summary, this thesis advances the state-of-the-art in CRTES predictability, presenting solutions that ensure more reliable timing for complex embedded systems in safety-critical applications. By addressing cache coherence, interconnect timing, and performance, this thesis provides tools and methodologies for better timing analysis, enabling MPSoCs to improve real-time guarantees.