Data from October, 31 are at d0mino:

/projects/810/fp_1/krivkova/FPD_data/

Files names are : run000***.dat 

---------------------------------------------------

I send you the picture of the trigger logic later.

---------------------------------------------------

Camac information:
==================

Scalers (Only the first (from the left) scaler is used):
--------------------------------------------------------

channel information
------- -----------
ch 0    two possible info:  1) (d1 or d2);  2) ((d1 or d2) and clock) prescaled
ch 1    two possible info:  1) (d1 and d2); 2) ((d1 and d2) and clock) prescaled
ch 2    two possible info:  1) (d1 and d2) and clock and SOUTH 
                            2) (d1 and d2) and clock and SOUTH and antiNORTH

ch 3    pulser 
ch 4    g-pulser (coincidence of pulser and antiBUSY from LAM module)
ch 5    pedestals prescaled   
ch 6    master trigger (sum of (ch0,ch1,ch2,ch5))


TDC information (Only the first (from the left) TDC is used):
-------------------------------------------------------------
(TDC start: output signal coming from the master trigger "OR" logic unit)

channel information
------- -----------
ch0     D1
ch1     D2


FERA (number : starts from the left): 
------------------------------------

number detector layer 3rd ribbon cable
------ -------------- ----------------
0      d1 u            16C20030  
1      d1 u'           16C20038 
2      d1 v            16C20033 
3      d1 v'           16C20034 
4      d1 x            16C20035 
5      d1 x'           16C20046 
6      d2 u            16C20040 
7      d2 u'           16C20041 
8      d2 v            disconnected 
9      d2 v'           16C20043
10     d2 x            16C20044 
11     d2 x'           disconnected



=========================================================

HV of L0PMT at D1 and D2: -1800V 
HV of MAPMT at D1 and D2:  -950V

threshold of the discriminator into which goes 
signal from L0PMT at D1 and D2:  -40mV

pulser frequency: 1kHz

peds:
- the accelerator clock is used to generate the pedestal
- on 30 Oct the clock was timed with the signals from D1 and D2
- to produce pedestal we use the delay unit (not to read pedestals when 
  it's possible to have a signal in the detector)
- accelerator clock we are getting is the TTL pulse; we use the TTL to NIM convertor to 
  create the NIM pulses; it is 36 (3 supperbunches with 12 bunches) signals for one evolution
=> the pedestal rate is pretty high and we have to prescale it 

acc.clock:
the width of the accelerator clock was set up for 50 ns (before making the 
coincidences with D1,D2)

HOW I timed the acc. clock and the D1,D2 signal:
------------------------------------------------
- trigger for the beam marker (P1A13)
- put the (D1 and D2)
- observe the second peak appearing after the beam marker
  (the first peak (which was not very frequent) is due to the early proton halo;
   the second peak should be due to the: interaction, intime antiproton halo, or
   the 'second bunch' early proton halo)
- delayed the first peak (first bunch) of the accelerator clock to be in the coincidence 
  with the second peak of the (D1 and D2)  

HOW I timed the SOUTH (or (SOUTH and antiNORTH)) Luminosity Monitor signal  :
-----------------------------------------------------------------------------
- trigger for the beam marker (P1A13)
- put the (D1 and D2 and clock)
- observe the first peak appearing after the beam marker
  (interaction, intime antiproton halo, or the 'second bunch' early proton halo)
- put SOUTH (or (SOUTH and antiNORTH))
- delayed the first peak to be in the coincidence with thefirst peak of the 
  (D1 and D2 and clock)  


HOW the SOUTH and NORTH Luminosity monitor signal looks like:
-------------------------------------------------------------
- distance of the NORTH (SOUTH) detector from the collision center is 4.5ns
- it is the "OR" of four scintillating tiles for each side
- it is the signal after the discriminator (50ns wide)
  => I could not distinguish between the early and intime hits
- I timed the first NORTH and SOUTH signal to appear in the same time after the 
  beam marker
- I observed the 'strange' three signals appearing sometimes in the same positions (appr.:
  70ns,135ns and 200ns) after the first signal for both NORTH and SOUTH side (I discussed 
  this with Mike Begel; he said that he observed this behavior already before - he will ask
  somebody who should know the nature of these peaks)
  I also observed the 396ns period of these pulses.

=========================================================

DATA files:
===========

time: after 14:00, 31 Oct
-----------------------------------------------------------------
we move the pots (D1 and D2 in);

we stop at the position:
D1 position: 29.8 mm from the home position
D2 position: 29.8 mm from the home position
rates:
D1 L0PMT: 12.7kHz (signal above -40mV) (254300counts in 20sec) 
D2 L0PMT:  5.0kHz (signal above -40mV) ( 99400counts in 20sec)
(D1 and D2): 4.5kHz ("AND" of the signals after the discriminator; 
                    the width of the signals 50ns) (89000counts in 20sec)
       
time: 15:43, 31 OCT
------------------------------------------------------------------
we run the pedestal program and loaded these pedestals 
------------------------------------------------------------------
we run the "rundaq"

run000109.dat (no clock)
------------- 
trigger going to LAM: * (D1 and D2) - prescaled by 10 
                      * (D1 or D2)  - prescaled by 10   
                      * peds        - prescaled by 959x999
camac scalers:ch 0     (d1 or d2) 
              ch 1     (d1 and d2)

ADC gate is 250 ns wide

------------------------------------------------------------------

run000110.dat (same as '109' but the ADC gate)
-------------
trigger going to LAM: * (D1 and D2) - prescaled by 10 
                      * (D1 or D2)  - prescaled by 10   
                      * peds        - prescaled by 959x999
camac scalers:ch 0     (d1 or d2) 
              ch 1     (d1 and d2)
ADC gate is 200 ns wide
(I FORGOT TO LOAD THE NEW PEDESTALS) - ADC data should not be very usefull

-------------------------------------------------------------------

run000111.dat (same as '109' but the ADC gate)
-------------
trigger going to LAM: * (D1 and D2) - prescaled by 10 
                      * (D1 or D2)  - prescaled by 10   
                      * peds        - prescaled by 959x999
camac scalers:ch 0     (d1 or d2) 
              ch 1     (d1 and d2)
ADC gate is 150 ns wide
(I FORGOT TO LOAD THE NEW PEDESTALS) - ADC data should not be very usefull

-------------------------------------------------------------------

time: after 16:37, 31 Oct
--------------------------------------------------------------------

we checked the rates in the L0PMTs:
D1 L0PMT: 13.2kHz (signal above -40mV) (263000counts in 20sec) 
D2 L0PMT:  5.1kHz (signal above -40mV) (102000counts in 20sec)
(D1 and D2): 4.6kHz (92000counts in 20sec)

--------------------------------------------------------------------

run000112.dat
-------------
trigger going to LAM: * (D1 and D2) - prescaled by 10 
                      * (D1 or D2)  - prescaled by 10   
                      * peds        - prescaled by 959x999
camac scalers:ch 0     (d1 or d2) 
              ch 1     (d1 and d2)
ADC gate is 200 ns wide
(I FORGOT TO LOAD THE NEW PEDESTALS) - ADC data should not be very usefull

-------------------------------------------------------------------

time: after 17:20, 31 Oct
--------------------------------------------------------------------

we checked the rates in the L0PMTs:
D1 L0PMT: 14.5kHz (signal above -40mV) (290000counts in 20sec) 
D2 L0PMT:  5.7kHz (signal above -40mV) (114000counts in 20sec)
(D1 and D2): 5.2kHz (104000counts in 20sec)

--------------------------------------------------------------------

checking of the clock timing

on Oct, 30 I setup using the beam marker (P1A13) the acc.clock to be in 
the coincidence with the signal from the D1,D2

--------------------------------------------------------------------

time: after 18:37, 31 Oct
--------------------------------------------------------------------

we checked the rates in the L0PMTs:
D1 L0PMT: 14.5kHz (signal above -40mV) (281000counts in 20sec) 
D2 L0PMT:  5.7kHz (signal above -40mV) (108000counts in 20sec)
(D1 and D2 and clock): 5.2kHz (90000counts in 20sec)

--------------------------------------------------------------------

time: 18:40, 31 OCT
------------------------------------------------------------------
we run the pedestal program and loaded these pedestals 
------------------------------------------------------------------

we run the "rundaq"

run000113.dat
-------------
trigger going to LAM: * (D1 and D2 and clock)   - prescaled by 10 
                      * ((D1 or D2) and clock)  - prescaled by 10   
                      * peds                    - prescaled by 939x999
camac scalers:ch 0     (d1 or d2) and clock 
              ch 1     (d1 and d2) and clock

ADC gate is 200 ns wide

------------------------------------------------------------------

run000114.dat (same as '113' but the ADC gate)
-------------
trigger going to LAM: * (D1 and D2 and clock)   - prescaled by 10 
                      * ((D1 or D2) and clock)  - prescaled by 10   
                      * peds                    - prescaled by 939x999
camac scalers:ch 0     (d1 or d2) and clock 
              ch 1     (d1 and d2) and clock

ADC gate is 150 ns wide
(I FORGOT TO LOAD THE NEW PEDESTALS) - ADC data should not be very usefull

------------------------------------------------------------------

run000115.dat (same as '114')
-------------
trigger going to LAM: * (D1 and D2 and clock)   - prescaled by 10 
                      * ((D1 or D2) and clock)  - prescaled by 10   
                      * peds                    - prescaled by 939x999
camac scalers:ch 0     (d1 or d2) and clock 
              ch 1     (d1 and d2) and clock

ADC gate is 150 ns wide
(I FORGOT TO LOAD THE NEW PEDESTALS) - ADC data should not be very usefull

------------------------------------------------------------------


note: problems with the veto of the (D1 or D2) by the anticlock)



-------------------------------------------------------------------

time: 23:16, 31 OCT
------------------------------------------------------------------
we run the pedestal program and loaded these pedestals 
------------------------------------------------------------------

run000118.dat
-------------
trigger going to LAM: * (D1 and D2 and clock)   - prescaled by 10 
                      * ((D1 or D2) and clock)  - not connected   
                      * peds                    - prescaled by 910x310
camac scalers:ch 0     (d1 or d2) and clock 
              ch 1     (d1 and d2) and clock

ADC gate is 150 ns wide

------------------------------------------------------------------

run000119.dat
-------------
trigger going to LAM: * (D1 and D2 and clock)   - not connected 
                      * ((D1 or D2) and clock)  - prescaled by 10   
                      * peds                    - prescaled by 910x310
camac scalers:ch 0     (d1 or d2) and clock 
              ch 1     (d1 and d2) and clock

ADC gate is 150 ns wide

------------------------------------------------------------------

study of the Luminosity monitor signals:

NORTH
SOUTH

------------------------------------------------------------------

time: 0:37, 1 Nov
------------------------------------------------------------------

HIGH RATE !!!

we checked the rates in the L0PMTs:
D1 L0PMT: 1MHz (signal above -40mV) (20104734counts in 20sec) 
D2 L0PMT: 0.47MHz (signal above -40mV) ( 9440842counts in 20sec)
(D1 and D2 and clock and SOUTH): 27kHz (546181counts in 20sec)

=> we had to move the D1,D2 from 29.8mm to 14.9mm

we checked the rates in the L0PMTs:
D1 L0PMT: 3.0kHz (signal above -40mV) (61420counts in 20sec) 
D2 L0PMT: 1.4kHz (signal above -40mV) (28220counts in 20sec)
(D1 and D2 and clock): 900Hz (17927counts in 20sec)
(D1 and D2 and clock and SOUTH): 50Hz (997counts in 20sec)

------------------------------------------------------------------

run000120.dat
-------------
trigger going to LAM: * (D1 and D2 and clock and SOUTH ) - prescaled by 1 
	              * (D1 and D2 and clock)   - prescaled by 10 
                      * ((D1 or D2) and clock)  - prescaled by 10 
                      * peds                    - prescaled by 910x310
camac scalers:ch 0     (d1 or d2) and clock 
              ch 1     (d1 and d2) and clock
              ch 2     (d1 and d2) and clock and SOUTH

ADC gate is 150 ns wide

------------------------------------------------------------------

run000121.dat
-------------
trigger going to LAM: * (D1 and D2 and clock and SOUTH ) - prescaled by 1 
	              * (D1 and D2 and clock)   - not connected 
                      * ((D1 or D2) and clock)  - not connected 
                      * peds                    - not connected 
camac scalers:ch 0     (d1 or d2) and clock 
              ch 1     (d1 and d2) and clock
              ch 2     (d1 and d2) and clock and SOUTH

ADC gate is 150 ns wide

------------------------------------------------------------------

time: 2:16am, 1 Nov
------------------------------------------------------------------

we checked the rates in the L0PMTs:
D1 L0PMT: 1.2kHz (signal above -40mV) (23049counts in 20sec) 
D2 L0PMT: 0.6kHz (signal above -40mV) (11669counts in 20sec)
(D1 and D2 and clock): 389Hz (7680counts in 20sec)

------------------------------------------------------------------

time: 2:27am, 1 Nov
------------------------------------------------------------------

we checked the rates in the L0PMTs:
D1 L0PMT: 1.2kHz (signal above -40mV) (23173counts in 20sec) 
D2 L0PMT: 0.6kHz (signal above -40mV) (11842counts in 20sec)
(D1 and D2 and clock and SOUTH and antiNORTH): 8Hz (154counts in 20sec)

------------------------------------------------------------------

run000122.dat
-------------
trigger going to LAM: * (D1 and D2 and clock and SOUTH and antiNORTH) - prescaled by 1 
	              * (D1 and D2 and clock)   - prescaled by 50 
                      * ((D1 or D2) and clock)  - prescaled by 50 
                      * peds                    - prescaled by 910x310
camac scalers:ch 0     (d1 or d2) and clock 
              ch 1     (d1 and d2) and clock
              ch 2     (d1 and d2) and clock and SOUTH and antiNORTH

ADC gate is 150 ns wide

------------------------------------------------------------------

run000123.dat
-------------
trigger going to LAM: * (D1 and D2 and clock and SOUTH ) - prescaled by 1 
	              * (D1 and D2 and clock)   - not connected 
                      * ((D1 or D2) and clock)  - not connected 
                      * peds                    - not connected 
camac scalers:ch 0     (d1 or d2) and clock 
              ch 1     (d1 and d2) and clock
              ch 2     (d1 and d2) and clock and SOUTH and anti NORTH

ADC gate is 150 ns wide

------------------------------------------------------------------

time: 2:48am, 1 Nov
------------------------------------------------------------------

we checked the rates in the L0PMTs:
D1 L0PMT: 1.0kHz (signal above -40mV) (20521counts in 20sec) 
D2 L0PMT: 0.5kHz (signal above -40mV) (10973counts in 20sec)
(D1 and D2 and clock and SOUTH and antiNORTH): 9Hz (175counts in 20sec)

------------------------------------------------------------------

time: 3:10am, 1 Nov
------------------------------------------------------------------

we moved the D1,D2 from 14.9mm to 23.0mm (distance from the home position) 

------------------------------------------------------------------

we checked the rates in the L0PMTs:
D1 L0PMT: 2.0kHz (signal above -40mV) (40721counts in 20sec) 
D2 L0PMT: 1.1kHz (signal above -40mV) (22515counts in 20sec)
(D1 and D2 and clock and SOUTH and antiNORTH): 10Hz (202counts in 20sec)

------------------------------------------------------------------

run000124.dat
-------------
trigger going to LAM: * (D1 and D2 and clock and SOUTH ) - prescaled by 1 
	              * (D1 and D2 and clock)   - not connected 
                      * ((D1 or D2) and clock)  - not connected 
                      * peds                    - not connected 
camac scalers:ch 0     (d1 or d2) and clock 
              ch 1     (d1 and d2) and clock
              ch 2     (d1 and d2) and clock and SOUTH and anti NORTH

ADC gate is 150 ns wide

------------------------------------------------------------------

time: appr. 4:00am, 1 Nov
------------------------------------------------------------------

they called us from the control room to moved the detectors out (they were inserting
 the collimators)

------------------------------------------------------------------
 
D1,D2 in home position

------------------------------------------------------------------

we checked the rates in the L0PMTs:
D1 L0PMT: 327Hz (signal above -40mV) (6543counts in 20sec) 
D2 L0PMT: 140Hz (signal above -40mV) (2807counts in 20sec)
(D1 and D2 and clock and SOUTH and antiNORTH): 1.5Hz (31counts in 20sec)