DFE Double-Wide Board Status
maintained by Jamieson Olsen
jamieson@fnal.gov

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Property Sticker: 566536
Daughterboard serno: 13
U3: XCV600-5BG560C
U5: XCV600-5BG560C
U1: XCV600-5BG560C

25 Aug 2005: Pulled from platform PW03-2-3 (CTOC) input link 8 has
             parity errors cleaned and resoldered the board.  Solder
             pressfit connectors.  Link test OK. Ready to go back in.

16 Nov 2005: Installed in PW03-2-6.  Seems to be working fine.

27 Dec 2005: Pulled from the platform PW03-2-6 link8 is reporting link
             errors again.  Confirmed that link8 bit 8 is bad.

28 Dec 2005: LVDS RX data bit 8 (U31.8) toggles between 3.1 and 2.4V.
             The problem was caused by a bad input on U5 (our friend
             74LCX16244).  Replaced U5.  Passed link test.  Installed
             in PW03-2-6 and appears to be working fine.

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Property Sticker: 566565
Daughterboard serno: 26
U3: XCV1000e-6BG560C
U5: empty
U1: XCV1000e-6BG560C

16 Nov 2005: Failed link test.  U3 reports bad input link2, link4,
             link7 and link8.  U1 reports bad input link 7.  Probably
             has major issues on the BGAs.  Need to run the JTAG tests
             on this board.  Do not install.

21 Nov 2005: Previous link errors were incorrect and due to link skew
             in the old link test firmware.  Complete re-write of the
             firmware and now all input and output links are fine.
             Cap mod, fuse mod, solder pressfits.  Ready for install.

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Property Sticker: 566440
Daughterboard serno: 49
U3: XCV600-5BG560C
U5: XCV600-5BG560C
U1: XCV600-5BG560C

16 Nov 2005: Pulled from platform (PW03-2 slot 6, CTOC) Parity errors
             on link2.  Needs additional testing.

30 Nov 2005: Running link test... all inputs and outputs test OK.
             Green dot, ready for installation.

27 Dec 2005: Installed on platform PW03-2-6.  Occasional parity errors
             on input link2 (same as before).  Suspect these bit
             errors are caused by a timing issue in the CTOC
             production firmware....?

28 Dec 2005: Pulled from the platform PW03-2-6 with parity errors on 
             link2.

29 Dec 2005: Link test shows NO problems.  Probed all output data bits
             from link2 LVDS RX (U25) and all outputs look fine.  No
             evidence of bad inputs/outputs on the 74LCX16244 chips.
             Cannot reproduce link2 bit errors at the test stand.  Cap
             mod, then ready for installation (again).

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Property Sticker: 566567
Daughterboard serno: <removed>

16 Nov 2005: A real mess. U3 reports the following input links as bad:
             1, 4, 7, 8.  U1 reports the following links as bad: 1, 7,
             8.  Additionally the U1 chip reports errors on the L3
             output bus.  Need to pull this board and run the JTAG
             test on it.  Do not install.

21 Nov 2005: Run through NEW link test and find four faults: Link 8
             bit 17 -- ignore, not used for LVDS-21 links Link 0 bit 5
             -- ignore, not used for LVDS-21 links L3out bit 20 --
             shorted to L3out 18 L3out bit 18

	     This motherboard is dead... the short is under the motherboard 
             connector and some of the screws are starting to strip out. 

	     Transferring the daughterboard to 566564...

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Property Sticker: 566564
Daughterboard serno: 20
U3: XCV1000e-6BG560C
U5: empty
U1: XCV1000e-6BG560C

16 Nov 2005: All input and output links test OK.  Cap mod, fuse mod, solder 
             press fit connectors. Ready for install.

29 Nov 2005: Installed as DFEF board in PC20-2 slot 8 (replaces 566438).

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Property Sticker: 566572
Daughterboard serno: 69
U3: XCV1000E-6BG560C
U5: XCV600E-6BG560C
U1: XCV1000E-6BG560C

18 Oct 2005: Pulled from platform.  PW03-1-20 FPD.  Link 1 reporting L1accept
             mismatch errors.

23 Nov 2005: Verified that link1 has problems on bit 8.  Buffer chip
             U35 input pin 30 has been pulled up to the +3.3V rail
             pretty hard.  Another failure on the Fairchild 74LXC16244
             buffers.  Marked with red dot until U35 is replaced.

30 Nov 2005: Replaced U35.  Link test reports the following errors:
             link2 bit 10 (all FPGAs); link8 bit 12 (U3 only); link9
             bit 4 (U5 only).  The latter two links are probably
             caused by an open solder ball under the BGA and are
             located on unused links anyway, so this is not a concern.
             The error on link2 bit 10 does not appear to be a bad
             LVDS receiver or a buffer chip; likely a bad connection
             on the motherboard.  This bit is not used for LVDS-21
             links and can be ignored.  Green dot, ready to install.

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Property Sticker: 566575
Daughterboard serno: 63
U3: XCV600-5BG560C
U5: empty
U1: XCV600-5BG560C

15 Jul 2005: Pulled from platform.  U49 motherboard CPLD periodically going into
             strange state where all LEDs glow dim and the backplane bus drivers 
             stay on, trashing the bus.  Cannot reproduce the problem up here.

22 Nov 2005: all input and output links test OK.  U49 verified OK, but
             reprogrammed all motherboard CPLDs as well.  Cap mod,
             fuse mod, solder pressfit connectors.  Trim the
             testpoints down -- maybe they were touching the
             neighbouring board?!?

29 Nov 2005: Replace large caps with 100uF tant caps.  Powerup OK on
             test stand.  Trimmed the test points a bit more.
             Installed as STSX in PW03-1-10.

31 May 2006: This board still has problems.  CPLD U49 going into
             strange state and causing the FPGAs to erase and halting
             backplane communication.  Seemed related to high rates
             and magnet operations...?  On the bench awaiting other testing.

01 Jun 2006: Board passes link test.  Remove and replace CPLD U49 from
             motherboard.  Passed link test OK.  Programs from the
             backplane at the combined test stand.  Ready for install.

07 Jun 2006: this board went back in but complains of halted dtack erorrs.
	     pulled out and is back on the bench.

08 Jun 2006: board immedately goes into reset even though supplies
	     look good.  U19.46 (unbuffered_reset) input on 74LCX16244
	     bad, pulled to ground and holding the board in reset.
	     Pulled U19, ordered more 74LCX16244 parts (switching to ST
	     micro instead of Fairchild).

14 Jun 2006: replaced U19 with new 74LCX16244 buffer chip (ST micro,
	     not Fairchild).  Tests OK, programs from the backplane.
	     Ready for install.  Before this mod the faulty U19 chip
	     was holding the net unbuffered_reset near the LVTTL
	     threshold, causing metastability in the chips on this net
	     and causing some strange behaviour.  That's the theory
	     anyway...

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Property Sticker: 566609
Daughterboard serno: 68
U3: XCV1600E-6BG560C
U5: XCV600E -6BG560C
U1: XCV600E -6BG560C

26 Aug 2005: U3 fails to program from the backplane.  Init OK from JTAG.  Do not
             install.  This is one of the early FPD boards.  Red dot.

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Property Sticker: 566583
Daughterboard serno: "CTOC-6"
U3: XCV600 -5BG560C
U5: XCV600 -5BG560C
U1: XCV600 -5BG560C

27 Jul 2005: replace fuse, replace caps, link test OK.  Solder pressfit connectors.
             Green dot, ready for install.

03 Oct 2006: Removed from platform by Stefan/Remi.  PW03-2-7.  Does not 
	     initilize.

12 Oct 2006: Link test OK.  Checking configuration signals.

19 Sep 2007: This board is back at my bench on WH14.  Why?
             Yellow dot.  Returning to D0.

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Property Sticker: 566438
Daughterboard serno: 35
U3: XCV1000e-6BG560C
U5: empty
U1: XCV1000e-6BG560C

29 Nov 2005: Removed from PC20-2 slot 8.  This DFEF board was losing
             init periodically.  Board 566564 installed in it's place.
             Marked bad and awaiting further testing.  VCC and GND
             test points on the daughterboard were too long and bent
             near each other.  This may be the cause of the resets.

30 Nov 2005: Running link test on this board.  Link4 bit 10 reported
             as bad.  (This bit is not used for LVDS-21 links.)
             Problem was traced to U39 74LCX16244.  The input pin was
             pulled to VCC 20 ohms.  Since this pin is not used it was
             lifted.  Green dot, ready for installation.

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Property Sticker: 566458
Daughterboard serno: 64
U3: XCV600-5BG560C
U5: empty
U1: XCV600-5BG560C

29 Nov 2005: Pulled from platform. It was STSX PW03-1-10.  Reports
             parity error on input link8.  Board passes link test.
             Clean and solder front pressfit connectors.  Replace bulk
             caps with 100uF tant caps.  Fuse mod.  Retest OK.  The
             link8 problem might be a caused by setup/hold violation
             in the STSX firmware..?  Green dot, ready for install.

31 May 2006: This problem appeared again on link8 and the board was
             pulled checked the buffered LVDS signals on the
             motherboard.  Everything looked OK, no bad bits on link8.
             Going back in... this is probably a timing issue with
             Thei's front end firmware.

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Property Sticker: 566599
Daughterboard serno: 60
U3: XCV600-5BG560C
U5: empty
U1: XCV600-5BG560C

16 Jun 2006: Pulled from platform.  It was STOV PW03-1-6.  Reports
	     show bad input link3.  Awaiting further testing.

31 Jul 2006: Still waiting on testing...!

11 Oct 2006: Hey, finally getting around to it.  Link 3 bit 10 is
             being pulled high due to faulty output diode in U41.
             Another instance of a bad 74LCX16244 buffer.  Will send
             to techs here on the 14th floor for repair.

16 Oct 2006: Buffer chip U41 replaced.  Link test OK.  This board has
	     been returned to DZERO.

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Property Sticker: <missing>
Daughterboard serno: 8
U3: XCV600 -5BG560C
U5: XCV600 -5BG560C
U1: XCV600 -5BG560C

03 Oct 2006: Removed from platform CTOC slot 7 (octant 5).  Observed
	     output bit 10 appears stuck at one which causes turn
	     number mismatch.  Removed by Remi and Stefan.

11 Oct 2006: Problem appears to be on the VRB/VTM end of things since 
	     the replacement board behaves the same way.  I'll retest 
	     board anyway to check the inputs and output links.

12 Oct 2006: All input and output links test OK.  Sending board back
	     to DZERO.

13 Oct 2006: Returned to DZERO and put into the CTS rack for storage.

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Property Sticker: 566568
Daughterboard serno: 46
U3: XCV1000e-6BG560C
U5: empty
U1: XCV1000e-6BG560C

19 Sep 2007: This board is back at my bench in WH14.  Why?  
             Yellow dot.  Returning to D0

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Property Sticker: 566442
Daughterboard serno: 51
U3: XCV600-6BG560C 
U5: XCV600-6BG560C 
U1: XCV600-6BG560C

29 Sep 2006: Removed from platform by Marc/Stefan.  PC20-2-2.  This
	     board apparently lost programming.

12 Oct 2006: Failed link test. Link3 bit 3 going to device U3 is bad.
	     Another LCX16244 output bit being pulled high.  Deliver
	     to techs to replace U41.

16 Oct 2006: Link test OK.  Checked all of the signals involved with
	     board configuration and found no problems.  Replace PTC
	     resettable fuse with a normal fuse and replace some of
	     the caps.  This board has been returned to DZERO.

19 Sep 2007: Green dot.  Returning to DZERO.

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Property Sticker: 566604
Daughterboard serno: 50
U3: XCV600-5BG560C
U5: XCV600-5BG560C
U1: XCV600-5BG560C

11 Jun 2007: Pulled from the platform PW03-2-8 (?)

15 Jun 2007: Link test found stuck bit on link4.  lcx16244 buffer input
             pulled high replacing both buffers.  Passes link test; 
             returning to D0.

19 Sep 2007: Green dot.  Returning to DZERO.

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Property Sticker: 566563
Daughterboard serno: 22
U3: XCV1000E-6BG560C
U5: 
U1: XCV1000E-6BG560C

01 Jan 2007: Pulled from the platform (Remi/Marc).  Removed from PC20 slot 6.
             Intermittent erase and losing defaults.

19 Sep 2007: Red dot; awaiting testing at WH14.

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Other daughterboards, not yet attached to a motherboard.  JTO 13 Jul 2006

2x DFEF/DFES type, no serno, not stuffed. 
1x CTQD type, no serno, "jtag ok 9-6-05" ???
1x CTQD type, no serno, "no output clock, link0 errors, L3out errors"  --> junk