Note from comparison between tests made during the week of September 25th 2007 by Stephane and Christophe and raw data taken in May 13th
module counting from 1 to 16 (P side : opposite order 16 -> 1)
Summary :
More investigation : 6N, 7P, 8P, 1N
Capacitor : 2, 10 and 13
LV/HV Connector : 15P, 9P
Modules with no correct JTAG response : 3P mod 14, 3N mod 1, 5P mod 1, 7N mod 13, 14N mod 15 and 16, 16N mod 1, 17P mod 5, 19P mod 13
Not JTAG response related : 13P mod 6, 16P mod 12, 19P mod 11, 20P mod 4 and 15
Ladder 1 :
P : OK, OK
N : OK when looking at raw data, Stephane noticed oscillation of one bit, should make the ladder noisy in data taking, unless it is a high value bit which may be suppressed by the RD board for the acquisition
Ladder 2 : HV trips during the run7 (set to 5 V), a high current is observed when testing it => shouldn't be a cooling issue but probably a capacitor issue.
P : mod 4 weird from data, ok from tests
N : ok
Ladder 3 : HV trips during run7, the current observed is not that high during the test => suspect that HV trip are related to the cooling issue.
P : Not correct JTAG response with module 11 and 14, however there are data coming from module 11 => suspect a broken connection in the JTAG loop after programmation of the module ie the JTAG connection suceeds to program the module but a broken connection happens after the input from the module to check that it is done correctly. Need to force this module.
But can not conclude about the status of module 14 since it was turn off during the run.
N : not correct JTAG response with module 1 but this module was turn off during the run, can not conclude about the status of this module.
Ladder 4 :
P : OK, not correct JTAG response for module 12 but data looks OK => broken connection in the JTAG chain, need to force this module
N : module 5 looks weird in the data, but looks ok during the test
Ladder 5 :
P : OK for data, not correct JTAG response with module 1 but can not tell since it was turn off during the run
N : OK, OK
Ladder 6 :
P : OK, OK
N : dead, dead
Ladder 7 :
P : dead, dead
N : dead from data but OK from the test bench analysis, not correct JTAG response with module 13 but since this ladder was off... Need to look how this ladder was turned OFF
Ladder 8 :
P : data in module 8 weird, funky behavior when tested : good behavior and suddenly (few minutes after turning it ON) module 8 shows a high current and then all the modules don't get any data anymore. (In general, it is observed from the data that the occupancy in ladder 8P is low.)
N : very noisy ladder from data, the pedestal value seems to increase as a function of time (not completely/correctly depleted ?), from the test, nothing special was observed from that point of view.
Ladder 9 :
P : funky data from module 7, nothing special observed during the test except HV/LV connection plug seems freaky, need to change the plug.
N : OK, OK
Ladder 10 : HV trips observed during the run7, high current is observed during the test too
P : module 4 data are funky and module 8 therehold (MUX_P) needs to be reajusted (ADC values > 255) but nothing special regarding these 2 items was observed during the test
N : OK, OK
Ladder 11 :
P : high ADC values in module 14 (need to re-ajust MUX_P), OK from test
N : not correct JTAG response with module 9 but data are OK so probably only a broken connection in the JTAG chain
Ladder 12 :
P : OK, OK
N : OK, OK
Ladder 13 : HV trips during the run7, also high current observed
P : No data observed in module 6, this is also observed during the test, however the module gives a correct behavior during JTAG initialization... To be investigate
N : OK
Ladder 14 :
P : OK, OK
N : funky behavior from data in the whole module like a stuck/missing bits + data from module 15 are weird (while this module has been turn OFF), error in the JTAG response for module 15 and 16, from data, can not conclude for 15 and 16 since these were turn OFF during the run.
Ladder 15 :
P : noisy but nothing observed during the test regarding this. The HV/LV connector is freaky, need to replace it
N : module 2 data are weird, but nothing special was observed during the test
Ladder 16 :
P : error in JTAG response with module 4, 5, 7, 8, 12 and 13 during the tests.
From data, modules 4, 7, 8 and 13 looks OK, so probably broken connection in the JTAG chain.
No data observed from module 12 (This module has been forced).
N : error in the JTAG response with module 1 and 10. From data, module 10 is OK : suspect broken connection in the JTAG chain. Module 1 was turn off during the run, can not conclude about it status.
Ladder 17 :
P : not correct JTAG responses with module 5, from data, this module is OK but it has been forced few days after this data were taken (Error few days later and forced May 16th).
N : OK, OK,
Ladder 18 :
P : OK, OK
N : data from module 11 funky but nothing special observed during the tests
Ladder 19 :
P : one alice128 missing in mod 3, error in JTAG response issue with module 13 but data are ok.
a latchup has been systematically detected in module 11, since in the test bench one do not expect high particle rate, it may be due to high current detection by the FPGA and it turns the module OFF. To be investigate...
N :module 6 has high ADC values, need to reajust the MUX_P, module 11 noisy, but nothing special regarding these 2 items were observed during the test.
Ladder 20 : HV trip sometimes during the run, but stable since we turn off the modules at the edge of the ladder : probably a cooling issue.
P : one alice128 dead detected during the test in module 15, can not confirm from data since this module was turn off,
also from data, on alice 128 dead was observed but in module 4, but this is not detected during the test... Weird...
N : OK