SVX II Upgrade Readout Electronics


Changes To The 
BE Chip Of The SVX 3 Chip Set

- Reduced Quiescent Current
- Low EMI Differential Signal Characteristics 
- Rise & Fall Time Timing Requirements
- Differential 'Odd Byte Data Valid' (OBDV) Signal
- Null Cycle Between Readout Of Two ICs
- Clock Edge To Data & OBDV Transition Timing Requirements



Ed Barsotti & Sergio Zimmermann
(with assistance from several others)
11 April, 1996


Document # ESE-SVX-960411


DRAFT DOCUMENT




TABLE OF CONTENTS

1. INTRODUCTION	
2. QUIESCENT CURRENT OF BACK END INTEGRATED CIRCUIT	
3. LOW EMI DIFFERENTIAL OUTPUTS & REQUIRED RISE & FALL TIMES	
4. 26.5 MHZ INPUT 'READOUT' CLOCK	
5. 'ODD BYTE DATA VALID' DIFFERENTIAL SIGNAL ... 50% DUTY CYCLE & SIMULATIONS REQUIRED	
6. CLOCK EDGE TO DATA TIMING	
7. READ BACK THE CONFIGURATION OF THE SVX 3 CHIP SET.	
8. REFERENCES	

Introduction
This document details changes requested to the Back End (BE) integrated circuit of the SVX 3 IC set.  The changes are listed below and are detailed in the following sections:

Reduce the quiescent current
Conform to low EMI signal characteristics
Insure rise and fall times of at least 1 to 1 nanoseconds but less than 3 nanoseconds
Add a differential 'Odd Byte Data Valid' signal
Add a null cycle between readout of the last byte of one IC and readout of the first byte of the next IC
Insure consistent (equal) timing from a received data readout clock edge and both assertion of data and transition of the 'Odd Byte Data Valid' signal  whether byte being asserted is the first or another byte of the readout
Quiescent Current Of Back End Integrated Circuit
The power supply current of the BE integrated circuit is proportional to the bias current of the data drivers, even when the IC is idle.  The BE chip has to be designed in such a way it consumes less than 8 mA of current when the IC is idle.
Low EMI Differential Outputs & Required Rise & Fall Times
The Low Current Differential Signals (LCDS) specification [1] defines the electrical protocol and timing for low EMI data transmission.  Presently Jihad, an IC designer from Ray Yarema's group is developing a transceiver IC to be used on the Port Card using the LVDS specifications.  We request that all differential outputs and the four shared data/control inputs of the BE integrated circuit conform to the output characteristics of these specifications.  These outputs include both the differential data signals on the BUS[0:7] pins and an 'Odd Byte Data Valid' (OBDV) signal defined in a following section.  The shared data/control inputs are those on the BUS[0:3] pins.

The rise and fall times, and other signal characteristics such as levels, of both the differential data and OBDV signals must be at least 1 to 1 nanoseconds but less than 3 nanoseconds.  These minimum and maximum rise and fall times are required to minimize EMI and to minimize lost data setup and/or hold times at the FIB, respectively. 

Other signal characteristics such as levels of both the differential data and OBDV signals must conform to the "driver AC characteristics" (Table 3) of the Low Current Differential Signals document [1]. 
26.5 MHz Input Readout Clock
The digitization/readout clock into the Back End (BE) integrated circuit remains 26.5 MHz during readout as in the past but particular care must be taken in the logic internal IC to insure very minimal duty cycle variation in this clock as it traverses through the IC and is used to form the Odd Byte Date Valid (OBDV) differential signal.  Reasons for this are explained in see Section 5.
'Odd Byte Data Valid' Differential Signal ... 50% Duty Cycle & Simulations Required
To insure reliable readout at FIB modules some ten meters from the SVX 3 ICs, a differential 'Odd Byte Data Valid' (OBDV) output signal must be added to the BE integrated circuit.  It is critical to the reliable reception of data at the FIB that both legs of the output differential OBDV signal, be as close in duty cycle to that of the input 26.5 MHz readout clock.  This input 26.5 MHz clock will be almost a 50% duty clock as it is generated in the Port Card by dividing a 53 MHz clock by two.  The OBDV signal is simply a gated input 26.5 MHz clock.  We require either leg of the differential output OBDV signal to not vary more than ( 1% in duty cycle from this input clock.  We request to see simulations (see Section 5) of this timing before the revised SVX 3 back end IC is submitted for fabrication.

The OBDV signal will be AC terminated at both ends of the cable from the Port Card to the SVX 3 ICs and will be DC biased at the Port Card such the state of OBDV = 0 and its compliment = 1 when no SVX 3 IC is driving this differential signal.  This termination and DC biasing will be external (e.g., not in an SVX 3 IC).  During the transmission of odd bytes (1, 3, ) of data from an SVX 3 IC, this signal is at logic 1.  Likewise, during the transmission of even bytes (2, 4, ) of data from an SVX 3 IC, this signal is at logic 0.  The transitions of OBDV coincide with those of data.

Figure 1 illustrates the operation of the 'Odd Byte Data Valid' signal for one SVX 3 IC.  Both the data and the 'Odd Byte Data Valid' signal are differential as described in Section 3.  Only the true (non-compliment) side of each signal is shown in Figure 1.  As with the data outputs, the 'Odd Byte Data Valid' signals should be differential and should conform to the driver specifications of the Low Current Differential Signals document [1].  Details of Figure 1 follow.  Rising edges of the 53 MHz clock to the Port Card (rising and falling edges of the 26.5 MHz clock from the Port Card to the SVX 3 BE IC) have been numbered to simplify understanding of the operation of this signal.  Priority In* and Priority Out* are low-true signals:

The 'Odd Byte Data Valid' signal is not being driven by any SVX 3 IC up to the trailing (low-going) edge of the SVX 3 BE IC's input 26.5 MHz clock (edge #3).  DC biasing on the Port Card is maintaining 'Odd Byte Data Valid' at logic 0 up until this time.
The receipt of the Priority In signal (low-going edge of 'Priority In*') starts the readout of the BE integrated circuit.  This signal has to transition low between a falling edge and the next high-going rising (edges #1 and #2, respectively) of the input 26.5 MHz clock.  Set up times at the PI input of the SVX 3 IC will be met by Port Card circuitry. 
The next falling edge (edge # 3 in Figure 1) of the input 26.5 MHz clock after the receipt of 'Priority In' = 1 ('Priority In*' = 0) causes the 'Odd Byte Data Valid' signal to be driven to logic 0 by the SVX 3 BE IC.  The signal was previously tri-stated by the SVX 3 BE IC and biased at logic 0 by external components.
At edge # 4, the SVX 3 BE IC asserts its data lines and, at the same time, drives the 'Odd Byte Data Valid' signal to logic 1.  Previously the data signals were tri-stated by the SVX 3 BE IC.
The readout proceeds with the 'Odd Byte Data Valid' signal toggling in synchronism with the assertion of the Status, Channel Number and Data bytes. 'Odd Byte Data Valid' is always at logic 1 during odd byte transmissions and at logic 0 during even byte transmissions.
At edge #7, the SVX 3 BE IC asserts its last data byte, sets 'Odd Byte Data Valid' to logic 0, and sets its 'Priority Out' signal to logic 1 ('Priority Out*' = 0).  The timing of 'Priority Out' must be such that the minimum set up time for the 'Priority In' signal of the next SVX 3 BE IC is met under all conditions.
At edge #8, the SVX 3 BE IC tri-states its data lines.
At edge #9, the SVX 3 BE IC tri-states its 'Odd Byte Data Valid' signal.


Figure 1
"Odd Byte Data Valid" Operation For A Single SVX 3 BE IC


Figure 2 illustrates the operation of the 'Odd Byte Data Valid' signal during transfer of readout from one SVX 3 BE IC to the next.  Note the addition of a null cycle between readout of successive ICs.  Details of 
Figure 2 follow:

SVX 3 BE IC 'N' asserts the last data byte, sets 'Odd Byte Data Valid' = logic 0, and sets 'Priority Out' = logic 1 at clock edge #2.
At edge #3, the beginning of the null cycle, BE IC 'N' tri-states its data signals and BE IC 'N+1' (the next SVX 3 BE IC) drives 'Odd Byte Data Valid' to logic 0.  This IC had had its OBDV driver tri-stated.  Since the 'Odd Byte Data Valid' signal is driven by a current sources, when both SVX 3 ICs are driving 'Odd Byte Data Valid' to logic 0, the voltage on the signal line simply drops to a lower positive output than when a single IC is driving the signal to logic 0.
At edge #4, BE IC 'N' tri-states its 'OBDV' driver.
At edge #5, the end of the null cycle, BE IC 'N+1' asserts data and sets its 'Odd Byte Data Valid' signal to logic 1.  Readout then proceeds as in Figure 1. 

The additional null cycle occurs between clock edges #3 and #5.  During this cycle no data is being asserted by either IC (data lines in their tristate mode).


Figure 2
Readout Of Two Successive SVX 3 BE ICs & The Null Cycle Operation


Author's comment:	Figures 1 and 2 and accompanying text throughout this document include details describing the timing of the SVX 3 IC assertion of 'Priority Out' ('Priority Out*' transitioning to logic 0).  The timing of this signal's assertion is detailed but not its removal.

Other important characteristics of the 'Odd Byte Data Valid' differential signal are as follows:

The electrical protocol of the 'Odd Byte Data Valid' signal should be the same as that for the data lines on the BUS[4:7] pins.
Some mechanism must guarantee that the 'Odd Byte Data Valid' signal always starts in logic level 0 (must be set internally by the SVX 3 BE IC at the receipt of 'Priority In' = 1).  One suggestion is to hold OBDV reset as long as a SVX 3 BE IC is not in readout mode and its 'Priority Out' signal is high.
It is necessary to make sure that the previous chip asserts 'Priority Out' in such a way that it respects the set up time of the 'Priority In' of next chip.
The assertion of data, the 'Odd Byte Data Valid' signal and 'Priority Out' should be edge-triggered by the internal 26.5 MHz clock edges.
Finally, though the readout speed will depend on implementation and technology of the BE integrated circuit, we request that the data lines supply valid information as quickly as possible after an internal 26.5 MHz clock edge and definitely before the next 26.5 MHz clock edge.  This has been accomplished in the SVX 2 IC.  Note that it is critical to the secure reception of data at the FIB module that the time from a 26.5 MHz clock edge to the assertion of data and 'Odd Byte Data Valid' be the same for first and all other data bytes (see Section 6).
Clock Edge To Data Timing
It is critical that the timing from either edge of the input 26.5 MHz clock to both the assertion of resultant data and the transitioning to the opposite stable state of the 'Odd Byte Data Valid' signal be consistent (approximately equal) from one data byte to the next regardless whether the data byte is the first or any other byte asserted by a SVX 3 BE IC.  The timing from either edge of the of the 26.5 MHz clock to the removal of data must not only be consistent (approximately equal) from one byte to the next but consistent (approximately equal) to that for the assertion of data.  These timings must also be consistent between any SVX 3 BE ICs.  The timing from a rising edge of the 26.5 MHz clock to the tri-stating of data must also consistent (approximately equal) between any SVX 3 BE ICs.

Discounting rise and fall times, data and the OBDV signal should be valid at the output of a BE chip for very nearly one half 26.5 MHz clock period (~ 18.9 nanoseconds).  Finally, this timing should remain consistent regardless of temperature and power supply voltage variations of the BE chip as well any variations cause by radiation effects to whatever extent that is practical.
Read Back the Configuration of the SVX 3 Chip Set.
We request another method to read back the configuration of the SVX 3 IC set.  Right now the procedure that we have adopted is to externally force the 'Priority Out' signal of the last IC in a chain of ICs onto one of the data lines. We request that the BE integrated circuit perform this task automatically, as we will explain below:

Add a pad on the side of the BE chip, close to the 'Priority Out' pad.  This pad has a internal pull-up resistor. 
The last IC in the chain of Priority Out/Priority In will have this pad grounded. 
If the pad is grounded and the BE integrated circuit is in configuration mode, the IC activates (removes from tri-stated mode) the BUS[7] differential signal and forces the configuration stream onto this line.  BUS[0:6] signals continue tri-stated.  The IC can continue to deliver the configuration stream on the 'Priority Out' signal.
If the pad is floating (it is internally pulled up), the BE integrated circuit leaves all differential signals tri-stated during configuration.
References
[1]	E. Barsotti & S. Zimmermann, Low Current Differential Signals, Doc. # ESE-SVX-950605, CD/ESE, Fermilab, 1995



Some SVX 3 IC Proposed Changes	09:01 AM	10/19/95

i


5