SVX II Silicon Strip Detector Upgrade Project


Dense Optical Interface Module (DOIM)




--PRELIMINARY--




March, 1996


Minglee Chu, Maotung Cheng, Yi-Cheng Liu




Academia Sinica
I. 	
GENERAL INFORMATION	1
II. 	FUNCTION AND INTERFACE OF DOIM TO SVXII	1
A. 	Functional Description of the DOIM	2
B. 	The Interface of DOIMs to SVXII system	4
C. 	Basic Requirements of DOIM	5
III. 	SPECIFICATIONS	6	
A. 	Packaging, Physical Size and Material	6
B. 	Pin Configurations and Signal Description	8
C. 	Electrical I/O Levels	11
D. 	Electrical Specifications	11
E. 	Power Requirements	13
F. 	Cooling Requirements	14
G. 	Environmental Requirements	14
IV. 	OPTICAL POWER BUDGET	15
V. 	QALITY ASSURANCE PROCEDURES	15
A. 	Quality Control Procedures in Production	16
B. 	Quality Assurance before Installation	18
VI. 	REFERENCES:	19
APPENDIX A 	A-1
1 	GENERAL INFORMATION

The Dense Optical Interface Module (DOIM) is a parallel byte-wide (w/clock) optical link used to transfer data from the Port Card [1] of SVXII detector to the Fiber Interface Boards (FIB)[2]. It replaces the conventional copper wires with optical fibers as the major data transmission medium due to its high bandwidth and EMI immunity. With the high luminosity and short bunch spacing in RUN II of Tevatron, the data rate is expected to be very large in the silicon vertex detector. The data transmission rate must be high enough to be ready for the level two triggers. Fiber optical technology has the benefit of high speed, however, the commercially available connection scheme do not meet the space limitation in SVXII environment. Therefore, a custom interconnection scheme has to be developed. The purpose of this document is to provide sufficient information for circuit designers to interface with the DOIM. Refer to the Appendices for the internal details of the DOIMs.
2 	FUNCTION AND INTERFACE OF DOIM TO SVXII

The function of DOIM is to replace the standard multi-channel line driver and receiver pairs by utilizing fiber optical technology. From a circuit designer's point of view, there is little or no difference between using DOIM or a standard driver-receiver pair, except that DOIM sends data through optical fiber with optical signal and DOIM is capable of operating at higher data rates and the copper has been replaced with optical fibers. 

2.1 	Functional Description of the DOIM

There are two modules making up one DOIM pair, one Transmitter Module (TX), and one Receiver Module(RX). Each TX and RX pair have nine identical channels. With externally defined 8-bit data channels and one bit clock channel, one pair of DOIM TX-RX provides one byte parallel transmitter and receiver pair.

The function of the TX is to accept nine independent digital electrical signals, and convert the electrical 'high' or 'low' signals to optical 'on' and 'off' signals. The function of the RX is to accept the nine channels of optical signals from remote TX, then convert the optical signals back to electrical signals.

Each module of the DOIM TX and RX consist of a hybrid package and a short optical ribbon fiber pigtail. The electrical contacts to the exterior of the modules are made with metal traces on the ceramic substrate for wire-bonding. The ribbon pigtail is the optical output(input) of TX(RX). The other end of the pigtail is terminated with standard MT type connector. The package of the TX module contains a custom chip and a Laser Diode Array (LDA). The chip internal to the TX accepts the electrical digital signals from other circuit outside TX and translates them to the proper current level to drive each LD in the LDA. The optical outputs from LDA are then coupled to the fiber ribbon output pigtail.

Internal to the package of RX, there is a custom receiver chip and a Photo Diode Array (PDA). The optical signals were fed into RX through a fiber ribbon pigtail. Each channel of the fiber ribbon is aligned with each PD of the PDA. The custom chip of the RX amplifies and digitizes the small current signals from PDs of PDA. The electrical output of the RX is standard digital differential ECL signals.

To provide complete data transmission link over a distance greater than few meters to a few ten's of meters, fiber ribbon with MT connectors on both ends as interconnection are required. Figure 2-1 shows the idea of a complete data link implementing a DOIM TX-RX pair.


Figure 2-1 Block diagram of one byte DOIM data link
2.2 	
The Interface of DOIMs to SVXII system

The TX will be implemented on the port card which is mounted at the edge of the SVXII barrels. The TX receives the digital input signal from the data bus of port card. The design of port card provide Low Current differential signal (LCDS) [3] digital signals to the TX. The RX will be implemented on the Fiber Interface Boards (FIB) which is mounted outside the detector. The output of DOIM RX is differential ECL signals to FIB. 

There will be five DOIM TXs on each port card. In the current design of SVXII, there are three barrels with 12 wedges per barrel and 2 port cards per wedge. The total number of DOIMs needed for the SVXII project is 360 pairs (spares are not included).

2.3 	Basic Requirements of DOIM 

As a digital data transfer device, it was essential to perform data transfer in designated data rate with reasonable low Bit Error Rate (BER). The requirements for the SVXII upgrade requires that the DOIMs operate at a data rate of 53Mbyte/sec/DOIM. Since the DOIM is designed for parallel data transfers, special care should be taken on the signal switching characteristic as well as the matching of timing between channels of the DOIM.

Other than the electrical and optical properties, radiation hardness, high density package, low total mass and low power dissipation is essential for TX to be used inside collider detector. A radiation hardness of 200 Krad is estimated to be sufficient for the RUNII experiment. As for the package size, mass and power dissipation, it is asked to be as small as reasonably possible .
3 	SPECIFICATIONS

Both the DOIM TX and RX should be viewed as a device from a circuit designer's point of  view. The format of data I/O is straightforward. However, the requirement of minimizing the package size implies non-standard pin configuration and special circuit board placement methods. Additional precautions should also be taken for the optical nature of the transmission medium during the handling and testing of DOIMs.

3.1 	Packaging, Physical Size and Material

Figure 3-1 gives the outline and dimensions of TX as well as RX. The package size of DOIM are 18mm x 8mm x 3.5mm and 15mm x 8mm x 3.5mm for TX and RX, respectively. The pitch of the I/O pins are 350um Both for TX and RX. (Refer to Appendix for details)

There are four plastic nuts on the bottom of the substrate for both the TX and the RX. It is required to have holes on the port card and the FIB to provide good thermal contact between the port card/FIB and the DOIM substrate. The location of and minimum hole size are as shown in Figure 3-1 . 

Table 3-1 lists the material used in DOIM. 


Figure 3-1	Outline and dimensions of DOIM and the example of the hole on the port card  and FIB to accept the nut of TX and RX respectively. The  black "L" shapes represent the corners of DOIM on circuit board. The half circles are the minimum holes required to accept the nuts of DOIM.( unit : (m )

Components
Material
Dimensions (in mm)


TX
RX
Substrate
BeO or  Al2O3
18 x 8 x 0.5
15 x 8 x 0.5
Submount
BeO or Al2O3
4.5 x 4 x 0.3 
6.2 x 2 x 1.5
Si 'V' groove
Si
4.5 x 4 x 1
O/E,E/O chip
GaAs
3.5 x 0.3 x 0.3
3.5 x 0.3 x 0.3
IC chip
Si or GaAs
3.5 x 2 x 0.3 
3.5 x 2 x 0.3 
Cover
Plastic
(Epoxy)
outline:
17.5  	x 8 x 0.5
wall thickness:
~ 1
outline:
14.5  	x 8 x 0.5
wall thickness:
~ 1

Table 3-1 Materials of DOIM ( fiber ribbon and connector not included)

3.2 	Pin Configurations and Signal Description


Figure 3-2 and Table 3-2 shows the pin out of both the TX and the RX of DOIM. The I1p, I1n to I9p, I9n 1 pins are the digital inputs of the TX. The 'EN' pin is the enable control which serve the purpose of saving power by turning off all LDs while data transmission is not needed. The O1p,O1n to O9p, O9n pins are the digital outputs of the RX.

The electrical connection of the DOIM TX or RX to printed circuit board of the port card or FIB should be wire-bonded. The thin film gold metal on the bottom side of DOIM is connected to Vee internally for both TX and RX. 




Figure 3-2  Pin out of DOIM TX and RX.



Transmitter
Receiver
Pin #
pin name
description
pin name
description
1
Vee
ground
Vee
ground
2
enable
enable/disable LDA
Vee
ground
3
I1p
1st channel '+' input
O1p
1st channel '+' out
4
I1n
1st channel '-' input
O1n
1st channel '-'out
5
I2p
2nd channel '+' input
O2p
2nd channel '+' out
6
I2n
2nd channel '-' input
O2n
2nd channel '-' out
7
I3p
3rd channel '+' input
O3p
3rd channel '+' out
8
I3n
3rd channel '-' input
O3n
3rd channel '-'out
9
I4p
4th channel '+' input
O4p
4th channel '+' out
10
I4n
4th channel '-' input
O4n
4th channel '-' out
11
I5p
5th channel '+' input
O5p
5th channel '+' out
12
I5n
5th channel '-' input
O5n
5th channel '-'out
13
I6p
6th channel '+' input
O6p
6th channel '+' out
14
I6n
6th channel '-' input
O6n
6th channel '-' out
15
I7p
7th channel '+' input
O7p
7th channel '+' out
16
I7n
7th channel '-' input
O7n
7th channel '-'out
17
I8p
8th channel '+' input
O8p
8th channel '+' out
18
I8n
8th channel '-' input
O8n
8th channel '-' out
19
I9p
9th channel '+' input
O9p
9th channel '+' out
20
I9n
9th channel '-' input
O9n
9th channel '-' out
21
Vcc
+5V supply
Vcc
+ 5V supply
22
Vld
power supply connect to the  common cathode of LDA
Vee
ground
23
Vld
power supply connect to the  common cathode of LDA
Vee
ground

Table 3-2 The pin name and functional description of DOIM
3.3 	Electrical I/O Levels

Transmitter
Each input of DOIM TX accepts differential voltage signals, with a voltage difference (Vdi=|V(Iip)- V(Iin)|) greater than 100mV. DOIM TXs interpret Vdx > +100mV as a logical high and Vdi < - 100mV as a logical low. Together with the termination resistor on the port card, the input of the TX complies with the required LCDS interface protocol.
The active low enable pin accept standard TTL level signals. 

Receiver
The outputs of the RX are compatible with differential ECL. As standard ECL devices, the output can be configured as positive ECL or negative ECL depending on the power supply configuration. By connecting +5V to Vcc and ground to Vee the outputs are positive ECL. By connecting ground to Vcc and -5V to Vee the outputs become standard ECL.

3.4 	Electrical Specifications
Table 3-3 lists the electrical specification of DOIM.

Common to TX and RX , over operating temperature range
nominal data rate
53Mbytes/sec
bit error rate
< 10-12
skew between each channel
(from the input of TX to output of RX, including the optical cable)
< 0.5ns
timing jitter
(from the input of TX to output of RX)
< 0.5ns
RX output duty cycle range of each channel
(with 26.5Mhz, 50% duty cycle input from TX)
45 to 55 %
operating temperature range (substrate)
-10to 35
Table 3.3a Common specifications of DOIM

DOIM Transmitter (TX)
input protocol
digital LCDS (differential voltage resulting with external termination resistor should be greater than 100mV)
input switching characteristic
tr, tf <2ns
Optical wavelength 
1550mm (10 mm)
optical output power
      (output from pigtail)
> 200(W/channel, on*
< 800(W/channel, on**
< 10(W/channel, off 
optical switching characteristic 
tr, tf <2ns ( time between 10(W and 200(W)
enable control signal
low active, TTL
Power supply
5V(0.5V ) and an additional voltage sinker with voltage Vcc-3V(0.5V). See next section for details
Power dissipation 
< 2W/TX (total)
< 1W to turn all LDs on,
1W constant for other circuit elements
Radiation hardness
> 500Krad*
Package dimension (not including pigtail)
18mm x 8mm x 3.5mm
*	200(W/channel optical power is for non-irradiated TXs. After 500Krad accepted the output power may degrade but should still be greater than 100(W.
** 	Maximum output power of TX is required to keep the RX from being saturated.

Table 3.3b Specifications of TX

  DOIM Receiver (RX)
input sensitivity range
(input from optical link)
>50(W(1550mm) for digital '1'*
usable up to 800mW
<10(W for digital '0'
Output protocol 
differential ECL
output switching characteristic 
tr, tf <2.5ns ( with 20% and 80 % between high and low)
Power supply   
5V(0.5V ) 
Power dissipation
<1.1W/RX, internal, constant
~0.9W/RX, external, constant **

Package dimension (not including pigtail)
15mm x 8mm x 3.5mm
*	The input sensitivity varies smoothly within the wavelength range from 1550mm to 1300mm. The input power requirement increase about 1.3 times if input wavelength is 1300mm. 
**	Assuming 390W pull down to ground resistor connected to all outputs.
Table 3-3c  Specifications of and RX

3.5 	Power Requirements

Transmitter
There are 3 pins for the power connection, Vcc, Vee and VLD . Vcc and Vee should be connected to 5V(0.5V ) and ground, respectively. The VLD pin is the common to the cathodes of the laser diode arrays (LDA)s internal to the TX. VLD should be connected to a precise, adjustable supply which can sink current at voltage about -3V referenced from Vcc, as in Figure 3-3 . It is important to keep VLD referenced to Vcc in order to keep the driving current to LDA stable. The constant voltage current sinker at VLD is required to sink up to 300mA per TX (with all the LDs are turned on). The voltage of the VLD controls the output optical power of the LDs. The adjustable range will be decided later, 0.5V should be sufficient.

Figure 3-3 Power supply connection of TX.
Receiver
The power supply for the RX is Vcc - Vee = 5V(0.5V ). It is helpful to use another 3V supply (referenced from Vee ) to reduce external power dissipation on the pull down resistor. In the case of dual supply, 50W to 100W of pull down resistors are recommended.

3.6 	Cooling Requirements

The output power of the Laser Diode is quite sensitive to the temperature. Although the specified operation temperature range is between -10 to 35, good thermal conduction and cooling is recommended for the TXs to keep the substrate temperature within the range from 0 to 20. The RXs will operate at less stringent conditions.

3.7 	Environmental Requirements

The dimension and material requirements of DOIM pose the limit that DOIM can not be hermetically sealed. The opto-electronic devices inside DOIM are sensitive to humidity. Controlled humidity environment is required in any time to keep DOIM from damage. It is also suggested that care be taken with the temperature difference between DOIM and ambient (especially when in higher ambient temperature while DOIM itself is cold) to prevent water vapor condensation on the surface of opto-electronic device.
4 	OPTICAL POWER BUDGET

Optical output level of TX and the sensitivity of RX is the most important factor to keep DOIM link operate. According to the preliminary study, we know that optical fiber is the only non-radhard component in the DOIM data link. With about 50Krad of dosage accepted by standard glass fiber, the transmission lost is as much as 30% to 50%. Table 4-1 lists the optical power budget for DOIM, based on the assumption that the radiation induced lost is within 50%, from TX to RX. Refer to the Appendix for the radiation properties of the components of DOIM.


Fresh
End of RUNII
Output from TX pigtail
200 mW to 800 mW
100 mW to 400 mW
Coupling efficency
(2 MT to MT connection)

>70 %
Coupled to RX
140 mW to 560 mW
70 mW to 280 mW
Input high threshold of RX
<50mW
Max. Input power of RX
800mW
Threshold power Margin of RX

>90 mW

> 20 mW

Table 4-1 Optical power budget of DOIM link
5 	QALITY ASSURANCE PROCEDURES

Quality assurance will be achieved by performing tests on each sub-component as well as on the completed packages of DOIM while in production. Double-check are also scheduled to be performed in Fermilab before installing on port card/FIB. 

5.1 	Quality Control Procedures in Production

Figure 5-1 explain the flow chart of the assembling process of DOIM. Dashed blocks indicate the tests which will be performed .The tests of the LDA/PDA on the sub-mounts and the test of chips on the substrates serve the purpose for selecting good semiconductor devices. DC performance tests before and after burn-in on sub-component level are usually enough to give component to pick out most failed devices. 

After the DOIMs have been produced, a series of tests will be performed. Table 5-1 is the list of these tests. Note that some tests such as BER[4] and reliability(lifetime) will be performed only by sampling for practical reasons. Only the DOIMs which pass all the tests after burn-in will be shipped to Fermilab.


Figure 5-1 The Assembly Process of DOIM
(refer to the appendix for the detail inside DOIM)
5.2 	
Quality Assurance before Installation
     
The packaged DOIM modules will go through component-level testing and quality control as described in the previous section. After the shipment to Fermilab, a final stage testing should be carried out to ensure that quality of DOIM is within the specification. Since all the DOIMs should have gone through all the tests and give reasonable degradation comparisons before and after burn-in, the double-checks in Fermilab should be enough to confirm the reliability of them. Basically, one can do all the tests listed in Table 5-1 to confirm the qualities. Follow the priority recommendations in the last column of Table 5-1 to arrange the testing procedures. Small quantity burn-in and reliability tests can also be done in Fermilab.

	DC tests
		Input voltage threshold	(TX)			* 
		Output optical power 	(TX)			***
		Input optical power range	(RX)			*
		Output voltage level	(RX)			*
		Supply voltage range	(TX,RX)		s+,*
		Supply current	(TX,RX)		s+,*
		Power dissipation	(TX,RX)		s-,*
	AC tests
		Optical switching characteristics	(TX)			**
		Optical skew		(TX)			s+,*
		Optical jitter		(TX)			s+,*
		Electrical switching characteristics	(RX)			**
		Electrical skew		(RX)			*
		Electrical jitter		(RX)			*
		Duty cycle		(TX+RX)		s-	
		BER		(TX+RX, sampling)	s-,***

Note. Input/Output level DC tests will be performed before and after burn-in. All other tests will be performed only after burn-in.
Last column is the recommendation on the tests in fermilab
s	test by sampling only, +/- means more/less percentage of sampling recommended
* 	test in Fermilab recommendations, more * means more care should be taken for the test.

Table 5-1 list of the tests which will be performed before shipping.
( the last column is the note to suggest the double check tests in Fermilab. )

6 	REFERENCES:

[1]	J. Andresen, K. Treptow, S. Zimmermann  --  Port Card for the SVXIII Chip (1995).
[2]	K. Woodbury  --  Fiber Interface Board (1995).
[3]	E. Barsotti, S. Zimmermann - Low Current Differential Signal, ESE-SVX-950605  (1995)
[4]	D. Husby  --  BERT, Bit Error Rate Tester (1995). ( Note : The outputs of the current version of BERT is not LCDS, level-conversion adapter board is required for testing the DOIM TXs. )
1 Iip ( Iin ) means the positive (negative ) input pin of the i-th channel.
18



DOIM specification		06/28/96
		

18


	
-M.L. Chu, M.T. Cheng, Y.C. Liu		i



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-M.L. Chu, M.T. Cheng, Y.C. Liu		10