Design, supporting documentation, and tools for a
Low Level RF (LLRF) evaluation board.

To make full use of the files in this kit, you will need a copy
of pcb (http://sourceforge.net/projects/pcb) and xcircuit
(http://opencircuitdesign.com/xcircuit/).  Both are Open Source/
Free Software.  They may or may not be available or useful on
Microsoft-based computers.  This board design was done on Debian
Sarge, a stable Linux distribution.

The known-good versions of these two pieces of software are
pcb-20040903, patched with the (included) pcb-bga-20060720.patch,
and xcircuit-3.1.19.  Both of these tools are in the midst of
active development.  Newer versions will probably also work,
as both have the policy of maintaining input compatibility
with older design files, like the ones in this kit.  The reverse
is not true; until I upgrade my tools from this ancient pair,
please don't send me files written by newer versions.  The
instructions and scripting in this kit are more fragile than
the design files themselves.

The two largest files in this kit are combo15.ps, a schematic,
and study46.pcb, the layout.  The two are related by a full board
netlist, generated as follows:

1. The parts of the design properly represented as a schematic
are kept in combo15.ps.  This file can be directly viewed by
any Postscript file viewer, like Ghostview.  It is also the
native file for the xcircuit program.  Use the xcircuit Netlist
menu to "Write pcb" to make the file "combo.pcbnet", containing
the resulting netlist.

2. Xilinx supplies the file spartan3_ft256.csv with FPGA pin
information.  This is used for power and ground pin assignment.

3. FPGA user I/O mapping is extracted from the mess2 file, which
has been pulled out from the layout tool (pcb).  This information
will also be used to make a constraint file for FPGA programming.

4. The wiring between the FX2 USB chip and the FPGA is specified
in the fx2-nets file, in tabular form.

5. A short perl program (pcb_netlist_hack3) combines information
from the above sources to make the final netlist: foo.pcbnet.
pcb_netlist_hack3 also includes the power supply assignments
to the eight FPGA banks.

The processing to generate the final netlist is automated by the
Makefile.  "make foo.pcbnet" should get you there.  Once foo.pcbnet
is complete, it can be imported into the layout program under
File/Load netlist file.

The second interesting automation step is the creation of orderable
parts lists.  This combines the parts list output from the layout
(*output_bom.txt) with a database of possible parts (parts.data).
Results are digi.dat (ready for on-line ordering at Digi-Key),
other.dat (the non-Digi-Key parts, shown with prices and supplier),
and cost_print.tex (incorporated in the documentation packet).

The Makefile also guides creation of the following targets:
   packet.pdf       documentation of the design, including text,
                    summary BOM, schematic, and layout check prints
   board4-fab.zip   board fabrication instructions, including
                    Gerber (RS-274X) files
   board4-assy.zip  board assembly instructions, including drawings
                    and a part coordinate file

Questions?  Comments?  Call Larry Doolittle at Lawrence Berkeley
National Lab.  Phone 510-486-7382, e-mail ldoolitt@recycle.lbl.gov