SVX II Silicon Strip Detector Upgrade Project


LOW CURRENT DIFFERENTIAL SIGNALS


Document # ESE-SVX-950605


--PRELIMINARY--



January 30, 1996



Ed Barsotti & Sergio Zimmermann

1. GENERAL INFORMATION	
2. ELECTRICAL SPECIFICATION	
3. DRIVER CHARACTERISTICS	
3.1 DRIVER OUTPUT LEVELS	
3.2 DRIVER SHORT-CIRCUIT SPECIFICATION	
3.3 DC AND AC OUTPUT IMPEDANCES	
3.4 DRIVER TRANSITION TIMES	
4. RECEIVER CHARACTERISTICS	
4.1 RECEIVER INPUT LEVELS	
4.2 RECEIVER DIFFERENTIAL AND COMMOM MODE INPUT IMPEDANCE	
4.3 RECEIVER COMMON-MODE REJECTION	
5. REFERENCES	

GENERAL INFORMATION
The primary goal of these specifications is to define a low current differential signals (LCDS)  physical layer for data transmission. The present application intended for this protocol is the transmission of data, commands and clocks between the Port Card and the Fiber Interface Board. Due to the fact that some of these drivers and receivers will have to be assembled on the Port Card, it will be necessary to adapt the design to a rad-hard technology. For related specifications and other source of information see [1] and [2].
These specifications alone are not complete. They only specify the physical layer for data transmission. They are independent of the number of drivers and receivers that we will need in each chip and the type of input of the drivers and output of the receivers. Figure 1 shows one of the possible instance for a driver and receiver using this protocol. Therefore, these specifications should always be supplemented by another specification that describes these other important characteristics of the drivers and receivers. Also, some of their details may be overwritten by some other set of specs.



Figure 1. Driver/receiver chip for eight bit plus clock data transmission
The main characteristics of this protocol are the following:

The clock edges are used as the time reference to sample the data.
Specified for a maximum frequency of 53 MHz and data transfer rates of 70 Mbps (35 MHz).
Differential current signals, with small adjustable current swings for optimization of low EMI radiation  and power dissipation.
Receivers with selectable hysteresis.
Unidirectional or bi-directional operation (if enables are used)
Driver and receiver with controllable tri-state output mode.
Specified minimum and maximum rise and fall times.
Intended for cables with characteristic impedance between 25 ( to 120 (.
Allows for different types of cable termination.
The control lines for the current swings and hysteresis must be common to several (or even all) drivers and receivers inside one chip. This is indicated in Figure 1 by the signals IREF and H.
By carefully complying to these characteristics, the maximum distance attainable by this link is limited by skew, attenuation, jitter and distortion of the signals.

ELECTRICAL SPECIFICATION
Figure 2 shows a proposed model for the output of the driver. This conceptual model is only intended to make the ideas behind these specifications easier to explain. It is not, by any means, intended for the actual design of the driver.
The two current sources supply the same current (tolerances are described later) and are controlled by the same reference input (IREF in Figure 2). The transistors operate like switches, sourcing or sinking current from the outputs OA and OB. The control of the transistors (signals A+ and A- in Figure 2) must be such that the transistors behave in the following way: when the driver input (not shown in Figure 2) is set to ONE, transistors TA1 and TB2 are closed, while TA2 and TB1 are open; when the input of the driver is set to ZERO, we have the opposite, transistors TA2 and TB1 are closed, and TA1 and TB2 are open.


Figure 2. Driver design model

We have the capability to set the output signal level at the driver side. We also would like to be able to adjust the hysteresis of the receiver. With this, one can set these parameters of the driver and receiver for the smallest signal level possible, while still keeping the proper signal to noise ratio (and therefore the bit error rate). The advantage is that smaller signals account for smaller power dissipation in the driver in addition to smaller EMI radiation on the cables. Note again that, as we indicated in Figure 1, the signals IREF and H are common to several (if not all) drivers/receivers inside a chip.
The proposed driver allows for different cable termination schemes, since the terminators are not added into the devices. In this section, we will present two of these terminations to aid in explaining the electrical characteristics of these devices. 
To select the proper termination scheme, we need to consider the reflection in the driver side of the cable. For example, if one is using this protocol to transmit unidirectional information in single pairs of cables, an unterminated driver as suggested in Figure 3 should suffice. In this case, the driver is sourcing/sinking current in the cable, which will travel up to the receiver side. There, it will not reflect back because the cable is proper terminated with Z0/2 resistors, and the receiver will discriminate between two logical levels. The signals E and  are, respectively, the enable and enable_not of the tri-state outputs of the transmitter and receiver, while IN and OUT are, respectively, the input and output of the driver and receiver. Also, note that this scheme may experience problems in noise environments, as we explain in the next paragraph.


Figure 3. Cable termination just on receiver side

	In case parallel information is being transmitted through ribbon cables, we can experience crosstalk between lines, which will couple a small signal in the adjacent pairs of cables. This small signal will travel in both directions of the adjacent pairs, and will reflect in the unterminated driver side. When it arrives to the receiver side, this spurious signal can be enough to cause the receiver to produce incorrect decision about the logical level of the input. Therefore, for ribbon cables it may be necessary to use the termination scheme suggested in Figure 4, where the driver side is also properly terminated. The same reasoning is valid if one is operating in noise environments. The two resistors R are used to bias the input of the receiver when the driver is not connected or tri-stated. In order to keep the input impedance very close to Z0, R need to be much greater than Z0.

Figure 4. Cable termination in both sides

These two termination schemes result in two different ways to consider the driver behavior. In Figure 3, the driver works as current source/sink, while in Figure 4, the set of driver and associated termination behave more like voltage sources for the cable. However, the fact that the driver is actually composed of current sources/sinks, allows the user to design the most suitable termination scheme for the specific application.
The differential input of the receiver discriminates differential voltages levels. Figure 5 shows the conceptual model of the receiver, with the additional selectable hysteresis. The hysteresis is fixed by the feedback resistor RF, which can be connected or disconnected by the switch. The position of the switch is controlled by the input H. Table 1 shows the effect of the control input H on the hysteresis.

Control input H
Operation

high
hysteresis enabled

low
hysteresis disabled

Table 1. Hysteresis control
Again, the model is only intended to give us better conditions to explain the ideas behind these specifications. The hysteresis is important in receiver design to eliminate the possibility of oscillating receiver output when the differential input is undefined. The undefined input can occur when the receiver inputs are unconnected, when the driver is powered down, or when transitioning between defined values. RF has to be far larger than R in order to avoid the positive feedback voltage to appear in the input of the receiver, as well as to keep the input impedance higher than the required minimum. The differential input voltage will be given by the line impedance, termination and the output current selected for the drivers.


Figure 5. Receiver design model

It is interesting to observe that the LCDS is independent of the interconnect media. As long as it has the adequate impedance and delivers the signal to the receiver within adequate noise and skew margins, the interface will operate properly.
The power supply voltage for both driver and receiver, is 5 V ( 5%. An important consideration on the design of these units is the tolerance to the common mode voltage (VCM, see Figure 3 and Figure 4), which will unavoidably occur between the drive and receiver. In order to keep the VCM to a maximum, the output voltage of the outputs of the driver should be centered around 2.5 V. By this reason, in Figure 3 and Figure 4, we have Z0/2 impedances connected to VCC/2.
All inputs and outputs of drivers and receivers must be protected against ESD at voltages up to 2 KV as tested under MIL-STD 883C, Methods 3015.7.
Table 2 to Table 5 contain the electrical DC and AC specifications of the driver and receiver, while Table 6 contains the absolute maximum rating. The next sections will describe in details each one of these electrical parameters.

VCC=5V ( 5%, TDIE=35(C, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Max
Units

|IOA|, |IOB|
Output current  adjustable range
Controlled by IREF
0.3
7
mA

|(IOM|
Maximum mismatch between source and sink currents
IOA or  IOB of the same or adjacent drivers

5
%

|ITl|
Output leakage current in tri-state
Vcc = 5.5 V

10
(A

Ro(DC)
DC output impedance, single ended

50

K(

|IOAS|, |IOBS|
Output short circuit current 
Drivers shorted to ground or VCC

11
mA

|IOABS|
Output short circuit current
Drivers shorted together

11
mA

Table 2. Driver DC specifications
VCC=5V ( 5%, TDIE=35(C, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Max
Units

VCM
Minimum input commom mode voltage range
Vcc = 5 V, (VIA and (VIB ( 0.5 V
0.5
4.5
V

VTH
Threshold voltage

30
50
mV

VHYST
Input differential hysteresis
VHYSTH - VHYSTL, H = 1
80
100
mV

RIDIF(DC)
DC receiver differential input impedance

50

K(

RICM(DC)
DC receiver common mode input impedance

50

K(

Table 3. Receiver DC specifications

VCC=5V ( 5%, TDIE=35(C, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Max
Units

DCDIST
Duty cycle distortion
Input freq. = 35 MHz, 50 % duty cycle
47.5
52.5
%

Ro(AC)
AC output impedance, single ended
Freq. = 53 MHz
50

K(

tf
IOA or IOB fall time, 20% to 80 %
25 ( < ZLOAD < 120 (
2
4
ns

tr
IOA or IOB rise time, 20% to 80 %
25 ( < ZLOAD < 120 (
2
4
ns

tDskew
|tPHLA - tPLHB| or |tPHLB - tpLHA|,
Differential skew
Any differential pair1
25 ( < ZLOAD < 120 (

0.2
ns

tCskew
|tpdiff[m] - tpdiff[n]|
Channel to channel skew
Any two signals2
25 ( < ZLOAD < 120 (

0.4
ns

Table 4. Driver AC characteristics

VCC=5V ( 5%, TDIE=35(C, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Max
Units

RiDIF(AC)
AC receiver differential input impedance
Freq. = 53 MHz
50

K(

RICM(AC)
AC receiver common mode input impedance
Freq. = 53 MHz
50

K(

Table 5. Receiver AC characteristics


Parameter
Limit
Driver outputs shorted to ground or VCC
Unlimited time

Output voltage
-0.5 to VCC+0.5 V

Input voltage
-0.5 to VCC+0.5 V

Temperature
60 (C

DC power supply
-0.5 to 7 V

Table 6. Absolute maximum ratings
DRIVER CHARACTERISTICS

Driver output levels
The load seen by the driver depends on the termination scheme chosen. For example, for Figure 3, the DC resistance is the input impedance of the receiver in parallel with the termination of the cable, or Z0 (note that the impedance of the receiver can normally be disregarded, because, in general, it is far higher than Z0). Therefore, the voltage swing of the output pins of the driver will vary in accordance with these terminations, and care must be taken to meet the required hysteresis of the receiver plus the desired noise margin.
The definition of |(IOM| is the following:


Figure 6 shows an example of the maximum mismatch current |(IOM| between source and sink currents (see Figure 2 for definition of IOA and IOB). For this example, we assume the following assumptions: (i) we consider that we have set the source/sink current of the driver to 1 mA, using the IREF input, (ii) that we have the maximum allowed mismatch current of |(IOM|=5%, (iii) that the output sink (IO(SK)) and source (IO(SR)) currents are the same for both outputs and finally (iv) that the terminator resistors are set to 50(. Therefore, we can now find the voltage swing of VOA and VOB. First, let's analyze the case where IOA is sinking current and IOB is sourcing current:


Following the same procedure one can find that, when IOA is sourcing current and IOB is sinking current, (VO =100 mV. However, note that the voltage swing of VOA and VOB is not centered in 2.5 V, because the actual current of the outputs are not the same as the one set (though they respect the proper tolerance). This will reduce the VCM of the receiver, in this example, by almost an insignificant amount. 


Figure 6. Example of maximum mismatch current |(IOM|

Driver short-circuit specification
Figure 7 and Figure 8 show the short circuit tests. Neither current should exceed the specified value in Table 2. Furthermore, even when all drivers in a chip are shorted as shown in these Figures, they should withstand this condition without damage.


Figure 7. Short to ground or VCC test circuit



Figure 8. Short together test circuit
DC and AC output impedances
The required minimum output impedance of 1.2 K( will guarantee that the impedance mismatch for a 120 ( cable will be 5%. So, if one uses a 5% precision resistor for the termination, it will guarantee a maximum impedance mismatch of 10%, that can be acceptable for a specific application.
The Norton equivalent output circuit for each driver output is shown in Figure 9, where RO refers to the output impedance of the driver. Note that the DC or static impedance RO(DC) may differ from the AC or dynamic impedance RO(AC). In any case, it is straight forward to design circuits to measure this impedance based on the performance of the driver output.



Figure 9. Norton equivalent of each driver output

Driver transition times
The fast transitions contain high frequency components that directly affect the EMI radiation created by the cable. The first approach that we pursue to reduce this problem is to have a specific minimum rise and fall times (tR and tF > 2 ns). The second takes advantage of differential signals, which produces single-ended signals that simultaneously fall and rise. The electromagnetic fields will be equal and opposite and will cancel each other, with the consequence reduction in EMI radiation. Therefore, it is important to have both single ended channels with small differential skew. Our specification requires tDSKEW  < 0.2 ns. 
RECEIVER CHARACTERISTICS
Receiver input levels
The receiver input signal is measured differentially (see Figure 10). The input hysteresis voltage of the receiver and the differential output current of the driver must be adjusted taking in consideration the impedance of the cable, line termination and the noise margin that one wants to achieve. There are two types of noise margins that we need to meet: one associated to DC inputs, where the input voltages VIA and VIB (see Figure 3 and Figure 4) are not switching, and another associated with the switching of VIA and VIB. 


Figure 10. Receiver signal levels
For stable DC input, the noise margin is given by VDIFFH - VHYSTH = VHYSTL - VDIFFL. However, when the inputs are switching and crossing the threshold region, the noise margin is given by the VHYST. If, at this exact moment of switching, some noise couples to the inputs of the receiver, and it is capable to invert the inputs by an amount larger than VHYST, the output can glitch. The solution to this engineering problem is not just to increase the current of the driver, because we can then run into other type of problems, like excessive EMI radiation and driver power consumption. In conclusion, one has to carefully evaluate the constrain of the problem and set these parameters accordingly.

Receiver differential and commom mode input impedance
The differential input impedance of the receiver is measure between the input pins of the receiver. Common mode impedance is defined as the impedance between each input IA and IB and the power supply common (see Figure 11).

Figure 11. Receiver differential and common mode input impedance
Receiver common-mode rejection
The receiver is intended to operate with a VCM with minimum range from 0.5 V to 4.5 V. Of course, given the adjusted differential current of the driver and the characteristic impedance of the cable, VCM can actually be smaller. Therefore, we are considering in these specs that for the required VCM the input voltage swing of inputs VIA and VIB of the receiver is smaller than 0.5 V. The common mode voltage is defined as the average of VIA (low, high) and VIB (low, high) measured with respect to the receiver ground potential (see Figure 12):




Figure 12. VCM reference circuit
REFERENCES

IEEE Draft Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), IEEE P1696.3-1995 Standard, Draft 1.05, Feb. 1995.

High Performance CMOS Interfaces for H4CPlus Series Gate Arrays, Application Notes 1521, Motorola Semiconductors, 1994.


1 Skew time measurement are made at the 50% point of the current transition
2 Skew time measurement made at 0 mA differential current.

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E.B., S.Z.	- Preliminary -	page i

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E.B., S.Z.	- Preliminary -	page 5