# Presentation: 143754

## P. E. Dodd, F. W. Sexton, M. R. Shaneyfelt, J. R. Schwank, and D. S. Walsh

Sandia National Laboratories, 
Albuquerque, NM

(505) 844-1447
email: pedodd@sandia.gov

- Sandia National Laboratories,
- Albuquerque, NM
- (505) 844-1447
- email: pedodd@sandia.gov

- This work was supported by the Defense Threat Reduction Agency under DTRA IACRO #01-4051 and Work Unit 03790 and the United States Department of Energy.  Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy under Contract DE-AC04-94AL85000.

**Epi, Thinned, and SOI Substrates: ****Cure-Alls or Just Lesser Evils?**

## Outline

- Motivation
- Epitaxial substrates
- Mitigation of single-event latchup
- Thinned substrates
- Wafer thinning as a means of reducing single-event upset
- Impact of wafer thinning on single-event latchup
- Silicon-on-Insulator (SOI) substrates
- Single-event snapback in SOI
- Anomalous charge collection in SOI devices and ICs
- Conclusions

## Motivation for Studying “Alternative” Substrates

- Continuing desire to use commercial devices in the space radiation environment
- higher performance, lower cost, better availability
- BUT: poor single-event effects performance (and getting worse)
- Techniques for radiation-hardening reduce performance and/or add area

*Is there a way to improve the SEE performance of **fully-fabricated commercial integrated circuits?*
- -and-
*By simply choosing parts with alternative substrates can we assure reduced SEE sensitivity?*

## Outline

- Motivation
- Epitaxial substrates
- Mitigation of single-event latchup
- Thinned substrates
- Wafer thinning as a means of reducing single-event upset
- Impact of wafer thinning on single-event latchup
- Silicon-on-Insulator (SOI) substrates
- Single-event snapback in SOI
- Anomalous charge collection in SOI devices and ICs
- Conclusions

## For a Given Technology, Epi Substrates Improve SEL Thresholds

- These ICs were
- fabricated by
- Motorola in 1992 for evaluation purposes.

**No latchup**
**observed**

- After Dodd,* et al., IEEE Trans. Nucl. Sci.* **48**, 2001.

## The Use of Epitaxial Substrates DoesNot Guarantee Latchup Immunity!

*Most devices fabricated on thin epitaxial substrates don’t exhibit SEL, *
*but the AMD K-5 is a worrisome counterexample.*

- After Johnston, *IEEE Trans. Nucl. Sci.* **43**, p. 505, 1996.

- No clear trend in single-event latchup threshold in various commercial technologies as a function of epitaxial layer thickness.

## Outline

- Motivation
- Epitaxial substrates
- Mitigation of single-event latchup
- Thinned substrates
- Wafer thinning as a means of reducing single-event upset
- Impact of wafer thinning on single-event latchup
- Silicon-on-Insulator (SOI) substrates
- Single-event snapback in SOI
- Anomalous charge collection in SOI devices and ICs
- Conclusions

## Wafer Thinning Improves Tolerance to SEE by Reducing the Charge-Collection Volume

*reducing charge-collection depth*

*Practical limits to wafer thinning will be set by the manufacturability*
*of the wafer thinning process, and the original process depths.*

## Wafer Thinning Does Not Improve SEUThreshold Until Epi Layer is Reached

- Sandia CMOS6
- 0.6-μm Process
- VDD = 4.5 V

*For wafer thicknesses less than 1 **μ**m, gate strikes dominate the*
*SEU response, similar to SOI technologies.*

- For wafers thinned to 0.5 μm, the overall improvement in upset threshold LET is about a factor of two.

***3D Simulations***

## Simulations Indicate Thinned Substrates Give Same Performance as Equivalent Epi Wafer

*These results indicate that the heavily-doped substrate of epitaxial wafers already efficiently truncates charge collection.*

- Modest improvements in SEL threshold result from wafer thinning, but only to the level of an epitaxial wafer with the same epilayer thickness.

## Backside Contacts in Conjunction with Wafer Thinning Greatly Enhance SEL Threshold

- Backside contacts serve to shunt the substrate resistance, similar to the heavily-doped substrate in epitaxial wafers.

*To use backside contacts, it is necessary to limit wafer thinning to prevent well-to-well contact.*

## Outline

- Motivation
- Epitaxial substrates
- Mitigation of single-event latchup
- Thinned substrates
- Wafer thinning as a means of reducing single-event upset
- Impact of wafer thinning on single-event latchup
- Silicon-on-Insulator (SOI) substrates
- Single-event snapback in SOI
- Anomalous charge collection in SOI devices and ICs
- Conclusions

## Silicon-on-Insulator Has GreatlyReduced Charge Collection Volume

- CMOS/Bulk

*Traditional wisdom is that SOI is only sensitive to gate region strikes, **and is immune to classical latchup.*

- In bulk technologies, charge deposited several μm deep can be collected.
- In thin-film SOI, the top silicon layer is typically
- less than 300 nm thick.

## Simulations Predict SOI Upset Thresholds 1-2 Generations Behind Bulk

*3D mixed-level**simulations of*
*fully-scaled**technologies*

## In Practice, Floating Body Effects LimitSEU Hardness of Partially-Depleted SOI

- Following an ion strike electrons are
- swept into the source and drain, but
- holes are confined to the body region.
- The body potential is raised by the
- accumulated holes, forward biasing
- the intrinsic source/body/drain bipolar
- transistor.

*The floating body bipolar effect can lead to amplified charge collection,*
*and in extreme cases leads to single-event snapback, a sustained **high-current condition similar to latchup.*

## Body Ties are Used to Limit Floating Body Effects

*Without body ties, SOI may be as SEU-sensitive as bulk CMOS.*

- cf. Massengill,* et al., IEEE Electron Dev. Lett. ***11**, p. 98, 1990.

## Snapback in SOI Limits Usable Device Width

- After Dodd*, et al., IEEE Trans. Nucl. Sci. ***47**, p. 2165, 2000.

*Snapback can also occur following a heavy ion strike, and behaves*
*similar to a single-event latchup.*

## Body Ties Can Improve Upset Threshold by >2X

- After Hirose*, et al., 2001 NSREC.*

- Mitsubishi
- 128K FDSOI SRAM
- LG = 0.2 μm
- VDD = 1.8 V

- Total Sensitive
- Area = 2 μm2/bit

- Gate
- Area  0.3 μm2/bit

## Broadbeam Heavy Ion Data Indicate Drain Strikes Can Cause Upsets 

- Gate
- Area = 0.64 μm2/bit

- Sandia CMOS7
- 1 Mbit SRAM
- 0.35 μm PDSOI
- VDD = 3V

- After Dodd,* IEEE Trans. Nucl. Sci.* **48**, 2001.

## Broadbeam Heavy Ion Data Indicate Drain Strikes Can Cause Upsets 

- Sandia CMOS7
- 1 Mbit SRAM
- 0.35 μm PDSOI
- VDD = 3V

- Gate + Drain
- Area = 6 μm2/bit

- Gate
- Area = 0.64 μm2/bit

- After Dodd,* IEEE Trans. Nucl. Sci.* **48**, 2001.

## Broadbeam Heavy Ion Data Indicate Drain Strikes Can Cause Upsets 

- Saturation cross section
- = 7-8 μm2/bit

- Sandia CMOS7
- 1 Mbit SRAM
- 0.35 μm PDSOI
- VDD = 3V

- Gate
- Area = 0.64 μm2/bit
- Gate + Drain
- Area = 6 μm2/bit

- After Dodd,* IEEE Trans. Nucl. Sci.* **48**, 2001.

## Microbeam Tests on Sandia 64K SOI SRAMsShow Significant Charge Collection from Drain Strikes

- 64K CMOS7 SOI SRAM
- 20 MeV Carbon Ions

*These data suggest that significant charge transport in or through the buried oxide is occurring.*

- Conventional wisdom is that no significant charge collection occurs
- in drain regions of SOI.

- P+ Drains

- N+ Drains/Sources

## At Low LET, Gate Strikes are theMost Sensitive Strike Location

- 35-MeV Cl ions:
- LET = 16 MeV-cm2/mg

**At Low LET, Gate Strikes are the****Most Sensitive Strike Location**

## At Higher LET, Microbeam SEU ImagesIndicate Drain Strikes Can Cause Upsets

- N-off Gates
- & Drains

- P-off Gates
- & Drains

- 35-MeV Cl ions:
- LET = 16 MeV-cm2/mg

- 50-MeV Cu ions:
- LET = 29 MeV-cm2/mg

**At Higher LET, Microbeam SEU Images****Indicate Drain Strikes Can Cause Upsets**

## Excess Charge Collection Appears to Be Coming From Buried Oxide and/or Substrate

- Carriers generated in bottom silicon may drift to top silicon via a conductive pipe and contribute to collected charge
- Charge could also be collected by other mechanisms, e.g., transport of charge generated in the oxide itself

- Si-Substrate

- Conductive pipe

- e

*Regardless of the mechanism, the anomalous charge collection will increase error rates in SOI ICs.*

## Conclusions

- The use of epitaxial substrates improves SEL sensitivity, but does not guarantee SEL immunity
- Wafer thinning may be useful in some cases
- minimal impact on SEU response, especially for epi technologies
- bigger impact on SEL response, but no better than equivalent epi
- can a manufacturable wafer thinning process be developed?
- Unexpectedly large charge collection from drain regions in SOI ICs
- microbeam and broadbeam data indicate drain strike charge collection can cause SEUs
- possible transport mechanism identified: conductive pipe through SOI buried oxide
- may dramatically increase error rates in SOI ICs

***Final Answer: Not Cure-Alls, Just Lesser Evils! ***