# Presentation: 317621

## Run2B silicon electronics  8/30/01

- Things to discuss
-  Hybrids
-  Cables/Connectors
-  L0 issues
-  SVX padring

## Run2B electronics    

- Run2B electronics

- Hybrid

- AC

- IB

- SVX4
- with side bonds

- differential

- Single ended

- commercial transceiver
- SVX3/SVX2 conversion

- Si sensor

- 60 um readout pitch

- HV

- LV

- SEQ

- jumper cable

- twisted pair cable

- SMT IIB

- Junction card

- Baseline concepts:
- Differential readout from SVX4 to AC
- Same SVX4 padring as CDF
- No long low mass cables : small jumper cable + twisted pair cable
- New AC interfaces SVX4 to D0 DAQ
- L2-L5 : on-board hybrids,  10 chips
- L1      : on-board hybrids,    6 chips
- L0      : analog LM cables, off-board hybrids,  2 or 4 chips
- Hybrids L1-L5 : on-board AVX 50 pin connector
- Jumper cable : AVX – kapton LM cable - AVX
- Junction card : passive, AVX – soldered twisted pair cable

- Aug 30th 2001

## Hybrid and Stave layout

- L2-L5

- Twisted pair cable

- Junction card X-Y view

- L1

- Junction card X-Y view

## Hybrid dimensions

-  chips 12.1 x 6.4 x 0.35 mm
- fingers AlO2  12 x 1 x 0.375 mm
- L2-L5 hybrid : 38.1 x 55 mm
- L1 hybrid :      23.35 x 55 mm
- AVX connector : receptacle and plug  50 contacts
-                               1.6 x 6.4 x 15.6 mm
-                               3mm high when plugged in
-                               0.5 mm for cable connection
- Capacitors
- - Run2A : LV used one 1206 LF, one 0805 MF
- per hybrid, one 0603 per chip, HV used 1812 (CDF)
- will know exactly what needed after SVX4 is ready
- capacitor dimensions
-                      0603 ( 1.6L x 0.8W x 0.9H mm)
-                      1206 ( 3.2L x 1.6W x 1.3H mm)
-                      1812 ( 4.5L x 3.2 W x 1.7H mm)
-                        1812 : 1000 V max 5600 pF

## Digital LM cable

- Number of wires
- 11 differential (D0-D7, DV, PRIOUT, CLK)
- 5 single ended (PRIIN, CHMOD, BEMOD, FEMOD, VCAL)
- 4 power (AVDD, AGND, DVDD, DGND)
- Scaling from D0 Run2A HDI pigtail :
- Total width of the cable : (27x(0.1+0.1)+2(2.5+0.2)+2+0.1 = 12.9  mm (Run2A 9.5 mm)
- Line thickness : 18 um
- Kapton thickness : 50 um, need to be thicker if want match impedance (~300 um?)
- Signals                 Power                      HV
-                         Ground
- Connector  AVX 50 pin : 27 signals + 3 x 4 power + 2 HV =  43 pins needed
- Chose 50 pin, 3 mm high (if fits) AVX connector, backup 2-2.5 mm
- Power  :  0.5 W/chip x 10 chips/ 2.5 V = 2 A (AVDD + DVDD)
- Current is  factor of 2 higher than for Run2A hybrids
- Unknown how splits between AVDD and DVDD
- AVX 0.4 A/pin : allocate 8 pins (=3.2 A for 2 A)
- CDF experience : 1.5 A  through 2 pins (=0.8 A) – no heating or other problems

**Digital LM cable**

## Digital LM cable

**Digital LM cable**

- HV  : AVX nominal 50 V max
- - HV pin at the edge of the connector :
-  remove 2 pins, distance 1.3 mm
- - Should hold ~ 1000 V
- - CDF experience :
-      removed one pin  ~ 0.8 mm gap
-      breakdown at ~ 600 V
-      concluded that ok for 300 V
**Bottom line : safe 300 V operation possible**
**Total cable count :**
**L5   30 x 4 x 2 = 240**
**L4   24 x 4 x 2 = 192**
**L3   18 x 4 x 2 = 144**
**L2   12 x 4 x 2 = 96**
**L1   12 x 6 = 72**
**L0   8 x 12 = 96**
**     ****(or 12x 12 = 144)**
**Total                  840****  (or 888)**

## Digital twisted pair cable

**Digital twisted pair cable**

- Number of pairs
- 10 differential (D0-D7, DV, PRIOUT)
- 5 single ended (PRIIN, CHMOD, BEMOD, FEMOD, VCAL)
- 15 pairs
- 2 thicker twisted pair for power (AVDD, AGND, DVDD, DGND)
- 1 twisted pair for HV
- 2 coax cables for clocks ( or shielded twisted pair ? )
- Still waiting for a quote from Axon for DELPHI like cable (terminated & non terminated) and
-                                           for cable which includes power and HV wiring in the same assembly
- Assume  5 mm OD possible for assembly (signals, power, HV and clocks) cable

## L0 readout

- sensors

- hybrid

- junction card

- Twisted pair cable

- 6 LM analog cables

- 3 (or 6) jumper cables

-  2 chip hybrid or 4 chip hybrid ?
- Deadtime issues :  assuming 20% max occupancy (based on Rich and CDF numbers)
-                              readout takes ~ 1.0 us /chip

- 2 vs. 4 chips comparison :
- ~ 20 % difference in deadtime
- (9.2 vs. 11.2 us)

## HV distribution

- Required HV -  300 V for the L2-L5, 700 V for L0-L1
-         700 V (limited by sensors),  get there after ~ 20 Mrad of dose
-         ~ 20 fb-1 @ 15 mm,  ~ 28 fb-1 @ 20 mm
-         supposed to be considerably better with oxygenated Si
-  HV bias goes to the backplane. Need p-side bias or ground it?
-  One HV cable / HDI. HV is split between upto 4 sensors
-  Need more HV power supplies (have ~ 300 )
-  L2-L5 can go through the same cable as signals
-  L0-L1  up to 1000 V
- - should go to AC bypassing IB
- - 2 HV connectors on the Clock Card ?
- - separate lines in the twisted pair cable
- - m.b. can go through LM jumper cable and AVX to hybrid
- - L0 : goes on the analog LM cable

- Foil ?

## Junction cards

- Dimensions :   30 mm x 80 (?) mm
- Mounted on cylinders
-            R         N     JC width
- L5   160 mm   30     33 mm
- L4   130 mm   24     34 mm
- L3   100 mm   18     35 mm
- L2   75   mm   12     39 mm
- L1   55   mm   12     29 mm
- L1 – L5  should fit
- L0 ?      2 chip hybrids
-              ring at R=45 mm  ⇨ 283 mm/48 = 5.9 mm  (cable OD 5 mm)
-              two rings tightly packed with cables needed for 8-fold pinwheel L0
-              ( three for 12-fold design 144 cables)
- Things are better for 4 chip L0 hybrids (48 and 72 cables)

## SVX4

**SVX4**

- Status
-         - Fermilab design showed better performance over LBL design
- - Optimum noise slope :  450 + 43 /pF  electrons
- SVX4 pad ring
- - Adopted the same padring as CDF – this is the baseline
- - Chip can have second padring where we can use advantages of on-chip bypassing. Potentially improves performance, eliminates some capacitors on hybrid.
- - Need to decide soon, submit D0 proposal this week

## Second padring 

- Second padring

- -  on-chip bypassing works : no QVDD, QGND
- -  no need for ROMODE since we do not use the transceiver chip
- -  VCAL can be stitch-bonded on the side : no need for VCAL on the back
- -  AREF, ABIAS, B2, IQUI are may be not needed. To have a backup we put them deeper in a third row of 4 pads.  To use them if needed we put in the D0 padring 2 pads PAD1, PAD2 close to the above 4 pads. So if needed we can stitch bond two of them to the back end. if more than 2 are needed we are in trouble.
- -  total number of pads in the proposed scheme is 32 instead of 29 as before. so we need to squeeze in 3 other pads. it seems the solution would be to have smaller power pads and 10% smaller pitch (180 um?) for the D0 padring.
- - FECLK, FECLKB have to be aligned with CDF BECLK, BECLKB as before to allow stitch bonding
- - so you may want to move around some pads to achieve this.

- starting from the top of the chip :
- AREF           AVDD
- ABIAS         PAD1
- B2                PAD2
- IQUI            ISLOPE
-                    VTH
-                    FEMOD
-                    BEMOD
-                    CHMODE
-                    FECLK
-                    FECLKB
-                    OBDV
-                    OBDVB
-                    BUS0
-                    BUS0B
-                    BUS1
-                    BUS1B
-                    BUS2
-                    BUS2B
-                    BUS3
-                    BUS3B
-                    BUS4
-                    BUS4B
-                    BUS5
-                    BUS5B
-                    BUS6
-                    BUS6B
-                    BUS7
-                    BUS7B
-                    SGND
-                    DGND
-                    DVDD
-                    SVDD