# Presentation: 521821

## Detectors R&D

- D. Peter Siddonsa
- _P. O’Connor_b
- a National Synchrotron Light Source Dept.
- b Instrumentation Division

## Outline

- Requirements for NSLS-II Detectors
- NSLS Detector Experience
- Emerging Technologies for Sensor/Electronics Integration
- Proposed R&D Plan

## Goals for NSLS-II Detector Development

- A pixel detector with multiple-tau time autocorrelation electronics on each pixel
- Dynamics of systems on the atomic scale.
- NSLS-II’s quasi-DC brightness will make it an optimal source for this experiment.
- Megapixel detector with *on-pixel correlators *can provide sufficient sampling density to access the sub-microsecond domain.
*3D technology* will provide the necessary integration density.
- A pixelated detector with *on-pixel MCA*
- Simultaneous spectroscopy/diffraction detector.
- Energy and spatial resolution.
- X-ray microprobes with microdiffraction and fluorescence analysis on the same sample position with the same detector.

## NSLS Detectors

- A series of detectors for selected SR applications has been developed over the past ~5 years
- Key technologies:
- Silicon pad and strip detectors (Instrumentation)
- CMOS **A**pplication **S**pecific **IC**s (Instrumentation)
- Advanced Data Acquisition hardware and software (NSLS)
- The highly parallel architectures enabled by these technologies lead to significant performance advantages

## Rapid XRF Elemental Mapping(BNL/CSIRO collaboration)

- Hardware: 32-element detector + 2 ASICs + digitizer/processor board.
- Dynamic Analysis real-time deconvolution demonstrated at 108 events/second.
- X-ray elemental images of Fiji pyrite collected at NSLS X27A beamline.
- 800 x 500 pixels of 10um x 10um, collected in 5 hr.
- 20X faster than conventional detector.
- Increase to 400 elements + NSLS-II brightness would give additional ×104 gain.

## Detector for Diffraction Applications

**80 mm**

## Limitations of Wirebonded Interconnection

- NSLS-II detectors will require:
-  larger area (100’s cm2)
-  finer pixels (< 200m)
-  more processing power/pixel (MCA, correlators)
-  mosaic construction

## Monolithic Approaches for Sensor/ASIC Integration

- Common Technology
- sensor in CMOS process (MAPS)
- transistor in sensor process (DEPFET, XAMPS)
- Charge-Shifting
- capture charge in a potential well and physically move it to output port (CCD, CDD)
- Physical Connection
- bump bonding (PbSn, In)
- direct wafer-wafer bonding

## Bump-bonding: Examples 

- Bump-bonding: Examples

**PX detector**
**Swiss Light Source**
**1M, 200********m****2**** pixels**

**large modules possible but:**
**expensive, esp. for fine-pitch**
**many post-fab process steps**
**Pb fluorescence**
**delamination**

**infrared imager**
**(Raytheon)**

## direct wafer-wafer bonding

-  Ultimate goal is monolithic integration of any technology
-  Immediate push in industry is for reducing wireload distribution in digital ICs
-  Science applications being pursued in optical/IR imaging, HEP tracking
-  FNAL and KEK have active HEP designs
-  Processes available at Lincoln Labs, JPL, OKI Semiconductor, IBM

## 3D CMOS/Photodiode Integration 

- 3D CMOS/Photodiode Integration

- 1024 x 1024 imager
- oxide bonded 275°C SOI process
- thinned to 50m
- 8m pixel pitch
- 106 3D vias; yield 99.999%
- 3.8x106 0.35m CMOS FETs
- 2nA/cm2 dark current
- 10 frames/sec
*V. Sunthuralingam, Lincoln Labs (ISSCC2005)*

**bonded 2 wafer imager stack**

## R&D Plan

- FY 07-08
- research the available 3D foundry services and the CAD tools required to access them
- acquire design capability
- 1 foundry run (test vehicle)
- FY 09-13
- further technology experiments as needed
- design of correlator and MCA chips
- other detector hardware (vacuum, cooling, motion control)
- design and production of DAQ hardware
- control, acquisition, and user interface software

## Milestones: FY 07-08

**Milestones**
- _FY07_
- Identify R&D partner with 3D capability.
- Acquire design tools compatible with R&D partner.
- Research correlator designs.
- Research ADC designs.
- _FY08_
- Design a suitable test device to verify 3D capability
- Fabricate test device with R&D partner.

## Application Examples

- Real-time growth / surface modification
* **Beamline X21 in-situ growth endstation*
- Reflectivity / truncation rods / GISAXS
* **Tests at Cornell*
* **System under construction for X9 undulator/CFN*
- Inelastic scattering
* **System under construction for Argonne*
* **Interest from SSRL*

## Test Data: Maltose

- Data on same material collected at X16C using flat crystal setup and at X12A using Guinier camera
- 1 sec/point for crystal instrument, 3274 points
- 50 sec/point for Guinier instrument (get 5X counts)
- So full detector of this design would have 300X speed advantage
- Simple improvements could provide higher intensity for Guinier instrument, easily X3, pushing advantage to 1000X.

## Process flow for 3D Chip