# Presentation: 530802

## The AMSRW Board for the Silicon Vertex Trigger upgrade at CDF

- INPUT STREAM
- Incoming hits are stored in a FIFO, and popped when the sequencer is ready to process them.
- The hits are then sorted into a number of classes according to their coordinate values. These classes are called Super Strips (SS). The mapping between each hit and the corresponding Super Strip is obtained through a 128k x 16 bit lookup table (SSMAP). SS are then sent to the AM++ boards through the P3 connector.
-  The AM++ boards compare the Super Strips on the fly with the associative memory content and signals whenever a stored pattern is matched in the requisite number of layers.
- The enabled AM++ board sends out a list of road addresses and for each road  the corresponding list of matched Super Strips inside the pattern, the “bitmap”.
- OUTPUT STREAM
- Whenever the road number is received, it is used as an address to a lookup memory, the Associative Memory Map (AMMAP), which stores for each layer the superstrip associated with the road.
- Roads and bitmpas are then sent to the Road Warrior which eliminates the redundant tracks (ghost roads).
- The output engine sends out the roads (not discarded by the RW) and also calculates the parity of the output stream and sends the end-of-event word, which contains the Event Number and diagnostic information.

- J.Adelman1, A. Annovi2,3, A. Bardi3, M.Bitossi2,3, R. Carosi3, M.Dell’Orso2,3, P. Giannetti3, P.Giovacchini2,3, J.Lewis4, T.Liu4, M.Piendibene3, M.Pitkanen4, B.Reisert4, M.Shochet1, B. Simoni2,3, F.Spinella3, F.Tang1, S. Torre3,4
- 1Departement of Physics, University of Chicago, Chicago, Illinois 60637, USA
- 2Dipartimento di Fisica, Università di Pisa, 56100 Pisa, Italy
- 3INFN Pisa, 56100 Pisa, Italy
- 4FNAL, PO Box 500, Batavia, Illinois 60510, USA

- The Silicon Vertex Trigger (SVT) processor has been built at CDF for extremely fast (~10 sec) and high precision (roughly offline quality) pattern recognition and it is going to be **upgraded** to have at high luminosity the same crucial role it had in the data collection for the RUN II physics.

- The greatly increased number of stored trajectories provided by the new AM++, the protocol for the new AM chips, and the necessity of increasing processing speed require:
- A new Sequencer for the AM++
- A new Road Warrior: the RW function eliminates redundant track candidates due to the use of majority logic in the pattern matching algorithm (N over M fired layers, N < M).

**Dataflow**

**Road Warrior logic**

- The Road Warrior stores the SS combinations (patterns) of found roads in a small associative memory built on the fly (AMRW) when roads are sent to the output (output engine).  Empty SS’s are identified and flagged using the bitmap.
- Each road is allowed to proceed to the output only if it differs from all roads previously sent in at least one non-empty SS.
- The RW logic includes a 72 bit wide associative memory (AMRW), 64 locations deep, which fits in one FPGA (95% full) of the Pulsar board (DataIO1).
- The output of the AMMAP, after receiving a road and applying the bitmap, is compared in parallel (in a single clock cycle) to all the previously stored roads in the associatice memory (AMRW):
-  If there is a **match**, the newly received road is a duplicate and is discarded.
-  If there is **no match**, the AMMAP output is copied into the next available location in the AMRW, and the road is sent to the output engine
- At the end of the event, the AMRW is cleared.

- The **AMS-RW** card implements and enhances the functions of two boards installed in the current SVT:
-  the **Associative Memory Sequencer (AMS)**: the operating controller for the AM++ associative memory boards.
- the **Road Warrior** **(RW): **The RW function eliminates redundant track candidates (ghost roads) as soon as possible to improve the SVT processing time.

**New AMSRW board**

**AMSRW logic dataflow**

**Stand alone test stand for first board validation**

**Test for validation (Pisa)**
- The AM++ is filled with random patterns.
- Random hits are generated and sent to the AMS-RW through the Merger (an SVT board with specific capabilities to inject high frequency inputs in SVT test stands, and to read back the SVT outputs)
- The datflow is simulated to calculates the expected roads.
- We read back (by VME) the found roads stored inside the Merger.
- Finally we compare these roads with the expected ones.
- This procedure validates both the boards and their simulation.

- The Pulsar board, programmed as AMS-RW,  has been deeply tested together with the AM++ boards.

- The system is controlled by several state machines. The main FSM is inside the control FPGA

- The main FSM

**Why a new board?**

- To perform this task we use a Pulsar board (a general-purpose 9U VME interface board for HEP applications developed by a group of physicist and engineers at the University of Chicago), which is highly reconfigurable and complies with CDF and SVT standards. We implement both the AMS and RW functions in a single pulsar board.
- Two custom mezzanine boards are plugged into the Pulsar to satisfy the memory needs (SSMAP and AMMAP) of the AMS-RW algorithms.
- The Pulsar combines the power of dedicated hardware with the flexibility of general purpose CPUs.
- We could have a working board in less than 1 year because the hardware was ready since the beginning and our work was mainly devoted to firmware development and validation.

**Mezzanine cards**

- Logic analyzer waveform example

**Installation in the SVT crate**

- The AMS-RW board is equipped with a slave VME interface, which permits the data exchanging with the crate CPU.

- The working frequency, suitable for the CDF needs, has been fixed to **40 MHz**. The same clock signal, generated by the AMS-RW board is also distributed through the backplane to the AM++ boards

- The new implementation is able to handle a much larger associative memory system and the integrated Road Warrior functionality allows eliminating the duplicate tracks early in the SVT pipeline, reducing the SVT processing time.

- The new AMSRW board in the SVT crate (Fermilab)

- The Pulsar board, programmed as AMS-RW,  has then been deeply tested spying real data in CDF and finally installed to be part of the SVT system in the Summer 2005.  Thanks to the previously made intensive tests the substitution of the old AMS and RW boards with the new AMS-RW has been extremely smooth. Up to now the system is running without any known problem.

- The firmware is distributed in the 3 FPGAs: the Road Warrior section is located in the FPGA named DataIO1, while the AMS fits in the other two.

- Implementation of the AMSRW inside the Pulsar board

- The board, like all devices in SVT, is equipped with two Spy Buffers: The Input Spy (INSPY) and the Output Spy (OUTSPY).These are circular memories, which continuously spy the data flowing into the Input Connector  (Hits) and going out of the output connector (Roads).
- If an error comes out, the Spy Buffers are automatically “freezed” by a dedicated board of the SVT crate (Spy Control) and then accessed through the VME interface to read the content. In this way many typologies of problems (such as a damaged cable) can be easily identified.

- The output stream for a particular event can be interrupted in two different cases:
- Truncated output (TO): to reduce the probability of very large processing time fluctuations, due to very crowded events.
- Not interesting event (KILL18): the event belongs to a class (identified by trigger logic before SVT) that should not be analyzed by SVT.

- Match algorithm details

- We have debugged the signals of the AMSRW firmware with the help of a logic analyzer (attached to dedicated pins on the Pulsar).