# Presentation: 218532

## Ferroelectric Memory Reliability and Qualification

- Gary F. Derbenwick and Stephen C. Philpy
- Celis Semiconductor Corporation
- Colorado Springs, Colorado 80918
- (719) 262-5144
- gary@celis-semi.com

- 2001 MRQW
- Dec. 11-12, 2001
- Pasadena, CA

## Ferroelectric Memory Storage

## Ferroelectric Memory Reliability and Qualification

- Different:
- Ferroelectric Materials
- Ferroelectric Memory Architectures
- Ferroelectric Processes
-  *All of the above affect reliability and qualification*

## Different Ferroelectric Materials

- PZT *(lead zirconium titanate)*
- Sputtered with Pt, IrOx or LSCO electrodes
- Undoped or doped (La, Ca)
- Affects high T retention, imprint and endurance
- SBT *(strontium bismuth tantalate)*
- Spin-on with Pt electrodes
- Undoped or doped (niobium)
- Affects high T retention, imprint and endurance

## Different Ferroelectric Memory Architectures

- 1T/1C
- Fatigue of sense amplifier reference cell limits retention and endurance
- 2T/2C
- True and complement bit lines avoid sense amplifier reference cell issue at expense of larger cell
- 1T
- Retention issue due to depolarization

## 2T / 2C Ferroelectric Memory Cell Design Schematic

## 2T/2C SEM Cross SectionOffset Memory Cell (Hynix)

## Different Ferroelectric Processes

- Ferroelectric Deposition
- Spin-on (or LSMCD)
- Sputtering
- MOCVD
- Metalization
- 1LM, 2LM or 3LM (w/wo W plugs)
- Ti-N local interconnect
- Passivation
- Oxide or Nitride

## Ferroelectric Reliability and Qualification

- Dependent on manufacturer
- Review status for 3 manufacturers
- Fujitsu (Ramtron foundry)
- Hynix
- Matsushita

## Rohm Co., Ltd.

- Early production for Ramtron
- PZT
- 2T/2C
- 1T (PZT w/floating gate)

## 1T Ferroelectric Memory Cell

- Rohm
- ISSCC 1995
- Retention issues
- Celis/COVA
- NIST ATP grant 2001
- New classes of ferroelectric materials
- Goal: prototype memory within 3 years with 6F2 1T memory cell (no floating gate)

## Ferroelectric ManufacturersFujitsu Fabrication Process

- Sputtered doped PZT
- Pt bottom, IrOx top electrodes
- 2LM (CMP and W plugs)
- W silicided gates
- Nitride passivation
- 2T/2C offset memory cell

## Fujitsu Roadmap(mid-year milestones)

- 1999
- 1LM 0.5 m 2T/2C 5V, 6-inch
- 2000
- 2LM
- 2001
- 3LM 0.35 m 2T/2C 3V
- 2002
- 1T/1C
- 2003
- 5LM, 0.18 m, 8-inch

## Fujitsu Ferroelectric PropertiesPZT

- Switched Charge	31 C/cm2
- Endurance
- Functionality		> 1012
- 10 yr retention		> 107
- Imprint			0.5 - 2 %
- Retention			10 yr (85 oC)
- Operating Range	-40 to 85 oC

## Fujitsu Products

- Cumulative shipments – 28M die at Feb 01
- 64K *(Ramtron)*
- Parallel and serial I/O
- 256K *(Ramtron)*
- 3V 50ns
- 1M Embedded FeRAM Macro *(Fujitsu)*
- ID card
- Cable TV secure processor (32K)
- Games (64K)

## Fujitsu Ferroelectric QualificationStandard Tests, 0.5 m

- HTS              150oC, 2016 hrs,   92 samples
- HTOL    6V, 125oC, 2016 hrs, 108
- THB       6V,   85oC, 2016 hrs,   46
- LTOL  5.5V,  -65oC, 1008 hrs,   11
- HAST  5.5V, 121oC,     72 hrs,   26
- PTHS  100%, 121oC,  504 hrs,   75
-    *No failures*

## Fujitsu Ferroelectric QualificationStandard Tests, 0.35 m

- Same tests as for 0.5 m
- Completion in Feb 2002
- Over 1000 hrs to date
-    *No failures so far*

## Fujitsu Sample Retention Screen

- 10 hour, 150 oC bake, or
- 4 hour, 200 oC bake
-  *Lot scrapped if more than 0.5% fail*

## Fujitsu Yield

- 82 - 93% for 64K and 256K FeRAMs
- Pt flakes
- IrOx sputter particles
-  0.7 defects/cm2
*(Logic product typical defects 0.4/cm**2**)*

## Ferroelectric ManufacturersHynix Fabrication Process

- Spin-on SBT
- Pt electrodes
- 2 level metal
- Ti-N local interconnect
- Nitride passivation
- 2T/2C offset memory cell

## Hynix Roadmap

- 1998
- 2LM, 0.8 m, 2T/2C offset cell
- R&D fab
- 2001 - 2002
- Installation in production fab (Ichon)
- 3LM, 0.35 m, 1T/1C offset cell
- After 2002?
- > 64M FeRAMs

## Hynix Ferroelectric PropertiesSBT

- Switched Charge	~ 15 C/cm2
- Endurance		> 1012
- Imprint			< 1 %
- Retention			10 yr (150 oC)
- Operating range		0 to 70 oC

## Hynix Products

- 64K FeRAM
- Standard JEDEC pin-out
- TTL I/O
- 5 V
- RFID Tag

## Hynix 64K FeRAM

## Hynix Retention

## Hynix Retention  (150 oC)

## Hynix Endurance

## Ferroelectric ManufacturersMatsushita Fabrication Process

- Spin-on SBTN
- Pt electrodes
- 1 level metal
- Nitride passivation
- 2T/2C offset memory cell

## Matsushita Roadmap

- 1996
- 1LM, 0.8 m, 2T/2C offset cell, R&D
- 1998
- Production at Uozu
- 1K RFID tag
- 1999
- 0.18 m, R&D at Kyoto
- 2001
- 2LM

## Matsushita Ferroelectric PropertiesSBT

- Switched Charge	8 C/cm2
- Endurance		> 108
- Imprint			< 1 %
- Retention			10 yr (70 oC)
- Operating Range	-20 to 85 oC

## Celis/Matsushita 1K RFID Tag

## Matsushita Ferroelectric QualificationStandard Tests

- HTS
- HTOL
- THB
- Thermal Shock
* **Only 1 failure in all tests @ 1000 hrs*

## Matsushita Ferroelectric Yield

## Matsushita Ferroelectric Yield

- ~ 99.3% for 1K RFID Tag
- Retention fails
-  0.23 defects/cm2
*(Logic product typical defects 0.4/cm**2**)*

## Matsushita FIT Failure Rate

## Matsushita Ferroelectric Failure Rates1K RFID Tag

- < 1 FIT @ 27 oC
- 2.5x better than EEPROM @ 27 oC

## Radiation Hardness of Ferroelectric Memory

- Ferroelectric device inherently radiation tolerant
- Limited by CMOS hardness
- Previous measurements show good ferroelectric radiation tolerance:
- Total ionizing dose
- Neutron irradiation
- Proton irradiation
- SEU events

## CONCLUSIONS

- Two commercial ferroelectric manufacturers
- Fujitsu and Matsushita, Hynix not far behind
- Yields are excellent
- Reliability levels are excellent
- More aggressive design rule sets, memory cells and metalization planned for the future
- With hardened CMOS, excellent radiation hardness