# Presentation: 076299

## Readout for the PIXEL detector for the Heavy Flavor Tracker upgrade at STAR

- Leo Greiner IPHC DAQ 2007-10

**Notes:**
Hi, I’m going to talk about the development that we are doing for the STAR vertex detector

## Talk Structure

- Review of Sensor development and coupled RDO development
- System design
- Detailed system structure
- Data Rates
- Ultimate sensor system discussion

- Leo Greiner IPHC DAQ 2007-10

**Notes:**
I’m going to break the talk down into a few slides each on the following topics...

## IPHC Functional Sensor Development

_**Data Processing in RDO and on chip by generation of sensor.**_

- The RDO system design evolves with the sensor generation.

- 30 x 30 μm pixels
- CMOS technology
- Full Reticule = 640 x 640 pixel array

- _Mimostar 2_ => full functionality 1/25 reticule, 1.7 ms integration time (1 frame@50 MHz clk), analog output. *(in hand and tested)*

- _All sensor families:_

- _Phase-1_ and _Ultimate_ sensors => digital output *(in development)*

- Leo Greiner IPHC DAQ 2007-10

**Notes:**
We are following a sensor development programme in collaboration with our colleagues at Strasbourg. There are two series of sensor that we follow with our mechanical and readout development. The first series is the mimostar series which we plan to use to produce a full prototype detector with analog readout. The characteristics are as shown... The ultimate series is the what we intend to use in the final detector. It has mostly the same pixel and physical characteristics as the mimostar series but with much more processing on chip such as on chip CSD, a much shorter 200 us integration time. Programmable dual discriminators and digital output via LVDS

## System Design – PIXEL Structure

_**Current Conceptual Design**_
- ALICE Style Structure – carbon
- fiber box beam
- 10 sensors / ladder
- 4 ladders / carrier unit
- 10 carrier units in the detector
- -1 < eta < 1
- Inner radius ~ 2.5 cm
- Outer radius ~ 8.0 cm

- Leo Greiner IPHC DAQ 2007-10

## System Design – System Blocks

- This is a  highly parallel system – a schematic representation is shown below.

- Leo Greiner IPHC DAQ 2007-10

## System Design – Physical Layout

- 1 m –
- Low mass twisted pair

- 3 m - twisted pair

- _System Design – Physical Layout_

- Magnet Pole Face
- (Low Rad Area)

- DAQ Room

- Power
- Supplies

- Platform

- 30 m

- 100 m - Fiber optic cables

- Leo Greiner IPHC DAQ 2007-10

## Detailed System Structure – Sensors and Cables

- Early prototype cable with 40 differential pair
- output, clock and control routed under sensor
- area.

- 4 LVDS outputs / sensor
- _Cable_
- 4 layer - 150 micron thickness
- Aluminum Conductor
- Radiation Length ~ 0.1 %
- 40 LVDS pair signal traces
- Clock, JTAG, sync, marker

- Fine twisted pair cables
- 125 micron diameter wire
- Soldered directly to cable
- Low stiffness / mass

- Leo Greiner IPHC DAQ 2007-10

## Detailed System Structure – LU Protection and Mass Termination

- 1 Main Board
- per carrier
- 10 carriers in
- the PIXEL
- detector

- Leo Greiner IPHC DAQ 2007-10

## Detailed System Structure – RDO Board(s)

- New motherboard

- Two board System – Virtex-5 Development board mated to a new HFT motherboard

- Xilinx Virtex-5 Development Board

- Digital I/O LVDS Drivers
- 4 X >80 MHz ADCs
- PMC connectors for SIU
- Cypress USB chipset
- SODIMM Memory slot
- Serial interface
- Trigger / Control input

- FF1760 Package
- 800 – 1200 I/O pins
- 4.6 – 10.4 Mb block RAM
- 550 MHz internal clock

- Note – This board is designed
- for development and testing.
- Not all features will be loaded
- for production.

- Leo Greiner IPHC DAQ 2007-10

## Detailed System Structure – RDO Functional Data Path – Phase 1

- Leo Greiner IPHC DAQ 2007-10

## Detailed System Structure – RDO Function Data Path – Ultimate

- Assumptions –
- Data sparsification with rolling shutter architecture. Output from sensor is a series of addresses – BUT – processing / readout time varies with event occupancy.
- Addition of a trigger input and a frame marker flag that strobes one frame after receipt of a trigger input. But this needs to be pipelined as well. Other simpler methods are also possible.

- Leo Greiner IPHC DAQ 2007-10

## Detailed System Structure – RDO Functional Data Path – Ultimate

- Leo Greiner IPHC DAQ 2007-10

## Detailed System Structure – System Level Functioning

- Leo Greiner IPHC DAQ 2007-10

## Data Rates - Parameters

- Rates as per Jim Thomas, L = 3 x 1027 for Phase-1, L = 8 x 1027 for Ultimate.
- 2.5 hits / cluster.
- 1 kHz average event rate.
- 10 inner ladders, 30 outer ladders.
- Factor of 1.6 for event format overhead (can be lowered).
- No run length encoding.

| 61.5 | 6.0 |
| --- | --- |
| 157.0 | 15.0 |

- _R = 2.5_

- _R = 8.0_

- _200 us_

- _640 us_

**Hits / Sensor at L = 8 x 10****27****.**

**Integration**
**Time**

**Radius**

- Leo Greiner IPHC DAQ 2007-10

## Data Rates

- Ultimate  => 49.7 MB / s raw addresses.
- 			  => **79.5 MB / s data rate**.
- Phase–1 => 59.6 MB / s raw addresses
- 			  => **95.4 MB / s data rate.**

- The dead-time is primarily limited by the number of externally allocated readout buffers!

- Leo Greiner IPHC DAQ 2007-10

## Data Rates – Dead time and Latencies

- Average Ultimate inner sensor event size is 3.1 kb.
- RDO at 160MHz on 1 LVDS link / sensor takes 19.4 us (< 200 us integration time)
- What is the latency for data sparsification?
- If the system were dead during the integration time (after trigger) and one serial RDO time we would be 21.9% dead at 1 kHz.
- Look for ways to improve, earlier method is just one.

- Leo Greiner IPHC DAQ 2007-10

## Ultimate Sensor System Discussion

- The design of the Ultimate _SYSTEM_ should be an integrated design with the sensor and RDO designed to complement each other's capabilities.
- Question – is it advantageous to use the processing capabilities inherent in an FPGA based RDO system to offload some of the functionality of the sensor? Would this help the overall system design?

- Leo Greiner IPHC DAQ 2007-10

- fin

- Leo Greiner IPHC DAQ 2007-10