# Presentation: 558912

## PHENIX Barrel Vertex Tracker (VTX)Front End Electronics for the Strip Layers

- Vince Cianciolo, Oak Ridge National Lab
- Project Readiness Review 01/19/2005

## Outline

- System Overview
- Readout Cards (ROCs)
- Front End Modules (FEMs)
- Some Details
- SVX4
- ROC Control Chip (RCC)
- Space/Trace Analysis
- Thickness Considerations
- Bandwidth Considerations
- Current R&D Status
- Cost & Schedule Determination

- V. Cianciolo, Si Strip FEE

## Readout Cards (ROCs)

- Each 3x6cm sensor has 1536 channels, 1 ROC.
- Implemented as a small aluminum/kapton flex cable.
- Each requires 12 SVX4 chips and 1 ROC Control Chip (RCC, details later).

- V. Cianciolo, Si Strip FEE

## Ladders

- Signal traces and power layers (already inherent in ROC) connected at ROC edges to form one signal and power bus per ladder w/o extra material.
- 5 or 6 ROCs per ladder forms one detector azimuthal segment.

- V. Cianciolo, Si Strip FEE

## Front End Modules

- RCCs drive/receive LVDS signals across a bus out of the active area (few meters) to a rack of Front End Modules (FEMs).
- FEMs are the interface to the PHENIX DAQ:
- Clock and Fast Control.
- Data Collection Modules.
- Slow Controls.

- V. Cianciolo, Si Strip FEE

## A Different System View

- V. Cianciolo, Si Strip FEE

## Some Numbers

| Strip Layers | Layer 3 | Layer 4 | Sum |
| --- | --- | --- | --- |
| Ladders | 18 | 26 | 44 |
| Sensors/Ladder | 5 | 6 |  |
| Sensors, ROCs, RCCs | 90 | 156 | 246 |
| SVX4s | 1,080 | 1,872 | 2,952 |
| Channels | 138,240 | 239,616 | 377,856 |

- V. Cianciolo, Si Strip FEE

## SVX4

- 128 channel chip.
- 5000 tested chips being purchased by RIKEN from FNAL.
- 0.25 μm TSMC process (inherently rad hard).
- Compatible with PHENIX DAQ:
- Sufficient L1 latency (w/ analog pipeline).
- Multi-event buffering (4 events).
- Simultaneous digitization/readout and acquisition.
- 106 ns RHIC clock sufficiently close to 132 ns Tevatron clock.
- Designed for Cdetector = 10-35pF:
- Noise 0.22-0.25 fC
- S/N 15-17 for 625μm sensors
- Power consumption ~ 3mW/channel.

- Designed for AC-coupled sensors:
- Strip-pixel sensors are DC-coupled.
- Dark current considerations strongly suggest using RC-chips (Hamamatsu) to provide AC coupling.
- Provide selectable on-chip 0-suppression w/ robust common-mode noise rejection:
- Double correlated sampling (store difference between samples separated by 3⁄4 of a clock cycle).
- Write-amplifier pedestal subtraction.
- Dynamical pedestal subtraction (if there’s an offset present on  a majority of channels due to common mode noise, this can be subtracted before 0-suppression).
- Latch-up probability greatly reduced (requires 200 mA) due to SVX4 epitaxial layer/low-resistance substrate fabrication process.

- V. Cianciolo, Si Strip FEE

## ROC Control Chips (RCCs)

- RCC functionality:
- State machine to direct serial control and data transfer.
- Dual FIFO to allow simultaneous conversion (digitization + SVX4 readout) and data transfer to FEM, each in < 40 μsec.
- Reduces # clock lines on bus.
- Isolates effects of single-point failures.
- Simplicity allows full FPGA prototyping, postponement of technology decision.
- ASIC vs. FPGA choice driven by:
- Radiation tolerance.
- Size, thickness.

- V. Cianciolo, Si Strip FEE

## Is There Room?

- Vertical Trace Layer

- Horizontal Trace Layer

- ROC trace count almost entirely accounted for in connections from the RCC to/from the ladder bus and the SVX4s.
- This number is reasonably well fixed by the SVX4.
- Figures to the right show a sketch of a possible trace layout to scale (100μm space/trace) showing that two trace layers is likely sufficient.
- Sufficient space also exists for edge connections.

- V. Cianciolo, Si Strip FEE

## How Thick Is It?

- Assumed bus structure shown at right.
- ATLAS-style (conductor/polyimide) ROC much thinner than CDF-style (BeO).
- Crucial for PHENIX because ROCs cover entire area of strip layers.
- Material summary shown below.
- Reductions from proposal:
- Eliminate substrate (small cards self-supporting).
- Cu  Al (hope to capitalize on pixel-layer R&D).

| Component | Material | X0 (mm) | Length (mm) |  | Width (mm) | Scale Factor | Height (um) | Qty | %X0 |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Ground/Power planes | Al | 89 | 60 |  | 30 | 1 | 20.0 | 2 | 0.045 |
| Capacitors, resistors, epoxy, wire-bond encapsulation | Estimate based on CDF hybrid |  |  |  |  |  |  |  | 0.147 |
| SVX4 | Silicon | 93.6 | 9.11 |  | 6.4 | 1 | 300.0 | 12 | 0.125 |
| Throughhole plating | Al | 89 | 60 |  | 30 | 0.6 | 13.0 | 2 | 0.018 |
| Trace planes | Al | 89 | 60 |  | 30 | 0.4 | 12.0 | 2 | 0.011 |
| Polyimide |  | 357.5 | 60 |  | 30 | 1 | 22.0 | 4 | 0.025 |
| Adhesive |  | 357.5 | 60 |  | 30 | 1 | 20.8 | 3 | 0.017 |
| RCC | Silicon | 93.6 | 7 |  | 7 | 1 | 300.0 | 1 | 0.009 |
| Gold flash | Gold | 3.35 | 60 |  | 30 | 0.5 | 0.4 | 1 | 0.006 |
| Nickel plating | Nickel | 14.7 | 60 |  | 30 | 0.5 | 2.0 | 1 | 0.007 |
| Photoresist |  | 357.5 | 60 |  | 30 | 0.5 | 20.0 | 1 | 0.003 |
| Total |   |   |   |   |  |   |   |   | 0.411 |

- V. Cianciolo, Si Strip FEE

## Front End Modules (FEMs)

- FEM serves as interface between RCC and the PHENIX DAQ (GTM, DCM, Serial Control).
- Functionally similar to PHENIX FEMs developed at ORNL.
- Different physical interfaces.
- Testbench designed to incorporate much of the required FPGA code but with USB/PC interface.

- RCC

- FEM

- FPGA

- V. Cianciolo, Si Strip FEE

## Data Format

- Data format not important at this point except as a demonstration that testbench development should be directly portable to the FEMs.

| Data Sent by RCC to FEM |  |  |  |
| --- | --- | --- | --- |
| Word Type | Bits 15-8 | Bits 7-0 | Note |
| 0 | 1000, 4-bit RCC Address | 0 | Once per ROC |
| 1 | BCLK 15-8 | BCLK 7-0 | Once per ROC (value sampled on receipt of LVL1) |
| 2 | 1001, 4-bit SVX4 Address | L1 Sample | Once per SVX4 |
| 3 | 0, 7-bit Channel Address | ADC | Potentially multiple values per SVX4 |
| 4 | FF | FF | If this is missing there is a conversion error: |
|  |  |  | a) PRI_OUT is high when ENDDAT_FEM arrives,  |
|  |  |  | b) Data exceeds RCC FIFO depth. |

| Data Sent by FEM to DCM |  |  |
| --- | --- | --- |
| Word Type | Bits 16-0 | Note |
| 0 | FFFF | DCM-required header word |
| 1 | Strip Barrel ID | Fixed # unique to strips. |
| 2 | Event # |  |
| 3 | Module ID | A unique # for each ladder |
| 4 | Flag Word | 0-suppression on/off |
| 5 | FEM BCLK Value |  |
| 6 -- 9 | Data | Copies of RCC/FEM word types 0-3 (drop empty SVX4, RCC addresses) |
| 10 | Error Word | Bit 15: 5th Level-1, Bits 13-8 RCC/FEM BCLK match (1 bit per RCC),       Bit 7: Data Transmission incomplete, Bits 5:0 Conversion Errors |
| 11 | FEM Serial # | Hard-coded on FEM Boards |
| 12 | FEM Firmware Version # | Encoded in FEM FPGAs |
| 13 | Parity Word | Bit-wise XOR of word types 1-12 |
| 14 | 0 | DCM-required trailer word |

- V. Cianciolo, Si Strip FEE

## Current R&D Status

- ROC implemented as four “hybrid boards” plus one “RCC board”.
- Large form factor allows for easier probing and debugging.
- Boards fabbed.
- Firmware and control GUI far along:
- Correct signal pattern for serial control, digitization, readout seen at hybrid header (as determined by previous work w/ CDF hybrid).
- Goal is to complete debugging and start testing with sensors in March.

- V. Cianciolo, Si Strip FEE

## Budget Estimation Procedure

- Different components broken out into four categories.
- R&D
- Design
- Prototype
- Fab
- Further subdivided to give WBS elements which are defined by:
- WBS dictionary page
- Systematic contingency calculation
- Cost sheet

- V. Cianciolo, Si Strip FEE

## Strip ROC Budget

- V. Cianciolo, Si Strip FEE

## Strip FEM Budget

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## Key Budget Assumptions

- Prototyping rounds:
- ROC: four (including two at nominal size, thickness).
- FEM: two (doesn’t take credit for testbench control card development).
- RCC: one (as an ASIC, after thorough debugging as an FPGA).
- Spares:
- Require 10% *working* spares.
- Assume 80% ROC yield, 90% FEM yield.
- Estimate total 3000 engineering hours.
- Physicist hours not included in project costs.
- All institutional overheads included.

- V. Cianciolo, Si Strip FEE

## Sample Dictionary Page

- V. Cianciolo, Si Strip FEE

## Contingency Calculation

| Technical, cost, and schedule risk weights |  |  |  |
| --- | --- | --- | --- |
| Technical | Cost | Schedule | Risk weight |
|  | Material cost OR labor rate | Same for all | 1 |
| Design OR manufacturing | Material cost AND labor rate |  | 2 |
| Design AND manufacturing |  |  | 4 |

| Technical, cost, and schedule risk factors |  |  |  |
| --- | --- | --- | --- |
| Technical | Cost | Schedule | Risk factor |
| Existing design and off-the-shelf hardware | Off-the-shelf or catalog item |  | 1% |
| Minor modifications to an existing design  | Vendor quote from established drawings | No schedule impact on any other item | 2% |
| Extensive modifications to an existing design | Vendor quote with some design sketches |  | 3% |
| New design, nothing exotic | In-house estimate based on previous similar experience | Delays completion of non-critical path subsystem item | 4% |
| New design, different from established designs or existing technology | In-house estimate for item with minimal experience but related to existing capabilities |  | 6% |
| New design, requires some R&D but does not advance the state-of-the-art | In-house estimate for item with minimal experience and minimal in-house capability | Delays completion of critical path subsystem item | 8% |
| New design, development of new technology which advances state-of-the-art | Top-down estimate from analogous programs |  | 10% |
| New design, way beyond the current state-of-the-art | Engineering judgment |  | 15% |

- Each item in the WBS is assigned three risk factors (F) and three risk weights (W).
- State of design
- Basis of cost estimate
- Schedule criticality
- C = FiWi, where repeated indices imply summation.

- C = 4x6%

- + 2x15%

- + 1x8% = 62%

- V. Cianciolo, Si Strip FEE

## Sample Cost Sheet

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## Strip ROC

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## Si Strip FEE Team

- ORNL
- Physics:
- VC (Subsystem Manager), K. Read, D. Silvermyr, C. Zhang,        S. Batsouli.
- Experience with PHENIX FEE, DAQ and testbench development (MuID, Pad Chamber) and with project management.
- EE:
- M. Bobrek (Lead Engineer), K. Castleberry, B. Bryan, U. Jagadish, C. Britton.
- Both digital and analog expertise.
- Specific experience with many PHENIX subsystems.
- ISU
- Physics
- C. Ogilvie, J. Lajoie, postdocs TBD.
- Experience with PHENIX L1 trigger.
- EE
- G. Sleege
- Experience with PHENIX L1 trigger.

- V. Cianciolo, Si Strip FEE