# Presentation: 378902

## D0 Trigger Status

- 128 terms

- 128 terms

- 50 Hz

- L2
- 100s

- L1
- 4.2 s

- Framework

**7 MHz input rate                                  Data**

- Data Log

- 7 kHz

- 1000 Hz

-    L3
- 48+ms

- 48 nodes

**Brief discussion of each project**
**Great progress all systems**
**Significant delays**
**Manpower Shortages**
**Technical Difficulties**
**Delivery**

## Framework Status

_**Components**_**(MSU)**
**Operational**
_**Commissioning/Schedule**_
**Support detector commissioning **
**Complete readout to L3 by 1/11**
**Integrating with L2**
**L2 trigger mask and pseudo-terms deferred?**
_**Firmware**_
**Need to complete pseudo-terms**
**Commission run-control**
_**Personnel**_
**Loss of senior engineer, Steve Gross**
**Loss of engineer, Kirsten Moore**
**Replacement uncertain**

- Good progress, on time

## Detector/L1/L2 Components

- L2FW:Combined
- objects  (e, , j)

- L1FW: towers, tracks, correlations

- L2STT

- Global
-    L2

- L2CFT

- L2PS

- L2Cal

- L1
- CTP

- L2
- Muon

- L1
- Muon

- L1FPD

- CAL

- FPS

- CFT/
- CPS

- SMT

- Muon

- FPD

- L1
- FPS

- L1
- LUM

- LUM

## Luminosity Monitor Status

_**Components(Brown)**_
**Scintillator(48) Complete**
**Electronics **
**CAFÉ boards(175) on hand**
**Completing ADC(~12) board layout, ordering parts**
**Vertex board, FPGA 75% complete, layout commencing.**
**Procuring signal cables(~60) soon**
**Crate/PS on hand**** **
_**Commissioning/Schedule**_
**Installed Scintillator 4/00**
**Cabling awaits FPS.**
**February 1, Electronics Installed**
**March 1, Luminosity Monitoring**
**March-April, and/or terms.**
_**Software**_
**Working on embedded software **
**Download currently underway.**
**Database under development**

- Good progress, on time

## L1CTP/FPS/FPD

## L1 CTP/FPS/FPD Status

_**Components**_
**Analog(Fermilab-D0)**
**AFE-8MCM (CFTax): At vendor, full order complete 1/18/00**
**AFE-12MCM (FPS):**
**motherboard prototype this month **
**daughter prototype board order 1/01**
**Crates/Cables on hand**
**Power supplies delayed until new year (partial).**
**Mixer(Fermilab-CD)**
**Super-sector (1/5th) 11/15**
**Full Mixer 1/01**
**Digital(Fermilab-D0)**
**Motherboard here**
**Transition module 1/11**
**CTP daughter boards 11/15 **
**FPS daughter board order out, parts on order**
**Crates/Cables/PS here**
_**Firmware**_
**AFE & Mixer complete**
**DFE 50%**
**Collector/Broadcaster 50%**
**No diagnostics**

## L1 CTP/FPS/FPD Status

_**Commissioning/Schedule**_
**Assembling test stands for digital/VHDL**
**Installing cables/crates on platform**
**Crates/Cables installed in MCH.**
**Analog**
**10 AFE8 installed, operating 12/00**
**Balance at FNAL by 1/18/01**
**AFE12 unknown (in prototype)**
**Supplies as arrive**
**Digital**
**Sufficient hardware for commissioning**
**Balance Installed by 12/00**
_**Personnel**_
**Recently lost Kin Yip (FNAL postdoc) & Juan Lizarazo (FNAL Co-op) both on VHDL**
**A position has been available but not yet filled & a new student arrived.**
**Reduced engineering (John Anderson) has delayed AFE12.**
**Have redirected Jamieson Olsen to assist with VHDL, Fermilab arranging technical help to assist reorganization and installation.**

- Good progress on all fronts
- AFE12, VHDL concerns

## L1 CAL Status

_**Components**_
**Analog pick-offs (320) to accommodate changed BW prototyped. 1FTE month to production**
**Quadrant hardware (40) circuit/firmware designed**
**L2/L3 Readout complete **
_**Commissioning/Schedule**_
**Inactive until framework complete 11/00. Within a month progress should resume**
**Start w/ analog pick-offs**
**L2 & L3 readout 11/00**
_**Firmware**_
**All exists, not all tested**
_**Personnel**_
**Same as framework**

- Late but well before 3/01

## L1 MUON Status

_**Components**_
**L1MuTrigger (4 crates) Prod Beginning(UAz)**
**Motherboard: starting production/fabrication**
**Scintillator daughter board: preproduction in assembly**
**Wire daughter board: production board in design **
**Crate Manager: testing production card, balance to be assembled**
**Trigger Manager daughter-board: starting prod/fab now**
**Serial Link Transmitters complete**
**Serial Link Receivers production testing**
**MCEN (5 crates) in Preprod Testing(BU)**
**MCEN: preproduction testing underway**
**Centroid Daughter Board: preprod, testing underway**
**Crate manager: preprod layout.**
**Crates/Backplanes complete**
**Power Supplies on order.**

## L1 Muon Status

_**Software**_
**Download Infrastructure in place**
**Preproduction versions of all firmware exist.**
**No alarms, monitoring**
_**Personnel**_
**Arizona down to zero from two postdocs. Advertising for one replacement **
**Boston post doc hired, visa difficulties**
**Discussing Ken Johns buy-out.**
**Need help w/ assembly/test of PSupplies**
_**Commissioning/Schedule**_
**One trigger, one manager crate in operation and readout.**
**Next providing L1CTPT Manager Crate.**
**Two Octants triggering by 11/00**
**L1 Muon full crate assembled 1/01**
**MCEN full crate assembled 3/01**

- L1Muon before 3/01
- Some concern MCEN, manpower

## L2 Component Status

_**Alpha serial processors (MSU,UM,UIC)**_**: **
**Production Status**
**3 preproduction worked “out-of-the-box”**
**ADCO, same vendor that produced CDF TDCs**
**About 25 stuffed or nearly stuffed**
**Parts for another 15 in reserve**
**Many key components obsolete**
**Diagnostics @ UM**
**Four boards**
**To our knowledge none work**
**Diagnostics @ UIC**
**10 boards**
**2 incorrectly mounted components 8  have partial functionality**
**Rapid learning curve**
**Considering a range of options**
**Repair sufficient boards for March 1, 2001**
**Build new boards with larger vias and reserve parts**
**Build new boards with larger vias. Recover components and build full complement.**
**Re-layout board and/or find new vendor**
**Complete redesign**
**Hope to decide before November 1, leaning towards full press: repair, new boards, and redesign**
**Complicating commissioning.**

## L2 Components Cont.

_**MBT I/O Cards(U-Maryland)**_**:**** **
**6 production cards received. 3 pass specs. 3 under test now**
**Firmware functionality 90% done.**
**Remaining 25 boards built, parts on hand**
**Balance by December.**
_**FIC L1/L2 Interface(SACLAY):**_
**Boards complete**** **
**Final firmware adjustments October 16-20.**
_**SLIC Parallel Proc.(NIU,Columbia)**_**:**** **
**Boards complete**
**First results from DSP Central algorithm meet speed/efficiency requirements**
_**CIC, SFO Muon/L2 Interface (U-Neb)**_**:**** **** **
**Prototypes pass battery of tests but not up to standard design practices (two layers, unconventional shielding planes, unequal traces on differential signals...)**
**Have solicited advice from Fermilab engineers but process delayed by illness. Restarting now.**
**Delivery December?**

## L2 Status Cont.

_**Software**_
**C++ Framework exists**
**Preprocessor algorithms well developed, global needs attention.**
_**Commissioning/Testing**_**:**** **
**MCH and test stand racks and crates 85% done. Cabling 65% done**
**Commissioning sequence under discussion.**_** **_
**Essentially on hold until alpha, CIC, SFO issues resolved.**
**Once alpha’s MBTs are on hand the L2CAL, L2CTT, L2PS can be assembled <1 month.**
_**Personnel**_
**Recently lost one key postdoc from UIC and one from Maryland, will lose another UIC postdoc at the end of the year**
**One UIC postdoc has been replaced and new ones added from MSU and Columbia**
**Lack of on-site coordinator has slowed progress. Discussing Nikos Varelas buy-out.**
**Lack of project engineer has slowed progress. However, Rich Kwarciany (CD Electronics System Engineer) has been a great help as an on-call consultant. Fermilab looking into this.**

- MBT, SLIC, FIC ready before 3/01
- Alpha, CIC/SFO, manpower concerns

## STT

_**Motherboard & communication daughter board **_
**First prototypes in hand or being built**
**November**
_**Fiber Road & Track Fit daughter boards**_
**Parts in hand**
**prototypes coming (Feb/ Dec)**
**VHDL and simulation in progress**
_**STC(hit filter, cluster finder)**_
**VHDL design/coding in progress**
**Not easy to fit into real estate**
**May change Altera to Xilinx?  **
**Or fancier Altera?**
_**VME CPU: purchase in progress**_
_**Schedule**_
**Schedule in mid-update**
**Attempt integration in ****Feb 2001**** with first prototypes, not 2****nd**
**Scheduled Complete Feb 2002**

## DAQ/L3

**Evolved to a single multipurpose card used in VRC, SB, processor nodes (~100)**
**VHDL code specific to VRC, SB, Node complete**
**ETG is one of a kind.**

## L3/DAQ Status

_**Components(Brown)**_** **
**Layout done for 6 wks, parts procurement difficult.****	**
**25 board order placed with vendor**
**Layout @ board houses. Bids received. Production complete < 2 weeks.**
**Procuring parts now w/ Fermilab assistance**
**5 days to stuff & check**
_**Software(Brown,Washington)**_
**Framework up and running**
**Nodes also operational**
_**Commissioning/Installation**_
**Maintaining emulators for commissioning, no schedule delay for other systems.**
**Cable plant is minimal - reuses infrastructure, MCH 50% done, remainder under discussion.**
_**Schedule (full chain by Jan 1**__**)**_
**After receipt of board 1-2 week at Brown, then install 4 VRCs @ DAB**
**2 wks install 1 SB, fiber between VRC-SB**
**2 wks install multiple node adapters, fiber between SB-node. **
**ETG January**

- Software in good shape
- Watching delivery closely

##  Filtering/Database

_**Components(Various Institutions)**_** **
**Operational version of ScriptRunner**
**Unpacking code for cal, smt and muon**
**electron, muon, jet, missing et, and tau tools**
**Database and interface in design.**
_**Installation/Commissioning**_
**Participating in online tests of PDTs, CFT.**
**Participating in 10% SiDet Test**
**Milestone: readout/filtering muon system!**
_**Personnel**_
**Impending departure of Charles Leggett (LBL) infra-structure (unpack,tool template,offline verification)**
**Carmem Silva (LAFEX) database, currently only 1FTE on database**
**Insufficient support for NT release & porting.**
**Too few tool authors!**
_**Schedule**_
**11/00 standard running including ScriptRunner in Mark & Pass mode**
**1/01 monitor displays available**
**3/01 operational versions of all physics tools ported and available**** **

- Filtering operable, needs personpower

## Reportable Milestones

**Priorities:**
**(1) FWK, L1mu, L1CAL, L3 **
**(2) L2Global, L2CAL**
**(3) L1&L2 CTPT, FPS**

## Personnel Increases?

**To free engineers for VHDL preparation **_**a senior technician**_** to assist CTPT construction.  Could also help with L1Muon, L2 installation. Fermilab investigating.**
_**An engineer**_** to assist L2 debugging & integration.  This could be considered an escalation of the already valuable on-call arrangement. Fermilab investigating**
**Trying to arrange **_**full-time contributions**_** from**
**Ken Johns L1Muon**
**Nikos Varelas L2 **
**Looking for**** **_**two programmers**_** for **
**L3 infrastructure/release (Fermilab/LBL?)**
**Database (Collaboration?)**
**Other needs:  **
**Examines**
**L2 tools & verification**
**L3 tools & verification! **

## Closing Comments

**Trigger making excellent progress in all areas. (Didn’t mention TrigSim but will be a release Nov 1.)**
**Responding to delays by adding people to construction and commissioning efforts.**
**Will make L2alpha decision soon & trying to accelerate L3 component delivery.**
**First priority FMWK, L1CAL, L1Muon, L3. Then will add systems as components come available.**
_**Now’s the time to help: tools, filtering, database, commissioning.**_