# Presentation: 352592

## Electronic Systems Engineering

- CD Project Status Meeting - Astrophysics
- July 18th, 2006
- Alan Prosser

- SuperNova Acceleration Probe (SNAP)

- Hardware/Firmware at ESE

## SNAP – Spacecraft and Instrument

- Baffled Sun Shade

- Solar Array, ‘Sun Side’

- 3-mirror/
- 2-meter Telescope

- Solar Array, ‘Dark Side’

- Instrument Radiator

- Spacecraft Bus

***Instrument Package***

_**SNAP – Spacecraft and Instrument**_

## SNAP DAQ Overview

- Slice Box

- Instrument
- Control
- Unit

- 80

- 2

- 80

- Instrument
- Control
- Unit

- *50Mb/s

- *2Gb/s

- *2Gb/s

- *300Mb/s

- Telemetry

- *300Mb/s

- Slice Box

- 80

- 2

- 2

- Participation:
-  Detector and readout electronics R&D: collaborating with LBL, UofM and FNAL/PPD
-  Electronics modules: design of BeO port card
-  Slice box: design of slice card and ICU interface
-  Instrument control unit: collaborating with SLAC and LBL
-  Memory modules: collaborating with FNAL/PPD
-  Telemetry: off-the-shelf solution

- * Peak data rates displayed. Data comes in bursts with a 10% duty cycle.

- Data compression
- Data management
- Data formatting
- Interface to electronics modules

- *8Gb/s

_**SNAP DAQ Overview**_

## Slice Concept – DAQ and Control

**Slice/Front End Electronics SPI Control Interface**

**Slice/Front End Electronics Science Data Interface**

**Slice/Downlink Control Circuit Science Data Interface (ICU Interface Unit)**

**Slice**

**Slice**

**Slice**

**Slice**

**Downlink **
**Control **
**Circuit**

**SPI **
**Controller**
**Interface**

**SPI-like Control **
**Interface with **
**ICU**
**(2 for redundancy)**

**Data Interface**
**With**
**Spacecraft**
**Telemetry**
**System**
**(2 for redundancy)**

***ICU Interface Unit***

**Slice/SPI-like Controller Interface (ICU Interface Unit)**

**Slice/Front End Electronics SPI Control Interface**

**Slice/Front End Electronics Science Data Interface**

**Slice/Downlink Control Circuit Science Data Interface (ICU Interface Unit)**

***Each line indicates a group of  LVDS Pairs***

***Slices***

***Front***
***End ***
***Electronics***

***25 Mbps***

***25 Mbps***

***300 Mbps***

**Detector**
**Front End**

**Detector**
**Front End**

**Detector**
**Front End**

**Detector**
**Front End**

## Slice Channel (4 to a Slice Card)

**Flash Memory**

**SDRAM**

**FPGA**

***Science File Data (to Downlink Controller)***

***SPI-like Controller Interface (to ICU)***

***SPI-like ***
***Control***
***(Front ***
***End ***
***Modules)***

***Science ***
***Data***
***(from ***
***Front***
***End***
***Modules)***

_**Slice Channel (4 to a Slice Card)**_

**4 Gbit**

**4 Gbit**

**4 Gbit**

**4 Gbit**

**4 Gbit**

**4 Gbit**

**4 Gbit**

**4 Gbit**

**256 Mbit**

*Two independent banks*

***25 Mbps***

***25 Mbps***

***25 Mbps***

***25 Mbps***

## Slice FPGA Functional Blocks

**SPI Controller**
**Interface**

**Front End Electronics**
**Control Interface**

**Front End Electronics**
**Science Data Interface**

**Flash Memory Interface**

**To Downlink Controller**
**Science Data Interface**

**SPI Command **
**Processor and**
**Output **
**Formatter**

**Science Data **
**Front End**
**Processor**

**Science Data **
**Compression**

**Flash Controller**

**SDRAM **
**Controller**

**File Data**
**Output **
**Controller**

**Data Management**
**Interface**

***FPGA Boundary***

**SDRAM Interface**

_**Slice FPGA Functional Blocks**_

**Input Data**
**Word **
**Interface**

**Compressed Data**
**Interface**

**File Data**
**Output**
**Data and Control **
**Interfaces**

## Slice FPGA Functional Blocks

**Science **
**Data**
**Words**

_**Slice FPGA Functional Blocks**_
_**Science Data Compression Block**_

**.**
**.**
**.**

**Primary**
**Input**
**FIFO**

**Secondary**
**Input**
**FIFO**

**FIFO**
**Control**

**FIFO**
**Control**

**Flash**
**Page**
**Buffers**

**Page Buffer**
**Output**
**Control**

**Sequence**
**Length**
**Evaluation**
**(Parallel**
**Blocks)**

**Option **
**Voting**
**(Pipelined**
**Blocks)**

**Block**
**Option**
**Code**
**FIFO**

**Compressed**
**Data**
**Sequence**
**Construction**
**(Parallel Blocks)**

**Flash Memory**
**Word**
**Construction**

**Output**
**Data**
**(to Flash)**

***CCSDS Compression Option Evaluation Blocks***

***CCSDS Sequence and Memory Word Construction Blocks***

**Square **
**Root**
**Prescaler**

**PEM***

****Prediction Error Mapper***

**Packet**
**Formation**

## Space Qualified Design Methodology
High Reliability/Redundancy
Radiation Hard Components and Techniques

Parallel Processing Architecture
CCSDS Data Compression 

Pipelined Architecture
Square Root Compression
Two Stage CCSDS Compression

File System Management

- High Reliability/Redundancy
- Radiation Hard Components and Techniques
- Parallel Processing Architecture
- CCSDS Data Compression
- Pipelined Architecture
- Square Root Compression
- Two Stage CCSDS Compression
- File System Management

_**Special Challenges**_

## Description 
Development and test of all slice FPGA functions

Scope 
Design of firmware for acquisition, compression, storage, delivery, and control

Schedule 
I/O Blocks, Command Processing and Flash Controller (tested)
Data Compression (porting from Xilinx Prototype)
SDRAM Controller (after Data Compression done)

Stakeholders 
Guilherme Cardoso, John Chramowicz, John Marriner, Alan Prosser, Marcos Turqueti

- Development and test of all slice FPGA functions
- Scope
- Design of firmware for acquisition, compression, storage, delivery, and control
- Schedule
- I/O Blocks, Command Processing and Flash Controller (tested)
- Data Compression (porting from Xilinx Prototype)
- SDRAM Controller (after Data Compression done)
- Stakeholders
- Guilherme Cardoso, John Chramowicz, John Marriner, Alan Prosser, Marcos Turqueti

_**Firmware Development Activities**_

## SNAP Slice Card Firmware Development

_**SNAP Firmware Test Card V1.0**_

**PTA/PMC **
**Connection***

**Flash Memory**

**SDRAM**

**FPGA**
**(Actel A3P1000)**

*** ******* For ICU, Front End, and Downlink Emulation***

## Slide 11

## Description 
Development and support of radiation testing of flash memory devices

Scope 
Design of hardware, firmware, and device drivers for test bench

Schedule
Tests at Indiana (IUCF) in July
Further Testing at Berkeley 

Stakeholders 
Guilherme Cardoso, Greg Deuerling, John Marriner, William Wester

- Development and support of radiation testing of flash memory devices
- Scope
- Design of hardware, firmware, and device drivers for test bench
- Schedule
- Tests at Indiana (IUCF) in July
- Further Testing at Berkeley
- Stakeholders
- Guilherme Cardoso, Greg Deuerling, John Marriner, William Wester

_**Flash Memory Test Activities**_

## Flash Memory Test Hardware

_**Flash Memory Test Hardware**_

**Flash Memory Device Under Test**

**ESE **
**Test **
**Board**

## Flash Radiation Testing

- Total ionizing dose (protons also cause bulk damage).
- Single event effects (catastrophic effects and upsets)
- Also, begin to investigate procurement strategies.

- Fifty new
- boards
- ready for
- more tests
- with FPGA
- DAQ board

## Work Progressing on Multiple Fronts

Slice Hardware/Firmware

DAQ System Engineering

Memory Testing Hardware/Firmware/Support

ASIC Test Engineering

Front End Electronics Packaging

- Slice Hardware/Firmware
- DAQ System Engineering
- Memory Testing Hardware/Firmware/Support
- ASIC Test Engineering
- Front End Electronics Packaging

_**Summary**_