# Presentation: 363193

## Work Plan for the BTeV Level 1 Trigger

- September 1,  2000

- Erik Gottschalk
- Fermilab

## Erik Gottschalk   f

- Level 1 Trigger Work Plan

- 1) design and build the quadrant processor
-  receives pixel hits from the pixel readout
-  sorts hits by time stamp and saves them in a buffer
-  produces pixel clusters (digital center, pixel count, ADCs of edge pixels)
-  accepts requests to send clusters to Level 1, and/or to the Level 2/3 trigger
-  study whether hits should be sorted by location (ordered by **, or *r*)
-  clustering across column boundaries may be ignored until later
-  simulate data flow (queuing simulation and timing analysis)
-  see if the architecture works for the muon trigger
-  study which FPGA is best suited for this task and why (Altera, Xilinx, etc.)
- 2) design FPGA tracker
-  study less complicated and/or less costly alternatives   (e.g. equality in associative memory, or Nevis processor approach)
-  subdivide track segments in *z* instead of quadrants to simplify DSP farm
-  simulate data flow (queuing simulation and timing analysis)

- Erik Gottschalk   f

## Erik Gottschalk   f

- Level 1 Trigger Work Plan (cont.)

- 3) design track/vertex DSP farm
-  simplify the design
-  replace the two-farm system with a single farm of DSPs
-  baseline design places severe restrictions on the trigger algorithm
-  for example:
-    The minimum track requirement and *p**t* cut on *B*-decay tracks could
-    come much earlier in the calculations required for a trigger decision,   if track segments from the tracker are not subdivided into quadrants.
-  eliminate the need to pass track parameters to a second farm
-  study alternative track/vertex algorithms running on a single DSP
-  design hardware that can support DSPs from more than one vendor
-  investigate what and how trigger primitives are passed to Level 2/3
-  simulate data flow (queuing simulation and timing analysis)

- Erik Gottschalk   f

## Erik Gottschalk   f

- Level 1 Trigger Work Plan (cont.)

- 4) design switching network between the FPGA tracker and the DSP farm
-  if track segments are subdivided in *z* then sort tracks using track slope
-  what are the data rates for data links?
- 5) develop software for the DSP farm
-  software is simplified if we have a single DSP farm instead of two farms
-  structure software for modular implementation of assembly-language code
-  timing for DSP code
-  study methods for timing code without having to write assembly language
-  investigate cuts for the Level 1 trigger
-  maintain code compatibility between Level 1 and Monte Carlo simulations

- Erik Gottschalk   f

## Erik Gottschalk   f

- Level 1 Issues

-  studies of bandwidth headroom and hardware limits for clusters, tracks, etc.
-  more realistic simulations (e.g. pixel clusters that span column boundaries)
-  study fault tolerance in the trigger design
-  study interactions with the DAQ and Global Level 1
-  rewrite tracking and vertexing code optimized for hardware
-  study algorithm robustness and methods to insure data integrity
-  design control and monitoring for Level 1
-  design and build a hardware prototype

- Erik Gottschalk   f