# Presentation: 667259

## FEM data management development

- S. Butsyk

## Basic concept

- Need to store hits from last 64 beam crossings according to the BCO
- Fast readout upon trigger decision
- Use set of 64 FIFO with steering logic on the input and output

- Data IN

- CLK

- FIFO select
- Reset logic

- Read Address

- Data OUT

- 128 word deep

**FIFO****0**

**FIFO****1**

**FIFO****62**

**FIFO****63**

- 32 bit wide

## Implementation

- Use standard FIFO Logicore elements with relationally placed macros (RPM)
- 64 2-bit buffers for previous highest BCO bit storage
- Lowest 6 bits define FIFO index
- FIFO RST logic activates 1 clock before the data from new BCO starts being written
- Global RST issued to all FIFOs on startup
- Current design utilization for V4VSX35 ~4200 cells(27%), 65 RAM16 blocks(33%)

## Steering logic

## FIFO select logic

- Shown for 4 FIFO array for simplicity

## Current test results

**888000c1 999000c1 aaa000c1 bbb000c1 ccc000c1 ddd000c1 ****00000000 00000000**
**eee000c2 fff000c2 000000c2 111000c2 222000c2 333000c2 ****00000000 00000000**
**444000c3 555000c3 666000c3 777000c3 888000c3 999000c3 ****00000000 00000000**
**aaa000c4 bbb000c4 ccc000c4 ddd000c4 eee000c4 fff000c4 ****00000000 00000000**
**000000c5 111000c5 222000c5 333000c5 444000c5 555000c5 ****00000000 00000000**
**666000c6 777000c6 888000c6 999000c6 aaa000c6 bbb000c6 ****00000000 00000000**
**ccc000c7 ddd000c7 eee000c7 fff000c7 000000c7 111000c7 ****00000000 00000000**
**	****	****    ****...**
**444000d3 555000d3 666000d3 777000d3 888000d3 999000d3 ****00000000 00000000**
**aaa000d4 bbb000d4 ccc000d4 ddd000d4 eee000d4 fff000d4 ****00000000 00000000**
**000000d5 111000d5 222000d5 333000d5 444000d5 555000d5 ****00000000 00000000**
**666000d6 777000d6 888000d6 999000d6 aaa000d6 bbb000d6 ****00000000 00000000**
**ccc000d7 ddd000d7 eee000d7 fff000d7 000000d7 111000d7 ****00000000 00000000**
**222000d8 333000d8 444000d8 555000d8 666000d8 777000d8 ****00000000 00000000**
**888000d9 999000d9 aaa000d9 bbb000d9 ccc000d9 ddd000d9 ****00000000 00000000**
**eee000da fff000da 000000da 111000da 222000da 333000da ****00000000 00000000**
**444000db 555000db 666000db 777000db 888000db 999000db ****00000000 00000000**
**aaa000dc bbb000dc ccc000dc ddd000dc eee000dc fff000dc ****00000000 00000000**
**000000dd 111000dd ****00000000 00000000 00000000 00000000 00000000 00000000**
**6660009e 7770009e 8880009e 9990009e aaa0009e bbb0009e ****00000000 00000000**
**ccc0009f ddd0009f eee0009f fff0009f 0000009f 1110009f ****00000000 00000000**
**	****	****    ****...**
**eee000ba fff000ba 000000ba 111000ba 222000ba 333000ba ****00000000 00000000**
**444000bb 555000bb 666000bb 777000bb 888000bb 999000bb ****00000000 00000000**
**aaa000bc bbb000bc ccc000bc ddd000bc eee000bc fff000bc ****00000000 00000000**
**000000bd 111000bd 222000bd 333000bd 444000bd 555000bd ****00000000 00000000**
**666000be 777000be 888000be 999000be aaa000be bbb000be ****00000000 00000000**
**ccc000bf ddd000bf eee000bf fff000bf 000000bf 111000bf ****00000000 00000000**

- FIFO 0
- FIFO 1
- FIFO 2
- FIFO 3
- FIFO 4
- FIFO 5
- FIFO 6
- FIFO 7

- 64 FIFO array model is synthesized and tested
- Fake signal is used for Chip_ID and BCO
- 3 bit Chip_ID increments on every clock
- 6 hits with one BCO generated
- Send RST, write data for 1 second, take a snapshot of the FIFO content
- Write frequency – 50 MHz
- Read frequency – 200 MHz
- Readout through the parallel port
- 2 data integrity errors in 3000 read trails
- FIFO is not reset from the previous BCO
- Possible solution : synchronous FIFO reset

- BCO

- CHIP_ID

- Last hit that was written before read

- Wrap around

## Conclusion 

- 64 FIFO array design implemented and successfully tested on V4VSX35 chip
- Design is logical and robust
- The read frequency can be high enough (200 MHz tested, 300 MHz expected) to output the large data sample (up to 128 hits) before the arrival of the next hit into the same FIFO
- Additional issues (data packaging by applying BCO counter as a separate data word e.t.c ) currently being studied