# Presentation: 653780

## ADC Analysis  

- Bow
- Happens across the chip
- This is a relatively large distance in IC terms
- Effect is SYSTEMATIC
- Can probably be modelled  with resistive&capacitive loading/parasitics across the chip
- Ch-Ch
- Effect is STOCHASTIC
- Concerns the circuit matching from ch-ch
- Transistor matching is mainly given by two parameters, deltaBeta and deltaVt

- 10/2002

## Ch-Ch Variation Analysis  

- Ch-Ch: deltaVt and deltaB
- How to know if process variation of Vth and/or Beta is the cause?
- The simulated comparator delay and variation should follow the measured one
- How to know which transistors are the cause?
- Put the measured statistical parameters for deltaVt and deltaBeta into a TSMC transistor model and run Monte Carlo simulation with this model only on certain transistors, while other transistors remain fixed
- Hypothesis: we will find a few transistors that are responsible for most of the variation
- How to know specifically what is the root cause?
- Changing the operating parameters of the sensitive transistors should have the effect on performance that is predicted by the level 2 model
- This gives us the answer as to exactly what needs fixed—bias point, size, current, etc. in the circuit

- 10/2002

## Simulations—Ramp Up 

- Choose the most likely candidates, simulate the max dVth given by the process, see if it will produce a variation corresponding to the measurements
- If so, MC makes sense, if not, maybe it’s a waste of time
- The result: Yes for 8/1.6 PCH transistors, max deltaVth gives 5.1 counts at 10uA
- Good start, next pair of transistors to try are 5.6/1.6 NCH
- What is the combined effect of varying the 4 NCH&PCH together
- What about the rest of the circuit: delay is less for all other devices
- Prove its not deltaBeta: No change in delay
- Why do you believe it?
- Its what theory predicts
- It follows the measurements

- 10/2002

## Summary—Ramp Up

**ADC Counts**

- 10/2002

## Simulations—Ramp Down

- Pedestal structure is different, can this be duplicated?
- Varying only the two 8.6/1.6 transistors, the behavior of the comparator&anadelay follows the measurements qualitatively
- The polarities deltaVth that cause the most variation in Ramp Up are not the same as those in Ramp Down
- This means that the pedestal structure will be different for Ramp Up and Ramp Down
- What about the variation range?
- Matches measurements with similar precision as the ramp up simulations

- 10/2002

## Summary—Ramp Down

**ADC Counts**

- 10/2002

## Conclusions—MC Sim Works 

- Why do you believe it?
- Its what theory predicts
- It follows the measurements
- What about that “root cause”?
- Increase Vgs by reducing W—delay variation range should decrease, absolute delay should increase:  This Works!
- Proof: “delay” and “variation” should be considered independently
- What to fix?
- I don’t propose to resize the comparator&anadelay transistors
- Check effect of raising the bias current, which is a modification that is effectively already proven by Len’s measurements
- Check effect of  moving n2, as Tom has already suggested, to put the current sources more in saturation
- Importance of a matching simulation setup
- We can verify design changes

- 10/2002

## What’s next 

- (1 week) I propose to implement the minimum fixes to the bias circuit only, and see if the simulation will give show acceptable performance
- Hopefully can avoid changing the comparator&anadelay cell
- When the channel comparator is faster, may need to make thresher faster; hopefully can be achieved by more current, rather than design change
- (1 week) I propose to study the “bow” issue next to understand its root cause, and determine the minimum fixes there
- Since the effects are somewhat interrelated in the measurement, the same fixes as above may reduce the problem
- Still want to fix the charge-injection from timing mismatch of comprst/comprst* and long routing of comprst and rrefsel
- Initial sims a few weeks ago didn’t implicate these, but need to double-check

- 10/2002