# Presentation: 664592

## MIPP TDC Card

- _Wu, Jinyuan_
- Fermilab, PPD/EED
- Apr. 2007

## The TDC Card

- 96 Channels.
- 12 connectors, 8ch each.
- Each MIPP_TDC FPGA digitize 48 channels inputs.
- The MIPP_DCC FPGA concentrate data from two TDC FPGA devices.
- Up to 32K event/spill are stored in the SDRAM.
- TDC resolution: 1.18ns (LSB). Bench tested @ 0.69ns (LSB) (See next pages)

- MIPP_DCC FPGA

- MIPP_TDC FPGA

- MIPP_TDC FPGA

- RJ-45

- SDRAM

## TDC Inside FPGA

**c0**

**c90**

**c180**

**c270**

**c0**

**Multiple**
**Sampling**

**Clock**
**Domain**
**Changing**

**Trans. Detection**
**& Encode**

**Q0**

**Q1**

**Q2**

**Q3**

**QF**

**QE**

**QD**

**c90**

**Coarse Time**
**Counter**

**DV**

**T0**
**T1**

**TS**

- Sampling rate: 360 MHz x4 phases = 1.44 GHz.
- LSB = 0.69 ns.
- Logic elements with critical timing are assigned as shown.

- 4Ch

- Logic elements with non-critical timing are freely placed by the fitter of the compiler.

## Bench Test of TDC

- Micro-processor address line driven by
- 45 MHz clock.
- 32 TDC bin = 1 clock cycle (0.69ns LSB)

- Micro-processor data line.
- Data out from different sources.

- eZ80

- RAM

- Flash
- RAM

- FPGA

- TDC

- eZ80

- RAM

- Flash
- RAM

- FPGA

- TDC

- 45MHz

- 45MHz

## The FPGA TDC Test Card

- Serial Port

- VME Interface
- (As hit input)

- FPGA

- Shown here is Fermilab Beam Loss Monitor (BLM) Control Card

- Microprocessor

## Differential Nonlinearity

- The placement above gives even bin width.
- Occupancy for each bin should 25%.
- The residual DNL < 690*(26-22)/25 = 110ps

- FPGA

- TDC

- Quasi-random
- Input

- The “beat” between input and 45MHz.

- 45MHz

## TDC Data Concentration

- Substituting Multiple Error Sources with Single Error Source

## TDC  With Hit Rate Limiter

- TDC

- T1
- T0
- DV

- Counter

- Hit Rate
- Limiter
- (4/256CK212)

- DVLD
- CLR

- CK212

- L/S

- LD

- TDC/HRL

- TDC/HRL

- TDC/HRL

- TDC/HRL

- CC[5..2]

- 4hits/256CK212,
- 4hits/1.2s
- 3.3MHz

- CLRHIT

- LD

- CLRCNT

- 0

- 1

- 2

- 3

- 4

- 5

- 6

- 7

- 1.2us

- 8

- 9

- a

- b

- c

- Reset

## TDC  Data Concentration 96 Ch

- L1 Buffer
- 1xM4K
- 16x256

- Zero
- Supp.

- TDC/HRL

- TDC/HRL

- EV Buffer &
- Truncating
- 16x128x2

- SDRAM
- 16x8M/spill
- 16MB/spill

- TDC/HRL

- TDC/HRL

- FPGA
- (DCC)

- Ch 4-7, TDC & L1 Buffer

- TDC/L1 Buffer/MUX
- Channels 16-31

- TDC/L1 Buffer/MUX
- Channels 32-47

- Ch 8-11, TDC & L1 Buffer

- Ch 12-15, TDC & L1 Buffer

- EV Buffer &
- Truncating
- 16x128x2

## Readout Timing

- G0
- B=0

- G4
- B=0

- G0
- B=1

- G4
- B=1

- G8
- B=1

- G12
- B=1

- G24
- B=1

- G8
- B=0

- G12
- B=0

- G16
- B=0

- G20
- B=0

- G16
- B=1

- G20
- B=1

- G24
- B=0

- G28
- B=0

- G28
- B=1

- 0

- 1

- 2

- 3

- 4

- 5

- 6

- 0,1

- 7

- 6.6us

- 1.2us

- 8

- 9

- a

- b

- c

- 0,1

- WR

- RD

- G32
- B=0

- G32
- B=1

- G44
- B=1

- 0,1

- 1.2us

## Data Format

- 1

- CH[3..0]

- CC[10..2]

- T1

- T0

- BD_CHGRP[4..0]

- CNT[7..0]

- EV[13..0]=1, 2, .. 16K-1

- EHID[5..0]

- Reserved Header/Ender

- EV Header 0

- EV Header 1

- Hit Data

- 0

- 1

- 1

- P

- 1

- P

- 1

- P

- 0

- 0

- 0

- 0

- 0

- No Data

- 1

- P

- CHGRP Header

- 0

- 0

- 0

- 0

- TS[7..0]

- 0

- 1

- 0

- 1

- 0

- 1

- P

- Ender

## Data Block

- CHGRP Header CHGRP=0

- EV Header 0

- EV Header 1

- No Data

- Hit Data

- Hit Data

- CHGRP Header CHGRP=1

- Hit Data

- CHGRP Header CHGRP=2

- CHGRP Header CHGRP=3

- Hit Data

- CHGRP Header CHGRP=4

- CHGRP Header CHGRP=5

- Ender (=No Data)

- CHGRP Header CHGRP=0

- EV Header 0

- EV Header 1

- No Data

- Hit Data

- Hit Data

- CHGRP Header CHGRP=1

- CHGRP Header CHGRP=2

- Ender (=No Data)

- EV Header 0

- EV Header 1

- No Data

- CHGRP Header CHGRP=3

- Hit Data

- CHGRP Header CHGRP=4

- CHGRP Header CHGRP=5

- Ender (=No Data)

- Hit Data

## Useful Numbers: for 96 Channel Board

|  |  |  |  |
| --- | --- | --- | --- |
| RF | 53.102MHz, 18.8ns |  |  |
| CK212 | 212.4MHz, 4.708ns |  |  |
| LSB | 1.18ns |  |  |
| Hit Rate Limiter Setting | 4hits/256CK212 | 4hits/64RF | 4hits/1.2s, 3.3MHz |
| Double Hit Min. Separation | 4xCK106, 37.7ns |  |  |
| Event Window | 2 x 1.2s |  |  |
| Absolute Maximum Hits/event/48ch | 123hits+5header/trailers | 128 x 2Bytes |  |
| Event Maximum Size/96ch | 256 x 2Bytes |  |  |
| SDRAM port data rate | 53MHz x 2Bytes | 4.8s/event |  |
| Number of events/spill | <32K |  |  |
| Absolute Maximum data/spill/FE card | 8M words | 16MB |  |
| Absolute Maximum data/spill/8 FE |  | 128MB | 1280Mbits |
| Readout Chain Data Rate | 26.5Mbits/s |  |  |
| Absolute Maximum Spill Readout Time | 48.3sec |  |  |

## TDC Description

- The TDC FE card has three FPGA devices: two named MIPP_TDC and one named MIPP_DCC.  Each MIPP_TDC digitizes 48 channels of inputs and sends data to MIPP_DCC which interfaces with a 16MB SDRAM and the daisy-chained interface to ship data back to the controller.  A TDC_FE card supports 96 input channels.
- Each channel in the MIPP_TDC has a hit limiter.  The time is split into 1.2us (or 64RF, RF=1/53MHz) periods which are counted after the reset at the start of each spill.  In each of the 1.2us, the number of hits in each channel is limited to 4 hits.
- A channel group contains 4 channels.  Every 4 cycles of CK106 (106MHz), hit data in each channel is written to the hold-shift register.  The hold-shift register then shift data of the 4 channels, one in each CK106 cycle, to the zero suppression block.  Therefore, the hit separation in each channel is 4 x 1/106MHz = 37.7 ns.
- The zero-suppressed data from the 4-channel groups, i.e., only the valid hits are stored in the L1 pipeline buffers.  A pipeline buffer is organized as 16 blocks of 16 words with 16-bit/word which uses a M4K RAM.  Each hit is stored as a 16-bit word, each channel can have maximum 4 hits in 1.2us.  Therefore, a 16 words block holds data of 4 channels in 1.2us.  The entire L1 pipeline length is 16x1.2us = 19.3us.
- Up to about 18us trigger latency are supported.  For each trigger, data in 2 x 1.2us time window are readout, which corresponding to 2 16-word blocks in the L1 pipeline buffer.  Data from 16 channels are grouped together, taking 1.2us to transfer from the L1 pipeline buffer to the EV buffer.  Data of 48 channels are transferred in 3.6us.
- Truncating happens while storing data into EV buffer if too many channels are hot.  The data for an event stored in the EV buffer contains 2 headers and 3 enders, one at the end of each 16-channel group.  The total number of hits allowed in 48 channels is 123.  The truncated data block is not good for experiment data, however, it contains all necessary header and enders to avoid hanging up the remaining readout system.
- Up to 256 16-bit words/event for 96 channels are stored in the 16MB SDRAM.  A total of 32K events can be held in the SDRAM.
- Daisy chained 8 TDC_FE cards are readout through a 26.5Mbit/s data link to the controller.  The total time to readout 8 x 16 MB is about 48.3 sec.

## ADC Using FPGA

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- ADC

- ADC

- ADC

- ADC

- FPGA

- TDC

- TDC

- TDC

- TDC

- R1

- R1

- C

- R2

- FPGA

- VREF

- Analog signals from AMP & Shapers are directly fed to FPGA pins.
- FPGA output and passive RC network are used to generate ramping reference voltage VREF.
- The input voltages and VREF are compared using FPGA differential input receiers.
- The times of transitions representing input voltage values are digitized by TDC blocks in FPGA.

- T1

- V1

- T2

- V2

- T3

- V3

- T4

- V4

## ADC Test: Reference on BD3_19

- FPGA

- TDC

- TDC

- 50

- 50

- 1000pF

- 100

- VREF

-  = 59 ns

- Longer time constant causes the V-T curve to be nearly linear.
- Sampling rate: 22.5MHz (2/88ns).
- Measurement range: 6 bits.
- Sensitivity: 10mV/LSB.

## ADC Test: Waveform Digitization on BD3_19

- Input Waveform

- Raw Data

- Input Waveform, Overlap Trigger

- Converted

## ADC Test: Reference on BD4_22

- FPGA

- TDC

- TDC

- 50

- 50

- 150pF

- 100

- VREF

-  = 7.5 ns

- Shorter time constant causes the V-T curve to be exponential.
- Sampling rate: 22.5MHz (2/88ns).
- Measurement range: 6 bits.
- Sensitivity < 6mV/LSB.
- Dynamic Range: ~8 bits.

## ADC Test: Waveform Digitization on BD4_22

- Input Waveform

- Raw Data

- Converted

- The data measured by trailing ramp is much more smoother than the leading ramp for small pulses.

- Small pulses are emphasized by the trailing ramp measurement.

## ADC Test: Summary

|  | Time Constant | Ramping Time & Sampling Rate | Sensitivity | Full Scale Range | Measurement & Dynamic Range
 |
| --- | --- | --- | --- | --- | --- |
| BD4
Discharge | 146 ns | 353 ns
> 2MHz | 1.1mV
/LSB
(@ 0.3V) | .25-2.7V | 9 bits &
~12 bits |
| BD3_19 | 59 ns | 44 ns
22.5MHz | 10mV
/LSB | 1.4-2.05V | 6 bits |
| BD4_22 | 7.5 ns | 44ns
22.5MHz | <6mV
/LSB
(@1.02V) | 1.02-2.48V | 6 bits &
~8 bits |

## Notes

- Like in any analog circuits, noise reduction is the key to reach good resolution.  Two primary measures are taken:
- Appropriate arrangement of the grounding for analog signals.
- Microprocessor are put in “wait” state during ramping and comparing.
- Large noise due to single ended TTL are bad.  But small and random noise from differential outputs can be good for “dithering”.  This is to be studied.
- Being non-linear, the RC exponential charging curve is bad.  But it allows expansion of dynamic range, which is good.  The conversion to linear scale in FPGA is very simple.

## Remarks

- The ADC functions tested have met requirements of many applications in high energy physics and accelerator instrumentation.
- The FPGA ADC will not completely replace commercial ADC or ASIC.  But it is appealing for sake of convenience (like for slow control/monitoring) or for low cost with large channel count (like for straw tube or TPC chambers).