# Presentation: 048835

## Electrical/Optical Issues in I/O CMOS Interfaces 

**Thad Gabara**
**Bell Laboratories**
**Murray Hill, NJ**

- Optical Interconnect Workshop

## Electrical vs. Optical

** ****Interconnect length is a limiting aspect**
**	****on-chip**
**	****between chips**
**	****between boards**
**	****between cabinets**
**	****between buildings**
**	****cities and countries**

**Electrical**

**Optical**

**thrend/BW**

- Optical Interconnect Workshop

## Rent’s Rule

**transistors (n)**

**I/Os**

**10****7**

**1K**

**10K**

**100**

- ISD June 1998, Tets Maniwa

- Memory

- Processor

- ASIC

**10****8**

**10****9**

**10****10**

**10****11**

**10****12**

**#I/O = k n****p**

**0.2 < p < 0.7**
**   ****3 < k < 4**

- Optical Interconnect Workshop

## Chip Interconnect Density

**Die size (mm****2****)**

**I/Os per die**

**6**

**10**

**14**

**1000**

**2000**

**3000**

**4000**

**5000**

- IBM, M. Nealon, Micro News

**8**

**12**

**16**

- Wire bond - 100m

- Wire bond - 70m

- solder bump - 225m

- Optical Interconnect Workshop

## Chip to Board Clock Rate

**Year**

**Clock rate (GHz)**

**95**

**00**

**05**

**10**

- Source: SIA 1997 Roadmap

- Multiplexed Bus

- Peripheral Bus

- Optical Interconnect Workshop

## I/O Impact of Scaling CMOS

** ****Density in core is increasing**
** ****Allows more data to be processed**
** ****Need to keep up information **
**transfer to/from core**
** ****I/O transfer rates increasing**
** ****Rent’s rule forces high pin count**

- Optical Interconnect Workshop

## Chip I/O Limitation

** ****Solder bump **
** ****Process and packaging step differences**
** ****CAD tools for chip partitioning**
** ****Offers new potentials for system growth**
** ****Allows for optimized process attachment **

- Optical Interconnect Workshop

## Solder Bump System Possibilities

** ****Shingling die**
**  ****Combine different optimized**
**    ****die together **
**  ****Allows formation of compact**
**    ****systems **
** **

**Memory**

**Bi-CMOS**

**Passives**

**CMOS**

- Optical Interconnect Workshop

## Optical Chip Communication

** ****Process added step to CMOS**
** ****SEED, VCSEL needs to cost compete**
**with solder bump**
** ****May offer backplane benefits**
** ****Current High BW interfaces may benefit**
**	****CPU-memory**
**	****Switching networks **

- Optical Interconnect Workshop

## CDR Background

** ****single interconnect**
**	****-  coding schemes**
**	****-  contains both clock and data**
**	****-  bandwidth efficient connection**
** ****at destination**
**	****- perform post-processing **
**	****  ****to extract clock from data **
** ****synchronize data at destination **
**	****- using recovered clock**
**	****	**

- Optical Interconnect Workshop

## Clock and Data Recovery Performance Trend

**Year**

**data rate (GB/s)**

**00**

**90**

**80**

**1**

**10**

**0.1**

**Source: International Solid-State Circuit **
**	**** ****Conference**

**projected**
**Sonet target**

- Optical Interconnect Workshop

## Shadowing

**die outline**

** ****Digital ASIC technique**
** ****Use same layout around the frame**
** ****Typically use a linear layout**
** ****Small swing buffers are a problem**

**gate**

**Measured Data of V****ol**** of **
**800mV swing(over several lots)**
**	****       ****Avg ********V****	****   ******
** ****linear****	****	****136mV****	****   31.6mV**

**gate**

- Optical Interconnect Workshop

## Rotational Symmetry

**die outline**

** ****Current matches**
** ****Gate segments match**

**gate**

**gate**

**Measured Data of V****ol**** of **
**800mV swing(over several lots)**
**	****       ****Avg ********V****	****   ******
** ****linear****	****	****136mV****	****   31.6mV**
**Rot Sym****	****30mV****	****   8.9mV**

- Optical Interconnect Workshop

## Packaging

**V****L**** = L di/dt**
**introduces Ground **
**Bounce**

**25%**

**40%**

**60%**

- PGA 100 mil pitch

- Area PGA
- 100 mil pitch

- Area BGA
- 50 mil pitch

- Direct Chip attach
- 20 mil pitch

**Package size reduction achieves:**
**Lower L ; smaller board area.**

- IBM, M. Nealon, Micro News

**  ****Need to get power/ground to the chip**

- Optical Interconnect Workshop

## Ground Bounce Reduction

**Wide Bus**

**enable**

**V****L**** = L di/dt**

**i**

**L**

**Equ**
**Model**

**  ****Want to dampen the circuit**
**  ****Use transistor sizing to control **
**     ****transistor impedance - R****C**
**  ****Insert impedance in VSS pad and**
**     ****inverse regulate ground **
**     ****impedance - R****G**
**	**

**K**

** ****PVT makes R****t****+/- 50%**

- Optical Interconnect Workshop

## Digital Transistor Sizing

**  ****Technique used over 2Gb/s**
**  ****Data path segregated from control**
**  ****Selector allows dynamic transistor sizing**
**  ****PVT (Process, Voltage, Temp) compensated (R and I)**
**  ****Controls impedance, performance, power, etc.**
**  ****Used in Ground Bounce buffers, HSTL and other buffers**

- Optical Interconnect Workshop

## Test Setup to Measure Bit Errors

**From Pulse Generator**
**10MHz (0-3.6V)**

**Ground Bounce**
**Test Chip**

**Old   or   New**

- N

- C

**From BERT**

**80Mb/s**
**(2****15****-1)**

**To BERT**

- N

- C

- 16

- 60

- 60

- 60

- 0

- 0

- (pF)

- Optical Interconnect Workshop

## Bit Errors Generated

**V****amp**** (volts)**

**Number of bit errors (OUT OF 4.8b BITS)**

**0.1**

**10**

**100**

**1K**

**10K**

**100K**

**1M**

**10M**

**100M**

**1B**

**0.2**

**0.3**

**0.4**

**0.5**

**0.6**

**0.7**

**0.8**

**0.9**

**1.0**

**1.1**

**1.2**

**7 orders of**
**improvement**

- Optical Interconnect Workshop

## Computer/Processor Trends

**Year**

**Instructions/sec**

**90**

**40**

**10**

**50**

**60**

**70**

**80**

**00**

**100**

**1K**

**10K**

**100K**

**1M**

**10M**

**100M**

**1B**

**10B**

**100B**

**HARVARD**
**MARK I**

**COLOSSUS**

**MARK II**
**COLOSSUS**

**ENIAC**
**30 TONS**

**EDVAC**

**ILLIAC**

**WHIRLWIND**

**UNIVACI**

**IBM 704**

**IBM 7090**

**IBM STRETCH**

**CDC 6600**

**CDC 6800**

**CDC 7600**

**IBM 360/85**

**IBM 801**

**CRAY I**

**CRAY XMP-4**

**Connection**
**Machine**

**INTEL**
**4004**

**INTEL**
**8080**

**INTEL**
**8086**

**WE32100**

**MC68000**

**IBM 3033**

**VAX 8200**

**MC68020**

**WE32200**

**CLIPPER**

**CRISP**

**IBM 3081**

**AMDAHL**
**5860**

**AM2900**

**VAX 8800**

**RCA GaAS**

- Optical Interconnect Workshop

## Optical Chip Clocking

** ****Process added step to CMOS - maybe?**
** ****Reduces skew**
** ****Easier to synchronize chip**

**CMOS Chip**

- Optical Interconnect Workshop

## Skin Effect

** ****Skin effect**
** ****Affects the cross-sectional area**
** ****The high-frequency components become **
**more attenuated **
** ****This causes “pattern dependent” effects which **
**     ****is know as intersysmbol interference**

*******f*********)****-0.5**

**Below some T, **
**the eye diagram **
**of the data **
**degrades in **
**W and H**

- W

- H

- T

- Optical Interconnect Workshop

## Optical Communication

** ****Skin effect doesn’t occur**
** ****Attenuation - 0.2db/km?**
** ****Electrical attenuation -5db at a few GHz**
** ****Electrical intersysmbol interference gone**
** ****This is nice**
** ****Circuits and techniques push the envelope**
** ****ULSI gives transistors to use for I/O **

- Optical Interconnect Workshop

## Equalization

** ****Pre-emphasizes signal to compensate**
**    ****for attenuation**
** ****Gives flat attenuation response from 0.2 **
**    ****to 2GHz**
**  ****4Gb/s over 100m**

- W. Dally and J. Poulton

- Optical Interconnect Workshop

## Conclusions

** ****Reviewed the SIA roadmap for I/O**
** ****I/O Impact of scaling CMOS**
** ****Circuit and system techniques **
** ****Skin effect**
** ****Equalization**
** ****CMOS circuit design, infrastructure, CAD tools, **
**        ****ULSI, all favor pushing existing limits**
** ****Tends to delay optical entry at the lowest level**

- Optical Interconnect Workshop