# Presentation: 218529

## Actel RTAX-S FPGA Reliability Summary

- Kangsen Huey, HiRel Program Manager
- Ravi Pragasam, Senior Marketing Manager

## Agenda : RTAX-S

- Introduction
- Qualification
**MIL-PRF-38535, Class Q**
**Actel Antifuse Reliability Studies**
**EAQ ( **_**E**_**nhanced  **_**A**_**ntifuse **_**Q**_**ualification)**
**HSB (**_**H**_**igh Single **_**S**_**, Single **_**B**_**) Design**
- New Processes and Procedures
**ELA : **_**E**_**nhanced **_**L**_**ot **_**A**_**cceptance**
**XSEM : Die Cross Sections at Antifuse**
- Reliability Data and FIT Rate
- Summary
- Actel Flash Product Roadmap

## RTAX-S Product Lineup

- Introduced in 2004 and QML class Q level Qualified in 2005
**Wafers fabricated on 0.15 μm process at ****United Microelectronics Corp (UMC), Taiwan**

## RTAX-S New Technology Features

- First Antifuse FPGA that offers up to 4 Million system gates with  enhanced features:
**Embedded RAM blocks**
**Extensive I/O standard support**
**Hardened charge pump, clock trees, Power On Reset circuit**
**TMR Flip Flops**
- RTAX-S Antifuse Technology
**Implemented with ****0.15**** ****μ****m CMOS process with new circuits designed to improve programming current and reduce net loading**
**Antifuse is similar in structure, but thinner than RTSX-SU generation due to the lower programming voltage**
**Results in less distance for material transport of the plate material during programming, resulting in better I****PEAK**** tolerance for net loading**
**Single S-Antifuses get 67% less I****PEAK**** stress during switching compared to RTSX-SU**
**Designer software has **_**SAL**_** (**_**S**_**- **_**A**_**ntifuse **_**L**_**oading) to dramatically reduce ****Single S-Antifuse count**
**Single B-Antifuses have 50% less I****PEAK**** vs. RTSX-SU**
**Architecture includes adding buffers to reduce net loading on long nets**
**Programming Current**
**B, I, S, K antifuses have 10% to 20% more programming current**

## RTAX-S QML Qualification with Enhanced Testing for Antifuse

**RTAX-S QUALIFICATION**

**MIL-PRF-38535, Class Q Qualification**

**Actel Antifuse Reliability Studies**
**(Enhanced Antifuse Qualification + HSB)**

**&**

## RTAX-S Qualification (1/3)

- MIL-PRF-38535, Class Q Level Compliant Qualification
**Qualification Burn In (QBI) Design was developed for qualification life test**
**Tests the overall CMOS and Antifuse technology**
**Maximizes resources utilization like the Flip Flops, IOs, SRAM, FIFO, Carry chains, etc.**
**Functional test vector developed to for 3-temp FT**
**Uses fully class Q level screened devices**
**Group C test**
**87 RTAX2000S and 98 RTAX1000S devices passed 1,000 hours of group C at 125****o****C**
**Pass/Fail criteria tightened to LTPD(3) equivalent of 129(1) of the largest RTAX2000S devices**
***Assuming every 2 RTAX1000S equals to one RTAX2000S***
**Added LTOL (Low Temp Operating Life) test**
**78 RTAX1000S devices passed 1,000 hours of LTOL at -55****o****C**
**Group A, B, D, ESD, Latch-Up, IO Capacitance also performed**
**6 parts (2 RTAX2000S and 4 RTAX1000S) in Group C and 1 part in LTOL failed due to equipment failures**
**FA reports available upon request**

## RTAX-S Qualification (2/3)

- EAQ (Enhanced Antifuse Qualification)
**Objective is to uncover antifuse failure modes and determine antifuse failure rate**
**Uses highly perceptive and stressful designs for antifuse evaluation**
***Similar to the antifuse studies employed for RTSX-SU***
**The EAQ design is capable to detect small (pico to nano seconds) shifts in net propagation delay, which can be detected through analyzing the delta delays**
**High and Low Temperature Operating Life tests (HTOL/LTOL) performed with RTAX1000S-CG624 devices**
**291 units passed 1,000 hours of HTOL at +125****o****C and 250 hours of LTOL at -55****o****C**
***One unit had CMOS process related failure (non-antifuse related) after 500 hours of HTOL***
***6 units failed due to equipment (BIB data contention)***
***Devices did not go through the Burn-In screening required for QML class Q level devices***
**120 units carried on and all passed 6,000 hours of HTOL with ****No failures**

## RTAX-S Qualification (3/3)

_**H**_igh single _**S**_-Antifuse and high single _**B**_-Antifuse (HSB) utilization design
**Testing was conducted after the completion of QML qualification activity**
**HSB design maximized the utilization of both single S-Antifuse and single B-Antifuse**
**High and Low Temperature Operating Life tests (HTOL/LTOL) performed with RTAX1000S-CG624 devices**
**298 units passed 1,000 hours of HTOL at +125****o****C and 250 hours of LTOL at -55****o****C**
***Two units had CMOS failure due to electrical over-stress ******(non-antifuse related) at 250 hours pull point of HTOL***
***Devices did not go through the Burn-In screening required for QML class Q level devices***

## RTAX-S Qualification Designs

- Design utilization for QBI, EAQ and HSB Reliability Testing
**Qualification designs represent the worst case ****end-use condition**
**User designs have generally less utilization than the above qualification designs**

## Antifuse Usage Statistics

- The EAQ and HSB designs were created to study specific Antifuse types like:
**The Critical K-Antifuse **
**Single S-Antifuse**
**Single B-Antifuse **
- Number of critical antifuses utilized in the various RTAX1000S Reliability Test Vehicles
_**NO**_** antifuse faults have been observed in RTAX1000S-CG624 reliability studies with these designs**

## RTAX-S Production Process Enhancement

**RTAXS**

**Wafer specific XSEM**

**Standard Quality Control Monitor**

**Extended Lot Acceptance (ELA)**

**Standard B, E Flow processing**

**Actel Specific E-test**

**Thermal Runaway Characterization**

**XY Programming**

**New Process Steps**

**Old Process Steps**

## RTAX-S Processes and Procedures (1/2)

- Standard Quality Control Monitor (QCM)
**Programming & functional test using LTPD 30 (8 samples, 0 failures)**
**Design is identical to QBI (targeted for general CMOS/Antifuses)**
**Test is done per assembly build for the RTAX250S**
- Extended Lot Acceptance (ELA)
**Test is done per **_**wafer lot**_** **
**168 hours of burn in at 125 oC with stringent EAQ design**
**Sample size:**
***RTAX250S – 100 units***
***RTAX1000S – 24 units***
***RTAX2000S – 14 units***
**Wafer lot acceptance criteria allows Zero antifuse related failures**
**If any failures or outliers are detected, failure analysis is performed to determine root cause**
- XY Programming
**Wafer number and die location on wafer is now programmed into each unit during wafer sort**
**Silicon Sculptor Programming SW revision also programmed into device at final design programming **

## RTAX-S Processes and Procedures (2/2)

- Wafer-specific cross section inspection (XSEM)
**Two samples per wafer are cross-sectioned ****at antifuses**
**XSEMs are inspected for anomalous antifuse construction**
**Wafers are scrapped if found to be beyond the specification**
**Susceptible wafers are required to be used as ELA samples**
**All the wafers that pass are built for shipments**
- Thermal Runaway Characterization
**This test is required per wafer lot (starting with 2007 fab out lots)**
**2 sample units are programmed with ELA design and characterized at oven temperature of 125****o****C, 130****o****C, and 135****o****C**
**Lots that exhibit thermal run-away phenomena are scrapped**
- Actel E-test
**In addition to wafer foundry provided E-test data, Actel runs additional E-test after wafers arrive**
**Provides more in depth information on antifuse related parameters**

## RTAX-S Reliability FIT Rate

- _NO_ Antifuse faults have been observed to date in any of the reliability testing (QBI, EAQ, ELA, HSB) thus far
- _1.7 Million device hours_ have been accumulated to date
***Refer ***_**[http://www.actel.com/documents/RTAXS_Rel_Test_WP.pdf](http://www.actel.com/documents/RTAXS_Rel_Test_WP.pdf)**__** for details (updated as needed)**_
- Failure rate estimation:  Device FIT = _11.7 __@ Tj = 55 oC_
**Using the chi-square distribution and a minimum upper confidence limit of 60% per JESD74**
_**CMOS**_** Activation Energy:  Ea = 0.7 eV**
**Includes 1 CMOS process related failure**
**The remaining failures were identified as EOS or equipment related**
**FA reports available upon request**

## RTAX-S On-Going Quality and Reliability Improvement

- Process Change Notification through GIDEP Problem Advisory
**SC7-P-06-01 (PCN0608), Elimination of RTAX-S ICCA Current Increase Due to Heavy Ion-Induced Upset**
**SC7-P-06-02 (PCN0606), EDAC Macro modification to correct simultaneous reads and writes occur to a single address.**
**SC7-P-07-02 (PCN0625), to correct routed clock timing under-estimation**
**All issues were associated with software bugs and discovered through internal and customer failure analysis**
**Silicon has remained the same since qualification**
- On-Going Process Improvement After Qualification
**X-Y Programming, Thermal Run-Away Analysis**
**High Frequency SET, High Temperature SEL, Prompt Dose**
**Completed ESD Testing**

## RTAX-S Reliability Summary

- Actel has enhanced its Qualification Procedure to include both MIL-PRF-38535 QML-Q and  Enhanced Antifuse Qualification (EAQ)
- New processes have been implemented to ensure high quality and highly reliable RTAX-S product is shipped
_*NO *_antifuse failures detected with almost 1.7M device-hours of testing which showcases robustness of this technology
- Parts have been baselined in many programs
- Has started to develop QML class V level qualification/certification with the RTAX4000S qualification process

## Planning to Fly RTAX-S

- MUOS

- Advanced EHF

- NPOESS

- Galileo

- Lunar Reconnaissance Orbiter

- James Webb Space Telescope

- Mars Science Lab

- Bepi Colombo

- GOES-R

- GAIA

## New Technology Plans:Space-Flight Flash FPGAs

- Actel continues to develop new technology for Space applications such as Flash based FPGAs
- Unique Flash advantages
**Non-Volatile and Live at Power-Up**
**Reprogrammable**
- RTA3PE (130nm)
**Based on the commercial Flash product line**
**Radiation projections – suitable for LEO / short duration payloads**
**Immune to SEL **
**TID to ~ 15 to 20 Krad, parametric and functional**
**To implement Soft TMR for protection against data SEUs**
**Flight units expected 2008 to 2009**
**Mil-Std-883 qualified**
- RT-G4 (90nm)
**Project founded by DTRA**
**In architecture concept phase**
**Expect flight units 2010 to 2012**
**Target TID to 300 Krad**
**5M to 10M system gates**

## Thank You