# Presentation: 289974

## APDs and Electronics System Design

***Roger Rusack***
***Minnesota***

## Outline

***Review of what we said in the proposal.***
***Proposal from Hamamatsu***
***What is between us and construction.***

## APD Housing Concepts

***We are making ~30,000 modules so the design has to begin with manufacturability.***
***We need to align the APD’s with the fibers - the better we do this the larger the fiber or the smaller the APD.***
***The square pixel structure is not optimized for the two-fiber readout.***
***We should stay within the same surface area of silicon to keep close to the same price.***

## Current thinking:

***We will use an APD array mounted on a PCB using “flip-chip” technology. This provides an alignment of ~10************m to the PCB. Alignment is reduced to aligning the fibers to the PCB.***
***Cooling by thermo-electric coolers to -15******o******C.***
***Readout through very front-end designed by Tom Zimmerman.***
***Front-end readout architecture still under discussion.***

## Proposed APD Layout

***Solder Bumps***

***Apperture ******in PCB for ******fibers.***

***2.3 mm gap***

***PCB substrate***

***APD pixels***

***Hole for Fiber ******connector***

## Basic Module concept.

- TE Cooler

- PCB

- ASIC

- ADC

- FPGA

- APD

- FiberConnector

- Support Ring

- Thermally isolated volume.

- Air Gap

- Thermally Conductive Mousse

***Other options are being considered see talk by Stuart Mufson***

***APD, ASICs and FPGA mounted onto PCB.***
***Casing made of injection molded components used to align fiber connector and insulate/isolate APD. ***

***Present in one option***

***FPGA for signal processing, IO and slow control.***

## Status.

***Tests at Hamamatsu:***
**Flip chip method tested and Hamamatsu is happy with the result - We have not seen the detailed results.**
**Minimum distance to border is understood.**
**APD layout with 10 pF matched to fibers defined.**
***Quote from Hamamatsu:***
**NRE for wafer design and TE cooler attachment and **
**20 prototypes in aro. 6 months $10,000 ea.**
**40 prototypes in same time scale $6,250 ea. **

***Important point is that schedule is only 6 months.***

## Front-End Readout options.

***Two options have been considered for the design of the front-end  readout the APD. ***
***Harvard design – see talk by John Oliver later.***
***Tom Zimmerman has designed a version of the front-end ASIC.***

## _x0010_Basic Concept

***Optimize design for low-noise readout during the spill.***
**32-channels to match the number of channels in a module.**
**Track and hold amplifier which is sampled every 500 nsec for 30 microseconds to cover spill. Samples are stored in a 64 deep switched capacitor array (64 × 32).**
_**After**_** spill begin conversion process.**
**32 channels compared with linear ramp. 10-bit resolution. **
**Covert next ramp and send out data.**
**Repeat until all channels digitized.**
**Digitize difference between odd neighbor cells OR digitize each cell and subtract digitally.**

## Main Operation – Spill Mode

**Main Operation – Spill Mode**

***64 deep capacitor array***

- 10

***32 input channels***

***Collect signal in SCA***

***Digitize Later***

***Linear Ramp ***
***Generator***

- 10

***Shift Register***

***Charge sensitive pre-amp***

***Comparitor***

***Latch***

***Readout strobe***

***Read Amplifier***

## Alternative Operation – Fast Digitization Mode.	

**Alternative Operation – Fast Digitization Mode.****	**

***Variants on the standard operation are included in the design.***
**Direct in to latch.**
**Non-linear ramp. **
**Complete digitization in 400 nsec. **

***Comparitor***

***Latch***

***Non-linear ramp***

***Read Amplifier***

## Status

***Design complete.***
***Full simulations complete. Calculated noise level with 10 pf and 250 nsec shaping is 150 electrons. Reality: hope for expect ~200. ***
***Next step layout and produce short run in 0.25 ************process. ***
***Plan is to submit this with other readout options.***

## Alternative Readout

***Alternative readout architecture which has same operation in both spill and supernova detection modes.***

***See talk by John Oliver later.***

## Development Schedule

***To go from initial design concepts to launch production of 30,000 APD modules we need to:***
**Design front-end readout ASIC.**
**Design front-end board with all ancillary circuits.**
**Prototype and test APD modules. **
**Design, make and qualify cooling system.**
**Build automated module testers for production.**
***We need final versions of the prototype in quantities of ~10,000 channels by Feb 2007.***
***We need to start production of modules by Oct 2008.***
***Installation May 2009.***

## Immediate Tasks	

***APD + TE cooler design - Hamamatsu    6 Months***
***Front-end electronics***
**ASIC design, layout and fabrication - FNAL + Harvard.**
**PCB design layout and fabrication - FNAL.**
**400 V bias supply - Cockroft Walton or distributed line?**
**TE cooler and controller. **
***Test modules.***
***Revisions.***
***Module tester.***

## Short Term Schedule

***ASIC ******development***

***Design******Revision***

***Test with prototype***

## Long Term Schedule

***Start mass ******production******Jan/09***

***Test with prototype***

## Other Major Issues

***Cooling TE cooler with water or air?***
***Beam signal and clock distribution.***
***Low Voltage network - Could be extensive.***
***Trigger and DAQ***
**Need to have an agreed set of specifications.**

***To be addressed in the coming months.***

## Summary

***APD structure***
**Some progress with APD design. Optimized for 32 channel modularity.**
***ASIC design of one version complete. Designed to meet beam and SN detector requirements.***
***Schedule***
**There is much to be done on a short timescale.**