# Presentation: 193968

## DØ Silicon Microstrip Tracker for runIIa

**Eric Kajfasz (CPPMarseille) **
**DAQ shifter training, Feb 18, 2003**

** ****Design**
** ****Production**
** ****Assembly**
** ****Readout**
** ****Installation**
** ****Commissioning/Operation**

- DØSMT_** **_

## The DØ Detector

- E. Kajfasz

- DAQ training, 02/18/03

## RunIIa SMT Design

- (2T)

- E. Kajfasz

- DAQ training, 02/18/03

## SVXIIe chip

**1.2 um CMOS amplifier/analog delay/ADC chip fabricated in the UTMC rad hard process**
**Designed by LBL/FNAL**
**Some features:**
**128 channels**
**32 cell pipeline/channel**
**8-bit Wilkinson ADCs**
**Sparsification**
**53 MHz readout**
**106 MHz digitization**
**6.4 x 9.7 mm2**
**~ 85,000 transistors**
**noise: 490e + 50e/pF**

- E. Kajfasz

- DAQ training, 02/18/03

## SVXIIe chip

**Externally programmed to achieve optimal performance for 132 or 396ns beam crossings and detector capacitances from 10 to 35pF (preamp bandwidth adjustment)**
**Chip noise****490e + 50e/pF****i.e. ~1200e ENC for C=15pF****1 MIP => ~4fC => ~25,000e****=> S/N ~ 20**
**Max delay in analog pipeline:****32 x 132ns = 4.2us**

- E. Kajfasz

- DAQ training, 02/18/03

## High Density Interconnect

**Kapton based flex circuits with 0.2 mm pitch for chip mounting**
**Laminated to Beryllium substrate and glued to Silicon sensor**
**Connects Sensor to SVXII chips and SVXII chips to flex circuit via wire bonds****(Al wedge bonding)**
**Connects to a Low Mass Cable which carries the signals out of the interaction region**

- E. Kajfasz

- DAQ training, 02/18/03

## Production: ladder design

- Be substrate

- wire bonds

- Silicon

- support rails

- Be support (Bulkhead)
- including cooling channel

- vertical scale

- E. Kajfasz

- DAQ training, 02/18/03

## L3

- Family of D0SMT
- Detector types
- (all AC coupled)

- L6

- L6

- L9

- L9

- F6

- F8

- H6

- n-side

- n-side

- n-side

- p-side

- p-side

- p-side

- 144 DSDM

- 72 Single Sided
- 50 um pitch

- 216 DS 2o stereo

- 144 DS +/- 15o stereo

- 50 (p)/153(n) um

- 50 (p)/60(n) um

- 50 (p)/62.5(n) um

- 92x2 SS +/- 7.5o

- Elma-Russia

- 70% Micron-UK, 30% Eurysis-France

- Micron-UK

- Micron-UK

- Micron-UK

- E. Kajfasz

- DAQ training, 02/18/03

## RunIIa SMT Design

**RunIIa SMT Design**

- 6 Barrels

- 12 F-Disks

- 4 H-Disks

- 6192 R/O chips = 792,576 channels
-         > 1.5 million wire bonds

- 8 layers
- 72 ladders
- 12 cm long

- Layers 1,2,5,6: L3 or L6
- Layers 3,4,7,8: L9

**Barrel**

**F-Disk**

**H-Disk**

- 12 F-wedges

- 24 H-wedges

- North

- South
- 1/2-cylinder

- E. Kajfasz

- DAQ training, 02/18/03

## Production: V-max

- E. Kajfasz

- DAQ training, 02/18/03

## Assembly: Barrel assembly

**Ladders placed on barrels using an insertion fixture**

**Internal alignment done using a CMM****(touch probe)**

- E. Kajfasz

- DAQ training, 02/18/03

## Assembly: Barrel-Fdisk mating

- E. Kajfasz

- DAQ training, 02/18/03

## Assembly: End Fdisks mating

- E. Kajfasz

- DAQ training, 02/18/03

## Assembly: Hdisk

- E. Kajfasz

- DAQ training, 02/18/03

## Assembly: Radiation monitors

- E. Kajfasz

- DAQ training, 02/18/03

## Assembly: 1/2-cylinder

- South Half Cylinder

- E. Kajfasz

- DAQ training, 02/18/03

## Assembly: 1/2-cylinder

- HDI connection to low-mass cable

- E. Kajfasz

- DAQ training, 02/18/03

## Installation

**Cylinder installation was completed on 12/20/00**
**A 1/2-cylinder of 3 barrels and 6 F disks was inserted into each end of the CFT bore**
**H Disk installation was completed on 2/6/01**
**The cabling (~15,000 connections) and electronics installation was completed in May 2001**

- Fiber Tracker

- Low Mass Cables

- High Mass
- Cables

- SMT

- Interface Boards

- Calorimeter

- E. Kajfasz

- DAQ training, 02/18/03

## 80/3M+CLK cables

- Adapter card

- Low-mass+CLK cables

- E. Kajfasz

- DAQ training, 02/18/03

## SE

- B5

- B4

- B6

- B2

- B3

- B1

- NE1

- NE0

- NW0

- NW1

- SW1

- NW

- NE

- SW

- INTERFACE
- BOARD
- CRATES

- ADAPTER
- CARDS

- 80/3M
- CABLE

- L.M.
- CABLE

- SE0

- 120 ladders
- 72 F-wedges
- 48 H-wedges

- SE1

- SW0

- H2
- H1

- H4
- H3

- Central
- Calo

- CFT

- F6
- F5
- F4
- F3
- F2
- F1

- F12
- F11
- F10
- F9
- F8
- F7

- Calo North End Cap

- Calo South End Cap

- Muon wall

- Muon wall

- Muon wall

- Muon wall

- East Cathedral

- West Cathedral

- E. Kajfasz

- DAQ training, 02/18/03

## Readout Electronics (Cathedrals)

**Interface Boards**
**8 crates (144 boards) located inside the cathedrals**
**Regenerates signals**
**SVX monitoring and power management**
**Bias voltage distribution**

- E. Kajfasz

- DAQ training, 02/18/03

## Readout Electronics (Platform)

**SEQuencers**
**6 crates (120 boards) located on the detector platform**
**Use SVX control lines to actuate acquisition, digitization and readout**
**Convert SVX data to optical signals**

- E. Kajfasz

- DAQ training, 02/18/03

## Readout Electronics (MCH2)

**VRBs (Readout Buffers)**
**12 crates (120 boards) located in MCH2**
**Data buffer pending L2 trigger decision**

**VRBs (Readout Buffers)**
**Input @ 5-10 kHz L1 accept rate ~ ****50 Mb/s/channel**
**Output @ 1 kHz L2 accept rate ~ ****50 Mb/s**

- E. Kajfasz

- DAQ training, 02/18/03

## HV distribution

- HV Modules
- (MCH2)

- Fanout Boxes
- (MCH2)

- Breakout Boxes
- (Platform)

- E. Kajfasz

- DAQ training, 02/18/03

## MCH3: 1553 Controllers

- E. Kajfasz

- DAQ training, 02/18/03

## Cathedral

**~19’-30’ High **
**Mass Cable     **
**(3M/80 conductor)**

**Serial Command Link**

**Cathedral**

**Interface**
** ****Board**
**Crates**
**(8x18)**

**8’ Low Mass Cables**

**3/6/8/9 Chip HDI**

**Sensor**

**CLKs**

**Horse Shoe**

**3/6/8/9 Chip HDI**

**Sensor**

**Adaptor **
**card**

**25’ High Mass Cable (3M/50 conductor)**

**CLKs**

- I
- B

**MCH2**

**V****R****B****C**

**S**
**B**
**C**

**V****R****B**

**Monitoring**
**SDAQ**

**PDAQ  (L3)**

**VRB**
**Crates**
**(12x10)**

**Platform**

**SEQ**

**SEQ**
**Controller**

**Optical Link**
**1Gb/s **

**Sequencer **
**Crates**
** ****(6x20)**

**VTM**

**Around Iteraction Region**

**CLKs**

**MCH3**

**PowerPCs and Single Board Computers are accessed thru Ethernet**

**MCH2**

**HV **
**Crates**
** ****(8x6+2x4)**

**Cathedral**

**Fuse**
**Panel**

**Bulk LV**
**Power Supplies**

**HV**
**fanout**
**1=>4**

**HV**
**breakout**
**box**

**VME**
**Crates**
**(4x3)**

**25 twisted **
**pair cables**

**17 twisted **
**pair cables**

**HV**

**LV**

**I,V,T Monitoring**

- E. Kajfasz

- DAQ training, 02/18/03

## Cooling system

**30% glycol + water at –10 ****o****C (=> detectors between –5 and 0 ****o****C)**
**The tracking volume is purged with dry air to prevent condensation**

- E. Kajfasz

- DAQ training, 02/18/03

## Operations: LV

**Operations: LV**

- NW

- NE

- SW

- SE

- 0

- 1

- 0

- 1

**Color coding**
**orange: OFF**
**green: OK**
**purple: idvdd a bit too high**
**red: idvdd too high**
**pink: dead**
**light blue: for HV only**
**red/black: tripped**
**gray: not used**

- E. Kajfasz

- DAQ training, 02/18/03

## HV Global GUI

- OFF

- ON

- E. Kajfasz

- DAQ training, 02/18/03

## HV channel GUI

- E. Kajfasz

- DAQ training, 02/18/03

## HV Alarms

- E. Kajfasz

- DAQ training, 02/18/03

## Calibrations

**Calibrations**

**SMT pedestal, noise and gain ****measurements are taken using SDAQ. **
**Pedestal and noise measurements are used to calculate the threshold per chip to be used in sparse read out**

- E. Kajfasz

- DAQ training, 02/18/03

## SMT Online Monitoring

**within the SMT shifter’s realm:**
**smt_event_display**
**displays strip level information**
**smt_examine**
**displays strip and cluster level information**
**online_monitoring**
**monitors and displays strip level information**
**not directly under SMT shifter’s control:**
**vertex_examine**
**cft_examine**
**physics_examine ...**

- E. Kajfasz

- DAQ training, 02/18/03

## smt_event_display

- E. Kajfasz

- DAQ training, 02/18/03

## smt_event_display

**a busier**
**event**

- E. Kajfasz

- DAQ training, 02/18/03

## smt_event_display

- problematic
- ladder

- E. Kajfasz

- DAQ training, 02/18/03

## smt_examine

**strip level information**
**per ladder/wedge:**
**average pulse height**
**sigma of pulse height**
**occupancy vs event**
**number of fired strips**
**fired strips**
**per chip:**
**pulse height vs event number**
**cluster level information**
**cluster charge**
**first strip in cluster**
**cluster width**
**cluster charge vs tick number**

- E. Kajfasz

- DAQ training, 02/18/03

## smt_examine

- E. Kajfasz

- DAQ training, 02/18/03

## smt_examine

**occupancy_gui**

- E. Kajfasz

- DAQ training, 02/18/03

## SMT Online Monitoring

**monitoring processes:**
**run in PPC in VRB crates**
**send data to server on d0ol28 which makes histograms available through web pages**
**can send significant events to the SES**
**what is monitored:**
**strip/chips signals**
**strip/chips hit counts**
**occupancies**
**raw data structure errors**
**what can trigger Alarms:**
**HDIs/chips never reading out**
**HDI occupancies**

- E. Kajfasz

- DAQ training, 02/18/03

## SMT Online Monitoring

- E. Kajfasz

- DAQ training, 02/18/03

## SMT Online Monitoring

- E. Kajfasz

- DAQ training, 02/18/03

## SMT Online Monitoring

- E. Kajfasz

- DAQ training, 02/18/03

## SMT Online Monitoring: what we need ...

**smt_examine:**
**include tick and turn checks**
**include histograms to better study L1busy**
**include global tracking and AA SMT stand alone tracking ****(including disks)**
**phi and z track distributions**
**clusters associated to tracks (charge, position, width)**
**detector efficiencies**
**automatize distribution checks**
**migrate from histoscope to root**
**online_monitoring**
**get a Visa for Maciej**
**improve the categorization of R/O errors**
**other tools:**
**raw data dump and check examine based tool**
**at L3:**
**include tick and turn checks**

- E. Kajfasz

- DAQ training, 02/18/03

## Operations issues: Pedestal shifts

- 3 superbunches
- of 12 bunches

- tick number

**pedestals seem to be different at the beginning of each superbunch **
**Investigating ...**

- E. Kajfasz

- DAQ training, 02/18/03

## Operations issues: F-Wedges noise (1)

- F11-1-2

**seems to affect only the p-side of a fraction of the Micron sensors**
**does not seem to depend on the biasing scheme**
**does not seem to depend on temperature**
**still investigating ...**

- E. Kajfasz

- DAQ training, 02/18/03

## Operation issues: F-Wedges noise (2)

| # of wedges
in disk | w/ > 10% noisy strips |  |  |  | w/ > 20% noisy strips |  |  |  | w/ > 30% noisy strips |  |  |  |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
|  | P-side |  |  | N-side | P-side |  |  | N-side | P-side |  |  | N-side |
| threshold (ADC) | 4 | 6 | 10 | 4 | 4 | 6 | 10 | 4 | 4 | 6 | 10 | 4 |
| 01 (Micron) | 6  | 4 | 1 | 3 | 2 | 2 | 1 | 1 | 1 | 1 | 0 | 0 |
| 02 (Micron) | 4 | 1 | 0 | 1 | 2 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
| 03 (Eurysis) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 04 (Micron) | 5 | 4 | 2 | 2 | 4 | 3 | 1 | 1 | 3 | 2 | 1 | 1 |
| 05 (Eurysis) | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 06 (Micron) | 7 | 5 | 5 | 7 | 6 | 5 | 3 | 4 | 4 | 3 | 2 | 4 |
| 07 (Micron) | 3 | 2 | 2 | 1 | 2 | 2 | 1 | 0 | 1 | 1 | 0 | 0 |
| 08 (Eurysis) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 09 (Micron) | 4 | 4 | 3 | 2 | 4 | 3 | 1 | 1 | 2 | 2 | 0 | 1 |
| 10 (Eurysis) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 11 (Micron) | 5 | 3 | 3 | 4 | 3 | 2 | 0 | 1 | 2 | 1 | 0 | 0 |
| 12 (Micron) | 6 | 3 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | 2 | 0 | 0 |
| TOTAL (144) | 40 | 26 | 18 | 23 | 25 | 19 | 9 | 10 | 16 | 12 | 3 | 7 |

- E. Kajfasz

- DAQ training, 02/18/03

## Bias currents

- wi(l)de range of behavior...

- current (uA)

- most of this is not bulk current.

- E. Kajfasz

- DAQ training, 02/18/03