# Presentation: 411140

## V & V @ AMD: Ensuring a Solid HPC Foundation and Data Confidence from Core to Cache and Beyond . . .  

- Seth Prejean
- April 26, 2007

## Presentation Overview

- Validation and Verification
- Data Protection
- Design Verification
- Product Validation
- Looking Forward
- Summary

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## V & V @ AMD

- Verification (Pre-Silicon)
- Ensure logical functionality of the design
- Simulation environment
- RTL
- Process Modeling
- Thermal CFD Modeling
- Validation (Post-Silicon)
- Ensure the product meets design specifications
- System environment
- Automated Test Equipment
- System Level Test
- Burn In

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## Confidence In Simulations

- How do we provide confidence in predictive simulations ?
- We must ensure data is reliable within our design
- V & V can ensure data will be processed correctly
- Data must be protected from corruption
- Prevent conditions for data corruption
- Unavoidable corruption is detected and in some cases corrected

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## Reliable Data

- What affects data reliability in a complex microprocessor?
- Soft Errors
- Cosmic upsets
- Alpha particle strikes
- Temperature
- Timing margin
- Test temperature coverage
- Power supply Noise
- Glitches on power supplies
- Power Grid Design

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## Reliable Data

- Soft Errors
- Scaling reduces Qcrit while also reducing collection volume
- Increase in number of storage nodes on a device
- Multiple cores impact total device FIT
- Mitigation
- Protect data with ECC and parity
- Report and repair errors with Machine Check Architecture
- Control and monitor process materials to ensure they are alpha emission free

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## Reliable Data

- Classifying Soft Fails

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## Reliable Data

- Soft Errors
- Taxonomy of Systems Effects from Soft Errors

- source: Dean Liberty; AMD RAS architect

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## Reliable Data

- On Die Thermals
- Scaling increases power density
- Hotspot detection is important
- Device Thermal gradients in the silicon can affect timing and data reliability
- Thermal runaway
-  SIDD(Temp(SIDD)) – feedback between static leakage and temperature can induce self heating
- Product Specifications ensure that these problems can be mitigated

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## Reliable Data

- On Die Thermals
- Test Temperatures ensure thermal coverage
- Understanding thermal profiles across device operation is critical
- Detection
- Diodes measure device temperature
- Distributed sensor networks can detect hot spots
- Prevention
- HTC Hardware Thermal Control
- Reduce frequency / voltage
- Thermal Trip reset mechanism

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## Data Protection

- Hammer Family Data Protection
- Prior history establishes protection structure and requirements; New design work extends coverage
- ECC and Parity
- L1 Data Cache ECC protected
- L2 Cache and Cache Tags ECC protected
- DRAM ECC Protected (with Chipkil ECC support)
- L1 Instruction Cache TLBs and Tags Parity Protected
- Read only data that system can recover Parity Protected

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## Data Protection

- Hammer Family Data Protection continues ...
- Cache Scrubbers
- Run in background checking and repairing data
- Address range and scrub rate are configurable
- Machine Check Architecture
- Reports failures and failure results
- Enables hardware and software error containment
- Physical bit Layout Interleaving
- ECC is SECDED
- Interleaving eliminated possibility of double or N-bit errors within same logical word

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## Design Verification	

- RTL Design Verification of Data Protection
- Soft error injection scripts
- ECC detection and correction
- Machine Check Architecture verification
- Error reporting mechanism works
- Valid data is reported to fail data registers

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## Design Verification	

- Thermal Design Verification
- Design CaC simulation for thermal density maps
- Thermal modeling to predict silicon device temperatures and gradients
- Max Power Test Pattern
- Worst case power dissipation in a real world functional state
- Useful for
- Sensor placement
- Timing margin reliability in hot spots
- Thermally aware design

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## Product Validation

- Product DFT features enable validation of implemented reliability features
- Machine Check Architecture / Parity / ECC
- Validate error reporting registers
- MCA functionality
- Inject bit flips during device operation

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## Product Validation

- Cosmic Soft Error Rates
- Accelerated Soft Error Rate measurement
- Los Alamos Neutron beam facility
- Memory and Logic Flop/Latch FIT rates measured
- System Level OS FIT rate measurement
- Architectural Relevancy Factor
- SER FIT rates are calculated at the product level

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## Product Validation

- Die Level Thermal Imaging
- System level device thermal mapping across different applications
- Thermal sensor validation/correlation
- On Die thermal gradient measurement

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## Looking Forward

- Multi-core products increase the challenge of ensuring reliable data while offering improved performance and data throughput with same quality.
- Logic to dominate Soft Error FIT rates
- SRAM FIT rates leveling off and well understood
- SRAM data reliability mitigation is common practice
- Logic data reliability is a new focus of development and will require checkpoint and logic ECC/parity mechanisms
- Design tradeoffs
- Data protection such as ECC and parity or other logic protection schemes impact performance and increase chip area

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## Summary

- Challenges to ensure Data Reliability increase as semiconductor technology advances.
- Simulation and modeling are key to addressing issues and ensuring confidence in our processors.
- Validation confirms the effectiveness of measures taken to ensure product reliability.
- Legacy techniques and customer requirements/expectations drive implementation of reliability features.

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## Thanks to contributions taken from the work of:
	Dean Liberty and Fred Weber

- AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Other names used in this presentation are for identification purposes only and may be trademarks of their respective owners.©2006 Advanced Micro Devices, Inc. All rights reserved.

- Thanks to contributions taken from the work of:
- 	Dean Liberty and Fred Weber

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