# Presentation: 534104

## CDF Run IIb Trigger & Data Acquisition Upgrades

- Peter Wilson
- Fermilab
- for the CDF Collaboration
- July 20, 2004

## Run IIb Trigger/DAQ Upgrades

_***The upgrades:***_
***1.3.1****** ******TDC replacement***
***Central tracker readout***
***1.3.2****** ******Level 2 trigger***
***Level 2 decision crate ***
***1.3.3****** ******(1.3.11)****** ******XFT upgrade***
***Level 1 track trigger***
***1.3.4****** ******Event builder***
***1.3.5****** ******Level 3 Processor****** ***
***Data acquisition***
***1.3.6****** ******SVT ***
***Level 2 silicon vertex trigger***
***1.3.7 Silicon DAQ***

_***Outline:***_
***Motivation***
***Run IIb physics goals***
***Trigger strategies***
***Upgrade Strategy and process***
***Specific projects***
***Status***
***New Scope****** ***
***Schedule***
***Cost***
***Conclusion***

## Trigger/DAQ Management

## Motivation

- The DAQ/Trigger upgrades presented here were originally driven by the Run IIb trigger and data acquisition needs to carry out our high-pT physics program.  However, the need to maintain parts of the B-physics program (eg Bs mixing)  in   Run IIb pushes us in the same directions.
- At the baselining our understanding was based upon
**Run IIa data: ****L**** ******** 2x10****31 ****cm****-2**** s****-1****, ****<1 interaction per crossing **
**Run I data: ****L**** ~2x10****31 ****cm****-2**** s****-1****, ~3 interaction per crossing**
- We are extrapolating to Run IIb
**L**** = 3x10****32 ****cm****-2**** s****-1****,**** ~8 interaction per crossing**
**Due to significant uncertainties in extrapolation, and a desire to be prepared for success, we have evaluated the bandwidth needs for:                                                                             ****L**** = 4x10****32 ****cm****-2**** s****-1**** , ****~10**** ****interaction per crossing**
- Now can make better extrapolations based on:
**Run IIa data: ****L**** ******** 1x10****32 ****cm****-2**** s****-1****, ****~2.5 interaction per crossing**

## Trigger Strategy

- Focus on Higgs & high *p**T* searches
- Know that triggers needed for these modes will allow for many beyond Standard Model searches
- Maintain B program to highest possible luminosity.
- ~1/2 data accumulated with Linst < 1⁄2 Lpeak
- General requirements:
- High pT electrons and muons
- Associated *WH*/*ZH* modes, also *t**Wb*
- Missing ET triggers
***ZH***** with *****Z ************ ********* , modes with taus
*b*-jet triggers
***H ************ bb*** , *b*-jets tagged by displaced tracks
- Calibration triggers
***Z ************ bb*****, *****J/************ ************ ************+***************, photons
- Hadronic B Triggers
***B ************ h******+******h******-***, ***B******s****** ************ ************, D******s***********, two displaced tracks

## CDF Data Acquisition System

- Level 1 trigger
- pipelined and “deadtimeless”
- fully synchronous
- designed for 132ns operation
- on L1A, write data to 1 of 4 local L2 buffers
- Level 2 trigger
- asynchronous
- L1 + supplemental info
- Level 3 trigger
- full detector readout
- PC farm runs reconstruction
- output to mass storage

## CDF Run II Trigger System

- Level 1 trigger
- tracking
- calorimeter: jets & electrons
- muons
- Level 2 trigger
- L1 information (tracks, )
- calorimeter clustering for jets and electrons
- calorimeter shower max
- silicon information
- algorithms run in L2 processor
- Level 3 trigger
- full detector readout
- “offline” processing

**Detector Readout path**

## Run IIb Trigger Table (High pT part)

- From Sep. 2002 DOE Review: extrapolated from L~2x1031 cm-2 s-1

## DAQ/Trigger SpecificationRun IIa vs IIb

- Run IIa L1A not achieved due to higher than specified Silicon Readout  + L2 Trigger execution times
- Assume ~5% from readout and ~5% from L2 processing
- Reminder: IIb trigger & bandwidth rates estimated based upon Run IIa, significant underestimate possible (assumes linear growth in fake contribution)

## Trigger/DAQ Upgrades          for Run IIb

- Need to Maintain or increase bandwidth
- Luminosity   Rate (=L)
- Luminosity  inter/x-ing                        Complexity (and fakes)                        Event Size, Exec. time and trigger
- All physics to tape
- L1 Bandwidth (output to L2)
- XFT Purity trigger(L1, L2)
- SVT, L2 L2 Exec. t L1 Bandwidth
- L2 Bandwidth (output to L3)
- COT TDC Readout rate
- Level 3 Processing  L3 Exec. t
- Event Builder Readout rate
- L3 Bandwidth (output to tape)
- CSL Tape rate (not under IIb project)

## General DAQ Upgrade Considerations

- Upgrades “targeted” to specific needs
*e.g.* COT TDCs replaced, but COT front-end (ASDQ, repeaters) unmodified
- Retain existing infrastructure
- Cables, crates unchanged
- I/O protocols, timings retained
- Upgrades plug compatible with existing components and where possible designed for parasitic commissioning
- Use IIa knowledge & experience
- Upstream/downstream components unchanged
- Can install each system when ready with minimal interruption to operations
- Minimize impact of commissioning on on-going data taking

## DAQ/Trigger Upgrade Process

- Each subproject within the DAQ/Trigger has followed/will follow a similar path (not all steps apply in each case)
- Conceptual design
- Simulation/Tests of conceptual design
- Internal Review of conceptual design
- Technical specification
- Construct/buy prototype/preproduction hardware and test
- Readiness review for production purchase
- Checkout and system test of production hardware
- Installation readiness review
- Each subproject also holds weekly internal project meetings for technical and management discussions

## Recent Reviews and Workshops

- Over the past few months several projects have been through reviews and workshops in this process.  Since upgrades will have an impact on operations, these workshops and reviews planned in coordination with CDF Operations Department.
- 1.3.1 TDC
- (Pre)Production Readiness Review - May 21, 2004
- 1.3.2 L2 Decision
- Production Readiness Review – Nov 7, 2003
- 1.3.3 (1.3.11) XFT
- Scope Review – May 25, 2004
- Scope and Project Plan Review – June 25, 2004
- 1.3.4 Event Builder
- Production readiness review – April 2004
- 1.3.6 SVT
- Workshops – April 28, June 14, 2004
- Scope and Plan Review – June 29, 2004

## COT TDC Upgrade

- Central Outer Tracker (COT)
- central drift chamber
_**COT readout path:**_
-  chamberASDQ  microcoax  repeater board flat cable TDC
- ASDQ = amplifier shaper discriminator with charge-encoding
- TDC = time-to-digital conversion
- Total of 315 9U VME boards (96 channels each) to instrument full COT

## COT Data Size

- Occupancy is higher than was expected before start of Run II
- Extrapolation (linear) from low luminosity (<2x1031cm-2s-1) to 4x1032cm-2s-1 predicted:
- 62.5 k hits/event for whole chamber or average of about 2 hits/wire/event
- Average of about 4 hits/wire in SL1
- Data size of 250 kB/event with   4 bytes/hit (current usage)
- Average data rate of 14MB/s in each crate (assuming 1.1kHz L2A rate)

- Occupancy confirmed by recent higher luminosity operation

## Run IIa TDC Limitations

- On-board processing (DSP) Time grows with # of hits
- t = 1200s/event  for SL1 (4 hits/ch) at 4x1032 cm-2s-1
- Pipelined w/readout
- VME Readout
- 16 TDCs per crate
- Read sequentially by                                                                             one block transfer                                                                                   (~14MB/s)
- VME to Event Builder
- TRACER TAXIVRB                                                                                link limited to 12MB/s
- 2002 Internal review                                                       recommended                                                                           pursuing replacement

- At time of  Sep. 2002 DOE Review

## Run IIb TDC Specifications

- Backward compatible with existing system
- No change to COT front-end, cables or calibration
- No change to track trigger (XFT) interface
- Accept CDF specific signals from CDF_CLOCK/TRACER
- Must handle the following rates
- 50kHz L1A, 1.1kHz L2A
- Perform hit finding for track trigger
- “TDC Specifications” document on web site provides details

## Run IIb TDC Design

**DC Power **
**convertors**

**Input**
**Connectors **
**And**
**LVDS **
**Repeaters**

**840MHz Diff LVDS inputs**
**TDC: Serial to 10bit parallel conversion (1.2ns/bit)**
**L1/L2 Buffering, hit processing + Readout (CBLT)**
**XFT Hit Generation**

**Trigger**
**Output **
**Drivers**
**(to XFT)**

**CDF**
**Clock and**
**Control**
**Interface**

**VME Interface**

**Altera Stratix FPGAs**
**(48chan/chip)**

## Block Diagram of a TDC Channel

- 48 Copies in each chip

## New TDC System Design

- Addresses on-board processing deadtime
-  Process 96 channels in parallel
- <10sec/event independent of occupancy (up to 7 hit/channel)
- Addresses VME Readout bandwidth
- One Chained Block Transfer (CBLT) per crate  lower overhead
- Compressed data size: 4 bytes/hit  56 bytes + 2 bytes/hit. (14kB/crate/event  8 kB/crate/event for 4x1032cm-2s-1 )
- Addresses TRACER  Event Builder (EVB) bandwidth
- Gigabit Ethernet from crate CPU (Motorola 5500) to LINUX PC (Virtual VRB).  Virtual VRB interfaces via gigabit Ethernet to upgraded EVB.
- Independent of new TDC board, can install/commission separately
- Design exclusive to COT system, reduces constraints
- Run IIa TDC will continue to work well for low occupancy systems (muons, hadron timing, CLC)

## Status of Run IIb TDC

- Additional Manpower this year
- FNAL EE and Comp Prof on testing
- Duke physicists on installation/commissioning
- Four Prototype boards
- Delivered Feb 2004
- Only needed 1 “blue” wire modification to make them work
- Timing Performance meets or exceeds specification
- Leading edge stability for 24 channels (dominated by ASDQ input variation)
- Slope = (0.9938+/-0.0013 cnts)/1.2ns
- Final measurements in progress
- A few issues with firmware for XFT outputs
- Can be resolved within firmware
- Measured readout rate with CBLT – achieved 17MB/s

## May 2004 TDC              Readiness Review

- Charge:
- Evaluate Run IIb TDC performance, plans for testing, Production, Installation
- Also evaluate status and ultimate performance of Run IIa  TDC
- Recommendations for IIb TDC design
- Proceed with PreProduction ASAP – in progress
- Complete tests of prototype boards in parallel – in progress
- More testing with XFT, DAQ, full crate and COT – modified plans

## Progress on Run IIa TDC

- New version of DSP code in                                                   use for several months is                                                           much faster:
- Was 1270s for 4 hits/channel
- Now 740s for 4 hits/channel
- Demonstrated that VME                                                           readout is slower than DSP
- Event size is limitation
- Review committee recommendations for Run IIa TDCs
- Adopt more compact IIb data format (~50% smaller) – In progress
- Recommend understanding the ultimate performance of the Michigan TDCs in a timely manner  - in progress
- Plan:
- 07/04 Run IIa TDC Performance Workshop (next week)
- 09/04 Run IIa TDC Performance Review

- Readout
- DSP Processing
- For high luminosity run (COT11)

## Run IIb TDC Progress

- July 2003 	Design Review
- Feb 2004 	First Prototype Board Ready for Testing
- May 2004 	(Pre)Production Readiness Review
- June 2004 Order PreProduction Boards
- Oct 2004 	Full crate test and tests with DAQ
- Nov 2004 	Test Full crate w/COT&DAQ (shutdown)
- Dec 2004 	Production Readiness Review					First TDC Tester Card Assembled
- Mar 2005 	TDC Production Checkout Begins
- June 2005 Installation Readiness Review
- July 2005 	TDC Production Checkout completed
- Project Milestones

## L2 Decision Crate Upgrade

- Level 2 trigger decision based on information from:
- L1 trigger components
- tracks, muons, missing ET
- Jet clusters, EM clusters
- central strip chambers
- silicon
- Information brought together and fed to processor(s) in the L2 decision crate
- L2 decision based upon trigger primitives
- high rate (up to 50kHz) in, must be fast

## Run IIa Level 2 Decision Crate

- 6 flavors of interface board
- (XTRP,SVT), L1, ISO, MUON, CES, Cluster
- each uses different input format, different board designs
- 1 board with Alpha processor for L2 processing/decision
- system designed to run with 4 Alphas
- Data input with custom bus (MagicBus)
- Diversity makes system challenging to test & maintain
- DEC  processors obsolete
- Did not achieve design execution time
- CDF internal review                                                          recommended replacing                                                        Alphas for Run IIb
- Upgrade with PULSAR board                                                           as universal interface

## Pulsar (Pulser And Recorder) Design

***   ***

**Mezzanine slots**

**AUX card**

**Pulsar**

- Custom
- Mezzanine

**Bottom view**

**S-LINK**
**PCI**
**Interface **
**To PC**

**Works**
**up to**
**100MHz**

**Top view**

- Pulsar (Pulser And Recorder) Design

**Three ALTERA APEX 20K400 FPGAs**

- I/O Mezzanine cards for:
-  S-LINK (CERN/LHC)
-  Hotlink
-  TAXI
-  to be specified

*Design philosophy: *
* **Modular - interface with any link format*
* **Self-testable *

## Pulsar based L2 decision

**               **

- Commissioning strategy:
- Use Pulsar Tx  Rx in teststand
- Split all input signals to Run IIa system, run parasitically with detector and beam

***Pulsar based L2 decision***

**Pulsar pre-processors**

**Designed for up to **
**Four PCs in parallel**

## Pulsars in Action

**Two crate teststand in B0**
**With transmitter boards and receiver/interface boards**

**Run IIb L2 Decision (Pulsar) crate**
**In CDF Trigger Room**

## L2 Decision Processing time Measurements

- PC with 2.4GHz AMD Opteron (64bit) Processor fed by SLINK from Pulsar system

**Level 2 Trigger algorithms run on real data in Run IIa system compared to Run IIb PC**
**Complete time including loading over S-Link/PCI and returning result <10********s**

## L2 Decision Progress

- Sept 2003 Pulsar PreProduction Readiness Review
- Dec 2003 Pulsar PreProduction Complete
- Nov 2003 Pulsar Production Readiness Review
- May 2004 Pulsar Production Complete
- June 2004 Core Firmware Complete
- July 2004 Core Software Complete
- Sept 2004 Ready for Installation
- Fall 2004 Installation Readiness Review
- Project Milestones

**Notes:**
“Installation readiness review” is to determine if we are ready to switch to Pulsar for L2 operation

## eXtremely Fast Tracker Upgrade

- XFT finds charged tracks with pT > 1.5 GeV/c
- Part of the Level 1 Trigger system
- (more detail in afternoon breakout session)

## Run IIa XFT Configuration

**~10 m of cable to XTRP**

**TDC Hits Binned into**
**2 bins: “Prompt” and “Delayed”**

## Baseline XFT Upgrade

**Ansley trigger cable (220 ft)**
**Data @45MHz LVDS**

**168  TDC**
**from COT**
** ****axial layers**

**24 crates**

**24+24**
**New**
**Axial**
**Finders**

**3 crates**

**3 crates**

**XTC**

**~2 m copper Cable Data @33MHz (channel link)**

**~10 m of cable to XTRP**

**24**
**New**
**Linkers**

**12**
**Stereo**
**Finders**
**SL7**

**24**
**LOMs**

**1 crate**

**Neighboring cards connected over backplane**

**New TDC or XTC for **
** ****stereo layers**

**Ansley trigger cable (220 ft)**
**Data @45MHz LVDS**

**Stereo**
**Association**
**Modules**

-  Retain cable infrastructure
-  4 Layers  5 layers (add SL7)
-  Finer resolution input to all

## XFT II Scope Reviews 

- Two reviews (5/21 and 6/21) to evaluate performance and scope of the XFT upgrade and recommend course of action.
- Progress was slow, problems discovered
- Not enough good Ansley cables (TDC to XFT) to instrument stereo SL7
- Significant progress in last 9 months
- Four new postdocs and three engineers join project
- More realistic simulations (and experience with Run IIa XFT)
- Merge raw COT data from zero bias events to model high luminosity.
- Reproduces trigger rates of recent higher luminosity operation
- Performance degradation of IIa system smaller than original projections
- Committee Conclusions
- Simulations demonstrate that baseline upgrade can achieve goals
- Baseline upgrade no longer feasible, given the time available to complete project.
- Consensus (Committee, XFT proponents, Run IIb management) that addition of more stereo (SL 3, 5 and 7) is the most reasonable course.

## Re-scoped XFT Upgrade

**Ansley trigger cable (220 ft)**
**Data @45MHz LVDS**

**168  TDC**
**from COT**
** ****axial layers**

**24 crates**

**24+24**
**Axial**
**Finders**

**3 crates**

**3 crates**

**XTC**

**~2 m copper Cable Data @33MHz (channel link)**

**~10 m of cable to XTRP**

**24**
**Linkers**

**12+12+12**
**Stereo**
**Finders**
**SL3+5+7**

**24**
**SLAMs**

**2 crates**

**~3m optical Cable @60.6MHz**

**Neighboring cards connected over backplane**

**New TDC or XTC for **
** ****stereo layers**

**New cable (~150ft) Optical Data ~45MHz**

**Data to L2**

**5**
**Stereo**
**Pulsars in L2 Decision Crate**

-  **4 Superlayers ******** 7 Superlayers**
** ****3 Layer Stereo tracking**
**Finer resolution input to Stereo**
**Allows parasitic testing**

**Notes:**
Allows for parasitic testing with beam before production instalation and during commissioning
Scope: New XTC card or Chicago TDC, Optical fibers TDC to New Stereo Finder, L1 Stereo Association Module, L2 Interface (Pulsar)
Current axial system will remain as it is.
Commissioning will be parasitic (no disassembly of the axial system).
If possible, make new finder design compatible with possible use in axial layers
Scope: New XTC card or Chicago TDC, Optical fibers TDC to New Stereo Finder, L1 Stereo Association Module, L2 Interface (Pulsar)
Current axial system will remain as it is.
Commissioning will be parasitic (no disassembly of the axial system).
If possible, make new finder design compatible with possible use in axial layers

## SVT Upgrade

_*Silicon Vertex Tracker *_*(SVT)*
- brings axial silicon information into trigger
- allows for cuts on impact parameter at Level 2 in trigger (!)
- In order to be fast, SVT must specifically handle
- SVX readout and geometry
- Tevatron beam position
- Original Run 2B upgrade scope
- Geometry change for Run 2B Silicon
- Upgraded boards would also speed up L2 Decision
- New scope review 6/29/04

## Re-scoped SVT Upgrade

- New AM++ hardware with narrower roads            (32K to 512K) reduces number of tracks to fit
- Bought by INFN
- New AMSequencer/Road Warrior (12 Pulsars)
- Interface for AM++
- New Hit Buffer               (12 Pulsars)
- Faster Track Fitters  reduce processing time on found roads             (12 Pulsars)

- Upgrade SVT Data Flow

**Note 12 Pulsars will be “recycled” from current use as “Road Warrior” boards**

## Expected SVT Performance

- SVT execution time has a large impact on L2 Trigger latency
- Last data to get to L2 (can’t start until after Si r- Readout)
- Higher Si occupancy at high luminosity will increase processing time just when we need to decrease it
- Simulation (MODSIM) of CDF DAQ/Trigger:
- L2 Upgraded SVT at 3x1032 has same bandwidth capability as pre-upgrade at 0.5x1032
- More detail in afternoon Breakout Session

## Event Builder/L3 Upgrade

_*Full detector readout occurs on Level 2 trigger accept*_
- Event Builder_* *_
- subsystems send data to VRBs in VME crates
- Event builder accepts data from VRBs, assembles the full event
- Level 3 Trigger
- event sent: EVBL3 PC farm
- single PC node per event runs reconstruction & trigger algorithms
- greater rejection at L3 needed in Run IIb

**Detector Readout path**

## Run IIb Event Builder Upgrade

**	****RunIIa** 	**Run IIb**
**Rate:****	****300Hz****	****1kHz**
**Event size:****	****250kB ****	****500kB**
**Throughput: ****	****75MB/s** **	****500MB/s**
**SCPU:****	****MVME2600****	****VMIC7805**
**SCPU OS****	****VxWorks****	****Linux**
**Switch:****	****ATM****	****	****Cisco 6509****	****	****	****(gigabit ****	****	****	****ethernet)**
**	****	****	**

**new Cisco 6509 switch**

**new VMIC 7805 boards (SCPUs)**

**new software (much less than IIa)**

## Event Builder Teststand

**Code development ongoing**
**VRB ******** Switch ********L3 Processor****	**
** ****36MB/s achieved**
** ****30MB/s specification**

**VRB crate **

**“****L3” nodes **

**Gigabit switch (for final system) **

**New VMIC 7805 boards**

## Event Builder Progress

- Sept 2003 Switch technology choice, place order for final 			system switch
- Jan 2004 	Arrival of final system switch, install test stand
- Apr 2004	Production Readiness review
- May 2004 	SCPU choice, place order for final system SCPUs, 		complete code design
- Sept 2004	Arrival of final system SCPUs, code skeleton 			complete, start of testing during shutdown
- Jan  2005	Completion of Shutdown testing
- May 2005	Code complete, system ready for installation
- May 2005	Installation Readiness Review
- Sept 2005	Run IIb Event Builder installed
- Project Milestones

## CDF Trigger/DAQ Labor

- TDC
- Chicago (ENG+TECH), Fermilab(ENG+PHYS+TECH), Duke(PHYS)
- XFT
- Ohio State(ENG+PHYS+TECH), Illinois (ENG+PHYS+TECH),      Purdue (PHYS), Fermilab (ENG+TECH), Baylor (PHYS)
- Level 2
- Fermilab(ENG+PHYS+TECH), Chicago(ENG+PHYS+TECH), Penn(ENG+PHYS+TECH)
- SVT
- Pisa(ENG+PHYS+TECH), Chicago(ENG+PHYS+TECH), Fermilab(PHYS), Ferrara(PHYS), Sienna(PHYS), Tsukuba(PHYS), LBNL(PHYS), Rome(PHYS), Wisconsin(PHYS)
- EVB/L3
- MIT(PHYS), Fermilab(ENG)

## Engineering/Technician Labor

- Key to completion of the SVT, TDC, and XFT projects in <14 months will be maintaining engineering effort
- Efforts of Chicago, Fermilab, Illinois, INFN and Ohio State
- TDC
- 2 EEs from Chicago on firmware and TDC Test card design
- EE and CP from PPD/EED on TDC testing and software, firmware for TDC Test card
- Technicians from CD/ESS (PREP) for checkout and maintenance
- SVT
- Engineer from Chicago to design mezannine card
- Engineer from Fermilab for Pulsar Firmware
- XFT
- EE and technician from OSU for SLAM board design, layout
- 2 EEs from Illinois for XTC mezannine card and TDC transition card
- 2 EEs, layout technician and CP from PPD/EED for Finder design, layout and testing

## DAQ/Trigger Project Schedule

## Cost by Subproject

- Total Costs listed in AY dollars:

## DAQ/Trigger Summary

- With these upgrades to the CDF Front-end, Trigger and Data Acquisition system we obtain the bandwidth needed to carry out the Run IIb physics program.
- In production or production complete:
- L2 Decision replacement
- Event builder/L3 upgrade
- Nearing production:
- COT TDC replacement
- New scope/big increase in effort
- XFT upgrade
- SVT upgrade
- The remainder of the Run IIa CDF front-end/trigger/DAQ system will perform well throughout Run IIb

## Additional supporting Slides

## Supporting Documentation

- CDF Run IIb Technical Design Report
- Report from DAQ review Oct 2003
- TDCs
- Specification for Run 2b TDC
- CDF6998 – Run IIB TDC-II Address Space
- CDF6999 – TDC-II Design and Specification – Run IIB TDC for the COT
- May 2004 Production Review Report
- L2 Trigger
- PULSAR Web page (documentation, schematics, BOM): http://hep.uchicago.edu/~thliu/projects/Pulsar
- CDF6259: “Run IIb Upgrade for CDF L2 Decision Crate”
- Nov 2004 Production Readiness Review Report
- XFT
- CDF7039 XFT Upgrade Options and Studies
- CDF6059 Specifications for the Upgraded XFT System for High Luminosity Running in Run 2
- May 2004 Review Report
- June 2004 Review Report
- SVT
- CDF7064 Silicon Vertex Trigger Upgrade
- Review report from June 2004 review
- EVB
- Report on Prototype test results – April 2004
- Report on review by DAQ Experts – April 2004

## The CDF Detector

- Important detector element for this talk is the Central Outer Tracker (COT)
- drift chamber with 30k sense wires
- solenoid field is 1.4T
- track needs pT~75 MeV to get to COT inner layer
- tracks with ||<1 pass through all COT layers
- inner layers see tracks with ||<2

**Run IIa CDF Detector**

## Limitations of Run IIa TDC

- TDC on-board hit data processing
- 96 channels processed serially by Digital Signal Processor (DSP) after L2A
- Time (=deadtime) grows with # of hits  at 4x1032cm-2s-1 in SL1 processing takes 1200sec/event (4 hits/channel)
- Run IIa processing time too large for Run IIb specification
- VME readout
- Hit processing for next event can occur during VME transfer for previous event
- 16 TDCs per crate read out serially by VME block transfer
- current VME transfer rate 14MB/s with additional overhead per board
- Run IIa, 300Hz...falls to ~150Hz (!) in Run IIb
- Data transfer
- TRACERTAXIVRB link is a bandwidth limitation
- maximum TAXI VRB is <12MB/s...Run IIb requires 14MB/s
- Internal CDF TDC Review committee (June 2002) _***Conclusion:***_
- Existing COT TDCs + VME readout system cannot maintain L2A rate in Run IIb
- TDC system must be replaced **OR** significant modifications to the DAQ & infrastructure must take place

- At time of  Sep. 2002 DOE Review

## XFT IIb Design

**Reduce fakes and improve resolution with improved axial track finding &  3D information **
- Take advantage of existing design and infrastructure
- Cables, I/O, data formats unchanged
- Difference between XFT & offline tracking is time binning. Segment angle match improves with finer time bins.
_***Upgrade:***_
- Utilize 396ns baseline to pipe more information per beam-X from TDCXFT.
- Go from two time bins to six time bins in the trigger
- Supplement axial tracking with stereo measurement
- Segment finding identical to axial XFT
- Stereo information provides:
- improved fake track rejection (important at high L)
- new: electron & muon matching in 

- From Sep. 2002 DOE Review

## Status of L2 Decision Upgrade

- Hardware:  all hardware production/testing finished
- Custom:  Pulsar, mezzanine cards, AUX, LVDS splitter
- Commercial: fiber splitter, SLINK mezzanine, SLINK-PCI cards,
- 			Linux processors
- Firmware:  all firmware in place, fine tuning started
-       Transmitters and receivers for all data paths
-        SLINK merger and L2 to trigger supervisor interfaces
-         about 14 different types of Pulsar firmware
- 	  Keys to success: uniformity modularity, CVS control, dedicated writers
- Software:  core software in place, fine tuning started
-       board testing, VME DAQ readout, online/offline monitoring,
-       infrastructure software for decision PC and L2 algorithm...
- Beam tests:  started June 2004
-       beam tests  monitoring  firmware/software fine tuning

## Run IIa Track Trigger System

- XFT works by finding line segments in the four axial superlayers
- “finder” boards
- Tracks are found by linking the segments into tracks
- “linker” boards

**Stereo superlayers **
**(unused in Run IIa XFT)**

## XFT Upgrade

- Track-based triggers are responsible for >50% of the Run IIb physics program
- e, , , *b*-tags
- COT occupancy at high luminosity causes significant L1 track trigger (XFT) degradation
- Significant growth in fake track rate (primarily at high *p**T*)
- Significant degradation in *p**T* and ***0* resolution

**Minimum bias MC events**

- From Sep. 2002 DOE Review

## Silicon tracking information in the trigger
find displaced tracks
Run IIb: important for Higgs, SUSY, Zbb
Also to continue hadronic Bs decays

- find displaced tracks
- Run IIb: important for Higgs, SUSY, Z*bb*
- Also to continue hadronic Bs decays

- Run IIa SVT

*B**0** **** h**+**h**-*

*B**+** **** D**0****+*

*D**0** ****K******+**,K****K**+**,********+*

## Run 2A Readout/L3 Architecture