# Presentation: 883604

## Reliability of Antifuse-Based Field Programmable Gate Arrays for Military and Aerospace Applications

- John McCollum, Roy Lambertson, Jeewika Ranaweera, Jennifer Moriarta, Jih-Jong Wang, and  Frank Hawley
- Actel Corporation

## Manufacturer Responsibility

- Antifuses are an addition to the base CMOS process
- Reliability of the ONO antifuse
- There are two states that must be reliable
- Open
- Short

## ONO Antifuse

**ONO Antifuse**

## ONO Antifuse Photomicrograph

**ONO Antifuse Photomicrograph**

## Slide 5

## Programmed State of ONO

**Programmed State of ONO**

## Note: No Switch off

- Programmed at 5mA

- Heating of Filament

## ONO Antifuse Switch off Test

**ONO Antifuse Switch off Test**

## Photomicrograph showing failure of  Poly Contact,

-  not the Antifuse

## SEDR Curve

**SEDR Curve**

- 90A Thickness
- Typical is 96A

## Amorphous Silicon Antifuses

- Amorphous-Silicon Antifuses allow higher density(Sea of Modules)
- Higher performance - Lower Capacitance
- Reliability analysis for opens and shorts

## Unprogrammed Antifuse

**Unprogrammed Antifuse**

- Antifuse

- Metal 3

- Via to Metal 4

## Slide 13

## Programmed Antifuse

**Programmed Antifuse**

## Slide 15

## Slide 16

## Data showing that switch off of the metal Antifuse

-  is over designed by at least a factor of 2

## SEDR of the Metal to Metal Antifuse

- SXS shows one failure
- at 2.85V
- max spec is 2.75V

- No failure

## Since BVG (Break Down Voltage) of ONO was lower than gate oxide, no antifuses are connected to pins
ESD thus achieved Class 2 >2000 Volts
Actel however discovered PID (Process Induced Damage) in Fabs
Implanters and Plasma Etchers could produce 20 volts on the wafer and destroy the ONO
Actel worked with the Fabs and solved this problem
Additionally Actel voltage stresses each part at Wafer Sort and Final Test to eliminate all antifuse defects

- ESD thus achieved Class 2 >2000 Volts
- Actel however discovered PID (Process Induced Damage) in Fabs
- Implanters and Plasma Etchers could produce 20 volts on the wafer and destroy the ONO
- Actel worked with the Fabs and solved this problem
- Additionally Actel voltage stresses each part at Wafer Sort and Final Test to eliminate all antifuse defects

- ESD > 2000 Volts

## Actel Gate Oxide Failures are Rare 

- Most MOS reliability defects are traditionally Gate oxide Failures
- By virtue of the high voltage stresses applied to Actel circuits for programming (even low voltage transistors) there have been very few oxide failures

## Slide 21

## Early defects related to via failures

## Note: no failures

## Testing ASICs with test vectors of less than 100%

**PPM**

- 0.70

- 0.80

- 0.90

- 0.95

- 0.96

- 0.97

- 0.98

- 0.99

- 0.995

- 0.999

- 0.7

- 0.999

- Fault Coverage

**Testing ASICs with test vectors of less than 100%**
** ****can lead to unacceptable failure rates**

**PPM Faults  vs Yield**

## FPGAs are However 100% tested

- All tracks
- All modules
- All clocks
- All programming circuits
- All I/Os
- All isolation transistors

- The charge pump
- All antifuses in the open state
- All antifuses are stressed
- A column of circuits is programmed (binning circuit) to verify programming

## During programming a small fraction of antifuses will fail to program
Once the programmer passes a part it is guaranteed to be 100% functional
Tests are performed to verify that the correct antifuse is programmed and is the correct impedance
Additional tests are done to verify that no other antifuse was erroneously programmed or any circuit damage was done

- Once the programmer passes a part it is guaranteed to be 100% functional
- Tests are performed to verify that the correct antifuse is programmed and is the correct impedance
- Additional tests are done to verify that no other antifuse was erroneously programmed or any circuit damage was done

## SEU Prevention

- If SEU is a concern, the use of CC Module or TMR techniques are required.  Actel  tools fully support these techniques in synthesis
- The RTSXS family has self refreshing TMR built into every register.  It has proven nearly ion proof, such that SEU upsets do not have to be considered in design

## RTSXS is Power-up Friendly

- RTSXS have new features to make it power-up friendly while the charge pump is turning on
- Outputs are tristated
- Logic Modules are in standby
- Outputs can be programmed to source or sink 50 A
- Once Charge pump has reached operating voltage the  modules are activated and  the outputs become valid with no glitches

## User Testing

- _FLIP FLOPs can remember their last state up to 24 hours in any MOS Circuit_
- Set flip flops to the opposite state of the desired power-up state for one hour before power-down followed by the power-up sequence
- Power-on reset signals should not be applied until the power supplies have reached spec.

## Summary

- ONO and Amorphous Silicon Antifuses have been shown to be very reliable
- Reliability is dominated by CMOS process
- Reliability of the the new Antifuse FPGAs is limited by the time allowed to collect reliability Data
- FPGAs are inherently more reliable than Gate Arrays if the Fault Coverage is less than 100%