# Presentation: 378909

## Design of an Upgraded DØ Silicon Microstrip Tracker for Fermilab Run 2b  

- Fermilab/University of Kansas
- for the D0 Run2b silicon group
- October 15, 2001
- 7th International Conference on Advanced Technology and Particle Physics

- Design of an Upgraded DØ Silicon Microstrip Tracker for Fermilab Run 2b

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Outline

- Run2b Concept
- Boundary Conditions for Design
- Tracker Layout
- Performance
- Conclusions

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Run 2  Physics Goals

- Need two experiments operating detectors with good b-tagging efficiency to see Higgs.
- Each experiment needs to obtain 15 fb-1

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Run 2b

- Although we just built a major silicon detector and are still commissioning it, a new silicon detector is planned; major undertaking.
- Current silicon detector designed for ~ 2 fb-1
- Laboratory supports extended running to ~ 15 fb-1 per experiment

- Run 2a Lifetime studies by both collider experiments

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Implications of Run 2b

- 2a Detectors will survive 2 fb-1 with high degree of confidence
- Inner Layers will definitely not survive 15 fb-1
- Detectors will require modifications to exploit full physics potential of Tevatron

- _Boundary conditions set by the laboratory_
- Limited budget for replacement
- New detectors to be designed to operate with confidence throughout Run2b with integrated luminosity of at least 15 fb-1
- Installation of new detectors in single shutdown of no more than 6 months duration in the year ’04

- Option chosen by both collider collaborations is to fully replace the existing silicon detectors, without retrofitting the existing DAQ system

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Boundary Condition: DAQ

- Retain readout system downstream of adapter card
- Cable plant allows for 912 low mass / high mass cables

- retain

- Some changes to voltage distribution will have to be made

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Irradiation Studies

- Studies carried out with ELMA  and CDF layer 00 sensors from Hamamatsu and Micron.
- Measurements agree well with other measurements

- Conclude that the design value for Silicon operating temperature at the inner layer should be T= -10 oC

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Design Considerations

- No compromise on performance compared to Run2a
- Minimize the variety of different components
- Modular design
- Provide stand-alone tracking up to || < 2.0

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Design Choices

- Drilled Be Beampipe with ID of 0.96”, 500m wall thickness
- Employ only single sided silicon
- Three different sensor types: 2, 3 and 5-chip wide
- Six layers, divided in two radial groups
- Inner layers: Layers 0 and 1
- Axial readout only
- Mounted on integrated support
- Assembled into one unit
- Designed for Vbias up to 1000 V
- Outer layers: Layers 2-5
- Axial and stereo readout
- Stave support structure
- Designed for Vbias up to 300 V
- No element supported from the beampipe

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Comparison 2a and 2b

- 2a:
- Innermost radius 25.7 mm
- Outermost radius 94.3 mm

- 2b:
- Innermost radius 17.5 mm
- Outermost radius 163.6 mm

- End views drawn to scale

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Design Choices

- Sensor lengths
- Inner layers: 78.4 mm, 6 sensors per half-module
- Outer layers: 100 mm, 5 or 6 sensors per half-module
- Longitudinal segmentation
- Readout is ganged in outer layers
- Hybrids are double-ended and service two readout segments

- Layers 2 and 3

- Layers 4 and 5

- Sensors are wirebonded

- hybrid

- Two hybrids per stave

- 100mm long sensor

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Design Choices

- Si temperature of inner layer should be kept at T=-10 oC
- Heat Load
- ~30 Watts ambient
- ~20 Watts at 15 fb-1 at innermost layer (T= -10 oC)
- ~0.5 Watts per readout chip
- Cooling will use 40%-60% water/ethylene-glycol mixture
- Tclnt = -15 oC
- Option to go to Tclnt = -20 oC with second chiller for inner layers
- Heat load too high to allow for readout chips to be mounted on silicon: analogue cables, off-board electronics for innermost layer

- CDF layer 00

- Analogue cables

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Layer 0

- Carbon foam structure lined with Carbon fiber
- Uses Peek cooling tubes
- Hybrids mounted off-board connected to silicon with Analog cables

- Hybrid out of detector volume

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Layer 1

- Carbon foam structure similar to that of Layer 0
- Layer 1 is mounted together with Layer 0
- Hybrids are mounted directly on the silicon

- Layer 0

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Outer Layers

- Staves are assembled from readout modules
- There will be 6 types of readout modules:
- 10-10 (axial, stereo)
- 10-20 (axial, stereo)
- 20-20 (axial, stereo)
- Ganged sensors will have traces aligned
- Stereo angle determined by mechanical constraints
- 10cm readout:  = 2.5o
- 20cm readout:  = 1.25o

- 20-20 Stereo Module

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Stave Structure

- Stave is doublet structureof many readout modules
- Two layers of silicon
- Axial and stereo
- separated by PEEK cooling lines
- Staves are mounted in end carbon fiber bulkheads

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Stave Readout Schematic

- Hybrid
- Digitizes Si analogue signal, launches the digital signal on the ...
- Digital Jumper cable
- Flex circuit which brings signals to the ...
- Junction card
- Passive element which transfers signals to high quality twisted pair signal cable which brings the signal to the ...
- Adapter card
- Active element that provides the differential drive for the svx4 chip

- Hybrids

- Digital Cables

- Junction Card

- Twisted Pair

- Layers 2 and 3

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Hybrids

- Characteristics:
- Layer 0
- 2-chip hybrids; each hybrid reads out one sensor
- Layers 1-5
- Hybrids are double ended
- 6-chip hybrids for layer 1
- 10-chip hybrids for layers 2-5
- Made of ceramic (BeO)
- Silkscreening and etching
- Can have multiple layers
- Hybrids carry the bias voltage for layers 2-5 (300 V)
- One HV feed / hybrid;
- HV is split between up to 4 sensors
- HV fed through AVX 50 pin connector

- 6-chip hybrid

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## SVX4 Chip

- Nov ’00 decision to employ common readout chip for CDF and DØ
- SVX4 in deep sub-micron, 0.25 m technology, intrinsically rad-hard
- Brand new chip with own personality/features
- Commercial foundries used
- Test chip submitted to MOSIS 06/04/01  (Full submission 11/01)
- 16 channels LBL design preamp + pipeline
- 48 channels FNAL design preamp + pipeline
- Common bias preamp+pipeline as in SVX3
- 12 different input transistor sizes used to optimize noise
- ENC = 450e + 43.0e/pF (optimum)

- LBL Pre-amp

- FNAL Pre-amp

- Pipeline

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Parameters

- Comparing channel count:
- 2a: 792576 channels
- 2b: 952320 channels
- Cable plant is slightly smaller

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Performance

- A full GEANT simulation has been done with D0 reconstruction code used to analyze the results
- The occupancy as a function of radius is shown here with and without noise.  For the innermost layer, the mean occupancy is around 2%

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Hit resolutions for WH events

- Resolution for inner layers for all clusters

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## B-tagging and mis-tagging rates

- Efficiencies are found using a impact parameter significance algorithm as a function of the efficiency is 19% higher than that for the Run2a detector at the same mistag rate

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau

## Conclusions

- The goal of the D0 Run2b detector is to provide adequate b-tagging efficiency to help discover the Higgs with 15fb-1 of data
- There were many constraints that led the design of the detector including those from time, space available, cost, and integration into the present D0 DAQ system.
- A 6 layer barrel device was chosen to maximize our physics capacity
- The design of the detector is proceeding on all fronts
- The performance as benchmarked using a full GEANT simulation with the D0 reconstruction code shows that we will have a device superior to the Run2a silicon detector particularly for tagging b quark jets

- Dzero Collaboration Meeting, Sept. 14, 2001  - M. Demarteau