# Presentation: 771805

## Measurements for the Reliability and Electrical Characterization of Semiconductor Nanowires

**Curt A Richter****, **
**Hao Xiong, Xiaoxiao Zhu, Wenyang Wang, Vince Stanford**†
**Semiconductor Electronics Division **
- † **Information Access Division **
**National Institute of Standards and Technology**
**Qiliang Li, D.E. Ioannou**
**	****Elect. and Comp. Engn, George Mason University**
**Woong-Ki Hong, Takhee Lee****, **
**    ****Gwangju Institute of Sci and Technology, Korea**

*2008 IEEE Reliability Physics Symposium*

**Measurements for the Reliability and Electrical Characterization of Semiconductor Nanowires**

## Purpose- metrology to enable emerging nanoelectronics -

**New test structures and associated measurement methods are needed to enable development, assessment, and adoption of emerging nanoelectronic device technologies such as those based upon semiconductor nanowires to enhance and extend the capabilites of CMOS.**

**Primary Metrology Needs**
- Test structures that enable electrical contacts to nanowires with sub-lithographic diameters.
- Advanced Electrical Characterization.
- 3.	Correlate electrical results with underlying physical properties (to determine the Structure-Function relationship).

## Outline

- _Why study Noise in semiconductor nanowires?_
- Conduction fluctuations, or signal-to-noise ratio, are a fundamental performance limiting factor for nanoelectronic devices.
- Most experimentally accessible defect characterization tool:

- Si-Nanowire Test Structures
- Single Nanowire manipulation System
- Directed Assembly Fabrication Approach.
- 1/f noise in semiconductor nanowire devices.
- Si nanowire FETs (with high-K)
- ZnO nanowire FETs
- Random Telegraph Signals (RTS)
- Quantitative Noise Analysis Approach
- Summary

## Si nanowire growth- vapor-liquid-solid mechanism -

- “Harvest” wires into dilute solution

- Gold Catalyst : Droplet mediated growth

- Growth from patterned catalyst

## Nanowire Test Structures - Wiring Nanowires -

**A “common” approach to fabricating NW devices**

- Disperse NW’s onto substrate
- 		(with fiducial marks)
- Locate Wires
- Custom Electron Beam Lithography

_**Difficulties of this approach**_
- No batch processing
- Process induced contamination/damage
- Expensive EBL required.

## SiNW Test Structures- Single nanowire manipulation system (SNMW) -

- Use SNMS to align NW and Photolithography to pattern metal contacts

- Kelvin Test Structure
- (to extract contact resistance)

**SNMW**

- (c)

- (d)

- (e)

- SNMS

- template substrate

- test substrate

*Q.Li et al., IEEE T. Nano (March 2007)*

## Kelvin Test Structure

- Traditional test method to extract contact resistance

## Nanowire Test Structures: TLM Example

- - **Transfer length method (TLM) test structure -**

- Extracting metal/SiNW contact resistance

- intercept =* **2R**C** *= 4.8 M

- (31 to 32.7) M/m
- slope = *l*

## SiNW Field Effect Transistors- Self-aligned SiNW Device Technology -

- SiNWs grown by the Vapor-Liquid-Solid Growth fabrication method

- Device Examples

*Qiliang Li, et al.  Nanotechnology, 2007*

- _Advantages _
-  Small diameter nanowires.
-  Full wafer simultaneous fabrication.
-  “Cleaner” processing

## Single SiNW Field Effect Transistors- Self-Aligned Assembly and ALD HfO2 -

**Single SiNW Field Effect Transistors****- Self-Aligned Assembly and ALD HfO****2 ****-**

- ALD HfO2 gate dielectric

- After
- Anneal

- Before
- Anneal

- Good Transistor Properties

- 5 minute
- Forming
- Gas anneal
- (300 C)

- 0

- 1

- 2

- Vds (V)

- -Ids (A)

- -Ids (nA)

- 0

- 400

- 800

- 1200

## 1/f Noise in SiNW FETs

**1/*****f***** Noise in SiNW FETs**

-   1
- (before): 0.93 - 1.16
- (after): 1.10 - 1.13

- VDS = -1 V
- VG = -1.5 V to -2.4 V

- Before Anneal

- Hooge’s const, ***H*

- 1/*f*

## Effect of Interface Traps on Noise

- Before
- Anneal

- After
- Anneal

- Dit  6 x 1012 cm-2
- H  5 x 10-2 before
- H  1.3 x 10-2 after

- From slope IDVG

## Hooge’s Constant

**Hooge’s Constant**

- ITRS criterion

- Noise compares acceptably with other emerging device technologies.
- Expect noise reduction with process optimization.

*Wenyong Wang et al, JAP 2007,*
*Janes et al APL, 2008*

- this
- work

- Metal Gate/HfO2

- poly-Si Gate/HfO2

- SWNT FET

- ZnO NW FET

- Si NW FET

## ZnO2 Nanowire devices

*Wang et al., J. Appl. Phys. (2007)*

- Single X-tal ZnO2 nanowires

- Make “good” transistors
- which...
- perform as oxygen sensors

- Ids (A)

- Vds (V)

## 1/f noise in ZnO nanowires

*Wang et al., J. Appl. Phys. (2007)*

- Utilize the noise to investigate oxygen sensing mechanisms

- 1/f Noise spectra (295K)

- Ids (A)

- Noise amplitude, A

- dry O2

- vacuum

## Random Telegraph Signals

- 1/f Noise spectra (295K)

- Random Telegraph Signals (4.2K)

*Xiong et al., APL 2007*

- Transition from 1/*f* spectra to Lorentzian “RTS” Spectra as cooled to 4.2K

- 10-10

- 10-8

- 10-6

## Individual Defect Characterization

**Individual Defect Characterization**

- _As V__G__ increases_

**Donor Trap**
- (more time unoccupied)

**Acceptor Trap**
- (more time occupied)

**Count**

- RTS

- histogram

- Switching among three-states attributed to two dominant scatters

## Quantitative Analysis of RTS data

- 2

- find states

**Quantitative Analysis of RTS data**

- 1

- 3

- decode
- RTS

- Apply Signal Processing techniques to quantitatively analyze RTS.

- form
- histogram

## Extracting Duration Times

- State 1
- <1> = 2.2 sec

- State 2
- <2> = 16 msec

- Decode Information
-  State
-  state

- Exponential state times

## Conclusions

- Appropriate test structures enable the extraction of the fundamental properties of nanowires
- Noise - ideal probe of scattering dynamics in nanoelectronic devices.
- Experimentally characterized the noise spectra of
- SiNW FETs
- ZnO FETs
- Noise is directly correlated with
- Interface trap density (SiNW)
- Oxygen sensing properties (ZnO-NW)
- Signal Processing techniques can improve the quantitative analysis of RTS

**- developing new approaches to characterize semiconductor nanowires -**

## Acknowledgements

- David Gundlach,
- O. Kirillov,
- M, Edelstein,
- John Suehle,
- Charles Cheung,
- Neil Zimmerman
- at NIST

**Acknowledgements**