# Presentation: 363169

## The BTeV Vertex Trigger

***Beauty 2002, June 17-21***
***Charles Newsom, The University of Iowa***
***for ***
***The BTeV Collaboration***

## BTeV detector

## Simulated B Bbar event-including neutrals

## Silicon pixel detector

**Silicon pixel ****detector**

***14,080 pixels (128 rows x 110 cols)***

***380,160 pixels***
***per half-station***

***total of 23Million pixels***
***in the full pixel detector***

## BTeV trigger block diagram

- 200 MB/s (4x compression)

## Level 1 vertex trigger architecture

**Level 1 vertex trigger architecture**

**30 station pixel detector**

## L1 vertex trigger algorithm

**Find beginning and ending segments of tracks from hit clusters in 3 adjacent stations (triplets):**
- beginning segments: required to originate from beam region
- ending segments: required to project out of pixel detector volume

**FPGA Segment Finder (Pattern Recognition)**

**Match beginning and ending segments found by FPGA segment finder to form complete tracks. **
**Reconstruct primary interaction vertices using complete tracks with p****T****<1.2GeV/c.**
**Find tracks that are “detached” from reconstructed primaries.**

**DSP Tracking and Vertexing**

## L1 vertex trigger algorithm

**L1 vertex trigger algorithm**

**Execute Trigger**

## L1 trigger efficiencies

| Process | Eff. (%) | Monte Carlo |
| --- | --- | --- |
|  |  |  |
| Minimum bias | 1 | BTeVGeant |
| Bs          D+sK- | 74 | BTeVGeant |
| B0          D*+- | 64 | BTeVGeant |
| B0          00 | 56 | BTeVGeant |
| B0          J/s | 50 | BTeVGeant |
| Bs          J/*0 | 68 | MCFast |
| B-          D0- | 70 | MCFast |
| B-          Ks- | 27 | MCFast |
| B0          2-body modes | 63 | MCFast |
| () |  |  |

## L1 vertex trigger: work-in-progress

**Status of L1 track finding & vertexing code:**
- C version of full tracking & vertexing code running on a TI C6711 based daughter card on the prototype board.
- Goal is to avoid hand optimized assembly for the TI DSP in order to simplify code maintenance and achieve greater portability.
- Incorporating various optimizations in C:  use of intrinsics, in-line code vs. external function calls, single precision arithmetic, etc.
- Current code speed tests are ~4x slower than in the proposal using today’s technology.

**Level 1 Vertex Code Benchmarks**

**Execution speed in units normalized to TI C6711 speed**
**(longer bars are better)**

***Pentium III***

***PowerPC G4***

***BTeV Proposal***

***TI DSP***

## L1 trigger 4-DSP prototype board

## Level 2 Trigger

**Start with the Level 1 tracks from the ``triggering collision” within the crossing.**
**Search for pixel hits along these tracks.**
**Refit the tracks using a Kalman Filter.  Resultant momenta are improved to about 5-10%.**
**Resultant event must satisfy one of the two following criteria:**
- A secondary vertex must be present or
- The collection of tracks must satisfy a minimum pT cut.
**The combined L1 and L2 rejection is 1000-1.**
**Overall Efficiency is roughly 50% for most B decays of interest.**

## Fault tolerant trigger & DAQ system

**Summary**
**The L1/L2 vertex trigger is a major component in the larger framework of the Global BTeV trigger and DAQ  system.**
**This larger framework is a massive and complex real-time system involving thousands of FPGA’s, DSP’s, and PC’s analyzing detector data generated at ~1.5 Terabytes/s.**
**BTeV will benefit from an NSF grant to develop a semi-autonomous, self-monitoring, fault-tolerant / adaptive system for this purpose.**
**Project involves collaboration of computer scientists and physicists from Vanderbilt, Illinois, Syracuse, Pittsburgh, and Fermilab known as the Real Time Embedded Systems (RTES) Research Group.**
**The BTeV trigger can be built with currently existing technology and will only improve as computing technology advances.**