# Presentation: 276415

## CTT CommissioningTrigger WorkshopOctober 22, 1999

**WBS 1.1.5.3 & 1.4.3.3**
**Presented by **
**Fred Borcherding**
**for the**
_**D0 Electronics Group**_

## Charge for the Workshop

- For each of the NIU sessions, we would like to have some preparedtalks to cover the following:
- 1. Schedule of completion of the hardware
- 2. Test program at the board level (who, where, when?)
- 3. Test/commissioning of the sub-detector trigger or frameworkprior to commissioning in the D0 environment in the D0 Hall.(who, where, when?)what other resources are needed (serial links, downloads, COOR,clocks, etc.)
- 4. Commissioning in D0.
- 	What is the sequence, time estimate for the commissioning?How will cosmic ray studies be used?What interactions with other systems are required?Give an estimated schedule for commissioning.

- September 24, 1998

## CTT Project

**Four separate installations**
**CFT Axial**
**CFT Stereo**
**CPS Axial**
**CPS Stereo**
**(FPS)**

**Several Steps**
**Production **
**Board Test**
**System Test**
**Installation**
**‘****In Place’ Commissioning**
**Run**

- September 24, 1998

## System Size

- CTT has three sets of boards.
- CTT has a total of about 10 ‘boards’
- CTT has very small signal Analog boards
- target of 5 fC threshold
- CTT has very high IO digital boards
- each DFE has ~15Gbits/sec input
- each MB has ~20Gbits/sec input & output

- AFE Board
- 8-MCM board
- 12-MCM board
- MCM daughter card
- Analog Input board
- DFE Board
- Mother board
- Transition board
- Daughter Boards
- Testing DB
- Tracking ( & cluster finding)
- collector (octant)
- DB2
- MB Mixing Box Board
- Input board
- Output board
- MB Test Board

- September 24, 1998

## Schedule of completion of the hardware

**CFT**
**8* Boards Manufactured**
**2/1/00****	****  AFE [8-MCM] (8)**
**12/1/99 Seq/SeqC/VRB/VRBC**
**1/3/00****	****  DFE+TDB (4)**
**3/6/00****	****  CDB (1)**
**3/22/00 DB2 (1)**
**3/6/00****	****  MB (1set)**
**All Boards Manufactured**
**7/28/00  AFE [8-MCM]**
**12/1/99  Seq/SeqC/VRB/VRBC**
**5/1/00  DFE+TDB**
**7/3/00  CDB**
**7/14/00 DB2**
**7/10/00 MB**

**FPS**
**8* Boards Manufactured**
**4/20/00 AFE [12-MCM] (4)**
**12/1/00 Seq/SeqC/VRB/VRBC**
**2/7/00****	****  DFE+TDB (1)**
**4/3/00****	****  CDB (1)**
**4/24/00 DB2 (1)**
** **
**All Boards Manufactured**
**7/28/00  AFE [12-MCM]**
**12/1/00  Seq/SeqC/VRB/VRBC**
**6/5/00****	****   DFE+TDB**
**7/28/00  CDB**
**7/28/00  DB2**

**CPS**
**8* Boards Manufactured**
**4/20/00 AFE [12-MCM] (4)**
**12/1/00 Seq/SeqC/VRB/VRBC**
**2/7/00****	****  DFE+TDB (1)**
**4/3/00****	****  CDB (1)**
**4/24/00 DB2 (1)**
** **
**All Boards Manufactured**
**7/28/00  AFE [12-MCM]**
**12/1/00  Seq/SeqC/VRB/VRBC**
**6/5/00****	****   DFE+TDB**
**7/28/00  CDB**
**7/28/00  DB2**

- NOTE: All dates subject to change

- September 24, 1998

## Test program at the board level- WHO.

- AFE Board
- 8-MCM board			John A, Pat S, Paul R, Mike M, Stefan G;
- 12-MCM board			John A, Pat S, Paul R, Mike M, Stefan G;
- MCM daughter card		John A, Pat S, Paul R, Mike M;
- Analog Input board 		John A, Pat S,
- DFE Board
- Mother board			J Olsen, Pat S,
- Transition board			J Olsen, Pat S,
- Daughter Boards
- Special Testing board 		J Olsen, Kin Y
- Tracking ( & cluster finding) 		J Olsen, Kin Y, Stefan G,
- collector (octant) 		J Olsen, Manuel M, Juan L, Brian
- DB2			J Olsen, Manuel M, Juan L, Brian
- MB Mixing Box Board
- Input board			J Olsen, M Vaz, Other?
- Output board			J Olsen, M Vaz, Other?
- Test board			 J Olsen, M Vaz

- September 24, 1998

## Test program at the board level- WHERE and WHEN.

- AFE Board
- 8-MCM board			DAB3 Analog Test Stand		Mar-Jun
- 12-MCM board			DAB3 Analog Test Stand		May-Aug
- MCM daughter card		DAB3 Analog Test Stand		May-Aug
- DFE Board
- Mother board			DAB3 Digital Test Stand		Dec-Mar
- Transition board			 DAB3 Digital Test Stand		Dec-Mar
- Daughter Boards
- Tracking ( & cluster finding) 		 DAB3 Digital Test Stand		Jan-Apr
- collector (octant) 		 DAB3 Digital Test Stand		Mar-Jun
- DB2 & others			 DAB3 Digital Test Stand		Apr-Jul
- MB Mixing Box Board
- Input board			 DAB3 Digital Test Stand		Jul-Aug
- Output board			 DAB3 Digital Test Stand		Jul-Aug

- September 24, 1998

## Board Testing

**AFE > 8 MCM**
**bench test - AnTS  **
**(on cassette in lab 3)**
**AFE > 12 MCM**
**bench test - AnTs **
**(on cassette in lab 3)**
**DFE **
**bench test - DTS**
**Mixing Box**
**bench test - DTS**

**The AFE testing @ lab3 requires **
**working cassettes**
**light pulser system w VTBG**
**Seq/SeqC/VRB/VRBC**
**trigger generation logic**
**1553 links**
**PC / bit3**

- September 24, 1998

## Board Testing cont.

**The DFE testing requires**
**input pattern generator**
**test patterns**
**tracks**
**output pattern analyzer**
**download link**
**1553 link**
**PC / Bit3**

**The MB testing requires**
**input pattern generator**
**test patterns**
**tracks**
**DFE for output analysis**
**PC / Bit3**

**The AFE testing requires **
**input pattern generator**
**DFE for output analysis **
**download link**
**SASEQ**
**VTBG system**
**1553 links**
**Bit3 / PC**

- September 24, 1998

## AFE Board Testing

**Some AFE production boards will be tested @ lab3 stand**
**Test with ‘real’ inputs**
**Test with more realistic grounding and noise environment**
**Test cryo and bias supply functions**
**Note: [MCM are tested prior to mounting on AFE]**

**Bench test requires development of analog input method**
**Low amplitude charge injection**
**VTBG System**
**Input conversion**
**HD connection that can survive 200 boards**
**FLEX type cable**
**mated to VTBG**

- September 24, 1998

## DFE Board Testing

**Special Test Daughter board produced**
**High speed “Data Pump” db generates patterns and fake event data, and checks the output of the DFE**

**Each of the different Daughter board types will require different test firmware/PC software**
**Mother board, Transition board, and daughter board sets are tested.**

- September 24, 1998

## MB Board Testing

**The ‘Mixing Box Test Board’ serves as input pattern generator and output analyzer**
**high rate input source**
**provides high speed and high bandwidth lvds loopback testing **
**Share PC and test stand with DFE**

**Bench test requires**
**Test pattern input board**
**Test pattern receiver board**
**Test generation software**
**Test analysis software**

- September 24, 1998

## Test/commissioning of the sub-detector

- 3. Test/commissioning of the sub-detector trigger ..prior to commissioning in the D0 environment in the D0 Hall.(who, where, when?)what other resources are needed (serial links, downloads, COOR,clocks, etc.)

- September 24, 1998

## Sub-Detector

**The CTT systems test/commission in THREE stages**
**1 - Analog + L3 Readout **
**2 - Digital (trigger)**
**2.1 - DFE alone**
**2.2 - DFE + L1MUON [CFT]**
**2.3 - DFE + Collector**
**2.4 - DFE + ... + L2pp & L1MTM**
**2.5 - MB + DFE**
**3 - Complete System**
**[+ MB for CFT]**
**Stage 1 and Stage 2 can be concurrent!**

- September 24, 1998

## Stage 1

**Test AFE and L3 Readout chain**
**Test lvds links - ****test fixture is DFE+DB with special firmware**

- September 24, 1998

## Stage 1 - AFE

**Hardware **
**Test Stand**
**Dummy Cassette**
**VTBG, Input Brd (pulser)**
**AFE Boards**
**Sequencer, Crate, Cont.**
**VRB, Crate, Cont.**
**DFE + daughter**
**Software**
**PC Software for control [a la MCM test software] **
**AFE board firmware**
**special DFE board based test firmware**

**Procedure**
**Download to SVX on AFE**
**Read SVX cal-inj patterns**
**Read ‘pulser’ inputs**
**Milestones**
**successful download**
**see all input channels in SVX data**
**see all input channels on DFE board with special test firmware**

- September 24, 1998

## Stage 2

**Work in the trigger end of the system**
**Test Generator / Receiver is MB test board**
**Actual MB inserted before DFE for stage 2.5**

- September 24, 1998

## Stage 2 - DFE

**Hardware **
**DFE Boards**
**L1 MUON cables**
**L1 MUON ‘test’ receiver**
**Test Generator / Receiver**
**Software**
**Test Generator firmware**
**Need Track Loader software (person) here**
**Download DFE**
**1553 I/O to DFE**
**PC control and analysis**

**Procedure**
**Download to DFE crate and boards**
**Run Test Generator**
**Monitor DFE output**
**Monitor Collector etc.**
**Monitor L1 Muon**
**Milestones**
**successful download**
**Data seen from DFE**
**Data seen at L1Muon**
**Data seen from collector etc.**

- September 24, 1998

## Stage 3 - Final Stage

**CFT/CPS Axial version with mixing box**
**FPS/CPS Stereo without**

- September 24, 1998

## Stage 3 - Final Stage

**Hardware **
**Combine AnTS to DTS**
**Software**
**Same functionality as at Test Stand PCs**
**But now link the two**

**Procedure**
**Same as Stage 2**
**Milestones**
**See all Stage 1 and 2 milestones on the combined system**

- September 24, 1998

## Commissioning in D0.

- 4. Commissioning in D0.
- 	What is the sequence, time estimate for the commissioning?How will cosmic ray studies be used?What interactions with other systems are required?Give an estimated schedule for commissioning.

- September 24, 1998

## Cosmic Ray Trigger

**Trigger on CR that penetrates to center of CFT**
**require MUON on inward track**
**require track through beam pipe with CFT**
**Can trigger down to ~0.5GeV in tracker(?)**

**Trigger elements**
**uScintOctant**
**CFT A-layer-back-to-back**
**other CFT layers to fine-tune rate**
**Timing**
**run at 396-132**
**live for CFT window - 80of396ns or 20%**
**Tests**
**L3 track finding**
**L2 trigger**
**L1 trigger**

- Similar Trigger forward with FPS & Forward Muon?

- September 24, 1998

## ‘In Place’ Commissioning

**Four Separate Systems can proceed independently**
**Each of the systems is commissioned in 3 Stages - **
**same as sub-system commissioning outlined earlier**
**Each stage adds more hardware**
**Each stage requires more software**
**A 4th stage - CR running - added with ****no special hardware**
**NOW Host software is ****ON-LINE**
**Can start with ‘one crate’**
**Can finish within one month after last crate**
**or about 3-4 months total time (whichever is longer)**

- September 24, 1998

## Overall Software Needs

**KISS Applies**
**keep it simple**
**Have different types of users**
**technicians**
**engineers**
**physicists**

**Have different environments**
**Stand alone bench tests**
**sub-dectector**
**as part of full detector**
**possible CR running**
**Have different goals**
**test/fix/maintain individual boards**
**develop system expertise**
**test/fix/maintain full system**

- September 24, 1998

## Software cont.

**Bench Tests**
**traditionally used PC, bit3 and windows /excel based software **
**need users (technicians & engineers) to be able to understand and modify software**

**Full system tests**
**want to run within full D0 system**
**run Examine’s and Calib’s with ON-LINE**
**Partial systems**
**gray area between bench and full system**
**in use / development at lab 3**

- September 24, 1998

## Infrastructure Required

**Bench Tests**
**PC**
**Trigger / clock generator**
**Input generator**
**Output capture**
**Group will provide**
**software / firmware**
**test fixtures**
**procedures**
**Need -**
**Physicists for system design / data analysis**
**PC based software help**

- September 24, 1998

## Infrastructure Required

- * Need new bodies for these outside of present group

**Full system tests**
**trigger generation**
**SCL ****(clock and control)**
**DAQ**
**Online**
**Group will provide**
**special trigger generator hardware**
**test fixtures**
**D0 provides**
**online system and software**
**examine and calib shells**

**Need* **
**MC Track generation software**
**MC Cluster generation software**
**(for CR) found-tracks to survey to new trigger-equations**
**Examine & calib software**
**help with special firmware**

- September 24, 1998

## Summary

**Hardware will arrive relatively late**
**Much work between production of hardware and running**
**A lot of support and fixture hardware needs to be designed and built **
**- Schedules will suffer without needed EE support.**
**A lot of support software needs to be written, and shaken out **
**- Schedules will suffer without needed PH support.**

- September 24, 1998