# Presentation: 473533

## Valerio Re, Massimo Manghisoni
Università di Bergamo and INFN, Pavia, Italy

Jim Hoff, Abderrezak Mekkaoui, Raymond Yarema
Fermi National Accelerator Laboratory

Lodovico Ratti 
Università di Pavia and INFN, Pavia, Italy

***Università di Bergamo and INFN, Pavia, Italy***
**Jim Hoff, Abderrezak Mekkaoui, Raymond Yarema**
***Fermi National Accelerator Laboratory***
**Lodovico Ratti **
***Università di Pavia and INFN, Pavia, Italy***

- IEEE Nuclear Science Symposium, Puerto Rico, October 24 – 27, 2005

- FSSR2, a Self-Triggered
- Low Noise Readout Chip
- for Silicon Strip Detectors

## The FSSR2 chip

- Mixed-signal integrated circuit for the readout of silicon strip detectors
- Final step of R&D effort begun with the design of the prototype chip FSSR
- TSMC 0.25 μm CMOS technology with enclosed NMOS for radiation tolerance
- 128 analog channels, address, time, and magnitude information for all hits
- Fast, self-triggered readout architecture with no analog storage, very similar to the FPIX2 chip (front-end for pixels in the BTeV experiment)
- Designed for the BTeV Forward Silicon Tracker, FSSR2 is suitable for a wide range of applications with microstrip detectors

## Major requirements

- Data driven architecture – no trigger
- Operation at 132 ns (2% strip occupancy), 264, or 396 ns    (6 % strip occupancy)  beam crossing
- Tolerance to total ionizing dose (5 Mrad) and single event effects (SEU)
- Equivalent Noise Charge (ENC) < 1000 e rms @ CD = 20 pF
- Threshold dispersion < 500 e rms
- Power < 4 mW/channel

## The FSSR2 chip

- 7.5 mm x 5 mm, input pads with 50 m pitch

## FSSR2 block diagram

- FSSR2 Core
- 128 analog channels
- 16 sets of logic, each handling 8 channels
- Core logic with BCO counter (time stamp)
- Programming Interface (slow control)
- Programmable registers
- DACs
- Data Output Interface
- Communicates with core logic
- Formats data output
- Same as BTeV FPIX2 chip

## Analog channels

## Analog channels

- Preamplifier
- NMOS input device, W/L = 1500/0.45, ID = 500 A
- Programmable charge sensitivity
- Integrator and shaper
- Unipolar 2nd order semigaussian shaper
- Four programmable shaping times (65, 85, 100, 125 nsec)
- Base Line Restorer
- Cancellation of the baseline shift due to the tail in the shaper output signal
- The BLR is selectable, so that it can be used only when signal occupancy is high
- Discriminator
- Binary information (hit / no hit)
- Programmable differential threshold (chip wide)
- 3 bit Flash ADC
- Pulse amplitude information for detector monitoring and calibration

## Digital section

**Digital section**

- Programming Interface
- Accepts commands and data from serial input bus
- Programmable registers hold input values for DACs providing reference currents and voltages to the core (discriminator thresholds, test signal amplitude,...)
- Data Output Interface
- Serializes data from the core and transmits data off chip
- Programmable number of output LVDS lines (1, 2, 4, 6)
- Maximum data transmission rate 840 Mb/s
- Output data word includes 3 bits for ADC pulse amplitude information, 5 bits for the logic set number, 4 bits for strip number and 8 bits for hit BCO number (time stamp)

## Test results

- The chip is fully functional and meets all specifications
- Power dissipation is 4 mW/channel
- The chip has been operated with a 70 MHz readout clock to provide 840 Mb output data rate.
- Threshold dispersion = 300 e rms
- 	(with BLR, high gain setting)
- ENC = 800 e rms
- 	(CD = 20 pF, peaking time = 85 nsec, with BLR)

## Shaper output response

**Sh****ap****er output response**

**Charge sensitivity at shaper output:**
**Low gain: 120 mV/fC**
**High gain: 160 mV/fC**

## Baseline restorer 

**Baseline restorer **

## Equivalent Noise Charge

**Equivalent Noise ****Charge**

## Equivalent Noise Charge

**Equivalent Noise ****Charge**

**The BLR improves the threshold dispersion               (AC coupling), but increases noise **
**However, ENC is well below the spec value of 1000 e rms at       C****D**** = 20 pF.**

## Radiation tolerance

**FSSR prototype**
- Irradiation with 27 MeV protons to a 1.9x1013 cm-2 fluence, corresponding to a total ionizing dose of 5 MRad
- After irradiation the chip remains fully functional with very little          (< 10 %) degradation of critical parameters such as ENC and threshold dispersion
**FSSR2**
- Irradiation with 60Co -rays to a total ionizing dose of 20 Mrad        (no bias applied during irradiation)
- Chip fully functional after irradiation; noise and charge sensitivity are not affected
- Threshold dispersion with BLR selected increases by about 15 %               (remains below the spec value of 500 e rms)

## Conclusions

- The 128-channel chip FSSR2 was designed and successfully tested.
- The device is fully functional and meets demanding specifications in terms of noise and threshold dispersion
- Because of its low noise, radiation tolerance and high data output bandwidth and of the flexibility provided by the various programmable features, FSSR2 can operate in different experimental environments and applications
- FSSR2 is being evaluated in view of its possible operation for detector readout in a tracking system providing information to a first level trigger for both fixed target and collider experiments

## Backup slides

## Baseline restorer

**Baseline restorer**

- Shaper output has small overshoot.
- Overshoot causes unwanted variable offset at discriminator input.
- BLR removes variable offset.

- Input signal discriminator scan _without_ BLR

- Input signal discriminator scan _with_ BLR

## Baseline restorer

**Baseline restorer**

## Threshold dispersion

**Threshold dispersion**

## Output data format

**Output data format**