# Presentation: 584513

## AGENDATuesday, January 14

**Introductions****	****	****	****        SwRI****	****	****13:00**
**Requirements Overview****	****	****M. Epperly/SwRI****	****	****13:05**
**CIDP Description ****	****	****M. Epperly/SwRI ****	****	****13:15**
**CIDP/SI Electrical Interfaces ****	****M. Epperly/SwRI ****	****	****13:45**
**CIDP/SI Data Protocols ****	****	****M. Epperly/SwRI ****	****	****14:15**
**CIDP/SCU Electrical Interfaces ****	****M. Epperly/SwRI ****	****	****14:45**
**CIDP/SCU Data Protocols****	****M. Epperly/SwRI ****	****	****15:15**
**CIDP Power Supply ****	****	****M. Epperly/SwRI ****	****	****16:00**
**Processor Module ****	****	****M. Epperly/SwRI ****	****	****16:15**
**Comm/Memory Module ****	****	****M. Epperly/SwRI ****	****	****16:30**
**Instrument Interface Module ****	****M. Epperly/SwRI ****	****	****16:45**
**Power Distribution Module****	****M. Epperly/SwRI****	****	****17:15**

## AGENDAWednesday, January 15

**Software Description****	****	****R. Killough/SwRI****	****	****08:30**
**CIDP Mechanical Interfaces****	****Kelly Smith/SwRI****	****	****10:00**
**Ground Equipment****	****	****M. Epperly/SwRI****	****	****11:00**
**Verification****	****	****	****M. Epperly/SwRI****	****	****11:15**
**Discussion/Action Items****	****	****            All****	****	****11:45**

## Introductions

## CIDP Requirements Overview

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## CIDP Requirements

**Collect science telemetry from each SI**
**Provide spacecraft pointing information to each SI**
**Nadir**
**Solar**
**Command and Control SI**
**Stored command table**
**Real time commands**
**Loads and dumps**
**Error response and safing**

## CIDP Requirements (Contd.)

**Compress SI data **
**Utilize CCSDS recommended algorithm**
**Estimate better than 1.6:1 lossless compression**
**Format SI data into CCSDS Source Packets**
**Segmented packet**
**Fixed Length**
**Transmit data across 1553**
**Several Subaddresses**
**Sent at 10 Hz Rate (controlled by SCU)**

## CIDP Description

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## VME Backplane

- SWITCHED +28V & RETURN

- DC/DC POWER
- CONVERTER
- SUBSYSTEM
- Module

- RAD6000-SC
- CENTRAL
- PROCESSOR
- Module

- COMMUNICATIONS/
- MEMORY
- Module

- 32 KB
- PROM

- 4 MB
- EEPROM

- +15

- -15

- +3..3

- +5

- ETHERNET

- 1553

- SCSI

- RS-232

- COP

- INSTRUMENT IF Module

- RPI
- ADM

- RPI

- LENA

- MENA

- HENA

- FUV

- EUV

- RS-422 Serial IF,
- δφ SYNC PULSES

- SI POWER IF Module

- HTR
- ASSY’S

- RPI
- ADM

- RPI

- LENA

- MENA

- HENA

- FUV

- EUV

- Switched 28V, Thermistors
- Power monitoring

- Double Buffer
- Data Memory

- GSE*

- SCU

- GSE*

- GSE*

- GSE*

- PDU

- *Used only for Lower Level Test and S/W Development

- PDU
- +28V

## CIDP Chassis

## CIDP General Description

**RAD-6000 Central Processor Module**
**LMFS Radiation hardened CPU**
**64 Mbyte DRAM (reduced from 128 Mbyte to conserve power)**
**Clock may be reduced to approximately 5 MIP to conserve power**
**Communications/Memory Module**
**Modification of SSFF Comm/Mem board**
**4 Mbyte EEPROM**
**32 Kbyte PROM**
**MIL-STD-1553 Interface**
**Ethernet interface in ground units only to aid S/W development effort**
**Instrument Interface Board**
**Serial Interface to each SI**
**Dual Port Memory**
**SYNC Interface to each SI**
**Radial ADM interface**

## CIDP Description (Contd.)

**Power Distribution Module**
**Provides switched power to each SI**
**Provides switched power to deckplate heaters**
**Interface to deckplate thermistors**
**Provides redundant switched power to axial ADM**
**Application of +28V initiates deployment (melts wax)**
**First motion indication**
**Deployment pulses**
**Power Supply Module**
**Provides power for use by CIDP**
**+/- 15V**
**+3.3 V**
**+5 V**
**Chassis**
**Based on SSFF Design**

## CIDP Electrical Interfaces

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## Spacecraft Power

**Peak CIDP plus SI power estimated at 300 Watts (~10A)**
**Single switched supply from SCU with multiple wires**
**Normal Density 9-pin connector to SCU power supply module**
**One shield and 4 each +28V and +28VRET wires**
**Normal Density Size 20 contacts rated for 7.5 amperes, nominal**
**4 pins provides a nominal 30 ampere capability (w/o derating)**
**CIDP and SIs will operate with the +28V S/C power characteristics as described in SCU EID.**

## CIDP/SI Electrical Interfaces

**CIDP transmits and receives data to/from each SI via a dedicated serial interface**
**38,400 baud, 8 data bits, no parity**
**Differential RS-422**
**Synchronization information provided by CIDP to each SI**
**Time code transmitted after ****δφ ****359**
**Valid time at nadir pulse (****δφ**** ****360)**
**Nadir indicated by double pulse**
**Solar view indicated by triple pulse**
**Switched +28V and return**
**CIDP monitors instrument current and reports in housekeeping telemetry**
**CIDP limits ADM, SI and heater currents**

## SYNC Pulse Timing

- SYNC

- NADIR

- DELPHI (δφ)

- Double Pulse - Nadir

- SYNC, DATA, ETC, WORD COUNT

- SYNC, DATA, ETC, WORD COUNT

- RPI-tx

- MENA-tx

- HENA-tx

- LENA-tx

- FUV-tx

- EUV-tx

- SYNC, DATA, ETC, WORD COUNT

- SYNC, DATA, ETC, WORD COUNT

- SYNC, DATA, ETC, WORD COUNT

- No Data Code (Multiple Revolution Integration)

- Triple Pulse - Solar

## Serial Data and SYNC Interface

**TX+**

**TX-**

**CIDP Transmit**
**Data**

**SI**

**CIDP**

**RX+**

**RX-**

**CIDP Receive**
**Data**

**26C31**

**26C32**

**SYNC+**

**SYNC-**

**CIDP SYNC**
**Data**

**26C31**

## CIDP/SCU Electrical Interfaces

**Minimized interface between CIDP and SCU**
**MIL-STD-1553 Interface for commands and data**
**SCU is Bus Controller**
**CIDP is Remote Terminal**
**Single Switched +28V and Return for deckplate**
**Multiple wires for redundancy and capacity**
**CIDP distributes power to all deckplate subsystems**
**SI**
**ADM**
**Heaters**

## CIDP ADM Interfaces

**The CIDP controls the axial and radial antenna deployment mechanisms**
**CIDP provides pulses to radial ADMs**
**CIDP provides +28V to axial ADM to initiate deployment**
**Redundant circuits**
**Wax actuators**
**Radial ADM deployment feedback**
**Four per revolution micro-switch**
**Full deployment micro-switch**
**Axial ADM deployment feedback**
**First motion micro-switch**
**Deployment pulses micro-switch**

## CIDP/Radial ADM Interface Circuitry

_**CIDP/Radial ADM Interface Circuitry**_

**ADMCK+**

**ADMCK-**

**ADM**
**Clock Pulses**

**DCU**

**CIDP**

**26C31**

- +5V

- +5V

- 54HCT14

- ADM REV
- MICROSWITCH

- ADM FULL
- DEPLOY
- MICRO-SWITCH

- MICRO-SWITCH
- COMMON

## CIDP/Axial ADM Deployment Circuitry

- +5V

- +5V

- 54HCT14

- ADMZ REV
- MICROSWITCH

- ADMZ
- FIRST MOTION
- MICRO-SWITCH

- MICRO-SWITCH
- COMMON

**ADMZ**

**CIDP**

- +28V

- ADMZ COIL #1

- ADMZ COIL #2

- COMMON RETURN

- +28VRET

- SWITCH

- SWITCH

## Heater Electrical Interface

_**Heater Electrical Interface**_

**Deckplate heaters have redundant mechanical thermostats to hold temperature at low limit of operating range**
**CIDP can detect mechanical thermostat closure**
**Thermistors located throughout deckplate provide input to CIDP**
**CIDP can turn on each heater, bypassing the mechanical thermostat**

- HEATER

- +28VRET

- MECHANICAL
- THERMOSTAT

- +28V

- Solid State
- Switch

- Control

- 1 mA
- Source

- 8:1
- Ana Mux

- 8:1
- Ana Mux

- +

- AMP02

- -

- AD
- 574

- CIDP   Deckplate

- Divider

## CIDP Data Transfer Protocols

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## CIDP/SI data transfer types 

**CIDP to SI Commands and Loads**
**CIDP receives parsed commands from SCU**
**Each SI is assigned a unique 1553 subaddress**
**CIDP transfers 64 byte 1553 frame to SI without preprocessing**
**CIDP queues SI stored commands and sends at appropriate time tag**
**SI to CIDP Service Requests**
**SI can request action from CIDP**
**SI to CIDP HK Telemetry**
**SI can provide CIDP with housekeeping telemetry values**
**All HK Telemetry is uncompressed**
**SI to CIDP Raw Data**
**CIDP buffers raw data**
**Compresses if necessary**
**Packetizes and forwards to SCU without further processing**

## Raw Data Protocol

**SI synchronizes transmissions with observatory rotation (nadir pulse)**
**SI must transmit a full package of data between nadir pulses**
**Header based SI packet structure**
**No Data Code - transmitted to CIDP if there is not data this rev.**
**Packet Header - informs CIDP data is present**
**Request Header - Tells CIDP service request is in packet**
**HK Header - Separates SI HK telemetry from raw data**
**Raw Data Header - Tells CIDP that raw data follows**
**Each header is followed by a word count to allow CIDP to parse packet**
**Entire packet terminated with a checksum**
**Packet may be made up of Request, HKTEL, Raw Data or any combination of the three**
**CIDP verifies packet structure with checksum and word counts**

## Raw Data Protocol Examples

- Valid Data Header

- Packet Word Count

- CIDP Request Header

- Request Word Count

- Request

- HK Telemetry Header

- HKTEL Word Count

- Valid Data Header

- Packet Word Count

- HK Telemetry Header

- Valid Data Header

- Packet Word Count

- Raw Data Header

- HK Telemetry

- Raw Data Header

- Raw Data Word Count

- Raw Data

- Checksum

- HKTEL Word Count

- Raw Data Word Count

- HK Telemetry

- Raw Data Header

- Raw Data

- Checksum

- Raw Data Word Count

- Raw Data

- Checksum

## Maximum packet sizes (per rev)

**CIDP double buffer size is 500 Kbytes per revolution (1M total)**
**Allocations based on EID estimates raised to a binary multiple**
**SI may use full allocation as long as transfer is complete before next nadir pulse**

## CIDP Service Request

**There may be instances where an SI desires action from CIDP**
**Mnemonics will be provided by each SI and coordinated with CIDP**
**Possible Mnemonics (suggestions only)**
**PR****	****Position Report****	****Provide latest Ephemeris data to SI**
**TC****	****Time Check****	****Provide SI with current time**
**PD****	****Download****	****Used If CIDP is queuing data to SI**

## SI Housekeeping Telemetry 

**CIDP extracts SI HKTEL from the revolution double buffer**
**CIDP inserts SI HKTEL into HKTEL source packet and forwards to SCU **
**Capability for action by CIDP based on HKTEL values**
**If required, SI must coordinate with CIDP team**
**Should be minimized due to latency of action (up to 120 seconds)**
**Autonomous SI activity is preferable**
**HKTEL format to be defined by SI and provided to ground segment**

## Command Protocol

**CIDP does not directly command SI**
**All commands are from ground**
**SCU strips overhead and determines recipient**
**SCU forwards command to appropriate 1553 subaddress**
**Real time commands are 64 words maximum (one 1553 frame)**
**All commands have time tag**
**Time Tag = 0 ****	****Real time command**
**Time Tag > 0****	****Stored Command**
**CIDP pulls command from 1553 interface and forwards to SI**
**SI stored command time tag is parsed by CIDP **
**CIDP stores SI commands in its stored command queue**
**When time tag expires, CIDP forwards commands to SI**
**Command formats are defined by each SI and provided to ground segment **

## 1553 Interface

**Interface uses multiple subaddresses to coordinate data transfers**
**Time/Ephemeris Frame Subaddress**
**SCU sends T/E frame every 100 msec.**
**Time accurate to 100 usec**
**New attitude information (quaternions and rate) every 200 msec.**
**Sixteen Source Data Subaddresses**
**Ping Pong buffer - changes when CIDP receives T/E frame**
**CIDP fills 8 subaddresses with data every 100 msec**
**SCU reads opposite 8 subaddresses every 100 msec**
**Two HKTEL Subaddresses**
**Ping Pong Buffer**
**Read every 200 msec**
**Seven Command Subaddresses**
**One for each SI**
**One for CIDP**

## 1553 Subaddress Allocation

**SCU to CIDP Subaddress Allocation**

**CIDP to SCU Subaddress Allocation**

## CIDP/SCU Data Protocols

**All data from CIDP to SCU follows CCSDS recommendations for Version 1 source packets**
**Segmented fixed length packets**
**Unique application ID for every SI**
**CIDP formats 2 fixed length packets every 100 msec**
**Each packet is 256 bytes long**
**Placed in 8 subaddresses of 1553  memory**
**SCU reads previous 8 subaddresses data every 100 msec **
**CIDP formats 1 fixed 64 byte HKTEL packet every 200 msec**
**Placed in 1 of two subaddresses and read by SCU**

## CIDP/SCU Data Flow Example

- Raw RPI Data 128,800 bytes/rev

- Packet ID

- Seq Ctrl

- Length

- Sec. Hdr. (Obs. Time)

- 16
- 2

- 16
- 2

- 16
- 2

- 48
- 6

- 1553
- Frame

- Raw RPI data - 128,800 bytes
- Raw HK Data
- collected every 120 seconds

- 2 RPI Source Packets - 256 bytes each
- formatted every 100 msec
- 1 HK Source Packet - 64 bytes
- formatted every 200 msec

- 2 RPI Source Packets split into 8 32 word
- frames transmitted every 100 msec
- 1 HK Source Packet in 1 32 word
- frame transmitted every 200 msec

- Packet ID

- Seq Ctrl

- Length

- Secondary Header (Obs. Time)

- Two Segmented Source Packets

- IMAGE Transfer Frame made from 4 SI Source Packets and 1 HK Source Packet created every 200 msec

- 1100 bytes
- 8800 bits

- Header

- 96
- 12

- 16
- 2

- 16
- 2

- 16
- 2

- 48
- 6

- 1952
- 244

- RPI Data

- 1952
- 244

- 8192
- 1024

- H-EP

- RPI Data

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- 1553
- Frame

- HK Telemetry

- Header

- RPI Data

- Two Segmented Source Packets

- 512
- 64

## Synchronization 

**Transferring large quantities of data across a 1553 interface requires some form of “throttling” **
**100 msec service routine selected**
**SCU transmits a Time/Ephemeris frame across 1553 every 100 msec**
**Latencies will be measured on the ground and removed with software**
**Time/Ephemeris contains time, position, and status information**
**6 bytes of observatory clock time (maintained by SCU)**
**16 bytes of inertial attitude information in Quaternion format**
**12 bytes of rate information**
**1 byte indicating which side of the double buffers the SCU will be reading during this 100 msec period**

## CIDP/SCU Data Transfer

- Transmits
- T/E Frame

- Receives
- T/E Frame

- Reads
- Subaddresses
- 10-17

- Fills Subaddresses
- 18-25 with
- SI Data Packets

- TIME

- t

- t + 100 msec

- Fills
- Subaddress 26
- with HK packet

- Transmits
- T/E Frame

- Reads
- Subaddresses
- 18-25

- Receives
- T/E Frame

- Fills Subaddresses
- 10-17 with
- SI Data Packets

- Reads
- Subaddress
- 26

- Transmits
- T/E Frame

- Receives
- T/E Frame

- Reads
- Subaddresses
- 10-17

- Fills Subaddresses
- 18-25 with
- SI Data Packets

- Fills
- Subaddress 27
- with HK packet

- Transmits
- T/E Frame

- Reads
- Subaddresses
- 18-25

- Receives
- T/E Frame

- Fills Subaddresses
- 10-17 with
- SI Data Packets

- Reads
- Subaddress
- 27

- SCU

- CIDP

- SCU

- CIDP

- t + 200 msec

- t + 300 msec

## CIDP Power Supply Module

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## CIDP Power Supply

**CIDP power supply is uses Interpoint power supply modules **
**Candidate Supply Modules**
**Interpoint 5962-9316301HXC****	****5V**
**Interpoint 5962-9319301HXC****	****+/-15V**
**Candidate EMI Module**
**Interpoint FME28-461/ES****	****Imax = 15A**
**Three terminal regulate creates +3.3 from 5 volt supply**
**Common buy parts for economy**

## Processor Module

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## Functional Block Diagram

## Characteristics and Features

**Proven 32-bit flight computer**
**Radiation hardened 32-bit RISC Super Scalar single chip CPU**
**Up to 128 Mbytes DRAM with internal DRAM ECC and system level EDAC**
**External interfaces: VME, RS-232, COP, and POWER (5V and 3.3V)**
**Performance:****	****20 MIPS @ 20 MHz **
**Size:****	****	****7.85” x 8.99”**
**Weight:****	****< 1 Kg**
**Power:**
**Full power mode: ****	****13.17 W @ 20 MHz,  nominal voltage, VME active**
**Low power mode:****	****2.43 W @ 2.5 MHz, nominal voltage, VME inactive**
**Radiation hardness:****	****Total dose > 30 Krad (Si), Latchup immune**
**Reliability:****	****	****0.981 (Space environment, full power, 25C, 2 year)**

## RAD 6000-SC Processor Components

## RAD 6000-SC Components Descriptions

_**Memory Interface Unit**_**	****Organizes accesses to and from local memory ****	****	****	****	****and provides RAM data to the cache unit**
_**Cache Unit**__**	**__**	**_**Coordinates accesses to the cache**
_**Instruction Buffer Unit**_**	****Pulls instructions from the cache and dispatches ****	****	****	****instructions to the fixed point, floating point, and****	****	****	****in page fetcher (branch instructions)**
_**Fixed/Floating Point**_**	****Provides separate pipelined execution units for ****	****	****	****their respective instruction types**
_**I/O Sequencer**__**	**__**	**_**Interfaces to RSC I/O bus and provides for ****	****	****	****	****initialization of the processor at start up**
_**Pipeline Control Unit**_**	****Controls proper sequencing and interlocking****	****	****	****	****operation of the other processor functional units**
_**COP Unit**_**	****	****Interfaces with external test equipment and assists ****	****	****	****in the resetting and initialization of the processor****	****	****	****registers and arrays**

## RAD 6000-SC Interfaces

**Memory Bus**
**64 data bits wide plus 8 ECC bits (direct to HMC)**
**24 address bits (interface to CELLA)**
**7 control signals (interface to CELLA)**
**RSC Input and Output Bus**
**32 multiplexed address and data bits**
**1 parity bit for address/data**
**14 control signals**
**17 external interrupts**
**Full interface to RBI gate array**
**COP Diagnostic Serial Bus**
**9 bits of control, clock and data**
**Interface only to external test equipment**

## CELLA

_**Decode and Handshake**_
**Decodes RSC memory control signals to determine current operation**
**Generates handshaking signals to the RSC**
**Sends control information to read/write state machines**
**Suspends current command during RSC ECC processing**
_**DRAM Control Logic**_
**Directs sequencing of LUNA control signals for memory read and write operations**
**Selects DRAM row based on input from pipelined address register and IPL/refresh logic**
_**IPL and Refresh Logic**_
**Performs pump-up cycles after POR**
**Provides 2048 refresh cycles every 32 milliseconds**
_**Pipelined Address Register**_** - buffers incoming RSC memory address while previous command completes**
_**DRAM Row/Address Address Mux**_
**Buffers current DRAM address**
**Selects and drives appropriate row/column addresses to the LUNA-C**

## I/O Functional Components - RBI

**RSC Bus Interface (RBI) unit interfaces I/O with RSC I/O Bus protocol**
**checks and generates RSC I/O bus address/data/control/parity**
**Interfaces with IOC and DHS logic**
**Carry out local memory DMA read and write cycles with the RSC processor**
**Controls VME data transfers**
**Contains software programmable and readable control and status registers **
**Maintains 8 byte data buffer for PIO store/read operations**
**Maintains 8 byte data buffer for DMA writes and PIO loads**
**Provides all external interrupts to the RSC processor**
**7 VME interrupts**
**RS-232 interrupts**
**Programmable Real Time Interrupt**
**Provides programming interface to RS-232 data and control registers in CELLA**

## I/O Functional Components - DHS

**Data Hierarchical Steerer (DHS) is responsible for VME data steering and VME interrupt vector storage**
**Controls data alignment for VME transfers**
**Moves the data between the RBI and the VME bus using address and byte count information provided by the IOC**
**2 separate data paths in DHS**
**Input data path moves data from VME bus to the RBI interface**
**Output data path moves data from RBI to VME bus**
**Provides the 32-bit interrupt acknowledge vector address for the VME interrupts generated by the IOC**

## I/O Functional Components - IOC

**Input/Output Controller (IOC) provides MFC interface to the VME bus**
**Decodes VME bus address to select RSC local memory**
**Manages contention between PIO and DMA operations, in conjunction with RBI**
**Requests the VME bus for all PIO VME operations**
**Passes VME interrupts and SYSFAIL to the RBI**
**Generates and acknowledges the MFC initiated VME interrupts**

## RAD 6000-SC Mechanical Configuration

## Comm/Memory Board

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## Communications/Memory Board Overview

**IMAGE Comm/Mem Board is modified SSFF board design**
**16 Mbytes EEPROM with EDAC**
**32 Kbytes CMOS PROM with EDAC**
**One (1) MIL-STD-1553B Compliant Interface**
**One (1) IEEE 802.3 CSMA/CD Compliant Controller (ETHERNET) with a IEEE 10BASE-T Compliant Interface (Non flight units only)**
**Interfaces designed for autonomous operation to off-load the host CPU**
**Built in test capability**
**Latch up immune**

## Comm/Memory Board Block Diagram

## Comm/Memory Board - Memory Section

## Comm/Memory Board - Ethernet Section

## Comm/Memory Board - 1553 Section

## MIL-STD-1553B Short-stub Direct Coupling

## Memory/VME Interface controller and Memory EDAC FPGA

## Communication/Memory Board- Front

## Communication/Memory Board - Back Side

## Instrument Interface Board

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## Instrument Interface Board - Requirements

**Provide two way serial communication between SIs and CIDP**
**Provide data double buffer to off-load processor**
**Provide observatory attitude pulses to each SI**
**Control Deployment of radial antennae**
**Deployment pulses**
**ADM position feedback **
**Provide discrete control of Power Distribution Module**

## Interface Definition and Quantity

**Instrument serial input/outputs****	****	****6**
**Instrument SYNC outputs****	****	****6**
**ADM clock outputs****	****	****	****4**
**ADM positional inputs****	****	****	****4**

## Instrument Interface - Block Diagram

**1 Mbyte Buffer**

**Instrument**
**Interface (1 of 6)**

_**Instrument Interface - Block Diagram**_

- Differential
- Receiver

- Buffer
- #1

- Buffer
- #2

- Async. Rx

- Address
- Counter

- Differential
- Driver

- Async. Tx

- Clock

- δφ Countdown Timer

- δφ Register

- δφ Counter

- Nadir Register

- Solar Register

- Differential
- Driver

- Double &
- Triple
- Pulse
- Generator

- TX+/TX-

- RX+/RX-

- SYNC+/
- SYNC-

**VME**
**IF**
**Logic**

**V**
**M**
**E**
**B**
**a**
**c**
**k**
**p**
**l**
**a**
**n**
**e**

**SYNC**
**Logic**

- NADIR

## Instrument Interface - Electrical Interface (1 of 6)

**TX+**

**TX-**

**CIDP Transmit**
**Data**

**SI**

**CIDP**

**RX+**

**RX-**

**CIDP Receive**
**Data**

**26C31**

**26C32**

**SYNC+**

**SYNC-**

**CIDP SYNC**
**Data**

**26C31**

## Double Buffer Access - State Diagram

- IDLE

- SYSRESET/

- Perform R/W
- WRCOMP = 1

- DSR/

- Prioritze and
- Grant

- !DSR/ +
- CPUREQ

- !DSR/ +
- CPUREQ

**State Diagram Variables**
**DSR/**
**Six different Data Set Ready signals, one from each SI**
**CPUREQ**
**Request from CPU to read from double buffer memory**
**WRCOMP and RDCOMP**
**Handshaking from machine to either one of the serial interfaces, or the VME interface to indicate the action is complete**
**DRDY**
**Signal to shift register machine and status buffer indicating TX buffer is full**

## SI Serial Input State Diagram

- RESET
- ADDCTR

- SYSRESET/

- NADIR

- Write data to
- buffer

- DSR/

- Increment
- ADDCTR

- ERROR

- OF

- !OF & DSR/

- !OF & !DSR/

- IDLE

- !WRCOMP

- DSR/

- WRCOMP

**State Diagram Variables**
**SYSRESET/**
**VME system reset**
**NADIR**
**Pulse from SYNC generator every Nadir crossing**
**DSR/**
**Data set ready from asynchronous receiver state machine**
**WRCOMP**
**Control signal from buffer access state machine indicating that requested write is complete**
**OF**
**Overflow signal, set if SI transmits more words than it is allocated (ADDCTR > ALLOC)**

## Asynchronous Receiver State Machine

- IDLE
- DSR/,OF/,FR =1

- SYSRESET/

- Shift in
- bit #1

- DSR/

- Wait 24
- clocks

- RX

- !RX

- Shift in
- bit #2

- DSR/

- Wait 16
- clocks

- DSR/

- Wait 16
- clocks

- Shift in
- bit #3

- DSR/

- Wait 16
- clocks

- Shift in
- bit #4

- DSR/

- Wait 16
- clocks

- Shift in
- bit #5

- DSR/

- Wait 16
- clocks

- Shift in
- bit #6

- DSR/

- Wait 16
- clocks

- Shift in
- bit #7

- DSR/

- Wait 16
- clocks

- Shift in
- bit #8

- DSR/

- Wait 16
- clocks

- Shift in
- Stop Bit (Bit 9)

- FR/=0

- RX &
- !STOP &
- EMPTY

- STOP

- OF/=0

- RX &
- !STOP &
- !EMPTY

- RX &
- EMPTY

- !RX &
- !STOP &
- !EMPTY

- !RX

- Data to Buffer
- DSR/=0

- EMPTY

- RX &
- !EMPTY

## Asynchronous Receiver State Machine Variables

**DSR/ - Data Set Ready**
**Low when a 8 bit word has been received and is ready to be read**
**EMPTY - Buffer Empty**
**High when RX buffer is empty and ready for contents of shift register**
**FR/ - Frame Error**
**Low when the stop bit was not correct**
**OF/ - Overflow**
**Low if first byte has not been read by CPU, a second byte is held in the shift register, and a third has begun reception, third word is ignored.**
**STOP - Stop Bit**
**Contents of cell 9 in the receive shift register, Low when a full word has been received correctly**
**RX - Receive bit**
**Output of differential receiver **

## Serial Interface - Transmitter State Diagram

- IDLE

- SYSRESET/

- Shift out a
- 0 (start)

- DSR/

- Shift out data
- bits (8 bits)

- Shift out a
- 0 (stop)

- DATA TO S/R
- TXR=0

**State Diagram Variables**
**WR/****	**
**I/O write to TX buffer**
**RD/**
**I/O read from status buffer**
**TXR/**
**Signal from shift register machine indicating it has loaded current word**
**DRDY**
**Signal to shift register machine and status buffer indicating TX buffer is full**
**TOF**
**Overflow signal, set if CPU attempts to transfer data into a full buffer, provided to CPU in status register, cleared by read of status register**

- DRDY

- !DRDY

- IDLE
- TOF,DRDY = 0

- WR/

- Load Buffer
- DRDY = 1

- !WR/

- WR/ &
- TXR

- !TXR

- !WR/

- ERROR
- TOF = 1

- RD/

- RD/

## SYNC Generation - Detailed Block Diagram

- δφ Counter

- Single,Double &
- Triple Pulse
- Generator

- Compare

- Compare

- Clock

- δφ Countdown Timer

- CO

- LD

- CK

- δφ Register

- Nadir Register

- Solar Register

**VME**
**IF**
**Logic**

**V**
**M**
**E**
**B**
**a**
**c**
**k**
**p**
**l**
**a**
**n**
**e**

## Antenna Deployment Mechanism Interface - Block Diagram

_**Antenna Deployment Mechanism Interface - Block Diagram**_

- Differential
- Driver

- Pulse
- Generator

- Rev
- Counter IF

- Counter

- Full
- Deploy IF

- ADMCK+/
- ADMCK-

- ADMREV

- ADMCOM

- ADMFD

- ADM Interface
- (1 of 4)

**VME**
**IF**
**Logic**

**V**
**M**
**E**
**B**
**a**
**c**
**k**
**p**
**l**
**a**
**n**
**e**

## ADM Interface - Electrical Interface (1 of 4)

**ADMCK+**

**ADMCK-**

**ADM**
**Clock Pulses**

**DCU**

**CIDP**

**26C31**

- +5V

- +5V

- 54HCT14

- ADM REV
- MICROSWITCH

- ADM FULL
- DEPLOY
- MICRO-SWITCH

- MICRO-SWITCH
- COMMON

## Power Distribution Module

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## Power Distribution Module - Requirements

**Board provides switched power**
**Each SI**
**Radial ADMs (via the DCU)**
**Axial ADM**
**Heaters**
**Board collects telemetry**
**SI current**
**Thermistor Data**
**Axial ADM deployment**
**Solid State Switching Circuit**
**Opto-isolators maintain isolation of signal grounds and power returns**

## Power Distribution Module - Block Diagram

_**Power Distribution Module - Block Diagram**_

- S/S Power Switch

- LENA

- MENA

- HENA

- EUV

- FUV

- RPI

- DCU

- ADMZ1

- ADMZ2

- HTR1

- S/S Power Switch

- S/S Power Switch

- S/S Power Switch

- S/S Power Switch

- S/S Power Switch

- S/S Power Switch

- S/S Power Switch

- S/S Power Switch

- S/S Power Switch

- HTR2

- S/S Power Switch

- HTRn

- S/S Power Switch

- ADMZ Position

- ADMZ

- Analog Mux

- To Thermistors

- Analog Mux

- ADC

- 1 mA Source

- Control

- Current
- Monitoring

**Control**
**from**
**IIM**

**V**
**M**
**E**
**B**
**a**
**c**
**k**
**p**
**l**
**a**
**n**
**e**

## SI Power

**CIDP utilizes solid state switches**
**All +28V goes through CIDP EMI Filter **
**Each SI provided with its own switched +28V power**
**Primary Return is common to all SIs and CIDP**
**Return is not attached to signal ground or chassis ground within any SI or the CIDP**

## Power Distribution Module - Current Monitor

- Current
- Sensing
- Resistor

- 1K

- 1K

- 50K

- 2200 pF

- 220 pF

- 1 M

- 100

- .33 uF

- 2M

- 2M

- 1 M

- 220 pF

- Values are typical

## DCU Power

**Power for the axial ADMs is supplied to the DCU by the CIDP**
**Power is enabled only during deployment periods**
**Utilizes same switching and monitoring circuit as SI power**
**Single supply on multiple wires for current capacity and redundancy**

## Axial ADM Power Distribution and Feedback

**Axial ADM uses thermal wax deployment actuators**
**Actuator contains two heater coils which melt wax initiating deployment**
**Only one coil powered at any time**
**First deployment micro-switch**
**Power removed as soon as first deployment is detected**
**Second micro-switch opens and closes 600 times during axial deployment**
**Heater coils controlled with same power switching circuit as used for SIs and DCU**

## Software Description

**Ron Killough**

## CIDP Mechanical Interfaces

**Kelly D. Smith**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## Packaging Concept

**Based on SSFF CCU and IRCU chassis**
**Common Design to be shared with RPI**
**Circuitry contained in easily removed modules**
**Modules have modified VME configuration**
**Package designed for conductive cooling**
**Package fabricated from aluminum to provide good thermal path and minimal weight**
**Package and modules are mounted with captive fasteners**

## Mass Properties

**Conduction cooling**
**5 electronic modules**
**3 spare slots**
**Captive mounting screws**
**Mounting alignment pins**
**Finish: White Chem-Glaze**

## Material and Construction

## Thermal Analysis

**Kelly D. Smith**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## Structural Analysis

**Kelly D. Smith**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## Ground Equipment

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## CIDP Ground Equipment Requirements

**Simulate 6 SI serial interfaces with realistic data quantities and rates**
**Analyze SYNC pulses for accuracy**
**Simulate SCU/CIDP command interface**
**Simulate CIDP/SCU data interface**
**Simulate ADM feedback**
**Simulate SI, ADM and heater power loads**
**Simulate Thermistor inputs**

## CIDP

- ETHERNET
- IF Card

- PC-1553
- BCRT Card

- Rack Mounted PC

**200 MHz Pentium**
**SVGA Monitor**
**3.5 Gbyte Hard Drive**
**Parallel/Serial Port**
**3.5” Floppy**
**Software**
**Windows 95 or NT**
**NAV 1553 Controller**
**Turbo C++**
**Lab Windows**

- To Worksatation

**Provides COTS BC functions for simulating SCU/CIDP Communication**
**Provides Windows based data pipe between Ethernet and 1553**
**Provides expansion capabiltiy through user written software**
**Workstation runs ASIST Integration & Test System from GSFC**

- Dual RS-422

- Dual RS-422

- Dual RS-422

- RS232

## CIDP

**COTS RS-422 interface to CIDP**

- ETHERNET
- IF Card

- PC-1553
- BCRT Card

- Rack Mounted PC

**200 MHz Pentium**
**SVGA Monitor**
**3.5 Gbyte Hard Drive**
**Parallel/Serial Port**
**3.5” Floppy**
**Software**
**Windows 95 or NT**
**NAV 1553 Controller**
**Turbo C++**
**Lab Windows**

- Dual RS-422

- Dual RS-422

- RS232

- Dual RS-422

## CIDP

- SI Load Simulator

- SYNC Pulse Analyzer

- 6 Differential
- Receivers

- ADM Simulator

- 6 Differential
- Receivers

**Provides resistive loads to all switched power outputs from CIDP**
**Monitors voltage on each line**
**Generates simulated thermistor outputs**

## CIDP

- SI Load Simulator

_**Custom Equipment - SYNC Pulse Test Equipment**_

- SYNC Pulse Analyzer

- 6 Differential
- Receivers

**Custom Hardware used to aquire SYNC pulses and forward to PC for analysis**

- ADM Simulator

- 6 Differential
- Receivers

## CIDP

- SI Load Simulator

- SYNC Pulse Analyzer

- 6 Differential
- Receivers

- ADM Simulator

- 6 Differential
- Receivers

_**Custom Hardware - ADM Simulator**_

**Custom Hardware used to aquire acquires clock signals from CIDP and generates feedback signals emulating ADM deployment**

## CIDP

- ETHERNET
- IF Card

- PC-1553
- BCRT Card

- Rack Mounted PC

**200 MHz Pentium**
**SVGA Monitor**
**3.5 Gbyte Hard Drive**
**Parallel/Serial Port**
**3.5” Floppy**
**Software**
**Windows 95 or NT**
**NAV 1553 Controller**
**Turbo C++**
**Lab Windows**

- Dual RS-422

- Dual RS-422

- Dual RS-422

- RS232

- Ethernet to
- Workstation

**COTS RS-232 interface to Processor**
**Ethernet on Comm/Mem board can interface to workstation or PC**

## CIDP Verifications System and Flow

**Michael E. Epperly**
**Instrumentation and Space Research Division**
**Southwest Research Institute**

## Preliminary Instrument Design and Test Environments

**Radiation Dose Depth Curve**
**Sinusoidal Vibration**
**Acoustic Vibration**
**Random Vibration**
**Pyrotechnic Shock**
**Thermal Cycling**
**Thermal Vacuum **

## Radiation Dose

**Reference EM NO. S-8089-SYS-003 for dose depth curve**
**CIDP will apply a radiation dose margin of 2 for electronic component selection**
**Spacecraft profiles an equivalent shielding of 0.02” Al**
**CIDP chassis to provide a minimum of 0.2” Al shielding**

## Sine and Random Vibration Tests

**CIDP will be vibrated to qualification levels**
**Sine****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	**
**Random****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	****	**
**Acoustic Levels per EM NO. S-809-SYS-003****	**

## CIDP TV Test Profile

- 24 hr
- bake out

- Hot
- Start

- Cold
- Start

- Non-operational
- cold soak

**8 hour hot and cold dwells**
**Powered transitions**

- +40

- +60

- -40

- -20