# Presentation: 764629

## ISI & NASA/Goddard RHBD Program Review MeetingFebruary 18, 2005

## Agenda

- 11:00 - Introduction  (Damoulakis)
- 11:05 - Overview of Test Needs (Ken LaBel)
- Low Cost Test Needs
- High Speed Test Needs
- 11:15 - Team Responsibilities & Partnerships (Jim Howard)
- Managerial Topics - Team, Responsibilities, Partnerships
- Testing - How & Why
- Functional/Facilities/Usage
- DUT Independence
- Design Flows
- 11:35 - Low Cost/Speed Tester (Hak Kim)
- Design Overview
- 11:45 - High Speed Tester (Scott Stansberry)
- Requirements
- Design Overview
- Status
- 12:00 – Lunch (provided)
- 12:30 - User I/F & VHDL Modules  (Charles Rogers)
- 12:50 - Test Coupons (Valencia Joyner)
- Describe coupon designs & Tests
- Describe SEU design & Tests
-  1:05 - TID & SEU Test Discussion  (Ken LaBel)
- Cobalt-60 facility and TID testing
- Non-Goddard facilities and SEU testing
- 1:10 - Summary  (John Damoulakis)
- 1:15 – General Discussion Q&A

## Radiation Effects Digital Tester:Why is this needed?

**Kenneth A. LaBel**
**ken.label@nasa.gov**
**Co-Manager, NASA Electronic Parts and Packaging (NEPP) Program**

## Outline

**Test Sources and Constraints**
**Three testers: each has a niche**
**High-speed technologies**
**High-speed “CMOS” generic**
**“****Cheap” tester**
**Charts from June 2004 Kickoff**

## Typical Ground Sources for Space Radiation Effects Testing

**Issue: TID -**
**Co-60 (gamma), X-rays, Proton**
**Issue: Displacement Damage – **
**Proton, neutron, electron (solar cells)**
**SEE (GCR)**
**Heavy ions, Cf**
**SEE (Protons)**
**Protons (E>10 MeV)**
**SEE (atmospheric)**
**Neutrons, protons**

**Wide Field Camera 3 E2V**
**2k x 4k n-CCD in front of Proton Beam at UCDavis**

## Radiation Test Facilities Used BY NASA/GSFC

**Co-60**
**Source at GSFC**
**X-Ray**
**NAVSEA Crane**
**Heavy Ion**
**Texas A&M**
**Brookhaven National Labs**
**Lawrence Berkeley National Labs**
**MSU National Superconducting Cyclotron Lab (NSCL)**
**Proton (SEE)**
**U. of California at Davis**
**Indiana University Cyclotron Facility**
**Mass. General**
**Proton Damage (Materials)**
**Van de Graaff at GSFC**

## Why is a new tester needed?

**Changes in technology**
**Speed and packaging**
**Custom hardware for packaging**
**High speed impacts cabling, thermal, power,...**
**ESD**
**Transients**
**Facilities**
**Remote chamber (air or vacuum)**
**Activation potential (proton irradiation)**
**Secondaries from protons**
**We’ve had secondary neutrons cause failures in “nearby” test equipment**
**Portability**
**Rugged**
**Cost**
**Modern ATE/BERT systems run to the millions and are not very portable**
**BERTs are VERY sensitive to shipping: we have had more issues with non-functioning equipment**

## Philosophy: Three Types of Testers

**Ultra-fast for SiGe, InP, etc...**
**Circuit for Radiation Effects Self-Test (CREST)/Built-in Error Self-Test (BEST)**
**Collaborative effort with DTRA, Mayo, OGA, etc**
**Speed test limited to technology of ICs (current IBM 5hp – 8 GHz, 8hp should be approaching 20 GHz)**
**Test chips need to be 128-bit shift registers**
**Can be used for Boeing/Georgia Tech SiGe test structures**
**High-speed for CMOS**
**Needed for generic high-speed test devices (> 500 MHz I/O)**
**Processors, FPGAs, etc...**
**Problem:**
**Cost per copy (~$20K RE) – if we do proton test, board gets activation/dose and must “cool down” before can be shipped**
**May also fail due to exposure**
**Low-speed (cheap)**
**At ~ $2-3K per copy, essentially throwaway**
**Moderate speed (few hundred MHz)**

## Test Support – CMOS Technology

**CREST/BERT Methodology is adequate when specific shift-register based test structures are available**
**What do you do when “other” structures are available for evaluation?**
**Existing “off-the-shelf” test systems are either**
**Non-portable ($M ATE) or**
**Designed for a few 100 MHz maximum operation**
**Scaled CMOS can operate at much higher internal clock speeds (look at >3GHz Pentiums!)**
**Recent data on CMOS (Benedetto, et al) has shown what the SiGe/GaAs test world has known**
**Higher clock speeds vastly complicate error modes from single particle strikes and test fixturing**
**Even worse when technology speed limit is pushed**
**Question: how do you build a tester that is “Generic” and approach at-speed data collection?**

**From June 2004 RHBD Kickoff Meeting**

## “New” Test System Concept

**“****New” Test System Concept**

**Test system focuses on digital SEE/functionality test**
**Flexible architecture to accommodate unknown test structures (memory, ALU, ring oscillator, etc.)**
**Portable**
**Must be able to decipher SEUs from SETs (at least 1****st**** order)**
**Means at-speed testing with variable input clock**
**Implies local (on-board) data capture)**
**Temperature, power, etc other usual constraints**
**Concept**
**Use the power of state-of-the-art reprogrammable FPGAs as the tester (processing IP)**
**Build 2 versions**
**Daughtercard plug-ins (slower devices)**
**Device under test (DUT) on-board (faster devices)**

**Reprogrammable**
**FPGA device**
**with embedded**
**processor and**
** ****HS serial link**

**Test chip with**
**unknown test**
**structures –**
**socketed/on-board or**
**daughtercard**

**New Generic Tester**

**Digital I/O and other**

**From June 2004 RHBD Kickoff Meeting**

## Test Card Concept

**DUT**
**or**
**BEST**

**Optional SiPo, Level Translators, Drivers/Receivers, etc.**

**Reprogrammable**
**FPGA**

**High-Speed Clock**

**From June 2004 RHBD Kickoff Meeting**

## Agenda

- 11:00 - Introduction  (Damoulakis)
- 11:05 - Overview of Test Needs (Ken LaBel)
- Low Cost Test Needs
- High Speed Test Needs
- 11:15 - Team Responsibilities & Partnerships (Jim Howard)
- Managerial Topics - Team, Responsibilities, Partnerships
- Testing - How & Why
- Functional/Facilities/Usage
- DUT Independence
- Design Flows
- 11:35 - Low Cost/Speed Tester (Hak Kim)
- Design Overview
- 11:45 - High Speed Tester (Scott Stansberry)
- Requirements
- Design Overview
- Status
- 12:00 – Lunch (provided)
- 12:30 - User I/F & VHDL Modules  (Charles Rogers)
- 12:50 - Test Coupons (Valencia Joyner)
- Describe coupon designs & Tests
- Describe SEU design & Tests
-  1:05 - TID & SEU Test Discussion  (Ken LaBel)
- Cobalt-60 facility and TID testing
- Non-Goddard facilities and SEU testing
- 1:10 - Summary  (John Damoulakis)
- 1:15 – General Discussion Q&A

## Project Overview

- Dr. James W. Howard Jr.

## Project Organization

## Partnering

- NASA Electronic Parts & Packaging Program (NEPP)
- Defense Threat Reduction Agency (DTRA)
- Mission Research Corporation (MRC)
- SEAKR

## Facility Issues

- Local High Speed
- Remote Operation
- Vacuum Operation
- Proton Dose
- On DUT
- On Tester

## Tester Philosophy

- Modular - Adaptable/Flexible
- DUT Independence
- Wide variety of devices to test: from simple test structures to microprocessors
- User simplicity
- First Test Vehicle
- Tester qualification
- Proof of capabilities

## Schedule

- Low-Speed Tester
- Initial Test - March 2005
- Delivery to RHBD Program - May 2005
- High-Speed Tester
- Design Complete/Hardware available - April 2005
- Board Support Package completed - May 2005
- Initial Single Event Effects Testing - June 2005
- Delivery to RHBD Program - June 2005
- Tester modifications/updates - August 2005
- All Milestone Dates Are Compatible With RHBD Program Goals

## Agenda

- 11:00 - Introduction  (Damoulakis)
- 11:05 - Overview of Test Needs (Ken LaBel)
- Low Cost Test Needs
- High Speed Test Needs
- 11:15 - Team Responsibilities & Partnerships (Jim Howard)
- Managerial Topics - Team, Responsibilities, Partnerships
- Testing - How & Why
- Functional/Facilities/Usage
- DUT Independence
- Design Flows
- 11:35 - Low Cost/Speed Tester (Hak Kim)
- Design Overview
- 11:45 - High Speed Tester (Scott Stansberry)
- Requirements
- Design Overview
- Status
- 12:00 – Lunch (provided)
- 12:30 - User I/F & VHDL Modules  (Charles Rogers)
- 12:50 - Test Coupons (Valencia Joyner)
- Describe coupon designs & Tests
- Describe SEU design & Tests
-  1:05 - TID & SEU Test Discussion  (Ken LaBel)
- Cobalt-60 facility and TID testing
- Non-Goddard facilities and SEU testing
- 1:10 - Summary  (John Damoulakis)
- 1:15 – General Discussion Q&A

## Low Speed Digital Tester

- Hak S. Kim

## Low Speed Digital Tester

- Description
- Requirement
- Design Approach
- Status
- Issues

## Description

- Tester for Digital Devices
- Low to Medium Speed
- Reusable Hardware and Software
- Minimize Design Time
- Reduce the Cost of Digital Device Test

## Description

- Testing Setup

- Device Under Test
- (DUT)

- Digital Tester

- PC Based
- Controller
- User Area

- Remote Test Location

## Requirement

- Flexible
- Reusable
- Re-programmable FPGA
- Multi I/O Lines
- 200 MHz Parallel

## Requirement

- Use of Industry Standards
- Program –VHDL & JTAG
- Communication to User –RS232 / USB etc.
- User Friendly Interface Software
- Affordable
- Added Features

## Design Approach

- Block Diagram

## Design Approach

- Xilinx Spartan 3 FPGA
- XC3S400, -1000, -1500
- 400K to 1.5M gates (8,064-29,952 Logic Cells)
- Up to 622 Mb/s Data Transfer Rate per I/O
- 264 to 333 (116 to 149 DS) I/Os
- 1.2V to 3.3V I/O Level
- Inexpensive

## Design Approach

- FPGA Programming
- JTAG
- On Board Selectable FLASH ROM
- Communication
- RS232
- USB

## Design Approach

- User I/Os
- 278 Total
- 34 Single / 122 Differential
- 235 Medium / 43 Low Speed
- 233 Dedicated / 45 Shared
- Clock
- 4 Clock inputs (Shared I/Os)

## Design Approach

- Added Features
- On Board SRAM
- Temporary Storage
- 1M x 16 SRAM
- Shared I/Os
- Current Monitor
- 4 Channel ADC with Shunt Resistors
- Re-configurable Gain Amplifiers
- Latch-Up Detection and Alert Signals
- Programmable Latch-Up Thresholds

## Status

- Hardware Design Completed
- PCB Components Being Populated
- FPGA Programming in Progress
- User Interface Software Programming in Progress

## Issues

- Daughter Board Fabrication
- Throwaway Use?
- Need Minimal Changes in Hardware
- VHDL Code Modification
- Different DUT Requires Different Flavor

## Agenda

- 11:00 - Introduction  (Damoulakis)
- 11:05 - Overview of Test Needs (Ken LaBel)
- Low Cost Test Needs
- High Speed Test Needs
- 11:15 - Team Responsibilities & Partnerships (Jim Howard)
- Managerial Topics - Team, Responsibilities, Partnerships
- Testing - How & Why
- Functional/Facilities/Usage
- DUT Independence
- Design Flows
- 11:35 - Low Cost/Speed Tester (Hak Kim)
- Design Overview
- 11:45 - High Speed Tester (Scott Stansberry)
- Requirements
- Design Overview
- Status
- 12:00 – Lunch (provided)
- 12:30 - User I/F & VHDL Modules  (Charles Rogers)
- 12:50 - Test Coupons (Valencia Joyner)
- Describe coupon designs & Tests
- Describe SEU design & Tests
-  1:05 - TID & SEU Test Discussion  (Ken LaBel)
- Cobalt-60 facility and TID testing
- Non-Goddard facilities and SEU testing
- 1:10 - Summary  (John Damoulakis)
- 1:15 – General Discussion Q&A

## Board Need

- This is a general purpose SEU tester capable of testing digital I/O up to 3.125GHz ranges.
- RHBD has a need to test higher bandwidth devices as circuit speeds increase.
- It will be used to test those circuits that are too fast for the low cost tester.
- The design, physical board, and a manual will be provided by ISI to the RHBD community.

## Increasing Clock Speeds

- Slide Courtesy Ken LaBel NGSFC

## High Speed Tester Board

## Requirements

- High and Low Speed I/O
- Eight banks of configurable I/O
- Single ended CMOS 1.5V to CMOS 3.3V levels (configurable via VCCO)
- Differential LVDS capabilty to 840MB/s (on chip termination)
- Sixteen High Speed Rocket I/Os (Rocket I/O 3.125 Gbs)
- SRAM (1Mx16 identical to Low Speed Tester)
- Configurable Voltage Supply & Current Telemetry
- Logic Standards Configurable
- Configurable Voltage Regulator or External Voltage Input
- Power FET shunt w/ fast comparator for latchup shutoff
- A/D and D/A converters (same as Spartan3 tester)
- Clock Speeds Flexible
- RS232, USB, and Ethernet

## Status & Schedule

- Long lead parts identified and on order.
- Schematic capture in progress.
- Design review in late February.
- H/W design complete by March 1.
- H/W fabricated and assembled by April 1.
- Board complete and ready for testing by June 1*.
- First test target is SDRAM.
- Follow on test target possibilities:
- Unspecified higher speed device
- Boeing Chips
- MRC Chips
- *Assumes firmware complete.

## Agenda

- 11:00 - Introduction  (Damoulakis)
- 11:05 - Overview of Test Needs (Ken LaBel)
- Low Cost Test Needs
- High Speed Test Needs
- 11:15 - Team Responsibilities & Partnerships (Jim Howard)
- Managerial Topics - Team, Responsibilities, Partnerships
- Testing - How & Why
- Functional/Facilities/Usage
- DUT Independence
- Design Flows
- 11:35 - Low Cost/Speed Tester (Hak Kim)
- Design Overview
- 11:45 - High Speed Tester (Scott Stansberry)
- Requirements
- Design Overview
- Status
- 12:00 – Lunch (provided)
- 12:30 - User I/F & VHDL Modules  (Charles Rogers)
- 12:50 - Test Coupons (Valencia Joyner)
- Describe coupon designs & Tests
- Describe SEU design & Tests
-  1:05 - TID & SEU Test Discussion  (Ken LaBel)
- Cobalt-60 facility and TID testing
- Non-Goddard facilities and SEU testing
- 1:10 - Summary  (John Damoulakis)
- 1:15 – General Discussion Q&A

## Agenda

- 11:00 - Introduction  (Damoulakis)
- 11:05 - Overview of Test Needs (Ken LaBel)
- Low Cost Test Needs
- High Speed Test Needs
- 11:15 - Team Responsibilities & Partnerships (Jim Howard)
- Managerial Topics - Team, Responsibilities, Partnerships
- Testing - How & Why
- Functional/Facilities/Usage
- DUT Independence
- Design Flows
- 11:35 - Low Cost/Speed Tester (Hak Kim)
- Design Overview
- 11:45 - High Speed Tester (Scott Stansberry)
- Requirements
- Design Overview
- Status
- 12:00 – Lunch (provided)
- 12:30 - User I/F & VHDL Modules  (Charles Rogers)
- 12:50 - Test Coupons (Valencia Joyner)
- Describe coupon designs & Tests
- Describe SEU design & Tests
-  1:05 - TID & SEU Test Discussion  (Ken LaBel)
- Cobalt-60 facility and TID testing
- Non-Goddard facilities and SEU testing
- 1:10 - Summary  (John Damoulakis)
- 1:15 – General Discussion Q&A

## PC Software Program and Common FPGA Code

- Scenarios
- Setup of new DUT test
- Running test (Users/PC perspective)
- Running test on FPGA
- Environment (PC, database, etc)
- Features (high level requirements)

## Scenario: setup a new DUT test

- Define personality module
- DB entries for commands
- DB entries for telemetry
- Define telemetry displays
- Write scripts

## Scenario: Running Test

- Load design bits via JTAG into the FPGA
- Start windows application
- Load personality module to FPGA
- Personality module defines commands, telemetry, etc.
- Load/Run 1st Script file containing setup commands and start command
- View and record results from first test on PC
- Rerun or run additional tests

## Scenario:  Running test on FPGA

- FPGA design is two parts
- Common tester interface
- High Speed DUT specific HW
- HS DUT specific section runs at full speed
- Common PC interface capturing data (slow)
- Last 10 errors
- Total error cnt

## HS Tester

- PC Application

- HS DUT specific
- HW

- HW common
-  tester interface

- Test Interface
- (registers)

- Serial/USB/Ethernet/Other

## PC Application Environment

- Win 2K / Win XP Operating system
- Communication (Serial, USB, Ethernet)
- Database containing personality module definitions (commands, telemetry) (Simple DB`, i.e. Paradox, MS Access, text file)
- Allows one application to be used for multiple tests
- Script processor allows tests to be defined and repeated (JavaScript)

## FPGA Common Interface Environment

- Common Code
- Embedded Xilinx processor (MicroBlaze)
- VHDL IP model
- Communication (Serial, Ethernet, USB)
- Use of hardware IPs
- Personality defines commands, telemetry
- Events (ASCII strings) can be forwarded to application log from HS DUT specific HW
- Interface using memory mapped registers/memory

## HS Tester Features

- Features
- Single Windows PC application that support multiple tests
- Personality module defines all commands and telemetry
- Command are sent to HS  DUT specific HW
- Telemetry received at definable rate from HS DUT specific HW
- Support for repeatable test operation (scripts)
- Store and time-tag received telemetry and commands

## Personality Module Features

- Setup application and DUT interface hardware
- Create personality
- Commands (5 commands with 32 bytes parameters)
- Telemetry (rate, locations, words)
- Add commands, telemetry to application database for display
- *** Simple commands and telemetry/// This is not a full ground system

## Agenda

- 11:00 - Introduction  (Damoulakis)
- 11:05 - Overview of Test Needs (Ken LaBel)
- Low Cost Test Needs
- High Speed Test Needs
- 11:15 - Team Responsibilities & Partnerships (Jim Howard)
- Managerial Topics - Team, Responsibilities, Partnerships
- Testing - How & Why
- Functional/Facilities/Usage
- DUT Independence
- Design Flows
- 11:35 - Low Cost/Speed Tester (Hak Kim)
- Design Overview
- 11:45 - High Speed Tester (Scott Stansberry)
- Requirements
- Design Overview
- Status
- 12:00 – Lunch (provided)
- 12:30 - User I/F & VHDL Modules  (Charles Rogers)
- 12:50 - Test Coupons (Valencia Joyner)
- Describe coupon designs & Tests
- Describe SEU design & Tests
-  1:05 - TID & SEU Test Discussion  (Ken LaBel)
- Cobalt-60 facility and TID testing
- Non-Goddard facilities and SEU testing
- 1:10 - Summary  (John Damoulakis)
- 1:15 – General Discussion Q&A

## Process Monitor/TID Characterization

- Valencia M. Joyner

## OUTLINE

- Current MOSIS Process Monitor
- Process Monitor Coupon Objectives
- Review of Impact Ionization and TID Correlation Techniques
- IBM 130nm Coupon Chip
- Expected Results
- Proposed Migration to 90nm
- Proposed Task on 130nm Library Distribution
- Schedule Status

## Current MOSIS Process Monitor Overview

- IBM 8RF Wafer

- BSIM Array

- Sheet Res.

- Ring Oscillator

-   Capacitor Array
-   Test Inverters
-   Contact Kelvin Bridge
-   Metal Step Coverage
-   RO Functional Tests

- MOSIS PM consists of an array of DC and AC parametric test structures and functional test devices for monitoring fabrication of wafers by foundries

## Process Monitor Coupon Objectives (1/3)

- Enclosed Layout Transistor (ELT) Device Characterization
- To simulate and design an IC using RHBD geometries such as ELTs, the characteristics of this device must be well defined
- Coupon includes an array of 24 ELT devices similar to the standard 2-edge transistor array used for BSIM parameter extraction
- Characterization will enhance the understanding of:
- The direction of current flow through the device
- How device parameters (, VT, , 1/f noise params, etc.) compare to the standard two-edge device
- An accurate model for the aspect ratio of the device
- How does drain/source placement affect parameters

## Process Monitor Coupon Objectives (2/3)

- Characterize the TID Radiation Induced Charge Build-up in the Process Oxide Layers (Gate and Field)
- Gate Oxide Structures:  Coupon includes standard two-edge PMOS and NMOS devices for measurement of TID induced parametric shifts
- Field Oxide (FOX) Test Structures are included to characterize the isolation oxide
- TID induced leakage paths in the isolation field oxide between neighboring devices can cause severe signal degradation
- Highly process dependent

- N+

- N-well

- VSS

- N+

- VDD

- +

- +

- VG

- +

- +

- +

- +

## Process Monitor Coupon Objectives (3/3)

- Investigate rapid, low-cost methods of tracking the TID radiation tolerance of the process
- The Field Impact Ionization Technique:  Used in the past, but is it useful for current deep-submicron technologies?
- Experiment:
-   High voltage pulses are applied across the device, injecting electrons from the substrate into the oxide via Fowler-Nordheim tunneling.
-   Injected electrons produce electron-hole pairs in the oxide through impact ionization.  These e-h pairs behave similarly to e-h pairs generated by TID radiation.
- Previous reports of correlation between pre-rad 1/f noise and post-rad oxide-trapped charge are promising

## Ionizing Radiation Review

**Area density of holes created by ionizing radiation**

## Field Induced Injection and Impact Ionization (F4I) Technique

- F-N Tunneling

**Fowler-Nordheim **
**Electron Current Density**

**Area density of holes created by **
**impact ionization**

## TID Radiation and F-N Impact Ionization Correlation

**Equivalent Dose delivered by F4I Technique**

- This technique will attempt to show that damaged introduced by electrical stress does indeed “track” the damage produced by Co60 radiation.

## Previous Results on TID and Electrical Stress Correlation

**Co60 Test**

**F4I Technique**

- [1] Boesch and McGarrity, IEEE Trans. on Nuc Sci, Vol. NS-26, No. 6, Dec. 1979.

**Tests reported in [1] on MOS capacitors show relative shift in flatband voltage for irradiated and stressed devices**

## ISI’s IBM 130nm Process Monitor Custom Coupon Chip

- 3.22 mm

-   Process: IBM 8RF-LM CMOS
-   Submitted to MOSIS for fab on 31 Jan 2005
-   Pads included for both wafer probe measurments and for wire bonding to packages
-   Includes a total of 42 devices and test structures

## TID Characterization Test Plan

- Circuit Board Adaptor

- GSFC (HP)
- Parametric Analyzer

-   TID Radiation Testing to 2Mrad at GSFC
-   Wafer probe measurements and electrical stress tests will be performed at MOSIS

## Proposed Migration to 90nm 

- A 90nm Process Monitor Coupon will be developed to characterize the TID hardness of the process
- RHBD Coupon Gen. 1 will be expanded to include test structures for monitoring the charge collection efficiency of the substrate for SEU Characterization
- Test Structures for SEL characterization, gate delay/timing characterization
- ISI proposes to collaborate with existing DTRA Digital SET (DSET) program
- Provide test structures to measure SET signal propogation for different levels of logic complexity

## Proposed Task on 130nm Library Maintenance and Distribution

- ISI proposes to
- Maintain and distribute a 130nm RHBD library through the MOSIS foundry service
- Provide complete library view support and ensure compatibility with commercial EDA tools
- Distribute the library to the RHBD community with appropriate export control (ITAR)

## Schedule Status

- IBM 130nm Process Monitor Chip Submitted to Fab on 31 Jan 2005
- Packaged chips expected in early May
- TID Radiation Tests scheduled at GSFC for mid-May
- TID Test Plan in progress
- Development of test plan for electrical stress test correlation (mid-April)
- Further investigation of rapid, low-cost radiation tolerance tracking techniques

## Agenda

- 11:00 - Introduction  (Damoulakis)
- 11:05 - Overview of Test Needs (Ken LaBel)
- Low Cost Test Needs
- High Speed Test Needs
- 11:15 - Team Responsibilities & Partnerships (Jim Howard)
- Managerial Topics - Team, Responsibilities, Partnerships
- Testing - How & Why
- Functional/Facilities/Usage
- DUT Independence
- Design Flows
- 11:35 - Low Cost/Speed Tester (Hak Kim)
- Design Overview
- 11:45 - High Speed Tester (Scott Stansberry)
- Requirements
- Design Overview
- Status
- 12:00 – Lunch (provided)
- 12:30 - User I/F & VHDL Modules  (Charles Rogers)
- 12:50 - Test Coupons (Valencia Joyner)
- Describe coupon designs & Tests
- Describe SEU design & Tests
-  1:05 - TID & SEU Test Discussion  (Ken LaBel)
- Cobalt-60 facility and TID testing
- Non-Goddard facilities and SEU testing
- 1:10 - Summary  (John Damoulakis)
- 1:15 – General Discussion Q&A

## Radiation Test Facilities Used BY NASA/GSFC

**Kenneth A. LaBel**
**ken.label@nasa.gov**
**Co-Manager, NASA Electronic Parts and Packaging (NEPP) Program**

## Radiation Test Facilities Used BY NASA/GSFC

**Co-60**
**Source at GSFC**
**X-Ray**
**NAVSEA Crane**
**Heavy Ion**
**Texas A&M**
**Brookhaven National Labs**
**Lawrence Berkeley National Labs**
**MSU National Superconducting Cyclotron Lab (NSCL)**
**Proton (SEE)**
**U. of California at Davis**
**Indiana University Cyclotron Facility**
**Mass. General**
**Proton Damage (Materials)**
**Van de Graaff at GSFC**

## NASA/GSFC’s Radiation Effects Facility (REF) – Co60 SourceInside the Room

**Original**
**Ultra-low dose**
**rate source**
**(to < mrad)**

**Shephard**
**Moderate dose**
**rate source**
**(to ~ 50 rads/sec)**

**Robot arm**
**with dosimetry**
**for calibration**

**DUTs are biased and placed in Pb-Al box**
**Dose rate is 1/r****2**** from source or**
**combined from two sources.**
**Testing per Mil 1019.6**

## NASA/GSFC’s Radiation Effects Facility (REF) – Co60 SourceOutside the Room

**Cable run**
**to test**
**equipment**

**Viewing**
**window**

**Source**
**Control**

**Test**
**Equipment**

**Cables come from the chamber**
**for bias power and/or in-situ measurements.**

## External Facility – Heavy Ion SourceInside the Chamber

**External Facility – Heavy Ion Source*****Inside the Chamber***

**Beam line –**
**Heavy ions**
**are collimated**
**to target**

**Simple**
**test fixture**

**Cables run from here to user area (~20-75ft)**

**Test**
**Equipment**

**Texas A&M testing can be done in open air**
**(higher energy facility than some others)**

## External Facility – Heavy Ion SourceInside the Chamber at TAMU

## Heavy Ion Testing at Brookhaven National Laboratories (BNL)

- Vacuum Chamber

- Test Stage

- Beam Diopter

- Test
- Equipment

- Beam Control Computer (can be interlocked with test computer)

## BNL - A little bit closer

- Assembly will lower,
- slide under vacuum
- chamber, raise up,
-  then seal.
- Connector feedthrus
- are available - cable
- length to user is
- ~6 feet

## Proton Testing at UCDavis Crocker Nuclear Laboratory (CNL)

- User end of beam line at CNL
- (test area)

- This wall has been removed,
- enabling larger test fixtures

- User room at CNL: >50feet of cable needed from
- test area. Includes beam control computer. Video
- monitor of test area available.

## Proton Test Hints

- Beware of stray neutrons on your test equipment.
- Here, Borax is shown on top of a power suppiy.
- We have seen failures in test equipment from stray neutrons.

- GSFC’s 4-axis
- remote-controlled
- test stage. Allows
- devices under test
- to be re-positioned
- without entering the
- chamber

**Irradiated parts and boards can**
**get activated and receive dose**

## Test Fixtures

**SiGe Test Fixture at TAMU – **
**Design for speed, power, thermal, and die access**

## Agenda

- 11:00 - Introduction  (Damoulakis)
- 11:05 - Overview of Test Needs (Ken LaBel)
- Low Cost Test Needs
- High Speed Test Needs
- 11:15 - Team Responsibilities & Partnerships (Jim Howard)
- Managerial Topics - Team, Responsibilities, Partnerships
- Testing - How & Why
- Functional/Facilities/Usage
- DUT Independence
- Design Flows
- 11:35 - Low Cost/Speed Tester (Hak Kim)
- Design Overview
- 11:45 - High Speed Tester (Scott Stansberry)
- Requirements
- Design Overview
- Status
- 12:00 – Lunch (provided)
- 12:30 - User I/F & VHDL Modules  (Charles Rogers)
- 12:50 - Test Coupons (Valencia Joyner)
- Describe coupon designs & Tests
- Describe SEU design & Tests
-  1:05 - TID & SEU Test Discussion  (Ken LaBel)
- Cobalt-60 facility and TID testing
- Non-Goddard facilities and SEU testing
- 1:10 - Summary  (John Damoulakis)
- 1:15 – General Discussion Q&A