# Presentation: 677441

## L1 Trigger Status/Issues

**C**entral **F**iber **T**racker & **P**re**S**hower Systems
- Framework
- Calorimeter
- Muon System

- DØ Collaboration Meeting, 6 - Oct -1999				Kin Yip

## Trigger Schematic

**5-10 kHz**
**128 bits**

**1000 Hz**
**128 bits**

**20-50 Hz**

**L2**
**100********s**

**L1**
**4.2 ********s**

**L3**
**100 ms**
**50 nodes**

**Frame**
**work**

**7 MHz, 132 ns crossing times**

**Accommodate :  **
**   ****L=2x10****32****cm****-2**** s****-1**** &**
**   ****Bunch Crossings 132 ns**
**Maintain Run I e, jet, m acceptance**
**Deadtime:  <5%**

- L2FW:Combined
- objects  (e, , j)

- L1FW: towers, tracks

- L1CAL

- L2STT

- Global   L2

- L2CFT

- L2PS

- L2Cal

- L1PS

- L1CFT

- L2
- Muon

- L1
- Muon

- L1FPD

**7 MHz**

**10 kHz**

**1 kHz**

- CAL

- FPS
- CPS

- CFT

- SMT

- Muon

- FPD

**Detector**

**L1 Trigger**

**L2 Trigger**

- L1 Trigger Status/Issues

## ANALOG/DIGITAL BOARDS

- LVDS links

-  Each MCM (Multi Chip Module) has 1 SVX(ADC) and 4 SIFT (discriminator);
-  CFT axial fiber signals are all managed by “8 MCM” boards;
-  CPS/CFT(stereo)/FPS fiber signals are all mixed in the “12 MCM” boards;

- L1 Trigger Status/Issues

## CFT and PS Front-End

**MCM**

- * Charge splitting only for PreShower

- Each CFT/CPS
- Analog board
- has 8/12 MCM’s

**CFT and PS Front-End**

- L1 Trigger Status/Issues

## Status and schedule

**80 identical Analog Front End (AFE) boards mounted on 40 VLPC cassettes.**
**release MCM for ****production**** on Nov. 1st ;**
**backplane in ****production**** NOW ;**
**“****8 MCM” AFE design ****layout ****to be**** ****approved on Nov. 1st ;**
**Scheduled to be ****tested**** on Nov. 1st, but probably would be delayed (Dec. 1st);**
**Bidding for prototype ;**
**“****12 MCM”  AFE : ****design**** issues being resolved (PS group / meeting)**
**8 MCM (in CFT axial) : 8 connected to one HDI (daisy-chain)**
**12 MCM (in PS/CFT)  : separated as 8 and 4 (?) to two HDI’s respectively.**
**Schematic**** in progress — OK for schedule.**

- L1 Trigger Status/Issues

## Status and Schedule

**Mixer Boards ( > 20 Gbits per second per board) :**
**Test Board has been ****made ****;**
**Single link (28 bits) was ****tested**** ;**
**16 links test starts on Oct 11;**
**OK for schedule;**
**A project that could be picked up by someone....**

- L1 Trigger Status/Issues

## Status and Schedule

- Digital Front End (DFE) :
- 40 identical DFE mother boards in two 6U VME crates ;
- each DFE mother board processes two sectors of the detector independently, one on each of two daughter boards ;
- DFE mother boards (Jamieson Inc.) are versatile ;
- Mother board prototype made and tested ;
- Transition Module — layout done, and prototype in fabrication ;
- backplane — layout done, and prototype in fabrication ;
- OK for schedule and budget ;

- L1 Trigger Status/Issues

## Status and Schedule

- DFE — Daughter Boards (DB):
- For CFT/CPS axial “tracking” and FPS clustering, layout near completion;
- testing scheduled for Nov. 23 — Jan. 5 (still on schedule) ;
- FPGA vendor (Xilinx) selected;
- Quadrant/Octant DB : schematic in process
- OK for schedule ;
- pre-Trigger-Manager DB : clone of CFT/CPS DB in design ;
- OK for schedule ;

- L1 Trigger Status/Issues

## Cost Scenarios (Xilinx vs Altera)

- The price for Xilinx ranges from $75k to $110k
- The price for Altera ranges from $100k to $135k
- [both using their slowest speed grade]

- NOTE: This does not include the 5th chip

- Cost vs headroom &vendor & speed grade

- L1 Trigger Status/Issues

**Notes:**
This slide shows three possible purchases of Altera FPGA’s.  
The first uses all 20K parts.  It seems less expensive but this is deceptive.  The 20K200 is a relatively low cost part but is not available until the 2nd quarter of 2000.  Therefore the low price may or may not come about, and all the parts will be less expensive one year from now.  If we substituted the 20k400, which is available now, the total is $350K.

The second could be done now, since all the parts are available.  The 10K200 is almost 1/2 the cost of the 20k200 or 10k250 so this option is really less than the first.  It also would work with the exception that the lowest Pt would have to be slightly above 1.5 GeV.

The third option forces all the logic into the 10k chips in an attempt to keep the cost down.  There is a considerable amount of risk in this, but it does reduce the cost to something comparable to Xilinx.

## CFT/CPS AXIAL FIBERS

- Fibers of each color are sent over separate links from the Mixing Box

- L1 Trigger Status/Issues

## BASIC DATA FLOW DIAGRAM

**FIND CFT**

**TRACKS**

**(4 large**

**FPGAs)**

**BASIC DATA FLOW DIAGRAM**

**CFT/CPS AXIAL TRIGGER DAUGHTERBOARD **

- 4 PT THRESHOLD BINS

**FIND CPS**

**CLUSTERS**

**SELECT THE SIX **

**HIGHEST PT TRACKS **

**FROM ALL PT **

**THRESHOLD BINS**

**(single CPLD)**

**to MUON**

**trigger **

**manager**

**MATCH **

**CLUSTERS TO**

**TRACKS* A**

**ND **

**TRACKS* **

**TO CLUSTERS**

**CHECK FOR ISOLATED**

**TRACKS AND CLUSTERS**

**(FPGA)**

**FORM **

**COUNTS**

**FOR L1**

**(FPGA)**

**STORE TRACKS**

**(bank of 4 FIFOs)**

**STORE CLUSTERS**

**(1 FIFO)**

**FORMAT L2 DATA**

**(FPGA)**

**L1 data is a list of **

**counts of found**

**tracks and clusters.**

**L2 data is **

**a list of found tracks**

**and clusters.  Up to**

**24 tracks and 8 **

**clusters can be **

**reported per sector.**

**L1**

**L2**

**to CFT**

**trigger**

**manager**

- contained in one of the

- large FPGAs

- FIFO CONTROL

- (small CPLD)

**RAW CFT/CPS AXIAL**

**DATA from DFE motherboard**

- fnct_blk.ds4

- 12 july 1999

- L1 Trigger Status/Issues

## Tasks to be Performed

- Tasks performed by ‘TRACKING’ chips
- Max Pt		>> Find tracks above 10 GeV
- High Pt 		>> Find tracks from 5 to 10 Gev
- Medium Pt 	>> Find tracks from 3 to 5 GeV
- Low Pt		>> Find tracks from 1.5 to 3 GeV
- for each of these produce number of tracks and a list of 6 tracks
- CPS		>> Find clusters
- Do this for 4 cases:: north/south//low/high-threshold
- Hits		>> Count number of fibers hit
- Multiple interaction flag

- L1 Trigger Status/Issues

## Tasks to be Performed

- Tasks performed by ‘BACK-END’ chip(s)
- Gather track lists from 4 Pt thresholds
- Gather cluster list
- Match tracks to clusters - set match bits
- Send isolation information over backplane
- Gather isolation information from backplane - set iso bits
- Gather hit count - set multiple interaction veto bit
- Form counts - by Pt threshold, by match, by iso
- At L2 times form L2 data string
- CPS clusters are matched with CFT tracks within  3 strips;

- L1 Trigger Status/Issues

## Tracking Trigger Overview

**Fiber hit pattern recognition** in the **CFT and PS** to
- look for tracks consistent with momentum PT > 1.5 GeV/c
- Match with the **Calorimeter** shower information

- CPS

- CFT

- CAL

- e-

- PS & CAL are matched
- for each quadrant

- L1 Trigger Status/Issues

## Track Equations in HDL

- T1520243035404652 <=  AL(15) AND BL(20) AND CL(24) AND DL(30) AND
-                          	      EL(35) AND FL(40) AND GL(46) AND HL(52)  ;
- T1520253035404652 <=  AL(15) AND BL(20) AND CL(25) AND DL(30) AND
-                          	      EL(35) AND FL(40) AND GL(46) AND HL(52)  ;
- T1520253035414652 <=  AL(15) AND BL(20) AND CL(25) AND DL(30) AND
- 	                        EL(35) AND FL(41) AND GL(46) AND HL(52)  ;
- T1620253035404652 <= AL(16) AND BL(20) AND CL(25) AND DL(30) AND
-                          	     EL(35) AND FL(40) AND GL(46) AND HL(52)  ;
- T1620253035414752 <= AL(16) AND BL(20) AND CL(25) AND DL(30) AND
-                                          EL(35) AND FL(41) AND GL(47) AND HL(52)  ;
- T1620253036414752 <= AL(16) AND BL(20) AND CL(25) AND DL(30) AND
-                                          EL(36) AND FL(41) AND GL(47) AND HL(52)  ;
- p(8)   <=   T**15**202430354046**52**
-            OR T**15**202530354046**52**
-            OR T**15**202530354146**52**
-            OR T**16**202530354046**52**
-            OR T**16**202530354147**52**
-            OR T**16**202530364147**52**** ** ;

- L1 Trigger Status/Issues

## # of Equations vs PT/offset

**# of Equations vs P****T****/offset**

-  NPT ~ 1/PT

- L1 Trigger Status/Issues

## Typical B physics spectrum

**Typical B physics spectrum**

- B Physics requires triggers at Low Pt

- L1 Trigger Status/Issues

## Track Binning

- P**T** binning yields sharper turn-on than offset binning
- offset = [(projection of H layer fiber hit on A layer) - A layer fiber hit] in units of fibers

**} 50%**

**} 20%**

**}15%**

**}15%**

**Eqn #**

- L1 Trigger Status/Issues

## Track Binning

- Pt thresholds    Bit patterns :
- ----------------------------------------------------
- Lowest        11           111     offset 14
-                    11           110     offset 13
-                    11           101     offset 12
-                    11           100     offset 11
-                    11           011     offset 10
-                    11           010     offset 9
-                    11           001     offset 8
-                    11           000     offset 7
- ----------------------------------------------------
- Medium     10           011     offset 6
-                    10           010     offset 5
-                    10           001     offset 4
-                    10           000     offset 3
- ----------------------------------------------------

- ********************************************************
-                                                Ptmin      Ptmax          Ptave
- High           01           011     5.00000     5.71429     5.33333
-                    01           010     5.71429     6.66667     6.15385
-                    01           001     6.66667     8.00000     7.27273
-                    01           000     8.00000    10.00000     8.88889
- ----------------------------------------------------------------------------
- Max            00          011     10.00000    13.33333    11.42857
-                    00           010     13.33333    20.00000    16.00000
-                    00           001     20.00000    40.00000    26.66667
-                    00           000     40.00000     infinite      80.00000

- L1 Trigger Status/Issues

## FPS Algorithms

-  No energy deposition in the front
-  Little energy in shower layers behind
- lead

-  Energy deposition in the front
-  Large energy in shower layers behind
- the lead converter
-  Coincidence in both front-rear layers

- L1 Trigger Status/Issues

## FPS Algorithm

-  In each FPS sector (22.5), there are 103 (u or v) strips in the upstream layer;
- 		    144 (u or v) strips in the downstream layer;
-  FPS sector are further divided into sub-sectors such that they match with CAL towers in ;
-  Form clusters in the downstream (shower) layers;
-  Match with the upstream strip bit pattern;
-  Cluster counts are sent to L1 Trigger Manager ;
-  Quadrant match with CAL is done in the Trigger Framework;
-  After L1 pass, a list of u- and v- clusters with all their characteristics (width, location, type, orientation) are sent to L2 ;
-  The algorithm in HDL has been written, modified, tested and timed.

- L1 Trigger Status/Issues

## Test Result

- Testing Result:
- Algorithm and timing have been tested in the vendor software simulation and implemented in a trigger test board with PLD’s;
-  The measured timing in the real PLD’s agrees very well with the simulation and the result of the trigger logic is what is expected.

- Tracking logic
- completed

**<** 85 ns

- simulation
- result

- L1 Trigger Status/Issues

## Forward Electron Trigger

**L1 Cuts:**
- FPS:  0.3 MIPs (upstream)
-   	       5 MIPs (downstream)
- 	       U view matching,V view matching
- CAL:  EM trigger tower above threshold
- Match FPS with CAL L1 Tower in Quadrant

- Factor of >2!

- L1 Trigger Status/Issues

## L1MU Trigger Status

- Bottom line:  Prototype stage complete
-                       Preproduction stage in progress

- L1 Trigger Status/Issues

## Calorimeter

- Readout to L2 & L3 are being built, due at MSU on Oct 22; FPGA design is underway;
- Quadrant Signal Processing (between CAL & CFT/PS) is underway;
- Trigger Pickoff signals from the BLS : Design work underway;
- L1 CAL Trigger connection to the Run II Trigger Control Computer Finished.

- L1 Trigger Status/Issues

## Trigger Framework

- Hardware is in place (and works)
- Master Clock OK (same hardware but new software, Carmen Rotolo) ;
- Serial Command Link Hubend : Testing prototype & all parts at DØ, sending data ;
- Control Path to Level 3 testing starts this week  Run I;
- remaining issues:
- Readout to Level 3

- L1 Trigger Status/Issues

## Summary

- Stefan Grünendahl:
- 	“All systems are well on their way, but there’s quite a bit of work left....
-      contributions are always welcome.”

- L1 Trigger Status/Issues