# Presentation: 559260

## Current Knowledge on CKM Front-end Electronics

- M. Bowden, K. Bowie, M. Campbell,
- P. Cooper, S. Hansen, B. Haynes,
- Inyakin, M. Kozlovsky,
- K. Nelson, Z. Shi, R. Tschirhart,
- J. Wu, T. Zimmerman

- Feb. 2003

## Since 2nd Edition of Proposal

- The front-end electronics, as the data source, need to match the global picture change – software trigger scheme.
- Large amount of new knowledge, test design, simulation, prototype, etc.
- Possible inherits (cost saving):  HV (LRS 1440) and crates, PS, racks, etc.

## Possible Inherits

- High voltage:  LRS 1440 from KTeV.
- What’s the best use of this? FVS? VVS?
- What about CW development?
- Work request for experts to study on this.
- Crates, PS, racks, etc: from other experiments.
- Inventory, quality?
- Work request for experts to study on this.

## CKM FE General Information

- Total channel count: 33K.
- TDC only channels: 27K.
- Chambers: UMS, KEAT and DMS.
- PMT: KRICH, PRICH, BTSM, ETP and CVP.
- TDC + ADC channels: 6K.
- PMT: from veto detectors VVS, FVS, BIVS, MVS and HVS.
- Pipeline structure, no DAQ dead time.
- Zero-suppression is needed before sending data through DAQ switch.

## ...

- Front-end Boards / Buffers

- Processors

- Switch

- Switch-based DAQ Architecture

## Switch-based DAQ Architecture, Commercial

- Front-end Boards
- / Buffers

## Details of Front-end Sub-systems

- Event Builder
- (Switch)

- CLK
- Sys.

- DATA
- Receiver

- PC Farm

- Digitizer

***Serial Links, Optic fiber or LVDS pairs***

## Jlab VVS Prototype PMT Base

- Discriminator

- HV in

- LVDS Out

- Analog Out

## Jlab VVS Prototype PMT Base

- Dark Current
- Traces

- 1500V

- Stored
- Anode

- Dynode Amp
- Out 10x
- Attenuation

- LVDS Out

## Jlab VVS Prototype PMT Base

- 2400V

## PMT base for VVS prototype were used in Jlab test beam.
The VVS base with integrated discriminator achieves threshold of 1 MeV.
Electronics noise is negligible.

- The VVS base with integrated discriminator achieves threshold of 1 MeV.
- Electronics noise is negligible.

- Jlab VVS Prototype PMT Base

## CMS QIE Test: FE Card

- CMS QIE

- Data Link

## CMS QIE Test: FE Card

- Block Diagram

## QIE readout card is a modified CoLink card. 

- CMS QIE Test: Readout Card

- Data Link

## CMS QIE Test: Software Interface

- QIE Data

- Controls

## CMS QIE Test: Results

- Calibration

- Phase Sensitivity

## CMS QIE with 10 m cable has good noise performance with our nominal VVS gain of 1x105 and FVS gain 5x103.
CMS QIE clock phase sensitivity is under control.
CMS QIE part now runs at 75 MHz, path to 100 MHz and 6-bit mantissa looks clear.

- CMS QIE clock phase sensitivity is under control.
- CMS QIE part now runs at 75 MHz, path to 100 MHz and 6-bit mantissa looks clear.

- CMS QIE Test: Results

## Commercial ADC: The Circuit Board

**AD6644**

**FPGA**

**Integrator(1)**
**AD8055**

**Input Pulse**

**EPC2LC20**

**Integrator (2)**
**OPA660**

**To Analyzer**

## COMADC: 2-phase Integrator

- Integrator Cap’s

## COMADC: Bleeding Integrator

- Input

- Q

- ADC

- Output

## Noise level is under control.  (RMS 1.01 to 1.8 LSB or 0.25MeV at 4GeV full scale).
There is no phase sensitivity issue (for bleeding integrator).
Linear response provides good multi-pulse detection.

- There is no phase sensitivity issue (for bleeding integrator).
- Linear response provides good multi-pulse detection.

- COMADC: Current Findings:

- Q1 + Q2

## Timing (or Clock) Distribution System (TDS)
The Far-End of the Cable is a Common Reference for all Receivers
Reference can be Determined by: T = (Round Trip Time)/2 Or
The Time from Incident Wave to the Reflected  Wave Divided by Two

**The Far-End of the Cable is a Common Reference for all Receivers**
**Reference can be Determined by: T = (Round Trip Time)/2 Or**
**The Time from Incident Wave to the Reflected  Wave Divided by Two**

- I-Wave

- R-Wave

- Round Trip Time = 2T

- I-Wave

- R-Wave

- TfarEnd= (TI-Wave – TR-Wave)/2

- I-Wave

- R-Wave

- TfarEnd= (TI-Wave – TR-Wave)/2

- TfarEnd= (TI-Wave – TR-Wave)/2

- Timing Distribution System (TDS)

## Data patterns are sent through the bi-directional communication links.
Media delay is sensed by recovered clocks or digital patterns of the data flow.
Compensated clock is generated with digital method.

- TDS: Block Diagram

- Data patterns are sent through the bi-directional communication links.
- Media delay is sensed by recovered clocks or digital patterns of the data flow.
- Compensated clock is generated with digital method.

## TDS: Building Block

- Data Link

## Timing distribution system uses digital method to distribute precise timing information over the CKM detector.
Media delay temperature coefficient is compensated with digital process.
TDS needs bi-directional communication links -- emergency service system can use the same physical system, just add firm-wares.

- Media delay temperature coefficient is compensated with digital process.
- TDS needs bi-directional communication links -- emergency service system can use the same physical system, just add firm-wares.

- Timing Distribution System (TDS) & Emergence Service System (ESS)

**	**

- From
- Detector

- 156 MHz
- Ref Clk

- Serdes Control

- 16bit Data

- FPGA

- Serial
- Receiver

- General I/O

- General I/O

- PCI Bus

- ORCA/Xilinx
- FPGA

- Optical or CML

**Simplified TDC Block Diagram**

- Notes:
- 1.)The SERDES receiver must be capable
-      of locking to the reference clock.
- 2.) The 8b10b encoder of the receiver must
-       be capable of being by-passed.

- TDC, DESER Based:

**Notes:**
The Phase-Lock-Looped input clock   is   Lock_To_Reference’d 					CML => Current Mode Logic, 
rather than the much more traditional    Lock_To_Data    use.  						the modern improvement on ECL

Traditional applications use input_clock phase-lock-loop 
to accommodate small and/or cyclic variations in the input rate,   
becoming   insensitive   to the input rate.

A feature found in some high-end PLD’s lets users accommodate non-standard uses.

Receive 16 bits serially per clock (I.e.multiply input clock by 16).
Count the 1’s, multiply by 1/16th the clock rate

For those of you who remember using Slideruler’s, this is analogous to a similar vernier ...

SerDes (Serializer / Deserializer) 

## TDC w/ 400ps Resolution 	
Input Pulse Width = 7FFF FC00 0000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns
Reference Counter Time = T Ref  = 105.6ns
T Ref Offset  = # of 0 bits from T Ref  x 400ps = 1 x 400ps = 400ps
Input Prop. Delay = 28.800075ns + T Ref Offset = 28.800075ns +400ps = 

**Input Pulse Width** = **7FFF FC00 0000****-> 21bits x 6.4ns/16 = 21 x 400ps = ****8.4****ns**
**Reference Counter Time = T**** Ref****  = 105.6ns**
**T**** Ref**** Offset  = # of 0 bits from T**** Ref****  x 400ps = ****1**** x 400ps = **400ps
**Input Prop. Delay = ****28.800075ns**** + T**** Ref**** Offset = 28.800075ns +400ps = **

- 7FFF

**29.200075ns**

- 105.6ns

- TDC, DESER Based: Simulation

## TDC, Chain Delay Based:

- IN

- CLK

- Same FPGA for ADC data handling

## TDC, Chain Delay Based: Test

- Power supply voltage changed to create variation of the delay.
- V = 2.5 to 1.8V: the change is very big.
- 30% cell delay variation is seen.
- Digital Compensation Works.

- TDC

- Input

- After digital compensation

## UMS Pre-amplifier

- Both UPENN-ASDQ and commercial-part-based ASD are tested.
- Left: test setup.
- Bottom: COM-ASD circuit schematics.

## UMS Pre-amplifier

- Measured:
- Equivalent noise charge (ENC) at input.
- Tr
- COM-ASD works as good as UPENN-ASDQ.

## DMS Pre-amplifier: Schematics

## DMS Pre-amplifier: Simulation

## RICH PMT Base: Structure

- 34 Pin Ribbon
- Connector

- RJ 45
- Connectors

- 16 Channels of Amp/Disc

- CW HV

- 8 tube adapter card

- Proposed16 Tube RICH Counter Card

- LV
- Power

## RICH PMT Base: Adapter Card

## Data sparsification is necessary in FE hardware.
A scheme of possible data structure is provided for software trigger simulation based current knowledge on hardware.

- A scheme of possible data structure is provided for software trigger simulation based current knowledge on hardware.

- Data Structure Study

## Data Structure

- Millenary Header

- Centenary 0

- Centenary 255

- Centenary ID word: Inserted while forming Millenary

## Data Structure: TS Establish Assumption

- Event Builder
- (Switch)

- CLK
- Sys.

- DATA
- Receiver

- PC Farm

- No-op

- Reset/Sync.

- CLK

- TS10

- TS32

- Digitizer

***Serial Links, Optic fiber or LVDS pairs***

## Data Structure: Data Flow Assumption

- Event Builder
- (Switch)

- CLK
- Sys.

- DATA
- Receiver

- PC Farm

- Digitizer

- When there is nothing else to transmit, send No-op and TS to maintain TS counters.

- Send hit data blocks when they are ready.

- Emergency service request

- DAQ data flow

- Emergency requests are serviced by CLK sys. and commands are sent back.

- More data and idle

## The End

- Thanks