# Presentation: 363173

## Layer 0 in D0 Silicon Tracker for run2b

- Kazu Hanagaki / Fermilab
- for D0 run2b Silicon Tracker group

-   Motivation & concept
-   Analog flex cable
-   Prototypes
-   Noise/Shielding studies
-   Summary and prospects

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Motivation

- Higgs search, new phenomena search, top physics,                 b physics...  all needs b tagging.
- B tagging by means of the longer life time of B meson/baryon                         better impact parameter resolution.                                    measurement at position close to the decay point.                       ~ meas(1+Rin/Rout)
- Design goal: S/N>10 after 15fb-1 for the Layer 0 (L0).
- Simulation for WH(bb) events:                                             b jet tagging efficiency  69% for run2b (50% for run2a)

- (0.11 for run2b, 0.27 for run2a)

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Concept

- SVX4 chip cannot sit on the sensors because of the cooling and space issues.                                                                 Signal must be read out from the sensor to the chip. Also bias voltage and its return must be provided.             Low mass analog flex cable.                                            Noise due to capacitive load and pick-up must be addressed.

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Requirement to Analog Cable

- S/N=10

- CSi

- Ccable

- S/N=10 after 15fb-1  Ccable < 23pF for 43.5cm long cable

- Total noise estimates VS total capacitance (Csi + Ccable)

-  Ccable < 0.53pF/cm

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Analog Cable Design

- 50 m pitch

- 100 m pitch

- 16 m wide trace with ~100m pitch satisfies the requirement of <0.53pF/cm

- FE calculation by ANSYS

-  91m trace pitch.
-  16m trace width.
-  No fan-in/out region.
-  Two cables laminated at the  edges with 45m offset.
-  50 m thick polyimide (Kapton type) substrate.

-  Use technically simpler solution which maintains low capacitance.

-  Alternative for 50m pitch readout

- 50m + 100m + 50m pitch

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Analog Cable Design (cont’d)

- 200 m is enough to avoid significant contribution from other cables.
- Low r material for spacer.  polypropylene mesh.

- Contribution from:
- Two neighbors = 0.208 pF/cm
- Two top neighbors = 0.014 pF/cm
- Two bottom neighbors = 0.017 pF/cm

- C = 0.328 pF/cm

- 100m pitch
- 8 x 16m traces

- 200m

- 50m

| r (spacer) | C (pF/cm) |
| --- | --- |
| 1 | 0.328 |
| 2 | 0.449 |
| 3 | 0.566 |

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Prototype Cable by Dyconex

- visual inspection on cables:
- look for not gold-plated (copper) pads as evidence for an open trace
- 129 tracesone open is allowed.
- check trace width on cables: 9-12 m depending on cable.

- Capacitance (one to neighbors) ~ 0.35pF/cm.

| # open traces | 0 | 1 | 2 | >2 |
| --- | --- | --- | --- | --- |
| #cables | 22 | 13 | 4 | 0 |

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## L0 Prototype for noise studies

- Dyconex analog cable                 + ELMA prototype sensor           + SVX2 chip (for run2a)
- Noise increase ~ 1000 e             consistent with SVX2 noise performance.

- HV

- GND

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Shielding

- edge

- RF pick-up by the analog cable.
- No external but shielding (= aluminum foil) only around the analog cable.

- Noise level w/ ext. shielding

- different shielding length

- center

- total noise

- random noise

- center region

- edge region

- sensor

- SVX2

- analog cable

- shielding length

- Shielding metal connected to GND

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Shielding (cont’d)

- Must be careful about capacitive coupling to nearby floating metal.
- Clear even-odd effect indicates capacitive coupling to the analog cable.  Distance between the traces to the metal; top-metal ~ 100m, bottom-metal ~ 50m.

- metal piece under the cable w/o ground connection

- metal piece

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## L0 Prototype with SVX4

- First prototype using new SVX4 chip.
- Large capacitive load
- Long analog cable  signal transmission
- L1 prototype hybrid with SVX4.

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Prototype w/ SVX4 (cont’d)

- Successfully reads out!                                              First time for SVX4 through long analog cable.
- (Systematic noise studies not yet done...)

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Grounding

- Sensor ground will be tied together to the CF structure. (Only L0. The others at hybrid.)

- Carbon Fiber (CF) support structure is regarded as a conductor for high frequency.             talk by B. Quinn

- Vertex 2002     Kazu Hanagaki

- November 6  2002

## Summary & Prospects

- Established baseline design for the analog cable.
- Test results of prototype analog cable are encouraging.
- L0 prototype addresses the feasibility of our baseline design.
- Noise studies are in progress.
- Grounding scheme will be tested by having prototype module.

- Vertex 2002     Kazu Hanagaki

- November 6  2002