# Presentation: 932109

## Proposal for a New Binary Architecture for STAR Microvertex Upgrade

**Wojciech Dulinski, IPHC, Strasbourg, France**

**Outline**
** ****Short history of beginnings: NSS-2004, Roma (W.Dulinski)**
** ****Review of existing results: work of M. Szelezniak (10****th**** ESSD, Wildbad Kreuth, 2005) and A.Dorokhov (FEE-2006, Perugia)**
** **_**Binary readout scheme, based on FAPS pixel**_
**Conclusions**

## Analog CDS on pixel using analog memories for storing two successive frames : possible way to limit the integration time, effective use of a trigger

**Analog CDS on pixel using analog memories for storing two successive frames : possible way to limit the integration time, effective use of a trigger**

**- Slow integration clock (1MHz ******** 640 μs integration time): low dissipation, comfortable stabilisation time of the on-pixel amplifier after Power_On**
**- Readout of all pixels after trigger only: no need for perfect internal readout chain compensation**
**- External compensation, global correction (common mode) possible: limited risk for experimental “unknown” factors**
**- Lower signal amplitude dispersion: less power, smaller digitisation precision required (~8bits)**

- READOUT

## RMSNoise < 8 ADCENC = 16-20 e-  

**Pixel_1: 400 fF**

**Storage capacitor discharge time of a (600 mV) pulse is more than comfortable. What after irradiation?**

- RMSNoise < 8 ADCENC = 16-20 e-

- Very preliminary!!!

**Time scale: 10s/sq.**

**First test results from Mimosa9 test structures**

**Fe****55**** 5.9 keV peak**

## Conclusions 2: STAR application- Increase of a dark current after irradiation is THE critical factor, in order to run detector at room temperature (not well controlled) AND using several milliseconds integration time- Each process and each layout should be carefully studied for this effect AND compared to STAR radiation environment - Going to shorter integration time (order of magnitude) and systematic research on the more radiation-tollerant layout techniques is strongly recommended, in order to have necessary safety factor for the experiment “unforeseen”- CDS on pixel using analog memory for two frames storing scheme seems promising, but still requires deeper understanding (new small prototypes)

**Conclusions 2: STAR application****- Increase of a dark current after irradiation is THE critical factor, in order to run detector at room temperature (not well controlled) AND using several milliseconds integration time****- Each process and each layout should be carefully studied for this effect AND compared to STAR radiation environment ****- Going to shorter integration time (order of magnitude) and systematic research on the more radiation-tollerant layout techniques is strongly recommended, in order to have necessary safety factor for the experiment “unforeseen”****- CDS on pixel using analog memory for two frames storing scheme seems promising, but still requires deeper understanding (new small prototypes)**

## DC coupled and AC coupled on-pixel amplifiers

**DC coupled and AC coupled on-pixel amplifiers**

- AC coupled amp:
- Separation from power supply of the sensing node
- Increase of the voltage  increase of the depleted region  no change on the operating point
- Separation from influence of the leakage current
- Increase of the leakage current after irradiation  change of the bias on the sensing node  no change on the OP

- DC coupled

- AC coupled

- Compact implementation

## DC versus AC diode coupling

**Charge collection efficiency and ENC in function of bias of charge collecting diode**

**DC seems to win in simplicity and performance...**

## Amplifiers for MAPS

**Amplification is needed to decrease noise contribution from switching networks, like clamping or sampling.**

- in

- out

- bias

- bias

- in

- signal
- current

- out

- reset

- cascode

- in

- vb

** ****PMOS transistors not allowed inside pixel -> signal decrease due to parasitic NWELL**
** ****but using PMOS transistor as a load would be the preferred choice to increase in-pixel amplifier gain...**

**load**

- gate

## Amplifiers for MAPS

- in

- out

- bias

- signal
- current

** ****gds****1**** and gds****2 ****<<**** ****gm****1****,**** **** ****gm****2 ****, gmb****2 **
** ****so one need to increase gm****1****  ****and decrease gm****2 ****and gmb****2**
** ****with decreasing gm****2**** we decrease DC current, and hence gm****1**** so there is a limiting contradiction for the gain/bandwidth of this schematic...   **

**Due to gm****2**** there is unwanted dependency of I****d**** on U****out ****, so**
**can we reduce**** **** dependency of I****d**** on U****out**** without changing gm****2**** ?**

- M1

- M2

**small signal Gain = V****out****/V****in**** = gm****1 **** ****/(**** ****gm****2 ****+gmb****2 ****+gds****1 ****+gds****2****)**

**Id**

**?**

**As an example from simulation to be presented later:**
**gm****1****=47 ********S  gm****2****=4 ********S  gmb****2****=0.9 ********S  gds****1****=8 nS  gds****2****=0.5 ********S**

## Improved load for the common source transistor

- in

- out

- bias

- signal
- current

**-> decouple the gate of the load transistor from the power supply with one additional NMOS transistor, used as a diode**

**due to the floating gate and parasitic gate-to-source capacitive coupling the AC voltage at the gate will follow to the output AC voltage -> **
** ****AC current and hence the load for the common source transistor decreases **
** ****load for DC is almost unchanged as DC voltage drop on additional NMOS transistor is small **

- gate

**The AC gain should increase, while the DC operational point should not change!**

**Gain = V****out****/V****in**** = gm****1 **** ****/(**** ****gm****2 ****+gmb****2 ****+gds****1 ****+gds****2****)**

- M1

- M2

- M3

## Test structures with new amplifier implemented in Mimosa15 chip 

**Test structures with new amplifier implemented in Mimosa15 chip **

**improved load with power on switch**

**low frequency-pass feedback**

**correlated double sampling circuit **

**common source transistor with power on switch**

**NWELL size is** **4.25 ********m x 3.4 ********m, pixel pitch size 30 ********m x 30 ********m, **
**pixel matrix: 4 columns x 15 rows**

**NWELL diode**

## Summary (VI-th Front End Electronics Workshop, Perugia, 2006)

** ****new resistive AC load, which uses only NMOS transistors, is proposed**
** ****NMOS based amplifier using new type of load and feedback is designed and simulated **
** ****the gain increases by factor of 2 in comparison to the gain of existing amplifier schematics, which use only NMOS transistors**
** ****in comparison to old schematic, the same gain can be achieved with smaller power consumption**
** ****the designed amplifier implemented in MAPS using AMS0.35 OPTO process and tested with ****Fe****55**** source**
** ****the tested MAPS**** has the following measured properties:  **
** ****low noise, ~7.5 e (after CDS), and hence higher signal-to-noise ratio**
** ****conversion gain is about 74 ********V/e**
** ****gain variation due to process variation is about 2 %**
** ****charge collection in seed pixel is 18 %**
** ****charge collection in the cluster 3x3 is 58 %**** **
** ****the amplifier can be also used in schematics, where one need to save the space, cause it does not contain PMOS transistors (and hence PWELLs)**

## Mimosa8 (TSMC-0.25μ, 8 μm epi) – a binary readout demonstrator

**CDS in pixel, based on “clamping” circuit solution **
**On-chip FPN suppression**
**Offset compensated comparator at the end of each column **
**Pixel pitch 25 x 25 μm2**

- Prototype in collaboration with Dapnia/Saclay

## Mimosa8 beam tests results

** ****Output noise: 0.9 mV (ENC = 15 electrons)**
** ****Pixel-to-pixel FPN: 0.45 mV (7.5 electrons)**
** ****Spatial resolution: ********r**** = ~7 μm**

** ****First demonstration of feasibility of FPN correction using on-chip real time circuitry**
** ****The design goal confirmed by the beam tests results: efficiency > 99 % **
**Second version (Mimosa16) in AMS-035 OPTO with 14 and 20 μm epi **_**under test**_

**Comparator voltage scan (all pixels)**

## Pixel optimization: diode size ↑ , charge collection ↑but also parasitic capacity and ENC ↑ ! 

**ENC = 12 e, G = 65 μV/e**
**Charge coll. eff. <25%**

**CSFb, 4.5x4.5 μm diode**
**ENC = 15 e, G =** **45 μV/e Charge coll. eff. >50%**

**CAFb, 4.5x4.5 μm diode**
**ENC = 12 e, G =** **65 μV/e Charge coll. eff. >50%**

*** Collection efficiency: charge collected in 3x3 cluster, measured on 20 μm thick epi wafer and 25 μm pixel pitch**

**Improved load**

**Self-biasing**

**Pixel optimization: diode size ****↑ , charge collection ↑but also parasitic capacity and ENC ↑ ! **
**Examples from measurements using recent AMS-035 OPTO test structures****.**

## After Mimosa16 and Mimosa22: Rapid Binary Sensor (MimoRaBinS?) for STARbased on two-memory cells FAPS combined with Double-Sampling inter-pixel offset compensation

_**Approach**_
**Profit from particular STAR timing for TPC (trigger + 1 ms readout). Split between acquisition and readout. During acquisition, the only active element is in-pixel amplifier (one row), without addressing long readout lines. Readout is ~four times slower, saving the power in  the ~equal proportion.**
_**Basic goal: decrease integration time (by an order of magnitude), still reducing power dissipation (factor of two-three).**_
**Try to use existing building blocks, if possible!**

## 1000x1000 pixels

**1000x1000 pixels**

**New block:****Diff. amplifier**

**Discriminators**

**Sparsifying logic**

**Acquisition**

**Readout**

**Power budget assumed for****Integration time = ****50 μs/n;**** n: number of parallel-processed rows **

**50 mW * n**

**??? (50 mW)**

**<100 mW**

**<100 mW**

**20 mW**

**Rapid Binary Sensor for STAR: power budget estimation**

**Conclusion: always < 100 mW/cm2; with a good safety factor**
**It is maybe a good idea to have the same power dissipation **
**during acquisition and readout phases: n = 5 ******** T****int**** = 10 μs.**
**Same power ******** same current ******** less problems with power lines**
**stabilization (?)**

## Conclusions

** ****A new scheme for a binary MAPS is proposed**
** ****Substantial decrease of integration time is possible, with a lower power budget!**
** ****Less sensitivity to dark current, lower occupancy, lower data throughput**
** ****Do we buy it and continue???**
** ****Answer expected ASAP**