# Presentation: 863812

## HYBRID PIXEL DEVICE

- Simon Kwan
*Fermi National Accelerator Laboratory, Batavia, IL 60510*
- _[swalk@fnal.gov](mailto:swalk@fnal.gov)_

## Outline

- Introduction
- Application in HEP experiments
- Past, present, and future
- Technical challenges
- Readout chip
- Sensor
- Interconnect (hybridization, High Density Flex-circuit)
- Mechanical and Cooling
- Test Beam results
- Other applications
- Conclusion

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## Hybrid Silicon Pixel Device

**Hybrid**** ****Silicon**** ****Pixel**** ****Device**

- Independent development and optimizations of readout chip and sensor
- used in FT expts at CERN and DELPHI
- will be used in ALICE, ATLAS and CMS at the LHC, BTeV
- Rad-hard or rad-tolerant processes: DMILL, deep submicron CMOS
- n+ silicon pixels on n-type substrates: (typically 50 x 400 m2, but can also be a square pixel like 150x150 m2
- Bump-bonding of flipped chip: 2 technologies  being considered: Indium (In)  and solder (Pb/Sn)

- Pixel readout chip

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## Motivations for using Pixel detectors

- Pattern Recognition
- 2-D device
- Fine granularity
- Considerations
- High multiplicity/particle track density in events of interest
-  Need many elements for low occupancy
- Driven by desire to minimize extrapolations to beam, detector placed close beams, and therefore, highest particle density

- WA97 (153 tracks!)

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## Resolving Ambiguities

- For 1 track, no ambiguity.
- For 2 tracks through a set of strip detectors, 4 combinations
- For 3 tracks through a set of strip detectors, 9 combinations
- For n tracks, ... n2
-           Imagine n = hundreds!
-        Imagine computing times,
-        difficulties for fast triggers

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## Motivations for Pixel Detectors in HEP

- Radiation damage
- Excellent S/N

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## Comparison of Hybrid Pixel Detectors used in experiments

|   Experiment
     Property |   WA97/NA57
     Pb-Pb
   Heavy ion FT |            DELPHI
         e+e-   Collider | NA50/NA60       
 Heavy Ion FT |
| --- | --- | --- | --- |
|     Pixel Size
   |   75 x 500 and   50x500  mm2 |     330x330 mm2  |  50x425 mm2
  |
|    Size of Unit   Subassembly | 5 x 5 cm2 
 |    2 x7 cm 2
       |    |
|     Number of     
      Pixels (K) |   1093  |   1226 |   790 |
|    Total Active 
         Area |    372 cm2 |      1335 cm2 |     200 cm2
        |
|     Material Xo  
     per plane |     ~ 1 % |     1.4 %
    1.62 % |     |
|       Number of chips |        792 |     2432 |   ~ 200 |

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## DELPHI VFT performance

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## NA50 and NA60 (Heavy Ion FT)

- NA50 dimuon event display
- Performance
- NA60 vertex detector:

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## Future Pixel Detector Systems Specifications

|   Experiment

     Property |     ALICE
     Pb-Pb
   Collider |      ATLAS
         p-p
     Collider |       BTeV
        p-p
     Collider |      CMS
       p-p
    Collider |
| --- | --- | --- | --- | --- |
|     Pixel Size
   |   50 x 425
  microns sq.  |     50 x 400
    microns sq.  |    50 x 400
    microns sq.  |  150 x 150
  microns sq.  |
|    Size of Unit   
  Subassembly | 5.4 x 0.58 
5.5 x 0.83 |    5 x 30 cm2
       |      5 x 10
     5 x  5 cm2 |   6.5 x 1.6
     cm2 |
|     Min.dist. to    
        beam |     40 mm |   43 mm (B)
   101 mm |      6 mm |    41 mm
   70 mm |
|     Number of     
          Pixels |   16 x 106 |   140 x 106 |     31 x 106 |   56 x 106 |
|    Total Active 
         Area |    0.26 m2 |      2.2 m2 |       0.62 m2 |     1.1 m2
        |
|     Material Xo  
     per plane |     1.4 % |     1.80 %
    1.62 % |        1.1% |    1.65 %
    2.3 % |
|       Special 
     Features |        50  
  tracks/cm2 |     4 bit TOT
        ADC |    Level 1 Trig
    3 bit ADC |   Low lum.    
 inner layer |

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## Future Pixel Detector Systems

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## Practicalities for Pixel Readout Chips

- Presence of small analog signal and digital activities on same chip
- Desired resolution in x and y directions per plane vs area for the circuitry -> high circuit density
- Low noise under constraint of low power and remain so during lifetime of the system after intense irradiation
- Leakage current compensation
- Low threshold dispersion
- Binary vs analog readout
- Capabilities per pixel vs area requirement
- Time stamp
- Triggered readout vs data-driven
- Radiation hardness
- Available technologies for implementation and possible technology changes
- Total dosage (cumulative) effects and single event effects
- Yield in production, wafer/chip/assembly testing
- Power consumption

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## LHC environment

**LHC environment**

**SIMULATION**
** ****Radiation environment dominated by pp secondaries**
** ****L=5 ********10****5**** pb****-1**** ******** ********6********10****14**** cm****-2**** in six years of operation at r=7 cm**

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## BTeV Radiation Background(L=2·1032  cm-2 s-1), charged hadrons Pixels, Z = (55 – 60) cm 

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## Pixel Readout Electronics design challenges

- Function is to handle charge signal from sensor
- Amplification
- Discrimination (hit decision)
- Store hits (when, which)
- Select hits of interesting events for further readout
- Find the hit pixels and read them out
- Architecture determined by
- Hit rate
- Trigger latency
- Readout rate

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## The LHC Challenge

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## BTeV Pixel Detector Readout Bandwidth

**Average Bit Data Rate, in Mbit/s**

- Data rate depends on:
- Luminosity
- Threshold
- Magnetic field
- location

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## Radiation Damage

- General alteration of the operational and detection properties of a device due to high doses of irradiation
- Radiation induced effects:
- Electron-hole pair creation – particle detection
- Atomic displacement – dislocation of atoms from normal sites in the lattice -> long term effects on bulk properties
- Chemical bond rupture – surface effects, carrier’s surface mobility decreases, oxide trapped etc -> surface damage

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## Radiation Damage

- Action plan for Readout chip
- Rad-hard to much high level cf strips
- CERN RD20 (DMILL)
- CERN RD49 (RADTOL)
- Military technology such as Honeywell, Harris, DMILL
- Deep submicron CMOS process
- SEE leading to special designs

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## Radiation effects in CMOS

- Total dose effects (cumulative)
- Threshold shifts
- Increase in noise
- Increase in leakage current between and within transistors
- Single event effects (SEE)
- Single event latch up – large increase in current resulting from turn on of parasitic structure
- Single event upset – change in logic state of a cell in RAM or shift register
- Others: SEGR, SEB etc

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## Motivation of the radiation tolerant approach in deep submicron CMOS process

- Radiation tolerance of thin gate oxide
- Rad-induced holes removed by tunneling
- Few rad-induced interface traps
- Features of the technology
- Large scale integration – density
- Performance – good speed and  noise
- Low power
- Large volume mainstream  process,
- High yield, low cost
- Superb results on chips designed for HEP
- Excellent  for pixel RO

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## ATLAS Pixel Readout Chip

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## FPIX History

- 1997: FPIX0, a 12X64 HP 0.8m CMOS process
- Two stage front-end, analog output digitized off chip
- A data driven non-triggered RO
- Successfully used in beam tests (more later)
- 1998: FPIX1, a 18X160 HP 0.5m CMOS process
- Two stage front-end, with one 2b FADC/cell.
- Fast triggered/non triggered R/O
- successfully used in beam tests
- 1999: preFPIX2_T, 2X160 TSMC 0.25m
- Radiation tolerant techniques forced us to design a new front-end with a new leakage compensation strategy.
- 2000:
- preFPIX2_I,  18X32 0.25 CERN process; same FE cell as in preFPIX2_T but with complete fast non-triggered RO
- preFPIX2_TB 18x32 TSMC 0.25m ; programmable bias
- and threshold by DACs

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## Floor Plan

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## Schematic of a Pixel Readout chip

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## Performance 

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## Deep Submicron CMOS process: Irradiation ResultsGeneral effects after 33 Mrad

- Chip fully functional
- No degradation in speed (as inferred from the kill/inject shift register operation).
- No change in settings (bias voltage, feedback current etc)
- Less than 10% change in “analog” power. Power was less after irradiation.

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## Linearity before and after 33 Mrad

- => 7 % max gain error. Believed to be due to output buffer only.

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## Noise and threshold distributions

- => Practically no change in noise and threshold dispersion.
- => 200 e- change in the threshold voltage.

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## preFPIX2I –Irradiation tests

- CERN/FNAL submission
- 0.25 m CMOS process
- 18x32 pixels, complete RO
- 4 chips irradiated with 200MeV protons to 4.4x1014  p/cm2
- Goals of tests: investigate SEGR and confirm rad-hardness
- Every pixel works after irradiation; noise about the same; less threshold dispersion
- No evidence of SEGR -> validates deep submicron process as rad-hard

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## Single Event Upset (SEU)

- a non destructive phenomenon induced by radiation in electronics chips.
- caused by heavily ionizing fragments and recoils depositing enough charge in a sensitive node of an electronic device.
- could change the logic state of a memory cell (Flip-Flop) and corrupts downloaded data  stored on-chip registers.
- Depending  on the SEU rate of a chip appropriate reset mechanisms could be needed in the design.
- We observed  63 bit errors in 22135 seconds during the exposure, this gives an average bit error rate of 2.8E-3s-1.
- We observed no bit errors in 43200 seconds with no exposure, this gives an upper limit of the accidental bit error rate of 2.3E-5s-1.

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## Issues for Pixel Sensors       

- Desired resolution in x and y directions per plane
- Radiation hardness
- Yield in production, wafer/chip/assembly testing
- Magnetic field effects
- Sensor material thickness
- Choice of sensor material
- Silicon
- Material choices (resistivity, crystal orientation, defect engineering)
- Double-sided technology
- “moderated” p-spray (patent and license)

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## Radiation effects in Silicon detectors

- Effects of displacements results in changes of the internal electric field, due to modified doping concentration
- For very high irradiations, conduction type will be inverted (type-inversion)
- Increase in leakage current
- Change in capacitance and resistivity
- Charge collection losses

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## Silicon Sensor Choices

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## Silicon Sensor

- n+ on n bulk which implies RD on isolation between implants (RD20, ATLAS)
- High voltage operation leading to complicated guard ring design (RD20, SINTEF, Padova)
- CERN RD48 (ROSE) collaboration plays a critical role
- Low resistivity wafer
- Oxygenated wafer (tested by H. Kraner et al ~1993)

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## Guard ring design 

**Guard ring design**** **

** ****Requirements**
-  **Breakdown voltage >500V**
** ****Read-out side grounded**
** ****Voltage drop on guards on the backside**
** ****Implementation already tested**
-  BNL design
- MPI/ATLAS pixel design
-  CMS Si microstrips

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## Examples of Guard Ring Design

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## SINTEF Sensor WaferBreakdown Voltage 

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## P-stop detector

- Common p-stop

- Individual p-stop

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## CMS sensor :  p-stop design

** ****Double open ring  Pstop:**
-  Keeps unbonded channels grounded
-  Reduces inter-pixel capacitance
-  Minimizes Breakdown
-  Baseline:
-  78 m n-implants surrounded by 2 p-stop rings with openings; resistive path ~ O(100 K)
** **

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## ATLAS: moderated p-spray

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## US-CMS Pixel (irradiation results)

- Fluence -6x1014

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## US CMS Pixel group (Irradiation results)

- Fluence -1x1014

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## Oxygenated Wafer

**Proton irradiation**

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## ATLAS Pixel Operation Scenario

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## Issues for Pixel Detector Assembly

- Completeness and uniformity of coverage
- Bump bonding (availability, yield, cost)
- Interconnection (yield, availability of vendors to meet the the specs for the High Density Interconnect: layers, line width, spacing, via )
- In-house vs industry
- Material budget (bumping/mating of thinned wafers/parts, thickness of metal layer on flex-cable)
- Radiation hardness

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## Bump Bonding Technologies

_**Indium Bumps**_
- Fabrication process: Evaporation
- Single die bumping possible
- Requires sputter deposited 2-metal layer barrier diffusion/adhesion UBM
- Minimum achievable bump size:   8-10 m and pitch: 18 m
- Soft bump with a MP of 156oC
- Bumps oxidized quickly: non-conducting and the oxide layer has to be penetrated
- Both sides have to be bumped
- Good Properties (electrical and mechanical): 1-2 /bump
- Mating done by pressure only (1-2gm/bump); needs precision flip-chip bonder

_**Solder Bumps**_
- Fabrication process: Electroplating
- Requires fabrication of solder bumps on one side only with wettable surface of the other side
- Excellent electrical and mechanical characteristics (a few /bump, shear strength > 30 grams)
- Minimum achievable bump size:       18 m  and pitch: 50 m
- Versatile in selection of solder alloy composition and MP
- Self aligning and self-planarizing bumps (upon reflow)
- Potential for low-cost in high volume

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## Pictures from AIT

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## Detectors from MCNC using solder bumps

- 25 m around the base and 28 m high

- _Detectors from MCNC using solder bumps_

*Sensor*

*Pixel readout chip*

- UBM

- Bumps

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## Technical challenges:

-  _Pixel readout chip:_
-  Wafer non standard thickness
-  8” wafer capability
-  Wire bond pads
-  Uneven distribution of bump pads
-  _Sensor:_
-  - Thin 4” wafers with structures on both sides
- _Thinning: _
-  when,  how, uniformity, planarity, stress, bump protection
-  _Module:_
- Chips abutted close to one another

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## Thinning of bumped wafers

- Wax process

- UV release tape

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## Delphi Module

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## Pixel Multichip Module – Baseline Design

- _Pixel Multichip Module – Baseline Design_

- 1) Readout Chips

- 2) Deposit Bumps

- 3) Flip Chip Bump Bond RD. Chip & Sensor

- 4) Glue Flex Circuit on the Sensor

- 5) Wire bond Flex Circuit to RD. Chip

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## ATLAS module

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## ATLAS module: MCMD technology

- _M_ulti-_C_hip _M_odule _D_eposited :Use thin-film technology to perform signal interconnections and power distribution on the edge of the sensor
- Conductive layer: up to 5 Cu layers, min. width and spacing 10 and 20 mm
- Dielectric layers: spin-on BCB with thickness per layer: 4-10 mm
- Advantages: bump-bonding is the only interconnection technique, low cross-talk
- Issues: bump bond failure rate, reliability of feedthroughs
- Investigate different feedthru layouts especially routing
- Possibility of integrating passive components

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## Mechanics and Cooling

- High power density
- Desire to operate at low temperature
- Hard to access (innermost part of detector)
- Compact layout (as close to IP as possible)
- Technical challenges
- Mechanical structure: low mass, low Z, mechanically stiff, stable (low CTE), rad-hard, low outgassing (BTeV)
- Cooling: efficient, leak-tight, coolant has to be low density, low Z, low viscosity, stable, non-corrosive, inflammable, and non toxic.

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## Thermal Management

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## BTeV Pixel Support Structure

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## Factors affecting the spatial resolution

- Energy deposition  by charged track along its path length (Spread of the electron cloud due to diffusion
- Drift in **E **corresponding to doping and bias voltage applied
**E** **x B **(our sensors will be in dipole field of 1.6 T)
- Realistic parameters of the front end electronics (noise, threshold, digitization accuracy).

- Electrons drifting in the electric field and spreading due to diffusion

- E

- E

- MIP crossing the sensor

- The interplay of these factors has been studied with a Monte Carlo simulation including:

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## BTeV Test Beam Results: Resolution vs angle

-  # No track projection error subtracted from the measurement
-  # Binary resolution degraded from 8-bit ADC

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## BTeV Test Beam Results: Occupancy Test

- Interaction vertex in diamond target

- Interaction vertex in pixel plane

- 2.2 mm thick diamond target used
- Handle occupancy much larger than expected at BTeV      ( ~ factor of 10 )

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## ATLAS Test Beam Results

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## ATLAS Test Beam Results

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## LHCb : Photodetector

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## Medipix

- Develop single photon counting pixel system for imaging applications
- Medipix1: preamplifier, comparator with 3-bit threshold adjustment and a 15-bit counter per pixel. Self-triggerable, 64x64 pixels of 170 m2
- Medixp2: deep sub-micron technology

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## X Ray detection

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## Concluding Remarks

- Hybrid pixel devices are powerful for tracking and will be used in all the future hadron( and heavy ion) collider experiments
- Increasingly being used in many other applications
- Technically very challenging; a lot of work lies ahead of us in the construction and operation of a large pixel system
- Required effort is often under-estimated particularly at the system level
- Work with industry to solve the technical challenges

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