# Presentation: 558105

## Readout for the HFT at  STAR

**Notes:**
Hi, I’m going to talk a bit about the readout for the Heavy Flavor Tracker at STAR.

## A Stand-alone Heavy Flavor Tracker for STAR

Z. Xu
Brookhaven National Laboratory, Upton, New York 11973
Y. Chen, S. Kleinfelder, A. Koohi, S. Li 
University of California, Irvine, California
H. Huang, A. Tai
University of California, Los Angeles, California 90095
V. Kushpil, M. Sumbera
Nuclear Physics Institute AS CR, 250 68 Rez/Prague, Czech Republic
C. Colledani, W. Dulinski, A. Himmi, C. Hu, A. Shabetai, M. Szelezniak, I. Valin, M. Winter
Institut de Recherches Subatomique, Strasbourg, France
M. Miller, B. Surrow, G. Van Nieuwenhuizen
Massachusetts Institute of Technology, Cambridge, MA 02139
L. Greiner,  H.S. Matis, M. Oldenburg, H.G. Ritter,  F. Retiere, A. Rose, K. Schweda, E. Sichtermann,  J.H. Thomas, H. Wieman, N. Xu, and more STARs!
Lawrence Berkeley National Laboratory, Berkeley, California 94720
I. Kotov
Ohio State University, Columbus, Ohio 43210

- Z. Xu
- Brookhaven National Laboratory, Upton, New York 11973
- Y. Chen, S. Kleinfelder, A. Koohi, S. Li
- University of California, Irvine, California
- H. Huang, A. Tai
- University of California, Los Angeles, California 90095
- V. Kushpil, M. Sumbera
- Nuclear Physics Institute AS CR, 250 68 Rez/Prague, Czech Republic
- C. Colledani, W. Dulinski, A. Himmi, C. Hu, A. Shabetai, M. Szelezniak, I. Valin, M. Winter
- Institut de Recherches Subatomique, Strasbourg, France
- M. Miller, B. Surrow, G. Van Nieuwenhuizen
- Massachusetts Institute of Technology, Cambridge, MA 02139
- L. Greiner,  H.S. Matis, M. Oldenburg, H.G. Ritter,  F. Retiere, A. Rose, K. Schweda, E. Sichtermann,  J.H. Thomas, H. Wieman, N. Xu, and more STARs!
- Lawrence Berkeley National Laboratory, Berkeley, California 94720
- I. Kotov
- Ohio State University, Columbus, Ohio 43210

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
These are the people involved and working on this effort.

## STAR HFT 

- _STAR HFT _

- Two layers
- 1.5 cm radius
- 4.5 cm radius
- 24 ladders
- 2 cm X 20 cm each
- ~ 100 Mega Pixels

**Purpose:**
**Greatly improve D meson capability in STAR**

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
The structure that does the tracking is shown here. This is the low mass tracking region. As you can see, there are 24 ladders arranged in 2 annular rings. 6 ladders in the inner and 18 ladders in the outer. Each blue tile represents a sensor. 

## HFT Ladder

- 10 MimoSTAR detectors / ladder (green)
- I => V conversion and driver electronics (blue)
- All ladders are the same

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
What is it that we need to read out? Each ladder has identical readout and electronics.

## MimoSTAR Detector Pixel Structure

- Mimosa5 detectors in a wafer

- Serial raster readout
- 640 pixels in a row
- 320 column / sector
- 2 sectors / detector
- 4 ms readout time (50 MHz pixel read clock)

- _MimoSTAR Detector Pixel Structure_

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
Let’s start at the detector. Raster scan readout. 

## I => V Conversion and driver electronics

- 20 I => V converters / drivers per ladder
- Additional clock, control and JTAG connections. Power and ground
- Analog signals and clock/control is transferred to the motherboard via fine twisted pair cable.

- _I => V Conversion and driver electronics_

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
Moving to the ladder, we have 10 detectors with 2 sectors each for 20 analog data streams per ladder plus clock, control, etc. This is basically what we need to design the readout electronics to handle. This is essentially the starting point of the readout electronics. What follows is what we do to process these signals and reduce the data to a manageable rate.

## HFT Readout Functional Goals

- Digitize every 20 ns.
- Triggered detector system fitting into existing STAR infrastructure.
- Deliver full frame events to STAR DAQ for event building at approximately the same rate as the TPC.
- Reduce the total data rate of the detector to a manageable level (<< TPC rate)
- Reliable, robust, cheap, etc.

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
Now we know what comes out of the detectors and the size and magnitude of the data stream that we need to deal with. What is required from the readout system to fit into the STAR framework with the greatest efficiency?
The first requirement is one driven by the technology of the aps sensors that we are using.
The second is to minimize the impact on daq, trigger, event building and offline analysis.
The third is driven by the necessity of having all of the data for a particular event written into the same file. STAR offline analysis does not currently do multiple related file analysis.
The third requirement is driven just by the resources available.

## Functional Block Diagram

- The readout system is a large parallel system. The block diagram shown above is for one ladder of a 24 ladder system.

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
Here’s a functional block diagram of what we are proposing. The entire system is pipelined and synchronous with the 50 MHz clock. Data is digitized. CDS is performed. Then hit and cluster finding. The data is then passed to buffers to be read out. We are using the ALICE developed SIU and RORC since it is what the TPC is using, is suited to our needs, and allows us to benefit from the experience already developed at STAR.

## ADC and CDS Block Diagram

- Synchronous Correlated Double Sampling and hot pixel removal.
- 8 bit data after CDS.
- Perform read – subtract – write on each clock tick.

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
The analog signals go through CDS where the value from the last pixel read is subtracted from the current read. This is implemented in an FPGA with SDRAM providing the circular buffer which is the map of the pixels inside each sector.

## Cluster Finding FPGA

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
This describes a simple FPGA algorithm to write out the 8-bit data for a 9 pixel cluster. The key is that this is a synchronously clocked system. At any point, there are 2 complete columns plus  the three pixels that form a contiguous block of 9 pixels. At the trigger of a high threshold, the data and center pixel address are latched in parallel into a cluster fifo for readout. This is a simple example. One can see that with the addition of more logic at the shift registers, one could impose additional low and combinatoric threshold conditions for the definition of a cluster. These cluster finding methods are currently under investigation. An elegant possibility is being able to adjust our logical definition of a cluster such that we would need to include only the address of the pixel containing the center of the cluster. If we can do that, we can significantly reduce the data rate. This is shown on the next slide.

## Slide 11

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
This is the same idea as before. The data is serially processed through a hi/low threshold discriminator. The resulting 2 bit result is written to the shift registers. As before, logic done on the results of the high/low threshold pattern can be done on the sliding window of 9 cluster possibly cluster forming pixels. A positive result will tell the cluster FIFO to load the addresss.

## Cluster FIFO

- Trigger enables FIFOs sequentially for 1 frame ( 204,800 clocks) with an offset to the enable that aligns the event start time with the location of the first pixel in the event.
- Each event FIFO is a  separate trigger event stream and can be enabled independently. This allows events to be triggered at ~1 ms intervals with our 4 ms latency.
- Each sector event FIFO is emptied by the SIU at the end of the frame.

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
Update this one

## Implementation Diagram

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
When we put it all together, we have the implementation diagram that you see above. A very nice feature of this design is that we already have been working on this hardware for a while. This is functionally what we have been developing to read out the prototype MIMOSA5 ladders that we ave been working with. Here is an example of the daughter card (show sample) that we have developed that is compatible with the address only version of the design. We would need a larger fpga to fit in the adc data version, but a lot of the vhdl pieces such as the memory and adc interfaces are already working. So we have quite a head start in this.

## Some Relevant Numbers

- bits/address = 18
- Number of inner ladders = 6
- Number of outer ladders = 18
- Sectors (half chips) per ladder = 20
- ave hits/half chip, inner, (L = 1027) = 200
- ave hits/half chip, outer, (L = 1027) = 40
- 1 KHz event rate.

- LG - STAR Upgrades Workshop Dec. 2005

## Data Rates

- Average event size = 90 KB
- Event size = 90 MB/sec at 1KHz
- 24 fibers
- 12 RORC (4 readout PCs)

- LG - STAR Upgrades Workshop Dec. 2005

**Notes:**
This is the event rate thatis passed to DAQ. There is some additional processing available to further reduce the data before it is built into an event and written to tape. In particular, in the case of the saved ADC values, these could be processed and the position of the centroid saved, greatly reducing the data rate for that case.

## Features of HFT Readout Scheme

- The daughter board hardware will provide the full data rate and functionality required for a complete first generation 4 ms HFT solution.
- Much of the required VHDL firm ware is running, tested and understood
- The cluster identifier runs at the same speed as digitization providing immediate data compression.  Only cluster center addresses are passed on for data storage.
- Data digitization and compression takes the same 4 ms for all events independent of data.
- The cluster identifier and data compression fits well in the FPGA environment.  It requires few resources and can be implemented  with simple straight forward VHDL coding.
- The design is triggered and fits the standard DAQ design.
- All the hits for an event are stored directly for that event.  There are no complications with frame boundaries or hits for an event located in different frames.  This is important because file handling software used in STAR data analysis does not have to be altered to accommodate the HFT.
- The latency is 4 ms, but the dead time is 1 ms matching the new TPC system.
- The HFT data size for an event is 90 kBytes, significantly less than the 2 Mbytes for TPC central collision event.

- LG - STAR Upgrades Workshop Dec. 2005

## Data Format

| Event/Header |
| --- |
| ladder address 0 |
| half chip address 0 |
| pixel address 157,921 |
| pixel address 159,203 |
|    .
   .
   .
   .
   .
   . |
| pixel address 142,888 |
| pixel address 148,321 |
| half chip address 1 |
| pixel address 155,423 |
| pixel address 155,231 |
|   .
  .
  .
  .
  . |
| ladder address 1 |
| half chip address 0 |

- 18 bit wide words

- LG - STAR Upgrades Workshop Dec. 2005