# Presentation: 388534

## Atlas CSC ASMII

- _[Kurt Vetter](http://www.inst.bnl.gov/~vetter/atlas/asmII.html)_
- Brookhaven National Laboratory
-  Presented at UCI
- May 9, 2000

## Topics

- Introduction and key facts
- Design Details
- Optical Links
- Radiation

## Slide 3

## ASMII FACTS	

- 5 per chamber
- 4 x-strip (2 per side)
- 1 y-strip
- 320 per system (256 x-strip, 64 y-strip)
- Total Material Cost $629,650
- $2,000 per ASMII
- 192 Channels per ASMII

## KEY MILESTONES

- Preliminary Design Review (PDR) – June 2000
- Beam Test – August 2000
- ASMII/Sparsifier Integration – April 2002
- ASMII Final Design Review (FDR) – March 2003
- Production Readiness Review (PRR) – July 2003
- ASMII production begins – August 2003
- ASMII fabrication complete – February 2004
- ASMII installation – April 2004

## ASMII Design Evolution

- ASMIIa
- 24-Channels
- FIFO Readout

**Design Objectives**
- - Develop SCA Controller
-  Test SCA (muon mode)
-  Preamp/SCA interface
-  Remote SCA control
-  Characterize ADC
-  Evaluate Noise
-  Beam Test Electronics

- ASMII
- Intermediate
- Prototypes

**Design Objectives**
-  192 Channels
-  Develop Readout Architecture
-  Develop Optical Link’s
-  Characterize Noise

- ASMII
- Final
- Design

## ASMII Block Diagram

## ASMIIa Block Diagram

## DESIGN DETAILS

## Power, Ground and Cooling

- 65W max per faraday shield
- Ground from ASMII to Faraday shield through ASMI?
- Cooling pipe circulates through faraday shield
- Thermal padding between ASMII and faraday shield
- Faraday shield bolted to chamber

|  | 1- GLink Tx (HDMP1022)
1- GLink Rx (HDPM1024) | 2-Glink Tx’s
1-Glink Rx |
| --- | --- | --- |
| ASMI | 2.4 watts | 2.4 watts |
| ASMII | 25.2 watts | 27.5 watts |
| Total per half chamber | 60 watts | 64.6 watts |

## Analog Design

**CHALLANGES**
- Pre-Amp to SCA interface
- SCA readout > 5MHz?
- ADC performance
- Board Layout

**Main Components**
**SCA**
- 		- 144x16 cells
- 		- 40MHz sampling rate
- 		- 8MHz readout?
- 		- 5V supply (1v-4v input linear dynamic range)
**AD9042 (ADC)**
- 		- 12 bits		- Thermal noise = 0.33LSB	     - DNL = +-0.4LSB
- 		- 600mw 		- Input BW = 100MHz	     - INL = +-0.75LSB
- 		- +5V supply	- Analog in = Vref +-0.5v	     - SNR = 67dB

## Digital Design

- Readout Constraints
- Readout Numerology
- Readout Architectures

## Readout Constraints

- Number of Optical Readout Links determined by
- SCA Readout Rate (5-8MHz)
- Number of samples
- SCA READ CLOCK
- Determined by the number of samples
- SCA requires 15 read-clock cycles to read 12-channels
- To readout 4-samples in <10us (L1=100KHz)
- SCA read clock >= 6.67MHz
- OPTICAL LINK
- As rate increases less time to package data into G-Link
- 192 bits packaged into G-Link within one read-clk cycle

## Readout Time and Data Rate

## SCA Readout Numerology

## Four Sample(12 ch. Per sample) SCA readout

## Single Sample (12 channel) SCA readout

## ASMII Readout Scheme Block Diagram

## Possible Link Configurations

|  LINK CONFIGURATION |         COMMENTS |
| --- | --- |
| Two Links @ 40MHz (SFM)
2-bits per ADC | Cannot support 5-samples.
4-samples may be tight. |
| Single Link, double frame Mode 2-bits per ADC  | Cannot support SCA readout
>5MHz. |
| Two Links double frame mode
4-bits per ADC | Can support 5-samples.
 |

- * Double frame mode implies 80MHz frame clock.

## Readout Implementation2-Bits per ADC, Single Frame Mode(1 of 2 links shown)

- Shift
- register

- Shift
- register

- 12

- 6

- 6

- 40MHz

- 40MHz

- From ADC 1

- D11..D6

- D5..D0

- 40MHz

- 6 cycles to shift out data
- RDclk = Wclk/6 = 6.67MHz
- Pipeline cannot accommodate higher readout rates.

- 4x per IC,
- 4-IC’s service 16 ADC’s

- From ADC 8

- D15

- D14

- G-Link
-  1 of 2

- D1

- D0

## Readout Implementation 2-Bits per ADC, Double Frame ModeOne Link Required

- G-Link

- 40MHz

- 16

- 40MHz

- a

- b

- a

- b

-  8

-  8

-  8

-  8

- Readout
- IC

- Readout
- IC

- Readout
- IC

- Readout
- IC

- 48

- ADC (1-4)

- 48

- ADC (5-8)

- 48

- ADC (9-12)

- 48

- ADC (13-16)

- a

- b

- Readout Implementation 2-Bits per ADC, Double Frame ModeOne Link Required

- Can add register before mux at 40MHz.
- Select mux at 80MHZ.
- 80MHz derived from G-Link STRBOUT.

## Readout Implementation 4-Bits per ADC, Double Frame Mode

- G-Link

- 40MHz

- 16

- 40MHz

- a

-  16

-  16

- Readout
- IC

- Readout
- IC

- Readout
- IC

- 48

- ADC (1-4)

- 48

- ADC (5-8)

- 48

- ADC (9-12)

- 48

- ADC (13-16)

- b

- G-Link

- 40MHz

- 16

- 40MHz

-  16

-  16

- a

- b

- Readout
- IC

## Readout Link Summary

- Serialize ADC’s to dedicated G-Link lines
- Number of ADC lines determined by SCA readout rate.
- SCA readout rate determined by number of time samples.
- Monitored data (supply current, temp)
-     fused into one Link.

## UCI Wish List What can BNL do to help?

- ADC lines can be serialized into G-Link.
- Readout links can be configured to dedicated planes
- if two links are used.
- Sequential output ordering may be possible by adjusting pre-amp to SCA interconnect.
- Sequential ordering achieved locally on ASMII.
- No inter-ASMII communication.
- Chamber ordering achieved by fiber cable interconnect.
- Monitoring data presented in same format as data.
- Only useful data will be sent.
- For two transmit Link approach, data width is 16-bits.
- Links should support double-frame mode at 80MHz.
- Readout will be determined by SCA controller on Sparsifier

## Optical Links

- One receiver required
- One or two transmitters?
- Probably two
- Two links provide inherent redundancy
- Also more power and space
- HDMP 1032/34 available
- Lower power (590mw Tx, 660mW Rx)
- Lower BW (1.12 Gbps)
- 16 bit interface

## RadiationASMII IC’s

| COMPONENT | COMMENTS |
| --- | --- |
| HDMP 1022 | Extensive testing has been performed.
Should conduct our own test. |
| HDMP 1024 | No testing performed.
Must test on our own. |
| SCA | Testing to be completed by LAr. |
| AD9042 (ADC) | Used on LAr FEB.
Ionizing survival test done by LAr. |
| AD8042 (op-amp) | Used on LAr FEB.
Ionizing survival test done by LAr. |
| Level Translators? | Required for SCA. Need to select and test. |
| DAC (used for Calibration PFN)
 | Need to select and test. |
| Readout Interface IC 
(FPGA or ASIC?) | Need to choose technology and test. |