# Presentation: 260414

## New Strategies for Radiation Hard Electronics

Ronald Lacoe, Donald Mayer, Jon Osborn and Stephanie Brown
Microelectronics Technology Department
Laboratory Operations, The Aerospace Corporation

2001 MRQW
December 11, 2001

- Ronald Lacoe, Donald Mayer, Jon Osborn and Stephanie Brown
- Microelectronics Technology Department
- Laboratory Operations, The Aerospace Corporation
- 2001 MRQW
- December 11, 2001

## Overview

- Why rad-hard-by-design targeting commercial foundries now
- “Push” from rad-hard foundries
- “Pull” toward commercial foundries
- Designing in radiation hardness
- Where we are today – technically
- Summary

## “Push” from Rad-Hard Foundries:Lagging Performance

- Microprocessors

- Memories

- Rad-Hard Lags 2-3 Generations Behind Commercial

## “Push” from Rad-Hard Foundries:Disappearing Foundries

**2 Digital /2 Analog**
**BAES & Honeywell/**
** ****Intersil & ADI **

**18**

**11**

**11**

**6**

**1985**

**1993**

**1995**

**0**

**2**

**4**

**6**

**8**

**10**

**12**

**14**

**16**

**18**

**7**

**4**

**7**

**4**

**Total Dose Hard**

**Upper-Hard**

**1985**

**1993**

**1995**

**1998**

**National & UTMC**

- *DTRA 1999

## “Push” from Rad-Hard Foundries:Low Volume Issues

- Low volume foundries potentially have difficulty:
- Achieving high yields
- Maintaining process stability resulting in schedule slippage
- Achieving competitive pricing

## “Pull” Toward Commercial Foundries:Performance Ahead of 1999 SIA Roadmap

- UMC Core Logic Roadmap

- 0.18

- 0.13

- 0.15

- 0.10

- 1999 SIA

## “Pull” Toward Commercial Foundries:Performance Ahead of 1999 SIA Roadmap

- TSMC Core Logic Roadmap

## “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Gate Oxide Threshold Voltage Shifts

- Gate oxide threshold voltage shifts depends on the square of the gate oxide thickness:
- each technology generation jump, oxide thickness decreases  radiation-induced threshold voltage shifts decrease
- For tox~ 50Å, quantum mechanical tunneling dominates and expect negligible threshold voltage shifts
- Difficult to design around gate oxide threshold voltage shifts

## “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Gate Oxide Threshold Voltage Shifts

- Decrease in VT due to thinner oxides, not “better” oxides

## “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness-- Isolated Transistor Edge Leakage

- As technology scaled, transitioned from
- 		standard LOCOS  recessed LOCOS 
- 		shallow trench isolation (STI)
- Unintended consequence of this scaling is improved edge total dose hardness  less edge leakage
- reduces/eliminates “birds beak” region at edges

## “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Isolated Transistor Edge Leakage

**Thinner gate and isolation oxides results in less hole trapping**
**Isolation oxides process and quality increasing as go from LOCOS to Recessed LOCOS to STI technologies**

## “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Isolation Oxides

- Isolation oxides are thick oxides, and hence, can trap lots of holes, resulting in large VT shifts
- If shift sufficient such that inversion occurs at or below the operating voltage, can degrade interdevice isolation
- Data to date suggests this is the weak-link from a total dose hardness viewpoint

## “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Isolation Oxides

- Chartered 0.35
- Recessed LOCOS

- TSMC 0.25
- Recessed LOCOS

## “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Dynamic Operation

- TSMC 0.25

- No change in power-delay product up to 3 Mrad(Si)

## “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Self Annealing

- Data indicates for both edge leakage and isolation oxide, get nearly full recovery after a biased high-temperature anneal
- Indicates most of the radiation induced degradation is associated with low-energy-trapped charge
- In space, natural dose rate is at least 10,000 x lower than that used during Mil. Std. 1019 testing dose rate
- When factor in annealing, can get substantial increase in process total dose hardness

## “Pull” Toward Commercial Foundries:Well-Controlled Processes

- HP 0.5

## Overview

- Why rad-hard-by-design targeting commercial foundries now
- Designing in radiation hardness
- Total Dose, SEE, SEL, and Prompt Dose
- Performance Comparison
- Two Approaches
- Where we are today
- Summary

## Designing In Radiation Hardness:Approach

- Leverage intrinsic total dose hardness and performance of commercial foundries
- Use design techniques to
- Achieve additional total dose hardness
- Mitigate against single event effects
- Mitigate against prompt dose effects

## Designing In Radiation Hardness:TID Hardness--Annular Transistors

- Off-state leakage remains low
- Increased die size
- Only needed for NMOS

- TSMC 0.25

## P+ guardband around NMOS devices prevents interdevice leakage by locally increasing the isolation oxide threshold voltage
Pay an area penalty that depends on foundry design rules and implementation strategy

- Pay an area penalty that depends on foundry design rules and implementation strategy

- Designing In Radiation Hardness:TID Hardness--Guardbands

## Designing In Radiation Hardness:SEE Mitigation

- As CMOS technology is scaled, individual nodes of data latches become more susceptible to upset
- Decreased charge storage capacitance and supply voltage ****** **decreased SEU threshold ?? ****** **increased SEUs ??
- Single-event upset mitigated with design and process techniques
- Rad-Hard foundries use either resistive damping, capacitive damping, or redundancy in design techniques
- Commercial foundries, in general, do not support resistor fabrication for resistive damping

## Designing In Radiation Hardness:SEE Mitigation Techniques

- Univ. of New Mexico
- HP 0.35 m, 0.5 m
- LET>160 MeV/mg-cm2

## Designing In Radiation Hardness: Single-Event Latchup

- Commercial foundries address and design to prevent against latchup during circuit operation
- As devices are scaled, Vdd is lowered which helps mitigate against latchup
- Once Vdd is below the sustaining voltage for latchup, latchup cannot occur
- Many commercial parts do not latchup in a space environment
- Latchup hardness can be enhanced with process changes
- Epitaxial starting material can reduce series resistance

## Designing In Radiation Hardness: Single-Event Latchup Mitigation

- Latchup hardness can be enhanced with design techniques
- Well separation or guardbands can suppress positive feedback path
- Multiple ground contacts can reduce series resistance

- Guardbands can significantly improve latchup hardness of CMOS integrated circuits

- Standard

- Guardbands

- NAND Gate

## Designing In Radiation Hardness: Prompt Dose Issues

- Design to avoid rail span collapse
- Well contacts
- Wide and/or redundant power and ground busses
- Bulk CMOS processes limited to about 5E9 rad/sec ? operate through levels
- Need SOI or SOS to achieve > 1E10 rad/sec
- Minimal hardware with operate-through requirements
- Potential foundries with SOI/SOS capabilities
- Peregrine (SOS)	-  SPAWAR (SOS)
- DMEA (SOS)	-  Lincoln Labs (SOI)
- Sandia (SOI)	 - Commercial SOI (?)
- Honeywell (SOI)

## Designing In Radiation Hardness: Performance Comparison

- Std. Design
- 0.35-m Comm.

- Std. Design
- 0.50-m “Rad-Hard”

- Rad-Hard-By-Design
- 0.35-m Comm.

**Edgeless**
**Transistor**

**Widened **
**Busses**

**Guard**
**Bands**

**1x  Area**

**1.7x  Area**

**2.3x  Area**

- 2NAND
- Logic Gate

## Designing In Radiation Hardness: Selected Performance Parameters

- HP

- HP

- HP

- 0.35 μm

- 0.35 μm

- 0.5 μm

- Parameter

- Commercial

- RHBD*

- "Rad-hard"

- Lambda, μm

- 0.20

- 0.20

- 0.30

- Cell area, μm

- 2

- 51.00

- 88.44

- 114.75

- W/L(n)

- 5.00

- 12.00

- 5.00

- W/L(p)

- 9.00

- 20.00

- 9.00

- Supply voltage, V

- 3.30

- 3.30

- 5.00

- Propagation delay,

- ns (FO=2)

- 0.10

- 0.09

- 0.14

- Power dissipation, μW/MHz

- 0.29

- 0.64

- 1.10

- Power delay product,

- aJ/MHz

- 38

- 80

- 168

- Gate density, Mgates/cm

- 2

- 1.96

- 1.13

- 0.87

- Maximum operating frequency, MHz

- 376

- 402

- 328

- Throughput per watt, Mgates-MHz/cm

- 2

- /μW

- 6.82

- 1.75

- 0.79

- *Rad-Hard-By-Design (RHBD)

- 2NAND
- Logic Gate

## Designing In Radiation Hardness: Cell Libraries

- Wide range of cell libraries possible (but not required) to reflect varying mission environments and threats
- Can optimize cell libraries for specific missions at the cost of multiple library development
- Two extremes
- Maximum performance approach
- Accept intrinsic radiation hardness of commercial process
- Use foundry standard cell library
- Foundry does layout and verification
- Lower risk approach
- High Margin approach
- Use aggressive design techniques to further mitigate against total dose, SEE and weapon effects
- Requires custom standard cell library
- Layout and verification done by contractor
- Higher risk approach

## Overview

- Why rad-hard-by-design targeting commercial foundries now
- Designing in radiation hardness
- Where we are today
- Total Dose
- SEE
- Prompt Dose
- Reliability
- Conclusions

## Where We Are Today:Total Dose

- Efficacy of annular transistors and guardbands demonstrated at the single transistor level
- CERN is building approximately 100 large ASICS for the Large Hadron Collider Experiment
- Employ annular transistors and p+ guardbands
- Driven to approach by cost and performance advantages over rad-hard approach
- Using the IBM 0.25 m process
- Largest circuit to date contains 13 million transistors
- Pixel Readout Integrated Circuit (ROIC)
- Not yet established what the density, power, and performance impact of RHBD will be

## Where We Are Today:Single Event Effects

- Long history of using design approaches for mitigating against Single Event Effects at the Rad-Hard Foundries
- Design-hardened latches have been demonstrated (UNM) with greater than 160 LET SEU thresholds
- The potential and limitations of system level approaches to achieve SEU hardness, such as EDAC and TMR, have not been well explored at the chip level
- Mitigation against Single-Event-Transients (SETs) remains a challenge for both RH and RHBD approaches

## Where We Are Today:Prompt Dose

- Data supports hardness of 5E9 rad/s in bulk CMOS
- Can we go higher?
- Generally believed to achieve hardness greater than 1E10 rad/s, need an insulating substrate technology
- Three components to prompt dose mitigation: circuit design, wafer technology, circuit fabrication process
- With RHBD, control design
- May be able to get foundry to allow user-supplied wafers
- Cannot control process
- Design approaches well understood, but have not been implemented in large scale circuits at commercial foundries

## Where We Are Today:Hot-Carrier Reliability

- TSMC 0.18

**10 yrs**

**1.8 V**

## Conclusion

- Market forces driving space technology toward commercial part performance
- Trend toward increased total dose hardness in commercial CMOS foundries increases the attractiveness of a RHBD approach
- RHBD techniques have been demonstrated for TID, SEE, and Prompt-Dose Mitigation at the device level, but validation not yet complete

## Backup Slides

## Selected Performance Parameters

| Parameter
 | TSMC 0.35 um
Commercial | TSMC 0.35 um
RHBD | HP 0.5 um
“Rad-Hard” |
| --- | --- | --- | --- |
| Lambda, um | 0.20 | 0.20 | 0.30 |
| Cell area, um2 | 51.00 | 88.44 | 114.75 |
| W/L (NMOS) | 5.00 | 12.00 | 5.00 |
| W/L (PMOS) | 9.00 | 20.00 | 9.00 |
| Gate capacitance, fF | 10.04 | 30.12 | 18.31 |
| Output capacitance, fF | 8.49 | 10.87 | 11.71 |
| Floating node capacitance, fF | 2.28 | 8.97 | 2.41 |
| Miller capacitance, fF | 3.17 | 10.41 | 4.29 |
| Interconnect capacitance, fF | 16.71 | 22.01 | 29.89 |
| Supply voltage, V | 3.30 | 3.30 | 5.00 |
| Output current, avg, H-L, mA | 0.51 | 1.22 | 1.13 |
| Output current, avg, L-H, mA | 0.92 | 2.21 | 1.98 |
| Propagation delay, ns (FO=2) | 0.13 | 0.12 | 0.15 |
| Power dissipation, uW/MHz | 0.29 | 0.64 | 1.10 |
| Power-delay product, aJ/MHz | 38.2 | 80.2 | 167.7 |
| Gate density, Mgates/cm2 | 1.96 | 1.13 | 0.87 |
| Max operating frequency, MHz | 376 | 402 | 328 |
| Throughput per W, Mgates-MHz/cm2/uW | 6.82 | 1.75 | 0.79 |

## Impact of Bias Conditions on TID Mechanisms*

- * DR Alexander and DG Mavis, “Design Issues for Radiation Tolerant Microcircuits in Space,”
-           1996 IEEE NSREC Short Course