# Presentation: 801754

## Detector Technologies for an 

- All-Semiconductor Tracker at the sLHC
- Hartmut F.W. Sadrozinski
- SCIPP, UC Santa Cruz

## Divide the sLHC Tracker into 3 radial regions with 10x fluence increase

- Fluence is a factor 10 higher than at the same radius in LHC:
- “ move systems outward” SCT -> Straw tubes, Pixels -> SCT, need new Pixels
- System performance can then be estimated.
- Guess at a specification of the charge needed in the 3 regions:

| Radius
[cm] | Fluence
[cm-2] | Specification for Collected Signal /
(CCE) | Detector Technology
Large areas -> Simple & Inexpensive |
| --- | --- | --- | --- |
| > 50  | 1014 | 20 ke-
(~100%) | “present” LHC SCT Technology, 
Consider: n-on-p  |
| 20 - 50 | 1015
 | 10 ke-
(~50%) | “present” LHC Pixel Technology ?
Consider: n-on-p  |
| < 20 | 1016
 | 5 ke-
(~20%) | RD50 - RD39 - RD42 Technology |

## Required Studies

| Radius /
Fluence | Limitation due to: | Simulations Needed |
| --- | --- | --- |
| > 50 cm
1014 | Leakage Current | Tracking Simulations: Layout Optimization |
| 20 – 50 cm
1015 | Depletion Voltage | Tracking Simulations: Strip length and stereo angle Optimization |
| < 20 cm
1016 | Trapping Time | Charge Collection/Trapping Simulations |

- Tracking detector technologies are limited by radiation
- The limiting process is different in the different radial regions
- This motivates different studies

## Simple SSD layout at Radius  > 20 cm

**Simple SSD layout at Radius  > 20 cm**
- 3 cm strip length vs. 12 for SCT
- R > 50 cm: Single layers,
- z  1cm
- 20 < R < 50 cm: Back-to-back single-sided
- z  1mm
- Problem:
- Confusion of stereo assignment
- Mitigated by length reduction
- But strips are much easier to build
- Explore availability of p-type substrates
- 	No type inversion
- 	Collect electrons
- 	Partial depletion operation
- Potential for semi-3D?

## SSD technology for radius  > 20 cm:

**SSD technology for radius  > 20 cm:**
- Recent results from ATLAS SCT beam test illustrates problem with charge collection after type inversion in common p-on-n detectors.
- N-on-p would provide much more “head room” in bias voltage
- (cheaper than n-in-n ?)
- But: electrons have larger Lorenz angle (tilt of SSD)

## Technologies for Inner-most “Pixels” System 

- Technologies for Inner-most “Pixels” System
-  Limitation: Trapping
- _1. Charge Trapping in Si SSD:_
- Collected Charge Q = Qo*(depletion)* (trapping)
- (depletion) depends on Vbias , Vdep -> effective detector thickness w
- 
- (trapping) = exp(-c/ t),
- 		c : Collection time
- t : Trapping time
- Trapping time is reduced with radiation damage:
- 	1/ t = 5*(ns-1
- 		(same for electrons and holes, measured up to cm-2
- t ~ 1/ 
- t = 0.2ns  for cm-2

## 2. Charge Collection in Si SSD of thickness w:

- _2. Charge Collection in Si SSD of thickness w:_
- Assume linear field (Diode case), field at depth x
- E(x)  = Eo + Em*(x/w) = Eo + 2*Vdep*(x/w2)
- Collection time  without Saturation
- c = ∫dx/v = ∫dx/(E(x)) = w2/(2Vdep)*ln{(1+R)/(R+(x/w))}
- R determines the over-depletion R = 1⁄2*(Vbias – Vdep)/Vdep
- Vdep is approximately proportional to fluence :
- Vdep (300um)  300V*(Vdep (100um)  30V*(
- 	c = 1/ t ~ 1/ 
- 		Without saturation c/ t independent of fluence !

## 3. Charge Collection in Si including Saturation:

- _3. Charge Collection in Si including Saturation:_
- Drift velocity saturates at v  107 cm/sec for E > 5*104 V/cm for electrons,		 	v about 30% -50% lower for holes
- Thus the collection time c depends on the thickness of the depleted region
- c = w/v = (w/100um) ns,
- 			for heavily damaged detectors (large Vdep and E)
- c  1 ns for w = 100um
- Saturation of the drift velocity  -->   c/ t ~ 
- c/ t = 1 for 20 um after  cm-2 !

## 4. Charge Collection in Si including Saturation:

- _4. Charge Collection in Si including Saturation:_
-  (Simple spread sheet study, agrees with data, full simulations and V. Eremin)

| Fluence  
[cm-2] | w @ 600V
[um] | c/ t | Q estimated
[k e-] | Q measured
[k e-] |
| --- | --- | --- | --- | --- |
|  | 300 | 3/10 | 19.4
86 % | 82% 
Casse et al |
|  | 300 | 3/2.5 | 13.0
58% | 65%
Casse et al |
|  | 140 | 1.4/0.2 | 1.3
6% | full simulations
Also V. Eremin  |
|  | 50 at 100V | 0.5/0.2 | 7.4    
33% | 3-D detectors |

##  3-d Detectors  

-   Differ from conventional planar technology, p+ and n+ electrodes are
-     diffused in small holes along the detector thickness (“3-d” processing)
-   Depletion develops laterally (can be 20 to 100 m): not sensitive to thickness

**Depletion**

- Sherwood Parker et al.,
- Edge-less detectors

**n**

**n**

**p**

**p**

**n**

**n**

**n**

**n**

**50-100 ********m**

**Depletion / Collection de-coupled **
**from Generation:**
- Depletion and Drift over short distance:
- much higher radiation tolerance

##    5. Detector Materials for Pixels for R < 20 cm 

| Material |  | Collected Signal | Comment |
| --- | --- | --- | --- |
| Si  | RT | < 2 ke- | Trapping: Not enough signal |
| Si | Cryo
 |  “Better than RT”
e.g. ~ 4 ke- with 3x less traps (?) | Can traps kept frozen out permanently ? 
Cryo Engineering |
| Si | 3-D |  ~ 7 ke- | Cost of Manufacturing |
| SiC | Epi
 | < 2 ke-
 | Trapping still problem, 
relatively slow collection
Cost of wafers |
| Diamond | Poly
 | < 3 ke- ? | Trapping ?
Cost of wafers |
| Diamond | Single
 | “Same as Poly?” 
 | Trapping ?
Cost of wafers |

## R&D Topics:

- P-type substrates: work with Japanese groups/HPK
- Find radiation source to irradiate to  = 1016 cm-2
- Measure trapping on cryogenic detectors
- Fabricate 3-D detectors with Japanese groups/HPK