# Presentation: 112817

## Tracking Upgrade R&D Meeting.Columbia University 

**A. Seiden**
**September 22, 2003**

## Assumption: Three regions for tracker. 

**Luminosity increase will be approximately a factor of 10.**
**r ≤ 20cm, separate volume tracker which may have to be periodically replaced. Don’t, even in principle, at present know how to do this part.**
**20cm ≤  r ≤  50 cm, region with fluence comparable to pixel detector now under construction.**
**50cm ≤  r, region with fluence comparable to strip detector now under construction.**
**Guess at what is needed:**
**3 layers for (1), 4 layers for (2) and 4 layers for (3).**

## Region (3)

**Reasonably simple detector may well be adequate. For example:**
**6cm detector split in half gives 3cm active region. Resolution along Z is then around 9mm compared to no resolution in straws. Good measurement of polar angle provided by inner layers.**
**Rate reduction: 4 from segmentation, 4 from increase in r2.**
**Detector and fiber readout should be okay with modest improvement in detector hardness. 0.25 micron CMOS works, but need for a large frontend transistor makes it difficult to realize power savings. SiGe analog section may be a very attractive choice. Need to clarify radiation hardness.**

## Slide 4

## Readout Electronics:

**The 0.25 micron CMOS processes are being successfully exploited for ATLAS and CMS.  **
**The industry is moving smaller. Preliminary results with the 0.13 micron technology show equally good results there are concerns about adequate analogue performance.  **
**The telecommunications industry is driving development of SiGe biCMOS processes which may provide superior analog performance, especially for larger capacitive front-end loads**
**The IBM processes, for example, have a SiGe bipolar process married to their standard submicron CMOS processes.  These are now available through MOSIS.  **

## CMOS vs. SiGe Front-End:

|  | 0.25m CMOS | IBM 7HP SiGe |
| --- | --- | --- |
| Analog Power:
Bias for all but front transistor | 
400 A      1. mW | 
100 A    0.35 mW |
| Analog Power:Front bias for 25 pF load
(Total power) | 
550 A   1.38 mW
               (2.4 mW) | 
270 A     0.69 mW
              (1.04 mW) |
| Analog Power:Front bias for 7 pF load
(Total power) | 
120 A     0.3 mW
               (1.3 mW) | 
  60 A     0.15 mW
                (0.5 mW) |
| Channel-to-channel matching at comparator | +/- 6% | +/- 3% |
| Band gap reference(for on-chip regulation) | Not available | Available |
| Design margin for faster shaping | No remaining margin at these power levels | Substantial Bandwidth margin remaining |

**A potential savings in power of ~2.5x could greatly simplify the cooling system.**
**It also will solve a difficult system problem of providing large currents over long cables.  **
**Better matching and faster shaping will better meet timing and occupancy requirements.**

## Region (2)

**Pixel detectors look like good choice but not clear that practical issues (enormous amount of bump bonding) are tractable. Back to back strip detectors (same dimensions as in Region (3)) with stereo arrangement might be an acceptable alternative. **
**Occupancy probably acceptable. For example two-sided confusion in matching improved by factor of (4)2 = 16 relative to present detector.**
**Depletion of detectors is an important issue. Signal-to-noise for a 150 micron thick detector should be adequate given 3cm strip length. The thickness reduction reduces depletion voltage by factor of 4. Detectors made with p-substrate might provide the appropriate choice.**

## Summary of R&D Topics:

**Electronics using 0.25 micron CMOS and also SiGe.**
**Detectors using p-type material. Also understand better the performance and limitations of n-type material (oxygenated, Czochralski material, etc.).**