# Presentation: 063402

## Summary of Lesser Packaged SNAP CCDs to Date

## Lesser Packaged CCDs

- 86135.8.9 (UASN5071)
- 107409.11.11 (UASN5450)
- 107409.12.11 (UASN5451)
- 86135.24.15 (UASN5452)
- 86135.8.15 (UASN5455)
- 86135.8.14 (UASN5456)
- 86135.8.8 (UASN5457)

## Flatness Measurements

- Taken on LBL metrology Lab vision machine
- Data extends to with 0.3 mm of CCD edge
- First data point at (0,0), last at (max(x), max(y))
- Data defined wrt least squares best fit plane
- Best fit always reduces standard deviation
- Two cases, best fit plane increases peak-peak separation (UA54570.7 m, UA50711.1 m)
- Option remains to redefine best fit plane for minimization of peak-peak flatness

## 86135.8.9

- L2 and U1 transistors appear damaged or disconnected.  Can read out entire CCD using U2 and L1 transistors.  Only Lesser packaged CCD with full imaging capability.
- No clock shorts detected, all serial and parallel clocks seem to work.
- Image quality good, except for two issues demonstrated in following slides.
- No glue voids, no signs of packaging damage to active region of CCD.

## Slide 5

## 107409.11.11

- Device does not image, significant clock shorts detected on V1-V2 (56 kW), less major short detected on FS2-FS3 (3 MW).  Possible open vias?
- No shorts found in output transistor.

## Slide 7

## 107409.12.11

- This Lesser packaged SNAP device has a 67 k short between FS1 and FS2.
- Given the size and location of the short, ESD is a likely cause.
- The short prevents parallel clocking and readout of the image.
- The wiring harness currently in use in the 6007 gold dewar ties together the FS clocks on both sides of the HMS, so it may be possible to readout half the CCD with a different wiring harness.

## Slide 9

## 86135.24.15

- Lower half of CCD looks great.  Upper half, not so hot.
- There does not appear to be a connection to the reset transistor on U2.
- Horizontal clock lines don't seem to be connected on the U2 side.
- No V clocks and can only image 1/4 of the device using the L2 transistor.
- For the L1U1 half of the CCD, the image is beautiful.  However, the U side
- bias level is strongly dependent on Vsub, varying wildly compared to the L side bias level.  This does not seem to affect the image quality although it does seem to have unusually high gain.
- Two image artifacts detected using L1U1 readout, see following two slides.

## Slide 11

## 86135.8.15

- Device not tested, sent to Fermi Lab for flatness measurements.
- Significant clock shorts detected, see table summary at end of presentation.

## Slide 13

## Scratch on Backside

- Scratch visible upon initial examination, reproduces in image.  Shipping, mishandling?  Not believed to be an artifact of the packaging process.

## Glue Void?

- Possible glue void, only apparent defect in packaging in all 7 CCDs, hard to tell since we cannot image other half of CCD.

## 86135.8.14

- 1.  Saturation near pads on L side of device.  No individual lightbulb evident but glow extends well into the active region, contaminating ~1000 columns.
- Examination of coldprobe data from Lick reveals hints of lightbulb
- before packaging.  However, Lick coldprobe procedure is not adequate to
- quantify or identify the defect.
- 2.  Defective reset feedthrough on U1 transistor.  Decay of reset feedthrough is described by extremely long time constant, with a tail extending into the summing well feedthrough.
- 3.  Defective reset feedthrough on U2 transistor.  Reset does not appear to be fully functional, signficant ropouts observed in otherwise square waveform.  Gain reduced by factor of ~3.
- Defective output transistor on L2 transistor?  Read noise is on the order of 1000 ADU, making identification of X-ray events impossible.
- Bizarre clock behavior observed, see next slide.
- Shorts detected on output transistors between OG-Vdd, ESD likely cause.

## Slide 17

## Dysfunctional Clock

- Defective serial clock in vicinity of U1.  Clock H1 prevents charge transfer, only when grounded is charge transfer possible, albeit highly inefficient.  Left:  central region of image, Clocks at nominal voltages.  Right:  H1 grounded, same region of image.

## 86135.8.8

- U1:  no signs of life.  No response to light or change in RG voltages.  Flat on scope trace.
- L1:  Flat on scope trace at Vsub=70 V.  Feedthrough enhanced at Vsub=100, revealing small but definitive reset feedthrough.  Approximately a factor of 10 smaller than usual.  Also shows response to light, exposure to ambient levels of light increase feedthrough to normal shape and size, however, no indication of integration of charge in scope trace, flat following reset and SW.
- U2:  Reset feedthrough is indecipherable, showing spike and valley as in U2 on 86135.8.14.  No change with light or Vsub.  Repeating problem?
- L2:  Nonexistent feedthrough at 70V, normal at 100 V.  Image L2U2.fits indicates that readout is still not working properly, contaminated with structured noise, but X-rays are evident, with estimated gain of ~0.5.  Scope trace shows some response to light, but not as significant as that observed in L1.
- Shorts observed on output transistor believed to be ESD

## Slide 20

## Streaking Columns

- L1 readout shows significant streaking, but no apparent degradation of CTE.  Only visible in flats, cause unknown.

## Inverted Column

- Occasional inverted columns detected, not believed to be residual from packaging process.  Believed to be caused by break in channel stop.  This artifact has been observed in other CCDs as well.

## Summary

| DEVICE | Images? | Clock Shorts | Transistor shorts? |
| --- | --- | --- | --- |
| 86135.24.15 | YES, U1L1 half | NO | N/A |
| 86135.8.9 | YES, Full array using L1 and U2 | NO | NO |
| 107409.11.11 | NO | YES, FS2-FS3: 3 M
V1-V2: 56 k | NO |
| 107409.12.11 | NO | YES, FS1-FS2: 67 k  | NO |
| 86135.8.14 | YES, L1U1 half | NO | YES, U1: 1 M |
| 86135.8.8 | NO | YES, V1-V2: 2.3 k | YES, U1 and U2: 470 k |
| 86135.8.15 | N/A | YES, H1-H2: 95 k
FS1-FS2: 86k
FS1 (FS2)-Vsub: > 500 k | N/A |