# Presentation: 811818

## BPM  Hardware

- Vince Pavlicek  CD/ESE

- 16 Dec 2003

## Hardware Outline

- Review the data processing architecture presented by Jim.
- Present the constraints we put on our search for candidate hardware.
- Present the search process and the current status.
- Outline the next steps.

- 16 Dec 2003

**Notes:**
What I plan to present today

## Architecture Block Diagram, Data Path

- Anti-alias
- Pre filter

- A2D
- 12/14b

- Down
- Convter
- & Filter

- Addt’l
- Data
- Process’n

- Memory

- Sensor

- 16 Dec 2003

**Notes:**
This is the architecture for BPM data processing that everyone agreed to.
The Additional processing can be FPGA or DSP based.
12 bits A2D are the minimum.  The down converter is what used to be called superhetrodyne back in the analog circuit days. 

## Initial Constraints

- The candidate hardware should be able to implement the chosen data processing architecture.
- We did not want to start from scratch with a new design.
- Therefore, we looked at current examples of BPM DA hardware.
- The BLM will not affect this selection as it will be independent of the BPM raw data path.

- 16 Dec 2003

**Notes:**
No time to go through the entire design process.
We went through many meetings of presentations.
BLM prototype is done and working and there are several ways to use this hardware architecture in the final design.

## Slide 5

- 16 Dec 2003

**Notes:**
Prototype BLM demonstrator sytem

## Initial Hardware Field

- Recycler and NUMI Echotek boards
- MI damper boards
- E-Cool DSR boards
- BNL RHIC BPMs
- Commercially available Analog to Digital Converter and Digital Signal Receiver boards.

- 16 Dec 2003

**Notes:**
The preference for local expertise hurt the BNL hardware although that talk added to everyone's technical knowledge.
What other presentations?
Lots of commercial boards but none was so much better than the Echotek that it overcame the advantage of it being in use locally.  We needed a big incentive to start completely over with a new COTS board.

## Slide 7

| Summary First Candidates |  |  |  |  |  |  |  |  |
| --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Module | Channels and A2D | Data Processor | Form |  | Num | System Use | Stage |  |
| Echotek | 8ch x 80 Msps x 14b | DDC  | VME |  | 120 | Recycler, NUMI | Product |  |
| DSR | 8ch x 65 Msps x 14b | DDC + DSP | VXI |  | 25 | Ecool, MI BPM | Product |  |
| Damper | 4ch x 212 Msps x 12b | FPGA logic +DSP | "NIM" |  | 5 | MI damper, RR | Proto |  |
|  |  |  |  |  |  |  |  |  |
| Module | Individual Issues |  |  |  |  |  |  |  |
| Echotek | Expensive, least flexible data processing, output FIFO limits flexibility. |  |  |  |  |  |  |  |
| DSR | Has some constraints on timing and data processing flexibility. |  |  |  |  |  |  |  |
| Damper | Most capable. Needs most engineering.  I/O is DSP to Ethernet. Only 4 channels. |  |  |  |  |  |  |  |
|  |  |  |  |  |  |  |  |  |
| DSR=Digital Signal Receiver  DDC=Digital Down Converter  DSP=Digital Signal Processor |  |  |  |  |  |  |  |  |

- 16 Dec 2003

**Notes:**
Lots of details to point out 
Include the fact that the timing constraints on the DSR board can be fixed with blue wire or with a quick layout change so that will be the default for this board in the future.
Damper probably capable of doing time separation if timing engineering can be done.

## Added Candidates

- Add modified Echotek with output FIFO replaced by dual-port RAM.
- Echotek2
- Add DSR board with faster DDC with new data buffers and DSP with larger memory.
- DSR2

- 16 Dec 2003

**Notes:**
These changes looked like they would fit in the schedule.  Echotek has given us a quote for the modified board. DSR already includes timing changes.  The DSR designers have given us an estimate on how much additional work is needed there.
Redoing the damper board was the next thing considered and it was noticeably more work with a longer schedule and higher risk.

## Slide 9

| Summary Current Candidates |  |  |  |  |  |  |
| --- | --- | --- | --- | --- | --- | --- |
| Module | Channels and A2D | Data Processor | Form | # | System                                          | State |
| Echotek | 8ch x 80 Msps x 14b | DDC  | VME | 120 | Recycler | Product |
| Echotek2 | 8ch x 80 Msps x 14b | DDC  | VME |  -- |   |   |
| DSR | 8ch x 65 Msps x 14b | DDC + DSP | VXI | 25 | Ecool, MI  | Product |
| DSR2 | 8ch x 65 Msps x 14b | DDC + DSP | VXI |  -- |   |   |
| Damper | 4ch x 212 Msps x 12b | FPGA logic +DSP | "NIM" | 5 | MI damper, RR | Proto |
|   |  |  |  |  |  |  |
| Module | Individual Issues |  |  |  |  |  |
| Echotek | Expensive, least flexible data processing, output FIFO limits flexibility. |  |  |  |  |  |
| Echotek2 | Expensive, most direct data processing. |  |  |  |  |  |
| DSR | Some constraints on timing flexibility. Most under sampled data. |  |  |  |  |  |
| DSR2 | Most under sampled data. |  |  |  |  |  |
| Damper | Most capable. Needs most engineering. I/O is DSP to Ethernet. 4 channels. |  |  |  |  |  |

- 16 Dec 2003

**Notes:**
This slide will only be shown for a short time because it has very little new information.
Need to explain next slide talk about getting to the first working crate and not the complete system.
At this point any of these should work but how much work is needed?  
We made many spreadsheets of data.
Samples of the collected info follows.

## Slide 10

| Module | Hardware Engineering Tasks | Design |  | Drafting |  | Board Fab |  | Board Checkout |  |   |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
|  |  | FTE | Wks | FTE | Wks | FTE | Wks | FTE | Wks |   |
| Echotek | None | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 4 |   |
| Echotek2 | None | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 4 |   |
| DSR Board | Some traces need to be added for triggering and reset.  No major layout changes. | 1 | 1 | 1 | 1 | 1 | 27 | 1 | 4 |   |
| DSR2 Board | Digitizer and DDC changed to 80MHz versions.  FPGA added to handle serial output of DDC, perform preliminary calculations, and interface with DSP. | 1 | 4 | 1 | 12 | 1 | 27 | 1 | 4 |   |
| Damper Board | DAC components used for dampers need to be removed.  External communication circuitry needs to be changed from Ethernet to VME. | 1 | 4 | 1 | 12 | 1 | 27 | 1 | 4 |   |
|   |   |   |   |   |   |   |   |   |   |   |
| Timing, Cal, BLM | Total design of custom cards. | 1 | 8 | 1 | 8 | 1 | 21 | 1 | 4 |   |
|  |  |  |  |  |  |  |  |  |  |  |

- 16 Dec 2003

**Notes:**
Example of spreadsheet used to estimate engineering effort for candidates.

## Slide 11

| Module | On board software/firmware engineering | FPGA Program |  | DSP Program |  |
| --- | --- | --- | --- | --- | --- |
|  |  | FTE | Wks | FTE | Wks |
| Echotek | FPGA may need to handle different triggering schemes | 1 | 3 | 0 | 0 |
| Echotek2 | FPGA needs new program to deal with data processing, memory management, and new backplane communication protocol. | 1 | 7 | 0 | 0 |
| DSR Board | DSP needs new program to deal with new data processing algorithms, different memory management, and different synchronization schemes. | 0 | 0 | 1 | 7 |
| DSR2 Board | New FPGA needs program to deal with data processing and DSP communication.  DSP needs new program to deal with FPGA communication, new data processing algorithms, different memory management, and different synchronization schemes. | 1 | 7 | 1 | 7 |
| Damper Board | FPGA needs to incorporate a digital down converter process with digital filters.  It must perform all data processing calculations and memory management.  It needs to be modified for new communication protocol. | 1 | 10 | 0 | 0 |
|   |   |   |   |   |   |
| Module | Slot zero (front end) software engineering | Slot Zero Program |  |  |  |
|  |  | FTE | Wks |  |   |
| Echotek | Needs robust, fast bus for continuous acquisition from BPM cards.  Needs new program to deal with data processing, memory management, and triggering. | 1 | 10 |  |   |
| Echotek2 | Programming of ACNET parameters and implementation of diagnostics communication.  Also will need to perform data processing that FPGA is unable to perform. | 1 | 4 |  |   |
| DSR Board | Programming of ACNET parameters and implementation of diagnostics communication. | 1 | 4 |  |   |
| DSR2 Board | Programming of ACNET parameters and implementation of diagnostics communication. | 1 | 4 |  |   |
| Damper Board | New hardware.  Requires MOOC interface programming, ACNET parameters, and diagnostics communication. | 1 | 7 |  |   |

- 16 Dec 2003

**Notes:**
Explain software work.
No details discussion

## M&S

| Numbers | # of BPMs | Total # of signals | Spares | Houses | Spare Crates |  |  |
| --- | --- | --- | --- | --- | --- | --- | --- |
|   | 236 | 944 | 142 | 27 | 2 |  |  |
|   |   |   |   |   |  |  |  |
| Numbers | Total channels | Total crates | Board/crate timing, cal, BLM | Board Cost of timing, cal, BLM | Total cost timing, cal, BLM | Note: Est. for front-end analog filter |  |
|   | 1086 | 29 | 1 | $4,000 | $116,000 | $40/chan  |  |
|  |  |  |  |  |  |  |  |
| Module | Cost/card | Chan/card | Total Cards | Cost/crate & slot zero controller | Total crates & slot zeros | Analog Filters | Total M&S |
| Echotek | $7,400 | 8 | $1,004,550 | $9,000 | $261,000 | $43,440 | $1,424,990 |
| Echotek2 | $7,600 | 8 | $1,031,700 | $9,000 | $261,000 | $43,440 | $1,452,140 |
| DSR Board | $1,900 | 8 | $257,925 | $12,600 | $365,400 | $43,440 | $782,765 |
| DSR2 Board | $1,900 | 8 | $257,925 | $12,600 | $365,400 | $43,440 | $782,765 |
| Damper Board | $2,200 | 4 | $597,300 | $9,000 | $261,000 |   | $974,300 |

- 16 Dec 2003

**Notes:**
Explain M&S details.

## More Spreadsheets

- We have several spreadsheets to help us understand the costs and effort involved with each candidate.
- Description, engineering, software and M&S were already shown.
- Summary to First Crate
- Fabrication
- Summary to Full system

- 16 Dec 2003

**Notes:**
We have a quite a few spreadsheets and I gave up trying to display them.
we are not here to go over them but to discuss where they lead us.

## What’s Next

- The Modified Echotek board is the candidate we will focus on and within the following steps we will pick a point to begin production.
- We verify proton/antiproton processing with a representative module.
- We need to understand how we will trigger the boards in all the modes and how we will generate those signals.
- We need to understand calibration.

- 16 Dec 2003

**Notes:**
We have a very good start on data collection but work needs to be done.
We have a start on calibration.  Info to be presented later this week.
Segue to Bob