# Presentation: 571935

## Radiation tolerant pixel FE in the TSMC 0.25 process

- _A. Mekkaoui, J. Hoff_
- _Fermilab, Batavia IL_

## FPIX History

- _1997: FPIX0, a 12X64 HP 0.8u process_
- Two stage front-end, analog output digitized off chip
- A data driven non-triggered RO
- Successfully used in beam tests
- _1998: FPIX1, a 18X160 Hp 0.5u process_
- Two stage front-end, with one 2b FADC/cell.
- Fast triggered/non triggered RO
- successfully used in beam tests
- _1999: preFPIX2_T, 2X160 TSMC 0.25u (to be presented today)_
- Radiation tolerant techniques forced us to design a new front-end with a new leakage compensation strategy.
- _2000: preFPIX2_I,  18X32 0.25u CERN process (In fab)_
- Same as FE cell as in preFPIX2_T but with compelete fast non-triggered RO.

- A. Mekkaoui

## FPIX1 front-end

- Iff

- Mf

- See the proceedings of the 1999 workshop on the electronics for the LHC (Snowmass) and references therein.

- A. Mekkaoui

## Main radtol design constraints

- The feedback structure used _two_ NMOS devices and a biasing PMOS device (as a current source Iff).
- In the previous design: stability, noise and proper shaping relied on having a long (W/L << 1) N-channel device in the feedback (Mf).
- Leakage current tolerance insured by the feedback structure.
- Problems to implement present DSM  radtol design:
- NMOS in 0.25 has higher transconductance than in 0.5 process.
- Minimum enclosed NMOS has W/L around 5. (See the RD49 reports.)
- Enclosed NMOS with its required guard ring occupy large area.

- It’s quasi impossible to implement the present design in the available area.

- A. Mekkaoui

## Feedback solution 

- One NMOS feedback transistor biased by a global voltage VFF.
- VFF generated such as to track (to the 1st order) the preamp DC level shifts due to global changes (process, temperature...)
- Feedback is current controlled as before. This current can be much higher than in the previous scheme.
- It is more reliable to work with higher currents.
- Leakage current compensation assured by a separate scheme (next slide).

- A. Mekkaoui

## Leakage current compensation scheme

- => Compensates only one polarity.
- => The new scheme, though more complexe, occupy a modest area

- Very low bandwith diff. Amp. Ideally:

- Simplistic analysis yields:

- S = Laplace variable

- A. Mekkaoui

## Leakage current compensation scheme

- Inductor

- A. Mekkaoui

## TSMC && the “CERN process”

- After some comparative work we decided to constrain our design to work well whether implemented in the “CERN” or TSMC process.
-  Minor additional layout is required to submit to both processes (mostly through automatic generation)
- TSMC is offered by MOSIS (4 runs/year). 6 runs/yr is planned.
- It is wise to have a 2nd source for production.=> CERN process is the process selected by CERN to implement their deep sub-micron radtol designs.

- A. Mekkaoui

## preFPIX2

- preFPIX2 is the first prototype we designed to investigate our ideas and to test the radiation hardness of the TSMC 0.25 process. It contains 8 pixel front-end cell and several isolated transistor.

- 8 prefpix2 front-end cells

- Test structures

- A. Mekkaoui

## Typical front-end response

- Buffered output of the second stage

- A. Mekkaoui

## Feedback control

- decreasing feedback current (IFF)

- A. Mekkaoui

## Feedback control

- A. Mekkaoui

## Feedback control

- A. Mekkaoui

## Leakage current compensation

- After the first nA no change in the response is observed !

- A. Mekkaoui

## Leakage current compensation II

- A. Mekkaoui

## Response to large signals

- A. Mekkaoui

## Linearity (small signals)

- => Ideal gain = (1/cf)(Cc2/cf2)  = (1/8fF)*4 = 80 V/e-
- => Spice predicted gain = 76 V/e-

- A. Mekkaoui

## Linearity (larger signals)

- A. Mekkaoui

## Threshold control and matching

- A. Mekkaoui

## Threshold control and matching II

- => 25 channels from 5 different boards.

- A. Mekkaoui

## Noise (measured from efficiency curves) 

- A. Mekkaoui

## PreFPIX2_T

- PreFPIX2_T is 2X160 pixel array. Each pixel cell contains all the functions needed for the BTEV experiment: kill and Inject logic, 3bit FADC, hit buffering, fast sparse RO.

- => EOC logic implemented off chip.
- => The analog and digital outputs of the two upper cells
- are available for direct test and characterization.

- A. Mekkaoui

## Top cell buffered outputs

- A. Mekkaoui

## preFPIX2_T front-end

- Same FE as preFPIX2 except that the injection transitor is a PMOS and the injection cap is realized with m1/m2 sandwich (2.6fF) instead of m1/poly (4fF). 2nd stage feedback “resistor” not shown.

- PMOS

- 4Cf2

- Cf2

- +

- -

- -A

- Main discriminator

- Cf

- Rf

- A. Mekkaoui

## preFPIX2_T pixel cell

- 3b FADC

- A. Mekkaoui

## PreFPIX2_T: pulse shapes

- Qin=3260e- channel R. 3 different feedback currents.

- A. Mekkaoui

## Irradiation of the PreFPIX2_T

- We have irradiated several test structures from two 0.25 processes, from TSMC and a domestic vendor.
- Besides the individual devices we have irradiated also the prefPIX2 and preFPIX2_T pixel circuits
- The irradiation took place at the Co60 irradiation facility of the Argonne National Lab.
- A complete report on the results is still under preparation.
- Partial and VERY preliminary results from the test of the preFPIX2_T will be presented today.
- Dosimetry accurate to 20%.
- No filter for low energy particles was used.
- All the results shown are after 1 to 7 days of annealing at room temperature.
- In all subsequent slides rad should read rad(SiO2)

- A. Mekkaoui

## General effects after 33 Mrad

- Chip fully functional
- No degradation in speed (as inferred from the kill/inject shift register operation).
- Less than 10% change in “analog” power. Power was less after irradiation. Understandable from circuit point of view and is due to small VT change in the PMOS (<50 mV).

- A. Mekkaoui

## Total dose effects on front-end

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## Total dose effects on front-end

- A. Mekkaoui

## Total dose effects on front-end

**=> 3 mV DC offset shift (due mainly to output buffer)**
**=> < 4% Rise time difference**
**=> < 5% change in fall time.**

- Before irradiation

- After 33 Mrad

- A. Mekkaoui

## Linearity before and after 33 Mrad

- => 7 % max gain error. Believed to be due to output buffer only.

- A. Mekkaoui

## Rise and fall time before and after 33 Mrad 

- => Changes are minimal and may disappear after annealing.

- A. Mekkaoui

## Noise and threshold distributions

- => Practically no change in noise and threshold dispersion.
- => 200 e- change in the threshold voltage.

- A. Mekkaoui

## Effects at higher threshold

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## Readout typical output

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## Readout Max speed

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## Conclusions

- We successfully migrated our design from 0.5 process to 0.25 using radiation tolerant techniques.
- The design can be submitted to two different vendors.
- Chip performed as expected before and after 33 Mrad.
- We are still working on the radiation results.
- DSM is the way to go for radiation hardness (if you can).

- A. Mekkaoui

## Acknowledgements

- William Wester co-organizer of the irradiation “week”.
- Tory Steed and Al. Al Svirmickas  from ANL for their precious help.
- Al Deyer and Kelly Knickerbocker for preparing the boards and the 100’s of feet of cable.
- Ray Yarema for his advice and encouragements.

- A. Mekkaoui