# Presentation: 185411

## The Fiber Road Card

- G. Steinbrück		Columbia U.
- STT Meeting
- 05/27/2000
-  SCL Init
- Monitoring and L3 Requests
- VME Interrupt vs Dedicated line
- Connector Test
- Track Truncation Study

- G. Steinbrück       STT meeting

- 5/27/00

## SCL Init at SCLF

- INIT_SECTION asserted on input
- Disable latching SCL data to SCLF
- Set INIT_ACK to SCL mezzanine
- Wait for SCAN_BUSY to clear
- Send SCL_INIT signal to CPU (on dedicated line or via VME interrupt)
- Wait for INIT_DONE from CPU (VME Register in SCLF)
- Enable latching SCL data to SCLF
- Clear L1_ERROR and L2_ERROR in SCLCR
- Clear INIT_ACK to SCL mezzanine

- G. Steinbrück       STT meeting

- 5/27/00

## SCL INIT Request to CPU

- SCAN_BUSY

- SCL_INIT

- SCL_INT

- G. Steinbrück       STT meeting

- 5/27/00

## SCL Init at CPU

- Write SCL_READY[i] signal bits to each VME memory register (BC, DB, MB)
- Receive SCL_DONE[i] from each elements (poll)
- Acknowledge by clearing SCL_READY[i] signal bit in all BC and DB VME memory registers
- Wait for all units to Receive SCL_INIT  from SCLF/FRC
- acknowledge (Units clear SCL_DONE[i])
- Send INIT_DONE to SCLF

- G. Steinbrück       STT meeting

- 5/27/00

## SCL Init at Component

- Each Component receives SCL_READY[i] from CPU
- Input elements (RR) clear data
- Disable latching input data
- Wait n clock cycles w/o valid data
- Enable latching input data
- Processing elements (SCLF, TRDF) reset inputs
- Reset Input FIFOs

- G. Steinbrück       STT meeting

- 5/27/00

## SCL Init at Component Cont.

- Buffer Manager reset inputs
- Reset Input FIFOs
- Mark all buffers as unused
-  Reset all Control/Status/Monitoring registers (except SCL_INIT registers)
- Each Component sets SCL_DONE[i]
- Wait for CPU to Clear SCL_READY[i]
- Clear SCL_DONE[i]

- G. Steinbrück       STT meeting

- 5/27/00

## SCL init handshaking

- SCL handshaking between CPU and components.

| Action | SCL_DONE[i] | SCL_READY[i] |
| --- | --- | --- |
| SCL_READY | 0 | 0 |
| CPU: SCL_INIT | 0 | 1 |
| Component inits | 0 | 1 |
| Component done | 1 | 1 |
| CPU ACK | 1 | 0 |
| Component CLEARS DONE | 0 | 0 |
| Ready | 0 | 0 |

- G. Steinbrück       STT meeting

- 5/27/00

## SCL init handshaking

- SCL handshaking between CPU and components.

- SCL_DONE

- SCL_READY

- CPU: Init

- Comp: DONE

- CPU: Ack

- Comp: Clear DONE

- G. Steinbrück       STT meeting

- 5/27/00

## Questions

- Since all reset requests are sent in parallel now, what about elements where the order matters: (i.e. road receivers before formatters)
- Solutions:
- The CPU could enforce the order by only sending the init request to a unit  after it gets the INIT_DONE from the previous one.
- The daughter boards handle the sequence by communicating with each other (not great)

- G. Steinbrück       STT meeting

- 5/27/00

## Questions

- What to send out to L3 upon SCL_INIT
- Kill everything, send nothing
- Finish current event, but dump everything afterwards
- Keep all events before the one with the SCL init
-  In b and c, SCLF has to know the state of the system

- Possible: State known via VBD_BUSY from BM
- SCLF only sends SCL_INIT request to CPU if VBD is done
- Or CPU could know about state of VBD (not so good).

- G. Steinbrück       STT meeting

- 5/27/00

## Questions

- What kind of monitoring data should be send after SCL init?

- Jim: The event the SCL init corresponds to and all up to 15 previous ones in the buffers can be thrown away: a) is fine.

- Jim: Don't need to send any, just start over.

- VME interrupt versus dedicated line. What if an SCL init request comes while VME is busy (i.e. VBD uses it for several hundred ****s or even ms?

- Wait until VBD releases VME
- Since nothing needs to be monitored /saved, the SCL init could come as a VME interrupt (highest priority) at any time the bus is released

- G. Steinbrück       STT meeting

- 5/27/00

## Monitoring and L3 Requests to CPU

- SCAN_BUSY

- Collect_Status

- READOUT_BSY
- (data in buffer)

- MON_INT

- MON_BUSY

- L2_ACCEPT

- SCAN_RDY

- L3_INT

- G. Steinbrück       STT meeting

- 5/27/00

## Monitoring Requests at the FRC

- Receive Collect_Status
- Wait for all data in Buffer (poll READOUT_BUSY*)
- Wait for VBD to released VME (poll SCAN_BUSY*)
- Send Monitoring request to CPU (MON_INIT)
- Wait for MON_DONE from CPU

- G. Steinbrück       STT meeting

- 5/27/00

## L3 Requests at the FRC

- Receive L2_Accept
- Wait for all data in Out FIFO (poll SCAN_READY)
- Wait for Monitoring to be done (poll MON_BUSY*)
- Send L3 request to CPU (L3_INIT)
- Wait for L3_DONE from CPU

- G. Steinbrück       STT meeting

- 5/27/00

## Connector Test

- An Qi laid out test board including holes for stand-off
- Connection can be tested using only two pins per connector
- Received quote from a company

- G. Steinbrück       STT meeting

- 5/27/00

## Truncation Study

- Use mc_exam:
- Includes info for

- Cal (Calorimeter digi), CFT, CPS, FPS, MET,
- Jets, Kine (generated event), Muon, SMT,
- Reco Track, Vergen (Vertex)

- Tested, Runs on 1.1 av Min Bias events, but crashes on fixed N(Min Bias)???
- Use Root ntuples
- Writing macro to do truncation and implement triggers
- Summer student June 5, stay tuned!

- G. Steinbrück       STT meeting

- 5/27/00

## What Next

- Finish Truncation Study by the end of summer
- Understand VRB/VRBC protocol and determine if we can adopt it for BM/BC communication
- Understand all buffering stages: FIFO depths, timing requirements

- G. Steinbrück       STT meeting

- 5/27/00