# Presentation: 061913

## Silicon Pixel FEM R&D

** ****Basic concept of pixel FEM**
** ****NA60 readout scheme**
** ****Schematic readout scheme for PHENIX**
** ****R&D Program**

_**Three Students working with me over the summer:**_
**Sanjee Abeytunge****	****	****MSI Thesis Fall 2003**
**Alan Dion****	****	****FEM readout tests at BNL**
**Dylan Walker****	****	****at CERN with NA60**

## Silicon Pixel FEM

**Basic assumption: Pixel readout will be similar to ALICE & NA60 readout**
**Pilot chip**
**GOL for optical transmission (Glink or cupper)**
**JTAG slow control**
**Function of pixel FEM**
**Multiplex multiple pilot/GOL chips or ladders**
**Adapt output from pixel ladder to “PHENIX” readout **
**Readout prototype pixel chips into PHENIX DAQ with existing DCM’s **
**Option to use existing PHENIX DCM’s (e.g. from MVD)****  **
**Other features**
**Optional zero suppression **
**Scheme expandable to other detector systems (silicon strips or HBD ..)**
**Central control board CCB**
**Slow control ArcNet (or what ever replaces it) to JTAG conversion**
**Clock distribution **
**Trigger distribution**

- Axel Drees

## Present Readout Scheme

**Silicon Pixel Ladders**

**FPGA**

**F**
**I**
**F**
**O**

**Glink**

**DCM**

**FPGA**

**F**
**I**
**F**
**O**

**Multiple Pilot/GOL per ladder**

**Piggy back receiver**

**JTAG, clock**

**clock, trigger**

- Axel Drees

## R&D towards FEM (update from DAQ Meeting 10/2002)

**Create programmable data source (NI 5311) **
**Hardware & Labview software available  (S.Abeytunge)**
**First readout tests  ****(planed for this summer A.Dion)**
**Simulate pixel data  **
**read through DC FEM **
**(in principle available thanks to L.Hammons)**
**develop test software**
**implement zero suppression algorithm**
**Develop FEM prototpye **
** ****(Master Thesis S.Abeytunge Fall 2003)**
**Data collector and Glink data transmission **
**Adaptable to data source and real pixel chip**
**Central Control Board prototype **
**(similar board developed for NA60 strip readout **
**by S. Abeytunge, reusable?)**
**trigger, clock**
**JTAG **
**FEM Test readout **
**two data sources **

**Obtain “real” data source**
**	****(D.Walker at CERN over summer)**
**ALICE single chip board**
**NA60 multichip interface**
**Develop control of pixel chip **
**(Fall 2003)**
**ArcNet JTAG translation**
**slow control software **
**HV and LV **
**Test readout with DC FEM **
**Readout test with FEM prototype **

- Axel Drees

## Programmable Data Source

**Programmable Data Source**

**Based on National Instrument  40 MHz arbitrary waveform generator  NI5411**
**	****system available**
**based on PXI bus **
**2x16 bit digital (TTL) pattern (two units synchronized)**
**40 MHz output (internal and external clock)**
**16 Mbyte memory**
**Multiple data segments **
**	****released sequentially on **
**	****internal or external trigger**
**Labview control program available**

**Software developed and tested **
**by S Abeytunge**

- Axel Drees

## Old slides

- Axel Drees

## NA60 pixel read out

**NA60 pixel read out**

**Pixel plane**

**Multichip interface**

**PCI card & Mezzanine**

**4 pixel chips**

**Control bus**

**Data bus**

**Low voltage “analog pilot” not shown**

**GOL**

**Pilot**

**32 bit**
**10 MHz**

**16 bit**
**20 MHz ?**

**Glink (twisted pair)**
**data, busy, control words**

**burst**
**buffer**

**FPGA**

**Glink **
**receiver**

**trigger**

**Corresponds to PHENIX Pixel ladder**
**hope to receive test chain this year: **
**1 chip test board + interface**

**PHENIX FEM**
**collects data from multiple pilot chips**
**could do zero suppression**

**PHENIX **
**DCM**

**JTAG**
**clock,trigger,slow control**

**Glink**
**JTAG**
**connection**

**burst**

**FPGA**

**40 MHz**
**clock**

**busy**

**Zero suppression: **
**	****replace 0 words by counter**
**Generate busy: **
**	****count evt received & triggers send **

- Axel Drees

## Schematic layout of FEM 

**2 kByte data from each pilot**
**~32000 16 bit words **
**multiple pilots deliver data to one FEM**
**one side ****	****max. 20 pilot chips  ****	**
**assume 4 pilots (one ladder) per FEM**
**5 FEM per side, 20 in total**
**Zero suppression on FEM (optional)**
**light suppression **
**marker arm/side/pilot/chip**
**replace empty 16 bit words by word counter**
**max length ~ raw data length **
**full suppression**
**marker arm/side/pilot/chip**
**only hit pixel rphi (8 bit), z (5 bit)**
**Busy generated by FEM and transmitted to DCM**
**transmit with data ala pilot chip? **

**GLink**

**GTM:**
**Trigger**
**clock**

**data collector**

**controller for **
**1 pilot**

**FPGA**

**GLink**

**FPGA**

**Arcnet**

**Slow**
**control**

**JTAG**

- Axel Drees

## (Universal Silicon) FEM readout scheme

**8 kByte data stream from each pilot:**
**via cable or optical fiber**
**no zero suppression**
**5 pilot chips deliver data to one FEM**
**2 (6) FEM’s per arm**
**1 (3) for each side**
**FEM’s suppress zero’s and reformat data **
**marker word****	****1 bit arm**
**	****	****(16 bit)****	****	****1 bit side**
**	****	****	****	****2 bit FEM**
**	****	****	****	****3 bit pilot**
**	****	****	****	****3 bit chip**
**data word****	****	****8 bit for word (r********)**
**	****	****(16 bit)****	****	****5 bit for channel (z)**
**data volume per FEM (for central collision)**
**uncompressed****	****40  kByte****	**
**16 bit per word****	****~3.3  kByte**
**40 marker words (one/chip)****	**
**3300 data words (1% occupancy)****	****	**

**data**
**bus**

- Transmitter
- GLink

**to DCM**

**FEM**

- Axel Drees