# Presentation: 112820

## Custom IC Development for SNAP

**Jean-Pierre Walder**
**Lawrence Berkeley National Laboratory**
**July 2002 **

## Outline

-  **Introduction**
**Custom ICs R&D goals**
**Front end readout block diagram**
**SNAP IC plan**
**Front end readout requirements**
**Signal processing**
**Front end dynamic range and resolution**
**Multi slope ADC concept**
**ADC architecture study**
**Technology survey**
**Behavior of sub micron CMOS at cold temperature**
**Radiation tolerance**
**Conclusion**

## Introduction

**SNAP instrument consists of CCDs and HgCdTe sensors for wide-field imaging and spectroscopy**** ******** We have identified areas where custom integrated circuits are a viable solution to meet SNAP’s requirements**
**Custom ICs allow power, noise optimization compared to a discrete solution. **
**  ******** ****We envision a readout scheme that focuses on CCD devices, keeping in mind the characteristics of the HgCdTe in case Rockwell is not sucessful.**
**R&D are required to mitigate technical & schedule risk:**
**Sensor front-end (correlated double sampler)**
**Analog-to-digital converter**
**CCD controller (maybe commercial parts or custom)**

## Custom ICs R&D Goals

**The R&D goals are to provide thorough and complete  answers in the following areas:**
**Readout noise*****noise optimization and signal processing study***
**Power optimization*****In general, low power is required for space, and very low power is mandatory if we want to locate the front end electronics close to the CCDs. Its power consumption should be a small fraction of the CCD power.***
**Operation at cold temperature*****Evaluate current technology performances at cold temperature (140K) and verify/modify the model for a reliable design.***
**Radiation hardness**** **** *****Evaluate current technology performances in radiation environment especially at low temperature***
**Prototype*****Design and test a reliable prototype before construction***
**   **

## Front end readout block diagram

- CCD

- Amplification

- Analog signal
- processing

- ADC

*Front end IC*

- Digital out

- Analog
-  input

- Clocks, control

- Mixed mode front end custom IC
- Multi channel chip

- (One channel)

## SNAP IC plan

-  **This is to verify:**
-  Noise performance
-  Power consumption
-  Multi slope concept
-  Operation at 140K and 300K
-  Radiation tolerance

-  Implementation of a signal processing test chip containing:
- 4 channels
- Input amplifier
- Correlated double sampling
- Integrator
- Multi gain amplifier (multi slope)
- Individual test structures
- Test transistors

- A second iteration implementing an integrated ADC with a low noise front end is planned.

-  **This is to verify:**
-  Noise performance
-  Power consumption
-  Resolution/linearity
-  Sampling rate
-  Electronic system noise

## Front end readout requirements

**Low noise:****Photometry: CCD + electronic noise ******** 4e rms****                      HgCdTe + electronic noise ******** 5e rms****Spectrograph: CCD + electronic noise ******** 2e rms****                      HgCdTe + electronic noise ******** 5e rms**
**Large dynamic range:****96dB from noise floor to 130ke well depth**
**Readout frequency:**** ******** 100 kHz**
**Radiation tolerant ****10 kRad ionization (well shielded)**
**Low power**** ******** 200mJ/image/channel**
**Operation at 140K and 300K****Allow normal operation at 140K and chip testing at room temperature **
**Compact**
**Robust, space qualified**

## Signal processing (1/4)

**Reset FET**

**Source**
**follower**

**Floating**
**diffusion**
**capacitor**

**Serial**
**register**

*Timing:*

- Reset signal

- Video signal

- RG (reset)

- SW

***Output stage***

**(Summing**
**Well)**

- Output
-  signal

- CCD output stage

## Signal processing (2/4)

- Thermal and 1/f noise of the output transistor

- Thermal noise of the output resistor

- Frozen noise charge, with a variance of KTC, stored in C**fd** just after reset.

- Signal processing is needed to reduce the CCD noise:

- Correlated double sampling ( Vsignal –Vreset): remove the KTC and 1/f noise.
- Integration: remove the thermal noise.

- CCD noise sources

**Thermal and 1/f noise**

**Thermal noise**

**KTC noise**

## Signal processing (3/4)

**X1**

**-X1**

- C (100pF)

- R

- (Noiseless)

- 

- 

- Out

- CCDnoisesource

- CCD conversion gain: 3.5V/e

***CCD noise only***

**Integration time ******

**Input referred noise (e) **

- 4s (R=20K

- 8s (R=40K

- 10s (R=50K)

- 2.6

- 1.86

- 1.8

- 

- 

*Correlated Double Sampler*

*Integrator*

- time

- Out

- Real integration during 2. Good rejection of the CCD thermal noise.

- Reset
-  integration

- Signal
-  integration

## Signal processing (4/4)

**X1**

**-X1**

- C (100pF)

- R

- (Noiseless)

- 

- 

- Out

- CCDnoisesource

- CCD conversion gain: 3.5V/e

***CCD noise + first stage noise***

**Integration time ******

**Input referred noise (e)****technology A / B **

- 4s (R=20K

- 8s (R=40K

- 10s (R=50K)

-  2.8 / 2.9

-  2.1 / 2.2

-  1.92 / 2

- The 1/f noise of the input stage is reduced by the CDS
- The thermal noise from the input stage is negligible compared to the CCD thermal noise

- 

- 

- time

- Out

- Reset
-  integration

- Signal
-  integration

## Front end dynamic range and resolution

- The dynamic range for the  signal is 96dB (16 bits)
- From 2 electrons  (CCD noise) up to 130000 electrons
- The Signal/Noise ratio of the sensor/readout chain is less due to the Poisson process of the light interacting in the sensor.
-    dN/N = 1/ (N)1⁄2 where N is the number of photons.
- The readout chain should digitize the signal with an LSB size which depends of the signal amplitude such that the quantization noise is still below the Poisson noise.

- CCD + electronic noise

- Poisson

- Quantization noise area

## Multi slope ADC concept

**Gain 1**

**Gain 2**

**Gain 32**

**MUX**

**12 bits ADC**

- Input

- Digital out

- The dynamic range is covered using 3 slopes and a 12 bit ADC

**Signal **
**processing**

- Poisson
- + elec noise

- 1⁄2 of (Poisson **** elec noise)

- Gain 32
- quantization noise
- referred  to the input

- Gain 2

- Gain 1

## ADC architecture study

- Several architecture were investigated.
- In the range of the required resolution (12 bits) and sampling rate (<100kHz), we have identified two types:
-  Pipeline ADC
-  Single ramp ADC

- S/H

- ADC

- DAC

- +

- -

**X2**

- Digital out (1 bit)

- Input

- ......X nb of bits

**Pipeline ADC**
**(1 bit cell)**

- Ramp

**cmp**

- Counter

- Digital

- Digital out

- Input

**Single ramp ADC**

- Sampling rate = Clock frequency
- Number of stages = number of bits

- Sampling rate << Clock frequency
- Number of stage = 1
- Multi channel: one ramp generator could supply m comparators.

- X m

## Technology survey

-  10 commercial CMOS sub micron processes where investigated.
-  Selection criteria:
- Noise
- Matching, precision
- Transistor performances
- Passive components availability and precision
- Expected production life time
- Radiation tolerance
- Two deep sub micron CMOS technologies were selected:
- Primary technology: **TSMC** 0.25 m (LBNL)
- Backup technology: **UMC** 0.18 m (France)

***Technologies studied for noise and power performance***

**Minimum feature size:**

## Behavior of sub micron CMOS at cold temperature

- One option is to locate the front end readout IC close to the CCD.
- But, the operating temperature then will be 140K.
*Does deep submicron technology work at 140K?*

- Several studies of sub micron CMOS operating at temperatures ranging from 77K to 300K have been done and are reported in the literature (IEEE transactions on electron devices).

-  Increase of mobility, (100K)/(300K) = 4 to 6	 ~ T, ~ 1.5

-  Increase of gm:
- 	gm(100K)/gm(300K) ~ (.I)1⁄2  *(usually 2 to 3)*
- With,  = (100K)/(300K)          I = Id(100K)/Id(300K)

-  Increase of threshold voltage Vth:	dVth/dT ~ -1mV/K

##  Measurement at the lab of a TSMC 0.25m CMOS testchip

- Measurement set up...

## Measurement of TSMC CMOS at cold temperature

- DC characteristic measurement of TSMC MOS transistors:
-  Both N Mos and P Mos.
- 	Nmos: W=17.5m L=0.39m Enclosed gate.
- 	Pmos: W=40m L=0.39m Enclosed gate.
-  Performed on transistors using a LBNL TSMC test chip.
-  Measurement of Id-Vd and Id-Vg for T = 300K, 250K, 200K	150K, 100K and 77K. (Temp sensor attached to the 	package)
-  Extraction of Vth and mobility ratio versus Temp.
-  Comparison with simulation using the HSpice TSMC 	models.

## Threshold voltage PMOS

- Slope: ~ -1mV/K

## Mobility ratio NMOS

- Spice parameter UTE = -1.3

- Minimum size transistor

## Mobility ratio PMOS

**Mobility ratio PMOS**

- Spice parameter UTE = -0.7

## Radiation tolerance

**Irradiation of deep sub micron test transistors were performed at the lab.**

- No significant change of threshold voltage was observed (<50mV)
- Enclosed geometry prevents leakage at high dose (10 Mrad)
- Standard geometry could be used for dose <100kRad

- Standard geometry

- Enclosed geometry

- Dashed line: Id versus Vgs before irradiation
- Solid line: Id versus Vgs after irradiation (10MRad)

***Standard geometry:***

***Enclosed geometry:***

## Conclusion

-  **The R&D has to provide thorough and complete  answers on identified areas. ****(power, noise, cold temperature, radiation)**
**The technology and signal processing needed to achieve the SNAP requirements have been selected.**
**The multi slope concept has been chosen to limit the ADC resolution.**
**A test chip design, implementing the signal processing building blocks has started.**
**The ADC architecture study is planned.**
** ****Deep sub micron CMOS works at low temperature and the behavior is predictable by Spice simulation.**
** ****Good radiation tolerance of deep sub micron processes have been observed.**