# Presentation: 860139

## CDF Run IIB Silicon Upgrade

- Director’s Review
- Aug.12-16, 2002
- Brenna Flaugher
- Run IIB Silicon Project Co-leader
- Fermilab
- For the CDF Collaboration

## Run IIb Silicon Technical Design

- Cost
- Silicon Project Costs
- Basis of estimate
- Schedule
- reportable milestones and contingency
- critical path
- Labor Profiles
- Risk Analysis
- Conclusions

## Silicon Project Costs

- Costs are in Then year $ and include overhead

- Total   (M$)      1.7           7.0            8.3            1.1            -          18.1

- Grand
- Total

## Silicon Project Costs

- Costs in FY02 $ without overhead

- Costs in Then year $ including overhead

## Silicon M&S Cost breakdown

- Costs are in Then year $ and include overhead

## M&S Cost Breakdown

- Costs in FY02 $ without overhead:

- Costs in Then Year $ including overhead:

## Silicon Labor Cost Breakdown

- Costs are in Then year $ and include overhead

## Silicon Labor Cost Breakdown

- Costs in FY02 $ without overhead

- Costs in Then year $ including overhead

## Cost: Basis of Estimate

- Costs (M&S and Labor) were derived in consultation with Run IIa project mechanical and electrical engineers
- BOE notebooks: quotations, drawings and the Run IIa schedule which were all used to estimate the costs.
- In general: 50% contingency on M&S and Labor Costs
- Specific deviations:
- Cost based on quotations: 30% contingency
- sensors
- power supplies
- A few high uncertainty items: 100% contingency
- SVX4 chip layout cost estimates
- L0 analogue cable production

## Schedule and Milestones

- The Base Schedule – No Contingency
- The schedule is constructed based on how long we think it will take to perform the tasks.
- has ~150 low level milestones scattered over the project
- End date is 4/21/05
- used to aggressively manage the project.
- Level 2 Milestones (includes contingency)
- Subset of low level milestones but dates include contingency
- 17 Level 2 milestones, ~1/quarter
- Reported to Directorate and DOE project manager
-  End date with contingency is 12/22/05
- Use of the contingency will be managed within the project, Fermilab and DOE project manager via change orders (similar to money contingency)

## Contingency and Milestones

## Schedule Contingency and Milestones

- Contingency on Level 2 milestones was set by silicon project managers based on the risk of those tasks
- Total contingency on L2 ends up at 34 weeks, ~ 25% of total project length.
- Level 1 Milestones (highest level)
- Subset of Level 2 milestones but includes an additional 47 weeks (~34%) of contingency
- We report on these to DOE headquarters

## Schedule: Critical Path

- Critical Path Level 3 Milestones
- (*Level 3 = Level 2 without the contingency)

- Schedule is driven by production and testing of outer layer
- stave components: Hybrids, Bus Cable, Mini-Portcard

## Status

- We have prototype parts and are just starting to build prototype modules and staves  - On track for 1st prototype stave milestone 10/15/02

## Stave Components

##  Critical Path Summary Schedule

- Each Round has all stave components: hybrids, bus cables, MPC
- Total base project length 137 weeks (686 days)
- Contingency on base schedule  for L2 milestones = 34 weeks (25%)
- Additional contingency for Level 1 = 47 weeks  (total of 59%)

## Critical Path Details: Stave Prototype Rounds 1 and 2

## Critical Path Details: preproduction and production

## Critical Path Details: Final assembly

- Similar
- to Run IIa

- 2m
- lag

## Final Assembly: Comparison to IIa

- Many Run IIb installation and final assembly tasks are similar to Run IIa
- Installation
- Run IIa average rate was 12 ladders installed and tested/week (peak was 18 ladders in one week)
- Run IIb schedule allows for 10 staves/week (2/day)
- Installation was (and will be) paced by ladder (stave) availability and testing time.
- Memorable dates in Run IIa final assembly
- Nov. 27th L00 (and beam-pipe) installed in SVX
- Dec. 17th Ready to install in ISL  (~3 weeks)
- Run IIb schedule has 5 weeks

## Labor

- Schedule includes time to perform each task
- To convert to FTE we apply an efficiency factor of 0.7
- 1456 hours of productive work per person per year (364 hr/qtr)

- Labor totals for Technical personnel
- and Physicists
- in base schedule
- Note that contingency Labor is not included in the plot

## Run IIb Silicon Institutions 

- 20 institutions have expressed interest thus far
- Negotiations with additional institutions are in progress

## Engineering and associated support

- #1

- #2

- Prepro

- Production

- Final A.

- Labor Cont.
- not included

## Sidet Technical Staff

- #1

- #2

- Prepro

- Production

- Final A.

- Cont. not
- included

## Technical Labor Total

- Cont. not
- included

## Risk Assessment: Silicon Project

| Evaluating Impact of a Risk on Major Project Objectives |  |  |  |  |  |
| --- | --- | --- | --- | --- | --- |
| Project Objective | Very low
0.05 | Low
0.1 | Moderate
0.2 | High
0.4 | Very high
0.8 |
| Cost |  | $100K - $200K increase | $200K-$500K increase | $500K - $1M increase | > $1M increase |
| Schedule |  | slippage 1 - 2 months | slippage 2-4 months | slippage 4-8 months | slippage > 8 months |
| Technical |  |  | technical performance affected but still acceptable | degradation of technical performance unacceptable for physics objectives |  |

- Based on Risk assessment table in the project management plan (Ref. Text: A guide to the Project Management Body of Knowledge  PMBOK Guide 2000 Ed.)
- Scope impact factors not estimated:  assume scope reductions would only be imposed as mitigation for catastrophic overruns of cost or schedule
- Two categories for technical impact

## Risk Assessment

- Risk analysis performed by Project manager for CDF Run IIa Silicon project (Jeff Spalding)
- ~ independent review of cost and schedule risk
- Risk assessment document lists risks associated with Level 4 summary tasks, with more detailed analysis for critical tasks

## Mitigation of Risks in Base Schedule

- Cost risk mitigated by attaching contingency to each task
- Total cost contingency ~50%  (M&S + Labor)
- Schedule risk mitigated by including  contingency lag time on major milestones.  This contingency time will be managed with change orders similar to cost contingency.
- Total Schedule contingency = 34 weeks at Level 2 (~25%)
- Technical Risk mitigated by:
- extensive testing time
- 2 prototype rounds for all stave components
- preproduction submission
- production submission

## Risk Assessment: Schedule Conclusions

| 
Milestone | Est Sched Impact (wks) | Est Sched Risk | Cumulative contingency needed (wks) | Milestone Lag  (wks) |
| --- | --- | --- | --- | --- |
| Production chip Submission - Reporting | 8-16 | 0.4 | 12 | 8 |
| Go ahead for DAQ Production | 8-16
8-16
4-8 | 0.1
0.4
0.2 | 24 | 12 |
| Production Staves Available | 4-8 | 0.2 | 30 | 20 |
| Stave installation complete | 4-8 | 0.4 | 34 | 28 |
| Outer Detector Complete | 4-8
4-8 | 0.2
0.2 | 38 | 32 |
| SVX2b Ready for Installation into ISL |  |  | 38 | 34 |

- Total contingency estimates are in good agreement

- Different choice
- for distribution
- of contingency
- within the project

- Contingency is
- distributed based on
- L2 PM risk assessment
- External Risk A.
- suggests putting more
- contingency
- earlier in project.

## Risk Assessment Conclusions: Cost and Technical

- Cost risk adequately covered by allocated contingency
- Technical risk: moderate
- Main areas of concern
- chip noise performance
- DAQ bandwidth
- mechanical alignment of final detector
- Risk mitigated by extensive prototyping and testing
- Unlikely that performance degradation would be severe enough to seriously impact physics capabilities

## Conclusions

- We have presented our resource loaded schedule
- Critical path is dominated by production and testing of outer layer staves

- Risk Assessment analysis found:
- Cost Risk adequately covered by contingency
- Technical Risk covered by multiple prototype rounds
- Schedule Risk covered by contingency on Level 1 and 2 milestones

- Total Silicon Project Costs

- Costs are in Then year $ and include overhead