# Presentation: 403520

## FPLD Decoder:  Components & Functions

**Florida State University**
**Roberto A Brown**
**6/11/99**

## Goals of the Project

- Design a device that will be able to identify, all the different characteristics of the input stream.
- The device should be able to handle great deals of information at a rapid rate.
- It should be able to store all the information required for later use.

## Approach 

- The main step was to determine, how we were going to separate/deal with the input stream
- Since we needed to identify about 5 different things form the input stream, it was decided to break the model into at least 5 different devices or sub-modules.
- Each sub-module will have a specific function within the total context of the decoder.
- There will be an enabler or selecting unit that will be responsible for activating each one of the units.

## Slide 4

## FIFO

- Main component of the decoder.
- Used to match the frequency of the FPGA and the unit that is sending the information.
- Ensures that the input information is complete before sending it to other decoder components.

## Counter & End of Event Check 

- The counter is triggered as soon as an input is detected.
- It is used to activate the different components of the decoder, at different stages.
- The EOE (end of event) is recognized by the counter device, which in turn gets reset.
- EOE is when the two MSB (most significant bits) of the input stream, are 1.

## SELECTOR DEVICE

- Unit responsible for activating the different identification devices.
- At a particular counter value,  an enable output goes high, which in turn activates one of the “ID” devices.
- For example:
-  When the counter value is equal to one that will activate the sequencer id device.
- When it is equal to to two it will then activate the HDI device, and so on.

## Sequencer Identification device

- Stores the first group of information (8 bits)  that comes in.
- It is activated by an enable output coming from the selector device.
- Once it has store the information, the enable goes back “low”, and nothing else will be stored until it receives another signal from the selector.

## HDI Identification Device

- This device is activated when the counter has a value of two and it’s enable goes high.
- Same as sequencer Id, once information is stored the enable goes back low, and nothing else can be stored.

## Chip Identification Device

- This device becomes partially activated after the counter value is greater or equal to three.
- The device becomes active when the selector detects that the 2 MSB of the input stream are “1” and “0”.
- The remaining six bits of the input stream are stored as the chip number.
- Then the chip device needs to ensure that the following input stream is all zeros.
- If the following stream is not all zeros then, an error has occurred, and we need to abort the all functions.

## Channel Address and Content Device

- This device is also partially activated when the counter value is greater or equal to three.
- The device becomes active when the selector detects that the 2 MSB of the input stream are “0” and “0”.
- The remaining six bits of the input stream are stored as the channel address.
- The following input stream is stored as the channel content.

## Problems to be Solved

- How to store the information for an ongoing line of inputs
- If the impact of the particles hits various strips, that are linked to different FPGA’s
- How will we compute the centroid
- How much ram will be needed to store all the information
- How the information stored, is going to be access to calculate the centroids