# Presentation: 112823

## Process Monitor/TID Characterization

- Valencia M. Joyner

## OUTLINE

- Current MOSIS Process Monitor
- Process Monitor Coupon Objectives
- Review of Impact Ionization and TID Correlation Techniques
- IBM 130nm Coupon Chip
- Expected Results
- Proposed Migration to 90nm
- Proposed Task on 130nm Library Distribution
- Schedule Status

## Current MOSIS Process Monitor Overview

- IBM 8RF Wafer

- BSIM Array

- Sheet Res.

- Ring Oscillator

-   Capacitor Array
-   Test Inverters
-   Contact Kelvin Bridge
-   Metal Step Coverage
-   RO Functional Tests

- MOSIS PM consists of an array of DC and AC parametric test structures and functional test devices for monitoring fabrication of wafers by foundries

## Process Monitor Coupon Objectives (1/3)

- Enclosed Layout Transistor (ELT) Device Characterization
- To simulate and design an IC using RHBD geometries such as ELTs, the characteristics of this device must be well defined
- Coupon includes an array of 24 ELT devices similar to the standard 2-edge transistor array used for BSIM parameter extraction
- Characterization will enhance the understanding of:
- The direction of current flow through the device
- How device parameters (, VT, , 1/f noise params, etc.) compare to the standard two-edge device
- An accurate model for the aspect ratio of the device
- How does drain/source placement affect parameters

## Process Monitor Coupon Objectives (2/3)

- Characterize the TID Radiation Induced Charge Build-up in the Process Oxide Layers (Gate and Field)
- Gate Oxide Structures:  Coupon includes standard two-edge PMOS and NMOS devices for measurement of TID induced parametric shifts
- Field Oxide (FOX) Test Structures are included to characterize the isolation oxide
- TID induced leakage paths in the isolation field oxide between neighboring devices can cause severe signal degradation
- Highly process dependent

- N+

- N-well

- VSS

- N+

- VDD

- +

- +

- VG

- +

- +

- +

- +

## Process Monitor Coupon Objectives (3/3)

- Investigate rapid, low-cost methods of tracking the TID radiation tolerance of the process
- The Field Impact Ionization Technique:  Used in the past, but is it useful for current deep-submicron technologies?
- Experiment:
-   High voltage pulses are applied across the device, injecting electrons from the substrate into the oxide via Fowler-Nordheim tunneling.
-   Injected electrons produce electron-hole pairs in the oxide through impact ionization.  These e-h pairs behave similarly to e-h pairs generated by TID radiation.
- Previous reports of correlation between pre-rad 1/f noise and post-rad oxide-trapped charge are promising

## Ionizing Radiation Review

**Area density of holes created by ionizing radiation**

## Field Induced Injection and Impact Ionization (F4I) Technique

- F-N Tunneling

**Fowler-Nordheim **
**Electron Current Density**

**Area density of holes created by **
**impact ionization**

## TID Radiation and F-N Impact Ionization Correlation

**Equivalent Dose delivered by F4I Technique**

- This technique will attempt to show that damaged introduced by electrical stress does indeed “track” the damage produced by Co60 radiation.

## Previous Results on TID and Electrical Stress Correlation

**Co60 Test**

**F4I Technique**

- [1] Boesch and McGarrity, IEEE Trans. on Nuc Sci, Vol. NS-26, No. 6, Dec. 1979.

**Tests reported in [1] on MOS capacitors show relative shift in flatband voltage for irradiated and stressed devices**

## ISI’s IBM 130nm Process Monitor Custom Coupon Chip

- 3.22 mm

-   Process: IBM 8RF-LM CMOS
-   Submitted to MOSIS for fab on 31 Jan 2005
-   Pads included for both wafer probe measurments and for wire bonding to packages
-   Includes a total of 42 devices and test structures

## TID Characterization Test Plan

- Circuit Board Adaptor

- GSFC (HP)
- Parametric Analyzer

-   TID Radiation Testing to 2Mrad at GSFC
-   Wafer probe measurements and electrical stress tests will be performed at MOSIS

## Proposed Migration to 90nm 

- A 90nm Process Monitor Coupon will be developed to characterize the TID hardness of the process
- RHBD Coupon Gen. 1 will be expanded to include test structures for monitoring the charge collection efficiency of the substrate for SEU Characterization
- Test Structures for SEL characterization, gate delay/timing characterization
- ISI proposes to collaborate with existing DTRA Digital SET (DSET) program
- Provide test structures to measure SET signal propogation for different levels of logic complexity

## Proposed Task on 130nm Library Maintenance and Distribution

- ISI proposes to
- Maintain and distribute a 130nm RHBD library through the MOSIS foundry service
- Provide complete library view support and ensure compatibility with commercial EDA tools
- Distribute the library to the RHBD community with appropriate export control (ITAR)

## Schedule Status

- IBM 130nm Process Monitor Chip Submitted to Fab on 31 Jan 2005
- Packaged chips expected in early May
- TID Radiation Tests scheduled at GSFC for mid-May
- TID Test Plan in progress
- Development of test plan for electrical stress test correlation (mid-April)
- Further investigation of rapid, low-cost radiation tolerance tracking techniques