# Presentation: 702120

## Advanced Modulation, Coding, Processing and Compression

**Advanced Modulation, Coding, Processing and Compression**
**	****	**
- Pen-Shu Yeh/564 (301) 286-4477
- Parminder Ghuman/564 (301) 286-2823
- July 16, 2002

## Advanced Coding Compression Processing Modulation and Space Electronics

**Objective:**
**	**
**reduce onboard storage, bandwidth requirement, contact time, quick-look**
** ****high performance data compression and onboard processing**
** ****increase the number of reliably transmitted bits per Hertz of available channel bandwidth**
** ****bandwidth efficent channel coding, modulation, equalization scheme**
**provides flexibility to ground processing architecture**
** ****low cost high throughput digital receiver**

## Roadmap

- Level 0+ Processing

- To PIs

## High Performance Data Compression

**Objective - ****Develop algorithm and ASIC hardware to maximize return of science data. The algorithm has to offer tunable compression ratio with processing > 20 Msamples/sec and < 5watts for onboard processing**

- Original Image

- Reconstructed at ratio 20:1

## Reconfigurable Data Path Processor for Onboard Processing

- Applications: Sensor readout correction, 1D-2D filtering, FFT, pixel neighborhood processing, feature extraction, ....

## Bandwidth Efficient Channel Coding 

**Objective - ****Develop bandwidth efficient channel coding technology for near Earth missions**

**Current Status**
**New LDPC codes perform well with iterative decoding and close to the Shannon limits.**
**Code rate >0.8**
**Codes are either cyclic or quasi-cyclic: encoding easily implemented with shift registers. **
**In the process of selecting LDPC codes to propose to CCSDS.**
**Encoder ASIC design planned for 2003.**

## Programmable Modulator/Demodulator

**Current Status**
**ASIC features CCSDS recommendations**
**SOQPSK, GMSK for 2 bits/symbol**
**4D TCM-8PSK for 2.5 (and 2.75) bits/symbol**
**0.35u RT CMOS selected**
**GMSK VHDL codes complete, TCM-8PSK SPW model complete**

**Objective - ****Develop mission selectable modulator ASIC in RT electronics up to 300 Mbps/channel and matching demodulator**

## Next Generation High Rate Digital Receiver

**Objective: **
**Develop a PCI-based prototype high rate digital receiver board using the demo chip, FPGAs, and associated components. **
**The system developed by this task will provide baseband data to level zero processing system.**
**Current Status:**
**Reduced cost (>10x) over existing analog processing systems**
**Increased data rates (>10x) over existing digital processing systems**
**Supports missions that have multiple data rate requirements**
**Test performed on TERRA direct broadcast @  26.25 Mbps**
**Test performed on Landsat7 @150  Mbps**
**Current hardware tested (in lab) at 300 Mbps/channel, x2 channels**

**Parallel Digital Receiver**
**Implemented in PCI card**
**(1.2-2.4 Gbps)**

**Bandwidth and Power **
**Efficient Coded Modulation Simplified for Ultra-high rate Digital processing**

## Yesterday  

**Reed Solomon Channel Coder (CCSDS compliant) in space since ‘95 on XTE NEAR COBRA TRMM CHANDRA TERRA EO1**
**Rad Hard 1.2u (UTMC)**
**200 Mbits/sec @0.85watt**

**Yesterday  **

**2001**

**Future**

** ****TID > 1Mrad**
** ****Mixed/analog**
** ****Ultra Low Temp (15k) RT ULP**
** ****Reconfigurable pipeline processor > 20 GOPS/watt**

**RTULP run2 **
**AMI 0.35u**
**TID > 200krad**
** ****No latchup**
** ****RS Coder**
** ****200 Mbits/sec **
**@ 0.004watt**

**Power Reduction:**
-   50x~100x/component
-      70%/spacecraft

**Radiation Tolerance Ultra Low Power Electronics Status**

**RTULP run3+ **
**AMI 0.35u**
**TID > 200krad**
** ****No latchup**
** ****SEU > 40 LET**
** ****RS Coder**
** ****USES compression chip**
**8051**
**FPGA**
** ****DSP C50 (non-RT)**
**STAR radiometer instr. electronics **

**2002**

**Flight Validation**
- ST5-2004