# Presentation: 013874

## TDC and ADC Implemented Using FPGA

- _Wu, Jinyuan_
- Fermilab, PPD/EED
- Feb. 2007

## Introduction

- FPGA devices are considered belonging to digital world while ADC is an analog measurement function.
- ADC can be implemented directly with FPGA plus a few passive (resistors and capacitors) components.
- Bench tests are done for ADC 6-bit@22.5 MHz and 9-bit@2MHz.  Other speed/resolution combinations are possible.
- The ADC is based on ramp & compare with TDC implemented inside FPGA with 0.69 ns LSB (200ps RMS).
- More than 32 channels of TDC are tested in Altera Cyclone (EP1C6Q240C6, $20) devices.

## ADC Using FPGA

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- AMP &
- Shaper

- ADC

- ADC

- ADC

- ADC

- FPGA

- TDC

- TDC

- TDC

- TDC

- R1

- R1

- C

- R2

- FPGA

- VREF

- Analog signals from AMP & Shapers are directly fed to FPGA pins.
- FPGA output and passive RC network are used to generate ramping reference voltage VREF.
- The input voltages and VREF are compared using FPGA differential input receiers.
- The times of transitions representing input voltage values are digitized by TDC blocks in FPGA.

- T1

- V1

- T2

- V2

- T3

- V3

- T4

- V4

## TDC Using FPGA (LSB 1ns+-)

- 4x Sampling:
- 250 MHz: 1ns(LSB), 288ps(RMS)
- 400 MHz: 625ps(LSB), 180ps(RMS)

## TDC Inside FPGA

**c0**

**c90**

**c180**

**c270**

**c0**

**Multiple**
**Sampling**

**Clock**
**Domain**
**Changing**

**Trans. Detection**
**& Encode**

**Q0**

**Q1**

**Q2**

**Q3**

**QF**

**QE**

**QD**

**c90**

**Coarse Time**
**Counter**

**DV**

**T0**
**T1**

**TS**

- Sampling rate: 360 MHz x4 phases = 1.44 GHz.
- LSB = 0.69 ns.
- Logic elements with critical timing are assigned as shown.

- 4Ch

- Logic elements with non-critical timing are freely placed by the fitter of the compiler.

## Bench Test of TDC

- Micro-processor address line driven by
- 45 MHz clock.
- 32 TDC bin = 1 clock cycle (0.69ns LSB)

- Micro-processor data line.
- Data out from different sources.

- eZ80

- RAM

- Flash
- RAM

- FPGA

- TDC

- eZ80

- RAM

- Flash
- RAM

- FPGA

- TDC

- 45MHz

- 45MHz

## Differential Nonlinearity

- The placement above gives even bin width.
- Occupancy for each bin should 25%.
- The residual DNL < 690*(26-22)/25 = 110ps

- FPGA

- TDC

- Quasi-random
- Input

- The “beat” between input and 45MHz.

- 45MHz

## ADC: Discharge Curve Reference: V-T Curve

- FPGA

- TDC

- TDC

- 50

- 270pF

- 511

- VREF

- The differential receivers are nearly rail-to-rail comparators, but perform best from 0.5-2.2V.
- Measurement range: 9 bits:
- Ramping time 512x0.69ns = 353ns.
- >2MHz sampling rate.
- Dynamic range: about 12 bits:
- 1.6mV/ns or 1.1mV/LSB @ 350ns.
- 2.2V/1.1mV ~ 212.

-  = 146 ns

## ADC Test: Reference on BD3_19

- FPGA

- TDC

- TDC

- 50

- 50

- 1000pF

- 100

- VREF

-  = 59 ns

- Longer time constant causes the V-T curve to be nearly linear.
- Sampling rate: 22.5MHz (2/88ns).
- Measurement range: 6 bits.
- Sensitivity: 10mV/LSB.

## ADC Test: Waveform Digitization on BD3_19

- Input Waveform

- Raw Data

- Input Waveform, Overlap Trigger

- Converted

## ADC Test: Reference on BD4_22

- FPGA

- TDC

- TDC

- 50

- 50

- 150pF

- 100

- VREF

-  = 7.5 ns

- Shorter time constant causes the V-T curve to be exponential.
- Sampling rate: 22.5MHz (2/88ns).
- Measurement range: 6 bits.
- Sensitivity < 6mV/LSB.
- Dynamic Range: ~8 bits.

## ADC Test: Waveform Digitization on BD4_22

- Input Waveform

- Raw Data

- Converted

- The data measured by trailing ramp is much more smoother than the leading ramp for small pulses.

- Small pulses are emphasized by the trailing ramp measurement.

## ADC Test: Summary

|  | Time Constant | Ramping Time & Sampling Rate | Sensitivity | Full Scale Range | Measurement & Dynamic Range
 |
| --- | --- | --- | --- | --- | --- |
| BD4
Discharge | 146 ns | 353 ns
> 2MHz | 1.1mV
/LSB
(@ 0.3V) | .25-2.7V | 9 bits &
~12 bits |
| BD3_19 | 59 ns | 44 ns
22.5MHz | 10mV
/LSB | 1.4-2.05V | 6 bits |
| BD4_22 | 7.5 ns | 44ns
22.5MHz | <6mV
/LSB
(@1.02V) | 1.02-2.48V | 6 bits &
~8 bits |

## Notes

- Like in any analog circuits, noise reduction is the key to reach good resolution.  Two primary measures are taken:
- Appropriate arrangement of the grounding for analog signals.
- Microprocessor are put in “wait” state during ramping and comparing.
- Large noise due to single ended TTL are bad.  But small and random noise from differential outputs can be good for “dithering”.  This is to be studied.
- Being non-linear, the RC exponential charging curve is bad.  But it allows expansion of dynamic range, which is good.  The conversion to linear scale in FPGA is very simple.

## Remarks

- The ADC functions tested have met requirements of many applications in high energy physics and accelerator instrumentation.
- The FPGA ADC will not completely replace commercial ADC or ASIC.  But it is appealing for sake of convenience (like for slow control/monitoring) or for low cost with large channel count (like for straw tube or TPC chambers).

## Beyond

- The TDC-readout system has excessive capabilities.  Don’t hastate to ask more if you need.
- TDC: Arrival time + pulse width.
- Chamber info in trigger.

## TDC FPGA (32 Ch)

- 4Ch

## The FPGA TDC Test Card

- Serial Port

- VME Interface
- (As hit input)

- FPGA

- Shown here is Fermilab Beam Loss Monitor (BLM) Control Card

- Microprocessor

## TDC-Readout System

## Slide 20

## CC = plain 26.5MHz clock most of time.

- On start, send marker D0 to reset TS and EV counters.
- For L1 trigger, send D1, TS and EV are stored into header.
- TS is mod 294 (super bunch?).
- Every 294 cycles, send D1 for TS error checking.
- The header contains TS and EV so that EV errors can be detected offline.