# Presentation: 125609

## Fermilab/Boeing Test Results for HiSTE-VI

**Don Lincoln**
**Fermi National Accelerator Laboratory**

## Analysis: Gain and Yield

**Gain determined by separation between    peaks**
**13 ADC counts per     femtocoulomb**
**Typical Gain 40 000**
** ****Yield (pe.) **
**      ****N****PE ****=**** **
**(Average -Pedestal)/Gain**

- same voltage)

## Analysis: Threshold

**VLPCs at operating temperature  (9 K)**
**VLPCs at operating voltage (6.2-8.0 V)**
**Pedestal run taken**
**Large 0-pe peak, much smaller 1-pe peak**
**Threshold set at 50kHz  (Typically 1.2-1.6 pe)**

- 99.5%

- ADC Counts

## Analysis: Efficiency

**N****MIP****,the number of photoelectrons expected from a minimum ionizing particle in the DØ fiber tracker: N****MIP**** = N****PE****x9/2**
**9 photoelectrons observed in the prototype of the DØ tracker in a cosmic ray test**
**2 is the number of photoelectrons in this setup, in the reference VLPC chip**
**Efficiency is the probability that the signal, which is assumed to have Poisson distribution with mean, N****MIP****, is greater than the threshold**

## Acceptance Criteria

**Data taken at several values of the bias voltage in steps of 0.2 V**
**Operating bias: average of pixels’ efficiency is a maximum (not Quantum Efficiency)**
**Chip accepted if at the operating voltage**
**The efficiency of each pixel greater than 0.99**
**The gains of all pixels similar**

## Analysis Technique: Summary

**Set background photoelectron rate (20 MHz)**
**Set signal rate (1.75 photoelectrons @ 500 Hz)**
**Find threshold ****(0.5% noise rate, 100 ns gate [0.35% in DØ])**
**Find gain (typically ********40 000 (or 80 LeCroy 2249 ADC counts per photoelectron))**
**Find photoelectron yield **
**Determine quantum efficiency ****(typically 80% @ 0 MHz)**
**Determine DØ single fiber trigger efficiency     ****(assume 9 pe/mip)**
**Vary voltage to maximize triggering efficiency**

## VLPCs for DØ

**VLPC’s manufactured in two distinct cycles**
**First 1/3 (700 series)**
**Then 2/3 (1100 series)**
**13 300 needed including 10% spares**
**17 845 tested at 20 MHz**
**15 541 accepted **
**Yield: 87%**
**Failed chip                                                recovery                                                    attempted.**
**0 MHz results**
**382 chips**

## Count Summary

**Count Summary**

**Tested: ****	****	****17845**
**Accepted: ****	****15541**
**Retested:****	****	****  2250 (Some failed,                                ****	****                       some never tested)**
**Accepted #2:****	****  1150 (50%) (typically lower gain)**

## Recoverable Failure Modes

**‘****Hot’ cryostats**
**Known bad channels (in test stand)**

- Boeing

- Fermi

## Efficiency, Bias Voltage

**Efficiency**
**much higher than the required minimum 0.99**
**Operating Bias    Voltage**
**ranges from **
**  ****5.8 V to 8.0 V**

- 

- V

- V

## Gain

**Gain**

**Gains (in thousands)**
**Range from **
**20 000 to 60 000**
**Gain dispersion of the pixels within one chip**
**About 1.5 %**

- 

- 

- 

## Recovered Chips

**Recovered chips tended to have lower gain**

## Threshold

**Thresholds for 50 kHz dark count rate**
**Range from **
**1.2 to 1.8 pe**
**RMS of threshold dispersion of the pixels within one chip**
**About 0.03 pe**

## Threshold

**Thresholds in fC (gain) X (threshold pe)**
**Range from **
**5 fC to 15 fC**

## Quantum Efficiency and Threshold

**Algorithm selects voltage where noise begins to grow, ****not at maximum Quantum Efficiency **
**Proper Normalization: 77% 20MHz, 71% 0MHz at optimum voltage**

## Quantum Efficiency

**Quantum Efficiency**

**Absolute QE for Calibration Chips Problematic**
**Initial Operating Voltages for Calibration Chips Chosen for Noise Characteristics at 0 MHz**

## Quantum Efficiency

**Quantum Efficiency**

**Absolute QE determined for few Calibration Chips (735-21)**

**At 9K, 7.0 V, <QE> was determined to be 81.7% (J13, I11, H12) (81.6,85.3,78.3) (systematic error on each ±6%)**

## Qualitative Threshold

**Noise grows very quickly, once a voltage threshold is exceeded.**

## Gain Behavior

**Gain poorly correlated with voltage, but relative gain extremely correlated.**

- RMS 1.9%

## Temperature Behavior

**Temperature affects response.**
**All plots normalized to signal at 9 K (nominal operating temperature).**

## Linearity at 0 MHz Background

**VLPC’s are linear to <10% for Equivalent PE ~600 (~750 photons)**
**Slight gain dependence, although gain is only tangentially related.**
**Linearity independent of voltage (limited checking).**

- Gain ~50 000

- Gain ~30 000

- Normalization Point

- Measurement
- Artifact

## Summary

**Test yield 87%, higher than anticipated, 93% after recovery**
**Chips need to be sorted because of the spread in the bias voltage and threshold**
**One bias per 8 VLPC chips in DØ detector**
**One threshold per 8 VLPC chips in the DØ trigger electronics**
**All pixels belonging to one chip have nearly identical efficiencies, gains, and thresholds**
**Operating phase space complex**
**Voltage, Gain, Threshold, Efficiency, ****Temperature****, ****Rate**** **
**We will make calibration runs to adjust operating voltage and thresholds to the actual background seen in the experiment**