# Presentation: 693465

## PEM  Qualification Requirements For Radiation Hardened Non-Hermetic Products to be used in Space Flight Applications

- Prepared for the 2001 MRQW Workshop by:
**Joseph J Fabula**
- Xilinx
- email: joef@xilinx.com
- tel: 408 879 5302

## Plastic vs HermeticWhy Choose ?

- Moisture Sensitivity & It’s Effects
- Mass & Weight Differences
- Shock & Vibration Response
- Material Outgassing Effects
- Package Qualification Data
- Board Qualification Data
- Future PEM Assembly Roadmap
- is Ceramic Assembly going the way of the Passenger Pigeon?

## Moisture Effects

- All Xilinx production PEMs are certified according to JESD20 (minimum moisture susceptibility Level 3)
- JESD20 certification includes three passes of solder simulation (currently at 230°C) to allow for a reasonable amount of board rework
- “POPCORN” occurrence is largely a myth (after a successful board assembly operation)
- Space is actually a benign, dry environment for PEMs                  (“it doesn’t rain in space”)

## “POPCORN”

- “POPCORN” can only occur _during_ the assembly process (and _only_ if industry standard rules are not followed)
- “POPCORN” is caused by the liberation of steam formed during the rapid thermal excursion to 230°C seen in the solder reflow process (note: in the future lead-free parts will make this excursion even worse, but better mold compounds may mitigate the effects)
- “POPCORN” can only occur when (if) adsorbed moisture is turned to steam faster than it can escape
- “POPCORN” does not occur in operation simply because temperatures and temperature ramp rates (in operation) are simply not high enough

## Thermal Comparisonavailable plastic versus ceramic

- PLCC84	28.4 °C/w
- PQ240	12.3 °C/w
- BGA432	10.7 °C/w        3.53 °C/w
- BGA560	10.2 °C/w        3.18 °C/w
- FG680	10.6 °C/w        3.46 °C/w
- FG900	13.5 °C/w        5.45 °C/w
- FG1156	13.4 °C/w        5.38 °C/w

- PG84		32.5 °C/watt
- PG175	21.9 °C/watt
- CB228	17.5 °C/watt
- CG560	14.3 °C/watt
- no higher pin count ceramic packages are currently available from Xilinx

***Theta JA***

***Psi JB***

***Theta JA***

## Weight & Launch Cost  Comparisons available plastic versus ceramic 

- PLCC84		6.8gr
- PQ240		7.1gr
- BGA432		7.1gr
- BGA560	          12.3gr
- FG680	          10.6gr
- FG900		4.2gr
- FG1156		6.2gr

- PG84		  7.5gr
- PG175		17.7gr
- CB228		17.6gr
- CG560		44.0gr
- no higher pin count ceramic packages are currently available from Xilinx

- CG560		$969.00
- BG560		$270.00
- FG900		$ 92.00

- Based on $10,000/lb
-  to GEO Orbit

## Shock & Vibration available plastic versus ceramic

- The lower weight (mass) of PEMs gives them a distinct advantage in passing board mount vibration tests
- PEMs are solid encapsulation, so ultrasonic cleaning and shock cannot affect bond wire integrity (beware the MQ package, it _is_ a cavity package)
- PEMs are qualified to all shock, vibration and life tests utilizing the following standard test methods:
- method 1010    T/C condition C
- method 1011     T/S condition C
- method 1005     Steady State Life
- method 2004     Lead Integrity
- method 2005     Vibration

## Shock & Vibration (continued)

- PEMs offer the additional advantages of being manufactured on main stream, high volume commercial manufacturing lines with:
- method 2011 bond strength, _under_ _SPC_ _control_ with CpKs > 2.0, on QML certified lines
- method 2019 die shear, _under_ _SPC_ _control_ with CpKs > 1.5, on QML certified lines
- method 2012 radiography, with die attach coverage and bond sweep _under_ _SPC_ _control_, on QML certified lines

## Outgassing Effects

- Data Source: NASA Web Site
- http://epims.gsfc.nasa.gov/og-cgi/uncgi/search/search_html.sh
- Key Parameters
- TML (total material loss)
- CVCM (condensable volatiles recovered)
- NASA Specifications
-   A	TML < 1.0%	CVCM < 0.1%
-   B	TML < 3.0%	CVCM < 1.0%
-   X	TML > 3.0%	CVCM > 1.0%

## Packaging Materials

- Injection Molded Packages (today)
- PLCC:      Nitto MP 8000
- PQFP:       Nitto MP8000, Sumitomo 7304
- PDIP/SO:  Sumitomo 6300
- Ball Grid Packages
- SBGA:      Hysol FP4450, BT Laminate
- BGA:        Plaskon SMBT-1, BT Laminate

## Outgas DataInjection Molded Packages

**PQFP, PDIP, SO, BGA**
- Sumitomo 6300 (PDIP, SO, PLCC)
- TML 0.27%
- CVCM 0.00%
- Sumitomo 7304 (PQFP, TQ/VQ)
- TML 0.17%
- CVCM 0.00%
- Nitto 8100 (PQFP, PLCC)
- TML 0.20%
- CVCM 0.01%
- BT Laminate (BGA substrate)
- TML 0.78%
- CVCM 0.01%
- Plaskon SMTB-1 (BGA mold compound)
- TML 0.28%
- CVCM 0.00%

## Outgas DataEncapsulated  Packages

**SBGA**
- BT Laminate (SBGA substrate)
- TML 0.78%
- CVCM 0.01%
- Hysol FP4450 (SBGA encapsulate)
- TML 0.13%
- CVCM 0.00%

## Circuit Board Outgasfor comparison

- FR-4 (various formulations)
- TML 0.22 - 0.41% (range)
- CVCM 0.00 - 0.01% (range)
- Polyimide Laminate
- TML 0.78%
- CVCM 0.01%
- Conclusion:  The PC board materials have considerably _more_ _outgassing_ _potential _than the various materials used to fabricate the PEMs mounted on these boards

## Possible Indicators of Quality Manufacturing

- ISO9000 Conformance
- DSCC QML Certification
- PURE Approval
- Open Data Communications
- On-going Reliability Monitoring Programs
- SPC Data Availability
- Applications Support

- SPC Control Programs
- TL9000 Certification
- Subcontractor Control Programs
- PCN/PDN Process
- Mask Revision Control
- Hardness Assurance Data
- SEU Upset Data

## Typical Wafer Fab SPC Report

## Parametric SPC Report

## Metal Step Coverage of CMP Process

## Metal Step Coverage of Reflow Process

## SPC Trends in SBGA Packages

## SPC Trends in PLCC Packages

## Plastic Qualification Tests

- Temperature Cycling (T/C)
- Moisture Resistance (PCT)
- Humidity Temperature Bias (85/85)
- Highly Accelerated Stress Test (HAST)

## Temperature Cycling (T/C)

- Performed to 883 Method 1010
- Moisture Pre-stress to Level 3 (minimum)
- Full Solder Simulation per JESD20
- Condition C (-65°C/+150°C) for Injection             Molded Packages (PQFP, PLCC, SO)
- Condition B for Ball Grid Packages
- Full Production Testing at end of Stress
- Package Decapsulation at End of Test to check for Die Cracking

## Results of Temp Cycle Testing

## Pressure Pot Testing

- Performed in 121°C Steam at 2 atm
- Moisture Pre-stress to Level 3 (minimum)
- Full Solder Simulation per JESD20
- Minimum test duration of 96 Hours
- Typical test duration of 168 Hours
- Full Production Testing at end of Stress
- Package Decapsulation at End of Test to Examine for Corrosion

## Moisture Resistance Testing

## Temperature Humidity Bias

- Performed to 85°C, 85%RH, Nominal Vcc
- Moisture Pre-stress to Level 3 (minimum)
- Full Solder Simulation per JESD20
- Minimum stress of 1,000 hours
- Full Production Testing at end of Stress
- Package Decapsulation at End of Test to check for Corrosion

## Temperature Humidity Bias

## Highly Accelerated Stress Test

- Performed at 130°C, 85%RH, 2atm, Vcc
- Moisture Pre-stress to Level 3 (minimum)
- Full Solder Simulation per JESD20
- Minimum stress of 100 hours
- Typical stress of 200 hours
- Full Production Testing at end of Stress
- Package Decapsulation at End of Test to check for Corrosion

## Highly Accelerated Stress Test

## 2nd Level Reliability Test - FG680 (SBGA)

**2nd Level Reliability Test - FG680 (SBGA)**

- 

**Package**

- 

**Motherboard**

- –

- 1.6mm Thick

- –

- 0.38mm Pad NSMD

- 

**Test Data**

- –

- TC2 is 1.25X More

- Damaging

## 2nd Level Reliability Test - FG1156 (PBGA)

**2nd Level Reliability Test - FG1156 (PBGA)**

- 

**Package**

- 

**Motherboard**

- –

- 1.6mm Thick

- –

- 0.38mm Pad NSMD

- 

**Test Data**

- –

- 2 Separate Nets/Device

- 

- Inside the Die

- 

- Outside the Die

- –

- Nets Inside the Die

- Failed First

- 

- Failures Primarily

- Underneath the Die

- –

- No Significant

- Difference Between

- TC1 and TC2 Results

## Packaging Industry Evolution

**1960’s**

**THRU-HOLE Packages**

**DIPs**
**2.54 mm Pitch**

**1980 - 1990**

**PERIMETER SMT**
**Packages**

**High Performance**
**High Pincounts / I/Os**
**Product Miniaturization**
**Portables**

***Size and Performance***
***Limitations***

**1991 ********  Millennium**

**BGA ****1.27mm**

**FBGA ****1.0 mm**

**CSP **
**0.8 - 0.5 mm**

**XILINX**
**1999-2000**

**AREA ARRAY SMT**
**Packages**

## Advanced Package and Technology Roadmap Y1997-Y2002

- Advanced Package and Technology Roadmap Y1997-Y2002

## Xilinx BGA Packaging Strategy

**Virtex**
**Spartan**
**CPLD**

**0.8-0.5mm**

**1.0-1.27mm**

- Package Tracks with Market Needs

- “SBGA”
- Cu-Based BGA
- 352-860 pins

- High Power / Thermal Dissipation
- High Density / IOs
- High Performance / Frequency Design
- Feature Crammed, High Speed Switching Systems

- Flip Chip BGA
- _>_ 900 - 1500 pins

- Highest Power / Thermal Dissipation
- Highest Density / IOs
- High Performance Interconnect Enabler
- Feature Crammed, High Speed Switching Systems
- Advanced High-End Products

**Xilinx CSP and FinePitch BGAs are ****. . .**
** ****	****	**** ****. . .**** *****“Application Optimized”***
***	******.  .  . Offers Total Product Solution******  ***

- Mid-Range / Mainstream
- General Functions
- Off-the-Shelf
- User Friendly
- Cost Effective

- “FinePitch BGA”
- Plastic Molded BGA
- 256-1156 pins

- Miniaturization, Light Weight
- Wireless Communication
- Height Restriction
- PCMCIA, Portables
- Low Cost and High Volume

- “CSP”
- Flex-Based BGA
- 48-280 pins

**1.0mm**