# Presentation: 053794

## FPGA ROD Implementation Model #2

- Atlas - Wisconsin Group
- Khang Dao, Damon Fasching, Richard Jared,
- John Joseph, Mark Nagel, Linda Stromburg and
- Lukas Tomasek
- December 17, 1999

## Model #2 96Link ROD Event DataPath

- Evnt
- Frg
- Bldr
- Fifo0

- Evnt
- Frg
- Bldr
- Fifo1

- Router

- Event
- Fragment
- Builder

- DSP3
- Fifo/Buffer

- DSP2
- Fifo/Buffer

- DSP1
- Fifo/Buffer

- DSP0
- Fifo/Buffer

- RODController

- DSP3
- Module

- DSP2
- Module

- DSP1
- Module

- DSP0
- Module

- vmeBUS

- bocCARD
- interface

- Link 0DATA    1b

- Link 11DATA  1b

- Link 12DATA  1b

- Link 23DATA  1b

- Link 24DATA   1b

- Link 35DATA  1b

- Link 36DATA  1b

- Link 47DATA  1b

- Link 48DATA   1b

- Link 59DATA  1b

- Link 60DATA  1b

- Link 71DATA  1b

- Fifo 40b
- DATA

- Fifo 40
- DATA

- Fifo 40b
- DATA

- Fifo 40b
- DATA

- Fifo 40b
- DATA

- Fifo 40b
- DATA

- EvntFrgBldr
- DATA  46b

- EvntFrgBldr
- DATA  46b

- Event        46b
- Header/Trailer

- Events  46b

- Events  32b

- Trapped 32b
- DATA

- Trapped 32b
- DATA

- Trapped 32b
- DATA

- Trapped 32b
- DATA

- SLINK 1b

- TIM EventDATA     16b

- TIM TriggerDATA    8b
- from TIM

- Processed  16b
- Trapped
- DATA

- Processed  16b
- Trapped
- DATA

- Processed  16b
- Trapped
- DATA

- Processed  16b
- Trapped
- DATA

- NOTE: Some signals have been omitted for clarity

- SLINK
- Event Fifo
- 32bx4W

- SLINK

- Link 72DATA  1b

- Link 83DATA  1b

- Link 84DATA  1b

- Link 951DATA 1b

- Fifo 40b
- DATA

- Fifo 40b
- DATA

- Formatter
- Fifo0

- DynamicMask        12b

- Formatter
- Fifo1

- Formatter
- Fifo2

- Formatter
- Fifo3

- Formatter
- Fifo4

- Formatter
- Fifo5

- Formatter
- Fifo6

- Formatter
- Fifo7

- DataValid 1b

## Model #2 96Link ROD DebugPath

- Router

- Event
- Fragment
- Builder

- DSP3
- Fifo/Buffer

- DSP2
- Fifo/Buffer

- DSP1
- Fifo/Buffer

- DSP0
- Fifo/Buffer

- RODController

- DSP3
- Module

- DSP2
- Module

- DSP1
- Module

- DSP0
- Module

- vmeBUS

- bocCARD
- interface

- Link 12DATA  1b

- Link 23DATA  1b

- Link 24DATA   1b

- Link 35DATA  1b

- Link 36DATA  1b

- Link 47DATA  1b

- Link 48DATA   1b

- Link 59DATA  1b

- Link 60DATA  1b

- Link 71DATA  1b

- Fifo 40b
- DATA

- Fifo 40
- DATA

- Fifo 40b
- DATA

- Fifo 40b
- DATA

- Fifo 40b
- DATA

- Fifo 40b
- DATA

- NOTE: Some signals have been omitted for clarity

- SLINK
- Event Fifo
- 32bx4W

- SLINK

- Link 72DATA  1b

- Link 83DATA  1b

- Link 84DATA  1b

- Link 951DATA 1b

- Fifo 40b
- DATA

- Fifo 40b
- DATA

- Formatter
- Fifo0

- Formatter
- Fifo1

- Formatter
- Fifo2

- Formatter
- Fifo3

- Formatter
- Fifo4

- Formatter
- Fifo5

- Formatter
- Fifo6

- Formatter
- Fifo7

- InMEM
- Memory0

- Link 0DATA  1b

- Link 11DATA  1b

- Link 12DATA  1b

- Link 23DATA  1b

- Link 24DATA   1b

- Link 35DATA  1b

- Link 36DATA  1b

- Link 47DATA  1b

- Link 48DATA   1b

- Link 59DATA  1b

- Link 60DATA  1b

- Link 71DATA  1b

- Link 72DATA  1b

- Link 83DATA  1b

- Link 84DATA  1b

- Link 951DATA 1b

- Link 0DATA  1b

- Link 11DATA  1b

- INMEM R/W & Control               32b

- DEBUGMEM R/W & Control      32b

- Debug
- Memory0

- Debug
- Memory1

- InMEM
- Memory1

- EVNTMEM R/W & Control         32b

- Evnt
- Frg
- Bldr
- Fifo0

- Evnt
- Frg
- Bldr
- Fifo1

## Model #2 96Link ROD ControlPath

- Event
- Fragment
- Builder

- RODController

- vmeBUS

- bocCARD
- interface

- Formatter
- Fifo0

- ShowTrailerFLAGS[7..0]                     8b

- DecoderWritesTrailer[11..0]                12b

- HeaderTrailerLlimit[7..0]                      8b

- EvntFrgBldrBUS                                  22b
- SetRegK, ClearPointers,ReadCounters
- 4+2adr, 8data, 4control

- FormatterBUS                                      26b
- 4+4adr, 16data, 3control

- NOTE: Some signals have been omitted for clarity

- Events  46b

- Event        46b
- Header/Trailer

- RouterBUS              24b
- Control Registers
- write through Registers

- XON/XOFF          1b
- from SLINK

- STOPOUTPUT                                 1b

- HOLDoutput   1b

- SLINK
- Event Fifo
- 32bx4W

- SLINK

- DSP3
- Module

- DSP2
- Module

- DSP1
- Module

- DSP0
- Module

- dspData/InstructionBUS
- 16adr,16data,6ctl     22b

- rodBUSY               2b
- busyModule

- EVENTTri-StateControl                   2b

- EvntFrgBldrWritingDATA               2b

- setupBUS      16b
- 10adr,8data,2ctl

- controlBUS    79b
- config,control,
- monitoring,
- processed/trapped
- data
- 32adr,32data,15ctl

- FEtrigger/timing  48b
- to FEmodule[0..47]

- slaveDSPs

- HALTOUTPUT   1b

- OR

- INMEM R/W & Control                       34b

- Formatter
- Fifo1

- Formatter
- Fifo2

- Formatter
- Fifo3

- Formatter
- Fifo4

- _Command_ w=16b
- _MessageList_
- portA portB

- _Command_ w=16b
- _MessageList_
- portA portB

- _Command_ w=16b
- _MessageList_
- portA portB

- _Command_ w=16b
- _MessageList_
- portA portB

- Formatter
- Fifo5

- Formatter
- Fifo6

- Formatter
- Fifo7

- TIM TriggerDATA    8b
- from TIM

- Evnt
- Frg
- Bldr
- Fifo1

- Evnt
- Frg
- Bldr
- Fifo0

- RodBusyLimit[7..0]                              8b

- Router

- DSP3
- Fifo/Buffer

- DSP2
- Fifo/Buffer

- DSP1
- Fifo/Buffer

- DSP0
- Fifo/Buffer

## FPGA ROD Implementation Model #2Formatter/Fifo

- Atlas - Wisconsin Group
- Khang Dao, Damon Fasching, Richard Jared,
- John Joseph, Mark Nagel, Linda Stromburg and
- Lukas Tomasek
- December 17, 1999

## Model #2 Formatter FPGA 

- _Formatter_
- _and_
- _Link_
- _Output_
- _FIFOs_

- Model #2 Formatter FPGA

- Link[11..0]DATA    12b

- FifoDATA              32b

- _Link Number:_
- 12:4 Encoder

- Link# hasTOKEN     4b

- HOLDoutput            1b

- _FWT Encoder:_
- latch Trailers and store new internal state
- on ShowTrailerFLAGS

- FormatterBUS       26b
- from RodContoller

- ShowTrailerFLAGS         1b

- L1TriggerPulse         1b

- TOKENin         1b
- from previous chip

- DecoderWritesTrailer       12b

- D
- FF

- HeaderTrailerLimit      1b

- FetchNextModeBits               1b

- Event
- Fragment
- Builder

- RodController

- NOTE: resolve latency requirement
- 12+6+1+15 clk cycles

- FormatterBUSStrobe[11..0] 12b

- HeaderTrailerLimit[11..0]                      12b

- DecoderWritesTrailer[11..0]                  12b

- TimeOutError[11..0]                              12b

- Link[11..0]hasTOKEN                           12b

- TOKENout      1b
- to next chip

- StrobeModeFifos       1b

- ModeFifoEmpty[11..0]   12b

- Formatter BUS        21b
- D[15..0]+
- A[3..0]+
- RNW

- ModeFifoEmpty      1b

- StrobeModeFifos     1b

- FifoDATA                 32b

- HOLDoutput              1b

- _Mode Bit Readout_
- 2, 12bit words
- 2bits each link

- ModeBitsIN[11..0]      12b

- RegTransferACK[11..0]  12b

- _OperationsController:_

- Acknowldge  1b

- A[7..4]          4b

- Strobe           1b

- MasterNSlave           1b

- DataValid[11..0]                                     12b

- CondensedMode[11..0]                          12b

- RODBusyLimit[11..0]                            12b

- FormatterBUSStrobe[11..0]   12b

- RegTransferACK[11..0]         12b

- HeaderTrailerLimit[11..0]  12b

- RODBusyLimit[11..0]       12b

- Link[11..0]hasTOKEN    12b

- ThisChipHasToken   1b

- RODBusyLimit            1b

- DataValid                   1b

- DataValid[11..0]                12b

- TimeOutError             1b

- TimeOutError[11..0]          12b

- CondensedMode         1b

- CondensedMode[11..0]      12b

- StoreTrailerHit
- 1ea
- 2 state
- state machine
- ClearCurrentFlag

- TokenToReadOutTimeOutREG   7b

- DataOverflowLimitREG               9b

- HeaderTrailerLimitREG                8b

- RodBusyLimitREG                       5b

- LimitREGs                29b

- Note: XCV400fg-5 4800 20

## Model #2 Formatter FPGA: Link Formatter and Link Output FIFO

- FifoDATA       32b

- TimeOoutError0, DataOverflowError0     2b

- TOKENin        1b

- TOKENout      1b
- to next link

- Link 0hasTOKEN    1b

- FormatterWritesTrailer 0                           1b

- HOLDoutput    1b

- HeaderTrailerLimit0,RODBusyLimit0     2b

- Link
- Output
- FIFO

- Formatter0DATA            32b

- _TOKENController:_

- .
- 10ea
- 12total
- .

- TOKENin         1b
- from previous link

- TOKENout                 1b
- to next chip

- Link 11hasTOKEN    1b

- FormatterWritesTrailer11                           1b

- Link
- Ouput
- FIFO

- Formatter11DATA           32b

- FormatterBUS          21b
- from RodContoller

- L1Trigger          1b

- TOKENin         1b
- from previous chip

- _TriggerCounter:_

- FifoDATA       32b

- TimeOoutError11, DataOverflowError11  2b

- HOLDoutput                                              1b

- HeaderTrailerLimit11,RODBusyLimit11  2b

- ModeBitsIN[1..0]0    2b

- FormatterBUSStrobe0    1b

- RegTranferACK0            1b

- MasterNSlave   1b

- FifoDATA     32b

- HOLDouput   1b

- Link 11DATA   1b

- Link 0DATA  1b

- .
- .
- .
- 10ea
- 12total
- .
- .

- Link
- Formatter

- Link
- Formatter

- FormatterBUS    21b

- DataValid0      1b

- FormatterBUSStrobe11   1b

- RegTranferACK11           1b

- FormatterBUS    21b

- DataValid11     1b

- CondensedMode         1b

- LinkStaticMask           1b

- NormalNRaw              1b

- HeaderTrailerLimit     1b

- CondensedMode         1b

- LinkStaticMask           1b

- NormalNRaw              1b

- HeaderTrailerLimit     1b

- ModeBitsIN[1..0]11   2b

- FormatterWritesTrailer     1b

- FormatterWritesWord      1b

- FormatterWritesTrailer     1b

- FormatterWritesWord       1b

- _Mode Bit Readout_

- FetchNextModeBits               1b

- LimitREGs                29b

- LimitREGs                29b

- DataOverError           1b

- DataOverError           1b

## Model #2 Formatter FPGA: Link Formatter

- FormatterDATA             32b

- Link DATA  1b

- CondensedMode         1b

- LinkStaticMask           1b

- NormalNRaw              1b

- HeaderTrailerLimit     1b

- FormatterWritesTrailer     1b

- FormatterWritesWord      1b

- almost_full           1b

- condensed_mode  1b

- config_mode        1b

- edge_mode           1b

- link_in             1b

- data_out_write   1b

- decoded_data    16b

- _Link Formatter:_

- _SerialToParallelDecoder_

- _Event Word Builder:_
- 16b to 32b conversion

## Model #2 Formatter FPGA: Link Output FIFO

- FormatterWritesTrailer        1b
- from Formatter

- FormatterWritesTrailer     1b
- to RODcontroller

- HeaderTrailerLimit            1b
- to Formatter

- PipelineDataOut  32b

- SeeHeader             1b

- SeeTrailer             1b

- HasWord                                 1b

- HOLDoutput                           1b

- EnableStateMachine     1b

- TimeOutError                1b

- DataOverflowError        1b

- ReadoutCntrlModeBits[1..0]  2b

- LinkHasToken              1b

- DataValid                      1b

- _TokenManager_

- TokenIn          1b

- PassToken      1b

- LinkHasToken            1b

- EnableTristate               1b

- EnableStateMachine   1b

- FormatterBUS              22b
- 4A+16D+1RNW+1Strobe

- _Fifo Control_
- _ __StateMachine:_

- PassToken                     1b

- _Operation State_
- _and _
- _Control_
- _Registers _

- TimeOutError                1b

- DataOverflowError        1b

- CondensedMode            1b

- LinkStaticMask             1b

- NormalNRaw                 1b

- TokenOut                    1b

- FifoData              32b

- FormatterData   32b

- EnableTristate           1b

- OccupancyCount   8b

- HasWord               1b

- >=1 comparator

- HeaderTrailerLimit  1b

- RodBusyLimit          1b

- >= comparator

- >= comparator

- HeaderTrailerLimitREG  8b

- RodBusyLimitREG          5b

- Fifo and
- Pipeline
- Control

- Fifo and
- Pipeline
- Control

- TokenToReadOutTimeOutREG   7b

- DataOverflowLimitREG               9b

- _FifoBuffer_
- 192Word
- x32bits

## Model #2 Formatter FPGA: FIFO Control StateMachine and Signals

- HOLDoutput                           1b

- EnableStateMachine               1b

- SeeHeader                               1b

- SeeTrailer                                1b

- TimeOutError                         1b

- DataOverflowError                 1b

- ReadoutCntrlModeBits[1..0]  1b

- TimOutError                             1b

- DataOverFlowError                  1b

- DataValid                                  1b

- NextReadoutAddress                1b

- EnablePipeline                          1b

- LinkHasToken                        1b

- TokenToReadOutTimeOutREG               7b
- from local REGister file

- DataOverflowLimitREG                           9b
- from local REGister file

- PassToken                                 1b

- FIFOOutputEnable                   1b

- Fifo and
- Pipeline
- Control

- ClearReadPointer                      1b

- EnableTristate                           1b

- FormatterWritesWord             1b

- HOLDoutput                           1b

- ReadoutCntrlModeBits[1..0]  1b

- HOLDoutput                           1b

- ClearWritePointer                    1b

- SelectDebugInput                     1b

- NextWriteInAddress                1b

- FifoWriteEnable                       1b

- _Fifo ReadOut StateMachine:_

- _Fifo WriteIn StateMachine:_

## Model #2 Formatter FPGA: FIFO StateMachine Structure

- State
- Register
- enable

- Inputs

- Next
- State
- Logic

- Output
- Logic

- PresentState

- NextState

- Outputs

- Clock

- Enable

## Model #2 Formatter FPGA: FIFO ReadOut StateMachine and Signals

- State machine contains a 2 clock delay from inputs to outputs
- Read out data on every clk given the following conditions:
- EnableStateMachine =  LinkHasToken
- _ReadoutModes:_
- 00  Normal Readout of Current Event - EventFragmentBuilder control
- 01  Link is Masked Off (no formatting nor data collection) - EvntFrgmntBldr control
- 10  Skip link for this event - EvntFrgmntBldr control
- 11  Read over first event in fifo and readout second event - EvntFrgmntBldr control
- _ERROR Timers/States:_
- 1 TOKEN to Readout TimeOut - Have not received data Words from formatter
-    - If  ((LinHasToken & (/HasWord) & (TimeOutError))
-    : count till TokenToReadOutTimeOut limit, assert PassToken
- 2 Link Spews Data - Events of greater than (31*16 Pixel, 768 SCT) Words
-    - If  ((LinkHasToken) & (DataOverFlowError))
-    : count till DataOverFlowError limit, assert PassToken

- HOLDoutput                           1b

- WordCountCounter(local)

- TokenToReadOutTimeOutCounter(local)

- EnableStateMachine               1b

- SeeHeader                               1b

- SeeTrailer                                1b

- TimeOutError                         1b

- DataOverflowError                 1b

- ReadoutCntrlModeBits[1..0]  1b

- TimeOutError                                             1b

- DataOverFlowError                                    1b

- DataValid                                                                     1b

- NextAddress

- ReadWord

- NextReadoutAddress   1b

- EnablePipeline              1b

- LinkHasToken                        1b

- >= comparator

- >= comparator

- TokenToReadOutTimeOutREG               7b
- from local REGister file

- DataOverflowLimitREG                           9b
- from local REGister file

- ClearOverFlowCounter    1b

- ClearTimeOutCounter      1b

- PassToken                                                                    1b

- TimeOutError                    1b

- DataOverflowError            1b

- FIFOOutputEnable                                                      1b

- Fifo and
- Pipeline
- Control

- ClearReadPointer                                                        1b

- DisableTristateBuffer

- EnableTristate      1b

## Model #2 Formatter FPGA: FIFO ReadOut StateMachine State Diagram

- State: RWDV
- ReadWord
- DataValid

- State: RWDVPT
- ReadWord
- DataValid
- PassToken

- State: RWPT
- ReadWord
- PassToken

- State: RW
- ReadWord

- State: IDLE

- State: Reset

- State: ND0
- NoData

- Reset

- ClearOverFlowCounter

- ClearTimeOutCounter

- ClearReadPointer

- DataValid

- NextAddress

- ReadWord

- PassToken

- DataValid

- NextAddress

- ReadWord

- State: PT
- Pass
- Token

- HasWord &
- ReadoutMode0

- ClearTimeOutCounter

- ClearTimeOutCounter

- HasWord &
- SeeTrailer

- HasWord &
- SeeHeader &
- SeeTrailer

- HasWord

- HasWord &
- SeeHeader &
- NOTSeeTrailer

- TimeOutError OR
- DataOverflowError

- ClearDataOverflowCounter

- PassToken

- ModeFifoEmpty

- 1

- NOTHasWord OR
- HOLDoutput

- HasWord &
- SeeHeader &
- SeeTrailer

- HasWord &
- NOTSeeHeader &
- NOTSeeTrailer

- ClearTimeOutCounter

- ClearDataOverflowCounter

- 1

- NOTHasWord

- ReadoutMode3 &
- HasWord

- HasWord

- ReadoutMode1 OR
- ReadoutMode2

- NextAddress

- ReadWord

- ClearTimeOutCounter

- NOTHasWord OR
- HOLDoutput

- ReadoutMode3 &
- HasWord &
- SeeTrailer &

- HasWord

- State: ND1
- NoData

- NOTHasWord &
- ReadoutMode0

- NOTHasWord &
- ReadoutMode3

- ReadoutMode0 OR
- ReadoutMode3

- PassToken

- ReadWord

- EnableTristate

- FIFOOutputEnable

- FIFOOutputEnable

- FIFOOutputEnable

- FIFOOutputEnable

- FIFOOutputEnable

- FIFOOutputEnable

- FIFOOutputEnable

## Model #2 Formatter FPGA: FIFO WriteIn StateMachine and Signals

- _Fifo WriteIn StateMachine:_
- State machine contains a 2 clock delay from inputs to outputs
- While in Modes 0,2,3: write in data whenever the Formatter commands it.
- _WriteinModes:_
- 00  Normal Writein of Event data - EventFragmentBuilder control
- 01  Link is Masked Off (no formatting nor data collection) - EvntFrgmntBldr control
- 10  Normal Writein of Event data - EventFragmentBuilder control
- 11  Normal Writein of Event data - EventFragmentBuilder control

- FormatterWritesWord             1b

- HOLDoutput                           1b

- ReadoutCntrlModeBits[1..0]  1b

- HOLDoutput                           1b

- ClearWritePointer                                                               1b

- NextWriteInAddress                                                           1b

- FifoWriteEnable   1b

## Model #2 Formatter FPGA: FIFO WriteIn StateMachine State Diagram

- State: FDW
- Formatter
- DataWrites

- State: FIAP
- Increment
- Address
- Pointer

- State: IDLE

- State: Reset

- Reset

- ClearWritePointer

- 1

- ReadoutMode1

- NextWriteInAddress

- ReadoutMode0,2,3

- 1

- FormatterWritesWord

## Model #2 Formatter FPGA: Operation State and Control Registers Block

- ConfigREG                                     0x1        5b
- local                          sel    R/NW    Adr    Data

- FlagsREG                                       0x0      15b
- local

- Register Select Decoder & Read/Write Control

- FormatterBUS         22b
- 4A+16D+1RNW+1Strobe

- HeaderTrailerLimit              1b

- HasWord                              1b

- TimeOutError                      1b

- DataOverflowError              1b

- HeaderTrailerLimit              1b

- Model #2 Formatter FPGA: Operation State and Control Registers Block

- CondensedMode                            1b

- LinkStaticMask                              1b

- NormalNRaw                       1b

- RegTranferACK                                       1b

- OccupancyCount                  8b

## Model #2 Formatter FPGA: FIFO Buffer

-  192Wx32b circularFIFO

- Detect  Header | Trailer

- DataOut    32b

- DataIn   32b

- 0

- 192W

- 1st Event Header

- SeeHeader  1b

- SeeTrailer   1b

- HasWord       1b
- from FIFOOccupancyCounter

- R
- e
- g
- i
- s
- t
- e
- r
- enable

- P0  32b

- P1  32b

- 2nd Event Header

- Clock  1b

- EnablePipeline  1b

- WriteInAddress  8b

- ReadOutAddress 8b

- FIFOWriteEnable       1b

- FIFOOutputEnable     1b

- ClearWritePointer         1b

- ClearReadPointer          1b

- WriteInAddress     8b

- ReadOutAddress   8b

- NextWriteInAddress     1b

- NxtAdrs         Write In AdrCounter               8b
- ClrPointer                                WriteInAddress

- NxtAdrs         Read Out AdrCounter             8b
- ClrPointer                               ReadOutAddress

- NextReadoutAddress     1b

- OccupancyCount    8b

- Reset                            1b

- DebugDataOut   32b

- FIFOWriteEnable       1b

- FIFOOutputEnable      1b

- EnablePipeline            1b

- NextReadOutAddress  1b

- NextWriteInAddress   1b

- Fifo and
- Pipeline
- Control

- ClearWritePointer        1b

- ClearReadPointer        1b

- Increment  FIFOOccupancy Counter            8b
- Decrement                             OccupancyCount
- Reset

## Model #2 Formatter FPGA: 192Word Circular FIFO

- FIFOWriteEnableLink0    1b

- FIFOOutputEnableLink0  1b

- WriteInAddressLink0        8b

- ReadOutAddressLink0      8b

- BlockSelectRam2,3                                                                                                    2 x 16bits x 256Words
- Link2                                                                               Link3
- Words[0:127]                                                                  Words[0:127]
- DataInA[31:0]                                                                                                             DataOutB[31:0]
- AddressA                                                                                                                     AddressB
- OutputEnableA                                                                                                            OutputEnableB
- WriteEnableA                                                                                                              WriteEnableB
-  ClkA                                                                                                                            ClkB

- BlockSelectRam4,5                                                                                                      2 x 16bits x 256Words
- Link0                    Link1                   Link2                     Link3
- Words[128:191]   Words[128:191]  Words[128:191]    Words[128:191]
- DataInA[31:0]                                                                                                              DataOutB[31:0]
- AddressA                                                                                                                      AddressB
- OutputEnableA                                                                                                             OutputEnableB
- WriteEnableA                                                                                                               WriteEnableB
-  ClkA                                                                                                                            ClkB

- BlockSelectRam0,1                                                                                                    2 x 16bits x 256Words
- Link0                                                                               Link1
- Words[0:127]                                                                  Words[0:127]
- DataInA[31:0]                                                                                                             DataOutB[31:0]
- AddressA                                                                                                                     AddressB
- OutputEnableA                                                                                                            OutputEnableB
- WriteEnableA                                                                                                              WriteEnableB
-  ClkA                                                                                                                            ClkB

- FifoInputData0                32b

- FifoOutputData0        32b

- FIFOWriteEnableLink1    1b

- FIFOOutputEnableLink1  1b

- WriteInAddressLink1        8b

- ReadOutAddressLink1      8b

- FifoInputData1                32b

- FifoOutputData1        32b

- FIFOWriteEnableLink3    1b

- FIFOOutputEnableLink3  1b

- WriteInAddressLink3        8b

- ReadOutAddressLink3      8b

- FifoInputData3                32b

- FifoOutputData3        32b

- FIFOWriteEnableLink2    1b

- FIFOOutputEnableLink2  1b

- WriteInAddressLink2        8b

- ReadOutAddressLink2      8b

- FifoInputData2                32b

- FifoOutputData2        32b

- Output
- Data/
- Address
- MUX

- clk                                     1b

- Input
- Data/
- Address
- MUX

## Model #2 Formatter FPGA: Token Manager

- TokenManager

- Set
-       Out
- Reset

- TokenIn             1b

- TokenOut                      1b

- Clock                 1b

- LinkHasToken              1b

- EnableTristate              1b

- EnableStateMachine     1b

- TokenOut  1b

- PassToken         1b

## Model #2 Dual EventFragmentBuilder

- TIM TriggerDATA   16b
- from RODcontroller

- _Event Formatter:_

- _EvntFrgBldr Engine0:_

- FifoDATA0                32b
- EventDATA

- Mode[0..1]_0              2b

- Link#hasTOKEN DecoderIC0      4b

- Link#hasTOKEN DecoderIC1      4b

- EvntFrgBldrBUS                         16b

- _EvntFrgBldr Engine1:_

- FifoDATA1               32b
- EventDATA

- Mode[0..1]_1              2b

- Link#hasTOEKN DecoderIC2      4b

- Link#hasTOKEN DecoderIC3      4b

- FIFO Ctrl Input0       3b

- FIFO Ctrl Output0    3b

- STOPOUTPUT        1b

- EventDATA0           32b

- WordCount0              8b

- Current Link #0         5b

- ErrorCounts0             8b

- STOPOUTPUT        1b

- STOPOUTPUT        1b
- from DataDirector

- Event: Header,Trailer         32b

- EVENTTri-StateControl     2b

- FIFO Ctrl Input1       3b

- FIFO Ctrl Output1    3b

- EventDATA1           32b

- WordCount1              8b

- Current Link #1         5b

- ErrorCounts1             8b

- HOLDoutput0             1b

- HOLDoutput1             1b

- TOKENin0                1b

- TOKENin1                1b

- EFBhasTOKEN0      1b

- TOKENout 0              1b

- EFBhasTOKEN1      1b

- TOKENout1               1b

- TIM Header                                                16b
- EventTYPE | L1ID | BCID | ThrottleFLAGs

- TIM Header                                                16b
- EventTYPE | L1ID | BCID | ThrottleFLAGs

- EvntFrgBldrWritingDATA 2b

- TimeOoutError0, DataOverflowError0     2b

- TimeOoutError1, DataOverflowError1     2b

- EventFIFO FULL,EMPTY0      2b
- to RODcontroller

- EventFIFO FULL                1b
- to RODcontroller

- EventFIFO FULL,EMPTY1      2b
- to RODcontroller

- EvntFrgBldrBUS     20b
- SetRegK, ClearPointers,ReadCounters
- 4+4adr, 8data, 4control
- from RODcontroller

- EvntFrgBldrBUS                         16b

- Note: XCV200fg-5 2352 14

## Model #2 GathererEngine preliminary

- CONTAINS: EventTYPE | L1ID | BCID |ThrottleFLAGs

- _Event_
- _Fragement_
- _Builder_

- FifoDATA0               32b
- EventDATA

- Mode[0..1]_0              2b

- TIM Header                                                16b
- EventTYPE | L1ID | BCID | ThrottleFLAGs

- EvntFrgBldrBUS                         16b

- FIFO Ctrl Input0       19b

- FIFO Ctrl Output0    19b

- HALTOUTPUT        1b

- EventDATA0           32b

- WordCount0              8b

- Current Link #0         5b

- ErrorCounts0             8b

- TOKENin0                1b

- EFBhasTOKEN0       1b

- TOKENout 0              1b

- Link#hasTOKEN DecoderIC0      4b

- Link#hasTOKEN DecoderIC1      4b

- HOLDoutput0             1b

- EventID FIFO EMPTY     1b

- TimeOutError0, DataOverflowError0     2b

- SendNextEvent           1b

- EventID FIFO FULL,EMPTY       2b
- to RODcontroller

- RODctrlr FE Status/Control          16b
- EventTYPE| L1ID | BCID | TrottledFLAG | Link#
- from RODcontroller

## Model#2 Event Fragment Builder Engine

- FifoDATA       32b
- EventDATA

- DecoderIC0                 4b

- FIFO: Error Counts

- Header Detector

- _L1ID offset Register File [0..47]_
- Adjust Link#  L1ID by countX

- Link# Encoder

- Current Link #    5b

- _Error Detector:_
- header, trailer, bit,
- sync, timeout, overflow

- Trailer Detector

- DecoderIC1                 4b

- Increment Link# Throttle Count     6b

- Throttle Detector

- RODctrlr FE Status/Control          16b
- EventTYPE| L1ID | BCID | DynamicMask
- from eventFIFO

- _OutputFIFO Controller:_
- FIFO Input   Pointer
- FIFO Output Pointer

- FIFO Ctrl Input     19b

- FIFO Ctrl Output  19b

- STOPOUTPUT       1b

- Output FIFOcount >= K Words
- EventID FIFO EMPTY

- EvntFrgBldrBUS               16b
- SetRegK, ClearPointers,ReadCounters
- 4adr, 8data, 4control
- from RODcontroller

- EventDATA       32b

- WordCount        8b

- Current Link #    5b

- ErrorCounts        8b

- DATA       32b

- SetRegK, ClearPointers

-  staticMASK, staticMODE
-  dynamicMASK, dynamicMODE

- HOLDoutput

- _ReadOUT Manager:_

- ReadOutWord

- EvntFrgBldr n-1

- EvntFrgBldr n+1

- EFBn has TOKEN

- SendNextHeader         1b

- EventID FIFO EMPTY    1b

- WordCount        8b

- Output FIFOcounter

- TimeOoutError, DataOverflowError     2b

- NOTE: This block must
-   1 drop 1/2word no-error trailers
-   2 overwrite non-error trailers in datawords with the next link header

- WriteInWord

- Format Event Data

- FIFO:WordCounts

- WordCounter

- Insert Link/Event Header/Trailer
- on  Link TimeoutError

- Adjust & Header L1ID for checking

## Model #2 EventFormatter

- Code, Format error type
- counts and generate messages

- Generate Event Trailer

- _Event Formatter:_

- Event: Header,Trailer       32b

- EVENTTri-StateControl    2b

- ReadoutTOKEN

- ReadEvent

- TIM EventID            16b
- from RODcontroller

- FIFO: TIM Header
- CONTAINS: EventTYPE | L1ID | BCID

- WordCount0              8b

- ErrorCounts0             8b

- WordCount1              8b

- ErrorCounts1             8b

- TOKENin0                 1b

- TOKENout1               1b

- EvntFrgBldr WritingDATA      2b

- EventFIFO FULL      1b
- to RODcontroller

## Model#2 Router

- EventDATA0           32b

- Current Link #0         5+2b

- Event: Header,Trailer       32b

- EVENTTri-StateControl         2b

- EventDATA1           32b

- Current Link #1         5+2b

- RouterBUS           24b
- FIFO control Registers

- _FIFOBuffer0:_
- _16K Words_

- FIFO Ctrl Input0       3b

- FIFO Ctrl Output0    3b

- FIFO Ctrl Input1       3b

- FIFO Ctrl Output1    3b

- _Router:_

- _FIFOBuffer1:_
- _16K Words_

- TS0

- TS1

- _TriSTATEcontrol Decoder:_

- TS2

- TS2     1b

- TS1     1b

- TS0     1b

- EventINFO
-             46b

- Events                    32b

- XON/XOFF                1b
- from SLINK

- EvntFrgBldrWritingDATA    2b

- EventINFO
-  39

- _SLINK:_

- SLINK DATA0   32b

- STOPOUTPUT         1b

- _DSP FIFO:_
- 256 Words
- 32 bits

- DSPDATA0          32b

- _DSP FIFO:_
- 256  Words
- 32 bits

- _DSP FIFO:_
- 256 Words
- 32 bits

- _DSP FIFO:_
- 256 Words
- 32 bits

- Insert Error/Status/Link#
- bits in link Header

- Dump events of specific
- type

- OR

- ValidData                1b

- HALTOUTPUT0  1b

- HALTOUTPUT1  1b

- HALTOUTPUT2  1b

- HALTOUTPUT3  1b

- SendData0              1b

- DSPDATA1          32b

- SendData1              1b

- DSPDATA2          32b

- SendData2              1b

- DSPDATA3          32b

- SendData3              1b

- HALTOUTPUT0  1b

- HALTOUTPUT1  1b

- HALTOUTPUT2  1b

- HALTOUTPUT3  1b

- Note: XCV200fg-5 2352 14              For 512 word DSP fifos we need the XCV300fg-5 3072 16

- _Comdensed Mode Register_

- _DSP0 Interface:_
- Configuredby DSP
-   to trap data by:
- 1 Event Type
- 2 L1ID3 ERROR Type

- _DSP1 Interface:_

- _DSP2 Interface:_

- _DSP3 Interface:_

## Model#2 Router: HeaderReplacer and DataDumper

- DirectorBUS     24b
- FIFO control Registers

- EvntFrgBldr WritingDATA   2b

- _Dump events of specific type:_

- ValidData              1b

- EventINFO       39b

- _Replace Header w/Link#:_

- Events                  32b

- EventINFO     32b

- CurrentLink#    5b

- EvntFrgBldr#   2b

- LinkNumberTranslator
- LookUpTable

- OverWriteHeader

- DumpEventsOfType                                    4b
- local                          sel    R/NW    Adr    Data

- Register Select Decoder & Read/Write Control

- RegTranferACK    1b

- DumpEventsOfTypeREG     4b

- EventINFO     32b

- Clock                                                         1b

- Clock                                1b

- R
- e
- g
- i
- s
- t
- e
- r

- R
- e
- g
- i
- s
- t
- e
- r

- Detect  Header | Trailer

- SeeHeader  1b

- SeeTrailer   1b

- _Dump Control_
- _ __StateMachine:_

- Detect and Compare  EventType

- DumpEvent   1b

## Model#2 Router: DSPInterface

- TrappedDATA0     32b

- WriteInAddress            ?b

- ReadOutAddress          ?b

- FIFOWriteEnable       1b

- FIFOOutputEnable     1b

- ClearWritePointer         1b

- ClearReadPointer           1b

- WriteInAddress     8b

- ReadOutAddress   8b

- NextWriteInAddress     1b

- NxtAdrs         Write In AdrCounter   log2QWDs
- ClrPointer                                WriteInAddress

- NxtAdrs        Read Out AdrCounter  log2QWDs
- ClrPointer                               ReadOutAddress

- NextReadoutAddress     1b

- Increment  FIFOOccupancy Counter log2QWDs
- Decrement                             OccupancyCount
- Reset

- FIFOOccupancyCount    8b

- ResetOccupancy           1b

- EventINFO                 32b

- DirectorBUS     24b
- FIFO control Registers

- EvntFrgBldr WritingDATA   2b

- _Trap Events of specific type:_

- DataTransferBlockSize                                 ?b
- local                          sel    R/NW    Adr    Data

- Register Select Decoder & Read/Write Control

- RegTranferACK              1b

- TrapEventsOfTypeREG         4b

- Clock                                     1b

- Detect  Header | Trailer

- SeeHeader  1b

- SeeTrailer   1b

- _Trap Control_
- _ __StateMachine:_

- Detect and Compare  EventType

- TrapEvent   1b

- _FifoBuffer_
- 256Words
- x32bits

- EnableOutput          1b

- DataBlockReadyToTransfer   1b

- >= comparator

- TrapEventsOfType+ResetTrap                    4b
- local

- DataTransferBlockSizeREG  ?b

- R
- e
- g
- i
- s
- t
- e
- r
- en

- R
- e
- g
- i
- s
- t
- e
- r
- en

- ClearWritePointer          1b

- ClearReadPointer           1b

- NextWriteInAddress      1b

- NextReadoutAddress     1b

- ResetOccupancy             1b

- ResetFifo     1b

- DSPDATA             32b

- FIFOWriteEnable           1b

- Reset                               1b

- ResetTrap                        4b

## Model #2: ROD Controller Functional Block Diagram

- _RodController_
- _DSPmodule:_      tms320c6201           SPI
- HPI
-                                                           EMI

- _Input FIFO:_

- _VMEbusIInterface:_

- _Output FIFO:_

- _TIMInterface:_

- RodStatusREG

- OutputFIFOWordCount

- VMECommandREG

- _FPGA Program Manager:_

- RodResourcesInterfaceProgramBits       1b

- RodResourcesInterfaceProgramBits        1b

- AFormattersProgramBits                         1b

- BFormattersProgramBits                         1b

- EventFragmentBuilderProgramBits        1b

- RouterProgramBits                                  1b

- EvntFrgBldrBUS                           16b

- FormatterBUS                               16b

- RouterBUS                                       8b

- BOCsetupBUS                                8b

- _busBuffer:_

- _busBuffer:_

- _busBuffer:_

- _busBuffer:_

- _busBuffer:_

- INMEM R/W & Control               32b

- FormtterTrailerInformation              12b

- FormtterDynamicMask                                                                             12b

- FECommandandConfiguration                                                                 48b

- EvntFrgBldrDynamicMask                                                                       16b

- _ControlREG,_
- _DebugMEM_
- _Interface:_

- _busBuffer:_

- DEBUGMEM R/W & Control      32b

- En,Dir

- En,Dir

- En,Dir

- En,Dir

- En,Dir

- En,Dir

- _FrontEnd Command Interface:_

- _FormatterDynamicMaskInterface:_

- _EvntFrgHeaderAndControlInterface:_

- _FrontEndOccupancyCounters:_

- TIM         8b

- _busBuffer:_

- _AddressDecoder:_

- _busBuffer:_

- _busBuffer:_

- _busBuffer:_

- BackEndDSP0                              16b

- BackEndDSP1                              16b

- BackEndDSP2                              16b

- BackEndDSP3                              16b

- _BOOT Strap:_
- PROM

- Interrupt   1b

- 16b

- 16b

- 16b

- 2b

- _DSP MEMORY:_
- 16Meg Bytes
- SDRAM

- Note: All bus size numbers indicate data bus size only, address and control signal have been omitted for clarity. XCV400fg-5 4800 20

- _busBuffer:_

- EVNTMEM R/W & Control         32b

- En,Dir

- L1triggerFormattersA,B                                                                            2b

## Model #2: BackEnd Slave DSP 1 of 4

- BackEndDSP[0..3]                       16b

- _BackEndSlaveDSP[0..3]_
- _DSPmodule:_      tms320c6701           SPI
- HPI                                                   EMI

- _Register:_

- _BOOT Strap:_
- PROM

- 32b

- _DSP MEMORY:_
- 16Meg Bytes
- SDRAM

- Note: Board resources are available for 4 DSP modules. Due to cost, only 2 are loaded.

- DSPDATA[0..3]     32b

- HALTOUTPUT0  1b

- SendData[0..3]         1b

- _Command_
- _MessageList_

## Model#2 RODController: Formatter and EFB Dynamic Mask Encoders

- TIM EventID             1b
- trigger headers
- from TIM

- TIM EventID                                                      16b
- EventTYPE| L1ID | BCID | DynamicMask | Link#
- to EventFragmentBuilder

- _Event Fragment Builder Header/Dynamic Mask Encoder_

- TIM EventTYPE       1b
- fast commands, trigger headers
- from TIM

- The TTC0-7 lines in the ROD TIM Interface document need the following
- changes (Lane).
-     TTC4  was 1 start bit + 24L1 ID bits + 12 BC ID bits (+trigger type)
-           should be 1 start bit + 24L1 ID bits + 12 BC ID bits
-     TTC5 was ROD Clear
-          Should be 1 start bit +8 trigger type bits.
-     TTC6 was unused
-          should be reserved for periodic reset.

- _TIM Event Packet to Event Fragment Builder_
- bit15                                                                                 bit0
- L1ID bits[15:0]--[15:0]
- TriggerType bits[7:0]--[15:8]           L1ID bits[23:16]--[7:0]
- BCID[11:0]--[15:4]   DetectorSpecificEventType[3:0--[3:0]
- DynamicMask for links [7:0]     2 bits/link
- DynamicMask for links [15:8]   2 bits/link
- DynamicMask for links [23:16] 2 bits/link
- DynamicMask for links [31:24] 2 bits/link
- DynamicMask for links [39:32] 2 bits/link
- DynamicMask for links [47:40] 2 bits/link
- DynamicMask for links [55:48] 2 bits/link
- DynamicMask for links [63:56] 2 bits/link
- DynamicMask for links [71:64] 2 bits/link
- DynamicMask for links [79:72] 2 bits/link
- DynamicMask for links [87:80] 2 bits/link
- DynamicMask for links [95:88] 2 bits/link

- FECommandPulse    1b

- _RodController Dynamic Mask to Event Fragment Builder_
- bit11                                                                                 bit0
- DynamicMask for links [11:0]   2 bits/link
- DynamicMask for links [23:12] 2 bits/link
- DynamicMask for links [35:24] 2 bits/link
- DynamicMask for links [47:36] 2 bits/link
- DynamicMask for links [59:48] 2 bits/link
- DynamicMask for links [71:60] 2 bits/link
- DynamicMask for links [83:72] 2 bits/link
- DynamicMask for links [95:84] 2 bits/link

- TIM TriggerInformation                                      12b
- ReadLink,SkipLink,ReadThrough
- to FormatterFifos

- _FromatterFifo /Dynamic Mask Encoder_

- FECommandPulse    1b

- FormatterDynamicMaskFifoWriteEnable[0..7]    8b

- OccupancyReadoutBUS             22b
- 16data+4adr+2ctrl

- OccupancyReadoutBUS             22b
- 16data+4adr+2ctrl

- L1triggerFormattersA,B                                       2b

- EFBDynamicMaskFifoWriteEnable[0..7]           8b

## Model#2 RODController: Front End Occupancy Counters

- ShowTrailerFLAGS0                             1b

- FormatterWritesTrailer                        12b

- .
- .

- ShowTrailerFLAGS7                             1b

- _FEmodule Trigger Controller0_

- FormatterWritesTrailer0,1      2b
-    Link0 FE 1/2moduleX 1of2
-    Link1 FE 1/2moduleX 2of2

- TriggerSetupBUS          22b
- 16data+4adr+3ctrl

- _DecoderWritesTrailer_
- _PulseDecoder 12b:96b_

- FormatterWritesTrailer[0..95]    96b

- _FEmodule Trigger Controller47_

- FormatterWritesTrailer 94,95  2b
-    Link0 FE 1/2moduleY 1of2
-    Link1 FE 1/2moduleY 2of2

- TriggerSetupBUS          22b
- 16data+4adr+3ctrl

- .
- .

- TriggerSetupBUS            26b
- 16data,7adr,3ctl

- FEOccupancyZero47        1b

- FEOccupancyZero0           1b

- FEOccupancyZero           1b

- .
- .

- FECommandPulse[0..47]   48b

- FECommandPulse0       1b

- FECommandPulse47      1b

## Model#2 RODController: FETrigger Counter

- _Comparator_ 4bits
- A                A=0

- Register Select Decoder & Read/Write Control

- _FEOccupancyCounter0_         4bits
- Increment
- Decrement                           Count

- _FEOccupancyCounter1_         4bits
- Increment
- Decrement                           Count
-              sel    R/NW    Adr     Data

- _Comparator_ 4bits
- A                A=0

- FEOccupancyZero0        1b

- CommandPulse                          1b

- DecrementOccupanyCount0      1b

- DecrementOccupanyCount1       1b

- OccupancyReadoutBUS             22b
- 16data+4adr+2ctrl

## Model#2 RODController: FETriggerCommands 

- CLK                             1b

- _FastCommandRegisterFile_
- _FastCommandShifter_
- SelectCommand             OUT

- REG
- 48

- TIMCommandPulses   4b
- TIM:TTC[0..3

- 1b

- MASK
- LOGIC
- 48
- mask

- FanOut
- 8:48

- 8b

- 48b

- REG
- 48

- FETrigCommand[0..47]  48b

- FECommandPulse[0..47] 48b

- FastNOTLongCommands  1b

- _LongCommand_
- _SyncronousSerialPort0_
- SelectCommand             CommandPulse
-                                        CommandStream

- 1b

- FanOut
- 1:8
- en
- load

- 8b

- 8b

- MASK
- LOGIC
- 48
- mask

- 48b

- _LongCommand_
- _SyncronousSerialPort1_
- SelectCommand             CommandPulse
-                                        CommandStream

- FanOut
- 1:8

- 8b

- 1b

- MASK
- LOGIC
- 48
- mask

- 48b

- FanOut
- 1:8

- 8b

- MASK
- LOGIC
- 48
- mask

- 48b

- FanOut
- 1:8

- 8b

- 1b

- Model#2 RODController: FETriggerCommands

- 1b

- 1b

- CLK

- CLK

- FanOut
- 8:48

- CLK

- FanOut
- 8:48

- FanOut
- 8:48

- CLK

- Mask0   48b

- Mask0   48b

- Mask1   48b

- Mask1   48b

- CLK

- CLK

- CLK

- Register Select Decoder & Read/Write Control

- _MASK0 Register_                 48bits

- _MASK1 Register _                48bits
-              sel    R/NW    Adr     Data

- TriggerSetupBUS                       22b
- 16data+4adr+2ctrl

- Mask1   48b

- Mask0   48b

- 1b

- CLK

- 8b

- CLK

- CLK

- FECommandPulse               1b