# Presentation: 853488

## DØ RunIIb Trigger Upgrade

**WBS 1.2**
**Darien Wood, Northeastern University****Hal Evans, Columbia University**

## Outline

**Trigger Strategies for Run IIb**
**Upgrade Design**
**Level 1**
**1.2.1 Calorimeter trigger**
**1.2.2: Cal-track matching**
**1.2.3: Track trigger**
**Level 2**
**1.2.5: Silicon Track Trigger upgrade**
**1.2.4: L2 Beta processors**
**Simulation & rates**
**Project Organization**
**Cost and Schedule**

## Run IIb Trigger Priorities

**Main physics driver for Run IIb: ****Higgs search**
**Need efficient triggers for Higgs production/decay in all major modes**
**Trigger objects:**
**Leptons**
**b-jets**
**taus**
**Missing E****T**
**SUSY**
**Trigger objects**
**Leptons**
**Missing E****T**** **
**taus**

**Top, W, Z**
**Trigger objects:**
**Leptons**
**Jets**
**Missing E****T**
**precision mass measurement to understand EWSB**
**Also important for background & calibration for Higgs search**
**Background/calibration channels **
** ****Z********bb, reduce top syst error x2**
**Some trigger load can be relieved by elimination of low-pt physics menu (lower energy QCD, b-physics, ...), but this is not sufficient.**

## The Run IIa Trigger System

**Level-1**
**Mainly single-detector-based**
**Correlations**
**Cal-Trk: quadrant level**
**Mu-Trk: L1trk info ******** L1Mu**
**Out rate ~5 kHz (r’dout time)**
**Level-2**
**Calibrated data**
**Extensive correlations**
**Physics objects out (e,********,********,j...)**
**Out rate < 1 kHz (cal r’dout)**

## Trigger Rates, w/o upgrade

**Core trigger menu, simulated at L=2e32, ********t=396 ns**

**Total L1 bandwidth = 5 kHz**

**Total rate****	****	****	**** ~30 kHz**

## Strategies for Trigger Upgrades

**Run efficient high-p****T**** trigger menu at L=2e32 @ 396 ns**
**allow headroom for running at L>2e32**
**allow capability of 132 ns operation**
**Increase trigger rejection at Level 1**
**1.2.1:**** L1 Calorimeter trigger upgrade to sharpen thresholds**
**1.2.2: ****Additional rejection from cal-track matching**
**1.2.3:**** L1 Tracking trigger upgrade to maintain rejection**
**Combat backgrounds at Level 2**
**1.2.4:**** L2 Processor upgrades ******** more complex algorithms possible**
**1.2.5:**** Expand Silicon Track Trigger (STT) for new silicon detector geometry**
**Upgrade/maintain DAQ/Online systems (see talk from S. Fuess)**** **

## WBS 1.2.1: Calorimeter Trigger Upgrade

**Digital Filtering of input signals**
**necessary for 132 ns operation**
**improves E****T**** estimate at all beam crossing rates**
**Jet/EM/tau clustering using ATLAS sliding-window algorithm**
**jets broader than 0.2x0.2 Trigger Towers (TT)**
**cluster topology cuts possible**

**WBS 1.2.1: **
**L3 managers: ****M. Abolins (MSU), ****H. Evans (Columbia), P. LeDu (Saclay)**

**Notes:**
Could also use block diagram from TTF.  This one is from Hal.

## Calorimeter Trigger Upgrade

**Calorimeter Trigger Upgrade**

**Sharpen thresholds by introducing EM, Jet clustering**

- Single tower

- Sliding window

- Sliding windowmean/rms = 0.2

- Single towermean/rms = 0.5

- Run IIa data

**Notes:**
Still need to add some captions to make it more clear.

## L1 Cal Design Progress

**L1 Cal:**
**ADF prototype design nearing completion**
**analog splitter board being fabricated to test Digital Filter and full system with real data**
**TAB prototype layout started**
**test boards for ADF-to-TAB cables being fabricated**

**Layout of input section of TAB**

## WBS 1.2.2: L1Cal-Track Trigger

**Exploit new L1Cal trigger**
**Improve Run IIa ******** matching granularity x8**
**Needed in triggers for Higgs searches**
**electrons in WH and H ********W*********W modes**
**taus in H ******** ********and H****+******
**Fake EM rejection is improved by ~x2**
**Fake ******** rejection is improved by ~x10**

**WBS 1.2.2: L3 manager: K. Johns (Arizona)**

## L1 Cal-track matching

**Uses same hardware as existing L1muon**
**modest cost and effort required**
**Design Progress:**
** ****detailed latency calculation for all system ******** OK**
**DØ pipeline depth to be increased for extra headroom**

## WBS 1.2.3: Level 1 Central Tracking Trigger (CTT)

**Level 1 Central Track Trigger (CTT) essential for electrons, muons, taus (WH********l********jj)**
**Tracking trigger rates sensitive to occupancy**
**Upgrade stategy:**
**Narrow tracker roads by using individual fiber hits (singlets) rather than pairing adjacent fibers (doublets)**
**Cal-track matching**

**WBS 1.2.3: L3 manager: M. Narain (Boston U.)**

## Run IIb L1CTT: Granularity

**Use full fiber resolution to restrict roads**

**Run IIa**

**Run IIb**

## Fake rate vs.luminosity

**Even at modest occupancies, the high-p****T**** single track trigger would fire at >15 kHZ**

**Green points = Run IIa CTT**
**Red points = Run IIb CTT**** **

## L1 CTT Implementation

**Digital Front End Axial (DFEA) daughter cards get replaced with new layout with larger FPGA’s (Xilinx Virtex-II XC2V6000)**
**Only 80 daughter cards get replaced; **
**rest of Run IIa system remains intact **
**Baseline algorithms compiled; occupy ~40% of the resources of the XC2V6000’s.**

**DFEA layout with new FPGA footprints**

## L1CTT Algorithm Results

**a(A) = inner superlayer,..., h(H) = outer superlayer**
**capital letter = doublet algorithm in that superlayer**
**FPGA resources = (# of equations) X (terms/equation)**

**Design progress: baseline algorithm chosen**
**extensive simulation ******** achieves performance goals**
**coded and compiled with FPGA tools (Synplify synthesizer) **

## L1: Additional features

**Muon triggers – No change needed to L1muon**
**but requires functioning  CTT trigger with <few% fakes**
**CTT upgrade allows higher muon p****T**** thresholds**
**Global calorimeter sums – better missing E****T**** with incorporation of intercryostat detector and massless gaps**
**EM shape and isolation – these cuts can be implemented in Level 1 after cluster finding, giving an additional factor of 2 rejection for electron & photon triggers**
**Topology – flexibility to require acoplanar jets, etc.**
**Flexibility: New clustering and tracking algorithms can be implemented with FPGA downloads**

## WBS 1.2.5: Silicon Track Trigger for Run IIb

**STT upgrade needed to accommodate new SMT geometry**
**SMT detector replacement: 6 axial barrel layers**
**Modest STT upgrade (5-layer readout) requires small quantity of same boards that are used in Run IIa. **

**Readout layers 0,1,2,3,5**

**WBS 1.2.5: L3 manager: U. Heintz (Boston U.)**

**Silicon Track Trigger (STT)**
**Run IIa STT available Fall 2002 (beyond the Run IIa baseline)**
**Vital for triggering on b-quarks**
**ZH********bb**
**Z********bb **
**b-jet energy scale, di-b-jet mass resolution**
**Improves track trigger**
**Sharper p****T**** turn-on**
**Reduced fake rate**

## Level2 STT Simulation

**65%**

## WBS 1.2.4: L2eta Upgrade

- 6U board

- Compact PCI

- 9U board

- 64 bit

- <2MHz

- VME

**FPGA**

**ECL Drivers**

*128 bits*

*~20 MHz*

*MBus*

*32 bits*

*66*

*MHz (max)*

*Local bus*

*64 bits*

*33 MHz*

*PCI*

- J1

- J2

- J3

- J5

- J4

**PLX**

**9656**

**UII**

**Drivers**

**Drivers**

- Clk

- (s)/

- roms

- In Run IIa, 24 beta processors replace existing Alpha processors
- installation in early 2003
- Add 12 additional processors for higher RunIIb luminosity
- processors only; use Run IIa adapter boards
- provide processing power (X 2-3 increase over RunIIa) needed to take advantage of the increased power at L1

**WBS 1.2.4: L3 manager: R. Hirosky (Virginia)**

## Trigger Simulations: Methods and Reality Checks

**Background rates: PYTHIA QCD Monte Carlo, plus Poisson distribution of PYTHIA min. bias events**
**Benchmarks with current data**
**Central Fiber Tracker occupancy vs. layer for real vs. simulated minimum bias**
**Calorimeter trigger rates at low luminosity for real vs. simulated QCD background**

## Trigger Rates

**Core trigger menu, simulated at L=2e32, ********t=396 ns**

**Total L1 bandwidth = 5 kHz**

**Total rate:                         ****	**** ~30 kHz    3.2 kHz**

**Additional headroom available from**
** ****topological cuts available in upgraded L1cal**
**Higher mu p****T**** threshold with upgraded CTT**

## Trigger upgrade:Limited scope

**Studied and eliminated several upgrade options in favor of lower schedule-risk and/or cost:**
**Level 1 stereo tracking**
**Preshower as 9****th**** tracking layer**
**Finer granularity of calorimeter towers (0.1x0.2)**
**6-layer Silicon Track Trigger**
** ****Use existing hardware (or minor modifications thereof) for new applications**
**Muon Trigger Cards for calorimeter-track matching**
**Existing DFE motherboards with daughter board replacement for tracking upgrade**
**Reuse L2Beta interface boards**
**Increase RunIIa STT production order to accommodate upgrade**

##  Trigger Upgrade Project

**Task Force Study:**** Summer 2001, DØ Trigger Task force studies upgrade options for trigger**
**Technical Design:**** **
**first draft TDR presented in April 2002**
**substantially revised to reflect significant process in developing detailed design, August 2002**
**Trigger Upgrade Project:**
**responsible institutions identified by January 2002**
**all WBS Level 3 managers in place by March 2002**
**Biweekly full group meetings, plus subproject meetings**
**Planning with fully resource-loaded schedule (341 tasks)**
**NSF MRI award:**** Trigger MRI submitted in January 2002, received in July 2002 **
**$456k + $113k matching for L1 tracking subproject**
**Complements ~$400k Saclay in-kind contribution for L1cal**
**Reviews:**** PAC (Oct 01, April 02), Technical Review Committee(Dec 01), Director’s Review Committee (April 02), DRC/TRC (August 02), DOE Baselining (Sept 02)**
**June 02 PAC recommends stage 1 approval**
**Sept 02 DOE recommends all D0 Trigger upgrades ready for baselining.**

## Trigger Upgrade Project Institutions

- Strong, active institutions
- Largely University-driven
- Combination of RunIIa experience and new ideas

- Engineering, technical and physicist manpower identified for delivering upgraded trigger
- Other institutions expressing interest

## M&S Cost Estimates ($k)

- (Detailed cost estimate provided to committee)

- FY02 k$
- total cost = 2,881 (+ contingency)

- Note: much of labor is covered by in-kind contributions from French laboratories ($587k) and  US Universities ($398k)

| Project | M&S equip | Labor | Total |
| --- | --- | --- | --- |
| WBS 1.2.1: L1 calorimeter | 457 | 947 | 1403 |
| WBS 1.2.2: L1 cal-track match | 177 | 77 | 254 |
| WBS 1.2.3: L1 tracking | 569 | 320 | 889 |
| WBS 1.2.4: L2 Beta | 49 | 44 | 93 |
| WBS 1.2.5: L2 STT | 172 | 63 | 235 |

## Baseline Schedule: Level 1

| project | Selected milestones |
| --- | --- |
| WBS 1.2.1: L1 calorimeter
ADF prototype shipped to Fermilab
TAB prototype complete
Production & Testing complete | 
11/03
7/03
1/06 |
| WBS 1.2.2: L1 cal-track match
Prototype MTFB complete
Production & Testing complete | 
6/03
9/04 |
| WBS 1.2.3: L1 tracking
Target FPGA algorithm coded
Prototype tested at Fermilab
Production & Testing complete
 | 
9/03
7/04
1/06
 |

- Detailed resource-loaded schedule included in material provided
- Installation begins after start of shutdown (3/30/06)

## Level 1 Schedule Sensitivity

| scenario | All production and testing complete | Trigger slippage (days) |
| --- | --- | --- |
| default | 1/10/06 | 0 |
| extra ADF prototype revision & test | 2/26/06 | 47 |
| extra TAB prototype revision & test | 4/4/06 | 84 |
| extra GAB prototype revision & test | 1/10/06 | 0 |
| double time for all in-situ and integration tests | 
2/6/06 | 
27 |
| 3rd prototype cycle for DFEAs | 5/3/06 | 113 |
| Cal-trk redesign after internal review | 1/10/06 | 0 |
| All of the above | 6/7/06 | 148 |

- Note: Shutdown period = 3/30/06 – 10/25/06
- All scenarios leave at least 4 months for installation and commissioning

## Baseline Schedule: Run IIb Level 2

| project | Milestone Date |
| --- | --- |
| WBS 1.2.4: L2 RunIIb beta
L2 beta prototype testing complete
L2 beta Production Complete | 
8/05
1/06 |
| WBS 1.2.5: L2 Run IIb STT
Place parts order
Production & Testing complete | 
4/03
10/05 |

- Detailed resource-loaded schedule included in material provided
- L2 beta processors could be ordered up to 2 years earlier—virtually no schedule risk

## Summary

**DØ trigger upgrade**
**preserves trigger capabilities for  critical physics processes at high-luminosity operation**
**Baseline design complete and documented in TDR**
**System design progressing rapidly**
**only modest design work necessary for several subsystems**
**prototypes expected in mid-2003 for other subsystems**
**Detailed schedule shows completion compatible with shutdown for installation of silicon detectors**
**Strong collaboration in place for prototyping, production, simulation, installation and commissioning**
**Much more technical detail available in breakout sessions**