# Presentation: 344254

## Monolithic Integration of Optoelectronic

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**Monolithic Integration of Optoelectronic**
**Devices with VLSI Electronics**
**- using reduced-temperature epitaxy and bonding**
- Prof. Clifton G. Fonstad
- MIT, Cambridge, MA, USA
- **************

- DOE Optical Interconnects for High Perfomance Computing Workshop (OIfHPC ‘99)

***Colleagues and Collaborators:***
- 	**Epi-on-Electronics:**  Joseph Ahadian, Dr. Aitor Postigo, Henry Choy, Sam Choy (U. Mass-Lowell, MIT Lincoln Lab), Prof. William Goodhue (U. Mass-Lowell, MIT Lincoln Lab), Prof. Sheila Prasad (Northeastern University)
- 	 **Aligned Pillar Bonding:**  Wojciech Giziewicz, Dr. Guiseppe Lullo, Hao Wang
- 	 **Silicon-on-Gallium Arsenide:**  Joanna London, Dr. Andrew Loomis (MIT Lincoln Lab) , Prof. Dimitri Antoniadis
- 	 **GaAs VLSI:**  Mr. Jim Mikkelson (Vitesse Semiconductor)

- **************

## Where I’m coming from:

**	****.... a good monolithic VLSI OEIC process,**
**	****.... and access to it for researchers**
**What we are doing about it is ....**
**	****.... working on 3 OEIC technologies:**
**	****	****1.  Epitaxy-on-Electronics (EoE)**
**	****	****2.  Silicon-on-Gallium Arsenide (SonG)**
**	****	****3.  Aligned Pillar Bonding (APB)**
**	****.... preparing OPTOCHIP-II research foundry:**
**	****     ****	****1.  H-GaAs IV electronics**
**	****	****2.  Lateral p-i-n detectors**
**	****	****3.  850 nm VCSEL sources (EoE or APB)**
**	****	****4.  SOS CMOS with APB’d VCSELs, and/or ****	****	****	****	****SonG CMOS with EoE VCSELs in future**

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**Where I’m coming from:**

## OEIC Applications:  Smart Pixel Arrays

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**OEIC Applications:  Smart Pixel Arrays**
- “computation, parallel processing of data and images, en/decryption”

**Smart pixel arrays**

**Diffractive element arrays**

**Light beams**

**OEIC**
**Pixel**

**DE Pixel**

- VCSEL
- array
- over a
- detector

**  ****Information **
**     ****transfers -**
- In-plane:  electrical
- Plane-to-plane:
- 	optical

- 3 x 3
- beam-
- steering
- hologram

**Concept:**
-   The plane-to-plane coupling pattern can be dynamically re-configured by selec-ting which VCSELs are illuminated.

## Very Large Scale Optoelectronic Integration

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**Very Large Scale Optoelectronic Integration**
- 	OBJECTIVES (our technology guidelines)

-  Our _goal_ is to make high performance, very large scale OEICs....
- 		...economical and cost competitive,
- 		...available and accessible, and
- 		...useful and important.

- 	Electronics:	VLSI densities and complexities
- 		State-of-the -art performance
- 		Standard design/layout/simulation tools
- 	Optoelectronics:	Unrestricted placement and quantities
- 		Uncompromised performance
- 	Processing:	Full-wafer processing
- 		Batch processing
- 		Standard, manufacturable processes

## Very Large Scale Optoelectronic Integration

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**Very Large Scale Optoelectronic Integration**
- 	 APPROACH (meeting our objectives)

-  The key elements in our _philosophy_ are...
- 	...to reap all the benefits of monolithic integration
- 	...to build on the investments of the Global IC industry
- 	...to eliminate or accomodate thermal expansion mismatch

- 	Exploit _monolithic integration_:	economics of scale
- 		low parasitics, high reliability and yield
- 		high densities, small device footprints
- 	Use a _commercial IC foundation_:	highly developed technologies
- 		state-of-the-art performance
- 		fully developed models and tools for
- 			simulation, design and layout
- 	Match _thermal expansion coefficients_:	full-wafer processiing
- 		reliable operation, long lifetimes

## Epitaxy-on-Electronics (EoE)

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**Epitaxy-on-Electronics (EoE)**

- Commercially processed GaAs electronics
- (circuitry custom-designed using standard layout and simulation tools; chips obtained through MOSIS
- Monolithic processing, high surface planarity, no excessive overcoating of optoelectronic devices
- All processing compatible with full-wafer and batch processing (no lattice or thermal expansion coefficient mismatch)
- Conventional growth and fabrication of optoelectronic devices
- (growth temperatures must be under 475ÞC)

## EoE-integrated P-i-N Diode/VCSEL Stack

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**EoE-integrated P-i-N Diode/VCSEL Stack**
- - array of top-emitting VCSELs over a bottom-input photodetector
- - illustrated on a GaAs MESFET DCFL integrated circuit

## How can we do EoE with Si electronics?

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**For many applications GaAs electronics is best, however...**
**for memory and microprocessor intensive applications Si CMOS is best**
**and for many people....Si CMOS is the*****only***** choice.**
**How can we do EoE with Si electronics?**
**_____________**

**__________**
**....Silicon-on-Gallium Arsenide (SonG)**

- 	**Observation #1:**	GaAs-on-Si has not worked because there is too much stress
- 	**Observation #2:**	Optoelectronic devices are intrinsically thick, but
- 			silicon MOSFETs are very thin.
- 	**Observation #3:****	**Thin materials can withstand large stresses,
- 			but thick materials can not.
- 	**The answer:**	Thin silicon and thick GaAs can work together in the
- 			spirit of SOI, and especially SOS (Si-on-sapphire),

**Note:**  The clearest proof that this can work is SOS (Si-on-sapphire.
- (The thermal expansion coeffiecient of GaAs equals that of sapphire.)

## Silicon-on-GaAs (SonG)

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**Silicon-on-GaAs (SonG)**
- providing CMOS substrates for EoE and APB

- GaAs substrate provided for inherently thick, strain-sensitive optoelectronic devices
- Silicon made no thicker than necessary to withstand stresses arising during high temperature processing steps
- Building on advances in MEMS, SOI, CMOS, and EoE
- Monolithic integration, full-wafer processing

## - Aligned Pillar Bonding -

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**- Aligned Pillar Bonding -**

**EoE has limitations **(whether on GaAs or SonG):
- 	*  The epitaxy conditions are not always optimal
- 	*  The substrate choice is not totally free; may not be optimal

- Thus we ask:
- 	**"How can we get the device heterostructures in dielectric****	****	****	****windows on ICs other than through epitaxy?"**
- and the obvious response is:  **"Wafer bonding"**
- 		Specifically...aligning and bonding pillars etched on a heterostructure
- 	wafer in the dielectric windows on a processed integrated circuit wafer
- 			**.****..ALIGNED PILLAR BONDING (APB)**

**Notes:**	*  The bonding temperature will be limited by the electronics.
- 	*  We must still match TECs, or we must bond at R.T. sufficiently to
- 		remove the substrate.
- 	*  The bonding must be uniform and complete on a very fine scale,
- 		and over the entire wafer.
- 	 *  APB can be done on silicon-on-sapphire (SOS) wafers also!

- ______________

## Aligned Pillar Bonding (APB)

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**Aligned Pillar Bonding (APB)**

- Optoelectronic heterostructures can be grown under optimal conditions on optimum substrates; bonded to GaAs or SOS
- All features of EoE process retained
- Near-room temperature bonding would enable integration of InP-based optoelectronics and silicon-based electronics

## APB-integrated P-i-N Diode/VCSEL Stack

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**APB-integrated P-i-N Diode/VCSEL Stack**
- - array of top-emitting VCSELs over a bottom-input photodetector
- - illustrated on a Silicon-on-Sapphire integrated circuit

## Monolithic Optoelectronic Integration

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**Monolithic Optoelectronic Integration**
- - options available with the MIT technologies -

-  comments

- GaAs MESFET VLSI

- SonG Si CMOS

- Aligned Pillar Bonding

- Epitaxy on Electronics

**Integration Processes:  **Epitaxy-on-Electronics or Aligned Pillar Bonding
- 			(illustrated using GaAs VLSI substrates)

**Electronic Circuitry:  **GaAs MESFET VLSI or SonG Si CMOS VLSI

## Monolithic Very Large Scale

- 	***Concept:***	Epitaxy on preprocessed electronics
- 	 ***Features:***	Full wafer, batch processing; monolithic integration; high planarity
- 	 ***Done:***	LED’s on OPTOCHIP and other chips; SEEDs, RTDs, PINs, also
- 	***Next:***	VCSELs and IPSELs now being grown, integrated
_**Silicon on Gallium Arsenide**_** (SonG)**
- 	 ***Concept:***	Si-CMOS foundation for EoE and APB
- 	 ***Features:***	Thin Si to take the stress; unstressed optoelectronics for survival
- 	 ***Done:***	Preparation by bonding and thinning of 4” SonG wafers
- 	 ***Next:***	Epitaxy on SonG substrates; planarized CMOS bonding
_**Aligned Pillar Bonding**_** (APB)**
- 	 ***Concept:***	Aligned, Pd-bonding of heterostructures replacing direct epitaxy
- 	***Features:***	Optimal growth conditions, optimum substrate, all EoE features
- 	***Done:***	Pillars aligned and transferred; small features Pd-bonded
- 	 ***Next:***	More aligned bonding; VCSELs on OPTOCHIP; pin’s on OEICs

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**The MIT processes for **
**Monolithic Very Large Scale**
**Optoelectronic Integration**

## Monolithic Integration of

- MIT Heterostructure Materials and Devices Group

- Professor Clifton G. Fonstad

- OIfHPC ‘99 - Nov. 8-9

**Looking further ahead:                               **
**Monolithic Integration of**
**CMOS, DCFL, and VCSELs**
- DCFL:  multi-Gbps signal processing
- CMOS:  memory, μ-processors
- VCSELs:  optical data transfer

-   Note:  Alternatively VCSEL layers can be EoE-grown directly into the device window on the bonded GaAs-CMOS wafer pair.

- SOI CMOS wafer (planarized)

- GaAs DCFL wafer (planarized)

- VCSEL wafer (partially processed)