# Presentation: 446276

## Low Noise Pulse Processing ASICs for Particle and Radiation Detectors

- RHIC collision

- P. O’Connor
- Instrumentation Division, Brookhaven National Lab

## Brookhaven National Laboratory

- Multipurpose federally-funded laboratory operated by US Dept. of Energy, Office of Science
- Builds and operates large/complex research facilities
*RHIC*
*NSLS*
*MRI & PET*
*TEM & STEM*
*Nanomaterials center*
- 3000 staff (800 scientists), 4000 guest researchers/year
- Long-term, high-risk research in
*High energy & condensed matter physics*
*Chemistry and biology*
*Environment and energy*
*Nuclear safeguards and nonproliferation*
- Technology transfer, industrial collaboration
- 5 Nobel prizes for work done at BNL

## User facilities

- Relativistic Heavy Ion Collider
*Accelerate gold ions to 200 GeV in intersecting rings*
*1760 superconducting magnets in 2.4 mile circumference*
*Study state of matter at extreme temperature and pressure*
*Deconfine quarks and gluons*
- Alternating Gradient Synchrotron
*World’s most powerful high energy proton source*
*Injector for RHIC since 2000*
- National Synchrotron Light Source
*2 electron storage rings which produce intense light from IR to X-ray*
*80 beamlines, 2500 users*
*Condensed matter physics, structural biology*
- Imaging and neuroscience center
*High-field MRI*
*Positron Emission Tomography (PET)*
*Nuclear medicine*
*Medical isotope production*

## A RHIC detector: PHENIX

- 4000 tons
- 13 detector subsystems
- 315,000 readout channels
- 500, 1.2 Gb/s optical links
- 13 custom ASICs
- 125 PCB designs

## Medical devices

-  3072 pixels
-  192 front-end ASICs
-  1.3M events/second
-  average FWHM 3.8% at 122keV

- 16 pixels 3 x 7 x 3 mm3
-  2 front-end ASICs
-  DEXA (Dual Energy X-ray Absorptiometry)
-  ASICs replaced 17 circuit boards (over 500 components) and improved performance

- Intra-operative probes

- Bone mineral densitometer

- solid-state gamma camera

## Radiation detection and measurement

- Radiation deposits energy in detecting medium
*gas, liquid, or solid*
- Deposited energy converted to electric current
*ionization charge motion in a drift field*
*scintillation light from excited atomic states directed into photodetector*
- Signal amplification
*controlled avalanche multiplication*
*electronic amplifier*
- Filtering to maximize signal to noise
*time domain*
- Feature extraction
*peak height*
*peak time*
*address of “hit” electrode*
- Data concentration and digitization
*sampling*
*multiplexing*
*zero suppression*

## Typical front-end channel

## Low noise charge amplification

- Voltage sensitive configuration

**V****s**

**A****V****>>1**

**V****s****(t)**

## Low noise charge amplification

- Current sensitive configuration

**V****s**

**Z****T ****>> 1**

**V****s****(t)**

- Non integrating
- Fast

## Low noise charge amplification

- Charge sensitive configuration (active integrator)

**A****V****>>1**

*Gain *_*insensitive*_* to C**det** and A**V*

## Amplifier series noise

- Comparison of voltage and charge sensitive configurations

**e****n**

**V****n,o**

**C****F**

**V****n,o**

|  | V-sens | Q-sens |
| --- | --- | --- |
| Vs |  |  |
| Vn,o |  |  |
| SNR |  |  |
| ENC |  |  |

- open-loop gain, Av
- bandwidth, B

## Single ended vs. differential amplification chain

- active preamp

- differential
- shaper

- Z?

- dummy preamp

- detector

- detector

-  low power
-  low noise
-  poor PSRR, coupled noise
-  nonzero baseline, drift
-  dynamic range limited in one polarity

-  2X power
-  2 X noise
-  improved PSRR
-  coupled noise rejection if Z? matches preamp + parasitics
-  zero baseline
-  dynamic range good in both polarities

## Transistor noise sources

- Drain/collector current and its fluctuation:

- in12

- D(C)

- S(E)

- G(B)

- Id (IC)

*White (thermal)  + 1/f (interface)*

- Ig (IB)

- in22

*White (shot)*

## Noise sources transformed to input

- D(C)

- S(E)

- G(B)

- Id (IC)

- Ig (IB)

- in22

- en2

- en2 = in12/gm2

## Noise sources for integrable devices

- Thermal – *Johnson (white) noise of channel incremental resistance:*
- 1/f (flicker) – *exchange of mobile carriers between channel and interface states*

*Compare typical JFET K**F** ~ 10**-27**J*
*PMOS devices have 3 - 30X lower 1/f noise than NMOS FETs*
*Weak dependence on bias conditions.*

## Input device comparison

- Bipolar junction transistor
*Highest gm/I*
*Low 1/f noise*
*High Ib makes it poor for high impedance sources*
*Superior device for fast shaping under power constraint*
- JFET
*Poor availability in VLSI processes*
*Lowest 1/f noise*
*Gate lengths > 3 um*
*Depletion mode*
- NMOS
*Most compatible with VLSI*
***** **30% worse than BJT*
*1/f noise  10 – 10**4** X worse than JFET*
- PMOS
*Similar to NMOS but:*
- gm/I ~ 3X poorer because of low hole mobility
- 1/f noise 3 – 10 X worse

## Equivalent input noise charge (ENC) for MOS

*amplifier with limited*
*bandwidth **BW** = t**m**-1*

*white*

*1/f*

- H(f)

-  ~ 2/3 – 1.0
*K**F* 1/f noise coefficient
*a1, a3* form factors

## Dimensioning the input MOSFET for minimum noise

- Choose minimum L for best *g**m**/C**gs* ratio
- Increasing M1 width makes *e**n* smaller while *C**gs* gets larger
-  optimum width for M1 must exist
- 1/f noise:
*C**gs,opt**  = C**det*
- White -- two cases :
- Fixed Vgs (fixed current density, fixed fT)
*g**m** **** C**gs*
***C******gs,opt******  = C******det***
- II. Fixed ID (practical case)
*g**m** **** C**gs**1/2*
*C**gs,opt**  = C**det**/3*

*white*

*1/f*

- P. O’Connor, G. De Geronimo, “Prospects for charge sensitive amplifiers in scaled CMOS”,
- NIM A480 (2002), 713 - 725

## Cdet = 3 pF
tm = 1 s
Pdiss = 1 mW
Ileak = 100 pA
Technology: 0.35 m NMOS

Optimum width for series noise is a compromise between white and 1/f components

*t**m* = 1 s
*P**diss** *= 1 mW
*I**leak** *= 100 pA
- Technology: 0.35 m NMOS
*Optimum width for series noise is a compromise between white and 1/f components*

*Min.*

- Composite noise

- thermal

**Notes:**
When we combine the white and 1/f noise components we can’t get a clean analytic solution to the optimization. We find the solution numerically by summing in quadrature the white, 1/f, and parallel noise contributions to the ENC. Here is an example The application scenario is ...
The 1/f match at c/c=1 as always. The white match is at about c/c=0.15, which means the device is just at the weak-strong inversion boundary. The overall optimum is about .3. Note also that the minima are rather broad, you could be in error by a factor of about 3 either way and only suffer a 40% increase in noise.

## Minimum series noise

- Input MOSFET fully optimized:
- Key ingredients for low series ENC:
*low C**det*
*long t**m*
*short ****el*
*low K**F*

**Notes:**
These expressions are same as Veljko’s save numerical constants dep. On weighting integrals, gamma, etc.
Allows to determine crudely if you wil be dominated by white or 1/f series noise. 
Recall kT/KF typically ~ 3000 for NMOS, 10,000 – 30,000 for PMOS. When tm < 1000 tel you are series noise limited. Can help NMOS/PMOS choice.

## Parallel noise

- From any noise current source connected to input:
*Detector biasing resistor*
*Shot noise of detector leakage current*
*Feedback resistor*

## Preamp reset – requirements

- all charge preamplifiers need DC feedback element to discharge the input node and stabilize the bias point
- usually, a resistor in the M – G range is used
- monolithic processes don’t have high value resistors
- we need a circuit that behaves like a high resistor and is also
*insensitive to process, temperature, and supply variation*
*low capacitance*
*lowest possible noise*
*linear*

**Notes:**
Linearity requirement varies with application. For some experiments signal dynamic range isn’t large and amplitude resolution can tolerate some nonlinearity.

## Preamp Reset with Nonlinear Pole-Zero Compensation

## Preamp reset with nonlinear PZ compensation – experimental results

- linearity

- output vs pixel leakage current

- G. De Geronimo, P. O’Connor, “A CMOS fully compensated reset system”,
- IEEE Transactions on Nuclear Science, Vol. 47, No. 4, Aug. 2000,1458-1462

## Limits the bandwidth for noise
Gives controlled pulse shape appropriate for rate
Control baseline fluctuations
Bring charge-to-voltage gain to its final value
By its saturation characteristics, sets upper limit on Qin
Feedback circuits give the most stable and precise shaping 
At the expense of power dissipation
Poor tolerance of passives limits accuracy of the poles and zeros
High-order shapers give the lowest noise for a given pulse width

- Gives controlled pulse shape appropriate for rate
- Control baseline fluctuations
- Bring charge-to-voltage gain to its final value
- By its saturation characteristics, sets upper limit on *Q**in*
- Feedback circuits give the most stable and precise shaping
*At the expense of power dissipation*
*Poor tolerance of passives limits accuracy of the poles and zeros*
- High-order shapers give the lowest noise for a given pulse width

- Filter topologies

- Integrated shaping amplifiers

## Practical amplifier considerations

- High order filters
- Programmable pulse parameters
- Circuit robustness:
- Self-biasing
- Low-swing,differential I/O
- Circuits tolerant to variations in
- Temperature
- Process
- Power supply
- DC leakage current
- Loading

**Peaking time variation**

- G. De Geronimo et al., “A generation of CMOS readout ASICs for CZT detectors", IEEE Trans. Nucl. Sci. 47, Dec. 2000, 1857 - 1867

## Scaling issues

- Fundamental device noise mechanisms
*Hot electron effects*
*New process steps effect on 1/f noise*
*Gate tunneling current*
- Change of the current-voltage characteristics
*Increase of weak inversion current*
*Mobility decrease*
*Velocity saturation*
*Drain conductance (device intrinsic DC gain)*
- Power supply scaling

## Scaling effects on key amplifier parameters

- Simplified predictive noise model to guide new front-end designs including:
-  NMOS, PMOS white and 1/f series noise
-  continuous transition from weak to strong inversion
-  mobility reduction and velocity saturation
-  output impedance degradation

- Results:
- Revised rules for optimum matching of input transistor to detector capacitance
- Noise/power tradeoff improves with scaling, especially for fast shaping
- Low supply voltage forces lower gain, reduces dynamic range below 0.5 m
- Limits foreseen for 0.1 m generation: gate tunneling leakage, poor amplifier gain

- Noise vs. power

- Dynamic range scaling

- CDET = 1 pF
- Shaping = 1 s

- CDET = 1 pF
- Shaping = 1 s

- P O'Connor and G. De GeronimoProspects for charge sensitive amplifiers in scaled CMOS
- NIM A480, 713 (Mar. 2002)

## Charge Amplifier based on Silicon MOSFET (1967)

- V. Negro et al., “A Guarded Insulated Gate Field Effect Electrometer”, IEEE Trnas. Nucl. Sci. Feb. 1967, 135 – 142
-  J.B. McCaslin, “A Metal-Oxide-Semiconductor Electrometer Ionization Chamber”, UCRL-11405 (1964)

## Spectroscopy amplifier (1989)

- Technology	3.0 m CMOS
- Power Supply	+/- 5V
- Chip size		2.5 x 2.5 mm
- Channels		1
*C**det*		300 - 1000 pF
- Reset		external resistor
- Shaping		CR-RC4, 1.6 s
- ENC		3800 + 4.1 e-/pF
- Power dissipation	96 mW
- Z. Chang, W. Sansen, *Low-Noise Wide-Band Amplifiers in Bipolar and CMOS Technologies*, Kluwer 1991 Ch. 5

## Preamp-shaper for cathode strip chamber

- Detector: cathode strips of 0.5m MWPC with 50 pF CDET
- Charge interpolation to 1/100 of the strip pitch
- Fast (70 ns), 7th order bipolar shaping for charged particle tracking in high rate environment

## Preamp-shaper for cathode strip chamber

## 384-channel X-ray fluorescence detector

- Goals:
*Energy resolution better than 300 eV FWHM *
*High x-ray flux (> 10 MHz)*
*High solid angle coverage*
*Highly integrated electronics*
*Peltier cooling*

- Sample

- Photodiode array sensor

- Si n-type high resistivity wafer 250μm thick,
- N = 384  p+ 1mm1mm pixels,

## ASIC channel overview

## charge preamplifier

- shaper with BLH

- discriminators and DACs

- counters

**ASIC photo**

## 96 channels (500,000 transistors)
Wirebonded to 96-channel cooled Si pad detector, 1 x 1 mm pads, 0.8 pF
1 cm2 circuit board replaces large rack-based system while delivering improved performance
270 eV FWHM (32 e- rms) at 10 kcounts/pad/s

- 96 channels (500,000 transistors)
- Wirebonded to 96-channel cooled Si pad detector, 1 x 1 mm pads, 0.8 pF
- 1 cm2 circuit board replaces large rack-based system while delivering improved performance
- 270 eV FWHM (32 e- rms) at 10 kcounts/pad/s

- Photon-counting ASIC for EXAFs

- Thresholds before and after DAC adjustment

## Slide 37

## ASIC overview

-  high order shaper
-  band-gap referenced output baseline
-  output baseline stabilizer (BLH)
-  test capacitors
-  analog and pixel leakage monitors
-  plug & play (fully self biasing)
-  serial interface
-  counters readout
-  gain / peaking-time setting
-  monitors & test enable
-  channel masking
-  DACs setting
-  token or chip-select mode

**ASIC overview**

| Technology | CMOS 0.35μm 3.3V 2P4M |
| --- | --- |
| Size |  3.6  6.3 mm2 |
| # MOSFETs |  180,000 |
| # Channels | 32 |
|    power / channel |  8 mW |
| # Discriminators | three / channel (1 thr., 2 win.) |
|    threshold adjustment | four 6-bit DACs (1.6mV step) |
|    threshold dispersion (adj) |  2.5 electrons rms |
| # Counters | three / channel |
|    bits per counter | 24 |
| Gain  (settable) | 750, 1500 mV/fC |
| Peaking time (settable) | 0.5, 1, 2, 4 μs |
| ENC @ 1μs |  14 + 12/pF electrons rms |
| ENC @ 4μs |  11 + 6/pF electrons rms |

## Data concentrating ASIC

## The two-phase peak detector concept

**Notes:**
Offset and CM voltages (both voltage dependent) are the same in the two phases

## Block diagram

- NCHAN = 32, NPD = 8
- Dual-mode TAC
- risetime
- time of occurrence
- Amplitude, address, time outputs
- 50 ns minimum pulsewidth
- tARB ~ 5 ns
- Rate capability ~ 10 MHz
- SPI interface:
- serial configuration of TAC gain and mode
- arbitration locking
- channel exclusion
- powerdown
- analog monitor
- Digital convenience outputs (used for configuring companion amplifier chip)
- FIFO-like control and readout interface

## Layout

- size : 3.2 x 3.2 mm2
- power : 2mW / channel
- technology: 0.35μm CMOS DP4M

## Slide 43

## Sampling and derandomization

**Black – Read Request**
**Blue – pulse input**
**Green – PD output**
**Red – TD output, occurrence time mode**

** ****12 pulses in 35 ********s**
**    ******** ****average rate 340 kHz**
** ****Readout rate 275 kHz**

## Summary

- New architecture for efficient readout of multichannel detectors
*Self-triggered and self-sparsifying*
*High efficiency at high concentration ratio*
*Rate capability improvement over present architectures*
- Based on new 2-phase peak detector combined with dual-mode TAC
*High absolute accuracy (0.2%) and linearity (0.05%), timing accuracy (5 ns)*
*Low power (2 mW per channel)*
- Experimental 32-channel chip demonstrated
*Accepts pulses down to 30 ns peaking time, 1.6 MHz rate per channel*
*Crosspoint switch and 8-event buffer for high efficiency*
*Simultaneous amplitude, time, and address measurement*

## BACKUPS

## Bias circuit for MF, low-Ileak detector

## White series ENC, CG,opt/CDET vs. CDET

- White series ENC, CG,opt/CDET vs. CDET

- Power allowed to scale with CDET:
- ENC ****** **CDET1/2

- De Geronimo et al. , NIM A 471 (2001) 192 - 199

- NMOS

- PMOS

**Notes:**
These next 2 slides show some noise and matching trends for the composite series noise. Here we’ve restricted ourselves to the case of 0.5um CMOS. 

## ENC vs. power and shaping time

- NMOS, 0.5 m technology