# Presentation: 223130

## CALGO Meeting

- CheckerBoard – Bus Error
- The reason
- The Fixing p14
- The next step

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## Reminder: BLS

- Figure taken from Run II CAL electronics TDR

**ADC raw****+****gain bit****+****L1 trigger**

- Trigger is unbiased with gain path

- The gainpath chosen
- is reported on a
- separate bus

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## Gain bit bus

- 4 wires transport in 2 seperate times
- First for tower 0 and 1
- Second for tower 2 and 3
- Each time is 7 bits of gain bit
- 3 bits for first tower (0 then 2)
- Checking bit to 1
- 3 bits for the second tower (1 then 3)
- In between : 7 bus dead times either
- Filled with well defined gain bit
- Or used for another purpose : random bit

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## First half of bls reading

| Information order | Wire 1 | Wire 2 | Wire 3 | Wire 4 |
| --- | --- | --- | --- | --- |
| Gain bit 1 | Tower 0 depth 0 | Tower 0 depth 0+1 | Tower 0 depth 0+2 | Tower 0 depth 0+3 |
| Dead time | Tower 0 depth 0 | Tower 0 depth 1 | Tower 0 depth 2 | Tower 0 depth 3 |
| Gain bit 2 | Tower 0 depth 4 | Tower 0 depth 4+1 | Tower 0 depth 4+2 | Tower 0 depth 4+3 |
| Dead time | Tower 0 depth 0 | Tower 0 depth 1 | Tower 0 depth 2 | Tower 0 depth 3 |
| Gain bit 3 | Tower 0 depth 8 | Tower 0 depth 8+1 | Tower 0 depth 8+2 | Tower 0 depth 8+3 |
| Dead time | Tower 0 depth 0 | Tower 0 depth 1 | Tower 0 depth 2 | Tower 0 depth 3 |
| Check bit 1 | 1 | 1 | 1 | 1 |
| Dead time | Tower 0 depth 0 | Tower 0 depth 1 | Tower 0 depth 2 | Tower 0 depth 3 |
| Gain bit 4 | Tower 1 depth 0 | Tower 1 depth 0+1 | Tower 1 depth 0+2 | Tower 1 depth 0+3 |
| Dead time | Tower 0 depth 0 | Tower 0 depth 1 | Tower 0 depth 2 | Tower 0 depth 3 |
| Gain bit 5 | Tower 1 depth 4 | Tower 1 depth 4+1 | Tower 1 depth 4+2 | Tower 1 depth 4+3 |
| Dead time | Tower 0 depth 0 | Tower 0 depth 1 | Tower 0 depth 2 | Tower 0 depth 3 |
| Gain bit 6 | Tower 1 depth 8 | Tower 1 depth 8+1 | Tower 1 depth 8+2 | Tower 1 depth 8+3 |
| Dead time | Tower 0 depth 0 | Tower 0 depth 1 | Tower 0 depth 2 | Tower 0 depth 3 |

- Gain bit copied to dead time

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## Second half of bls reading

| Information order | Wire 1 | Wire 2 | Wire 3 | Wire 4 |
| --- | --- | --- | --- | --- |
| Gain bit 1 | Tower 2 depth 0 | Tower 2 depth 0+1 | Tower 2 depth 0+2 | Tower 2 depth 0+3 |
| Dead time | Tower 3 depth 0 | Tower 3 depth 1 | Tower 3 depth 2 | Tower 3 depth 3 |
| Gain bit 2 | Tower 2 depth 4 | Tower 2 depth 4+1 | Tower 2 depth 4+2 | Tower 2 depth 4+3 |
| Dead time | Tower 3 depth 0 | Tower 3 depth 1 | Tower 3 depth 2 | Tower 3 depth 3 |
| Gain bit 3 | Tower 2 depth 8 | Tower 2 depth 8+1 | Tower 2 depth 8+2 | Tower 2 depth 8+3 |
| Dead time | Tower 3 depth 0 | Tower 3 depth 1 | Tower 3 depth 2 | Tower 3 depth 3 |
| Check bit 1 | 1 | 1 | 1 | 1 |
| Dead time | Tower 3 depth 0 | Tower 3 depth 1 | Tower 3 depth 2 | Tower 3 depth 3 |
| Gain bit 4 | Tower 3 depth 0 | Tower 3 depth 0+1 | Tower 3 depth 0+2 | Tower 3 depth 0+3 |
| Dead time | Tower 3 depth 0 | Tower 3 depth 1 | Tower 3 depth 2 | Tower 3 depth 3 |
| Gain bit 5 | Tower 3 depth 4 | Tower 3 depth 4+1 | Tower 3 depth 4+2 | Tower 3 depth 4+3 |
| Dead time | Tower 3 depth 0 | Tower 3 depth 1 | Tower 3 depth 2 | Tower 3 depth 3 |
| Gain bit 6 | Tower 3 depth 8 | Tower 3 depth 8+1 | Tower 3 depth 8+2 | Tower 3 depth 8+3 |
| Dead time | Tower 3 depth 0 | Tower 3 depth 1 | Tower 3 depth 2 | Tower 3 depth 3 |

- Gain bit copied to dead time

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## Reading errors

| Information order | Wire 1 |
| --- | --- |
| Gain bit 1 | Tower 0 depth 0 |
| Dead time | Tower 0 depth 0 |
| Gain bit 2 | Tower 0 depth 4 |
| Dead time | Tower 0 depth 0 |
| Gain bit 3 | Tower 0 depth 8 |
| Dead time | Tower 0 depth 0 |
| Check bit 1 | 1 |
| Dead time | Tower 0 depth 0 |
| Gain bit 4 | Tower 1 depth 0 |
| Dead time | Tower 0 depth 0 |
| Gain bit 5 | Tower 1 depth 4 |
| Dead time | Tower 0 depth 0 |
| Gain bit 6 | Tower 1 depth 8 |
| Dead time | Tower 0 depth 0 |

- Clock signal on another line
- Reading at falling edge
- Reference time can fluctuate
- Time for gain bit can fluctuate

- Sometimes reading is done in the dead time on
- The copied gain bit
- Or a « random » bit

- Correct and incorrect clock

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## Candidates to gain error

- Tower 0 and 1 reading
- Tower 0 depth (0,1,2,3) are « 99.98% » sure  ref
- Each other cell
- If gain bit is different form ref : this is the right gain
- If identical : there is a possibility of gain swaping
- Tower 2 and 3 reading
- Replace in the previous explanation tower 0 by tower 3

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## Correction at hardware level

| Information | Wire 1 |
| --- | --- |
| bit 1 | Tower 0 depth 0 |
| Dead time | Tower 0 depth 0 |
| bit 2 | Tower 0 depth 4 |
| Dead time | Tower 0 depth 0 |
| bit 3 | Tower 0 depth 8 |
| Dead time | Tower 0 depth 0 |
| Check bit 1 | 1 |
| Dead time | Tower 0 depth 0 |
| bit 4 | Tower 1 depth 0 |
| Dead time | Tower 0 depth 0 |
| bit 5 | Tower 1 depth 4 |
| Dead time | Tower 0 depth 0 |
| bit 6 | Tower 1 depth 8 |
| Dead time | Tower 0 depth 0 |

- Clock signal on another line
- Reading at falling edge
- Reference time re-adjusted
- Fluctuations do not misreport the gain anymore

- Fluctuation scale needed to read in the dead time are much more rare

- Old and corrected clock

- All gain path clock re-adjusted
- 12(crate)*12(ADC card)*4(wire) =576 wires checked one by one

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## Correction at raw level

- GAIN BIT AVAILABLE
- Tower (0,3) depth 0 always present
- Strategies to be thought of
- Numbers of actual gain bits swap back
- Shower shape consideration
- L1 guidance needed
- 		****** ****Can solve ****almost ****all**** gain report error**

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## Correction at thumbnail level

- Sum up L3 transverse energy in L1 trigger tower
- If difference is less than 4GeV , then do nothing
- If not, then change the gain factor of one cell so that |L1-L3| is minimum
- We do not have the actual gain for each cell
- Gain Guessing
- Give confidence to L1 : if not saturated (L3<60 GeV)
- All towers can be affected
- Only these regions
- ieta<-7 and iphi16 (main checker board location)
- ieta<-16 and 41  iphi  44
- ieta<-20 and 47  iphi  48
- -12  ieta  -1 and 43  iphi  48

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## Location of troubles

- L1-L3 Et>15GeV
- 89k entries
- Gain 8 instead of 1

- L1-L3 Et<-15GeV
- 12k entries
- Gain 1 instead of 8 (previous slide configuration)

- EM layersL1<59GeV

**Mostly tower 1 and 2**

**Uniform tower distribution**

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant

## Summary

- Hardware has been fixed and checked
- No more crap in Raw data from now on
- Raw level fixer is being thought off
- Efficiency ? Expected as very good
- Goal is p17 ? Feasable at unpacker level
- A quick fixer has already been released for p14 data reprocessing
- No gain guessing, swap back one cell to macth L1, not paying much attention to gain bit correlations.

- Dean Schamberger, Jan Stark, Jean-Roch Vlimant