# Presentation: 401785

## Status of HFT 

- Wieman
- RNC
- LBNL
- HFT workshop
- LBNL
- Fri 14 October 2005

## Status Report

- IReS Pixel Chips
- Ladder readout
- DAQ developments
- Ladder mechanical development
- Reduced mechanical scope
- Beam pipe
- Future fast pixels

**Meet the 2008 Au + Au challenge and the 2014 high luminosity challenge**

## IReS MIMOSTAR chips 

- MIMOSTAR1 (0.25 m TSMC)
- Reduced size prototype but sophisticated chip with complete functions for operation in a real detector system
- Everything operating except pixel signal because of 0.25 m TSMC feature:  Unexpected short signal decay time compared to theory and AMS experience.
- MIMOSTAR2(0.35 m AMS optical process)
- Just back from the foundry
- First word from IReS, it works perfectly.

## Readout system

- Emphasis on early delivery, i.e. off ladder ADC approach
- Not enough time to develop piggy back readout chip for 2008 running
- Excellent recent progress in solving the technical problem of fast cable readout
- A product of close communication with IReS – a SPICE model dialogue
- An outgrowth of the prototype ladder using MIMOSA5 chips, the work of:
- Bieser, Greiner, Gareus and Kushpil

## Spice model for ladder cable

**Manufactures provide models of their products**

**100 MHz analogue OK**

## SPICE dialogue

## Readout/DAQ

**Based on SIU/RORC connection**
**Tonko Ljubicic **
**solution for both TOF and new TPC electronics**

**HFT data to fit into STAR data stream like any other detector **
**A reduction in scope from previous plans to achieve early implementation with current man power.**

## Mechanical Ladder Development

- Refining construction and bonding of light weight structures
- Testing for stability and flatness

**100 ********m**

## STAR Micro Vertex Detector

- Full self consistent spatial mapping prior to installation
- Installation and removal does not disturb mapping

## Conceptual mechanical design

## Full  = 2 concept

**Full ******** = 2******** concept**

**In the interest of early deployment, simplify interconnecting mechanics by reducing to one module with ******** = 2******** /3**
**What is the physics price?**

## Beam pipe

- Meetings and discussions with
- Wolfram Fisher
- Dick Hseuh
- Robert Pak
- Dan Weiss
- Our beam radius OK for accelerator, but we are a limiting aperture
- Accelerator can live with 10-5 (we expect 10-9, but what can we live with?)
- PHENIX has adopted our 1.5 cm radius, 0.5mm wall.
- Preferred bake out 200-250 C to activate NEG coating

## Next generation fast APS detector - good for 2014

- Submitted requirements list to IReS.  They will provide estimates for building

**Candidate  Technology MIMOSA8**

| Ladder active area | 2cm  20cm |
| --- | --- |
| Pixel size | 30m  30m |
| ~Pixel mapping on the ladder | 640  6400 |
| Minimum operating distance from beam | 1.5 cm |
| Power | 100 mW/cm2 |
| Operating temperature | 30 C |
| Integration time[1] | 0.2 ms |
| Mean silicon thickness | 100m |
| Readout time | 1 ms |
| Efficiency (min I)[2] | 98% |
| Accidental cluster density | 50/cm2 |
| Binary readout, number of threshold bits[3] | 1 or 2 |
| Radiation tolerance [4] | 124 kRad |
| Number of conductors supporting the ladder (10 chips/ladder)[5] | 140 |
| Triggered readout, maximum trigger delay[6] | 2 s |