# Presentation: 349360

## The Intrinsic Stability of Polycrystalline Thin Film Devices 

**D. Albin, T. Berniard, T. McMahon, R. Noufi**
***National Renewable Energy Laboratory***

**S. Demtsu**
***Colorado State University***

**Disclaimer and Government License**
- This work has been authored by Midwest Research Institute (MRI) under Contract No. DE-AC36-99GO10337 with the U.S. Department of Energy (the “DOE”).  The United States Government (the “Government”) retains and the publisher, by accepting the work for publication, acknowledges that the Government retains a non-exclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this work, or allow others to do so, for Government purposes.
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## Acknowledgments

- National Team members
- First Solar, Canrom, BP-Solar, Shell Solar
- Institute of Energy Conversion, Florida Solar Energy Center
- Colorado State Univ., Univ. of S. Florida, Univ. of Toledo, Colorado School of Mines
- A. Fahrenbruch
- NREL
- Polycrystalline Thin Film Group (K. Ramanathan, M. Contreras, R. Bhattacharya, Z. Wu)
- Characterization (S. Asher, J. Pankow)
- Reliability (J. Pern, S. Glick, G. Jorgensen)

## Systems Driven Approach

**Systems Driven Approach**

## Core Data Analysis Backbone for Device-Level Stability Research

## FY04 Results to be Discussed

- Removal of “extrinsic” shunt degradation mechanism in CdTe
- new design resulted in about a 60% improvement in stability achieving an efficiency stabilized (ESDL) degradation level of 20%
- Improvement of “intrinsic” stability in CdTe
- thin CdS prone to instability
- balancing of initial performance and stability
- brief summary of results; to be published in IEEE
- Application of discrete diode models towards understanding edge-related shunting (Karpov, et al.)
- Side-by-side comparison of CdTe and CIGS device stability

## Initial Degradation Studies “noisy”

- hard to correlate stability with processing given this kind of statistical variation
- Makes predicting service-life difficult
- Differences in Degradation appear to be shunt-related

*Initial Degradation Studies “noisy”*

## Mitigation of “Extrinsic” Shunt Degradation

*Mitigation of “Extrinsic” Shunt Degradation*

- “catastrophic” degradation insidious; hard to predict; occurred in ~10% of devices
- “margined” structure all but eliminates shunting in standard processing; greatly improved statistics
- “margined” structure shows a “stabilized” efficiency, in this case an ESDL of about 20%

**Notes:**
Also mention possible ramifications to modules
Sensitivity of non-margined cells to humidity

## Optimization of “Intrinsic” Stability

- 3x2x2x2 Orthogonal Design
- CdS thickness (34,37,41m)
- CdTe thickness (8,11 um)
- v-CdCl2 ambient (0,100 Torr O2)
- With and Without NP etch
- 2 replicates (48 Devices)
- Measured Initial Performance and Performance vs. Stress Time (Voc-1 Sun-100C)
- Generated Least-Squares Model
- Model well-correlated; predicted and actual responses well-aligned

## Optimization of “Intrinsic” Stability

- Next dominating effect was CdS window layer thickness; thicker is better
- Thinner CdS prone to again “catastrophic” failure; excessive shunting possibly through bulk of film

*Optimization of “Intrinsic” Stability*

## Optimization of “Intrinsic” Stability

- Effect of oxygen appears to be dependent upon both the CdS window layer thickness and whether the CdTe surface is treated with NP etch.
- Highest efficiency devices obtained with thin CdS exhibited least stability
- Same devices but with thicker CdS exhibited modest drop in performance (12.912.6%) and significant improvement in stability (50%  15% degradation)

*Optimization of “Intrinsic” Stability*

## Optimization of “Intrinsic” Stability

- “off-normal” processing, e.g., use of thinner CdS window layers still exhibited these tendencies
- latter mechanisms may be bulk related rather than edge
- Results of this optimization for “intrinsic” effects yielded ESDL of <10% while still maintaining high initial performance.

*Optimization of “Intrinsic” Stability*

## Pspice “discrete diode” modeling of edge-related shunts

*Pspice “discrete diode” modeling of edge-related shunts*

## Pspice “discrete diode” modeling of edge-related shunts

*IR Thermography (+1.2V, 6.0 mA)*

- “hot spot”

*Pspice “discrete diode” modeling of edge-related shunts*

## Pspice “discrete diode” modeling of edge-related shunts

*IR Thermography (+1.2V, 6.0 mA)*

*Pspice “discrete diode” modeling of edge-related shunts*

## Side-by-Side Comparison of CdTe and CIGS device stability

*Side-by-Side Comparison of CdTe and CIGS device stability*

- Stress conditions: Voc bias, 85C, 1 Sun (t = 521 hrs)
- Only a select group shown (concerns regarding use of 85C as a stress temperature)
- CdTe cells are margined but not optimized (i.e., “std” cells)
- Again, ESDL of <10% for CdTe have been achieved
- CIGS devices include those from (2) different sources
- Transients handled by simple dark soak (12-24 hrs) at ~25C

- %change (521 hrs)

## FY04 Summary

- Efficient system for stress testing polycrystalline thin film devices completed
- “extrinsic” degradation removed by improved device (margined) structure resulting in an ESDL of ~20%
- “intrinsic” degradation further reduced to ESDL ~10% using experimental process optimization techniques
- Presence of Te, CdS window layer thickness determined as key factors affecting stability
- Discrete-diode approach (Karpov, et al.) found useful for understanding edge-related shunting
- side-by-side comparison:  CIGS quite stable (dry); CdTe has a little catching up to do