# Presentation: 211659

**DØ  Collaboration**

- October  2000

- 2000 IEEE
- NUCLEAR SCIENCE SYMPOSIUM
- and MEDICAL IMAGING CONFERENCE
- Lyon, France    October 15-20, 2000

## Fermilab Accelerator Upgrade

**Two new machines at FNAL for Run II:**
**Main Injector**
**150 GeV conventional proton accelerator**
**Supports luminosity upgrade for the collider, future 120 GeV fixed-target program, and neutrino production for NUMI **
**Recycler**
**8 GeV permanent magnet (monoenergetic) storage ring**
**permits antiproton recycling from the collider**
**Tevatron Status and Schedule**
**DØ and CDF roll in – January 2001**
**Run II start              – March 2001**
**1.8 Tev ******** 2 TeV**
**Goal: ********L *****dt***** = 2 fb****-1      ****by 2003**
**                         ****15 fb****-1****+ by 2006?**
**Very first p-pbar collisions seen (August 2000)**

## Run II Parameters

## Timing

**3.56us**

**4.36us**

**2.64us**

**superbunch**

**gap**

**396ns**

**gap used to form trigger**
**and sample baselines**

**this gap is too small to**
**form trigger and sample**
**baseline**

**Bunch structure**

- Run I    6x6

- Run II 36x36

**Design all the electronics, triggers and DAQ to handle bunch structure with a minimum of 132ns between bunches and higher luminosity**
**Maintain detector performance**

## Calorimeter Readout Electronics

**Objectives **
**Accommodate reduced minimum bunch spacing from 3.5 ********s to 396 ns or 132 ns and ****L****~ 2 x 10****32**** cm****-2 ****s****-1**
**Storage of analog signal for 4 ********s for L1 trigger formation**
**Generate trigger signals for calorimeter L1 trigger**
**Maintain present level of noise performance and pile-up performance**
**Methods**
**Replace preamplifiers**
**Replace shapers**
**Add analog storage**
**Replace calibration system**
**Replace timing and control system**
**Keep Run I ADCs, crates and most cabling to minimize cost and time**

## Calorimeter Electronics Upgrade

**Calorimeter Electronics Upgrade**

**55K readout channels**
**Replace signal cables from cryostat to preamps (110******** ******** 30******** for impedance match)**
**Replacement of preamps, shapers, baseline subtraction circuitry (BLS)**
**Addition of analog storage (48-element deep Switched Capacitor Array (SCA))**
**New Timing and Control**
**New calibration pulser + current cables**

**Preamp/**
**Driver**

**Trig. sum**

**Filter/**
**Shaper**

**x1**

**x8**

**SCA (48 deep)**

**SCA (48 deep)**

**SCA (48 deep)**

**SCA (48 deep)**

**BLS**

**Output**
**Buffer**

**Detc.**

**Bank 0**

**Bank 1**

**Replace cables**
**for impedence**
**match**

**new low noise **
**preamp & driver**

**Shorter **
**shaping**
**~400ns**

**SCA analog storage**
**>4********sec, alternate**

**Additional**
**buffering for L2 & L3**

**SCA**

**new calibrated**
**pulse injection**

- BLS Card

**Notes:**
Analog delay required to pipeline signal until trigger is formed
Shorter shaping time required to reduce pile-up
400ns matches drift time in the Lar and initial beam crossing time
Replace cables to match those in cryostat
prevent reflections
 lengths matched to minimize error in signal timing (around 300-500 inches total)

## Preamplifier

**FET**

**driver**

**preamp**

- similar to Run 1 version except
-  Dual FET frontend
-  Compensation for detector
-    capacitance
-  Faster recovery time

- New output driver
- for terminated
- signal transmission

**New calorimeter preamp**
**Hybrid on ceramic**
**48 preamps on a motherboard**
**New low-noise switching power supplies in steel box**

**Notes:**
Charge integrating preamplifier
high DC open-loop gain; High DC input impedance; Low input bias current; Low noise; High linearity
Additional requirements
Increased noise therefore use two input jFETs
Sensitive to reflections at BLS input therefore preamp output terminated and back-terminated
Driver stages added for gain to compensate for termination, current drive capability and differential output capability
Sensitive to RC time constant introduced by detector capacitance and cable impedance  cancel the effect with appropriate peaking circuit in preamp first stage
Sensitive to reflections at preamp input  tune preamp open loop gain to maintain 30ohm impedance
Motherboard
8-layer printed circuit board: noise and cross-talk minimized with
Ground or power planes of solid copper separating buried signal planes
Grounded copper pour around signal traces
RC filter on power lines with 1⁄4 ohm resistors and three caps. (150uF,4.7uF and 0.1uF) to attenuate high and low frequency ripple (high frequency caps. On both ends of the board)
All components surface-mounted to prevent high freq. Radiation and pick up from lead ends
Capacitance of all calibration pulser signal traces equalized
Dual-row of pins on preamp connectors for better mechanical stability
Keying pins to ensure preamps are correctly mounted
Preamp power dissipation 80mW (Run 1)  280 mW (Run II)
More efficient switching supplies to be used, noise performance good
Require magnetic shielding

## Preamp Species

**14+1 (ICD) species of preamp **
**Feedback provide compensation for RC from detector capacitance and cable impedance**
**Readout in towers of up to 12 layers**
**0:EM1, 1:EM2, 2-5:EM3, 6:EM4, 7-10:FH, 11:CH**
**4 towers per preamp motherboard provides trigger tower (EM+ HAD) of **x **0.2 x 0.2**

| Preamp species | Avg. Detector cap. (nF) | Layer readout | Feedback cap (pF) | RC 
(ns) | Total preamps |
| --- | --- | --- | --- | --- | --- |
| A | 0.26-0.56 | EM1,2, HAD | 5 | 0 | 13376 |
| B | 1.1-1.5 | HAD | 5 | 26 | 2240 |
| C | 1.8-2.6 | HAD | 5 | 53 | 11008 |
| D | 3.4-4.6 | HAD | 5 | 109 | 8912 |
| E | 0.36-0.44 | CC EM3 | 10 | 0 | 9920 |
| F | 0.72-1.04 | EC EM3,4 | 10 | 14 | 7712 |
| G | 1.3-1.7 | CC EM4, EC EM3,4 | 10 | 32 | 3232 |
| Ha-Hg | 2- 4 | EC EM3,4 | 10 | 47-110 | 896 |
| I | —    | ICD | 22 | 0 | 384 |
|  |  |  |  |  | 55680 |

**Notes:**
Equal compensation
The integrating feedback cap is replaced with an RC circuit, which partially differentiates the output.
This counteracts the partial integration performed by the detector RC network (det. cap. plus cable impedance), giving the desired output of the original charge deposited in the detector.  Different caps in different parts of detector, hence different RC.
The open loop gain adjusting RC circuit helps pull out charge from det faster than the RC det network would otherwise allow

## BLS Card

**L1 SCAs (2+2)    L2 SCA**
**Array of 48 capacitors to**
**pipeline calorimeter signals**

**BLS Card**

**BLS motherboard v2.2**

**BLS daughterboard**

**Shapers (12)**

**Use 2 L1 SCA chips for each x1/x8 gain                        - alternate read/write for each superbunch**
**Readout time ~ 6 ********s (< length SCA buffer)**
**L2 SCA buffers readout for transfer to ADC after L2 trigger decision**
**No dead time for 10KHz L1 trigger rate**
**Trigger tower formation (0.2 x 0.2) for L1**
**Rework existing power supplies**
**New T&C signals to handle SCA requirements and interface to L1/L2 trigger system( use FPGAs and FIFOs)**

**Output**
**circuit**

**Trigger pickoff/summers**

**~ 1 inch**

**shaper**

**Notes:**
Shaping – symmetric unipolar signal

12-bit accuracy, 15-bit dynamic range needed
SCA only 12 bit (1/4000) hence need 2 pipelines (high + low gain)
To minimize deadtime and have a long enough pipe, use 2-dual pipeline SCAs

## SCA

**Designed by LBL, FNAL, SUNY Stony Brook (25k in system)**
**Not designed for simultaneous read and write operations**
**two SCA banks alternate reading and writing**
**12 bit dynamic range (1/4000)**
**low and high gain path for each readout channel (X8/X1)**
**maintain 15 bit dynamic range**

**cap ref**

**input**

- packaged

## Preamp signal shape

**return to zero by about 1.2********s**
**Sample at 320ns**
**Mostly insensitive to 396 ns or 132 ns running**
**BLS-Finite time difference is measured**
**Uses three samples earlier**
**Pile-up**

**Preamp output is integral of detector signal**
**rise time > 430ns**
**recovery time 15********s**
**To minimize the effects of pileup, only use 2/3 of the charge in the detector**
**Shaped signal sampled every seven RF buckets (132ns)**
**peak at about 300ns**

**After shaper**

**Signal from preamp**

**0**

**400**

**1200**

**800**

**ns**

**amplitude**

**320 ns**

**Detector signal**

**Notes:**
Because the signal is faster, we need to adjust the sampling relative to the beam to a much higher precision.
Because the peak value will also be used as the baseline for a different bunch, signals uncorrelated to the accelerator clock average exactly to zero.
Energy which is uncorrelated to the trigger, but in synch with the beam will approximately average to zero.  Except for the first few in each superbunch.

As the recovery time of the shaped signal is about 1.2s, the bunches in the beginning of each superbunch will be slightly different from later bunches.
This effect is essentially independent of 396ns or 132ns running because the shaping time chosen.
Following the L1 decision, the reading with appropriate gain factor and relevant baseline 
subtracted is passed to L2 SCA (also analog)

Full scale Energy (not E_t) per cell
approx 100 GeV
except of EM 3-4 where it is approx 200 GeV
same as run 1....but
Linearity
First look is hopeful, but may still require more than the three numbers/channel used in run 1

## Noise Contributions

**Design for**
**400ns shaping**
**lower noise – 2 FET input**
**luminosity of 2x10****32 ****cm****–2**** s****-1**** **
**Re-optimized**** ****three contributions **
**Electronics noise: ******** x 1.6**
****** ****shaping time (2********s ******** 400ns) (~******** t)**
****** ****lower noise preamp (2 FET)  (~ 1/******** 2)**
**Uranium noise: ******** x 2.3**
****** ****shorter shaping time (~ ******** t)**
**Pile-up noise: ******** x 1.3**
****** ****luminosity (~ ******** L)**
****** ****shorter shaping times (~ ******** t)**
**Comparable noise performance at 10****32**** with new electronics as with old electronics at 10****31**
**Simulations of the  W mass “bench-mark” confirm that pile-up  will not limit our W mass at Run II.**

**Notes:**
Run 1
Electronic noise (rms): 4 MeV EM, 36 MeV FH
Ur noise: 7 MeV EM, 62 MeV FH
Elec. + Ur noise (rms): 8 MeV EM, 72 MeV FH

## Estimates of Noise Contributions

**Estimates of Noise Contributions**

**EM3 layer per cell**

****

**nF**

**GeV**

**GeV**

**GeV**

## Electronics Calibration

**Goals**
**Calibrate electronics to better than 1%**
**Measure pedestals due to electronics and Ur noise**
**Determine zero suppression limits**
**Determine gains (x1,x8) from pulsed channels**
**Study channel-to-channel response; linearity**
**Commissioning**
**Bad channels**
**Trigger verification**
**Check channel mapping**
**Monitoring tool**
**Oracle Database for storage**
**Database used to download pedestals and zero-suppression limits to ADC boards**

## Electronics Calibration System

- Preamp
**Box**

**2 Fanouts**
**(2x3x16 switches****)**

-  switch

**Electronics Calibration System**

- Pulser

- Trigger

- Power Supply

**6 commands (3x2)**
**96 currents**

**Pulser Interface Board:**
** **VME interface
-  automated calibration procedure

**Active Fanout with Switches: **
- pulse shaping and distribution
-  Open switch when receive command signal

**Pulser: DC current and command generator:**
** **DC current set by 18-bit DAC
-  96 enable registers
-  6-programmable 8-bit delays for command signals with 2ns step size

**LPNHE-Paris**
**LAL-Orsay**

## Calibration Pulser Response

**Calibration Pulser Response**

**Linear response for DAC pulse height (0-65k)**
**Fully saturate  ADC **
**    ****(at DAC= 90k)**

**Linearity of calibration and calorimeter electronics better than 0.2% (for DAC < 65k)**
**Cross-talk in neighboring channels < 1.5%**
**Uniformity of pulser modules better than 1% **
**No significant noise added from the calibration system**
**Correction factors need to be determined**

- 

- mean

- Deviation from linearity

- Single channel (ADC vs. DAC)

- better than 0.2%

## Pulser Signal Shapes

**Calorimeter Signal at Preamp Input**

**Calibration Signal at Preamp Input**

**Calorimeter Signal after Preamp and Shaper**

**Calibration Signal after Preamp and Shaper**

**400ns**

**400ns**

**400ns**

**400ns**

- Response of calorimeter signal w.r.t. calibration signal <1% at max. signal for variation of different parameters (cable length, Zpreamp, Zcable,...)
- No test beam running  absolute energy scale will have to be established from the data
- Maximum response time for EM and hadronic channels differ due to different preamp types.  Use delays and modeling to accommodate these
- Correct pulser response for different timings and shape
- Use initial “guess” based on Monte-Carlo sampling weights and Spice models of the electronics.

- Signal reflection

## Conclusions

**Dzero is upgrading its detector**
**L.Argon calorimeter untouched**
**Harder machine conditions and new environment (solenoid) **
**New Calorimeter Electronics**
**Improved ICD**
**New Central and Forward Preshower**
**      ****Similar  performance with 20x more data**
**Run II start in 6 months **
**          **

**Notes:**
All systems are designed to run at high luminosity (2*1032) and reduced bunch spacing (132ns)