# Presentation: 401783

## STAR Vertex Detector Upgrade –HFT PIXEL Development

*Outline:*
*Heavy Flavor Tracker at STAR*
*PIXEL detector as part of HFT*
*PIXEL detector requirements*
*Low mass detector design*
*Sensor development for PIXEL*
*Readout system development*
*Prototyping results and outlook*

*Michal Szelezniak*
*on behalf of LBNL RNC group*

## Extend the physics reach of the STAR experiment for precision measurement of the yields and spectra of particles containing heavy quarks:
Study charm and beauty energy losses to test pQCD in a hot and dense medium at RHIC 
Charm flow to test thermalization at RHIC
Direct reconstruction of charm decays with small cτ, including D0 and Λc+

Method:

- ~100 μm

- Extend the physics reach of the STAR experiment for precision measurement of the yields and spectra of particles containing heavy quarks:
- Study charm and beauty energy losses to test pQCD in a hot and dense medium at RHIC
- Charm flow to test thermalization at RHIC
- Direct reconstruction of charm decays with small cτ, including D0 and Λc+
- Method:

**Heavy Flavor Tracker @ STAR**

**Resolve displaced vertices (>60 ****μ****m)**

- RHIC – Relativistic Heavy Ion Collider
- STAR – Solenoidal Tracker at RHIC

## TPC points at the SSD ~ 1 mm

SSD points at the IST ~ 300 μm 

IST points at the PIXEL ~ 250 μm 

PIXEL points at the vertex <30 μm

**HFT and PIXEL detector**

- TPC points at the SSD ~ 1 mm
- SSD points at the IST ~ 300 μm
- IST points at the PIXEL ~ 250 μm
**PIXEL points at the vertex <30 ****μ****m**

- PIXEL at 2.5 and 8 cm

- IST at 14 cm

- SSD at 23 cm

- Heavy Flavor Tracker (HFT)‏

- SSD – Silicon Strip Detector
- IST – Inner Silicon Tracker

## Two layers at 2.5 & 8 cm radii
Sensor spatial resolution < 10 μm 
Coverage 2π in φ and  |η|<1
Over 400 M pixels 
0.3 % radiation length/layer 		
Thinned silicon sensors (50 μm thickness)‏
Air cooled
Power dissipation ~100 mW/cm2
Integration time <200 μs
Radiation environment at the level of up to 300 krad/year and 10×1012/cm2 Neq /year
Quick extraction and detector replacement
Stability and insertion reproducibility within a 30 μm window

- Sensor spatial resolution < 10 μm
- Coverage 2π in φ and  |η|<1
- Over 400 M pixels
**0.3 % radiation length/layer**
- Thinned silicon sensors (50 μm thickness)‏
- Air cooled
**Power dissipation ~100 mW/cm****2**
**Integration time <200 ****μs**
- Radiation environment at the level of up to 300 krad/year and 10×1012/cm2 Neq /year
- Quick extraction and detector replacement
- Stability and insertion reproducibility within a 30 μm window

**PIXEL detector characteristics**

**Very challenging mechanical and sensor design**

**Notes:**
at high intensities, short integration time is needed 

## Low mass detector design

## PIXEL detector design

- Ladder with 10 Monolithic Active Pixel Sensors (MAPS) (~ 2×2 cm each)

- Mechanical support with kinematic mounts

- 2 layers

- Cabling and cooling infrastructure

- Detector extraction at one end of the cone

- New beryllium beam pipe (0.5 mm thickness, 2 cm radius)‏

## Cable
4 layer - 150 micron thickness
Aluminum Conductor
Radiation Length ~ 0.1 %
40 LVDS pair signal traces

- _Cable_
- 4 layer - 150 micron thickness
- Aluminum Conductor
- Radiation Length ~ 0.1 %
- 40 LVDS pair signal traces

**One of the preliminary designs**

- LVDS – Low-Voltage Differential Signaling

## MAPS 100 mW/cm2 (160 W total) + drivers 80 W 

The temperature of operation is still under consideration.  
An optimum temperature for the detectors is around 0 deg C, but they can be operated at 34 deg C without too much noise degradation.

The cooling system design is simplified if we can operate at 24 deg C, 
if the cooler temperature is required the cooling system will be equipped with thermal isolation and condensation control when the system is shut down.  

Cooling studies show that air velocities of 8 m/s are required over the detector surfaces and a total flow rate of 200 cfpm is sufficient to maintain silicon temperatures of less than 10 deg C above the air temperature.

- MAPS 100 mW/cm2 (160 W total) + drivers 80 W
- The temperature of operation is still under consideration.
- An optimum temperature for the detectors is around 0 deg C, but they can be operated at 34 deg C without too much noise degradation.
- The cooling system design is simplified if we can operate at 24 deg C,
- if the cooler temperature is required the cooling system will be equipped with thermal isolation and condensation control when the system is shut down.
- Cooling studies show that air velocities of 8 m/s are required over the detector surfaces and a total flow rate of 200 cfpm is sufficient to maintain silicon temperatures of less than 10 deg C above the air temperature.

**Notes:**
if the cooler temperature is required the cooling system will be equipped with thermal isolation and condensation control when the system is shut down.  
The design will include humidity and temperature control as well as filtration.  

## Sensor design

## Properties:

Standard commercial CMOS technology 
Sensor and signal processing are integrated in the same silicon wafer
Signal is created in the low-doped epitaxial layer (typically ~10-15 μm) → MIP signal is limited to <1000 electrons
Charge collection is mainly through thermal diffusion (~100 ns), reflective boundaries at p-well and substrate → cluster size is about ~9 pixels (20-30 μm pitch)‏
100% fill-factor 
Only NMOS transistors inside the pixels

**Properties:**
- Standard commercial CMOS technology
- Sensor and signal processing are integrated in the same silicon wafer
- Signal is created in the low-doped epitaxial layer (typically ~10-15 μm) → MIP signal is limited to <1000 electrons
- Charge collection is mainly through thermal diffusion (~100 ns), reflective boundaries at p-well and substrate → cluster size is about ~9 pixels (20-30 μm pitch)‏
- 100% fill-factor
- Only NMOS transistors inside the pixels

**MAPS technology is an attractive choice for the PIXEL detector**

- MAPS pixel cross-section (not to scale)‏

| 
MAPS and competition | 
MAPS  | Hybrid Pixel Sensors | 
CCD |
| --- | --- | --- | --- |
| Granularity  | + | - | + |
| Small material budget | + | - | + |
| Readout speed | + | ++ | - |
| Radiation tolerance | + | ++ | - |

## MAPS @ Institut Pluridisciplinaire Hubert Curien

- We are working in collaboration with IPHC to produce sensors that meet the requirements of the STAR PIXEL detector
- IPHC-DRS (former IRES/LEPSI) proposed using MAPS for high energy physics in 1999

*CNRS - IPHC, Strasbourg-Cronenbourg *

-  More than 20 prototypes developed
- several pixel sizes and architectures (simple 3-transistor cells, pixels with in-pixel amplifiers and CDS processing)
- different readout strategies (sensors operated in current and voltage mode, analog and digital output)
- Large variety of prototype sizes (from several hundreds of pixels up to 1M pixel prototype with full-reticule size)

##  	Coupled nature of readout and sensor development

** ****	****Coupled nature of readout and sensor development**

- 2011 (planned)
- Install final detector

- 2010 (planned)
- Install 3-module engineering prototype (based on Phase1)‏

- Today
- First prototypes in hand and tested

- analog
- signals

- Complementary detector readout

- MimoSTAR sensors 4 ms integration time

- Ultimate sensors  < 200 μs integration time

- analog

- digital

- digital signals

- Phase-1 sensors  640 μs integration time

- CDS – Correlated Double Sampling

## Prototypes with analog readout

- Analog readout – simpler architecture but ultimately slower readout

- Based on tests of several different prototypes
- S/N>12 allows detection efficiency >99.6%

**MAPS show promising performance for the PIXEL detector**

- MimoSTAR2 test results

- Prototypes in AMS 0.35
- MimoSTAR 2
- 128 × 128 pixel  (30 μm pitch)‏
- MimoSTAR 3
- 320 × 640 pixel  (30 μm pitch)
- Half-reticle size‏

## Prototypes with binary readout

*IEEE TNS, vol 53, no 6, 2006, pp 3949 - 3955  *
*IEEE TNS, vol 52, no 6, 2005, pp 3186 - 3193*

- Prototypes Mimosa 8 and Mimosa 16 developed by IPHC and DAPNIA feature binary readout ** **
**a major step towards on-chip data sparsificaiton**

- Significantly reduces pixel-to-pixel dispersions

- Meets PIXEL requirements

- Mimosa16 test results

**Notes:**
Digital readout – offers increased speed but requires on-chip discriminators or ADCs

## Phase-1 prototype for PIXEL

- Phase-1 combined with on-chip zero suppression
- 2 outputs per sensor
- On-chip zero suppression has been successfully implemented and tested at IPHC as a small size prototype
- The prototype zero-suppression circuitry works up to 115 MHz
- Pixel reduced from 30×30 μm down to 18.4×18.4 μm to improve radiation tolerance against non-ionizing radiation damage

**Final sensor for the PIXEL detector**

- Full reticule sensor
- Architecture based on Mimosa8/16
- Binary readout of all pixels (4 outputs)

- Integration time ~640 μs
- The chip is ready for production

## Readout system design

## Triggered detector system fitting into existing STAR infrastructure (Trigger, DAQ, etc.)

Deliver full frame events to STAR DAQ for event building at approximately the same rate as the TPC (1 KHz for DAQ1000). 

Reduce the total data rate of the detector to a manageable level (< TPC rate).

Reliable, robust, cost effective, etc.

- Triggered detector system fitting into existing STAR infrastructure (Trigger, DAQ, etc.)
- Deliver full frame events to STAR DAQ for event building at approximately the same rate as the TPC (1 KHz for DAQ1000).
- Reduce the total data rate of the detector to a manageable level (< TPC rate).
- Reliable, robust, cost effective, etc.

- Example for a full detector:

## Readout path

**10 parallel independent readout modules (4 ladders per module)**

## Readout system - physical layout

## Readout system implementation choices

**Readout system implementation choices**

- Motherboard

- Xilinx Virtex-5 Development Board

- Digital I/O LVDS Drivers
- Cypress USB chipset
- Fast SRAM
- Serial interface
- Trigger / Control input

- FF1760 Package
- 800 I/O pins
- 4.6 – 10.4 Mb block RAM
- Up to 550 MHz internal clock
- Individual IODELAY

- Optical link

- Commercial product			Our design		CERN ALICE RORC-SIU

- Half duplex connection
- Up to 1.2 Gbps
- Part of DAQ1000 upgrade

## Prototyping of mechanical support structures is planned to begin in the next few months
Full reticle 2 × 2 cm Phase-1 should be available at the end of this year 
detector engineering prototype  (3/10 of the complete detector) will be constructed and should allow to perform physics measurements in 2010
New prototypes with on-chip discriminators are capable of the required S/N ratio for >99% detection efficiency but with a limited safety margin
Resistance to radiation damage level that can be expected in the STAR environment with the final luminosity (8×1027 /cm2/s ) is being studied
The readout concept has been validated with LVDS readout test (BER <10-14 @ 160 MHz and 2 m fine twisted pair cable) and the full readout system production prototypes are being developed

- Prototyping of mechanical support structures is planned to begin in the next few months
- Full reticle 2 × 2 cm Phase-1 should be available at the end of this year
- detector engineering prototype  (3/10 of the complete detector) will be constructed and should allow to perform physics measurements in 2010
- New prototypes with on-chip discriminators are capable of the required S/N ratio for >99% detection efficiency but with a limited safety margin
- Resistance to radiation damage level that can be expected in the STAR environment with the final luminosity (8×1027 /cm2/s ) is being studied
- The readout concept has been validated with LVDS readout test (BER <10-14 @ 160 MHz and 2 m fine twisted pair cable) and the full readout system production prototypes are being developed

## Thank you for your attention

## Backup slides

## Fast, column-parallel architecture

**CDS at column level (reduces Fixed Pattern Noise below temporal noise)**

*V**READ,CALIB*

*V**C*

*V**in1,2*

*V**S_READ*

*A**1 **V**off1*

*A**2**, V**off2*

**Developed in IPHC - DAPNIA** **collaboration**

## The final detector system is expected to have LVDS data transfers at the maximum rate of 160 MHz

- Ladder mock-up with 1-to-4 LVDS fanout buffers

- Mass termination board + LU monitoring

- Virtex-5 based RDO system with RORC link to PC
- Virtex-5 individual IODELAY was adjusted for each channel

- Buffered path 160 MHz 2.3 m cables

**Bit Error Rate  < ****10****-14**

- 42 AWG wires

- 24 AWG wires

## RDO system for prototype with binary full-frame readout

- RDO system for the final sensor with on-chip zero suppresion