# Presentation: 657053

## Slide 1

## Overview

- IceCube
- Design Requirements
- IceCube DAQ
- Reliability, Quality Assurance
- Lessons Learned
- Performance

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## IceCube

- 70-80 Strings
- 60 DOMs per String
- IceTop Air Shower Array on top of String

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**Notes:**
70-80 Strings 
-> 60 Optical modules per string (We call them DOM)
-> On top of each string is an IceTop-Station (Icetop is am air-shower array) 
-> all strings end in one place, the counting house

Same Electronics used for IceCube and Icetop

## Design Requirements

- 10-15 Years lifetime goal
- Reliability / Robust Design
- Remotely controllable
- Failure must not propagate
- Resistant to Radio Frequency Interference
- Expected Hit rate ~0.8 kHz
- Low power consumption < 5W/DOM
- Surface temperatures     -20°C to -70°C
- At-depth temperatures    -10°C to -40°C

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**Notes:**
Failure must not propagate: Catastrophic failing DOM must not take out a String
RFI: Many Transmitters present at the South Pole. Many of them high power and all of them near by.
Hit Rate: We know now 0.8kHz but we designed for more
Low Power: Fuel flown in to the South Pole

## Physics Requirements

- Timing, 7ns RMS		4ns RMS
- Waveform capture
- 300MS/s for 400ns, 40MS/s for 6.4μs
- Charge Dynamic Range
- >200PE/15ns		~500PE/15ns
- In Situ Calibration (internal and external)
- In-Ice Hardware Local Coincidence

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**Notes:**
Timing refers to Photon arrival time resolution

## DAQ System Overview

- Ethernet

- DAQ
- E
- l
- e
- c
- t
- r
- o
- n
- i
- c
- s

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**Notes:**
Strings with DOMs connected
Strings end in DOMHub (1 DOMHub per String)
Custom Hardware: - DOM
			- DOR Cards at the surface end of Cable
- After the DOMHub standard computer HW and Ethernet is used

The same Custom hardware is used for IceCube and IceTop

## Timedomains

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**Notes:**
We don’t distribute a Clock signal oce the whole array
 -> Each DOMs uses its own Clock(Time) source
 -> The Surface HW (DOR) uses GPS “master time units”
 -> We do time calibration (Tcal) between the DORs and DOMs
   -> Stringprocessor converts the local DOM time to the GPS master time. 

## DOMHub

- 8 DOR Cards

- GPS
- distr.

- Chassis Fans

- Power Distr. Card

- DOM Power Supplies

- CPU

- Hard Drive

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**Notes:**
A DOMHub is a rack-mountable PC with an PCI backplane.
DOR Cards plugged in to the DOMHub make the Interface to the DOMs.
DOMHubs are self contained (Own DOM power supply and has alternative clock source if GPS is not present)

## DOM Readout Card

- DOM Communication      DOM Power Input      GPS Master Time Input

- Main Cable Connector        PCI interface        DOM Power Distribution

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**Notes:**
DOR card developed by our colleagues at DESY-Zeuthen

Left Side: 2 Connector servicing 2 twisted quads (8 DOMs)
Right Side: 96V and GPS input
Two FPGAs: one for PCI and one for communications

## Main Cable

- 0.9mm Twisted Quad Copper Cable
- 2.5km long (continuous in ice) + Surface Cable
- 2 DOMs per wire pair
- Power, Timing and Communications over the same wire pair
- > 50dB suppression near end cross talk
- > 30 db suppression far end cross talk

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**Notes:**
Just for quick reference, the cable:
We use Twisted Quads because the use less space than Twisted pairs (twist 4 wires and use the two diagonal pair)
“Star Architecture” because of Requirement ‘one DOM must not take out the whole string’
Relaxed to one DOM can take out one other DOM (the one on the same wire pair)
Each DOM has its own connector for easy deployment
Cross talk requirement for for a good communications link

## Digital Optical Module

- Passive Base
- HV Supply
- Flasher Board
- Main Board
- Delay Board

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**Notes:**
Benthos Sphere
10’’ PMT
Mu metal shield
Flasher board used to calibrate neighbor DOMs
Flasher Board and MainBoard are attached to the PMT neck
Cathode is on “Ground” level to avoid an electric field in the Gel
 -> PMT signal is on High Voltage -> Transformer coupled (Better performance, than capacitors, for long pulses)

## DOM Main Board

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**Notes:**
Point out:
Analog section
ATWD (custom SCR based ADCs)
FPGA/CPU/memory/CPLD
X-Tal
Communications / Local Coincidence
Power Supply
 -> Also note the 2 big white capacitors. Foil and NOT Electrolytic 

Developed at LBNL

## DOM Main Board

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## DOM Main Board

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## Altera Excalibur

- FPGA 400,000 Gates
- ARM9 CPU
- Bus bridges between CPU and FPGA
- Dual Ported Memory between CPU and FPGA
- Power consumption 0.5 – 0.7W

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**Notes:**
Bridges between FPGA and CPU (Dual Ported Memory, Bus from CPU to FPGA and FPGA to CPU)

CPU: High level control
FPGA: Used for fast, timecritical deterministic tasks

e.g.
Communications: Low level is in FPGA. High level in CPU (retransmit, ..). DPM serves as data buffer
DAQ: FPGA collects data, subtracts pedestal, compresses data, DMA transfer to CPU memory through bus bridge.

## DOM Main Board

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## ATWDAnalog Transient Waveform Digitizer

- ASIC
- Switched Capacitor Array
- 4 Channels x 128 Samples Deep
- Sampling on Launch
- Sample Speed 250 - 800MSamples/s
- Digitization, ~30μs/waveform
- Power consumption 125mW

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**Notes:**
ATWD is an ASIC developed at LBNL
Used before in Nestor and KamLAND
Starts sampling on launch -> delay for signal required

## DOM Main Board

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## Oscillator

- Reference “time” of DOM
- High Reliability Part
- Screened for short term stability

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**Notes:**
Reminder: Local clock in each DOM
Stability for less frequent time calibrations

Allen Variance is a measure of clock stability

SRS: Rubidium Clock
Monitor: Custom X-Tal for stability (we didn’t get what we asked for)
TCO-999: Toyocom
C2560: Corning/Vectron screened part; Specs are guaranteed
Critical Part:
Used for clocking
Local DOM “time” based on it -> good short term stability

## DOM Main Board

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## Local Coincidence

- Reduce Data Rate
- Rate without LC ~1KHz
- Rate with LC <15Hz
- Dedicated Full Duplex LC connection
- Transmit and Receive go through FPGA
- LC functionality can be reprogrammed

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**Notes:**
Main Noise source is radioactive decay in Benthos Sphere

## Reliability, Quality Assurance

- DOMs are not accessible after deployment
- By Design
- Production
- Testing

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**Notes:**
Because of the volume of Items I split it up into 3 Groups. Some points could fit into more than one group.

## Design

- Qualified Manufacturer List
- GIDEP (Government-Industry Data Exchange Program)
- No Wet Electrolytic Capacitors
- Derate Parts
- HALT (Highly Accelerated Lifetime Testing) Input
- Serial number; electronic, barcode and human readable
- Robust Boot Mode
- Little Redundancy in the DOM (Deployed Spares)
- MTBF calculation not reliable (Temperature range)

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**Notes:**
HALT testing: -80C to +80C and 30G rms vibration to find weak parts
Redundancy: We have some redundancy but not much, because of design constrains (Budget, power, ...) instead we tried to make everything as reliable as possible
MBTF: Manufacturer data, if available, usually doesn’t address low temp failure modes

Designing was an iterative process. 

## Production

- IPC610 class 3 for Board production and loading
- No Microwelds in PCB
- Use of Industrial Temperature Parts
- Tin-Lead Parts wherever possible (NO pure tin parts)
- Close work with Board manufacturer and loading house for fast feedback
- Digital picture of Boards after loading
- ESD Precautions

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**Notes:**
IPC610 class 3: sets tolerances for PCB production and Board loading
e.g. wetting of pins, alignment of Parts, trace width and spacing

Microwelds:
Standard practice
Allowed in class 3
Repairing discontinuities by welding copper tape to the trace

No Military parts used. They are too expensive. Lifetime buy for critical parts

Digital Picture: Trace ability of Parts (data and lot codes) used

ESD Precautions because ESD can leave unseen damage (Part is weakened but not destroyed)

## Testing

- Initial room temperature Test
- HASS (Highly Accelerated Stress Screening)
- 48 hour Main Board burn-in hot and cold
- Interface test
- Integrated DOM burn-in 21 days at various Temp.
- Test before Deployment at ~-25°C
- In Summary; Testing, more Testing and even more ...
- All Test results are stored in Database
- ESD Precautions

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**Notes:**
HASS testing: -50C to +65C and 7G rms vibration (enough stress to find weak parts but not too much to significantly shorten the live)

## Lessons Learned

- Test Framework (bench, integration, before deployment and after deployment)
- DOMHub can run standalone
- Terminal Connection to DOM
- Script Language/Interpreter on DOM

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**Notes:**
Stuff we did not plan that way from the beginning.
Stuff I would like to see in a future experiment.

## Performance

- One String and 4 IceTop Stations are deployed
- Time Calibration
- Noise/Discriminator Threshold
- Muon Reconstruction

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**Notes:**
One String and 4 IceTop Stations are in the Ice. Don’t expect a lot of physics.

## Time CalibrationReciprocal Active Pulsing 

- Verified using:
- Flasher Boards
- IceTop –IceCube coincidences
- AMANDA – IceCube coincidences

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**Notes:**
As mentioned earlier, each DOM has its own “time”.
Important to verify we can synchronized the clocks.

Standard synchronization is RAP Cal. It is working.
RAP Cal was verified using:
Flasher boards (establishing time between DOMs)
Muon conicidences

## Clock Stability

- Time Calibration every 3.5s

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**Notes:**
The drift is mostly due to the measurement error

## Noise/Discriminator Threshold

- PMT Gain 107
- Noise in the Ice is ~800Hz
- Threshold as low as ~1/8SPE

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**Notes:**
Important for the physics is the noise and from there the discriminator threshold.

## Muon Reconstruction

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**Notes:**
Fast but not least some real physics

## Summary

- DAQ Design
- Reliability
- One IceCube string deployed
- Four IceTop Stations deployed
- String is working very well
- All 76 DOMs function well
- In Jan, Feb up to 10 more Strings deployed
- Full Array deployed by 2009-10

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**Notes:**
Good design and reliability paid off!
String and IceTop stations are working well. Except one DOM running are reduced HV

## Thank You

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