# Presentation: 842434

## Muon Tracker Front-end Electronics

- PHENIX FEE Review
- June  10-11, 1998
- Brookhaven National Laboratory

- Belinda Wong-Swanson
- LANL NIS-4
- Tel: 505-665-8787
- Email: bwong-swanson@lanl.gov

## Topics

- MuTr Signal Requirements and Channel Counts
- MuTrFEE Design Team
- MuTrFEE Overview
- Technical Design Requirement & Constraints
- Detector-FEE Circuit Requirements & Constraints
-  Cathodes FEM Layout & “FEM” Description
- Cathode FEE Counts

## Topics (continued)

- Current Status
- Prototype Plan and Schedule
- MuTrFEE Schedule
- Overall Schedule
- Fabrication Schedule
- Major Milestones

## MuTr Signal Requirements

- Cathodes
- 4 pulse-height samples per event (stale hits rejection)
- Channel Matching ~ 1% (after calibration)
- Noise < 3000 e ̄
- 11-bit dynamic range (0.1  10 x 80 fC)
- ~750ns integration time & < 12s decay time for    10 –150 pF strip capacitances

## MuTr Signal Requirements

- Anodes
- Latch (1-bit A/D)
- 10 – 50 pF input capacitance, ~70 ns chg collect’n time
- DO NOT IMPACT ACCEPTANCE
- Must hide in shadows of detector octant frames

## MuTr Channel Counts

## MuTrFEE Team

- *Grad Students have grants  Free to PHENIX

## MuTrFEE Technical Design Requirements & Constraints

- General
- Interface to PHENIX Online System
- Provide Ancillary (Remote) Controls & Monitors
- Robustness (_No_ access for _~months_ at a time)
- Nothing between Stations 1 & 2
- Station-1 electonics upstream of Station-1 detectors
- Stations-2&3 electronics between Stations-2&3 detectors

## MuTrFEE Technical Design Requirements & Constraints (cont’d.)

- Stations-2&3 electronics _inside_ magnet
- minimal-to-no access for very long periods
- engineer against multiple single-point failures
- low-noise electronics in a magnetic field
- no (iron-core) transformers
- no electric motors/fans
- low-noise electronics inside a dirty “oven” - 30°C ambient
- cooling in a hot/humid/stagnant environment
- fluid-based cooling
- dried atmosphere with good thermal conduction
- _enclosures_ for environmental isolation

## MuTrFEE Technical Design Requirements & Constraints (cont’d.)

- Nothing in acceptance downstream of Sta-1
- Extremely limited “radial” space at Station-2
- Anodes readout must hide behind Sta-2 octant framesand not enlarge “dead bands” at Sta-3 octant boundaries
- Clear lines of sight for alignment monitoring
- Limited space in all dimensions for cathodes readout at Stations 2&3
- Anodes readout must have radial “holes” along spokes

## Slide 11

## Slide 12

## MuTrFEE Technical Design Requirements & Constraints (cont’d.)

- Limited space in both r and z at Station-1
- Also must leave space for BB-counters’ cabling
- Minimal cathode analogue-cable lengths
- avoid noise pickup
- Limited magnet “penentrations” availablefor MuTrEE services and signals
- Lower ones consumed by magnet power & cooling
- Must not distort or load detector structures

## Top view of an octant

- between Station 2 and
- Station 3, South-Arm

## MuTrFEE Technical Design Requirements & Constraints (cont’d.)

- Top 5 lampshade panels are removable
- Cannot attach to/mount anything from them
- Must try to avoid having anything delicate near them
- Big, heavy, oddly shaped, unstable orientations
- Can’t rely solely on jigs & rigging fixtures
- Must avoid noise sources _safely_
- Humidity + dissimilar metals  cathodic currents
- Need electrical isolation wrt det mounts & magnet
- _BUT_ must not allow hazardous step potentials to develop

## Detector-FEE Circuit Requirements and Constraints

- Detectors + FEE constitute a LARGE, DISTRIBUTED, REACTIVE NETWORK
- Difficult to establish a “True” Ground
- Cathode and Anode electrodes are physically far apart
- Ground & Power Paths are Intimately Connected to Detector & FEE Operations
- Signal Returns are tied to Preamp LV Power Rails

## Detector-FEE Circuit Requirements and Constraints (continued)

- Grounding & Power Distribution must be designed to minimize noise and EMI pickup
- Especially for Cathodes subsystem
- Grounding & Power Distribution must be designed to protect equipment & personnel

## Detector-FEE Power and Grounding Strategies

- Independent returns for all signals to only one common at the detectors
- Dedicated plane in detector PCBs
- Isolation of detector frames from magnet to avoid long term degradation of grounds due to corrosion with dissimilar metals
- Low voltage DC power “floated” with respect to (HV + detectors)

## Detector-FEE Power and Grounding Strategies (continued)

- Passive ground isolation and filtering in both HV and LV circuits to prevent pickup on power cables from leaking into detector-FEE circuits
- Isolation of FEE frames from detector frames and magnets and mechanical structures.
- Bleeder resistors in HV distribution to allow the detector to discharge in case of HV faults.

## Detector-FEE Power and Grounding Strategies (continued)

- Considering active monitoring for ground faults between magnets, detectors, and FEE structures that may lead to step-potentials build-up during abnormal operations or failures.
- Studying details regarding filtering, TVSS, etc. in AC-power system.

## Cathodes FEM Layout

## Definition of MuTr “FEM”

- Chassis has 2 Front End Modules (FEMs)
- Half-chassis has 1 FEM
- FEM has
- Backplane
- Mates with FEM Transition Module
- Analogue/Digital interconnect for Cathodes/Anodes

## Definition of MuTr “FEM” (continued)

- Readout Interfaces (2)
- Slow Controls Interface
- ARCNet + Serial  for configuration & initialization
- DAQ Interface
- Glink-in + Fast Timing & Control + Data Formatter + GLink-out
- sometimes called “Heap Manager” in other subsystems

## Definition of MuTr “FEM” (continued)

- ReadOut Cards
- Cathodes ROC (2)
- pre-amp + AMU-ADC + some buffering
- Analogue ins via Cathodes Analogue Input & Calibration Card
- So can replace  FEM cards w/o disturbing detector cables
- Analogue inputs perpedicular to fast backplane signals
- Includes circuitry for precision cathodes calibration

## CAIC

**To 14**
**channels**

**Ccal**

**Ccal**

**Ccal**

**Ccal**

**CH1**

**CH2**

**CH3**

**CH4**

**Ccal**

**Ccal**

**Ccal**

**Ccal**

**CH5**

**CH6**

**CH7**

**CH8**

**To 14**
**channels**

**To 14**
**channels**

**To 14**
**channels**

**Preamp**
**ASIC**
**1 of 8**

**CROC**

**From**
**Det.**

**From**
**Det.**

**From**
**Det.**

**From**
**Det.**

**From**
**Det.**

**From**
**Det.**

**From**
**Det.**

**From**
**Det.**

**SD_IN**

**DATA**
**CLOCK**

**BEAM**
**CLOCK**

**RD_WR***

**SUBSEL0**

**SUBSEL1**

**SUBSEL2**

**CRDSEL0**

**CRDSEL1**

**CRDSEL2**

**HARDWIRED**
**CARD SELECT**
**and CONTROL**
**LOGIC**

**MB0 (RESET)**

**MB1 (RESET)**

**MB6 (CAL)**

**MB7 (CAL)**

**MODE_ENBL**

**BACKPLANE**

**CONTROL LOGIC**

**EN**

**A0**

**A1**

**DAC1_8BIT**

**DAC2_8BIT**

**DAC3_8BIT**

**DAC4_8BIT**

**LATCH**

**DATA**
**CLOCK**

**RD_WR***

**LATCH**

**SWITCH_EN1**

**SWITCH_EN2**

**SWITCH_EN3**

**SWITCH_EN4**

**VREF**

**ANALOG**
**OUT**

**8-BIT**
**DAC1**

**NO**

**NC**

**SD_OUT1**

**EN**

**A0**

**A1**

**SWITCH CONTROL**

**V**

**Vr**

**EN**

**SWITCH EN1**

**DATA**
**CLOCK**

**RD_WR***

**LATCH**

**VREF**

**ANALOG**
**OUT**

**8-BIT**
**DAC2**

**NO**

**NC**

**SD_OUT2**

**EN**

**A0**

**A1**

**SWITCH CONTROL**

**V**

**Vr**

**EN**

**SWITCH EN2**

**DATA**
**CLOCK**

**RD_WR***

**LATCH**

**VREF**

**ANALOG**
**OUT**

**8-BIT**
**DAC3**

**NO**

**NC**

**SD_OUT3**

**EN**

**A0**

**A1**

**SWITCH CONTROL**

**V**

**Vr**

**EN**

**SWITCH EN3**

**DATA**
**CLOCK**

**RD_WR***

**LATCH**

**VREF**

**ANALOG**
**OUT**

**8-BIT**
**DAC4**

**NO**

**NC**

**SD_OUT3**

**EN**

**A0**

**A1**

**SWITCH CONTROL**

**V**

**Vr**

**EN**

**SWITCH EN4**

**DATA**
**CLOCK**

**RD_WR***

**LATCH**

**DAC1_8BIT**

**DAC2_8BIT**

**DAC3_8BIT**

**DAC4_8BIT**

**CONTROL LOGIC**

**RST**

**(INJECT)**

**SD_OUT1**

**SD_OUT2**

**SD_OUT3**

**SD_OUT4**

**SD_OUT**

**CAIC**

**CRDSEL**

**CRD_SEL**

**RST**

**RST**

**RST**

**RST**

**(FROM SLOW CONTROLS)**

**(FROM TIMING & FAST CONTROLS)**

**(FROM SC)**

## CROC Block Diagram

- From cathode analog input and calibration card

- MuTrFEE has only 2 ASICs: CPA which is unique to MuTr, and AMUADC which is common to 4 PHENIX subsystems

## Cathode FEE Counts

## Current Status

- CPA prototype chips now under test
- 2 test stands, allow both bench-top and on-detector tests
- Bench-top test results all agree with expectations from simulations
- 2 _minor_ design mods & _no additional prototyping req’d _ in order for all design specs to be met
- Foresee no obstacles to completion by Jul98
- Additional tests will focus on analog interconnects and CAIC-circuit prototyping
- Ready for CPA Production ASAP after 10/1/98

## Current Status (continued)

- Backplane design (including layout and simulation) almost complete (on hold for final decisions regarding proposed simplifications)
- Detailed CFTM and CAIC design underway
- Detailing AMUADC timing and control requirements (to accommodate 4 samples/event) underway
- Preparing for on-detector tests with CPA test stand

## Current Status (continued)

- Beginning to develop test equipment for prototype testing of FEM boards
- Completed FEM Chassis design
- Detailing cooling system design
- Detailing cabling and services plants routing requirements
- Detailing mechanics designs
- Beginning to develop installation scenarios.

## Cathode Prototype Plan and Schedule

- Plan presented at May98 Muon Arms  MiniTAC Review was to delay almost all prototyping until 10/1/98. LANL P-Division has agreed to provide some support for earlier prototyping.
- Plan explicitly incorporates 2 rounds of prototyping.
- Prototyping and integrated-FEM tests to be completed by June 99.

## MuTrFEE Schedule (Calendar in Fiscal Year)

**MuTrFEE Schedule (Calendar in Fiscal Year)**

## Fabrication & Integration Milestones

- 10/01/98 CPA ASIC production
- 06/17/99 Cathodes FEM design integration and tests completed
- Start fab’ing prod’n parts for S-Arm cathodes
- After 04/01/99 (JFY boundary)
- 05/99-09/99 Prepare cathodes FEM test stations
- 08/05/99 Begin FEE infrastructure installation
- after detector installation complete

## Fabrication & Integration Milestones (continued)

- 09/99-01/00 Assemble and test S-Arm cathodes FEM
- 11/10/99 Begin S-Arm cathodes FEM installation in assembly area
- 02/14/00 S-Arm cathodes FEMs installed
- S-Arm ready for roll-in

## Major Milestones After S-Arm Installation

- In current project plan
- 03/01 N-Arm cathodes FEMs installed
- 07/01 S-Arm anodes FEMs installed
- 08/01 N-Arm anodes FEMs installed
- These dates are dependent on
- access to collision hall
- availability of AEE contingency funds for anodes development and production