# Presentation: 903483

## PHENIX Silicon Meeting

- August 28-29, 2006
- Los Alamos National Laboratory

## PHENIX Silicon Radiation Environment

- Common with VTX
- Based on Skutnik’s thesis
- VTX ASIC Discussion
- Two Baseline Operational Scenarios
- LDRD:	RHIC I Intensities
- FVTX:	RHIC I & RHIC II (assumed 10x RHIC I)
- Radiation levels for p-p worst case (10x Au-Au)
- Component behavior gleaned from multiple sources and extrapolated to PHENIX environment.

## PHENIX Silicon Radiation Environment Consequences

- Component Selection
- FPGAs
- SERDES
- Voltage Regulators
- Component Placement
- Maximize distance from beam
- Logic Design Approach
- Methodologies
- Soft mitigation

## PHENIX Silicon Radiation Environment Summary

- 10 year Total Integrated Dose - <200 kRad
- Dose rates – 90k n/cm2-sec (12.8 mRad/sec) for p-p

## FPGA Radiation Performance

|  | Actel Axcelerator | Actel ProASIC3 | Altera Stratix II GX | Altera Cyclone II |
| --- | --- | --- | --- | --- |
| Model | AX 2000 | A3PE3000 | EP2SGX60 | EP2C70 |
| Configuration type | Anti-fuse | FLASH | SRAM | SRAM |
| Single-ended I/O / Differential I/O pairs | 684 / 342 | 616 / 300 | 534 / 78 | 622 / 262 |
| Voltages | 1.5 | 1.5 | 1.2 | 1.2 |
| Power (Quiescent) | 22mA | 25mA | 820mA | 250mA |
| Built-in SERDES | No | No | Yes | No |
| I/O Rates  | LVDS - 700 Mb/s | LVDS - 700 Mb/s | LVDS-6.375 Gb/s | LVDS-622 Mb/s |
| Configuration Errors | No | No | Yes | Yes |
| SEE types | clocks, data memory | clocks, data memory | configuration, clocks, memory, SERDES | configuration, clocks, memory |
| SRAM Memory- Data | 294912 | 516096 | 6747840 | 1152000 |
| SRAM Memory- Configuration | 0 | 0 | 16951824 | 14319216 |
| FLASH Memory- Configuration | 0 | 0 | 32 Mbyte | 16 Mbyte |
| RHIC I AuAu SEU Rate - 10 cm /hr-chip | 0.00 | 0.00 | 27.12 | 22.91 |
| RHIC I AuAu SEU Rate - 40 cm /hr-chip | 0.00 | 0.00 | 1.70 | 1.43 |
| RHIC II AuAu SEU Rate - 10 cm /hr-chip | 0.00 | 0.00 | 271.23 | 229.11 |
| RHIC II AuAu SEU Rate - 40 cm /hr-chip | 0.00 | 0.00 | 16.95 | 14.32 |
| RHIC II p+p SEU Rate - 10 cm /hr-chip | 0.00 | 0.00 | 2169.83 | 1832.86 |
| RHIC II p+p SEU Rate - 40 cm /hr-chip | 0.00 | 0.00 | 135.61 | 114.55 |
| Total Integrated Dose (functional) | >200k | >200k | >50k | >50k |
|  |  |  |  |  |

## PHENIX Silicon Radiation Environment Mitigation

- Actel FLASH-based FPGA for ROC
- Evaluating SERDES parts for Radiation tolerance
- Both National and TI have tested devices.
- Evaluating LDO Linear Voltage Regulators
- National, Linear Technology and Micrel parts have tested devices.
- Logic design using proven mitigation techniques
- TMR (triple module redundancy) of sequential logic.

## Electronics Design Approach

- Top Down Design
- Requirements driven
- Specifications define design
- Interfaces defined by design
- R&D Development
- FPGA Prototyping w/development boards
- Calibration circuitry
- Complete Prototype System
- Common Design Tools
- Mechanical ( ProE)
- Electrical (Mentor Graphics ExpeditionPCB)
- Logic Design (VHDL)

## Electronics Design Short-term Objectives

- Definition of all interfaces both mechanical and electrical by Q4 2006
- Component selection for ROC (driven by radiation environment) completed by 4Q 2006
- Fully functional LDRD prototype at LANL by Q1 2007
- Interface to 8-chip FPIX module
- Interface to PHENIX DCM
- GTM emulation with FPGA card

## Plan Forward for Electronics Design

- LANL providing specifications to FNAL for interface and mechanical requirements
- LANL to negotiate collaboration with Columbia
- LANL set up PHENIX DAQ locally
- Continue with electronics design
- ROC
- FEM
- Functional Prototype at LANL