# Presentation: 649872

## L1 & L2  Trigger Data Flow

- MUO

- SMT

- CFT

- CPS

- FPS

- CAL

- L1MUO

- L1CFT

- L1FPS

- L1CAL

- L2MUO

- L2CFT

- L2CPS

- STT

- L2FPS

- L2CAL

***axial***

***stereo (u,v)***

- _L1 & L2  Trigger Data Flow_

- L2
- Global

***refit tracks***

***z-vertices (?)***

- All objects  in physics coordinates

- 1st event-wide trigger decision

- S
- L
- I
- C

## DØ Level-2

## Example L2 Crate; Calorimeter

- P
- M
- -
- B
- I
- T
- 3

- V
- B
- D

- F
- I
- C

- F
- I
- C

- F
- I
- C

- All Hotlink connections are single channel UTP cables on Front Pannels
- MBT (hotlinks) outputs L2 objects to Global MBT receiver

- Optical Signal inputs from L1
-    4       2       4

- six MBT channels

- four MBT channels

- _Example L2 Crate; Calorimeter_

*MagicBus*

- to L3

- MCH1

## Example L2 Crate; Muon

- P
- M
- -
- B
- I
- T
- 3

- V
- B
- D

- S
- L
- I
- C

- S
- L
- I
- C

- S
- L
- I
- C

- All Hotlink connections are single channel UTP cables on Front Pannels
- MBT (hotlinks) outputs L2 objects to Global MBT receiver

- Coax. (SMB cable) inputs from FE &L1
- into 14 CIC’s in dedicated crate

- eleven MBT channels

- _Example L2 Crate; Muon_

*MagicBus*

- to L3

- •••

**eleven**
**total**

- double channel UTP
- cables to SLIC’s

- MCH3

- M
- B
- T

- M
- B
- T

**pilot**

**SCL**

- to Global

**assist.**

- S
- F
- O

## L2 Crate Locations 

- _L2 Crate Locations _

## L2 to Test Stand Connections 

- MCH3
- Muon

- MCH2
- STT
- CTT , PS

- MCH1
- CAL
- Global

- FCH2
- Test
- Stand

**Patch **
**Panel**

**Image**
**Patch **
**Panel**

**Permanent **
**cabling**

- Patch panels have
- identical maps

| Source | # Inputs |
| --- | --- |
| SCL (Hub) | 1 (?) |
| SCL | 6 |
| CAL | 10 |
| PSH | 12 |
| CTT | 16 |
| MUO | 18 |
| Global | 10 |
| L1 Mask | 1 |
| SLIC | 14 |
| Total | 88 |

- _L2 to Test Stand Connections _

-  **MBT Channels**

**SLIC Channels**

- Permanent cabling between
- MCH and T.Stand is open
-  ended at MCH for minimal
- noise. Cables are bundled
- acc. to table above.
- Connect as needed

- obs: window
- is 45x45 cm
- conn.=2x3cm

- (*)

- (*) The only non-hotlink
-         connection in P.Panel

## Status of Installation

- Racks, Crates, Power, Cooling (MCH and FCH)
- Except muon CIC crate (April?)
- Almost all Cabling in place
- building muon pigtails
- some remaining cabling at the test stand
- cabling for L3 readout
- MCH-FCH Window Patch Panel
- not installed yet
- need to build 2nd patch panel for the test stand
- L2 trigger mask to L2HWFW (soon?)
- L1HWFW to L2Global (via FIC) (soon?)
- Monitoring of Alphas by L1 Scalers
- ORC’s in April

## Status of L2 Cards

- FIC
- All cards are done
- BIST errors identified last Fall have been fixed at SACLAY by replacing mismatched signal path with UTP cable
- One modified FIC worked fine in BIST mode
- Cards are currently at UIC to do the wire mods
- MBT
- All cards at UMd; testing in progress
- 3 production cards at D0 (3/13/01)
- commissioning of Alpha-MBT communication in progress
- VHDL firmware is ~95% done
- Programmed I/O, Broadcast, Monitoring
- SCL handling (April)

## Status of L2 Cards cont’d

- SLIC
- All cards are here
- It’s a software problem now
- Basic operating system done
- CIC
- BIST tests with the two pre-production boards were completed last week
- <1x10 BER with 40 Forward-Central Sci/MDT channels
- of these channels 1 found dead and 2 gave ~1x10 BER (consistent with L3 BIST testing) - suspect problems with Mu FE cable/driver
- must test the remaining ~100 PDT channels with BIST
- board released for production last Monday (3/12/01)
- expected delivery of 18 (tested) boards by mid-May
- needed only by muon system

## Status of L2 Cards cont’d

- SFO
- two pre-production boards pass all tests
- released for production last week
- expected delivery of 28 tested boards by mid-May
- needed by muon system and for test stand
- Alpha
- 2 pre-productions (+1 CDF) worked within 1 week almost a year ago
- 24 production boards delivered on Sep 13, 2000
- zero boards worked within 1 week!

## Alpha Board

## 21172 Chipset

- _21172 Chipset_

## Status of L2 Cards cont’d

- Alpha cont’d
- Many production errors are to blame
- broken vias
- small finished sizes
- boards sat 6 months from preprod to final production
- aging of OPC coat decreases solderability
- OPC is reactive and can thin vias
- popcorning of Universe BGA (almost 100% failure)
- recently confirmed by failure analysis
- delamination of the CIA BGA (>63% failure)
- recently confirmed by failure analysis
- additional concern: bad CIA chips - wire bond cross over
- bad quality control
- rotated chips, missing components, no connectivity to some components, marginal solder coverage to some R/C’s

## Status of L2 Cards cont’d

- Alpha cont’d
- currently we have 9 functional boards (2 pre-prod + 7 prod)
-  total number is limited by the number of bad-CIA boards
- replacing the CIA has been very adventurous; BGA sits in the middle of a 9U board; much better repair yield with Universe BGA
- long term reliability has been recently tested for almost all boards; encouraging results, _however_, there are concerns with board lifetime/handling
- some Mbus problems (PIO/DMA) make testing of board difficult
- Bob, Stephen, and Drew are currently at D0 debugging these remaining features; hopefully all problems are fixable in firmware

## Status of L2 Cards cont’d

- Alpha cont’d
- Assembly of 12 additional boards; last shot
- CIA will be socketed due to concerns of bad chips in hand
- buying 5 more sockets to fix for existing Alphas
- 4 weeks lead time; PO in progress
- mods to the production layout are completed (Stephen, UM/CDF); Johnny Green is reviewing the changes (this week?)
- mods include: “dogbone” widths under BGA, wire mods, L3 cache, re-route R/C’s near the CIA for socket installation
-  board vendor has been selected;  PO is ready
- turnaround time is 5-10 days
- use white-tin plating instead of OPC
- bake BGA’s before installation
- expect prototype board >4 weeks after PCB’s with remaining boards 4 weeks after that
- realistically around July for tested boards
- Beta design proceeds full speed ahead (Orsay, UMd, UVA)

## Online Software Status

- Much of structural software exists in simulation
- Control/data flow for preprocessor and global
- Draft drivers/setup for MBT and event loop           March/April
- Some alpha firmware problems?
- SCL_INIT, and DAQ interface
- VME driver, buffer allocation 		      Done
- VBD/L3 readout beginning 	  	       **DONE (3/14)!**
- Error logging and beginnings of monitoring 	       Done
- Downloading, release to Worker 		     95% done
- Admin/Worker control; data flow		      May
- SLIC:
- Basic operating system in place
- Code moving to CVS; testing download scheme
- VME drivers written 			       March

- _Online Software Status_

## Algorithms in Simulator

- 			Central, Fwd track assembly code		**April**
- CTT
- not tested yet
- PS
- CPS	more work needed
- FPS            written				                **April?**
- Cal
- e	   	~ Run 1B L1.5
- j 		merge needs work
- MET	= L1
- Global
- e(cal,cps), j(cal)	(e: fps, ctt ready)
- Ht, MET (mass)
- Mu(with ctt)	**	****	****	****              Apr/May?**
- STT 	      					              **April?**

- _Algorithms in Simulator_

- 

## Time Line

- 15-Mar             6-11 Alphas Available	   ****
- 15-Mar             MBT's on Site		   ****
-  1-Apr		 MBT-Alpha-VBD Data Flow   ****
-   Apr		 L2 Muon Software Integrated
-   May               2Alpha/MBT/VBD Integration
-   May               Begin Cal/Muon/Global  Ind. Integration
-   May	 	 Muon I/O Cards (CIC/SFO's)
-   Jun		 Global/Cal/Muon in L3/DAQ
-   Jul		Twelve Additional alphas (repair+prod)
-   Jul		Start PS/CTT