# Presentation: 363177

## The CDF Silicon Vertex Trigger

**The CDF Silicon Vertex Trigger**

- Beauty 2005
- Mauro Dell’Orso
- Istituto Nazionale di Fisica Nucleare
- Pisa – Italy

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Outline

- CDF and the Silicon Vertex Trigger (SVT)
- Motivations
- Design
- Performance
- Upgrade
- Conclusions

- Mauro Dell'Orso - Beauty 2005

- June 2005

## CDF r-z view

- SVX IISILICON VERTEX
- 5 LAYERS

- INTERMEDIATE
- SILICON LAYERS

- COT
- TRACKINGCHAMBER

- LAYER 00

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVX II

- -sector

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Why and how?

**Why and how?**

- Trigger on B hadronic decays
- B physics studies, eg. CP violation in B decays, Bs mixing
- new particle searches, eg. Higgs, Supersymmetry
- A b-trigger is particularly important at hadron colliders
- large B production cross section for B physics
- high energy available to produce new particles decaying to b quarks
- overwhelming QCD background O(103)
- need to improve S/B at trigger level
- Detect large impact parameter tracks from B decays using the fact that (B)1.5 ps

- secondary vertex

- primary vertex

**Technical challenge!**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Exploit lifetime to select b,c

- Proton-antiproton
- collision point

- B decay vertex

- Impact parameter (d)

- ~ 1 mm

- Transverse view

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVT: Input & Output

**Inputs:**
**L1 tracks from XFT (********, p****T****)**
**digitized pulse heights from SVX II**
**Functionalities:**
**hit cluster finding**
**pattern recognition**
**track fitting**
**Outputs:**
**reconstructed tracks**** ****	****	****(****d****, ********, p****T****)**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVT Design Constraints

- Detector
- Raw Data

- Level 1 pipeline: 42 clock cycles

- Level 1
- Trigger

- L1
- Accept

- Level 2
- Trigger

- Level 2 buffer: 4 events

- L2
- Accept

- DAQ buffers

- L3 Farm

- Level 1
- 7.6 MHz Synchromous Pipeline
- 5.5 s Latency
- 45 kHz accept rate

- Level 2
-  Asynchromous 2 Stage Pipeline
- 20 s Latency
- 300 Hz accept rate

- Mass Storage (50~100 Hz)

- 7.6 MHz Crossing  rate

**45**** kHz input rate**
**O(10****3****) SVX strips/event**
**2-D low-res COT tracks**
**Latency ****O(1****0) ********sec**
**No Dead Time**
**Resolution ********offline**

- SVX read out after L1

- At L3 it is too late

- SVT here

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Tracking in 2 steps

- Find low resolution track candidates called “roads”. Solve most of the pattern recognition

- Super Bin  (SB)

**Tracking in 2 steps**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## ...

- The Pattern
- Bank

**Pattern matching**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## AM: Associative Memory

**Each pattern with ****private comparator**
**Track search ****during**** detector**** readout**

**AM****: A****ssociative ****M****emory**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## AM chip & system

** ****Undoable with standard electronics **(90’s)
** ****Full custom**** VLSI chip - **0.7m (INFN-Pisa)
** ****128 patterns, 6x12bit words each**
** ****Working up to 40 MHz**

**Limit to 2-D**
**6 layers:  5 SVX + 1 COT **
**~250 micron bins **** ********  32k roads / 30****0**** ******** sector**
**>95% coverage for P****t**** > 2 GeV**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## AM chip internal structure

**DB<11:0>**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## AM chip working principle

**AM chip working principle**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Track Fitting

- Track confined to a road: fitting becomes easy
- Linear expansion in the hit positions xi:
- Chi2 = Sumk ( (cik xi)^2 )
- d = d0+ai xi ;   phi = phi0+ bi xi ;   Pt = ...
- Fit reduces to a few scalar products: fast evaluation
- (DSP, FPGA ...)
- Constants from detector geometry
- Calculate in advance
- Correction of mechanical alignments via linear algorithm
- fast and stable
- A tough problem made easy !

- Mauro Dell'Orso - Beauty 2005

- June 2005

## From non-linear to linear constraints

- Non-linear geometrical constraint for a circle:

*F(x**1 **, x**2 **, x**3 **, ...) = 0*

- But for sufficiently small displacements:

*F(x**1 **, x**2 **, x**3 **, ...) ~ a**0 **+**  **a**1****x**1** + a**2****x**2** + a**3****x**3** + ...  = 0*

- with constant *a**i*

- (first order expansion of *F*)

**From non-linear to linear constraints**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Constraint surface

**Constraint surface**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVT crates in CDF counting room

- Mauro Dell'Orso - Beauty 2005

- June 2005

## The Device

- Hit Finder

- AM Sequencer

- AM Board

- Hit Buffer

- Track Fitter

- Detector Data

- Hits

- SuperStrip

- Matching
- Patterns

- Roads

- Roads + Corresponding Hits

- L2 CPU

- Tracks + Corresponding Hits

- Mauro Dell'Orso - Beauty 2005

- June 2005

## AM Board

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Hadronic B decays with SVT

-  **L1**:
- Two XFT tracks
- Pt > 2 GeV;  Pt1 + Pt2 > 5.5 GeV
-  < 135°
-  **L2**:
- d0>100 m for both tracks
- Validation of L1 cuts with >20°
- Lxy > 200 m
- d0(B)<140 m

- Two body decays

-  **L1**:
- Two XFT tracks
- Pt > 2 GeV;  Pt1 + Pt2 > 5.5 GeV
-  < 135°
-  **L2**:
- d0>120 m for both tracks
- Validation of L1 cuts with >2°
- Lxy > 200 m
- d0(B)<140 m

- Many body decays

- Two paths

- @ 3 x 1031 cm-2 s-1

- Mauro Dell'Orso - Beauty 2005

- June 2005

_**The SVT advantage:**_
_**3 orders of magnitude**_

- B0  had + had Trigger

- Mauro Dell'Orso - Beauty 2005

- June 2005

##                  Performance @ 5x1031

**                 ****Performance @ 5x10****31**

-      0     10      20     30     40     50
- Latency (s)

- 24 s

- -500       -250           0          250          500
- (m)

- 35m  33m
- resol  beam
-   = 48m

- 0.00          0.05          0.10           0.15
- Impact parameter (cm)

- Efficiency

- Given a fiducial offline track with SVX hits in 4/4 layers used by SVT

**0.8**

- SVT
- Impact parameter

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVX only

- Good tracks from just 4 closely spaced silicon layers
- I.p. as expected due to the lack of curvature information

- impact parameter distribution

-  ~ 87 m

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Online beamline fit & correction

**Online beamline fit & correction**

- Subtracted

- Raw

- <d> = Ybeamcos – Xbeamsin

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Hadron-hadron mass distribution

**M****hh**** (GeV)**

**Ks**

**D0**

**L~180 pb****-1**

**B********h h**

**Hadron-hadron mass distribution**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Upgrading SVT

- Reduce SVT processing time: c1+c2*N(Hit) +c3*N(Comb.)
- More patterns  thinner roads
- Move Road Warrior before the HB
- New TF++, HB++, AMS++, AM++  @ > 40MHz

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Dead Time vs. L1 Accept Rate

**Dead Time vs. L1 Accept Rate**

- SVT @ 0.5 x 1032

- SVT @ 3 x 1032

- UPGRADE @ 3 x 1032

- Mauro Dell'Orso - Beauty 2005

- June 2005

## New AM chip 

- Standard Cell UMC 0.18 m
- 	10x10 mm die - 5000 patterns
- 	6 input hit buses
- 	tested up to 40 MHz, simulated up to 50 MHz
- 116  prototype chips on September 2004
- 	MPW run – low yield  37%
- 3000 production chips on April 2005
- 	good yield 70%
- 	private masks     	better process parameter tuning 				           for dense memory

- Mauro Dell'Orso - Beauty 2005

- June 2005

## LAMB++

**LAMB++**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Fast Track  (FTK)

**Fast Track  (FTK)**

- Next challenge is silicon tracking
- at both Level 1 & Level 2

- LHC, Super B factory, ILC

**What next ?**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SUMMARY

- The design and construction of SVT was a significant step forward in the technology of fast track finding
- We use a massively parallel/pipelined architecture combined with some innovative techniques such as the associative memory and linearized track fitting
- Performance of SVT is as expected
- CDF is triggering on impact parameter and collecting data leading to significant physics results
- B-physics, and not only, at hadron colliders substantially benefits of on-line tracking with off-line quality

- Mauro Dell'Orso - Beauty 2005

- June 2005

## 
BACKUP SLIDES

- BACKUP SLIDES

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Level 1 drift chamber trigger (XFT)

- 1          1.5          2         2.5         3          3.5        4
- offline transverse momentum (GeV)

- XFT efficiency

- Finds pT>1.5 GeV
- tracks in 1.9 s
- For every bunch
- crossing (132 ns)!
- (1/pT) = 1.7%/GeV
- (0) = 5 mrad
- 96% efficiency

- Mauro Dell'Orso - Beauty 2005

- June 2005

## CDF Run II trigger architecture

-                DØ results

- Tracking system
- central outer tracking (COT)
- silicon tracking (SVX II & ISL)
- three-level trigger
- L1: 5.5 s pipeline
- XFT: L1 2D COT track
- L2: 20 s processing time
- two stages of 10 s
- SVT at stage 1 of L2
- SVX II readout
- hit cluster finding
- pattern recognition
- track fitting

- Mauro Dell'Orso - Beauty 2005

- June 2005

## 2005 Trigger Performance & Limitations

| Level | Input rate  | Output rate | Potential limitations
Current limitation | Future upgrades | 2006 Output rate |
| --- | --- | --- | --- | --- | --- |
| 1 | ~1MHz | 25kHz
(spec 45kHz) | Silicon readout
SVT processing time
L2 processing time | XFT upgrade
SVT upgrade
L2 Pulsar DONE | 25kHz (higher at low lum) |
| 2 | 25kHz | 400Hz
(spec 300Hz) | Readout (non Si)
Event builder
L3 processing | TDC modification
Event builder
Faster L3 nodes | 1kHz |
| 3 | 380Hz | 85Hz
(spec 75Hz) | CSL/data logging | Parallel logger  45 MB/s 
CSL upgrade >60MB/s | 100Hz |

**Rates are “peak rates that we can achieve with good livetime.”**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Building the “Pattern Bank”

- In this example:
- Straight lines, 5 layers, 12 bins/layer
-                         Total number of patterns ~ (12)2*(5-1) = 576

**Building the “Pattern Bank”**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVT basic architecture

- Pattern recognition and track fitting done separately and pipelined

- Hits

**Hit Buffer**

- Roads

- Roads + hits

**Track **
**Fitter**

**Associative**
**Memory**

- Tracks
- (d, pT, )

- Pattern recognition with Associative Memory (AM)
- highly parallel algorithm
- using coarser resolution to reduce memory size

- Fast track fitting with linear approximation
- using full resolution of the silicon vertex detector

- Hits

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVT Wedges

- Mauro Dell'Orso - Beauty 2005

- June 2005

## An SVT Slice

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVT system architecture 

**Hit Finders**

**Merger**

**Associative Memory**

**Hit Buffer**

**Track Fitter**
**    ****to Level 2**

*COT tracks *

*fromXTRP*

* *

- 12 fibers

*hits*

*roads*

*hits*

***x 12 phi sectors***

**Sequencer**

*raw data from*
*SVX front end*

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVT: board count

**Hit Finders****	****42****	**
**Mergers****	****	****16**
**Sequencers****	****12**
**AMboards****	****	****24**
**Hit Buffers****	****12**
**Track Fitters****	****12**
**Spy Controls****	****  8**
**XTFA****	****	****  1**
**XTFB****	****	****  2**
**XTFC****	****	****  6**
**Ghostbuster****	****  1**

- + spares

**TOTAL**

** ****136**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVT: board and crate layout

**SVT: board and crate layout**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## SVT data volume requires parallelism

**SVT data volume requires parallelism**

- Reduces gigabytes/second to megabytes/second

- 0,1

- 2,3

- 4,5

- 6,7

- 8,9

- 10,11

- fan-out

- fan-in

- 20 (0.5) GB/s

- 100 (1.5) MB/s

- Peak (avg):

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Expectations for runII

**- Level 1: 20 kHz  (bw  50 kHz)**
**- Level 2: 39 Hz    (bw  300 Hz)**
**- Level 3: negligible**
**Expected yields in run II (2 fb****-1****)**
**  **Mode**                     **Events
**  ****B****d**  ******************             15,200**
**  ****B****s  ** **D****s****  ********            10,600**
**  ****B****s**  **D****s  ********        12,800**
**  ****B****s  ** **D*********s****  ********            9,400**
**  ****D***** ********	****	****  300,000**
**  ****Z  **  b-bbar	    **32,000**

**Expectations for runII**

_**5**__****__** sensitivity up to **__***x***__***s***__** ~ 40**_

_**N.B. : yields without SVT **__****__** **__**O(1) event !**_

_**angle **__****__**  at few degrees level**_

****
****
****

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Promise is promise

- What we promised.... From SVT TDR (’96) using offline silicon hits and offline CTC tracks

-  ~ 45 m

- Mauro Dell'Orso - Beauty 2005

- June 2005

**Notes:**
Metterci anche quella con SVX-only

## SVT performanceNot just impact parameter

- :  SVT – COT

- Curvature: SVT - COT

- Loop on all SVT-COT track pairs and compare parameters

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Level 1	@Lum=40x1030 cm-2 sec-1

- Two Major Components
- Calorimeter Triggers: Jets, electrons, photons, etc.      	~4-5 kHz
- 	In SVT: 	L1_JET10_&_ET90 (Higgs multijet)
- 			L1_TWO_TRK2_&_TWO_CJET5 (Zbb)
- 			L1_MET15_&_TWO_TRK2 (Higgs Z  ~2 kHz
- 			L1_TWO_TRK10_DPHI20 (Di TAU exotic)
- L1_EM8		(Gamma + bjet)
- L1_CEM4_PT4 	(B electron)
- L1_CMUP6_PT4	(B muon)
- Hadronic B Decays: Two XFT tracks			~11-12 kHz
- Using three classes of B triggers
- Scenario A
- pT>2,  pT,1+pT,2>5.5, opp. charge, <135DPS
- Scenario C
- pT>2.5,  pT,1+pT,2>6.5, opp. charge, <135PS by 2
- Low PT
- pT>2, <90Heavy DPS, saturate bandwidth
- Not considered for long-term

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Physics Prospects: All-Hadronic B decay Trigger

**Physics Prospects: All****-****Hadronic B decay Trigger**

**Impact parameter from the SVT**

**Trigger on secondary vertices (B hadrons)**

**B**

**0**

****

**d**

**B**

**0**

**s**

**D  n******

**Level 1:****  2D COT tracks (XFT)**

** ****Two stiff tracks  (P****t**** > 2.0 GeV/c)**
** ****Remove back-to-back pairs ( ********< 135  )**
** ****Opposite charge**

**Level 2:****  SVT tracks**

** ****Two tracks with ****large impact parameter**
** ****Vertex tracks - require positive decay length**

**Trigger**** ****Strategy**

**o**

**s**

**( CP**** ****Violation)**

**Level 3:  ****full event reconstruction**

**Z          bb**

**0**

**(b-jet calibration **
**/ top mass)**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## WHY 4/5? Signal Yields with 4/5

- 4/4

- 4/5

**1430**

**970**

**J/psi**

**D0**

**D0**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Accurate deadtime model (ModSim) to understand DAQ upgrades

**Accurate deadtime model (ModSim) to understand DAQ upgrades**

- Two SRCs in parallel
- L2 processor upgrade
- 87 bit SVX digit.
- - 3 sec in SVT proc.time
- cut SVT tails above 27 sec

**BUT  the recent **
**use of 4/5 in SVT **
**changes the conditions!**

- DeadTime

- L1A rate (kHz)

- 4/4

**4/4**** – ****4/5**

**4/4**** – ****4/5**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## CDF DAQ & Trigger

-  Asynchronous 3 Stage Pipeline
-  **20 ********s Latency**
-  300 Hz accept rate

**CDF DAQ & Trigger**

**Detector**
**Raw Data**

- Level 1
- pipeline:
- 42 clock
- cycles

- L1
- Accept

- Level 2
- Trigger

- Level 2 buffer: 4 events

- L2
- Accept

- DAQ buffers

- L3 Farm

- Level 1
- 7.6 MHz Synchromous Pipeline
- 5544 ns Latency
**50 KHz accept rate**

- To Mass Storage (50~100 Hz)

- 7.6 MHz Crossing  rate

- SVT here

- Level 1
- Trigger

**50 kHz accept rate**

-  **20 ********s average Latency**

**~20 kHz actual**

**~35 ********s actual**

**Tails are important**

- Design goals

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Slide 53

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Upgrading SVT 

**AM++**
**512k patt.**

**1st pulsar:**
**AMS+RW**

**2****nd**** pulsar:**
**HB**

**3****rd**** pulsar:**
**TF**

**Upgrading SVT**** **

- Mauro Dell'Orso - Beauty 2005

- June 2005

## 512 Kpattern / phi sector

**512 Kpattern / phi sector**

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Pulsar in SVT++

- Sequencer + RW
- RW remove redundant roads as soon as they are returned by AM sensitively reducing the amount of data handled by the Hit Buffer

- Large memory cannot be handled by old SVT boards.
- The new ones are developed using Pulsar
- Fast enough to handle the new amount of data
- SVT interface built in
- Developers can concentrate on firmware (= board functionalities)

- Hit Buffer  and Track Fitter
- They need to handle larger amount of roads and hits
- Fully exploit the fast logic of the Pulsar

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Upgrade is on schedule

**Upgrade is on schedule**

- AM++ and RW with 32k patterns have been already used in test runs for data tacking
- Plan to install AM++ with 32k pattern in July
- Studies of 128k patterns coverage and efficiency are underway
- Plan to install TF++ as soon as it will be ready (August) then move to 128k
- HB++ expected to be installed during fall with 512k pattern memory

- Real data

- AM++

- AMS/RW

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Circular buffers monitor every data link:like a built-in logic analyzer

**Circular buffers monitor every data link:****like a built-in logic analyzer**

- SVT board 1

- SVT board 2

- Mauro Dell'Orso - Beauty 2005

- June 2005

## On-crate monitoring of circular buffers

**On-crate monitoring of circular buffers**

- 107 tracks
- per hour!

- occupancy

- detector channel

- 
- azimuth (radians)

- -1000   -500      0     500     1000
-                 impact parameter (m)

- monitor resolution

- monitor acceptance

- monitor noisy channels

- Sample hits, roads, tracks at high rate
- Check boards against emulation software
- Fit for beam position ...

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Why SVT succeeded

**Why SVT succeeded**

- Performance:
- Parallel/pipelined architecture
- Custom VLSI pattern recognition
- Linear track fit in fast FPGAs
- Reliability:
- Easy to sink/source test data (many boards can self-test)
- Modular design; universal, well-tested data link & fan-in/out
- Extensive on-crate monitoring during beam running
- Detailed CAD simulation before prototyping
- See poster by Mircea Bogdan
- Flexibility:
- System can operate with some (or all) inputs disabled
- Building-block design: can add/replace processing steps
- Modern FPGAs permit unforeseen algorithm changes
- Key: design system for easy testing/commissioning

- Mauro Dell'Orso - Beauty 2005

- June 2005

## Doing silicon tracking quickly

**Doing silicon tracking quickly**

- Three key features of SVT allow us to do in tens of microseconds what typically takes software hundreds of milliseconds:
- Parallel/pipelined architecture
- Custom VLSI pattern recognition
- Linear track fit in fast FPGAs

- Mauro Dell'Orso - Beauty 2005

- June 2005