# Presentation: 479201

## SVT upgrade status

- A. Annovi for the SVT group

## SVT upgrade

**Speed up SVT execution**
**cope with high lumi**
**reduce dead-time**
**extra features**
**forward muon/electron trigger**
**increase coverage e.g. beam spot**
**How to do that?**
**more powerful Associative Memory**** (32k --> 512k patterns)**
**Improve pattern recognition resolution**
**Reduce number of roads to fit**
**Replace AMS, RW, HB, TF**** with Pulsar boards**
**Support 512k pattern/wedge**
**Faster track fitting**

## Tsukuba

- Chicago
- Fermilab

- Chicago

- Pisa

## Personnel (2005)

-  Project management: A. Annovi
-  Coordination in Italy: P. Giannetti
-  AM++: A. Bardi, P. Giannetti, M. Bitossi, P. Giovacchini
-  AMS/RW: F. Spinella, M. Piendibene, M. Bitossi
-  Hit Buffer: I. Furic, T. Maruyama, S. Chappa, A. Masato
-  Track Fitter: J. Adelman, U. Yang
-  Mezzanine: F. Tang, M. Shochet
-  Software: (Pisa) R. Carosi, S. Torre, B. Simoni, A. Annovi,
- 			S. Donati
-                    (Rome) M. Rescigno, B. Di Ruzza, L. Zanello,
- 			F. Gabor
- 	         (LBL)  A. Cerri (Wisconsin) J. Bellinger,

## AM++ board (Pisa)

**Standard cell ****AMchip prototype working >40MHz**
**Production received: ****evaluating yield**
**LAMB and AM++ vme board:**
**3****nd**** prototype build and tested**
**Need final test w/ board full of AMchips**
**Building a 4****th**** AM++ vme board prototype**** **
**fix minor issues**
**Production available by ****June**
**ON SCHEDULE**

## AMS/RW status (Pisa)

**AMS and RW firmware ****implemented and tested**
**next step implement SVT firmware tools **
**ON SCHEDULE**

- Pisa had the most risky responsibilities,
-  but we are now in very good shape

## Non italian responsabilities

**Pulsars **
**Pulsar production ****arrived**
**Large RAM**** ****mezzanine**** production done**** **
**Small RAM**** ****mezzanine**** ****prototype under test**
**ON SCHEDULE**
**TF**
**First firmware written**
**Standalone tests starting**
**ON SCHEDULE**
**HB**
**Firmware writing just started**
**BEHIND SCHEDULE**
**More man power ****(firmware engineer joined)**

## Software and integration

**SOFTWARE**
**Work in progress**
**Critical**** part for ****test ****and ****installation**
**BEHIND SCHEDULE**
**project reorganized**** after internal review**
**4 main blocks**** identified **
**coordinators assigned: ****R. Carosi, A. Annovi, A. Cerri, M. Rescigno**
**Additional man power**** ****(w.r.t. baseline) ****mostly Pisa people**
**CAN RECOVER**
**INTEGRATION**
**Vertical slice parasitic test**** ****begun **
**	****with**** AM++ ****and**** AMS/RW**
**Add boards ****as they become available**

- Real data

## Installation plan

- Fermilab goal was to install during the shutdown
- Shutdown postponed to October (at least)
- Plan to install 128kpatterns per wedge by June/July
- Installing also new TF (as soon as it is ready)
- Take advantage, as soon as possible, of
- better AM resolution
- RW function moved before HB
- faster TF

## Effect of 128k patterns

|  | < # roads > | < #roads
+ RW > | < # fits > |
| --- | --- | --- | --- |
| 32k (<63 roads) | 24.1 | 13.5 | 32.0 |
| 32k | 29.9 | 17.2 | 37.1 |
| 128k | 19.1 | 9.5 | 15.4 |

- We will get half the number of fits + better RW + faster TF and finally faster HB

- B. Simoni

## 128k + TF

- Inside SVT

- 512k + HB
- Inside SVT

## Conclusions

## Backup slides

**Backup slides**

## TODO list

**Hardware:**
**AM++ board**
**Standard cell AMchip**
**AM++ vme board**
**LAMB board (plug in with AMchips) **
**AMS/RW, TF, HB**
**Pulsars**
**2 RAM mezzanines (one big 4Mx48, one small 512Kx24)**
**Firmware**
**Software**
**Svtvme**
**Svtconfig**
**Svtsim**
**Monitoring**
**Integration**

## Final configuration

- AM++

- AM++

- AMS/
- RW

- HF

- HF

- HF

- AM++

- AM++

- AMS
- /
- RW

- HF

- HF

- HF

- n
- ewHB

- SVT
- tracking
- crate
- (2 wedges)

- n
- ewT
- F

- MERGER

- MERGER

- n
- ewHB

- n
- ewT
- F

- 12

- cables

- AMBUS slots

- to
- LVL2

- 1

## Year	   chip     boards    	     devel.   Total

- 2003?   120 kE	10 kE	(test b.)       5 kE	   135 kE
-      Ferrara    	10 kE (protot.)      30 kE	   40 kE
-         53 kE        100 kE (produc.)	             153 k
-             +40 kE					  +40 kE
- 		  +50 kE					  +50 kE
- 							+60 kE (MURST)
- 					Pisa
- Le Pulsar sono pagate dagli USA
- 	         totale secondo upgrade 310k$

## Slide 17

## Slide 18

## TEMPI DI REALIZZAZIONE

-  Nuova AM-board: inizio estate 2004 (Pisa)
-   	durante estate 2004: test con FPGA (Pisa)
-  Progetto prototipo AM-chip: luglio 2004 (Ferrara-Pisa)
- 	consegna chip ~2 mesi – disponibile ad ottobre.
-  Nuova LAMB: montare nuovo AM-chip a ottobre 2004 (Pisa)
-  test del chip + scheda: ottobre – dicembre  2004 (Pisa-Ferrara)
-  produzione: inizio 2005 (Pisa-Ferrara)
-  installazione: estate 2005 (Pisa-Ferrara)
-  	Altri DAQ/Trigger upgrade: previsti nel **2006**

- Road Warrior: 	. 	.	.	        (~60 k$ Fermilab)
- messa in opera entro fine 2003  F. Spinella      (in funzione)

##  Current schedule

- Apr/May: finalize AMSRW, AM++
- Apr/June:  TF test @ FNAL w/ teststand and beam
- May/July: HB tests and software development
- Apr/June: software development
- June/July: 1st AM++ board + AMSRW installation
- June/July: TF installation
- July/August: board rearrangement (get ready for HB)
- 				final MRG and GB to SVT08, SVT09
- August/September: HB installation
- Installation plan: different scenarios depending on which boards are ready first