# Presentation: 474476

## Hall DLevel 1 Trigger

- Dave Doughty
- 7/23/03
- Hall D Electronics Review

## Outline

- The Challenge
- The Architecture
- The Algorithm
- Real hardware – the link

## Hall D - The Numbers

- According to Design Report (Table 4.7 - 9 Gev)
- Tagged Photon Rate			300 MHz
- Total Hadronic Rate			365 KHz
- Tagged Hadronic Rate			  14 KHz
- Conclusions:
- Trigger needs better than 25-1 rejection
- “Tag event” is nearly useless in trigger

## Triggering

- Factor of 25 is tough
- Requires essentially “full reconstruction” to separate on photon energy!!
- Hard to design hardware “up-front” to do this
- Hard to do it in 1 pass
- Hard to do it fast
- Conclusion
- Do it in 2 stages - 1 hardware 1 software

## “Electronics” View of Trigger/DAQ

- Digital Pipeline

- Front End
- “Digitizer”

- FE/DAQ
- Interface

- Trigger

- Analog
- Data

- To ROC

- Event Block
- Buffers

- Every 64-256 events

- Every
- event

## Photon Energy Spectrum

*Photon Energy Spectrum*

## Cross Section

## Photon Rates

**Software-based**
**Level 3 System**

**Start @ 10****7**** ********/s**
**Open and unbiased trigger**
**Design for 10****8**** ********/s**
**     ****15 KHz events to tape**

**Level 1 trigger system**
**With pipeline electronics**

## Trigger Rates

## L1 Trigger – What do you want?

- Cut events with E < 2-5 GeV
- Some function of available params (energies, tracks)
- Minimum/Maximum/Exact number of tracks in:
- Start Counter
- Forward TOF
- Minimum or Maximum for energy in:
- Barrel Calorimeter
- Forward Calorimeter
- Complex function which incorporates all of these
- Time window for matches
- Output delay from trigger/timestamp match

## L1 Trigger – Why is it Hard?

- Lots of low energy photons with high cross sections
- At high tag rates, tagger doesn’t help
- Many final states are interesting
- Some are mostly charged particles
- Some are mostly neutral particles
-   p -> X(1600) n -> 0 + n-> n +  - +
-   p -> X(1600) n -> Eta0+  n -> n + 
-   p -> X(1600) 0 ->  +  - +  n 0 -> +  - + n  
-   p -> 0 p-> + - p

## L1 Trigger 

- Four separate subsystems
- Start Counter - compute number of tracks
- Forward TOF - compute number of tracks
- Barrel Calorimeter - compute energy
- Forward Calorimeter - compute energy
- Each subsystem computes continuously - at the pipeline rate of the FADC pipelines - 250 MHz
- 4 level computing hierarchy
- Board -> Crate -> Subsystem -> Global

## Timing

- Flight/Detector Time			  32 ns
- PMT latency				  32 ns
- Cables to FEE				  32 ns
- FEE to trigger out			  64 ns
- Crate sum				  64 ns
- Link to subsystem			128 ns
- Subsystem trigger processing		256 ns
- Transfer SER to GTP (64 bits)		256 ns
- GTP 					512 ns
- Level 1 output to FEE			128 ns
- TOTAL = 1.504 S - design FEE for 3 s (~768 stage)!

## Trigger Simulation

- Genr8 – create events
- HDGeant – simulate events
- hddm-xml – convert output to XML
- JAXB – create Java objects for XML description
- JAS – for analysis
- Function Optimization – for GLUEX

## Slide 15

## Particle Kinematics

- All particles

- Most forward
-      particle

******p****  ****→ ****X p**** ****→ ****K****+****K****─********+********─**** ****p**

## Reactions

- 12 datasets (~120,000 events)
- 4 Reactions simulated at 9 GeV
-   p -> X(1600) n -> 0 + n-> n +  - +
-   p -> X(1600) n -> Eta0+  n -> n + 
-   p -> X(1600) 0 ->  +  - +  n 0 -> +  - + n  
-   p -> 0 p-> + - p
- 3 of 4 are simulated at 1 and 2 GeV
- 2 Background Delta Reactions
- p -> n +
- p-> p 0

## Event Characteristics

- High Energy (9 GeV) Events
- More energy overall
- Greater fraction of energy in the forward direction
- Greater track counts in forward detectors
- Background (1-2 GeV) Events
- Less energy overall
- More energy in radial direction
- Track counts larger in side detectors

## Conditional Trigger

- Fairly successful formula:
- If Energy in Forward Cal < .5 GeV and Tracks in Forward TOF = 0
- Or
- If Total Energy < .5 GeV  and Forward Cal Energy < Barrel Cal Energy
- Cut

## Conditional Trigger Results

- Eval Score 0.786

- REACTION	TOTAL	CUT	   NOT CUT 	%CUT
- n3pi_2gev		10000	3088		6912		30.88
- n3pi_1gev		10000	4507		5493		45.07
- pro2pi_2gev	10000	4718		5282		47.18
- pro2pi_1gev	10000	6106		3894		61.06
- e2gamma_1gev	10000	4229		5771		42.29
- e2gamma_2gev	10000	5389		4611		53.89
- delta_npi+		10000	8199		1801		81.99
- delta_ppi0		10000	9773		227		97.73
- n3pi_9gev		9851		25		9826		 0.25
- e2gamma_9gev	9962		4		9958		 0.04
- pro2pi_9gev	9942		30		9912		 0.30
- xdelta_9gev	10000	50		9950		 0.50

## Functional Form

- Z >= TFM*TTOF + EFM*EFCal + RM*((EFCal +1)/(EBCal + 1))
- TTOF - Tracks Forward TOF
- EFCal - Energy Forward Calorimeter
- EBCal - Energy Barrel Calorimeter
- How do we decide what values to assign the coefficients and Z?
- Use a Genetic Algorithm (GA)
- Driving the GA
- if Background Event and is Cut  +1
- if Good Event and isn't Cut +5
- if Good Event and is Cut –50
- if Total number Good Events Cut > 50,  reset

## Results - Unchanged Energy

## Results

- The methodology works for simulated events
- Good Events:
- Cuts less than 0.5%
- Background Events:
- Average Cut: 72 %
- Range: 41% to 99.99%
- Varying hadronic energy deposition doesn't change results
- Tested with +- 20%

## Gluex Energy Trigger – Moving Data

- 250 MHz 8 bit flash ADC
- 16 (?!) Flash ADC channels/board
- 16 boards/crate -> 256 channels/crate
- 576 channels in barrel calorimeter -> 3 crates
- 2200 channels in forward cal -> 9 crates
- Energy addition in real time
- 256 8 bit channels/crate -> 16 bit sum
- If 256 12 bit channels/crate -> 20 bit sum
- Each crate must be capable of pumping 20 bits of data at 250 MHz or 625 MBytes/s

## Gluex Energy Trigger - III

## Link Features

- High speed > 625 MByte/sec
- Optical preferred
- More flexibility in trigger location
- No noise issues
- Easy-to-use interface
- “Daughter card” design might be good
- Minimizes layout issues of high speed signals if a single, well tested,  daughter card design is used.

## S-Link	

- An S-Link operates as a virtual ribbon cable, moving data from one point to another
- No medium specification (copper, fiber, etc.)

- 32 bits
- 40 MHz
- 160 Mbytes/s

## HOLA at JLAB = JOLA

- Cern’s HOLA Slink card – used in numerous places
- Uses TI TLK2501 for higher speed serialization/deserialization
- Data link clock is 125 MHz (@ 16 bits)
- Data link speed is 250 MBytes/s
- Actual throughput is limited by S-Link to 160 MBytes/s
- Obtain license from CERN
- Fabricate our own JOLA boards.
- Test JOLA S-Link cards using existing text fixtures:
- SLIDAD (Link Source Card)
- SLIDAS (Link Destination Card)
- SLITEST (Base Module)

## S-Link Testing

## Test Setup (SLITEST) - Base Module

## Setup Continued... (JOLA)

## Setup Continued (Source Card)

## Setup Continued (Destination Card)

## JOLA Status

- It works!
- Initial testing shows that both of the S-Link ends (LSC & LDC), are correctly sending/receiving the data.
- Further testing will be aimed to:
- Enhance understanding of the S-Link Protocol
- Determine the BER (bit error rate) of the link

## S-Link64

- The S-Link cannot keep up.  It has a throughput of 160 MBytes/sec, and we need at least 500 - 650 MBytes/sec.
- The S-Link64 is an extended version of the S-Link.
- Throughput:   800MBytes/sec
- Clock Speed: 100MHz
- Data size: 64 bits
- Second connector handles extra 32 bits

## The next step...JOLT (Jlab Optical Link for data Transport)

- S-Link64 will work for us, but a copper cable with a 10 m cable length will not.
- Xilinx’s new V-II Pro offers nice features for next gen.
- The V-II Pro chip can replace both the Altera FPGA as well as the TI TLK2501.
- Incorporates PowerPC 405 Processor Block
- Has 4 or more RocketIO Multi-Gigabit transceivers
- Each RocketIO has 3.125 Gbps raw rate -> 2.5 Gbps data rate
- 10Gbps  (1.25 Gbyte/s) if 4 channels are used.
- The full S-Link64 spec requires 3 lanes
- Error correcting will likely require 4 lanes

## JOLT – 1 and JOLT -2

- JOLT will give a crate-to-crate transfer rate of 4 x 2.5 Gbit/s or well in excess of S-Link64 spec of 800 Mbyte/s
- First design is Slink (Jolt-1)
- One lane version
- Easily testable with current support boards
- Second design is Slink-64 (Jolt-2)
- CERN is interested in our development.

## Conclusion

- Have an algorithm and rough design for the Level 1 trigger
- Have simulated the algorithm for Level 1 with good results
- Have a roadmap to get to very high speed links supporting fully pipelined Gluex triggers
- Borrows liberally from existing designs.  Is technically feasible today
- All we need is CD0!