# Presentation: 674681

## 
CDF Run II Silicon
Tracking Projects

8th INTERNATIONAL WORKSHOP ON VERTEX DETECTORS
Texel, Netherlands
 20-25 JUNE 1999

Presented by 
Alan Sill
Department of Physics
Texas Tech University

- CDF Run II Silicon
- Tracking Projects
*8th INTERNATIONAL WORKSHOP ON VERTEX DETECTORS*
*Texel, Netherlands*
* **20-25 JUNE 1999*
*Presented by *
*Alan Sill*
*Department of Physics*
*Texas Tech University*

## Slide 2

## Goals for CDF Run II Silicon

**Previous CDF vertex detectors covered interactions within |z| < 0.27 m, New silicon detectors designed to cover |z| < 0.43 m**
**Interaction region expected to be more concentrated in z in Run II**
**Increase silicon angular acceptance to cover approximately ******** ******** 2. **
**Overall effect should be approximately a factor of 2 increase in acceptance for particles with good tracking and vertexing**
- Improve top tagging for high-pT physics:
- Improve B physics capability of the experiment

## CDF II Detector - Run II Configuration

## Quadrant of CDF II Tracker

- LAYER 00

## Fermilab Run II Silicon

## CDFII Silicon Tracker: Layer 00 + SVXII + ISL

_*Goals and Features*_*:*
- Precise 3D track impact parameters
**B tagging: top, SUSY, Higgs**
**B Physics**
-  Improved forward coverage
**0 ******** ******** ********  2**
- Level II displaced-track trigger (SVT)
**Hadronic B decays**
**Calibration triggers**
- Improved pT resolution
- High tracking efficiency with good purity

## SVX3D R/O Chip

- Rad-hard 0.8 um Honeywell CMOS
- Tested to ~ 4 MRad
- Deadtimeless

- Dynamic pedestal subtraction
- Common to all Run II CDF silicon projects

## SVX3D R/O Chip

## Readout Chip Specifications

- *

## SVX II Collaboration

## SVX II: 3 Barrels, 5 Layers 

## SVX II vs. Previous Detector

## SVXII Parameters

## Silicon Specifications

- SVX II silicon sensor specifications for
- Hamamatsu (90o layers 0,1, 3) and
- Micron (1.2o layers 2, 4)

- *

## SVXII Barrel Fabrication

- Fixture for installing SVX II ladders into barrel (precision aligned bulkhead pair)

- Test assembly with mock aluminum  bulkheads and mechanically accurate ladders

## SVX II Ladders

- SVX II half ladder, consisting of two silicon
- sensors wirebonded with the readout
- electronics mounted on the first
- sensor.

## Layer 00 Collaboration

**FNAL, INFN-Pisa, INFN-Padova, **
**LBNL, Purdue,U.California-Davis, **
**U. Florida, U. Glasgow, U. Liverpool **

## Layer 00

- Beam pipe layer of 1-Sided Silicon
**Improve IP resolution**
- Better B tagging for higgs, SUSY
**Extend useful lifetime **
**Long-term operational experience with LHC rad-hard silicon**

**Resolution improvements:**

## Layer 00 Design Values

## Layer 00 in SVX II

- 2.2 cm

## ISL Collaboration

**FNAL, INFN-Pisa, INFN-Padova, **
**INFN-Bologna, LBNL,Texas A&M, **
**U.California-Davis, U.California-Los Angeles,**
**U. Cassino, U. Florida, U. Karlsruhe, **
**U. Rochester,U. Tsukuba, Osaka City University **

## Intermediate Si Layers

- CDF ISL: Proposal and Conceptual Design (FNAL). Final Design (Pisa).
**Emphasis on simplicity and low cost. **
- Space frame manufactured in Italy; INFN Pisa & FNAL are the main production sites (roughly half each).

## ISL Modules

- Overview of Design
**C Fiber substrate**
- All bond pads are accessible from both sides
**3 Sensors**
- 112 m pitch (both sides)
- Double Sided 1.2o Stereo Angle
**Hybrid mounted off Silicon**
- 8 readout chips per hybrid
- Module Production
**Mechanical Fabrication:**
- less than 2 hours
**Wirebonding:**
- 20 minutes per side 	(roughly 1 hour total w/setup)
**Testing & Repair**
- Under study

## ISL Ladder Assembly

- Pilot production ladders
**Karslruhe fixtures refined w/use**
- Hybrids
**Expect all substrates end of summer**
**Prototypes operate as expected**
**Final assembly limited by SVX3D availability**

## CDF Run II DAQ

- Fully pipelined DAQ+Trigger architecture (396 -->132 ns)
- Operates “deadtimeless”
- One of our largest subprojects
- Total board count  >15,000.
- ~100 different  custom boards
**~ 35 High volume   boards (qty >100)**
- For SVX3D,  everything up to L1 accept is on the chip
- SVT (not covered here) provides L2 displaced-track trigger

## Silicon DAQ

- *

## SVXII DAQ

## ISL DAQ

- each HDI (and DOIM) has 16 chips
- — 4 per side on each of two ladder ends

- *

## Final Assembly / Installation

## Simulation: Run II CDF Si

- Open Inventor based

- ROOT based

## Expected Performance

- Reported previously for SVX II, ISL
- Improvements with L00:

- Good overall
- top tagging

- Improved IP
- resolution

- More tracks
- In top b tag

- Should survive
- ~10 MRad

## Conclusions

- SVXII + ISL + L00 design provides complete silicon tracker that should give robust performance throughout Run II
- Silicon on track for complete delivery by early to mid 2000
- Hybrid substrates complete (SVXII) or will be soon (ISL, L00); population in progress
- SVX3D chip provides rad-hard deadtimeless operation
- _PROBLEMS_:
**Slow delivery of some silicon has delayed sensor production**
**Yield problems and other difficulties with Honeywell SVX3D**
**Infancy failures of some chips**
- _SUCCESSES_:
**Overall the projects are on track**
**Many problems solved**
**Installation sometime in 2000 should be possible**