# Presentation: 248980

## TTF2/XFEL RF Station Interlock Architecture

**Holger Leich**
**DESY Zeuthen**

** ****Joint project: DESY Hamburg and DESY Zeuthen**
** ****People involved:**
**S. Choroba,** **T. Grevsmuehl, J. Kahl**, **F.R. Kaiser,**
**K. Rehlich,** **O. Hensler**, **S. Simrock, H.J. Eckoldt**
**(****DESY at Hamburg** **)**
**A. Kretzschmann, H. Leich, U. Schwendicke, R. Wenndorff,**
**G. Trowitzsch, S. Weisse**
**(DESY at Zeuthen)**

- TTF2/XFEL Interlock Architecture

## Sources of Interlock Error Signals

-  Hard component failures (non-reversible hardware malfunction)
- --> broken cable or damaged contact, dead sensor, ...
-  Soft errors (e.g. sparks in the klystron or wave guide system,
- temperature above a threshold, ...)
-  Error conditions caused by transient noise from the RF station itself

**Main Task of the Interlock Sytem**

- --> Guarantee operator /other persons safety
- --> Prevent any damage from the cost expensive components of the RF station
- --> Prevent also any damage from other environment

- TTF2/XFEL Interlock Architecture

## Components of a TTF2/XFEL RF Station

**HV Power Supply**
- Provide the input voltage of 0-12 KV to the capacitor bank of the Modulator
**Modulator**
- Discharges a fraction of the energy stored in the capacitor bank into the pulse transformer. A bouncer circuit will ensure that the 120 kV high voltage output pulse will be flat i.e. voltage drop will not exceed some predefined level.
**HV Transmission Line**
- Connects the Modulator with the pulse transformer.
**Pulse Transformer**
- Transforms the 12 kV, 1200 A pulse generated by the Modulator into a 120 kV, 120 A pulse driving the Klystron cathode voltage.
**Persons and machine safety systems**
- Several personnel and machine safety systems are interacting together to provide a safe operation of the whole system
**Low Level RF System (LLRF)**

- TTF2/XFEL Interlock Architecture

## Interlock System Architecture

- Analog Process Input

- Sensor

- Sensor

- Components of the RF Station

- Process Analysis

- Digital Process Input

- Output to Process

- Analog  Output

- Digital Output

- Adapter Unit

- Adapter Unit

**Interlock System Architecture**

- Interlock Controller

- Higher Level Control System

- Strictly hierarchical Architecture

- TTF2/XFEL Interlock Architecture

## TTF2/XFEL Interlock Subsystems

**Interlock**

**Persons**
**Interlock**

**SPS**
**Laser**
**Interlock**

**DOOCS**

**Gun**
**Interlock**

**SPS**
**Beam**
**Inhibit**
**System**

**Profibus connection**

**Low**
**Level RF**

**Modulator**
**Interlock**

**SPS**
**Modulator**

**RF-Leakage**
**Detection**

**GUN**
**Solenoid**
**Magnets**

**Cabel connection**

**LightLink**

**TTF2/XFEL Interlock Subsystems**

- TTF2/XFEL Interlock Architecture

## Interlock Inputs

-  Digital Inputs
- - Oil levels
- - Cooling water flow
- Vacuum pump current
-  Analog Inputs
- - Oil temperature
- - Cooling water temperature
- - Klystron Filament voltage & current
- - Solenoid voltage & current
- - SF6 gas pressure

- TTF2/XFEL Interlock Architecture

## Interlock Inputs / Outputs

-  Inputs from other Subsystems
- - Persons interlock
- - RF leakage detector
- - Modulator ready
- - Gun interlock
- - RF system ready
-  Interlock Outputs
- - Modulator on/off
- - Heater power supply on
- - Klystron solenoid power supply on
- - RF enable

- TTF2/XFEL Interlock Architecture

## Response Times

-  Ultra Fast (UF):	Rt < 1 μs
-  Fast (F):		Rt = 1 ... 5 μs
-  Normal (N):		Rt > 5 μs
- --> Actual implementation only N and F
- --> ca. 70 signals to process, number increasing

- TTF2/XFEL Interlock Architecture

## The Implementation

****** ****3U-Eurocard board format with two 5-Row connectors (CPCI type): 125 + 110 = 235 pins**

** ****enough pin resources per slot and to build a compact interlock/control system**
** ****Front-to-rear connections:****	****	****	****	****40 Pins**
** ****Control Bus:****	****	****	****	****	****50 Pins**
** ****Time Multiplex Bus:****	****	****	****	****16 Pins**
** ****Service Request lines:****	****	****	****	****20 Pins (one per slave slot)**
** ****Direct Digital Out:****	****	****	****	****	****24 Pins**
** ****Service Request Lines:****	****	****	****	****20 Pins**

**Data throughput:  **
** ****Control Bus:****	****	****	****	****	****15 MBytes/s**
** ****Time Mux Bus:****	****	****	****	****	****updates 128 Interlock ****	****	****	****	****	****	****Status Signals within 1****μ****s**

**The Implementation**

- TTF2/XFEL Interlock Architecture

## ...

- Hardwired Interlock Logic

- 32 Bit RISC CPU
- (NIOS-II)

- Slave Expansion Board (optional)

- Interlock Controller

- Backplane

- Processor Bus, Interrrupt and misc. Busses

- Pure Hardware

- Progr. Processor

**Architecture Overview**

- Interlock Status Bus

- TTF2/XFEL Interlock Architecture

## Structure of the Interlock Crate Bus System

- TTF2/XFEL Interlock Architecture

## Bus Timing

- D(2)

- D(1)

- D(0)

- D(0)

- D(0)

- 3

- 2

- 1

- 0

- BCLK

- ADDRi

- ADDRj

- Data Out

- Data In

- SRVRQ_l

**Bus Timing**

** ****Time Multiplex Bus**

** ****Control Bus**

** ****Service Request/Direct IO Bus**

- Direct_DO

- TM_addr

- BCLK

- TM_data

- INIT_l

- WE_l

- CTRL_addr

- BCLK

- CTRL_data

- TTF2/XFEL Interlock Architecture

## Interlock Crate: Layout

**Slotnumber:**
**0   1   2   3   ......                            19   20**

- Controller

- side B
- -CPCI Form
- -cable outlet

- side A
- -inverted CPCI connector
- -no cables !

- handle

- TTF2/XFEL Interlock Architecture

## Components to be tested:

- Controller
- Backplane
- Slaves (all installed)
- Power Supply modules and Fans

**Interlock Selftest**

- TTF2/XFEL Interlock Architecture

## Constraints

- After reset a test of all components is performed using a special Test Mode (System Test). Two dedicated bus lines (SysTest_A and SysTest_B) control the operations in this mode.
- If SysTest was successful the system enters the normal Interlock Mode
- In Interlock Mode all components, which are accessible from the CPU, can be tested (e.g. periodically when the HV pulse pauses)
- Simple logic – let the Controller CPU do most of the jobs

- TTF2/XFEL Interlock Architecture

## Implementation

- SysTest_B controls a MUX, which maps TMadr into the address space of the CPU

- TTF2/XFEL Interlock Architecture

## Implementation constraints

- The memory address mapping of all Slaves has to be follow certain rules:
-  the adddress space of the external bus interface: 0 ... FFFFFF is divided into a User and an ICS (Identification Control and Status) & Systest region

- ICS & SysTest
- User

- FFFFFF
- FF0000
- 000000

- TTF2/XFEL Interlock Architecture

## Each modul is assigned a fixed station number. In the interlock crate it must reside in the slot which corresponds to its station-No. 
Adr[23..19] == station-No. inside the user region
Adr[23..13] == 1111 1111 110, A[12..8] == station-No. in the ICS-region

- Adr[23..19] == station-No. inside the user region
- Adr[23..13] == 1111 1111 110, A[12..8] == station-No. in the ICS-region

| System Test space of Module @ Station 20 | FFF400-FFF4FF |
| --- | --- |
| ... |   |
| System Test space of Module @ Station 2 | FFE200-FFE2FF |
| System Test space of Module @ Station 1 | FFE100-FFE1FF |
| reserved for future use | FFE000-FFE0FF |
| Not used |   |
| ICS space of Module @ Station 20 | FFD400-FFD4FF |
| ... |   |
| ICS space of Module @ Station 2 | FFC200-FFC2FF |
| ICS space of Module @ Station 1 | FFC100-FFC1FF |
| reserved for future use | FF0000-FFC0FF |
| reserved for special applications | B00000-FEFFFF |
| address space for Slaves | 080000-AFFFFF |
| reserved for future use | 000000-7FFFFF |

**Implementation constraints (cont.)**

- TTF2/XFEL Interlock Architecture

## Modul ID Structure

| Field type | Field name | Field length
(byte) | example |
| --- | --- | --- | --- |
| Binary | Station number | 1 | 18 |
| Binary | A/B-side flag | 1 | 1 (B-side) |
| ASCII | module name | 24 | Controller |
| ASCII | Version # | 8 | 1.2 |
| ASCII | Prog. File name | 24 | Intlk3_cntrl.pof |
| ASCII | Prog. File date | 8 | 051103 |

**Modul ID Structure**

- TTF2/XFEL Interlock Architecture

## Controller Architecture

**External Devices **

**NIOS-II**
**32-Bit RISC CPU**

**Internal SPI Interface**

**Hardwired Interlock Logic**

- Flash Memory
- 32 MByte

**Cyclone-II **
**EP2C35F484-C7**

- Data Bus

**Interlock **
**Direct Data Out**

**Time Mux Bus :**
**Address Out **
**Data In**

**Cntrl Bus:**
**Address Out**
**Strb,We**
**Data I/O**

**Interlock Bus Interfaces:**
**Control Bus, Time Multiplex Bus**
**Service Request lines, ...**

- Address Bus

- SDRAM
- 64 MByte

- RTC
- (connected to  SPI)

- Ethernet Controller

- 256 KByte MRAM

**Controller Architecture**

**Interlock **
**Service Request**

**Read Interlock Status, Channel masking, ...**

- TTF2/XFEL Interlock Architecture

## 
      The 32-bit RISC processor on the Controller board performs all necessary control functions to all slave modules in the interlock crate. The interface to the DOOCS Control System is implemented via Ethernet. A TINE server runs on the NIOS processor and provides an interface to a DOOCS client.

All status information and all mask data will be accessable as properties in the context of TINE
All actual values of analog input channels are implemented as properties
All commands to the interlock crate (to the controller) are implemented as DOOCS properties and may be issued by a DOOCS client
The actual values of the data mentioned above are stored in the DOOCS History Format

-       The 32-bit RISC processor on the Controller board performs all necessary control functions to all slave modules in the interlock crate. The interface to the DOOCS Control System is implemented via Ethernet. A TINE server runs on the NIOS processor and provides an interface to a DOOCS client.
- All status information and all mask data will be accessable as properties in the context of TINE
- All actual values of analog input channels are implemented as properties
- All commands to the interlock crate (to the controller) are implemented as DOOCS properties and may be issued by a DOOCS client
- The actual values of the data mentioned above are stored in the DOOCS History Format

**Interface to the higher level Control System**

- TTF2/XFEL Interlock Architecture

## A Fail-safe timer on the controller monitors the TINE-server operations. After it times out (if the TINE server hangs up or as a result of a special TINE command) a Web-Server is started automatically. 

The Web-server provides access to all system resources (status, masks, analog channels) but also provides the possibility to upload new software onto the controller and to reprogram the serial flash device which holds the actual FPGA configuration. 

Only authorized users are able to change flash content (program flash or FPGA configuration flash) and/or perform reset operations (Hard- or Soft-reset)

- The Web-server provides access to all system resources (status, masks, analog channels) but also provides the possibility to upload new software onto the controller and to reprogram the serial flash device which holds the actual FPGA configuration.
- Only authorized users are able to change flash content (program flash or FPGA configuration flash) and/or perform reset operations (Hard- or Soft-reset)

**Web-Server for debugging and maintenance**

- TTF2/XFEL Interlock Architecture

## Slave Module Overview

**Digital IO Light Link**
- Versatile Link (VL)- or ST- Connectors
- Basic card: 4x Input + 4x Output + max. 2 piggyback‘s
- piggyback: 	either 	8x Output (VL)
- 		or 	8x Input (VL)
- 		or	4x Input & 4x Output (VL)
- 		or	3x Input & 3x Output (ST)

- TTF2/XFEL Interlock Architecture

##  Digital Input/Output Module

** ****Digital Input/Output Module**

-  8 Input Groups: 2 groups with 8 channels and 6 groups with 4 channels per group:
-  Input Voltage Range: –14 V to 40 V;
-  Switch Detection Threshold: typical 3.75 V
-  Programmable Wetting Current
-  4 programmable inputs per group to Monitor 4 Switch–to–Battery or 4 Switch-to-Ground Switches
-  2 Output Groups with 4 channels per group:
-  RDS(ON) of 0.55 Ω  (typical)
-  Outputs are current limited (0.8 A to 2.0 A) to drive incandescent lamps
-  Output voltage clamp is +45 V and -20 V (typical) during inductive switching.
-  Short circuit detect and current limit with automatic retry
-  Independent over-temperature protection
-  Each group is DC-decoupled from all other groups and the rest of the board
-  The module incorporates an interface to the interlock hardware

- TTF2/XFEL Interlock Architecture

##  Analog Input/Output Module

-  **Analog Input/Output Module**

-  4 groups of 4 channels each:
-  2 output channels (based on a 16 bit DAC) and 2 input channels (based on a 16 bit ADC)
-  Voltage range for input and output is 0 ... 10V
-  Outputs are buffered to drive 600 Ω loads
-  Conversion time is: tbd
-  integrated self test possibility: each voltage output can be connected (via an analog switch) to a corresponding voltage input
-  Each group is DC-decoupled from all other groups and the rest of the board

- TTF2/XFEL Interlock Architecture

##  Analog Input Module with Window Comparators

-  36 analog inputs; 32 of them are fed via programmable window comparators
-  two versions:
-  current input: 4...20 mA; 	Label **A**
-  voltage input: 0...+10 V; 	Label **V**
-  Sample rate: all 36 inputs are updated within 1 ms
-  Sensor excitation from internal +12 V; optional +24 V
-  Accuracy : ± 0,5 K guaranteed, typically better than ± 0,1 K
-  Resolution for interlock : 0,1 K
-  Drift with temperature : < 100 ppm  which is 0,1 % /  10 K, not compensated
-  access to all data and control registers via the **Control Bus**
-  This module incorporates an interface to the interlock hardware

- TTF2/XFEL Interlock Architecture

## Interlock Crate with Backplane

- TTF2/XFEL Interlock Architecture

## Interlock Controller Board (Prototype)

- TTF2/XFEL Interlock Architecture

## Light Link IO Board (Prototype)

- TTF2/XFEL Interlock Architecture