# Presentation: 177356

## A Unified Approach toFast Digital Processing for Beam Dampers, Instrumentation, & Controls

- Bill Foster
- July ‘02

## What’s the Scoop?

- 1)  Fast, High Precision Pipelined ADC’s
- AD6645:   14 Bits,  105 MHz,   SNR 72+ dB
- AD9430:   12 Bits,  210 MHz,   SNR 65+ dB
- 2)  Fast , huge FPGA’s
- e.g. Altera Stratix & Apex devices
- Pre-built DSP blocks including 250 MHz digital filters
- > 20 GMAC/s  per chip
- 10 Mbits on-chip RAM,  1 Gbit/sec/pin digital I/O
- glueless LVDS interface to fast ADCs

## Generic Hardware Concept for Accelerator Instrumentation & Control

- Monster
- FPGA

- 53 MHz, TCLK, MDAT,...

- Minimal
- Analog
- Filter

- FAST
- ADC

-  Cables
-   from
- Tunnel

- Minimal
- Analog
- Filter

- FAST
- ADC

- .
- .
- .

- .
- .
- .

- .
- .
- .

- FAST
- DAC

- 14

- _CPU Bus_
- VME/
- VXI/
- PCI/
- PMC
- etc.

- _INPUTS:_
- BPM
- Stripline Pickup
- Resistive Wall
- Flying Wire PMT
- RF Fanback
- Kicker Monitor
- ...etc.

- _OUTPUTS:_
- Stripline Kicker
- RF Fanout
- Analog Monitor
- ...etc.

## Five Example Applications using this same basic hardware:

- 1) Universal Beam Position Monitors (BPMs)
- Handles full variety of FNAL beam RF structure
- 2) Generic instrumentation readout “Scope”
- ex: Flying Wire readout for arbitrary bunches
- 3) Recycler / Injection Damper (fixed frequency)
- Bunch-by-bunch, narrow band, or both at once.
- Transverse and Longitudinal
- 4) Beam Loading Compensation
- 5) Universal Beam Dampers / Beamline Tuner

## You can (basically) buy this...

- Prieto, Meyer et. al. evaluating 65MHz DDC for RR BPM upgrade
- Asmanskas, Foster purchasing 105 MHz version for RR Dampers

- Board similar to this originated at SLAC
- Local users: Prieto, Meyer, Voy & Co.
- Digital Down Conversion Chip implements specific filtering algorithm (many parameters)
- Same chip used by Chase et. al. on board for e-cooling BPM with excellent results
- Echotek Board Includes medium-sized FPGA & Output FIFO,   (can bypass DDC chip)
*It is possible that we can do everything            we need inside the FPGA, without DDC chip.*

- Echotek ADC / DDC Board

## Slide 7

## Slide 8

## AD6645 Functional Block Diagram

- Two-Stage Pipelined ADC
- Internal Track & Hold
- Differential Analog Inputs

## Slide 10

## Application #1: Universal BPM(Beam Position Monitor)

- Measures position of each bunch on each pass around the ring with full-bandwidth FIR filter
- (R-L)/(R+L) for each bunch measurement.
- Multi-bunch averages available for lower noise
- per batch, per turn, many turns, different bandwidths
- Multiple users can share hardware w/o conflicts
- ADC is always active, FPGA stores data many ways
*Same Hardware OK for Booster, MI, RR, TeV, & beamlines.*

## “Universal BPM”  Hardware

- “Universal BPM”  Hardware

- Monster
- FPGA(s)

- 53 MHz, TCLK, MDAT,...

- Minimal
- Analog
- Filter

- ADC

- Split Plate
- Pickup  #1

- Minimal
- Analog
- Filter

- FAST
- DAC

- 14

- _CPU Bus_
- VME/
- VXI/
- PCI/
- PMC
- etc.

- Minimal
- Analog
- Filter

- Minimal
- Analog
- Filter

- 106 MHz

- Pickup #4

- Analog Position Monitor
- Test Point  (Optional)

- ADC

- ADC

- ADC

- .
- .
- .

- .
- .
- .

- R

- L

- T

- B

## Appropriate Digital Filtering can deal with all these Bunch RF Structures

***Appropriate Digital Filtering can deal with all these Bunch RF Structures***

## “Universal BPM” Application: Signal Processing Steps

- 1)  Bandwidth-Limit input signal to ~53 MHz
- 2)  14 Bit Digitization at 106 MHz / 212 MHz
- 3)  FIR filter(s) to get single-bunch signal(s)
- 4)  Sum & Difference of plate signals
- 5)  (Difference / Sum) gives position
- 6)  Linearization lookup table or polynomials
- 7)  Bunch, Batch, Multiturn Averaging
- 8)  “Scope Trace Buffers” on every signal
***Multiple users can be acquiring and filtering data multiple ways without conflicts***

- Inside
- FPGA

- Echotek
- Board

## “Universal BPM” Signal Processing Step #1:  Bandwidth Limit Signal

- Raw signal has high-frequency components which can cause signal to be missed by ADC
-   “Aliasing”
- Bandwidth limited signal (to ~53 MHz) cannot be missed by 106 MHz ADC
-   Example: Gaussian Filter
- Eliminate low-frequency ripple, baseline shifts, etc. with Transformer or AC coupling
- Digital Filtering can provide additional rejection

## BPM Signal Doublet

- Positive signal as image charge arrives, negative as it leaves  ==> Bipolar Doublet

***This signal is***
***too fast - can ***
***be missed by ***
***100 MHz ADC***

## Signal From Long Stripline

- If Stripline Length > Beam Pulse Length,
- we get two separate opposite-polarity pulses

## If Beam Pulselength > Pickup Length

- Shape is ~ the derivative of the beam current.
- Pulse height is reduced:  VOUT ~ 1/(FWHM)2

***This type of signal sets      low end of Dynamic Range***

## Gaussian Filter - Impulse Response

- Many implementations,   e.g.  traversal filter

***Spreads signal +/-5ns in time so it will not be missed by ADC***

***Reduces ADC Dynamic Range requirement, since spike does not have to be digitized***

## Gaussian Filter - Doublet Response

***Filtered Signal can be sampled by 100 MHz ADC***

***Filtered Output Pulse Shape is insensitive to Bunch Length***
***(for Tb < 10ns)***

***Digitized Pulsehight is “A - B”***

## Gaussian Filter - Pulse Train Response

***Filter Output is good sine wave independent of bunch length***

***“******A - B”***
***still gives good bunch-by-bunch measurement***

***Can digitally average over many bunches in a batch to get lower noise***

## Analog Filter Design is Complicated!

- Tradeoffs between sharpness of frequency cutoff and propagation delay spread
- Gaussian filter chosen here for no good reason
- Echotek board uses hybrid lowpass filter module from Mini-circuits.  Is this what we want?

***Cutoff is Sharper than Gaussian***

## “Universal BPM” Signal Processing Step #2:  Analog-Digital Conversion

- _What ADC Clock Speed is needed?_
- ~53 MHz Bandwidth limited signal,  sampled by 106 MHz ADC, measures _either_ *in-phase* (cosine) _or_ *quadrature *(sine) component
- but not both ==> ADC clock phasing matters!
- 212 MHz sampling measures _both_ *in-phase* _and_ *quadrature* components.  *Phasing is not critical* to determine vector magnitude.

## In-Phase and Quadrature Sampling

***“******A - B”  gives bunch-by-bunch “in-phase” signal***

***Vector Sum ***
***sqrt(I**2 +Q**2)  is insensitive to clock jitter***

***“******D - (C+E)/2”  gives ***
***bunch-by-bunch “out-of-phase” quadrature signal***

- This is the argument for sampling at 2x Nyquist

## This ADC can sample 53 MHz signals at 4 samples per cycle

- to measure both In-Phase and Quadrature on each cycle

## Synchronous vs. Asynchronous ADC Sampling

- The choice is between N*53 MHz beam phase locked sampling, or asynchronous sampling at a (possibly) lower rate
- Asynchronous sampling of a waveform will allow you to recover all the information, IF:
- you know that the input is a pure sine wave, or
- you know the input is repetitive (stored beam), or
- the sampling rate is much higher than fMAX

## The Perils of Undersamplinga Single-Pass Beam

***If a single-pass beam does not have uniform bunch populations, the ADC input is NOT a good sine wave and an undersampled waveform can give an erroneous picture of the beam signal.***

***The signal CAN be reconstructed with many passes of stored beam.***

## Conclusions on ADC Clock Rate

- A *Universal* BPM system must sample at      2-4x the maximum bunch frequency, depending on whether we want to guarantee the clock phase stays aligned or not.
- You can never be:
- too rich
- too thin
- or have too many ADC samples

## “Universal BPM” Signal Processing: How Many ADC bits are needed?

- _Biggest Signal:_ Coalesced Proton Bunch
-  350E9 particles in single ~10ns bunch
-  if bunch is shorter, doesn’t matter, filter will spread it
- _Smallest Signal:_  Antiproton Pilot Shot at 2.5 MHz
- 10E9 particles/bunch in four ~50ns bunches
- this gives ~25x smaller pulse height than same number of particles in 10ns bunch, but ~5x smaller pulse area
- Off-center beam positions require an additional  4:1 dynamic range  (maybe less with hybrid)

## Biggest Signal in Main Injector

*Coalesced bunch  *
*puts ~350E9*
*in single  *
*53MHz Bucket*

*Bunch length will be ~3ns at transition *
*with GPJ low emittance coalescing. *

## No guarantees on bunch populations    or individual bunch transverse positions

*No guarantees on bunch populations    or individual bunch transverse positions*

## ADC Dynamic Range(Main Injector, which is worst case)

- Set up so 14 Bit ADC (16k counts) almost saturates for full scale hit from coalesced bunch (300E9)
- Lose factor of 30 = (10E9/300E9) for bunch charge of Antiproton Pilot Shot
- Lose Factor of 25 for pulse height of 50ns bunch vs. 10ns bunch    ==> 21 counts per sample
- Signal from 4-bunch pilot shot shows up in ~40 samples ==>800 counts if beam centered in BPM
* **ADC bit noise is sub-mm contribution to resolution*

## “Universal BPM” Signal Processing Step #3:  Digital Filter

- Many Filters can operate in parallel in FPGA
- single Bunch FIR filter (weighted sum of samples)
- single Batch filter (53 MHz, 2.5 MHz, 7.5 Mhz)
- Multi-pass averaging (can extract all harmonics of revolution frequency for stored beam)
- Automatic peak-finding or calculation of I**2+Q**2  to make timing less critical
- Waveform capture allows filters to be debugged & optimized & new versions tested *offline*

## “Universal BPM” Signal Processing Step #4,5,6:  Beam Position Signal

- 4)  Calculate Sum & Difference of plate signals
- Traditionally done in analog “Σ-Δ” Hybrid
- This saves 1-3 bits of dynamic range for ADC
- 14-bit ADC dynamic range OK without Hybrid
- 5)  (Difference / Sum) gives position
- 		X ~ (Right - Left) / (Right + Left)
- 6)  Linearization lookup table or polynomials		(X,Y) CALIBRATED = F(XRAW, YRAW)

## Main Injector BPM Response Map

***Linearization can be done in FPGA ***_***or***_*** readout software***

***J. Crisp***

## “Universal BPM” Signal Processing Step #7:  Averaging and Filtering 

- Many Types of averaging possible:
- 	Position Averaging over Bunches in a Batch
- 	Multi-Turn Averaging of Positions
-     Multi-turn averaging of Raw Signals
- 	Fitting to betatron frequency (injection errors)
- 		- this gives info for -function measurement
- 	Emulation of DDC chip functions
- 	Spectrum analysis of position & phase
*Different filters can be simultaneously active*

## Application #2:   Generic Instrumentation Readout Scope 

_**What we want in a  “Generic ‘Scope”:**_
- 1) Ability to trigger on TCLK events, Beam Synch Events, analog threshold crossings of different channels, etc.
- 2) Multiple Users Sharing without conflicts
- 	- separate copies of trigger logic
- 	- separate buffers to store captured signals
- 	- separate filter algorithms run simultaneously
- 3) Common hardware & software among systems

## Example Application of Generic ‘Scope:  Flying Wire PMT Readout

- Monster
- FPGA

- 53 MHz, TCLK, MDAT,...

- Minimal
- Analog
- Filter

- FAST
- ADC

- PMT(s) in Tunnel

- Minimal
- Analog
- Filter

- FAST
- ADC

- DAC

- 14

- _CPU Bus_
- VME/
- VXI/
- PCI/
- PMC
- etc.

- Minimal
- Analog
- Filter

- FAST
- ADC

- Minimal
- Analog
- Filter

- FAST
- ADC

- 106 MHz

- Encoder Signals

- Motor

- Motor Drive

## Example Application of Generic ‘Scope:  Flying Wire PMT Readout

- Photomultiplier Tube (PMT) pulses presented to Analog filter to limit BW
- Summing circuits in FPGA give total PMT pulse height in narrow and wide gates
- Individual gates report signals for 36x36 or more bunches, average over many turns, etc.
- FPGA can be used to control & trigger the fly
- Raw PMT pulses can be simultaneously looked at via “multi-user” hooks

## Application #3:  Recycler / Injection Damper

- Fixed revolution frequency simplifies design.
- Measures position of each “bunch” on each pass,  then kicks it back on center.
- Same circuit usable for Injection Dampers, which also operate at fixed frequency.
- Digital multi-turn filters used to calculate kick.
- Narrow-band and Broad-band filters can run simultaneously on same device, if needed.

## Analog Beam Damper SystemSimplified schematic of narrow band Transverse Damper for 53 MHz bunched beam

- Move from Analog to Digital
- Processing inside FPGA

- -

- Power Amp (Buy / Exists)

*McGinnis*

*The Digital system can exactly emulate this,  plus run other algorithms for various bunch structures.*

## “Recycler / Injection Damper”(same generic hardware)

- Monster
- FPGA

- 53 MHz, TCLK, MDAT,...

- Minimal
- Analog
- Filter

- FAST
- ADC

- Stripline
- Pickup
- “A”

- Minimal
- Analog
- Filter

- FAST
- ADC

- FAST
- DAC

- 14

- _CPU Bus_
- VME/
- VXI/
- PCI/
- PMC
- etc.

- Minimal
- Analog
- Filter

- FAST
- ADC

- Minimal
- Analog
- Filter

- FAST
- ADC

- 106 MHz

- OPTIONAL
- Pickup
- “B”

- Stripline
- Kicker

- Power
- Amp.

- 106 MHz

- > 27 MHz

- “Recycler / Injection Damper”(same generic hardware)

## Emulating a 53 MHz Analog Mixer /LPF

*Both circuits have identical impulse response, *
*and identical sensitivity to 53 MHz clock noise*

- Impulse response

**ANALOG MIXER FILTER**

- 70 MHz
- LPF

- BPM

- LPF

- 53 MHz sin

- Impulse response

**53 MHz DIGITAL FILTER   (FIR or IIR)**

- 70 MHz
- LPF

- BPM

- Digital
- Filter

- 53 MHz Clock

- ADC

## Advantages of Digital Filters

- Digital filter can also operate at multiple lower frequencies  ...simultaneously if desired.
- MI will not be blind at 2.5 and 7.5 MHz Beam
- Digital filters more reproducible (=>spares!)
- Re-use Standard hardware with new FPGA code
- or same code with different filter coefficients
- Inputs and Outputs clearly defined
- filters can be developed & debugged offline

## Signal Processing Steps forRecycler / Injection Damper

- 1)  Bandwidth-Limit input signal to ~53 MHz
- 2)  14 Bit Digitization at 106 MHz or 212 MHz
- 3)  Filter to get single-bunch signal
- 4)  Sum & Difference of BPM plate signals
- 5)  Multi turn orbit difference filter w/delay
- 6)  Pickup Mixing for correct Betatron Phase
- 7)  Pre-Emphasis for Kicker Amp & Cable
- 8)  Power Amp for Kicker

- Inside
- FPGA

- Echotek
- Board

- Buy

## Processing Beam Position Measurements to Calculate Kick

- One or two beam pickups
- One or many turns
- Nasty problems:
- kicker phase adjustments vs. machine tune
- DC orbit offset rejection

## 3 - Turn Filter

- Damper kick is calculated from single BPM position reading on 3 successive turns.

*Arbitrary Betatron Phase of Kicker can be accommodated*

## HERA-P Damper uses a 3-turn Digital FIR Filter

*Digital Bunch by Bunch @ 96ns Spacing*
*Immediate digitization following peak detection*
*... **a very attractive system for FNAL to copy...*

*Klute,*
*Kohaupt et. al.   EPAC ‘96*

## Recycler / Injection Damper FPGA Logic(single pickup with 3-turn filter)

- Recycler / Injection Damper FPGA Logic(single pickup with 3-turn filter)

- ADC

- Pickup

- 14

- Stripline
- Kicker

- Power
- Amp.

- 106 MHz

- > 27 MHz

- ADC

- Gain Balance

- FIR
- Filter

- 1-turn
- Delay

- 1-turn
- Delay

- 1-turn
- Delay

- Weighted
- Sum for Arbitrary Betatron Phase

- Standard BPM Processing

- 3 - Turn Filter

- Optional
- Pre-compensation
- Filter for Cable

- DAC

## 3 Turn Filter Coefficients

- Damper kick is weighted sum of beam positions on the 3 previous turns.
- 3 Filter Coefficients Uniquely Determined by:
- System Gain
- Betatron Phase Desired at Kicker
- Constraint that sum of filter coefficients = 0               (so that filter does not respond to DC offsets.)

## 2 Turn Filter  (2 pickups)

- Damper kick is calculated from 2 BPM position readings on two successive turns.

*Arbitrary Betatron Phase of Kicker can be accommodated using both BPMs*

## Recycler / Injection Damper FPGA Logic(two pickups with 2-turn filter)

- Recycler / Injection Damper FPGA Logic(two pickups with 2-turn filter)

- ADC

- Pickup 1

- 14

- Stripline
- Kicker

- Power
- Amp.

- 106 MHz

- > 27 MHz

- ADC

- GAIN

- FIR
- Filter

- 1-turn
- Delay

- 1-turn
- Delay

- 2 - Turn Filter

- Optional
- Precompensation
- Filter for Cable

- DAC

- ADC

- Pickup 2

- 14

- ADC

- GAIN

- FIR
- Filter

- Weighted
- Sum for Arbitrary Betatron Phase

## Two-Turn Filter Coefficients

- First step synthesizes desired Betatron phase at kicker from linear combination of signals from two different pickups.
- Final step is to take orbit difference on two successive turns.  Unweighted subtraction  ensures zero response to DC offsets.
- Coefficients in registers writeable from CPU

## Narrow band vs. Wide band Dampers

- In some cases instabilities only occur with specific frequency and mode patterns in ring
- Dealing specifically with those modes lowers the required kicker power and reduces noise.
- A wide band (bunch-by-bunch) damper can use digital filtering to provide higher gain for specific mode patterns.
- Many digital filters can operate simultaneously inside some device -- ADC and DAC are shared

*The flexibility of Digital Filtering inside the FPGA is a major advantage of this approach.** *

## Damper Output Filter

- Multiple Filters in parallel calculate kick
- Kick signal is split according to frequency
- Hi-bandwidth outputs to stripline kicker
- cable & amplifier pre-compensation w/FIR
- Low bandwidth outputs to magnetic kicker (used mainly at injection)

## Application #4:   Beam Loading Compensation 

- 1) Digital Pipeline to reproduce I&Q signals from RW bunch monitor with N-turn delay.  *(N=1...1/****S**)*
- 2) Digital filters for transients and synchrotron osc.
- _Input_:  Resistive-wall monitor *(& RF gap monitor?)*
- _Digitization_:  bunch-by-bunch I & Q signals
- _Outputs_:  I&Q to damper cavity, or LLRF
*frequency swing issues for LLRF drive*
*Antiproton vs. Proton timing*

## Longitudinal Beam Instability in FMI 

- Driven by cavity wake fields within bunch train
*This is a time domain problem!*

- First Bunch ~ OK

- 7th Bunch Trashed

- Occurs with 7 bunches filled    (out of 588)
- Prevents low emittance bunch coalescing

## Time Domain vs. Frequency Domain

- The classical mode analysis applies best to completely filled machines with instabilities which develop over full circumference.
- Many of the problems FNAL sees are transient (time domain) phenomena  *(e.g. last slide).*
- High bandwidth digital processing is equally comfortable with both, simultaneously.
- Example: damping instability on previous slide:
- 1) Wake field subtraction with narrowband filter.
- 2) Bunch-by-bunch feedback.
- ... *all on same FPGA*.

## 2.5 MHz Beam Loading in MI

- 7-Bunch train causes cavity to ring
- Feedback kills ringing before next turn
- Need feed-forward to kill effects within train

*Gerry Jackson*

## Frequency Sweep Issues

- Machines with frequency sweep (Booster!) must adjust ADC input clock and DAC output clock phases as frequency sweeps.
- This can be generated with Phase-locked loops and delay-locked loops present inside FPGAs.
- This requires access to both the RF clock, and                   a cable-delayed version of the RF clock,                      as timing references.
- One-turn digital delay using FIFOs in FPGAs.
*Same hardware can be used for Booster thru Tevatron.*

## RF Clockingwith acceleration 

*Equal Length Cable Fanout*
*so Beam Sees Same RF Phase*
*at all Cavities as RF Frequency *
*Sweeps During Acceleration*

- # of Clock Cycles
- per Turn is
- harmonic number h

## ADC Clockingduring frequency sweep 

*Round-Trip Cable Delay *
*on ADC Clock ensures*
*ADC Clock & Beam Input*
*Stay in Phase as*
*Beam Accelerates*

- May need additional phase adjustment
- to track phase jumps at transition, etc.

## DAC Clockingduring frequency sweep 

*Propagation Delay: *
*CK **** DAC **** Cable **** Kicker*
*should match RF Fanout Delay*
*so Kick Stays in Phase *
*as Beam Accelerates*

## Generic Dampertolerating frequency sweep 

*FIFO needed due to phase shifts between DAC and ADC clocks as beam accelerates*

*All Logic*
*Inside*
*FPGA*

## DAC  Issues

- Bunch-by-bunch (transverse) kicker:
- step function with flat-top *after cable at kicker*
- FIR filter can pre-compensate for Amp & Cable
- RF drive:
- heavily modulated 53 MHz sine wave
- High Bandwidth DACs now include interpolation logic to “make up” missing points on sine wave
- yields higher effective update rate ~400 MHz

## Slide 66

## AD9777   TxDAC

## Application #5: “Universal Damper”

- Big advantage if same Damper hardware can be used for Booster, RR, MI, & TeV
- Frequency swing during acceleration introduces same timing complications as above.
- Digital Filter which operates on I & Q signals from individual 53 MHz bunches can also be reprogrammed to operate at lower frequencies.
- Tevatron noise requirements make all dampers tough (except injection dampers).

## “Universal Damper” Application

- “Universal Damper” Application

- Monster
- FPGA

- 53 MHz, TCLK, MDAT,...

- Minimal
- Analog
- Filter

- FAST
- ADC

- Stripline
- Pickup
- “A”

- Minimal
- Analog
- Filter

- FAST
- ADC

- FAST
- DAC

- 14

- _CPU Bus_
- VME/
- VXI/
- PCI/
- PMC
- etc.

- Minimal
- Analog
- Filter

- FAST
- ADC

- Minimal
- Analog
- Filter

- FAST
- ADC

- 106 MHz

- Stripline
- Pickup
- “B”

- Stripline
- Kicker

- Power
- Amp.

- 106 MHz

- > 27 MHz

- Cable Delayed
- 53 MHz Clock

## “Universal-Damper” Application: Signal Processing Steps

- 1)  Bandwidth-Limit input signal to ~53 MHz
- 2)  14 Bit Digitization at 106 MHz or 212 MHz
- 3)  FIR filter to get single-bunch signal
- 4)  Sum & Difference of plate signals
- 5)  Multi turn difference filter (FIR) w/delay
- 6)  Pickup Mixing for correct Betatron Phase
- 7)  Bunch-by-bunch gain, dead band etc.
- 8)  Timing Corrections for Frequency Sweep
- 9)  Pre-Emphasis for Kicker Power Amp
- 10)  Power Amp for Kicker

- Inside
- FPGA

- Echotek
- Board

- Buy

## Damper Parameters for various Machines at FNAL

- (See Doc.)

## CONCLUSIONS

- Fast ADCs and Huge FPGAs may   revolutionize Accelerator Instrumentation
- The same basic hardware can perform a large number of Instrumentation & Control functions
- A good first application of this technology is    a “Universal” beam damper

## - To Pursue This -

- Capture digitized waveforms of relevant signals
- to begin development of analog and digital filters
- Test fitting example logic into FPGAs
- Contemplate a change in balance of skills:
- fewer custom analog designs, NIM modules, etc.
- fewer designs, more complex FPGA programming.
- Need to train large body of expertise ASAP
- Standardize hardware: No orphaned digital projects!
- Train many people on standardized components.
- Identify expertise at lab, experiments, and elsewhere.