# Presentation: 025239

## System Architectures: Near, Medium and Long-term Scalable Design Issues

- Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company,for the United States Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.

**System Architectures: Near, Medium and Long-term Scalable Design Issues**

**Arun Rodrigues**
**Sandia National Labs**

## The Problem

**The Problem**

**Hardware**
**Data Movement**
**Power**
**Reliability**
**Software**
**Scaling**
**Emerging applications worse**
**What’s Next?**
**Economic**
**Cost**

**Integrated**
**Solution**

**Power**

**Reliability**

**Data**
**Movement**

**Packaging**

**Notes:**
Must have integrated solution, or any one of these is a show stopper

## Finding the Bottleneck: Data Movement

**Finding the Bottleneck: Data Movement**

**In the node, Memory performance is key bottleneck**
**Even perfect branch prediction and infinite FUs would be less valuable than improving memory latency. **
**Prefetching, caches don’t help emerging applications**

## Impediments to Useful Exascale Computing

**Impediments to Useful Exascale Computing**

**Power Consumption**
**Do Nothing: 100 MW to 1 GW**
**.8-.9 Watt to cool each Watt**
**Data Movement**
**Local**
**Cache architectures**
**Main memory architectures**
**Remote**
**Topology**
**Link BW**
**Injection Rate**
**Messaging Rate**

**Resilience / Reliability**
**Perhaps a harder problem than all the others**
**Do Nothing: an MTBI of 10’s of minutes**
**Software Environment**
**Data movement will require new paradigms**
**OS (functionality vs noise)**
**Users want to run web server on compute nodes, architects want to remove printf()**
**Cost**
**Machine Cost**
**Power: ~$800K / MW / Yr**

- Can we even build it?

- Will it be fast?

- Can we program it?

- Will it break?

**Notes:**
...
Are we doomed? 
largely yes, but...

## The Promise of Packaging

**The Promise of Packaging**

- Less distance = Lower Latency, More Bandwidth

- ?????

**Resilience / Reliability**
**Perhaps a harder problem than all the others**
**Do Nothing: an MTBI of 10’s of minutes**
**Software Environment**
**Data movement will require new paradigms**
**OS (functionality vs noise)**
**Users want to run web server on compute nodes, architects want to remove printf()**
**Cost**
**Machine Cost**
**Power: ~$800K / MW / Yr**

- Amortize packaging cost.

- Processors

- Optics

**DRAM**

**DRAM**

**DRAM**

**DRAM**

**DRAM**

**DRAM**

- Quilt Packaging

- 3D Integration

**Advances at device level are getting more expensive, face diminishing returns**
**On-chip heterogeneous integration (i.e. logic + DRAM) never really worked**
**Advanced packaging offers potential solution**

- Tighter integration = lower power

**Power Consumption**
**Do Nothing: 100 MW to 1 GW**
**.8-.9 Watt to cool each Watt**
**Data Movement**
**Local**
**Cache architectures**
**Main memory architectures**
**Remote**
**Topology**
**Link BW**
**Injection rate**
**Messaging Rate**

## Lessons from Embedded

**Lessons from Embedded**

**Power Consumption**
**Relentless simplification of processors**
**e.g. Rockwell-Collins AAMP/MicroCore**
**1000 MIPS @ 500 Mhz**
**0.12 mm^2 in 90nm**
**3.75 mW!!!**
**Dedicated, efficient HW features**
**Specialized instructions**
**DMA engines**
**BIST, self-repair, self-diagnosis**
**HW debug support**
**Network offload?**
**“****OS Processor”?**

**Embedded world offers parallels to HPC**
**High reliability demands**
**Tight cost/power constraints**

**Notes:**
We’re obviously much cooler...
power  resil:Redun  SW:OSes, predict

## Low level Sync for Message Passing

**Low level Sync for Message Passing**

**Current MPI requires entire buffer be delivered before any part can be used.**
**Fine-grain memory locking could allow overlap of buffer use and reception**
**Unexpected message copy sets FEBs/Base&Bound**
**Little change to user code**
**Computation blocks if data not available**
**Potentially lowers BW requirements**
**Many Sandia apps consume buffers at only 200-500 MB/sec**

- Copy Data

- “Fill” FEB

- Use

- Data

- ...there

- ... not there

- go!

- wait...

- If Data is...

- ... then

- go!

**Notes:**
Low Level HW Synch is not just for threads

## Design Issues: Scenario 1

**Design Issues: Scenario 1**

**Near-Term: Early Diversity**
**Vendors begin integrating heterogeneous cores, scratch-pad memories on chip**
**Ad Hoc programming solutions developed**
**Medium-Term: Customization**
**Vendors begin entertaining customized use of Si**
**“****Mix-and-Match” from vendor’s set of cores, memory**
**Custom mixed chip for <$10M**
**Ad Hoc solutions lead to general solution for accelerators, hierarchical memory - Generic Hardware Interface (GHI)**
**Long-Term: Mix-and-Match**
**Industry develops library of IP blocks with standard interfaces which can be connected together through adv. packaging**
**lightweight cores, heavy cores, MT cores, DRAM, network **
**Sandia hosts “When GHI is Not Enough” Workshop**

**Notes:**
To address the original question... a couple of scenarios

## Design Issues: Scenario 2

**Design Issues: Scenario 2**

**Near-Term: SMPs on a chip, little novelty**
**Medium-Term: Many cores in Package**
**Improved sync primitives enable pervasive multithreading**
**DRAM in package **
**2-4 coherency domains / package, simple topology**
**Libraries provide main interface to specialized features**
**Hierarchy: thread/core/coher. domain/package/node/system**
**Long-Term: MPP in heterogeneous package**
**Memory (DRAM, NV), interconnect (optical, router) on package**
**Special hardware: debug, monitor, net/OS offload - in package**
**Many small, redundant cores**
**10s-100s coherency domains / package, hierarchical topology**
**New programming models allow access to special HW features**