# Presentation: 212984

## LDRD/DOE Project Layouts

- LDRD:
- FPIX chip: 128x22 channels
- Pixel silicon: 50 x 400 m pixels

- 8 chips wide= 7 cm
- 24 chips high = 15 cm
- 1-4 phi positions, 4 layers
- 768*N chips

- DOE:
- PHX chip: 512 channels
- Mini-strips: 50 m x 2-13 mm wide

- 8 chips/layer 1, 11 chips/layer in back 3 layers
- 48 towers/layer, 4 layers, 2 arms
- 3936 chips, ~384/96 boards (11/41 chips/board)  (~2M channels)

- ?

## ?

**Arcnet (FPGA program., chip download)**

- Serial download to chips
- Pass beam clock

## I/O Requirements for Interface Board

- Chip↔Interface Board:
- (1,2,4 readout lines)*(11,41,96...chips) = 11, 22, 44... lines (pairs)
- Serial Download to Chips:
- 5 lines per 8-chips (pairs) (from Guilherme)
- Clock 1 line per chip (pairs) (from Guilherme)
- T+FC interface: 20 lines
- DCM interface: 20 lines
- Output to Lvl-1: ? John says they expect to receive the same data streams that the interface board receives
- ARCNet (or equivalent) for downloading chips/FPGA
- Pulser input(s) ?

## Interface Board FPGA Code Requirements

- Code to initialize chips:  Currently have code from Fermilab which does this, but probably want to convert to straight VHDL.
- De-serialize data stream coming from chips:  if more than one readout line, combine lines to make data word, strip pieces off needed for buffer
- Buffer Space:
- Need to store 64 clocks worth of data
- May require up to ~50kbits for AuAu events (modest, if memory management is smart enough.  Could be much more if not done right?)
- Read/Write asynchronous (though one clock is expected to be integral multiple of other)
- Lvl-1 Accepts:  Must be able to handle up to 5 lvl-1 accepts
- Data Output and packaging
- Upon lvl-1, retrieve data from appropriate clock, package, and ship to DCM
- Will be variable-length data packets (?)
- Upon every clock, ship data from that clock to Lvl-1 decision maker, with latency<N clocks
- Data Integrity Checks:
- Keep track of synch + data words and check for apparent missed bits...
- Need to tag data or respond otherwise if chip appears to have “fallen behind” and/or data has maxed out buffer space so may be incomplete
- ...
- Data size limit (from Chi):   (50s)/(25ns/16 bit word) = 2000 16 bit words

## LDRD/DOE Project Numbers

| Layers Ganged | channels/chip | chips/ board | channels/ board | Occupancy | Interactions/ 64 clocks | Real Hits/ 64 Clocks | Real data size/64 clocks (kbits) | Noise | Clocks | Noise Hits/ 64 Clocks | Noise data size/64 clocks (kbits) | Buffer needed for 64 clocks (kbits) | Number of Readout Lines | Readout Time/data word (nsec) | Readout Latency (beam clocks) | Noise Hits/chip needed to Fall Behind | Noise Rate/chip | Readout Clock Speed (Mbps) |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| 1 | 512 | 11 | 5632 | 0.015 | 1 | 84.48 | 2.03 | 0.001 | 64 | 360.4 | 8.7 | 10.7 | 1 | 212.4 | 17.4 | 0.5 | 0.5 | 113 |
| 4 | 512 | 44 | 22528 | 0.015 | 1 | 337.92 | 8.11 | 0.001 | 64 | 1441.8 | 34.6 | 42.7 | 1 | 212.4 | 17.4 | 0.5 | 0.5 | 113 |
| 1 | 512 | 11 | 5632 | 0.015 | 1 | 84.48 | 2.03 | 0.001 | 64 | 360.4 | 8.7 | 10.7 | 2 | 106.2 | 8.7 | 0.9 | 0.5 | 113 |
| 4 | 512 | 44 | 22528 | 0.015 | 1 | 337.92 | 8.11 | 0.001 | 64 | 1441.8 | 34.6 | 42.7 | 2 | 106.2 | 8.7 | 0.9 | 0.5 | 113 |
| 1 | 512 | 11 | 5632 | 0.015 | 1 | 84.48 | 2.03 | 0.001 | 64 | 360.4 | 8.7 | 10.7 | 4 | 35.3 | 2.9 | 2.8 | 0.5 | 169.8 |
| 4 | 512 | 44 | 22528 | 0.015 | 1 | 337.92 | 8.11 | 0.001 | 64 | 1441.8 | 34.6 | 42.7 | 4 | 35.3 | 2.9 | 2.8 | 0.5 | 169.8 |
| 1 | 512 | 11 | 5632 | 0.015 | 1 | 84.48 | 2.03 | 0.001 | 64 | 360.4 | 8.7 | 10.7 | 6 | 35.4 | 2.9 | 2.8 | 0.5 | 113 |
| 4 | 512 | 44 | 22528 | 0.015 | 1 | 337.92 | 8.11 | 0.001 | 64 | 1441.8 | 34.6 | 42.7 | 6 | 35.4 | 2.9 | 2.8 | 0.5 | 113 |
|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
| 1 | 2816 | 8 | 22528 | 0.0014 | 1 | 31.5392 | 0.76 | 1E-04 | 64 | 144.2 | 3.5 | 4.2 | 1 | 212.4 | 9.0 | 0.5 | 0.3 | 113 |
| 12 | 2816 | 96 | 270336 | 0.0014 | 1 | 378.4704 | 9.08 | 1E-04 | 64 | 1730.2 | 41.5 | 50.6 | 1 | 212.4 | 9.0 | 0.5 | 0.3 | 113 |
| 1 | 2816 | 8 | 22528 | 0.0014 | 1 | 31.5392 | 0.76 | 1E-04 | 64 | 144.2 | 3.5 | 4.2 | 2 | 106.2 | 4.5 | 0.9 | 0.3 | 113 |
| 12 | 2816 | 96 | 270336 | 0.0014 | 1 | 378.4704 | 9.08 | 1E-04 | 64 | 1730.2 | 41.5 | 50.6 | 2 | 106.2 | 4.5 | 0.9 | 0.3 | 113 |
| 1 | 2816 | 8 | 22528 | 0.0014 | 1 | 31.5392 | 0.76 | 1E-04 | 64 | 144.2 | 3.5 | 4.2 | 4 | 35.3 | 1.5 | 2.8 | 0.3 | 169.8 |
| 12 | 2816 | 96 | 270336 | 0.0014 | 1 | 378.4704 | 9.08 | 1E-04 | 64 | 1730.2 | 41.5 | 50.6 | 4 | 35.3 | 1.5 | 2.8 | 0.3 | 169.8 |
| 1 | 2816 | 8 | 22528 | 0.0014 | 1 | 31.5392 | 0.76 | 1E-04 | 64 | 144.2 | 3.5 | 4.2 | 6 | 35.4 | 1.5 | 2.8 | 0.3 | 113 |
| 12 | 2816 | 96 | 270336 | 0.0014 | 1 | 378.4704 | 9.08 | 1E-04 | 64 | 1730.2 | 41.5 | 50.6 | 6 | 35.4 | 1.5 | 2.8 | 0.3 | 113 |

## Where we are

- FSSR chip and associated DAQ up and running in lab
- Are to receive FPIX+silicon+HDI in January
- Are to receive 6-chip FSSR setup soon (?)
- Have FPGA code which takes care of initializing chip, reads data back from chip and dumps into PC DAQ for event crunching
- Source code to DAQ FPGA which can allow us to change clocks, etc.
- Have FPGA development board(s) which can be played with to develop some FPGA code
- Have Mini-DAQ at LANL, but needs computer, has not been set up yet
- Assume we can get some T+FC, DCM copper-fiber translator boards relatively easily to get optical links when we are ready for that

## Possible Development Timeline:  FPGA Development board initially, switching to real board

- Develop Our Data Deserializer

- Develop Buffer for 1 chip

- Dump Data to PC (initially just buffer dump?)

- Accept a trigger in (generic)

- Get trigger from T+FC module

- Expand to multiple chips

- Grab data from BCO of interest and dump, with full buff.

- Input to Board

- Data Management on Board

- Data Out from Board

- Add packaging for DCM

- Add copper/fiber translater and DCM

- Design and Prototype Real Board

- Switch to real board for software development

- Misc:
- Data in from chip immediately or some simulated data?
- Convert chip download code to VHDL (and add to this code)
- Where to add various clock passing
- Where to add lvl-1 out
- ...

## Discussion

- Pieces of FPGA code required and best graded approach to writing code
- Best buffering scheme
- Number of chips to gang together/interface board.  1 FPGA/board or should multiple FPGAs per board be considered?
- Interfacing to Lvl-1 AND DCM:  imply different coding or not, additional requirements...
- How to handle “BUSY”
- Distributing work of interface card

## Backups

## Occupancies from AuAu (Hubert/Dave)

- 7/cm20.7% occupancy at innermost radii (50 m x 2 mm strips)

## Sort FSSR data according to beam crossing number

- Receiver End Block Diagram – A possible starting point from Chi

- Sort in coming data  according to the BC number

- FSSR serial data in

- 64 buffers cover
- 6.4 microsec
- Buffer can be construct
- 4Kbits block in FPGA

- Data to L1

- Data to DCM if
- triggered

- 4ns
- R/W
- Clk

- Each block has to have read/write counter

## Slide 12

## FPIX/PHX chips

- FPIX – Fermilab-developed chip for BTEV.  Would make a production run for LDRD project
- PHX – modified FPIX chip which has channels which match the full FVTX detector geometry (128x22 channels  512 channels)
- Serial download to chip initializes:
- Number of readout lines/chip
- Thresholds (0-7) (one per chip)
- Optionally mask out channels
- Pulse injection (on some chips)
- Shaping time
- ...?
- Data out from chip:
- 2816/512 channels per FPIX/PHX chip
- Push system, 140 Mbps per readout line, 1,2,4 or 6 lines/chip possible
- 24 bit words

## FPIX State Machines