# Presentation: 697384

## SNS Timing Master
LA-UR-03-3377

Eric Bjorklund

**LA-UR-03-3377**
**Eric Bjorklund**

## Basic Characteristics

- Event System.
- 256 events possible.  25 events currently in use.
- ~5 millisecond machine cycle.  60 Hz.
- Option to go to 120 Hz. when second target added.
- 10 second super-cycle.
- Clock synchronized with ring RF.
- Ring RF is 1.057767 Mz at 1 GeV
- Clock is 32 X Ring RF

## Timing System Components

**Timing System Components**

**Ring RF**

**Timing**
**Reference**
**Generator**

**Neutron**

**Choppers**

**AC**

**Line**

**SNS Event**

**Link**

**Master**

**X32 PLL**

**(33 MHz)**

**SNS Real**

**Time Data**

**Link**

**Master**

**10 MHz**

**Crystal**

**Osc.**

**Timing**

**Slave**

**(V124S)**

**Machine**

**Protection**

**System**

**ICS IOC's**

**SNS Utility**

**Module**

**LEBT**

**Chopper**

***4 PLL**

**(64 MHz)**

**Experimental**

**Halls**

**Diagnostics**

**RTDL**

**Event**

**Link**

**Master**

**Timing IOC**

**SNS Time Stamps**
**Beam data**

**RF Gates**
**Extraction Kickers**
**TxHV Gates**

**High resolution timestamps**
**Machine Modes**

**SNS Timestamps**
**Remote Reset**
**Synchronous ISR’s**

**Beam Delay**
**Beam Phase**
**Micro pulse width**
**Macro pulse width**

**SNS Time stamps**
**Delays**
**Gates**
**Triggers**

**Timing System**

**Hardware**

**Timing System Users**

**Experimental Systems**

**Subsystem Hardware**

## Two Transmission Links

- Event Link
- Transmits the timing events that define a machine cycle.
- Each event is 8 bits plus parity (256 events maximum).
- Clock is variable and derived from the ring revolution frequency (32 * Frev).
- Events 0 – 63 are generated by the timing system hardware.
- Events 64 – 255 are generated by software (no fixed times).
- Real-Time Data Link (RTDL)
- Transmits machine parameters and data prior to every new cycle.
- 128 frames possible (expandable to 255).
- Each frame contains an 8-bit frame number, 24-bits of data, and an 8-bit CRC.
- Clock is 10 MHz.

## Sample RTDL Data Frames

- 	_**Frame Number**_	_**Data**_
- 		1 – 3 	Time of day
- 		4 	Event link period
- 		5 	MPS mode
- 		6 	60 Hz phase error
-             	7	Beam Width
- 		15 	IOC Reset Address
- 		17 	Pulse Flavor
- 		18-21	RF Gate Widths
- 		24 	Previous Pulse Status
- 		25 	Cycle
- 		255 	24-bit CRC (calculated)

## Timing Master Crate Layout

## Event Link Generator Hardware

- Event Link Master  Module (V123S)
- VME Module.
- Generates event link carrier (~17 Mhz).
- Accepts, prioritizes, and transmits “hardware” and “software” events.
- Event Link Input Module (V101S)
- VME Module for generating “hardware” events.
- Communicates with the event link master module over the VME P2 backplane.
- Hardware events generated from TTL inputs to the V101S
- 16 events per module.

## RTDL Generator Hardware

- RTDL Master Module (V105S)
- VME Module
- Generates the 10 MHz RTDL Carrier Signal and the RTDL frames.
- RTDL Input Module (V206S)
- VME Module.  8 frames per module.
- Stores the data frames to be sent each cycle on the RTDL.
- Communicates with the RTDL master module over the VME P2 backplane.

## Additional Modules

- Timing Reference Generator
- Double-Wide VME module.
- Provides the 60 Hz “Cycle-Start” signal to the event link master module (V123S).
- Uses a PLL to track the AC line zero-crossing and “smooth out” power grid frequency fluctuations.
- Resolves the “conflict of interest” between power supplies that need to be “line locked” and the neutron choppers’ need for stable timing.
- Frequency Counter
- VME Module in the Timing Master crate.
- Used to monitor the frequency of the event link clock.
- Frequency is broadcast on the RTDL and sent to the timing reference generator to compensate for changes in the ring revolution frequency.

## Additional Modules

- GPS and GPS Interface Module
- GPS provides time source and NTP time service to the site computers.
- VME interface card captures the GPS time at each “Cycle Start” time.
- Captured time is sent out on the RTDL.
- Event Link Monitor
- Monitors the event link and records which events occurred and when.
- Buffers one full “Super-Cycle” (10 seconds).
- Used by the event-link part of the time line monitor to make sure the event link is correct.

## Machine Cycle Timeline

**Data Link****(RTDL)**

**Extract**

**MPS FPAR**

**Event**
**Link**

**End Injection**

**Machine Cycle Timeline**

**0**

**2 ms**

**1 ms**

**6 ms**

**4 ms**

**7 ms**

**5 ms**

**8 ms**

**3 ms**

**Anytime**

**Anytime**

**Informational Events,  non critical timing**

**Time Critical Events,  (soft events disabled)**

**RTDL****Transmit**

**Snapshot, 1Hz, 6Hz, etc...**

**RTDL Valid**

**RTDL parameter transmission****(for next cycle)**

**RF & High Voltage Events**

**MPS FPL**

**System xxx Trigger Events**

**(Alternate) Cycle Start**

**Machine**

- +60 Hz ZeroCrossing

- -60 Hz ZeroCrossing

**Line-Synch**
**Reference**
**Clock**

**Beam On**

**Cycle Start**

- Mostly Stable Triggers

- Beam On Range

- Allowed Range for Variable Triggers

**Extraction Kicker Charge**

**beam accumulation**

## The Product and the Perpetrators