# Presentation: 768306

## The research in this paper was carried out by the Jet Propulsion laboratory, California Institute of Technology out under contract with the

- National Aeronautics and Space Administration (NASA)  code AE.

**Notes:**
Good morning. Today I talk about Single-event upset in the PowerPC7400 microprocessor which is known as G4. This work is done by Radiation group at JPL.

## Outline 

- Introduction
- Setup
- Experimental method
- Proton results
- Heavy-ion results
- Conclusions
- Future measurements

**Notes:**
First, let me outline my talk. At the beginning, in introduction I briefly describe why we are interested in commercial microprocessors. Then I will talk about experimental setup and experimental method. After that I present results for proton and heavy ion and finally I go over conclusions and future work

## Increased performance compared to hardened processors
Potential applications for instruments and data processing
Particularly critical for autonomous instruments
Simplified data transmission in deep space

- Potential applications for instruments and data processing
- Particularly critical for autonomous instruments
- Simplified data transmission in deep space

**Why are we interested in commercial Processors?**

- Introduction

**Notes:**
In recent years there has been increased interest in the possible use of commercial microprocessors in space because of the increased performance compared to hardened processors. However, commercial processors are susceptible to upset and degradation from radiation, and more information is needed on how they respond to radiation before they can be used in space.
There are potential applications for use of commercial microprocessors in various space applications, including earth orbiting, deep space and planetary exploration missions. 

## The PowerPC750 was co-designed by IBM and Motorola.
We have previously reported single-event measurements on Motorola and IBM PowerPC 750 processors*.
The PowerPC 74xx series incorporates a more advanced processing unit (AltiVec).
The PowerPC 74xx series with AltiVec unit can execute 20 operations per clock cycle compare to conventional processors which generally execute one to three instructions per cycle.

- We have previously reported single-event measurements on Motorola and IBM PowerPC 750 processors*.
- The PowerPC 74xx series incorporates a more advanced processing unit (AltiVec).
- The PowerPC 74xx series with AltiVec unit can execute 20 operations per clock cycle compare to conventional processors which generally execute one to three instructions per cycle.

**Summary of Motorola’s PowerPC ****Family of Advanced Processors**

- Introduction

- * *G. M. swift, et al., IEEE Trans. Nucl. Sci., vol. 48, no. 6,*
*   **pp. 1822-1827,2001*

**Notes:**
The powerPC750 was co-designed by IBM and Motorola.  We have previously reported single-event measurements on Motorola and IBM PowerPC750 Processors (Gary Swift et al.) The 4th generation PowerPC by Motorola called G4 series.The PowerPC 74xx series incorporate a more advanced processing unit called AltiVec. The AltiVec unit can execute 20 operations per clock cycle compare to conventional processors which generally execute one to three instruction per cycle.

## Summary of Motorola’s PowerPC Family of Advanced Processors

| 
Device | Feature Size (μm) | Die Size (mm2) | Core Voltage
 (V) | Max. Operating Freq. (MHz) |
| --- | --- | --- | --- | --- |
| MPC603 (G2) | 0.50 | 196 | 2.5 | 300 |
| MPC750 (G3) | 0.29 |   67 | 2.5 | 350 |
| MPC7400 (G4)* | 0.20 |   83 | 1.8 | 500 |
| MPC7450 (G4)* | 0.18 | 106 | 1.6 | 867 |
| MPC7455 (G4)*# | 0.18
 | TBD | 1.6 | 1000 |

- Introduction

**Summary of Motorola’s PowerPC ****Family of Advanced Processors**

- *AltiVec processing unit
- #SOI

**Notes:**
Note that the feature size of the PowerPC7400 is reduced from 0.29 to 0.20 μm compared to the PowerPC750, with the core voltage reduced from 2.5 to 1.8 V. The larger die size of the PowerPC7400 is due to the more advanced design. Recently announced, PowerPC7455 is the latest generation of the Motorola PowerPC family which are fabricated with Silicon-On-Insulator, SOI, technology. We plan to do SEU measurements on this new processor in very near future.

## Radiation testing was done using a development board from Motorola known as “Yellowknife”
Basic PROM-based system monitor instead of a complex operating system
Small daughter card for processor and cache with no active. components underneath (important for proton beam penetration)
External communication with serial connection and JTAG port
An Agilent Technology 5900B JTAG probe was used
Many nodes of interest, e.g. GPR, FPR, Caches, etc. can be read
indirectly through the JTAG port
It is able to interrogate the processor even when unexpected
events occurred 

- Basic PROM-based system monitor instead of a complex operating system
- Small daughter card for processor and cache with no active. components underneath (important for proton beam penetration)
- External communication with serial connection and JTAG port
- An Agilent Technology 5900B JTAG probe was used
- Many nodes of interest, e.g. GPR, FPR, Caches, etc. can be read
- indirectly through the JTAG port
- It is able to interrogate the processor even when unexpected
- events occurred

- Setup

**Notes:**
Radiation testing was done using a development board from Motorola known as “Yellowknife”.  This board was chosen because it eliminated the large engineering effort that would be required to design a custom test board for the processor and also provided a very basic PROM-based system monitor instead of a complex operating system.  This provides far better diagnostic information and control of processor information during SEE testing compared to more advanced operating systems.  The Yellowknife board has a small daughter card for the processor and cache with no active components underneath, which is important for proton beam penetration.  This allowed us to shield other components on the board during proton tests, assuring that the measured response was entirely due to effects within the processor.  The only external communication channels provided on the Yellowknife are a simple serial connection for a “dump” terminal and a JTAG port.  An Agilent Technology 5900B JTAG probe was used for our tests.  This probe made it possible to interrogate the processor even after unexpected events occurred (such as operational errors during irradiation).

## Heavy-Ion Setup

**Notes:**
This shows our setup at TAM heavy-ion facility in the air. Processor, Jtag, and thermocouple. Water circulation to take heat away from processor and Jtag

## Custom Heat Sink

-  A custom heat sink with a hole for the processor die was used to contact heat away from the package
-   A routine was developed to read out the processor’s junction temperature
-  A thermocouple was used to measure temperature increases during the time that the device operated

**Notes:**
A copper custom heat sink with a hole for the processor die was used to contact heat away from the package. A routine was developed to read out the processor’s junction temperature. A thermocouple was used to measure temperature increases during the time that the device operated.

## Fill internal registers or data cache with recognizable pattern
Perform a one word instruction in a small infinite loop
Write a register or changes in data cache snapshot to a strip chart in the physical memory every half second using decrementer interrupt
After the irradiation, an external interrupt triggers a program to count state changes in internal registers or the data cache 

- Perform a one word instruction in a small infinite loop
- Write a register or changes in data cache snapshot to a strip chart in the physical memory every half second using decrementer interrupt
- After the irradiation, an external interrupt triggers a program to count state changes in internal registers or the data cache

- Basic Approach

**Notes:**
In our test method, the processor was programmed to perform a one word instruction in a small infinite loop and write a register snapshot to a strip chart in the physical memory every half second.  After the irradiation ended, an external interrupt triggers a program to count state changes in internal registers or the data cache. 
A more complex method was required to examine errors in the L1 data cache.  Upsets in the data cache were counted with a special post beam software. The data cache was initialized under specified conditions prior to irradiation and then disabled.  Then a clearly recognizable pattern, designed to be distinctly different from contents of the cache, was placed in the external memory space covered by the cache. Comparing the cache contents after irradiation provided verification of the cache contents. Tag upsets, as well as upsets of the data valid flag, were detected by monitoring the distinctly different pattern. The tag and data valid upsets were thus distinguished and counted separately from upsets of the data bits themselves.

## Proton tests with energies above 65 MeV were performed at IUCF
Tests at lower energies were done at UC Davis
Heavy-ion tests were performed at the TAM using ions with 25 and 40 MeV/amu
Irradiating from back
Because of limited range of heavy-ion beams, we ground down the back surface of the PowerPC 7400
Reduced thickness from 720 to 50-200 μm 
No impact on electrical characteristics

- Tests at lower energies were done at UC Davis
- Heavy-ion tests were performed at the TAM using ions with 25 and 40 MeV/amu
- Irradiating from back
- Because of limited range of heavy-ion beams, we ground down the back surface of the PowerPC 7400
- Reduced thickness from 720 to 50-200 μm
- No impact on electrical characteristics

- Basic Approach

**Notes:**
Proton tests with energies above 65 MeV were performed at the Indiana University Cyclotron Facility.  Tests at lower energies were done at the UC Davis cyclotron.  Because of sufficient range of protons to penetrate the packaging material of the PowerPC7400, tests were done in air without any need for package modification.
Heavy-ion tests were performed at the Texas A&M accelerator.  This facility produces the long-range ions needed for SEU testing through thick materials.  Particularly, the 25 and 40 MeV/amu beams are quite penetrating, and it is practical to do irradiations in the air rather than in a vacuum. However, the total thickness of the die for PowerPC7400 is ~719 μm and, in contrast to proton beams, the limited range of heavy-ion beams does not allow them to penetrate the package.  The “flip-chip” design of the PowerPC7400 does not allow the device to be “delidded” without destroying the pad and bonding connections.  In order to get around the delidding problem, we grounded down the back surface of the PowerPC7400.  This reduced the total thickness of the die to 50-200 μm without impacting the electrical characteristics. The thin die did not affect charge collection because it has a thin-epitaxial layer.  There is good agreement for SEU results obtained from different thicknesses of the PowerPC processor, after correcting for energy loss through the thinned substrate (Gary’s talk). 

## Basic Approach

- Upsets measured in
- Registers
- L1 data cache and their tags
- L2 tags
- Translation Lookaside Buffer TLB
- Overall results for processor functionality

**Notes:**
We measured single-event upset in the registers, L1 data cache and their tags, L2 tags, TLB, and overall results for processor functionality.

## Cross section for transitions between “1” and “0” are statistically identical
Threshold is 5-7 MeV
Saturated cross section is about 3x10-14 cm2/bit, which is in agreement with data for the PowerPC 750 with its feature size of 0.29 μm

**Threshold is 5-7 MeV**
**Saturated cross section is about 3x10****-14**** cm****2****/bit, which is in agreement with data for the PowerPC 750 with its feature size of 0.29 ****μ****m**

- Proton Test Results for Cache

**Notes:**
In this figure we show results of cross section measurements for the PowerPC7400 Data-Cache Memory bits for “1” to “0” and “0” to “1” transitions.  The cross section for transitions between “1” and “0” are statistically identical.  The threshold cross section is about 5-7 MeV, and the saturated cross section is about 3x10-14 cm2/bit, which is in agreement with data for the PowerPC750 with its feature size of 0.29 μm. This indicates that the higher density and increased speed of the PowerPC7400 does not increase the sensitivity of the registers to upset from protons. The low threshold behavior is reasonable if one considers that the cache memory must fit within a restricted area within the processor.The lower saturation cross section is probably due to reduced device area in the high-speed cache registers. The large number of storage locations within the data cache allows more statistically significant numbers of errors to be measured, decreasing the error bars due to counting statistics. The cross section for D-cache Tags and Flags shows similar behavior, except the saturation cross section is about 1x10-9 cm2/bit. 

## Results of cross section per bit measurement for TLB of the PowerPC 7400 MMU versus proton energy
For comparison we show our previous measurements for the PowerPC 750
The saturated cross section is about 5x10-14 cm2/bit
The threshold energy is 15 MeV
Agreement with results for PowerPC 750

**For comparison we show our previous measurements for the PowerPC 750**
**The saturated cross section is about 5x10****-14**** cm****2****/bit**
**The threshold energy is 15 MeV**
**Agreement with results for PowerPC 750**

- Proton Test Results for TLB

**Notes:**
In this figure we show results of cross section per bit measurements forTLB of the PowerPC7400 MMU versus proton energy.  For comparison we show our previous measurements for the PowerPC750. The saturated cross section is about 5x10-14 cm2/bit and the threshold energy is about 15 MeV, which are in agreement with results for the PowerPC750. 

## Results of cross section for PowerPC 7400 FPR for “1” to “0” transitions
The LET threshold is about 5 MeV-cm2/mg
The saturated cross section is about 1x10-7 cm2/bit 
The cross section for “1” to “0” is the same as for “0” to “1” transitions
There is a good agreement for results obtained from different thicknesses
Agreement with results for PowerPC 750

**The LET threshold is about 5 MeV-cm****2****/mg**
**The saturated cross section is about 1x10****-7**** cm****2****/bit **
**The cross section for “1” to “0” is the same as for “0” to “1” transitions**
**There is a good agreement for results obtained from different thicknesses**
**Agreement with results for PowerPC 750**

- Heavy Ion Test Results for FPR

**Notes:**
In this figure we display results of cross section measurements for the PowerPC7400 Floating Point Register for “1” to “0” transitions.  The LET threshold is about 5 MeV-cm2/mg, and the saturated cross section is about 1x10-7 cm2/bit.  The cross section for “1” to “0” transitions is the same as for “0” to “1” transitions. These data were taken with several parts with different thicknesses.  The LET at the device surface had to be corrected to allow for decrease in beam energy as ions traversed the device from back to the sensitive top surface of the device.  There is a good agreement for results obtained from different thicknesses.  This is expected since advanced processors require a fairly thin epitaxial layer and there is no major charge collection differences between devices with different thicknesses.  It is interesting to compare these results with earlier results for the PowerPC750.  The LET threshold and saturated cross section for the two types of processor are the same. Thus, the increased die size, decreased feature size and decreased internal core voltage of the PowerPC7400 did not appear to have changed the sensitivity to the single-event upset very much.  

## The saturated cross section is about 4x10-8 cm2/bit
The saturated cross section is slightly lower than PowerPC 750
This might be related to smaller die size for MMU unit in the PowerPC 7400
We plan to do measurements at lower LET to compare the threshold cross section with results for PowerPC 750

**The saturated cross section is slightly lower than PowerPC 750**
**This might be related to smaller die size for MMU unit in the PowerPC 7400**
**We plan to do measurements at lower LET to compare the threshold cross section with results for PowerPC 750**

- Heavy Ion Test Results for TLB

**Notes:**
In this figure we  show results of heavy-ion measurements for the TLB of the PowerPC7400 MMU.  The saturated cross section is about 4x10-8 cm2/bit.  For comparison, the figure shows data for the PowerPC750.  The saturated cross section is slightly lower than the PowerPC750.  This might be related to smaller die size for MMU unit in the PowerPC7400.  We plan to do the measurements at lower LET to compare the threshold cross section with the result for the PowerPC750.  

## Conclusions

- Although the PowerPC 7400 has smaller, geometry, lower internal core voltage and design advances, its proton and heavy ion upset susceptibility are somewhat *lower* than PowerPC 750
- PC7400	0.20 μm, 1.8 V
- PC750	0.29 μm, 2.5 V
- The low space rates, immunity to latchup, and relatively low power consumption, allow them to be used successfully in many space environments
- They can be used in data analysis or instrument control applications where occasional malfunctions or errors from single-event upset can be tolerated and corrected

**Notes:**
The advanced commercial PowerPC microprocessors are slightly  less sensitive to single-event upset compare to earlier generations of the PowerPC microprocessors. Although the PowerPC7400 has smaller, sub-micron geometry, lower internal core voltage and design advances, its proton and heavy ion upset susceptibility is only slightly lower than the PowerPC750.  The low space rates, immunity to latchup, and relatively low power consumption, allow them to be used successfully in many space environments.  They can be used in data analysis or instrument control applications where occasional malfunctions or errors from single-event upset can be tolerated and corrected.  

## Future Measurements

- Measure single-event upset in the new Motorola SOI PowerPC7455 microprocessor
- Measure single-event upset in the new IBM SOI PowerPC750FX microprocessor

**Notes:**
We plan to do measurement on new SOI processor by Motorola and IBM in near future. The IBM750FX was introduced in late January of 2002 and Motorola 7455 in the October of 2001. To see if SEU effects improves or gets worse. 

## Slide 18

## Slide 19