<!-- Title: Owl shift. Fri Oct  6, 2000 -->
<!-- Leader: Peter Wilson -->
<!-- Ace: G Veramendi, D Ambrose -->
<!-- Co1: Subir Sarkar -->
<!-- Co2: Marina Brozovic -->
<!-- Co3: Nigel Lockyer (SOS1) -->
<!-- Co4: Kevin Burkett (SOS2) -->
<!-- Co5: &nbsp; -->
<!-- Notes: -->
<pre>SVX Rad Mon 
W Inner - 0 
W Outer - 24.72 
E Inner - 0 
E Outer - 23.24</pre>


<!-- Date: Fri Oct 6 00:34:07 2000 -->
<pre>Currently running with no L3 output (switched fourth L3 
parameter "subfarmout" to 0 from 1) to see if all crates 
have been properly rebooted.  After rebooting wcal01, are 
not getting any reformatter errors.  After Tony arrives, 
will Ctrl-C out of temporary CSL-fix, and switch back 
L3 output paramter to 1.</pre>
<!-- Author: dave -->
<!-- Comment: Fri Oct  6 00;58;43 comment by...Dave -->
<pre>To run fake CSL:

--> ssh cdfdaq@b0dau30
--> cd $FER_DIR
--> cd src
--> cd runControl
--> ./clientNew /csl

Do a Ctrl-C to quit.</pre>
<!-- Date: Fri Oct 6 00:50:23 2000 -->
<pre>MCR called, are terminating TeV beam, putting in another 
store.</pre>
<!-- Author: dave -->


<!-- Date: Fri Oct 6 00:58:24 2000 -->
Vaia and Marina have looked into CEM and CHA pedestals that were at 0 in DBANA (see OWL shft Oct 5).  They observed that the pedestals are normal if only the CEMPED and CHAPED sets are selected.  However if they select the WHAPED, PEMPED and PHAPED in addition the CEM and CHA PED plots get messed up.  This does not happen with the QIE (slope) plots.  This appears to be a bug with selecting data that does not have plots defined (WHAPED, PEMPED and PHAPED).  Vaia expects to implement those plots tomorrow.  Until they are implemented, the CEMPED and CHAPED plots should be viewed only when only those sets are selected. 
  
<!-- Author: Peter Wilson -->



<!-- Date: Fri Oct 6 01:07:37 2000 -->
<pre>Robin looking at PCAL2,4,10</pre>
<!-- Author: dave -->
<!-- Comment: Fri Oct  6 01;21;33 comment by...Robin Erbacher -->
<br><i>pcal04 and pcal10 look healthy.  I don't know why they
are out of the run configuration.  However, for pcal02, the reset
line does not appear to be working, and the processor is hung.
There is nothing I can do without speaking to Jim P or someone
else who knows how to get it out of that state.  Cannot reboot 
because I cannot log on.  </i>


<!-- Comment: Fri Oct  6 02;50;16 comment by...Peter Wilson -->
Robin and I simultaneously noted that the +5V digital supply on
pcal02 is in fault.  See plug log book entry: <a href=/cgi/elog/det-system-elog.pl?nb=plug&action=view&page=24&anchor=02:47:16 target=_top><img src='/elog/gifs/gr_menu.gif' width=19 height=10 border=0></a>
<!-- Comment: Fri Oct  6 03;43;34 comment by...Peter Wilson -->
Cycled power on West plug crates.  pcal02 power supply
recovered.
<!-- Date: Fri Oct 6 02:12:50 2000 -->
<pre>Tony ended up rebooting the CSL, are now taking run 100505. 
Were not able to take CLC calib before new beam in TEV, but 
will try later.</pre>
<!-- Author: dave -->


<!-- Date: Fri Oct 6 02:33:28 2000 -->
<pre>Ran for ~40k events. 
Stopping so that Tony can restart CSL, and so we can turn 
on silicon bias voltage, and add COT, XFT, HTDC, and  
two missing pcals.</pre>
<!-- Author: Greg V. :: (run 100505) -->


<!-- Date: Fri Oct 6 02:39:03 2000 -->
<pre> 
 
Restarted CSL. It no longer communicated with Run Control. 
The process handling this died for some reason (RTServer 
crash/restart?). Several CSL processes did not die nicely, 
b0dau32 needed to be rebooted. 
</pre>
<!-- Author: Tony V -->



<!-- Date: Fri Oct 6 03:05:05 2000 -->
<pre>Doing integration tests. Problem crates which don't improve 
with Reset Bus/Reboot (these fail on cold start): 
XFT1: Cannot find card in slot 5 
COT2: Resetting card in slot 8 failed  
b0cot17: Resetting b0cot07card in slot 6 failed  
b0cot07: Resetting card in slot 14 failed  
b0cot12:Resetting card in slot 6 failed  
b0cot01: didn't log into this crates, assuming similar problem 
 
Next we got event id errors on eb13, so we are removing W. COT 
</pre>
<!-- Author: Greg V. :: (run 100509) -->
<!-- Comment: Fri Oct  6 06;31;02 comment by...Jay Dittmann -->
The b0xft01 problem is fixed.  The XFLD_01 bankset needed
to be modified to include slot 4 instead of slot 5.
<!-- Date: Fri Oct 6 03:24:11 2000 -->
<pre>Finally ran, but all events were being rejected because 
of "data quality" (reformatter) errors from XTRP-->Removed. 
</pre>
<!-- Author: Greg V. :: (run 100511) -->


<!-- Date: Fri Oct 6 03:35:29 2000 -->
<pre>Got event id problems in eb12, and we got a reformatter 
error in XFT2, so we yanked all the XFT since they 
correspond to eb12</pre>
<!-- Author: Greg V. :: (run 100512) -->



<!-- Date: Fri Oct 6 03:50:59 2000 -->
<pre>After about 9600 events, start getting event ID errors on 
b0eb14 (COT east), says "crate 62".  Also, PCAL10 had 100% 
occupancy, page Robin.</pre>
<!-- Author: dave :: (run 100513) -->
<!-- Comment: Fri Oct  6 04;15;57 comment by...Peter Wilson -->
See YMON occupancy plot for PCAL10 problem.   <a href=/cgi/elog/elog.pl?nb=2000&action=view&page=144&anchor=04:03:55 target=_top><img src='/elog/gifs/gr_menu.gif' width=19 height=10 border=0></a>
<!-- Comment: Fri Oct  6 08;20;55 comment by...R. Erbacher -->
<br><b>b0pcal10</b>:It looks like the FRAMs in slots 18 and 19 were loaded with 
high values:<pre>
  Addr
 0000    002F    002F    002F    002F    002F    002F    002F    002F
 0008    002F    002F    002F    002F    002F    002F    002F    002F
 0010    002F    002F    002F    002F    002F    002F    002F    002F
 0018    002F    002F    002F    002F    002F    002F    002F    002F
 0020    002F    002F    002F    002F    002F    002F    002F    002F
 0028    002F    002F    002F    002F    002F    002F    002F    002F
...
</pre>
I recalibrated and downloaded the flashram.  All checked out ok.
However, when I went to look at the flashrams again, slot 18 didn't respond!  Did a ped test and it looks like the fuse is 
blown (or admem needs resetting).  Rebooted and got the same:<pre>
   18    0    0     no events
   18    0    1     no events
   18    0    2     no events
   18    0    3    4000   7.0     1023.0   0.0
   18    1    0     no events
   18    1    1     no events
   18    1    2     no events
   18    1    3    4000   7.0     1023.0   0.0
...
</pre> Need to check this during an access.  Something happened just now, <i>after</i> I calibrated successfully.
<!-- Comment: Fri Oct  6 19;10;47 comment by...RDE -->
<br>I take back what I said about slot 18 having a blown fuse.
It seems to have fixed itself.  When I was able to read the
FRAM, they were all loaded with 0033 or something similar.
But the peds weren't working as shown above.  Later in the day (10/6) I reset the crate and now the FRAMs look ok.  Not only 
that but the peds and calibration run well.  I re-examined this
slot because the triggers were still hot.  I will see if they
hot triggers go away now with fresh FRAM values.
<!-- Date: Fri Oct 6 04:01:57 2000 -->
<pre>New SOS, Kevin Burkett, has arrived.</pre>
<!-- Author: Peter Wilson -->


<!-- Date: Fri Oct 6 04:03:55 2000 -->
<table><tr><td><a href=/elog/notebooks/2000/Fri_Oct__6_2000_Owl.040349.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>PEMDETower Energy and occupancy</a></td></tr></table>
<!-- Author: Subir Sarkar -->



<!-- Date: Fri Oct 6 04:33:39 2000 -->
<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> 
<html> 
<head> 
   <meta name="GENERATOR" content="Mozilla/4.75 [en] (X11; U; Linux 2.2.16-3 i686) [Netscape]"> 
</head> 
<body> 
Running with trigger table commissioning_table_2 V5.  Looking at Trigger 
rates in Scaler Monitor: 
<br>  
<center><table BORDER COLS=3 WIDTH="80%" NOSAVE > 
<tr> 
<td>Bit Number</td> 
 
<td>Trigger</td> 
 
<td>Rate (kHz)</td> 
</tr> 
 
<tr> 
<td>0</td> 
 
<td>SUM_ET_10</td> 
 
<td>1</td> 
</tr> 
 
<tr> 
<td>4</td> 
 
<td>JET_2</td> 
 
<td>10</td> 
</tr> 
 
<tr> 
<td>12</td> 
 
<td>?</td> 
 
<td>10</td> 
</tr> 
 
<tr> 
<td>21</td> 
 
<td>MINIMUM_BIAS/1000</td> 
 
<td>0</td> 
</tr> 
 
<tr> 
<td>23</td> 
 
<td>ZERO_BIAS/100,000</td> 
 
<td>7600</td> 
</tr> 
</table></center> 
<font color="#FF0000"></font> 
<p><font color="#FF0000">What is bit 12?</font> 
</body> 
</html>
<!-- Author: Peter Wilson :: (run 100515) -->


<!-- Date: Fri Oct 6 04:33:41 2000 -->
<pre>Run ended with a Done TO in SVX_2 
~40k events 
turning on myron mode... 
</pre>
<!-- Author: Greg V. :: (run 100515) -->
<!-- Comment: Fri Oct  6 04;44;11 comment by...Greg V. -->
evb registered error when trying to end run...
then when activating for next run it ack an error again...
cleaning up


<!-- Date: Fri Oct 6 05:51:59 2000 -->
<pre>run with myron mode normal 
ended with Busy TO in SVX 
</pre>
<!-- Author: Greg V. :: (run 100520) -->


<!-- Date: Fri Oct 6 05:54:37 2000 -->
<pre>Attempted to run with Myron mode early L1 accept, 
but all rates on FRED were zero... 
 
Went back to normal Myron mode, and got  
event id errors again in eb11 after 8k events 
(100523)</pre>
<!-- Author: Greg V. -->
<!-- Comment: Fri Oct  6 05;57;11 comment by...Greg V. -->
tried removing silicon to see if myron early would
work, but it still doesn't: 0 events, 0 rate on FRED


<!-- Date: Fri Oct 6 06:04:56 2000 -->
<pre>QIE calibration, run 100525: 
--> WCAL02 fail 10 (no fitting), slots 16-21 
--> PCAL00 fail 10 (no fitting), slot 14</pre>
<!-- Author: dave :: (run 100525) -->
<!-- Comment: Fri Oct  6 08;33;57 comment by...R. Erbacher -->
<br>The problem in pcal00 is in slot 14, channel 7 (14,7) and is
a known problem:  we get no signal from this channel.  Wcal02
has a fault on the power supply 5V analog.  Will ask Peter to
reset it if he is still around.
<!-- Comment: Fri Oct  6 08;36;47 comment by...R. Erbacher -->
The fault occured at about 11:30am on 10/5!
<!-- Date: Fri Oct 6 06:11:06 2000 -->
<pre>LED calibration, run 100526, successful.</pre>
<!-- Author: dave :: (run 100526) -->


<!-- Date: Fri Oct 6 06:17:49 2000 -->
<pre>XEF calibration, run 100527.</pre>
<!-- Author: dave :: (run 100527) -->


<!-- Date: Fri Oct 6 06:30:41 2000 -->
<pre>COT calibration, run 100528, on setup got following errors 
(we were including COT1-3,6-14,16-19): 
 
--> COT12, resetting card in slot 6 failed 
--> COT01, resetting card in slot 3 failed 
--> COT07, resetting card in slot 14 failed 
--> COT17, resetting card in slot 6 failed 
--> COT02, resetting card in slot 8 failed 
 
Added in COT4,5 and removed above crates (1,2,7,12,17), started 
run 100529, get following: 
 
--> COT09, VISIONread/write failed in slot 9 
 
but run worked.</pre>
<!-- Author: dave -->
<!-- Comment: Fri Oct  6 10;06;31 comment by...Ting Miao -->
<pre>I did a bus restting for above crates and recoved all the TDCs 
listed above. Sometime one needs to the resetting twice (for 
b0cot07 slot 14 for example)</pre>
<!-- Date: Fri Oct 6 06:48:50 2000 -->
<pre>Starting integration test using software event builder, 
run 100530, have: 
 
--> all CCAL, all PCAL ('cept 10), all WCAL 
--> CLC 
--> CMU, CMP, CMX, IMU, MUSC, MUTR 
--> HTDC 
--> FIB_SVX0,2,4,6, VRB_SVX0-8, SVT_TRK1,2, SVT_FIT6 
--> all L1CL, L1GL, L2CL, L2_DEC_1, SCALERS 
 
Rate is about 1 Hz.</pre>
<!-- Author: dave :: (run 100530) -->
<!-- Comment: Fri Oct  6 06;52;48 comment by...Greg V. -->
<pre>Also the consumers don't seem to be able to work. I 
ran gdb, and there was something about a trybos
header file missing?.... so it doesn't seem like
the consumers will run with the sevb right now..
</pre>

<!-- Comment: Fri Oct  6 07;52;04 comment by...Greg V. -->
<pre>correction, YMon and Event Display both crash when starting
them with the current run. gdb says something about a trybos
header file, but it's unclear that ED and YMon have the same
problem.
</pre>

<!-- Comment: Fri Oct  6 07;57;01 comment by...Greg V. -->
Ended run with 5.8k events.


<!-- Date: Fri Oct 6 07:58:33 2000 -->
<font color=red>Shift Summary: </font><pre>SVX Rad Mon: 
E Inner - 0 
E Outer - 24.72 
W Inner - 0 
W Outer - 23.25 
 
Ran complement of calibrations: QIE, XEF, LED 
For next shift(?): CLC calibration (requires no beam) 
 
Ran w/HEVB w/COT then w/o COT since Event ID errors worst with COT. 
Myron Mode run with L1 Normal - successful 
Myron Mode run with L1 Early - did not work: no events 
Run with SEVB at 1Hz! (no COT) </pre> 
<!-- Author: Peter Wilson -->