<!-- Title: 01:21:01  Thu Aug  8 2002 -->
<!-- Crewchief: Silicon People -->
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<!-- Notes: -->
<pre>Previous file too long 
</pre>


<!-- Date: Thu Aug 8 01:22:17 2002 -->
<pre>Spent a fair amount of time with Torture test on PITWIB. 
Nothing special out of it so we will need to seat down with  
Steve N. and make a plan for the next couple of days. 
</pre>
<!-- Author: Gino -->


<!-- Date: Thu Aug 8 01:23:36 2002 -->
<pre>The silicon is NOW on the OFF state. 
There is NO-reason to bring it to STDBY untill the next store is IN. There is only something to loose if a quench ... 
 
The expert on call should be aware of this.</pre>
<!-- Author: Gino -->


<!-- Date: Thu Aug 8 10:01:40 2002 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-682&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-682  width='300' align='top'></td><td>This is what now pops up when someone clicks the outdated "SVX," "ISL," or "L00" buttons on the iFix Global Alarms page.  So much for subtlety. </a></td></tr></table>
<!-- Author: Andy H. -->


<!-- Date: Thu Aug 8 11:12:22 2002 -->
<h3>Retro- fib firmware</h3> 
I put back <i>pipe26.jam</i> into b0fib03 sl 12 aka the 
pitwibfib (say that 12 times fast) and verified that it 
has Chris's favorite development sequences in it (<i>CPC_070802_abort3.seq</i> or something to that extent). 
 
Shot soon, so no goofing around at the moment.  
<!-- Author: SCN -->
<!-- Comment: Thu Aug  8 14;45;24 comment by...SCN, Chris -->
<h3>Dangerous sequence</h3>Made a new sequence w/o the
minidigitize at the end of readout (but with the keepalive still)
and applied it to this fib, with the idea of running the 
pitwib in the next store and seeing if it dies.  Sequence
is called CPC_070802_abort_nominidig.seq or something like that)<P>
Made no attempt yet to see that the pitwib will be integrated, will leave that to Gino.

<!-- Comment: Thu Aug  8 15;56;16 comment by...Gino -->
<pre>FIB_ISL_03 SLOT 12 CHANNELS 0,1,2 are now online in the HDWDB

When writing CAENvolts.dat I get only SB1W7L1 not Xed and so I 
manually remove the Xs from  SB1W7L0, SB1W7L2 and SB1W7L3

From David Error Monitor I see data out of the last 2 weeks only
for e231 and not for e230 and e232. I'm going to discuss it with 
Steve Nahn.
  </pre>

<!-- Comment: Thu Aug  8 16;54;42 comment by...SCN -->
looking at raw data from run 149579 on fcdfsgi2 via<BR> 
<I>od -Ax -h /cdf/data08/look/itestr/ir02484b.0001test</I><BR>
I certainly see headers for all 3 pitwib channels. Of course, I am 
looking for <B>f</B>23[0,1,2] not <B>e</B>23[0,1,2].
Here's a snippet:
<pre>
0009bd0 f230 03fc c1c1 0000 f231 03fc c1c1 0000
0009be0 f232 03fc c1c1 0000 4000 0ba5 ffff ffff
</pre>
I'm going to discuss it with Gino Bolla.<P>
By the way, from the looks of it, someone disabled the channels
after cold start.

<!-- Comment: Thu Aug  8 19;49;18 comment by...David -->
<P>
The problem of data appearing in DEM for only f231 is my fault. My code only looked there because that is all that used to be there. I added the other hdis as of now and will toss a couple of old files into the queue for reprocessing. Sorry for the confusion.
<P>

<!-- Date: Thu Aug 8 22:57:44 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB2W0L2 
<li>problem n: 30 
<li>Status: fixed
<li>Action: Diagnosis_update
<li>entered by: chill 
<li>description is: Corrine Kluge installed on access, problem appears to be fixed (no errors in svxdaq). </ul>
<!-- Author: Problem DB -->



<!-- Date: Fri Aug 9 08:42:23 2002 -->
<pre> 
 
SB2W10, 
last night we had 1 hour access and we installed a modified FTM 
for SB2W10-11. 
The modification consist of a resistor of a different value so  
that the FECLK for PORT A (SB2W10) is driven at 10 mA (instead  
of the normal 5 mA).  
The results are that we added a little bit of reliability but the problem just shows up later but keep showing up. 
Back to Vince for discussion. 
 
Furthermore during the access we measured the resistance on the FECLK line for SB2W5 and it came out ot be 9 MOhms (compared with the nominal 120 Ohms). 
The resistance between PIN 1 (FECLK) and others is normal (120 Ohms) while the resistance between PIN 14 (FECLK*) and others is 9 MOhms (maybe open). 
The symptoms once again are very similar to SB2W10. 
 
<a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=118&frame=2&anchor=03:16:02'> 
Report from previous access </a>  
 
<a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=118&frame=2&anchor=11:05:45'> 
Report from previous investigation </a>  
 
</pre> 
  
<!-- Author: Gino Chris and Steve -->


<!-- Date: Fri Aug 9 14:24:10 2002 -->
<pre>&lt;a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=662&frame=2&anchor=13:47:01'&gt; 
Work done by Steve Nahn with the PITWIB this morning &lt;/a&gt;  
 
 
</pre>
<!-- Author: Gino for Steve -->
<!-- Comment: Fri Aug  9 14;25;46 comment by...Gino -->
<pre>Well, I tried but probably Steve can do better.
</pre>


<!-- Comment: Fri Aug  9 17;29;13 comment by...HTML Expert -->
<a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=662&frame=2&anchor=13:47:01'>Oop ack</a>
<!-- Date: Fri Aug 9 16:42:28 2002 -->
<pre>Had a temperature alarm on CCE1L6_1OUT.  Alarm threshold is  
19.0 degrees and it was reading 19.1.  Performing a cold start  
fixed it.</pre>
<!-- Author: Cigdem, Gino, Eva -->


<!-- Date: Fri Aug 9 16:44:24 2002 -->
<pre>In case it was not obvious, this was an ISL temp alarm.</pre>
<!-- Author: Eva H. -->


<!-- Date: Fri Aug 9 17:05:29 2002 -->
Did some torture testing and also probed L1 Done Timeouts.   
List of Runs and Rates are in the <a href= 
'/cgi/elog/det-system-elog.pl?nb=tsi&action=view&page=5&frame=2&anchor=13:42:08'>TSI elog</a> 
<!-- Author: SCN -->

<!-- Date: Fri Aug 9 17:28:16 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB3W1L4 
<li>problem n: 80 
<li>Status: needs_observation
<li>Action: Added_hdwdb
<li>entered by: cigdem 
<li>description is: <pre>Had to take out of the hardware database, because it was 
drawing high bias current (3300mC) at 15 V Bias. </pre> </ul>
<!-- Author: Problem DB -->




<!-- Date: Fri Aug 9 19:17:39 2002 -->
<pre>SVXMon has been passed on to the CO as of the evening shift. We will be around over the week-end to see how the COs are doing. 
</pre>
<!-- Author: Eva, Henri -->


<!-- Date: Sat Aug 10 07:30:06 2002 -->
<pre>L00 to OFF</pre>
<!-- Author: ADF -->


<!-- Date: Sun Aug 11 01:57:13 2002 -->
<pre>run  149686 - Please have a look at the shift e-log: we detected 
the following problems: 
 SB5 W9 L4   1 chip (phi) yellow 
 SB5 W9 L3   (z) all chips red</pre>
<!-- Author: milena deninno -->

<!-- Date: Sun Aug 11 02:22:00 2002 -->
<p><font size=+1> D-mode Calibration Job Started </font>
<p><pre>
Job id            : 181
Calibration type  : standard
Run period tag    : Aug_2002
DPS-off run       : 149689
DPS-on run        : 149688
Requested by      : Jim Kraus
Main process id   : 45189309
</pre>
<!-- Author: CDF silicon D-mode calibration job server v1.3 -->



<!-- Date: Sun Aug 11 02:29:27 2002 -->
<pre>When turning the system to standby post-quench, SB4W6 L3 showed an external trip; but the ladder's full status remained ON / SBY. 
Also, the trigger inhibit status page seems to list something 
in the last wedge as a trip.  Finally, iFix Global HV page  
does not turn off L00 when you tell it to. 
 
L00 OFF, SVX / ISL SBY</pre>
<!-- Author: ADF -->

<!-- Date: Sun Aug 11 14:48:44 2002 -->
<p><font size=+1> D-mode Calibration Job Started </font>
<p><pre>
Job id            : 182
Calibration type  : standard
Run period tag    : Aug_2002
DPS-off run       : 149709
DPS-on run        : 149706
Requested by      : Takashi Ogawa
Main process id   : 47530983
</pre>
<!-- Author: CDF silicon D-mode calibration job server v1.3 -->



<!-- Date: Mon Aug 12 10:30:42 2002 -->
<pre>Warm up of silicon to 16C begins. 
Changed temp limits to: 
SVX                   ISL                     L00 
BH      15-&gt;25        CC      20-&gt;25          SIL 15-&gt;25 
DOIM    20-&gt;25        CPC     15-&gt;25          Hyb 15-&gt;25 
PCW1A_2 28-&gt;30        blocked 33-&gt;35 
DDR     21-&gt;25         CC 
</pre>
<!-- Author: Eva -->
<!-- Comment: Mon Aug 12 14;17;49 comment by...Eva H. -->
<pre>We are warm.</pre>
<!-- Date: Mon Aug 12 10:32:43 2002 -->
<pre>This morning we had a problem with IFix Gui communication. 
Gui was updating and SVXinter was rebooted but  
did not fix the problem.  I restarted PSMon script 
on IFiX PC and communication was re-established.</pre>
<!-- Author: Eva H. -->



<!-- Date: Mon Aug 12 17:32:48 2002 -->
<P>Modified <b>IB1W4</b> and <b>IB4W5</b> power supplies so that their bias 0.1 channels have a splitting of 20% / 80% (from 0% / 100%).  Hopefully this will solve their pinhole problems. 
<p>
<!-- Author: Napora and Forrester -->
<!-- Comment: Mon Aug 12 18;49;51 comment by...Chris Hill -->
<pre>Thanks to these changes, IB1W4L0 and IB4W5L0 can now be depleted.</pre>
<!-- Date: Mon Aug 12 17:44:01 2002 -->
<pre>Access Report of Daniel, Josan and Cigdem 
========================================= 
 
We tried first to reproduce the errors on the ladders, we were 
planning to swap the RX's of.  
 
SB5W7L3	RX Swap		SE-CORNER (b0fib06) 
 
	Problem reproduced (see laser 1529.svx) with svxdaq. 
	Let's wait for Cigdem to swap the RX. 
	RX swap is made, and problem is fixed (see laser1535.svx). 
 
We took out RX 0355 and put in RX1139 (gold pinned).  
Problem is solved.  
 
SB2W6L4 RX Swap	        SW-CORNER (b0fib02) 
 
	Problem reproduced (see laser 1533.svx) with svxdaq. 
	Let's wait for Cigdem to swap the RX. 
	RX swap was made, but bit errors remain in e264 (bit 4) and  
	e271 (bit 1). 
	Another RX swap was made, but one bit error remains in e271 (bit 1). 
	This error can be recovered by the bank unpacker. 
 
On e264:    1) RX 0911 out   RX 0679 in (gold pinned) 
            2) RX 0679 out   RX 0161 in (gold pinned) 
               Problem solved! 
 
On e271: We first replug the Doim cable, this did not cure the 
         problem. Than we swap an RX: 
         RX0363 out RX 0537 in (gold pinned). 
         Problem remains! 
Since the detector is warm, we think we have a chance, that the  
bit error on 271 may be going away, after the detector is cooled 
again... 
 
IB0W1L1 This problem could not be reproduced (was bit 1 error). 
	No action needed! 
</pre>
<!-- Author: daniel, jason, cigdem -->
<!-- Comment: Tue Aug 13 01;02;55 comment by...Gino -->
SB2W7L1 bit 1 <a href=
'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=117&frame=2&anchor=15:07:27'>
IS A WELL KNOWN PROBLEM </a> nothing to worry about. The job is finished and well done
<!-- Date: Mon Aug 12 19:21:12 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB1W4L0 
<li>problem n: 404 
<li>Status: fixed
<li>Action: PS_work
<li>entered by: chill 
<li>description is: PS modified for 50k/200k HV-/HV+ split.  Sensor looks depleted at 55V (10V over nominal) drawing 746 uA.  HDWDB bias changed to 55V, current limit set to 1000 uA. </ul>
<!-- Author: Problem DB -->



<!-- Date: Mon Aug 12 19:28:38 2002 -->
<pre>SB2W5 
I peeled the plastic and the shield in a very limited area 
about 15 cm from the connector (this is the FIB timing cable 
at the end close to the FTM) and with resistance measurements 
I proved that the OPEN (High resitive path =~ 9-10 MOhms) is 
NOT on the first 15 cm from the connector.</pre>
<!-- Author: Gino -->
<!-- Comment: Mon Aug 12 19;34;42 comment by...Gino -->
<pre>Forgot to mention that The shield is back in shape and the 
little piece of plastic I removed is now replaced by a 
fair amount of kapton tape.</pre>

<!-- Date: Mon Aug 12 21:35:55 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB4W5L0 
<li>problem n: 539 
<li>Status: fixed
<li>Action: PS_work
<li>entered by: chill 
<li>description is: PS modified for 50k/200k HV-/HV+ split. Sensor looks depleted at 55V (10V over nominal)                                                                        drawing 752 uA. HDWDB bias changed to 55V, current limit set to 1000 uA.  </ul>
<!-- Author: Problem DB -->



<!-- Date: Tue Aug 13 00:48:48 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Tue_Aug_13_2002_004834.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-684  align='top'></td><td>FECLK signal with WEDGE OFF LIGHT GREEN and WEDGE ON BLUE for SB2W10</a></td></tr></table>
<!-- Author: gino -->
<!-- Comment: Tue Aug 13 00;51;57 comment by...GIno -->
<pre>The GRAY trace is C_CLK seeing 3 of them implies PARST.
Here are the resistance measurments:

SB2W10 resistance measurements:

RED	BLACK	R(Ohms)
feclk+ 	feclk- 	128.5
c-clk+	c-clk-	119.4
c-data+	c-data-	109.5
c0+	c0-	97.9
c1+	c1-	104.3
c2+ 	c2-  	92.3
c3+	C3-	95.0
c4+	c4-	103.9
beclk+	beclk-	102.1
l1a+	l1a-	120.0
prd2+	prd2-	120.6

Some numbers are lower than I expected still I cannot find a
 single short when I cross measure between various signals
</pre>

<!-- Comment: Tue Aug 13 00;57;48 comment by...Gino -->
Resistance measurements made today are different from <a href=
'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=118&frame=2&anchor=03:16:02'>
last access</a> This surprise me a little but I cannot explain it.






<!-- Date: Tue Aug 13 06:44:05 2002 -->
<pre>Begin to cool down the silicon. Heaters from outside COT are ON.</pre>
<!-- Author: Mircea Coca -->


<!-- Date: Tue Aug 13 09:53:41 2002 -->
<pre>I have cooled the silicon at 6 C. 
Changed the temperature trip limits to: 
SVX                   ISL                     L00  
 
BH      15        CC      20                SIL 15 
DOIM    20        CPC     15                Hyb 15  
PCW1A_2 28        blocked 33  
DDR     21        CCs  
======================================================= 
Now         
	      SVX    ISL   L00 
min temp       5      6      5 
max temp       7      10     7 
 
 </pre>
<!-- Author: Mircea Coca -->


<!-- Date: Tue Aug 13 11:49:15 2002 -->
<pre>Access Report of Daniel and Cigdem  
================================== 
 
We measured the light output of ISL B0W2L4 (SWT).  
Until we got everything setup the Silicon was cooled.  
We measured the lightoutput of Bit 0,1,2, and 3 and OBDV.  
All show low signals: 
OBDV ~50micro Watts 
Bits ~&lt;10micro Watts. 
 
We played with the connections to see if the light output is  
changing drastically, but this was not the case.  
We are veryfing what we see upstairs in the datastream.  
The bits 1,2,3 are stuck low. Where as bit 0 is somehow making  
it..... 
This ladders seems to have an internal problem.  
 
 
</pre>
<!-- Author: daniel and cigdem  -->
<!-- Comment: Tue Aug 13 12;36;16 comment by...SCN -->
In desparation mode we ought to check 2VDOIM and 5VDOIM voltages
and currents-however, hard to imagine how this affects one ladder
on the portcard.

<!-- Comment: Tue Aug 13 12;49;25 comment by...David -->
<pre>and check the fiber connection in the bore when there is access.</pre>


<!-- Date: Tue Aug 13 16:32:05 2002 -->
    <h1>Chip Checker Results</h1> 
I used Sean Tulin's Chip Checker feature to look for 
corrupt bitstreams coming back from the Fib crate.  Most of what I found is trivial <ul> 
<li>Ladders which don't exist but have bitstreams are usually wrong  
<li> Masked ladders return no info at all, so what is checked 
is what the <i>svxdaq</i> file has in it (typically read all (RA) DPS OFF) 
<li> Ladders are offline, so the DPS status (which is remapped in 
calibration) is incorrect if the last calibration run was DPS OFF. 
<li> Known ISEL = 0 set in HDWDB. 
</ul> 
I found two questionable ones in the hdwdb which I will ask Chris and Dave about and maybe Lester about. 
<h3>Questionable</h3> 
    <table> 
      <tr><th>Ladder<th>Chip(s)<th>Problem<th>Comment</tr> 
      <tr><td>IB0W4L4<td>8-15<td>Polarity = Other, Pipe Sel = 0, Cal Dir = Ramp Dir = 
	      Comp Dir = 1<td>This is how the hdwdb is set.  <a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=ISL&wedge=B0W4&layer=L4&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a></tr> 
      <tr><td>SB0W0L2<td>7,9<td>ISEL=0<td>Offline, AVDD2, why not Chip 8?</tr> 
       
    </table> 
     
    <h3>Trivial</h3> 
    <table> 
      <tr><th>Ladder<th>Chip(s)<th>Problem<th>Comment</tr> 
      <tr><td>SB0W6L3<td>0<td>ISEL=0<td>Chopped, <a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B0W6&layer=L3&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a></tr> 
      <tr><td>SB1W3L0<td>0-3<td>DPS OFF, RA<td>Offline, Masked <a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B1W3&layer=L0&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a></tr> 
      <tr><td>SB0W2L2<td>0-4<td>ISEL=0<td><a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B0W2&layer=L2&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a> (AVDD2)</tr> 
            <tr><td>SB5W5L0<td>0,1<td>ISEL=0<td><a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B5W5&layer=L0&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a> (Jumper) </tr> 
            <tr><td>SB4W9L4<td>0-6<td>ISEL=0<td><a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B4W9&layer=L4&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a> (Jumper)</tr> 
            <tr><td>SB3W8L0<td>0,1<td>ISEL=0<td><a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B3W8&layer=L0&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a> (Jumper)</tr> 
            <tr><td>SB5W1L4<td>0-5<td>ISEL=0<td><a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B5W1&layer=L4&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a></tr> 
            <tr><td>SB4W10L4<td>0-6<td>ISEL=0<td><a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B4W10&layer=L4&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a> (Jumper)</tr> 
            <tr><td>SB4W3L2<td>4<td>ISEL=0<td><a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B4W3&layer=L2&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a> (AVDD2)</tr> 
            <tr><td>SB3W3L4<td>10<td>ISEL=0<td><a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B3W3&layer=L4&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Problem DB</a> (AVDD2)</tr>       
      <tr><td>IB4W3L3<td>0-15<td>DPS OFF, RA, ISEL=0x65c<td>Uncooled</tr> 
      <tr><td>IB3W1L3<td>0-15<td>DPS OFF, RA, ISEL=0x65c<td>Uncooled</tr> 
      <tr><td>IB3W1L4<td>0-15<td>DPS OFF, RA, ISEL=0x65c<td>Uncooled</tr> 
      <tr><td>IB1W1L1<td>0-15<td>DPS OFF, RA, ISEL=0x65c<td>Uncooled</tr> 
      <tr><td>IB1W1L3<td>0-15<td>DPS OFF, RA, ISEL=0x65c<td>Uncooled</tr> 
      <tr><td>IB1W2L1<td>0-15<td>DPS OFF, RA, ISEL=0x65c<td>Uncooled</tr> 
      <tr><td>IB1W2L3<td>0-15<td>DPS OFF, RA, ISEL=0x65c<td>Uncooled</tr> 
      <tr><td>IB3W2L0-3<td>0-15<td>DPS OFF, RA, ISEL=0x65c<td>Uncooled</tr> 
      <tr><td>SB2W5LX<td>0-max<td>RA<td>Offline, SPT</tr> 
      <tr><td>SB1W7LX<td>0-max<td>RA, DPS OFF<td>Offline, Masked (Dead Wedge)</tr> 
      <tr><td>SB0W1L4<td>0-13<td>DPS OFF, RA<td>Offline, Masked, <a href='http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBsearch.pl?detsys=SVX&wedge=B0W1&layer=L4&problem=Any&group=Any&status=Any&type=Any&action=Any&search=Latest&date=Any&sortby=None'>Unfixable</a> </tr> 
      <tr><td>IB2W2L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>IB3W2L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>IB2W3LX<td>0-max<td>Various<td>Doesn't Exist/SOC/PitWib</tr> 
      <tr><td>IB3W3LX<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB0W0L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB0W1L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB0W2L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB0W3L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB0W4L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB0W5L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB1W0L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB1W1L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB1W2L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB1W3L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB1W4L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
      <tr><td>LB1W5L4<td>0-15<td>Various<td>Doesn't Exist</tr> 
    </table> 
We'll try to program in some if not all of these so we can  
see real problems.  Right now there is no evidence of corruption 
in the stored bitstreams on the Fib crate.
<!-- Author: SCN -->


<!-- Date: Tue Aug 13 21:27:16 2002 -->
<h3>Further investigation on SB2W10 and SB2W5</h3> 
Gino should make an entry too or comment on this one.  We went 
in this morning and made further invstigations on SB2W5 and SB2W10.  We found <ul> 
<li>SB2W5 has a 8 MOhm termination resistance on FE CLOCK (known from before).  We had some trouble seeing the CLK with the diff. probe until we swtiched the probe option of DC reject on, then we could see the signal differentially.  Not sure what this means.  Gino has pictures on the disk to add. 
<li> SB2W10 seems to have a thermal behaviour.  Resistance measurements have shown <a href= 
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=119&frame=2&anchor=00:48:48'>various values</a> and this time FE CLOCK looked fine until the PC and ladders had been turned on, then 
it suddenly changed shape.  Once it was bad (again. Gino has pictures) we measured infinite resitance between the lines.   
After some time with the ladders/PC off, the resistance came 
back to Gino's original measurement of 155 Ohm.  Both Gino 
and I made measurements to check each other's work, everything seems consistent with a time dependent (thermal?) open in the 
FE CLOCK lines. 
</ul> 
We will post the pictures here and also show them to Vince to see if there are suggested kludges to the DAQ we can do to overcome these problems.  The real fix would be to find the source of  
the resistances and fix/replace them.  
<!-- Author: SCN, Gino -->


<!-- Date: Tue Aug 13 22:57:19 2002 -->
This store began with lumi around 24E30.  Losses look reasonable -- none higher than 10kHz.<BR> 
However, COT SL2 trip is still there.  As a result, I see no reason to bring silicon into the run.<BR>  
<!-- Author: Jason -->


<!-- Date: Tue Aug 13 23:28:14 2002 -->
Just got off the phone with Gino.  In light of the COT problems this store, and assuming this will be a long store, we decide to go ahead with the temperature scan.  (See  
<a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=669&frame=2&anchor=20:02:27'> 
Gino's instructions in the CDF shift e-log</a>.)  
<!-- Author: Jason -->


<!-- Date: Wed Aug 14 00:11:16 2002 -->
Silicon is in without too much trouble.
<!-- Author: Jason -->

<!-- Date: Wed Aug 14 02:10:51 2002 -->
<p><font size=+1> D-mode Calibration Job Started </font>
<p><pre>
Job id            : 183
Calibration type  : standard
Run period tag    : Aug_2002
DPS-off run       : 149851
DPS-on run        : 149841
Requested by      : Jason Nielsen
Main process id   : 55254423
Comment           : trigger inhibit ignored
</pre>
<!-- Author: CDF silicon D-mode calibration job server v1.3 -->



<!-- Date: Wed Aug 14 03:01:21 2002 -->
Trigger was inhibited by e202. 
<BR>  VBiasSet was set to 2.0 in the GUI, but the VBias read 38V.  We remembered that this is the half-ladder which touches e302, and it should be biased at 55V according to problem db. 
<BR> 
I don't understand how this got set to 2.0V in the GUI.  VBias in the hdwdb has been 55V since April at least. 
<BR> 
After the change, the trigger is no longer inhibited.
<!-- Author: Jason -->
<!-- Comment: Wed Aug 14 09;05;11 comment by...Andy H. -->
After <b>what</b> change?
<!-- Comment: Wed Aug 14 12;08;43 comment by...Jason -->
Changed VBiasSet for e202 to 55V in the GUI by hand, matching the bias for e302.
<!-- Comment: Thu Aug 15 08;38;43 comment by...Jason -->
Problem was that e202 had status ON in the GUI, and I used the GUI to turn things ON one-by-one instead of using iFix.  Consequently e202 stayed in quasi-ON state, biased via contact with e302.
<!-- Date: Wed Aug 14 03:09:08 2002 -->
<pre>We are cooling down the silicon from 6 C to 2 C. </pre>
<!-- Author: Mircea Coca -->


<!-- Date: Wed Aug 14 04:18:10 2002 -->
<pre>CDF run 149859 is taken with SVX/L00 coolant at +2C.</pre>
<!-- Author: ADF -->


<!-- Date: Wed Aug 14 05:59:43 2002 -->
<pre>I've lowered the temperature for SVX to 0 C. ISL is untouched. 
 Changed the chiller evaporator temperature low limit from 0 C 
 to -10 C for the moment.  </pre>
<!-- Author: Mircea C -->


<!-- Date: Wed Aug 14 07:28:29 2002 -->
<pre>CDF run 149866 is the T=-2C run</pre>
<!-- Author: ADF -->



<!-- Date: Wed Aug 14 11:35:05 2002 -->
<center><a href='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-685&button=yes' target='xxx' onclick='jswindow()'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-685' width='300'></a><a href='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-686&button=yes' target='xxx' onclick='jswindow()'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-686' width='300'></a><a href='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-687&button=yes' target='xxx' onclick='jswindow()'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-687' width='300'></a></center>
<!-- Author: Gino -->
<!-- Comment: Wed Aug 14 11;39;22 comment by...Gino -->
<pre>These pictures show a rough (very rough) behavior of the power 
consumtion due to the BIAS lines on the 3 system (SVX, L00 and 
ISL) during the temperature scan.

These are the plots made by IMON online.
There is a gap of roughly 2-3 hours between 6 and 8:30 without entries.
Overall we can see how the temperature is affecting the leakage 
current.

Obviously a more detailed analisys is necessary OFFLINE.
</pre>


<!-- Date: Wed Aug 14 11:52:48 2002 -->
<pre>Summary of the new cooling conditions implied by the fact   
we are running at a much lower temperature; from 6C to -6C.  
  Temp trip limits(old limits are b/w brackets);  
 
         SVX                  L00   
---------------------------------------------------------------  
BHs     6 (15)               SIL 5 (15)        
DOIMs   13(20)               HYB 5 (15)  
PCW1A_2 20(28)           
DDR     14(21)  
 
These temperatures are based on a simple rule; take maximum + 5C 
and they will be fine tuned along the way. 
The warning/alarm limits in the Global Alarm page are updated   
to the new conditions.  
 The chiller supply/return temperature ranges are; 
TE_CHSUP       -7.5        -2.0  C 
TE_CHRLR_1     -7.5        -2.0  C  
 
The conductivity in SVX line stayed at 4 mSm/cm during the  
cooling process.  
 
 
  </pre>
<!-- Author: Mircea Coca -->


<!-- Date: Wed Aug 14 13:23:32 2002 -->
<p><font size=+1> D-mode Calibration Job Started </font>
<p><pre>
Job id            : 184
Calibration type  : standard
Run period tag    : Aug_2002
DPS-off run       : 149881
DPS-on run        : 149880
Requested by      : Kathy Copic
Main process id   : 56652759
</pre>
<!-- Author: CDF silicon D-mode calibration job server v1.3 -->



<!-- Date: Wed Aug 14 14:34:03 2002 -->
<h3>Calibration Configuration</h3>Since Jason had a hell of a time running the EVB in a partitioned mode last night, I implemented some of Ilya's recommendations in DaqTest/SVXCAL. 
It seems to work, however<ul> 
<li>When running with the EVB partitioned, an ACTIVATE on  
one partition seems to cause a BUSY timeout on the other 
<li>When including the Muon Scintiillator Crate you might 
fail if the other partition is using either muon or SVT crates  
you will fail to book "DAQ_VRB_00" 
<li> Right now the rate is adjusted to be about 10 MB/s, which is 
low enough for being able to run in partitioned mode. 
<li> EVB and L3 commands from seperate partitions are processed  
serially, so you might have to wait for the other partition's 
COLD START to occur before your RECOVER proceeds (for example). 
</ul> 
The Silicon D Mode calibration, having these huge enourmous events, is quite sensitive to EVB issues.  It might be best to 
take all of Level 3 when trying to do this.  If so, we can also 
increase the rate by about x2. 
<!-- Author: SCN -->

<!-- Date: Wed Aug 14 14:41:29 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB1W0L0 
<li>problem n: 604 
<li>Status: needs_observation
<li>Action: Init_RB_mask
<li>entered by: nahn 
<li>description is: In process of  <a href= 'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=119&frame=2&anchor=14:34:03'> testing calibration mode</a> I hade to mask off the readback. It reads back all ffs.   </ul>
<!-- Author: Problem DB -->


<!-- Date: Wed Aug 14 15:14:59 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB2W7L4 
<li>problem n: 605 
<li>Status: needs_observation
<li>Action: Init_RB_mask
<li>entered by: chill 
<li>description is: Init failed several times during cold start.  Note this is first cold start after temperature was changed to -6 deg. </ul>
<!-- Author: Problem DB -->



<!-- Date: Thu Aug 15 08:35:58 2002 -->
After quench at 2:29 this morning, silicon stayed ON, with no trips.<BR> 
It looks like a clean quench in the silicon radiation plots.  (I am looking at them with the monitoring ace.) 
Unfortunately the following runs were cosmic runs, so the FIBs were out.  As a result the silicon system has not been cold-started since the quench. 
  
<!-- Author: Jason -->
<!-- Comment: Thu Aug 15 09;46;55 comment by...chill -->
<pre>Post-quench SOP (even if looks clean):

1) Perform COLD START (in your own partition or w/ CDF)
2) Check L00 crowbars by checking current drawn on bias.
   All but a few (~3) ladders should draw current even at STANDBY

*There is no need to go to OFF, but if the system has largely
 tripped off already or there was an accelerator failure which
 you think will make the next shot ugly you can do so at your
 own discretion.  Feel free to consult w/ Gino or myself. </pre>

<!-- Comment: Thu Aug 15 12;25;57 comment by...ADF -->
<pre>Lack of coldstart due to shift crew pilot error; intention
was to run with silicon in CDF, but loading the default
cosmics configuration kicked out the silicon crates.

System was turned off due to onset of TeV studies, which
are completely unpredictable, not due to the quench and
subsequent quiet time.</pre>
<!-- Date: Thu Aug 15 09:52:44 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB0W4L4 
<li>problem n: 139 
<li>Status: needs_observation
<li>Action: Currents_investigated
<li>entered by: chill 
<li>description is: IV performed, Draws ~500uA at operating voltage.  Current limit changed to 1000uA and ladder now being run biased (was being run at 3V).  Need to see from data if this ladder is getting depleted at 45V. </ul>
<!-- Author: Problem DB -->


<!-- Date: Thu Aug 15 09:54:49 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB0W4L4 
<li>problem n: 607 
<li>Status: fixed
<li>Action: Diagnosis
<li>entered by: chill 
<li>description is: Incorrect bitstream detected by online chip checker.  Was legacy guinea pig settings from p/n asymmetry studies.  Correct bitstream now in place. </ul>
<!-- Author: Problem DB -->


<!-- Date: Thu Aug 15 10:38:04 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB0W4L4 
<li>problem n: 139 
<li>Status: fixed
<li>Action: Currents_investigated
<li>entered by: chill 
<li>description is: Probably has a pinhole.  Changed bias voltage to 55V and now sensor is definitely depleted.   </ul>
<!-- Author: Problem DB -->




<!-- Date: Thu Aug 15 13:58:02 2002 -->
<h3>Post quench diagnosis and a little X mode</h3> 
I turned the Silicon to Standby with the intention of trying 
to work on X mode and also check that everything still intializes.  Sequence of Events <ul> 
<li> Power to Standby was kinda rocky<BR>Immediate trips <ul> 
<li> SB0W6 L1 AVDD OVC -> try again, trip -> try again, trip -> power Off then On whole Wedge, OK 
<li> SB1W2 2VDOIM OVC -> Turn on PC, OK -> Turn on Wedge, OK 
<li> IB1W4 L4 (A/D?)VDD OVC -> try again, OK 
</ul> 
After a little bit trips<ul> 
<li> IB4W1 L? External Trip -> try again, OK 
<li> SB4W9 L4 AVDD OVC -> try again, OK 
<li> SB1W5 L0 DVDD OVC -> try again, OK 
</ul> 
<li> <B> All Ladders Initialize OK </B> 
<li> X Mode has some trouble with L00 data, to be analyzed. 
</ul> 
Gave the DAQ to Chris for ISL work
<!-- Author: SCN -->

<!-- Date: Thu Aug 15 14:23:13 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB0W4L0 
<li>problem n: 135 
<li>Status: unfixable
<li>Action: Diagnosis_update
<li>entered by: chill 
<li>description is: The first half-ladder has a FE that is saturated most of the time due to the problems diganosed above.  Occasionally it is not saturated, does it see physics?  I have increased the bias voltage from 3V to 58V so that we can find out. </ul>
<!-- Author: Problem DB -->


<!-- Date: Thu Aug 15 19:39:10 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB1W5L4 
<li>problem n: 11 
<li>Status: needs_bore_access
<li>Action: Removed_hdwdb
<li>entered by: nielsenj 
<li>description is: reformatter, yes, but also light output probs at bore (prob unfixable) </ul>
<!-- Author: Problem DB -->
<!-- Comment: Thu Aug 15 19;47;44 comment by...Chris, Jason -->
Seems unfixable, to tell the truth.  The light output measurement in <a href=
'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=112&frame=2&anchor=18:44:13'>this e-log entry</a> look like the pulses are malformed by the Tx.  Are the resistor driver bits already maxed out?
<!-- Date: Thu Aug 15 19:42:00 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB0W6L3 
<li>problem n: 609 
<li>Status: needs_observation
<li>Action: Init_RB_mask
<li>entered by: nielsenj 
<li>description is: History of failed init (as does rest of wedge) </ul>
<!-- Author: Problem DB -->



<!-- Date: Thu Aug 15 21:04:32 2002 -->
<p><font size=+1> D-mode Calibration Job Started </font>
<p><pre>
Job id            : 185
Calibration type  : standard
Run period tag    : Aug_2002
DPS-off run       : 149909
DPS-on run        : 149910
Requested by      : Jason Nielsen
Main process id   : 61236188
</pre>
<!-- Author: CDF silicon D-mode calibration job server v1.3 -->



<!-- Date: Thu Aug 15 22:17:55 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Thu_Aug_15_2002_221517.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-690  align='top'></td><td>latest run SVT good wedges. Did Not change much since  august 9th. </a></td></tr></table>
<!-- Author: Gino -->
<!-- Comment: Thu Aug 15 22;22;56 comment by...Gino -->
<pre>To be compared with the same plot taken on &lt;a href=
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=663&frame=2&anchor=20:23:23'&gt;
August 9th &lt;/a&gt; .
&lt;table&gt;&lt;tr&gt;&lt;td&gt;&lt;a href=/cgi/elog/elog.pl?nb=2002&action=view&page=-5761&button=yes
target='xxx' onclick='jswindow()'; align=top&gt;&lt;img
src=/cgi/elog/elog.pl?nb=2002&action=view&page=-5761 width='300' align='top'&gt;&lt;/td&gt;&lt;td&gt;This is the plot form August 9th. &lt;/a&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/table&gt; &lt;BR&gt;

Still some work to do on both sides Silicon group and SVT to cover the holes.

The stability over a week should be taken as a good signal.

</pre>

<!-- Comment: Thu Aug 15 22;23;09 comment by...Gino -->
<pre>To be compared with the same plot taken on &lt;a href=
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=663&frame=2&anchor=20:23:23'&gt;
August 9th &lt;/a&gt; .
&lt;table&gt;&lt;tr&gt;&lt;td&gt;&lt;a href=/cgi/elog/elog.pl?nb=2002&action=view&page=-5761&button=yes
target='xxx' onclick='jswindow()'; align=top&gt;&lt;img
src=/cgi/elog/elog.pl?nb=2002&action=view&page=-5761 width='300' align='top'&gt;&lt;/td&gt;&lt;td&gt;This is the plot form August 9th. &lt;/a&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/table&gt; &lt;BR&gt;

Still some work to do on both sides Silicon group and SVT to cover the holes.

The stability over a week should be taken as a good signal.

</pre>

<!-- Comment: Thu Aug 15 22;25;59 comment by...Gino -->
You can see I'm not that good with HTML. Still learning but Here is what I wanted to do 
<table><tr><td><a href=/cgi/elog/elog.pl?nb=2002&action=view&page=-5761&button=yes
target='xxx' onclick='jswindow()'; align=top><img
src=/cgi/elog/elog.pl?nb=2002&action=view&page=-5761 width='300' align='top'></td><td>This is the plot from August 9th. </a></td></tr></table> <BR>

<!-- Date: Fri Aug 16 11:13:36 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: LB0W0L0 
<li>problem n: 285 
<li>Status: fixed
<li>Action: Swap_RX
<li>entered by: chill 
<li>description is: 326 out, 322 in, bit 0 problem fixed.  No problems in svxdaq. </ul>
<!-- Author: Problem DB -->



<!-- Date: Fri Aug 16 11:15:15 2002 -->
<pre>2 hours access report: 
 
	SB2W7L4 swapped the RX because Bit 2 and 3 are stuck LOW 
		It did NOT solve the problem. 
		Swapped fibers between SB2W7L4 and SB2W7L3 
		the problem stays with SB2W7L4 so it is  
		somewhere internal 
		NEXT STEP LIGHT INVESTIGATION 
 
	LB0W0L0 swapped RX because Bit 0 stuck LOW 
		Problem SOLVED. 
</pre>
<!-- Author: Jason, Chris, Gino and more -->
<!-- Comment: Fri Aug 16 11;18;36 comment by...Gino -->
<pre>Ladder		RX Out		GOLD Pinned RX In
SB2W7L4		#286		Not recorded 
LB0W0L0		#326		#332

Sorry I forgot to record the ID of the RX I put in Sb2W7L4</pre>