<!-- Title: 11:35:53  Thu Nov 28 2002 -->
<!-- Crewchief: Gino and Steve -->
<!-- Op1: &nbsp; -->
<!-- Op2: &nbsp; -->
<!-- Op3: &nbsp; -->
<!-- Op4: &nbsp; -->
<!-- Op5: &nbsp; -->
<!-- Op6: &nbsp; -->
<!-- Notes: -->
<pre>New File. 
Happy thanksgiving. 
Silicon Is back to OFF state due to another kicker pre-fire. 
We had 3 of them in the month of November: 
11/09/2002 
11/22/2002 
11/28/2002 
This is very very unusual. 
The Silicon will stay OFF untill: 
1. The Beam division investigate the extremely high rate of  
   prefires during this month and evaluate the risk for the  
   near term 
2. A list of the kicker prefire incidents (including run 1 and  
   run 2 data) is provided to the CDF Silicon group. 
 
Once these information will be available we will review the  
decision to stay OFF. 
   
</pre>

<!-- Date: Tue Dec 3 10:38:00 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB4W8L2 
<li>problem n: 48 
<li>Status: unfixable
<li>Action: Diagnosis_update
<li>entered by: chill 
<li>description is: Studied w/ SVXDAQ.  The ladder does not init (currents never go to initialized values).  The ladder does not readout either (no channel, no data - only ffd0d0c2 c2c4).  Since other ladder in this FIB are ok, this is an internal problem (something is seriously wrong with the PC to ladder communication for this channel).  It is hard to tell more than this since it doesn't function at all.   
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B4W8&layer=L2">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Tue Dec 3 17:29:32 2002 -->
<pre>Access Report Julia,Cigdem,Chris 
================================ 
 
We measured the resistance of the fib command  
cable head. All values are normal and we did not find 
anything abnormal: 
 
FE_CLK+ to FE_CLK-  122.4 ohm 
FE_CLK- to FE_CLK+  122.5 ohm 
FE_CLK+ to C_CLK+   120.1 ohm 
FE_CLK+ to C_CLK-   120.0 ohm 
FE_CLK+ to C_DATA+  117.4 ohm 
FE_CLK+ to C_DATA-  117.8 ohm 
FE_CLK- to C_CLK+   122.4 ohm 
FE_CLK- to C_CLK-   122.3 ohm 
FE_CLK- to C_DATA+  119.4 ohm 
FE_CLK- to C_DATA-  119.9 ohm 
 
We than measured parasitacaly the command cable signals and they 
looked fine.  
Except that we did not find the signal for L1A, which is  
most probably related to our unexperience to operate the  
scope. Chris told us, that he is getting data upstairs..... 
 
We asked Chris to try to run e25_all and see if the layers 
are still tripping.  
Except for layer 4, which may have his own problem all the  
other layers were behaving fine and they did not trip.  
 
We decided to swap the FTM board, because, we did not find  
anything wrong with the cable or the signals. May be  
plugging in and out the fib command head from the FTM board  
is somehow due to a flacky contact on the FTM board causing 
the layers not to trip for a while.  
So, we gave it a try and swap the FTM board.  
IN 564035 OUT 563648 
 
We will test the FTM taken out in FCC and see if our assumption  
about the flacky contact on this board is true.  
 
Before we swap the FTM the e24/5_all were tested by Chris.  
The post-testing was ok. We did not introduce any new 
problems.  
e25 is running except of layer4.  
We have to observe its behaviour and see if it will go back to its former habit to trip on DVDD OC.  
 
 
</pre>
<!-- Author: cigdem -->
<!-- Comment: Wed Dec  4 08;26;40 comment by...SCN -->
<ul>
<li> L1A is an active low signal (different from all the rest) so
you either need to turn the probe around or change the trigger level
<li> Many similar investigations have already been done <ol>
<li> <a href=
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=118&frame=2&anchor=11:05:45'>
08/02/02 Out for SPT </a>
<li>  <a href=
'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=119&frame=2&anchor=08:42:23'>
08/09/02 FECLK* seen at 9 MOhm </a>
<li> <a href=
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=119&frame=2&anchor=19:28:38'>
08/12/02 Cable peeled/wiggled to investigate for opens </a>
<li>  <a href=
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=119&frame=2&anchor=21:27:16'>
08/13/02 8 MOhm reconfirmed </a>
<li> <a href=
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=127&frame=2&anchor=10:45:40'>
10/22/02 Resistance looks ok </a> Reintegrated
<li> <a href=
'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=131&frame=2&anchor=09:39:00'>
11/22/02 L4 won't init, (DVDD OVC) Kicked out </a> 
<li>  <a href=
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=131&frame=2&anchor=22:12:12'>11/25/02  Layers 1,2,3 removed b/c of constant trips</a> No entry in PDB...
<li> <a href=
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=132&frame=2&anchor=04:14:49'>
11/26/02 L0 removed b/c bit 6 problem and excessive stuck cap ids</a> 
</ol>
<ul>
Perhaps we could investigate between 10/22 and 11/22 to see
what gives?
<!-- Comment: Wed Dec  4 08;27;12 comment by...      -->
</ul>
<!-- Comment: Wed Dec  4 08;29;13 comment by...     -->
</ul>
<!-- Date: Tue Dec 3 17:58:06 2002 -->
<h3>PS Access Report</h3> 
Swapped low-voltage & sense cables from SB5W4 to SB4W5.  According to Chris on the DAQ upstairs, this had no positive effect.  We wanted to test the light-output here but we ran out of time while we were trying to get the scope setup to make the measurement.  
<!-- Author: mumford and napora -->

<!-- Date: Tue Dec 3 19:51:01 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB5W4All 
<li>problem n: 758 
<li>Status: needs_access_2hr
<li>Action: Diagnosis_update
<li>entered by: chill 
<li>description is: Increased current limit to 2330 mA.  Ran w/ SVXDAQ.  Init stream is not read back, but ladders do get initialized (from currents). No data is readout either, as if no light is being put out of the DOIM.  Theory is that the resistive path through which the extra  current flows causes a voltage drop, so that the DOIMs are underpowered.  To test we moved the cables on access to a PS which was configured to run the DOIMs hotter (2V DOIM was 150 mV lower). This did not change the result.  Need to do light-output measurement.       
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B5W4&layer=All">report</a></ul>
<!-- Author: Problem DB -->





<!-- Date: Wed Dec 4 08:48:01 2002 -->
<p><font size=+1> D-mode Calibration Job Started </font>
<p><pre>
Job id            : 213
Calibration type  : standard
Run period tag    : Dec_2002
DPS-off run       : 154691
DPS-on run        : 154692
Requested by      : Jason Nielsen
Main process id   : 38142832
</pre>
<!-- Author: CDF silicon D-mode calibration job server v1.3 -->


<!-- Date: Wed Dec 4 12:35:12 2002 -->
<p><font size=+1> D-mode Calibration Job Finished </font>
<p><pre>
This is a computer-generated silicon D-mode calibration status report.
Silicon D-mode calibration job 213 FAILED.

Job info
--------
Calibration type : standard
DPS-off run      : 154691
DPS-on run       : 154692
Requested by     : Jason Nielsen
Submitted        : 2002-12-04 06:45:09
Completed        : 2002-12-04 10:32:35
Status           : FAILURE

Last processing stage reported : combining ROOT files
Failure diagnostics :
Failed to combine pulse height histograms in 3 case(s):
Run 154692, software dps false.
Run 154691, software dps false.
Run 154691, software dps true.
Exiting.
</pre>
<!-- Author: D-mode script run_calib_analysis.tcl -->



<!-- Date: Wed Dec 4 15:24:39 2002 -->
We were getting warnings about high COT-face pressures on the 
L00 flow loops.  This was because the SVX air separator pressure 
was pretty high due to the normal slow degradation of the vacuum. 
Jim E. switched the system over to a different vacuum pump and 
will rebuild the old one as per usual
<!-- Author: Andy H. -->


<!-- Date: Wed Dec 4 16:48:31 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Wed_Dec__4_2002_164820.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1044  align='top'></td><td>AVDD current of e3b1 on 03-30-2002.</a></td></tr></table>
<!-- Author: David -->
<!-- Comment: Thu Dec  5 11;04;39 comment by...David -->
<B>AVDD2 Investigation</B></br>

<OL>
<LI>AVDD Current Drop:  The above current plot shows a drop of  ~240uA on Mar 30th. This would be consistent with an 80uA drop due to damage of chip 2 plus a drop of 160uA (2 x 80uA) from chips (0 and 1) downstream of initialization.</LI>
<LI>Initialization History:  The Initialization Summary tool shows a drastic increase in init. failures after Mar. 30th.</LI>
<LI>Today's Run:  Doesn't Initialize; reads back 0's. Last Pulse Histogram shows chip 2 is damaged and chips 0 and 1 are "dead" as expected from above AVDD current plot.</LI>
<LI>BE of Chip:  Back end of chip 2 responds as expected when ramp pedestal is changed.</LI>
<LI>FE of Chip:  Front end of chip 2 does not respond - the AVDD current does not change - when ISEL bits are all set to 0.</LI>
</UL>
<B>Conclusion</B></br>
</br>
All 5 symptoms are consistent with AVDD2 bond breaks: A textbook case!

<!-- Comment: Thu Dec  5 12;44;35 comment by...David -->
<br>
Units typo in item 1 above: all uA should be mA.<br>

<!-- Comment: Sat Feb 22 13;17;31 comment by...fix -->
<pre>&lt;/ol&gt;</pre>
<!-- Comment: Sat Feb 22 13;17;48 comment by...html -->
</ol>
<!-- Date: Thu Dec 5 14:07:25 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB1W0All 
<li>problem n: 691 
<li>Status: fixed
<li>Action: Diagnosis_update
<li>entered by: sforrest 
<li>description is: Problem appeared after quench 09/21/02 <a href= 'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=124&frame=2&anchor=19:05:57'> e-log entry</a>  Problem seemed to have resolved itself after access on 09/27/02 <a href= 'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=124&frame=2&anchor=19:49:47'> e-log entry </a> <br> During access an Rx swap on an adjacent FTM was performed.  DRO could be caused by poor connections for this wedge.   
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B1W0&layer=All">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Thu Dec 5 14:29:47 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB2W5All 
<li>problem n: 599 
<li>Status: needs_observation
<li>Action: Added_hdwdb
<li>entered by: sforrest 
<li>description is: Wedge failed slowly over time between 11/06/02 with layer 4 being removed from hwdb.  By 11/27/02 entire wedge was removed from hwdb.  After <a href= 'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=133&frame=2&anchor=17:29:32'> FTM swap</a>  only layer 4 still seems to be tripping.    
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B2W5&layer=All">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 02:16:40 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB2W9L4 
<li>problem n: 5 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: bolla 
<li>description is: <pre>Lowered the AVDD Limit in IMON from 1035 to 1030</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B2W9&layer=L4">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 02:20:49 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: LB0W3L3 
<li>problem n: 107 
<li>Status: fixed
<li>Action: IMON_limits
<li>entered by: bolla 
<li>description is: <pre>BIAS 1 Upper limit changed to 20 uA</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=L00&wedge=B0W3&layer=L3">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Fri Dec 6 02:38:55 2002 -->
<pre> 
Silicon is back into data taking. 
 
TRansistion from OFF to STDBY SB0W5-6 refused to go brought them up by hand succesfully. 
 
Transition from STDBY to ON SB1W6 refused to go brought up by hand succesfully. 
 
Taken data on my own partition without any problem. 
 
Given Silicon to CDF and a lot of trouble started due to a <a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=1017&frame=2&anchor=02:01:54'> 
SVT problem </a> that made me stay very long and Steve Nahn to spend one hour on the phone. 
 
Some PINKIES in IMON here is the list: 
SB2W9L4 AVDD lowered by 5 more mA  
SB2W5L0 BIAS raised (was off for a while so radiation damage was  
                    not reflected on IMON limits) 
IBIW4L2 B1, IB5W3L4 B0, IB5W2L2 B0, IB4W2L0 B0,  
IB1W5L4 B0, IB1W4L0 B0, IB1W0L0 B0, IB0W5L0 B0  
IB0W1L0 B1  
are now drawing 0 current. lowered their limits and passed the ball to the monitoring to check for physics. 
 
 
  
</pre>  
<!-- Author: Gino -->

<!-- Date: Fri Dec 6 02:46:06 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB0W1L0 
<li>problem n: 801 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: bolla 
<li>description is: <pre>0 bias current on BIAS1. Changed IMON lower limit. Check for Physics.</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B0W1&layer=L0">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 02:48:17 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB0W5L0 
<li>problem n: 802 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: bolla 
<li>description is: <pre>0 bias current on BIAS0. Changed IMON lower limit. Check for Physics.</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B0W5&layer=L0">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 02:49:12 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB1W0L0 
<li>problem n: 803 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: bolla 
<li>description is: <pre>0 bias current on BIAS0. Changed IMON lower limit. Check for Physics.</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B1W0&layer=L0">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 02:51:47 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB1W4L0 
<li>problem n: 804 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: bolla 
<li>description is: <pre>0 bias current on BIAS0. Changed IMON lower limit. Check for Physics.</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B1W4&layer=L0">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 02:53:21 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB1W5L4 
<li>problem n: 805 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: bolla 
<li>description is: <pre>0 bias current on BIAS0. Changed IMON lower limit. Check for Physics.</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B1W5&layer=L4">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 02:53:56 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB4W2L0 
<li>problem n: 806 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: bolla 
<li>description is: <pre>0 bias current on BIAS0. Changed IMON lower limit. Check for Physics.</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B4W2&layer=L0">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 02:55:13 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB1W4L2 
<li>problem n: 807 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: bolla 
<li>description is: <pre>0 bias current on BIAS1. Changed IMON lower limit. Check for Physics.</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B1W4&layer=L2">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 02:55:26 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB5W2L2 
<li>problem n: 151 
<li>Status: needs_observation
<li>Action: Action_request
<li>entered by: bolla 
<li>description is: <pre>0 bias current on BIAS0. Changed IMON lower limit. Check for Physics.</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B5W2&layer=L2">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 02:56:14 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB5W3L4 
<li>problem n: 808 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: bolla 
<li>description is: <pre>0 bias current on BIAS0. Changed IMON lower limit. Check for Physics.</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B5W3&layer=L4">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 03:24:28 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB2W0L4 
<li>problem n: 809 
<li>Status: needs_observation
<li>Action: Incident
<li>entered by: bolla 
<li>description is: <pre>No data in SVXMON (assuming I read correctly the name in SVXMON)</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B2W0&layer=L4">report</a></ul>
<!-- Author: Problem DB -->
<!-- Comment: Fri Dec  6 08;39;41 comment by...chill -->
<pre>You did read the name correctly, it looks like an OBDV problem.</pre>
<!-- Date: Fri Dec 6 03:31:20 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB4W2All 
<li>problem n: 810 
<li>Status: needs_observation
<li>Action: Monitoring
<li>entered by: bolla 
<li>description is: <pre>in RUN 155113 this is the only wedge causing HRR from SVXMON.
Looking at SVXMON all ladders in this wedge get in the 
'Stuck ladder' mode.</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B4W2&layer=All">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Fri Dec 6 06:38:30 2002 -->
<pre>Paged for more ISL sensors drawing zero current on bias. 
 
IB1W4L4 bias0 - redefined range 0.0 to 10.0 uA, nominal was 40. 
IB5W4L2 bias0 - rededined range 0.0 to 10.0 uA, nominal was 38. 
 
These need to be checked for physics, although I think this is  
probably just "normal" post-off behavior for ISL micron sensors.  
 
Note: PDB appears to be down.</pre>
<!-- Author: chill -->

<!-- Date: Fri Dec 6 08:34:32 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB2W0L4 
<li>problem n: 809 
<li>Status: needs_access_2hr
<li>Action: Diagnosis
<li>entered by: chill 
<li>description is: 100% No chip ID, c2c2 termination since 155111.  AVDD, DVDD, DOIM currents normal. Suspect OBDV problem, should pursue Rx swap. 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B2W0&layer=L4">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Fri Dec 6 08:43:55 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB1W4L4 
<li>problem n: 811 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: chill 
<li>description is: Redefined bias0 range (0-10uA), prior nominal was 40.  Check for physics. 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B1W4&layer=L4">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 08:55:52 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB5W4L2 
<li>problem n: 812 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: chill 
<li>description is: Redefined bias0 range (0-10uA), prior nominal was 38. Check for physics.   
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B5W4&layer=L2">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Fri Dec 6 19:10:06 2002 -->
<p><font size=+1> D-mode Calibration Job Started </font>
<p><pre>
Job id            : 214
Calibration type  : standard
Run period tag    : Dec_2002
DPS-off run       : 155119
DPS-on run        : 155117
Requested by      : JJ Schmidt
Main process id   : 4274277
Comment           : see Eve shift elog 6-Dec
</pre>
<!-- Author: CDF silicon D-mode calibration job server v1.3 -->


<!-- Date: Fri Dec 6 23:09:37 2002 -->
<p><font size=+1> D-mode Calibration Job Finished </font>
<p><pre>
This is a computer-generated silicon D-mode calibration status report.
Silicon D-mode calibration job 214 FAILED.

Job info
--------
Calibration type : standard
DPS-off run      : 155119
DPS-on run       : 155117
Requested by     : JJ Schmidt
Submitted        : 2002-12-06 17:06:54
Completed        : 2002-12-06 21:06:33
Status           : FAILURE
Comment          : see Eve shift elog 6-Dec

Last processing stage reported : combining ROOT files
Failure diagnostics :
Failed to combine pulse height histograms in 3 case(s):
Run 155117, software dps false.
Run 155119, software dps true.
Run 155119, software dps false.
Exiting.
</pre>
<!-- Author: D-mode script run_calib_analysis.tcl -->


<!-- Date: Sat Dec 7 01:11:30 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB0W8L3 
<li>problem n: 791 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: chill 
<li>description is: IMon pinkie due to another <a href= 'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=1020&frame=2&anchor=00:38:31'> DVDD step up</a>.  There is the associated <a href= 'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=1020&frame=2&anchor=01:01:47'> AVDD step down</a> as well.  Increased upper limit on DVDD from 180 to 190 mA. 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B0W8&layer=L3">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Sat Dec 7 14:48:43 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB0W8L3 
<li>problem n: 791 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: chill 
<li>description is: IMon pinkie for AVDD2 which keeps going down gradually.  Adjusted AVDD lower limit down from 760 to 720 mA. 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B0W8&layer=L3">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Sat Dec 7 14:54:17 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Sat_Dec__7_2002_145353.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1048  align='top'></td><td>e083 continues to have erratic AVDD current.</a></td></tr></table>
<!-- Author: chill -->

<!-- Date: Sat Dec 7 18:15:59 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB0W8L3 
<li>problem n: 791 
<li>Status: needs_observation
<li>Action: IMON_limits
<li>entered by: chill 
<li>description is: AVDD finally stabilized at 690 mA, after a drop of 80 mA consistent with the total loss of analog power to a chip.  The 2nd z-side chip has low-occupancy in SVXMon, so that is the place to start further investigation.  Re-defined lower limit to 680 mA. 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B0W8&layer=L3">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Sat Dec 7 18:17:18 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Sat_Dec__7_2002_181711.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1051  align='top'></td><td>AVDD for e083 after plateau.  Lost ~80mA = 1 chip.</a></td></tr></table>
<!-- Author: chill -->

<!-- Date: Sun Dec 8 02:44:40 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB5W3L1 
<li>problem n: 750 
<li>Status: needs_maintenance
<li>Action: Incident
<li>entered by: chill 
<li>description is: AVDD OC trip during data taking, which is not too suprising since this ladder has a jumper failure. AVDD limit should be reviewed and increased if necessary. 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B5W3&layer=L1">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Sun Dec 8 03:44:48 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB5W4L2 
<li>problem n: 812 
<li>Status: fixed
<li>Action: IMON_limits
<li>entered by: chill 
<li>description is: Now drawing ~10 uA.  Changed IMON limits back to where they were before adjustment above (0.2,76.0). 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B5W4&layer=L2">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Sun Dec 8 09:35:22 2002 -->
<p><font size=+1> D-mode Calibration Job Started </font>
<p><pre>
Job id            : 215
Calibration type  : standard
Run period tag    : Dec_2002
DPS-off run       : 155119
DPS-on run        : 155117
Requested by      : Jason Nielsen
Main process id   : 9608843
</pre>
<!-- Author: CDF silicon D-mode calibration job server v1.3 -->



<!-- Date: Sun Dec 8 14:30:06 2002 -->
Had to remove SB1W4 because it was having stuck cells, <a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=1024&frame=2&anchor=14:16:49'> 
DVDD current spikes, </a> and high z-side occupancy.  This did <B>NOT</B> result in AutoHRR because as this was a known wedgewide problem it was masked in SVXMon. See  
<a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=1024&frame=2&anchor=14:23:52'> 
shift e-log.</a> Had to remove wedge for safety reasons.  
<!-- Author: chill -->

<!-- Date: Sun Dec 8 14:34:14 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB1W4All 
<li>problem n: 594 
<li>Status: needs_access_2hr
<li>Action: Removed_hdwdb
<li>entered by: chill 
<li>description is: Removed since silicon is not protected by AutoHRR when this wedge gets stuck cell ids beacuse it is masked in SVXMon. 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B1W4&layer=All">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Sun Dec 8 14:38:20 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Sun_Dec__8_2002_143802.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1053  align='top'></td><td>SVT coverage after removal of SB1W4.  Too many holes and/or inefficient wedges, some which are clearly due to non-optimal SVT patterns, such as the hole in SB2W5 which is a result of SVT using L4 when we have it OFF.  Paged SVT, Marco and I will meet tomorrow to see what we can improve.</a></td></tr></table>
<!-- Author: chill -->

<!-- Date: Sun Dec 8 14:48:45 2002 -->
<p><font size=+1> D-mode Calibration Job Finished </font>
<p><pre>
This is a computer-generated silicon D-mode calibration status report.
Silicon D-mode calibration job 215 FAILED.

Job info
--------
Calibration type : standard
DPS-off run      : 155119
DPS-on run       : 155117
Requested by     : Jason Nielsen
Submitted        : 2002-12-08 07:30:57
Completed        : 2002-12-08 12:43:49
Status           : FAILURE

Last processing stage reported : comparing to the reference calibration
Failure diagnostics :
The calibration failed the following reference comparison criteria:

            Cut Name    Sensor Set   Cut Value   Data Value
--------------------    ----------   ---------   ----------
 dps_off_ped abs max    SVX_PHI      0.5         0.956097  
  dps_on_ped abs max    SVX_PHI      0.2         0.320829  
    bad_chan rel max    SVX_Z        0.25        0.391865  
bad_fraction abs max    SVX_PHI      0.02        0.021084  

Reference calibration runs are 151443 (DPS off) and 151441 (DPS on)
</pre>
<!-- Author: D-mode script run_calib_analysis.tcl -->



<!-- Date: Sun Dec 8 17:55:05 2002 -->
<h1>Are they Shelling us?</h1> 
There are some rather high dose readings lately, 
on <a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=1021&frame=2&anchor=12:09:23'>Saturday Dec 7</a> and  <a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=1024&frame=2&anchor=10:12:06'>Sunday Dec 8</a>.  <b>These are  
quite huge</b>, rivaling what we see in a big quench, but there is no other logbook entry noting anything anomolous.  Now, maybe I 
don't understand something, but this smells kinda bad. 
  
<!-- Author: SCN -->
<!-- Comment: Sun Dec  8 20;48;01 comment by...Andy H. -->
Several hundred rad of dose per store is par for the course at these luminosities.

<!-- Comment: Mon Dec  9 07;56;52 comment by...SCN -->
OK, I guess these measurements were just made at a different
time than nominal.  Searching the CDF e-log for "W Inner BLM" 
shows these as distictly different from most measurements.  Glad
to hear it is expected.

<!-- Comment: Mon Dec  9 09;23;45 comment by...Gino -->
<pre>The SVRAD integrates only when the rate is above 2 mrad/sec (8 for 2 of them) so lately we had something like 4 mrad/sec that is 14 rads per hour. 10 hours store -&gt; 140 rads. Not so far from what we see.

</pre>
<!-- Date: Mon Dec 9 08:43:34 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB1W10L4 
<li>problem n: 603 
<li>Status: needs_observation
<li>Action: Monitoring
<li>entered by: bolla 
<li>description is: <pre>First Chip shows up as 8f (should be 8d) and It always readout all channels. 
All other chips have wrong capID according to DEM.
This appeared at run ir025de5 (155109 12/06/02) the previous 
run ir025c5a (154714 11/28/02) had only the problem with 
chipID 88.
Is it possible that we introduce some trouble in access?</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B1W10&layer=L4">report</a></ul>
<!-- Author: Problem DB -->




<!-- Date: Mon Dec 9 11:25:01 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Dec__9_2002_112426.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1061  align='top'></td><td>AVDD current for e231 on Mar 30, 2002.</a></td></tr></table>
<!-- Author: David -->
<!-- Comment: Mon Dec  9 16;01;19 comment by...David -->
Bad file; <a href=
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=133&frame=2&anchor=15:45:09'>
see below</a>.
<!-- Date: Mon Dec 9 12:44:02 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: IB2W0L4 
<li>problem n: 809 
<li>Status: needs_observation
<li>Action: Swap_RX
<li>entered by: sforrest 
<li>description is: We (chris, cigdem & stan) swapped Rx.<table border=1>
<tr><td><b>IN:</b></td><td><a href="http://nkek15.fnal.gov/cgi-bin/rxdb/DBreport.pl?serial=0792">0792</a></td></tr>
<tr><td><b>OUT:</b></td><td><a href="http://nkek15.fnal.gov/cgi-bin/rxdb/DBreport.pl?serial=0769">0769</a></td></tr></table> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=ISL&wedge=B2W0&layer=L4">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Mon Dec 9 15:01:13 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB2W9L4 
<li>problem n: 813 
<li>Status: needs_work
<li>Action: Incident
<li>entered by: bachacou 
<li>description is: 100% stuck cellid in chip 88 since run 155141. 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B2W9&layer=L4">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Mon Dec 9 15:45:09 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Dec__9_2002_154446.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1067  align='top'></td><td>e231 AVDD current drop for Mar 30, 2002 (day 453).  </a></td></tr></table>
<!-- Author: David -->
<!-- Comment: Mon Dec  9 15;56;53 comment by...David -->
<P><B>AVDD2 Investigation </B>done 12-5-02
<OL>

<LI>AVDD Current Drop: The above current plot shows a drop of ~200mA on Mar 30th. 
This would be consistent with an <80mA drop due to damage of chip A2 plus
a drop of <160mA from chips (A0 and A1) downstream of initialization.</LI> 

<LI>Initialization History: The Initialization Summary tool shows a drastic increase 
in init. failures after Mar. 30th.</LI> 

<LI>Today's Run: Doesn't Initialize; reads back 0's. Last Pulse Histogram shows 
chip A2 is damaged and chips A0 & A1 are turned off as expected from above AVDD
current plot.</LI>

<LI>BE of Chip: Back end of chip A2 responds as expected when ramp pedestal is 
changed.</LI>

<LI>FE of Chip: Front end of chip A2 does not respond - the AVDD current does not 
change - when ISEL bits are all set to 0.</LI>

</OL>
<B>Conclusion</B><P>

All 5 symptoms are consistent with AVDD2 bond breaks.<P> 





<!-- Date: Mon Dec 9 16:20:17 2002 -->
<center><a href='/elog/notebooks/silicon/Mon_Dec__9_2002_161527.ps'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1069' ></a><a href='/elog/notebooks/silicon/Mon_Dec__9_2002_161755.ps'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1071' ></a></center>
<!-- Author: David -->
<!-- Comment: Mon Dec  9 16;31;04 comment by...David -->
<P><B>AVDD2 Investigation of e062</B> done 12-5-02
<OL>

<LI>AVDD Current Drop: The 1st plot shows uncommonly irratic current. The 2nd current plot shows a drop of ~100mA on Jan 16, 2002 (day 381). 
This would be consistent with an ~20mA drop due to damage of chip A1 plus
a drop of 80mA from chip A0 downstream of initialization.</LI> 

<LI>Initialization History: The Initialization Summary tool shows a drastic increase 
in init. failures after Jan. 16th.</LI> 

<LI>Today's Run: Doesn't Initialize; reads back 0's. Last Pulse Histogram shows 
chip A1 is damaged and chip A0 is turned off as expected from above AVDD
current plot.</LI>

<LI>BE of Chip: Back end of chip A1 responds as expected when ramp pedestal is 
changed.</LI>

<LI>FE of Chip: Front end of chip A1 does not respond - the AVDD current does not 
change - when ISEL bits are all set to 0.</LI>

</OL>
<B>Conclusion</B><P>

All 5 symptoms are consistent with AVDD2 bond breaks.<P> 




<!-- Comment: Tue Dec 10 11;42;25 comment by...David -->
<br>According to the Initialization Summary, from 11/6-11/17, there were no init. failures. This coincides with the step up in current at that time. Since then, the current has dropped back to near where it was and init failures have returned. Did the AVDD2 problem go away for awhile?<br>
<!-- Date: Mon Dec 9 16:34:16 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Dec__9_2002_163252.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1073  align='top'></td><td>e072 AVDD current on Mar. 30th, 2002.</a></td></tr></table>
<!-- Author: David -->
<!-- Comment: Mon Dec  9 16;44;53 comment by...David -->
<P><B>AVDD2 Investigation of e072</B> done 12-5-02
<OL>

<LI>AVDD Current Drop: The above current plot shows a drop of ~360mA on Mar 30th. 
This would be consistent with ~20mA drop due to damage of chip 88,87,86, or 85 plus
a drop of 340mA from chips downstream of initialization.</LI> 

<LI>Initialization History: The Initialization Summary tool shows a drastic increase 
in init. failures after Mar. 30th.</LI> 

<LI>Today's Run: Doesn't Initialize; reads back 0's. Last Pulse Histogram shows 
chip 87 is damaged and chips A0 to 86 are turned off as expected from above AVDD
current plot.</LI>

<LI>BE of Chip: Back end of chip 87 responds as expected when ramp pedestal is 
changed.</LI>

<LI>FE of Chip: Front end of chip 87 does not respond - the AVDD current does not 
change - when ISEL bits are all set to 0.</LI>

</OL>
<B>Conclusion</B><P>

All 5 symptoms are consistent with AVDD2 bond breaks.<P> 




<!-- Date: Mon Dec 9 16:47:26 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Dec__9_2002_164623.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1075  align='top'></td><td>e5b0 AVDD current for Mar. 30, 2002</a></td></tr></table>
<!-- Author: David -->
<!-- Comment: Mon Dec  9 17;01;47 comment by...David -->
<P><B>AVDD2 Investigation of e5b0</B> done 12-5-02
<OL>

<LI>AVDD Current Drop: The above current plot shows a drop of ~140mA on Mar 30th (not shown is the continuing current at ~220mA). 
This would be consistent with a <80mA drop due to damage of chip A1 plus
a drop of <80mA from chips A0 downstream of initialization.</LI> 

<LI>Initialization History: The Initialization Summary tool shows a drastic increase 
in init. failures after Mar. 30th.</LI> 

<LI>Today's Run: Doesn't Initialize; reads back 0's. Last Pulse Histogram shows 
chip A1 is damaged and chip A0 is turned off as expected from above AVDD
current plot.</LI>

<LI>BE of Chip: Back end of chip A1 responds as expected when ramp pedestal is 
changed.</LI>

<LI>FE of Chip: Front end of chip A1 does not respond - the AVDD current does not 
change - when ISEL bits are all set to 0.</LI>

</OL>
<B>Conclusion</B><P>

All 5 symptoms are consistent with AVDD2 bond breaks.<P> 


<!-- Date: Mon Dec 9 16:58:07 2002 -->
<H3>Recalculated chip thresholds for "wing chips"</H3> 
The thresholds in this list should give 0.66% sparse occupancy (approx. 2% NN occupancy) for the last chip on each layer 7 z-side half-ladder.  The chip numbers for such chips are always 11 or 15. 
<PRE> 
Detector E 7 0 -A Z (IB4W0L0C15) has threshold 13.0 
Detector E 7 0 -B Z (IB5W0L0C15) has threshold 12.0 
Detector E 7 1 -A Z (IB4W0L2C11) has threshold 10.0 
Detector E 7 1 -B Z (IB5W0L2C11) has threshold 10.0 
Detector E 7 2 -A Z (IB4W0L2C15) has threshold 10.0 
Detector E 7 2 -B Z (IB5W0L2C15) has threshold 14.0 
Detector E 7 3 -A Z (IB4W0L4C11) has threshold 10.0 
Detector E 7 3 -B Z (IB5W0L4C11) has threshold 9.0 
Detector E 7 4 -A Z (IB4W0L4C15) has threshold 10.0 
Detector E 7 4 -B Z (IB5W0L4C15) has threshold 20.0 
Detector E 7 5 -A Z (IB4W1L0C11) has threshold 12.0 
Detector E 7 6 -A Z (IB4W1L0C15) has threshold 14.0 
Detector E 7 7 -A Z (IB4W1L2C11) has threshold 12.0 
Detector E 7 7 -B Z (IB5W1L2C11) has threshold 8.0 
Detector E 7 8 -A Z (IB4W1L2C15) has threshold 13.0 
Detector E 7 8 -B Z (IB5W1L2C15) has threshold 11.0 
Detector E 7 9 -A Z (IB4W1L4C11) has threshold 9.0 
Detector E 7 9 -B Z (IB5W1L4C11) has threshold 8.0 
Detector E 7 10 -A Z (IB4W1L4C15) has threshold 12.0 
Detector E 7 10 -B Z (IB5W1L4C15) has threshold 10.0 
Detector E 7 11 -A Z (IB4W2L0C11) has threshold 9.0 
Detector E 7 11 -B Z (IB5W2L0C11) has threshold 9.0 
Detector E 7 12 -A Z (IB4W2L0C15) has threshold 9.0 
Detector E 7 12 -B Z (IB5W2L0C15) has threshold 12.0 
Detector E 7 13 -A Z (IB4W2L2C11) has threshold 10.0 
Detector E 7 13 -B Z (IB5W2L2C11) has threshold 8.0 
Detector E 7 14 -A Z (IB4W2L2C15) has threshold 8.0 
Detector E 7 14 -B Z (IB5W2L2C15) has threshold 17.0 
Detector E 7 15 -A Z (IB4W2L4C11) has threshold 8.0 
Detector E 7 15 -B Z (IB5W2L4C11) has threshold 8.0 
Detector E 7 16 -A Z (IB4W2L4C15) has threshold 17.0 
Detector E 7 16 -B Z (IB5W2L4C15) has threshold 10.0 
Detector E 7 17 -A Z (IB4W3L0C11) has threshold 8.0 
Detector E 7 18 -A Z (IB4W3L0C15) has threshold 17.0 
Detector E 7 19 -A Z (IB4W3L2C11) has threshold 9.0 
Detector E 7 20 -A Z (IB4W3L2C15) has threshold 14.0 
Detector E 7 21 -A Z (IB4W3L4C11) has threshold 12.0 
Detector E 7 21 -B Z (IB5W3L4C11) has threshold 7.0 
Detector E 7 22 -A Z (IB4W3L4C15) has threshold 11.0 
Detector E 7 22 -B Z (IB5W3L4C15) has threshold 12.0 
Detector E 7 23 -A Z (IB4W4L0C11) has threshold 8.0 
Detector E 7 24 -A Z (IB4W4L0C15) has threshold 12.0 
Detector E 7 25 -A Z (IB4W4L2C11) has threshold 8.0 
Detector E 7 25 -B Z (IB5W4L2C11) has threshold 8.0 
Detector E 7 26 -A Z (IB4W4L2C15) has threshold 11.0 
Detector E 7 26 -B Z (IB5W4L2C15) has threshold 12.0 
Detector E 7 27 -A Z (IB4W4L4C11) has threshold 8.0 
Detector E 7 27 -B Z (IB5W4L4C11) has threshold 8.0 
Detector E 7 28 -A Z (IB4W4L4C15) has threshold 11.0 
Detector E 7 28 -B Z (IB5W4L4C15) has threshold 12.0 
Detector E 7 29 -A Z (IB4W5L0C11) has threshold 8.0 
Detector E 7 29 -B Z (IB5W5L0C11) has threshold 8.0 
Detector E 7 30 -A Z (IB4W5L0C15) has threshold 8.0 
Detector E 7 30 -B Z (IB5W5L0C15) has threshold 9.0 
Detector E 7 31 -A Z (IB4W5L2C11) has threshold 10.0 
Detector E 7 31 -B Z (IB5W5L2C11) has threshold 8.0 
Detector E 7 32 -A Z (IB4W5L2C15) has threshold 19.0 
Detector E 7 32 -B Z (IB5W5L2C15) has threshold 9.0 
Detector E 7 33 -A Z (IB4W5L4C11) has threshold 12.0 
Detector E 7 33 -B Z (IB5W5L4C11) has threshold 7.0 
Detector E 7 34 -A Z (IB4W5L4C15) has threshold 20.0 
Detector E 7 34 -B Z (IB5W5L4C15) has threshold 19.0 
Detector E 7 35 -A Z (IB4W0L0C11) has threshold 7.0 
Detector E 7 35 -B Z (IB5W0L0C11) has threshold 29.0 
Detector W 7 0 -A Z (IB0W0L0C11) has threshold 13.0 
Detector W 7 0 -B Z (IB1W0L0C15) has threshold 23.0 
Detector W 7 1 -A Z (IB0W0L2C15) has threshold 7.0 
Detector W 7 1 -B Z (IB1W0L2C11) has threshold 11.0 
Detector W 7 2 -A Z (IB0W0L2C11) has threshold 11.0 
Detector W 7 2 -B Z (IB1W0L2C15) has threshold 14.0 
Detector W 7 3 -A Z (IB0W0L4C15) has threshold 10.0 
Detector W 7 3 -B Z (IB1W0L4C11) has threshold 15.0 
Detector W 7 4 -A Z (IB0W0L4C11) has threshold 13.0 
Detector W 7 4 -B Z (IB1W0L4C15) has threshold 18.0 
Detector W 7 5 -A Z (IB0W1L0C15) has threshold 8.0 
Detector W 7 5 -B Z (IB1W1L0C11) has threshold 12.0 
Detector W 7 6 -A Z (IB0W1L0C11) has threshold 12.0 
Detector W 7 6 -B Z (IB1W1L0C15) has threshold 8.0 
Detector W 7 7 -A Z (IB0W1L2C15) has threshold 8.0 
Detector W 7 7 -B Z (IB1W1L2C11) has threshold 11.0 
Detector W 7 8 -A Z (IB0W1L2C11) has threshold 12.0 
Detector W 7 8 -B Z (IB1W1L2C15) has threshold 16.0 
Detector W 7 9 -A Z (IB0W1L4C15) has threshold 9.0 
Detector W 7 10 -A Z (IB0W1L4C11) has threshold 8.0 
Detector W 7 11 -A Z (IB0W2L0C15) has threshold 8.0 
Detector W 7 11 -B Z (IB1W2L0C11) has threshold 10.0 
Detector W 7 12 -A Z (IB0W2L0C11) has threshold 12.0 
Detector W 7 12 -B Z (IB1W2L0C15) has threshold 12.0 
Detector W 7 13 -A Z (IB0W2L2C15) has threshold 8.0 
Detector W 7 13 -B Z (IB1W2L2C11) has threshold 8.0 
Detector W 7 14 -A Z (IB0W2L2C11) has threshold 11.0 
Detector W 7 14 -B Z (IB1W2L2C15) has threshold 19.0 
Detector W 7 17 -A Z (IB0W3L0C15) has threshold 9.0 
Detector W 7 17 -B Z (IB1W3L0C11) has threshold 8.0 
Detector W 7 18 -A Z (IB0W3L0C11) has threshold 8.0 
Detector W 7 18 -B Z (IB1W3L0C15) has threshold 13.0 
Detector W 7 19 -A Z (IB0W3L2C15) has threshold 6.0 
Detector W 7 19 -B Z (IB1W3L2C11) has threshold 9.0 
Detector W 7 20 -A Z (IB0W3L2C11) has threshold 13.0 
Detector W 7 20 -B Z (IB1W3L2C15) has threshold 19.0 
Detector W 7 21 -A Z (IB0W3L4C15) has threshold 11.0 
Detector W 7 21 -B Z (IB1W3L4C11) has threshold 8.0 
Detector W 7 22 -A Z (IB0W3L4C11) has threshold 12.0 
Detector W 7 22 -B Z (IB1W3L4C15) has threshold 14.0 
Detector W 7 23 -A Z (IB0W4L0C15) has threshold 1.0 
Detector W 7 23 -B Z (IB1W4L0C11) has threshold 9.0 
Detector W 7 24 -A Z (IB0W4L0C11) has threshold 15.0 
Detector W 7 24 -B Z (IB1W4L0C15) has threshold 13.0 
Detector W 7 25 -A Z (IB0W4L2C15) has threshold 8.0 
Detector W 7 25 -B Z (IB1W4L2C11) has threshold 8.0 
Detector W 7 26 -A Z (IB0W4L2C11) has threshold 16.0 
Detector W 7 26 -B Z (IB1W4L2C15) has threshold 17.0 
Detector W 7 27 -A Z (IB0W4L4C15) has threshold 9.0 
Detector W 7 27 -B Z (IB1W4L4C11) has threshold 7.0 
Detector W 7 28 -A Z (IB0W4L4C11) has threshold 13.0 
Detector W 7 28 -B Z (IB1W4L4C15) has threshold 12.0 
Detector W 7 29 -A Z (IB0W5L0C15) has threshold 7.0 
Detector W 7 29 -B Z (IB1W5L0C11) has threshold 8.0 
Detector W 7 30 -A Z (IB0W5L0C11) has threshold 15.0 
Detector W 7 30 -B Z (IB1W5L0C15) has threshold 14.0 
Detector W 7 31 -A Z (IB0W5L2C15) has threshold 7.0 
Detector W 7 31 -B Z (IB1W5L2C11) has threshold 9.0 
Detector W 7 32 -A Z (IB0W5L2C11) has threshold 11.0 
Detector W 7 32 -B Z (IB1W5L2C15) has threshold 8.0 
Detector W 7 33 -A Z (IB0W5L4C15) has threshold 8.0 
Detector W 7 33 -B Z (IB1W5L4C11) has threshold 8.0 
Detector W 7 34 -A Z (IB0W5L4C11) has threshold 16.0 
Detector W 7 34 -B Z (IB1W5L4C15) has threshold 13.0 
Detector W 7 35 -A Z (IB0W0L0C15) has threshold 7.0 
Detector W 7 35 -B Z (IB1W0L0C11) has threshold 15.0 
</PRE> 
Chips which were not calibratable in the most recent calibration are not included in this list.
<!-- Author: Jason -->
<!-- Comment: Mon Dec  9 21;55;32 comment by...Jason -->
I have just finished implementing these changes in the hardware database.  The Resistor Driver setting was changed to 1 for all half-ladders except the ones in the list above.<BR>
If there are any new problems with half-ladders, maybe one should first try to change the Rdriver setting back to 7 (the maximum) and see if the problem persists.
<!-- Comment: Mon Dec  9 22;25;59 comment by...Jason -->
Sorry, this comment is on the wrong entry.  I didn't change the thresholds for ISL.  I changed the resistor drivers for SVX.
<!-- Date: Mon Dec 9 17:06:15 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Dec__9_2002_170559.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1077  align='top'></td><td>e242 AVDD current for 11/9/02.</a></td></tr></table>
<!-- Author: David -->
<!-- Comment: Mon Dec  9 17;11;18 comment by...David -->
<P><B>AVDD2 Investigation of e242</B> done 12-5-02
<OL>

<LI>AVDD Current Drop: The above current plot shows a drop of ~300mA on Nov 9, 2002. 
This would be consistent with an ~80mA drop due to damage of chip A4 plus
a drop of ~220mA from chips A0 to A3 downstream of initialization.</LI> 

<LI>Initialization History: The Initialization Summary tool shows a drastic increase 
in init. failures after Nov 9th.</LI> 

<LI>Today's Run: Doesn't Initialize; reads back 0's. Last Pulse Histogram shows 
chip A4 is damaged and chips A0 to A3 are turned off as expected from above AVDD
current plot.</LI>

<LI>BE of Chip: Back end of chip A4 responds as expected when ramp pedestal is 
changed.</LI>

<LI>FE of Chip: Front end of chip A4 does not respond - the AVDD current does not 
change - when ISEL bits are all set to 0.</LI>

</OL>
<B>Conclusion</B><P>

All 5 symptoms are consistent with AVDD2 bond breaks.<P> 



<!-- Date: Mon Dec 9 19:43:51 2002 -->
<pre>ACCESS REPORT. 
installed super-duper FIBs 
		PREP 	SERIAL 
SB5W4/5	OUT	560604	116 
SB5W4/5	IN	550968	152 
SB0W6/7	OUT	560617	132 
SB0W6/7	IN	550954	153 
 
WE DID NOT INTRODUCE ANY TROUBLE  
BUT WE DID NOT SOLVE ANY PROBLEM  
IF NOT THAT SB0W6L4 WAS GIVING NO  
DATA AT ALL AND NOW GIVES A LOT  
OF GARBLED DATA. 
 
 
 
 
</pre>
<!-- Author: Gino and Stan -->

<!-- Date: Mon Dec 9 19:49:53 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB0W6/7All 
<li>problem n: 814 
<li>Status: needs_observation
<li>Action: Swap_FIB
<li>entered by: bolla 
<li>description is: Swapped Fib. </pre><table border=1> <tr><td><b>IN</b></td><td>PREP:</td><td>550954</td><td>Serial:</td><td>153</td></tr> <tr><td><b>OUT</b></td><td>PREP:</td><td>560617</td><td>Serial:</td><td>132</td></tr></table> <table border=1>
<tr><td><b>IN</b></td><td>PREP:</td><td>550954</td><td>Serial:</td><td>153</td></tr>
<tr><td><b>OUT</b></td><td>PREP:</td><td>560617</td><td>Serial:</td><td>132</td></tr></table> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B0W6/7&layer=All">report</a></ul>
<!-- Author: Problem DB -->
<!-- Comment: Mon Dec  9 19;53;02 comment by...Gino -->
<pre>NOW there is a super-duper FIB</pre>
<!-- Date: Mon Dec 9 19:51:58 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB5W4/5All 
<li>problem n: 653 
<li>Status: needs_observation
<li>Action: Swap_FIB
<li>entered by: bolla 
<li>description is: SWAPPED FIB WITH SUPER-DUPER FIB<table border=1>
<tr><td><b>IN</b></td><td>PREP:</td><td>550968</td><td>Serial:</td><td>152</td></tr>
<tr><td><b>OUT</b></td><td>PREP:</td><td>560604</td><td>Serial:</td><td>116</td></tr></table> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B5W4/5&layer=All">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Mon Dec 9 19:57:16 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB0W6L4 
<li>problem n: 620 
<li>Status: needs_observation
<li>Action: Diagnosis_update
<li>entered by: bolla 
<li>description is: <a href= 'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=133&frame=2&anchor=19:43:51'> Installed SUPER-DUPER FIB </a> need observations. 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B0W6&layer=L4">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Mon Dec 9 19:58:11 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB5W5L2 
<li>problem n: 702 
<li>Status: needs_observation
<li>Action: Diagnosis_update
<li>entered by: bolla 
<li>description is: <a href= 'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=133&frame=2&anchor=19:43:51'> Installed SUPER-DUPER FIB </a> need observation 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B5W5&layer=L2">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Mon Dec 9 20:08:23 2002 -->
<p><font size=+1> D-mode Calibration Job Started </font>
<p><pre>
Job id            : 216
Calibration type  : standard
Run period tag    : Dec_2002
DPS-off run       : 155194
DPS-on run        : 155193
Requested by      : Jason Nielsen
Main process id   : 13537211
</pre>
<!-- Author: CDF silicon D-mode calibration job server v1.3 -->




<!-- Date: Mon Dec 9 22:21:03 2002 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1078&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1078  width='300' align='top'></td><td>This SVXMon map is from the cosmics run immediately following my resistor driver changes.</a></td></tr></table>
<!-- Author: Jason -->
<!-- Comment: Mon Dec  9 22;57;14 comment by...Jason -->
<pre>ISL shows a large number of errors, too, but I did not touch the settings there.  From the SVXMon error logger, I can tell that most of the errors (in SVX as well as ISL) are occupancy-related.
Every single wedge in ISL and SVX has a sad face.
&lt;BR&gt;
Then again, the errors for the previous run 155195 (before I finished the changes) are the same as for this run 155196.</pre>

<!-- Comment: Mon Dec  9 23;18;56 comment by...Jason -->
I am doing a little test for run 155197.  I blew away my rdriver settings <B>for Layer 0 only</B> and changed all of them back to 4.  Will this help make SVXMon super-green and make the sad faces go away? ... NO, it does not.  There are exactly the same errors as for the previous run 155196.
<BR>
Bottom line is that I can't tell from this cosmic run whether the rdriver changes have introduced problems or not.  I think we could check the readout with svxdaq Tuesday and find out what needs to be fine-tuned.

<!-- Comment: Tue Dec 10 09;53;34 comment by...Gino -->
<table border=0><td><tr><td bgcolor=#e0e030><pre>The Rdriver is a parameter that affects only the digital part of 
the chip. SO the expected problems that might be introduced by 
changing them are either NO DATA or BIT TROUBLE. This problems 
will show up in the CELL ID STATUS MAP.
The CHIP STATUS maps include analog parameters like occupancy, 
mean-charge and RMS-charge that are not affected by the RDRIVER 
so SVXMON can give you the feedback you need.</pre></td></tr></td></table>
<!-- Comment: Tue Dec 10 11;26;10 comment by...Andy H. -->
It's been <a href=
'http://www-cdfonline.fnal.gov/cgi/elog/elog.pl?nb=2002&action=view&page=824&frame=2&anchor=20:07:22'>my experience</a> that you
get lots of SVXMon redness during cosmics, which I always
rationalized away by figuring that cosmics don't give you a high
enough occupancy.

<!-- Date: Tue Dec 10 01:20:59 2002 -->
<p><font size=+1> D-mode Calibration Job Finished </font>
<p><pre>
This is a computer-generated silicon D-mode calibration status report.
Silicon D-mode calibration job 216 FAILED.

Job info
--------
Calibration type : standard
DPS-off run      : 155194
DPS-on run       : 155193
Requested by     : Jason Nielsen
Submitted        : 2002-12-09 18:05:07
Completed        : 2002-12-09 23:17:02
Status           : FAILURE

Last processing stage reported : comparing to the reference calibration
Failure diagnostics :
The calibration failed the following reference comparison criteria:

            Cut Name    Sensor Set   Cut Value   Data Value
--------------------    ----------   ---------   ----------
 dps_off_ped abs max    SVX_PHI      0.5         0.595496  
  dps_on_ped abs max    SVX_PHI      0.2         0.208281  
    bad_chan rel max    SVX_Z        0.25        0.359904  
bad_fraction abs max    SVX_PHI      0.02        0.022559  

Reference calibration runs are 150096 (DPS off) and 150097 (DPS on)
</pre>
<!-- Author: D-mode script run_calib_analysis.tcl -->






<!-- Date: Tue Dec 10 12:00:13 2002 -->
<center><a href='/elog/notebooks/silicon/Tue_Dec_10_2002_115720.ps'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1082' ></a><a href='/elog/notebooks/silicon/Tue_Dec_10_2002_115903.ps'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1084' ></a></center>
<!-- Author: David -->
<!-- Comment: Tue Dec 10 12;33;03 comment by...David -->
<P><B>AVDD2 Investigation of e012</B> done 12-6-02
<OL>

<LI>AVDD Current Drop: First plot shows uncommonly erratic currents. The second current plot shows a drop of ~170mA on Jan 16th (day 381). 
This would be consistent with an <80mA drop due to damage of chip A4, A3, or A2 plus
a drop of <80mA/chip from chips downstream of initialization.</LI> 

<LI>Initialization History: The Initialization Summary tool shows a drastic increase 
in init. failures after Jan 16th.</LI> 

<LI>Today's Run: Doesn't Initialize; reads back 0's. Last Pulse Histogram shows 
chip A4 is damaged and chips A0-A3 are turned off as expected from above AVDD
current plot.</LI>

<LI>BE of Chip: Back end of chip A4 responds as expected when ramp pedestal is 
changed.</LI>

<LI>FE of Chip: Front end of chip A4 does not respond - the AVDD current does not 
change - when ISEL bits are all set to 0.</LI>

</OL>
<B>Conclusion</B><P>

All 5 symptoms are consistent with AVDD2 bond breaks.<P> 




<!-- Date: Tue Dec 10 12:38:33 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Tue_Dec_10_2002_123752.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1086  align='top'></td><td>e013 AVDD current on 11/9/02 (day 677).</a></td></tr></table>
<!-- Author: David -->
<!-- Comment: Tue Dec 10 12;51;34 comment by...David -->
<P><B>AVDD2 Investigation of e013</B> done 12-6-02
<OL>

<LI>AVDD Current Drop: The above current plot shows a drop of ~20mA on Nov. 9th. 
This would be consistent with an <80mA drop due to damage of chip A0.</LI> 

<LI>Initialization History: The Initialization Summary tool shows NO init. failures from 10/28-12/6.</LI> 

<LI>Today's Run: Initializes OK. No CAP ID errors - no errors of any kind - during run. Histograms show 
chip 86 has weird noise and downstream chips are not 'dead'.</LI>

<LI>BE of Chip: Back end of chip 86 responds as expected when ramp pedestal is 
changed.</LI>

<LI>FE of Chip: Front end of chip 86 responds - the AVDD current decreases by 10mA - when ISEL bits are all set to 0.</LI>

</OL>
<B>Conclusion</B><P>

The weird noise on chip 86 is not due to a broken AVDD2 bond.<P> 




<!-- Date: Tue Dec 10 15:11:33 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Tue_Dec_10_2002_151003.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1088  align='top'></td><td>e033 AVDD current.</a></td></tr></table>
<!-- Author: David -->
<!-- Comment: Tue Dec 10 16;09;28 comment by...David -->
<P><B>AVDD2 Investigation of e033</B> done 12-5-02
<OL>

<LI>AVDD Current Drop: Erratic current. On 9/4 (day 611) the current increased from ~830mA to ~1050mA. Then on 9/12 the current dropped to ~925mA. This is not consistent with AVDD2 bond breaks.
</LI> 

<LI>Initialization History: The Initialization Summary tool shows essentially no init failures except for the period of 10/3 to 10/22.</LI> 

<LI>Today's Run: Init. OK. A few errors during run. Last Pulse Histogram shows 
chip A4 is damaged and chips A0 to A3 are "on" but affected.</LI>

<LI>BE of Chip: Back end of chip A4 responds as expected when ramp pedestal is 
changed.</LI>

<LI>FE of Chip: Front end of chip A4 responds - the AVDD current changes by 30mA - when ISEL bits are all set to 0.</LI>

</OL>
<B>Conclusion</B><P>

e033 does not exhibit broken AVDD2 bond symptoms.<P> 


<!-- Date: Tue Dec 10 15:26:22 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB0W3L3 
<li>problem n: 511 
<li>Status: fixed
<li>Action: Swap_RX
<li>entered by: bachacou 
<li>description is: No high rate of bit error or 00f3 found in the past month. <table border=1>
<tr><td><b>IN:</b></td><td><a href="http://nkek15.fnal.gov/cgi-bin/rxdb/DBreport.pl?serial=??">??</a></td></tr>
<tr><td><b>OUT:</b></td><td><a href="http://nkek15.fnal.gov/cgi-bin/rxdb/DBreport.pl?serial=??">??</a></td></tr></table> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B0W3&layer=L3">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Tue Dec 10 15:30:44 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB0W3L3 
<li>problem n: 339 
<li>Status: fixed
<li>Action: Swap_RX
<li>entered by: bachacou 
<li>description is: No high rate of bit error or 00f3 found within the past month. Declared fixed. <table border=1>
<tr><td><b>IN:</b></td><td><a href="http://nkek15.fnal.gov/cgi-bin/rxdb/DBreport.pl?serial=??">??</a></td></tr>
<tr><td><b>OUT:</b></td><td><a href="http://nkek15.fnal.gov/cgi-bin/rxdb/DBreport.pl?serial=??">??</a></td></tr></table> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B0W3&layer=L3">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Tue Dec 10 15:33:24 2002 -->
I re-implemented the rdriver settings for Layer0.  (I had backed them out last night because of SVXMon confusion.)  
<!-- Author: Jason -->

<!-- Date: Tue Dec 10 15:51:14 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB3W8L4 
<li>problem n: 737 
<li>Status: needs_observation
<li>Action: Monitoring
<li>entered by: bachacou 
<li>description is: Between Nov 09 and Dec 09, the ladder has failed initialization 127 times (27 for 'normal' ladders).  
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B3W8&layer=L4">report</a></ul>
<!-- Author: Problem DB -->




<!-- Date: Tue Dec 10 17:01:37 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Tue_Dec_10_2002_170051.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1092  align='top'></td><td>e182 AVDD current (only nonzero values) up to Dec. 2nd, 2002</a></td></tr></table>
<!-- Author: David -->
<!-- Comment: Tue Dec 10 17;10;43 comment by...David -->
<P><B>AVDD2 Investigation of e182</B> done 12-5-02
<OL>

<LI>AVDD Current Drop: No permanent current drops seen. Erratic currents.</LI> 

<LI>Initialization History: No init. failures for range of days in above plot.</LI> 

<LI>Today's Run: Initializes OK. Lots of errors though; truncate, 00sequence, Ill Ch., Data Overrun, No EOR. No damaged chips according to histograms.</LI>

<LI>BE of Chip: No chip looks damaged so didn't perform this test.</LI>

<LI>FE of Chip: No chip looks damaged so didn't perform this test.</LI>

</OL>
<B>Conclusion</B><P>

Not consistent with AVDD2 bond breaks.<P> 



<!-- Date: Tue Dec 10 17:12:11 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB0W8L4 
<li>problem n: 73 
<li>Status: needs_observation
<li>Action: Sparse_out_chip
<li>entered by: bachacou 
<li>description is: <pre>Still 30% 00f3 and pipeline out of sync. No chip on this ladder is DPS OFF!</pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B0W8&layer=L4">report</a></ul>
<!-- Author: Problem DB -->


<!-- Date: Tue Dec 10 17:21:10 2002 -->
Entered in Silicon database: <ul>
<li>Ladder: SB0W6L3 
<li>problem n: 609 
<li>Status: needs_observation
<li>Action: Monitoring
<li>entered by: bachacou 
<li>description is: <pre>Failed init 45 times between Nov 09 and Dec 09. </pre> 
<li>See <a href="http://nkek15.fnal.gov/cgi-bin/newproblemdb/DBreport.pl?detsys=SVX&wedge=B0W6&layer=L3">report</a></ul>
<!-- Author: Problem DB -->



<!-- Date: Sat Dec 21 18:21:59 2002 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1158&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-1159  width='300' align='top'></td><td>PHI side cluster position for e013 (SB0W1L3). Chip 86 is pretty much dead even during real data taking</a></td></tr></table>
<!-- Author: Gino -->