<!-- Title: 08:16:47  Mon May 14 2001 -->
<!-- Crewchief: Paul Shepard -->
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<pre>SB0W1 or S1OUT WEST</pre>


<!-- Date: Mon May 14 08:24:22 2001 -->
<pre>This one is going to be difficult to plug as there are only two half 
rails so be careful.  Owl shift completed the checklist up to the WIB  
test (all LIB testing done).  WIB appeared to initialize based on currents, 
but the layer 0 readback was all ones.  Layer 3 and 4 were not reading  
out correctly and had chip ID errors on every event.  Layer 3 would  
not readback its initialization string correctly, but layer 4 did. 
The flashlight test indicated that layer 3 was not passing light, and 
layer 4 may be missing some fibers.   Needs to be checked further by 
the day shift.</pre>
<!-- Author: Paul Shepard -->


<!-- Date: Mon May 14 17:32:59 2001 -->
<pre>Tested with WIB: 
 
Found DOIM cables 0 and 3 were labelled incorrectly  
and were consequently swapped. I swapped them to be 
correct (did not relabel though, sorry) 
 
DOIM cable for channel 4 is bad. I left this doim 
unconnected at the COT face. 
 
Plugged it in; aside from the broken DOIM everything 
reads out fine (tested L4 via DOIM cable 3) 
and it is RTV'd.</pre>
<!-- Author: Lester & Aaron -->
<!-- Comment: Wed May 23 17;38;30 comment by...ADF -->
<pre>Inspected 5/23 No RTV in back (necessary for OUT's along
40inch web.)  Put RTV in back.</pre>

<!-- Comment: Thu May 24 14;46;58 comment by...ADF -->
<pre>DOIM 4 cable reputed to have been swapped.  Took 100 events
w/o R/O errors.</pre>


<!-- Date: Wed May 30 04:49:46 2001 -->
<pre>final pass: reads fine 
run 121 biased</pre>
<!-- Author: YG -->


<!-- Date: Fri Jun 1 13:54:21 2001 -->
<pre>RTV on -phi rail looks suspicious.  See Thu. May 31 21:10 
general silicon elog entry.</pre>
<!-- Author: ADF / SDW -->


<!-- Date: Mon Jul 2 11:04:22 2001 -->
<pre>Tested pre-integration 
OK to integrate, no error, bias ok, laser448.svx</pre>
<!-- Author: Saverio, SK -->


<!-- Date: Mon Jul 9 21:47:08 2001 -->
<pre>had to take L4 out of the run since it kept tripping on AVDD  
overcurrent...</pre>
<!-- Author: Petra -->


<!-- Date: Tue Aug 7 09:52:02 2001 -->
<a href= 
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=57&frame=2&anchor=09:23:16'> 
L2 gave problemsa but they disappeared</a>   
<!-- Author: jean, Valeria, Angela -->


<!-- Date: Mon Oct 29 20:32:58 2001 -->
<pre>Channel  2 drops readout z-side (Chip A3)</pre>
<!-- Author: Lester, Saverio, Steve -->


<!-- Date: Mon Oct 29 20:41:27 2001 -->
<table border=0><td><tr><td bgcolor=#e0e030><pre>Layer-4 AVdd OVERCURRENT</pre></td></tr></td></table>
<!-- Author: Steve,Saverio, Sinead -->


<!-- Date: Fri Nov 9 13:21:22 2001 -->
<pre>summary from the access for L4 
============================== 
Pretest OK; AVDD overcurrent 8/9/01 
(10/22 no trip seen now, ladder works fine!) 
10/22 later: trips very easily, very high AVDD4 current 
      even if it turns on, it doesn't init (doesnt read right  
      things back) or readout anything (RO empty). 
      CURRENTS after init: DVDD4=35, AVDD4=1885. 
11/01 measure resistances for DVDD4;  
      go with the cart and lower AVDD4 voltage 
11/09 DVDD and AVDD GROUND SHORTED, voltage lowered, doesn't init  
      reads back 000 plus a few numbers 
      reads out empty events, truncated with c2c2 after FIB header 
 
GIVEN UP ON IT... 
</pre>
<!-- Author: Petra -->