<!-- Title: 17:43:38  Mon Jan  8 2001 -->
<!-- Crewchief: Jaco -->
<!-- Op1: Ming -->
<!-- Op2: Dmitry -->
<!-- Op3: Alexei -->
<!-- Op4: &nbsp; -->
<!-- Op5: &nbsp; -->
<!-- Op6: &nbsp; -->
<!-- Notes: -->
<pre>After the commissioning and before March...</pre>


<!-- Date: Mon Jan 8 17:44:48 2001 -->
<pre>Ran qietest on b0clc00. All ADMEMs are fine except the 
two bad channels (0 and 48). Couldn't run calibrations  
due to RT server problem.</pre>
<!-- Author: Alexei -->


<!-- Date: Fri Jan 12 13:38:08 2001 -->
<pre>CLC Calibrations taken (not known if successful). 
File is ar019c9b.0001cali. 
</pre>
<!-- Author: alexei -->


<!-- Date: Mon Jan 29 21:13:38 2001 -->
CLC Bad Channel Debug 
--------------------- 
From the swapping data that Alexei had taken, we think 
that many of the "bad" channels (in time measurement) 
from ~ch1 to ~ch31 are due to bad T.B. We performed some 
tests to check if this is true. 
 
Action                                Run # 
------------------------------------------------------ 
Default arrangement               A20010129181359.test 
 
Remove TB #0 from slot3. 
Move TB #1 from slot4 to slot3    ar019feb.0001phys 
 
Put TB #0 back into slot3 
and TB #1 back into slot4         ar019fee.0001phys 
 
 
The data are stored in /data1/cdf_clc/eledebug  (b0dau30)
<!-- Author: Alexei & Ming -->


<!-- Date: Mon Jan 29 21:17:30 2001 -->
CLC Bad Channel Debug 
--------------------- 
From the swapping data that Alexei had taken, we think 
that many of the "bad" channels (in time measurement) 
from ~ch1 to ~ch31 are due to bad T.B. We performed some 
tests to check if this is true. 
 
Action                                Run # 
------------------------------------------------------ 
Default arrangement               A20010129181359.test 
 
Remove TB #0 from slot3. 
Move TB #1 from slot4 to slot3    ar019feb.0001phys 
 
Put TB #0 back into slot3 
and TB #1 back into slot4         ar019fee.0001phys 
 
The data are stored in /data1/cdf_clc/eledebug  (b0dau30)  
<!-- Author: Alexei & Ming -->


<!-- Date: Thu Feb 8 09:17:48 2001 -->
<pre><pre>Replacement of TB 
----------------- 
Two TBs which have bad channels were taken out and sent 
to Charlie Nelson for repair. They are replaced by two 
spares. 
 
ch #     Bad TB serial #        Replaced by TB serial # 
-------------------------------------------------------- 
0-15           0                          6 
32-47          2                          8 
 
</pre></pre>
<!-- Author: Ming -->


<!-- Date: Fri Feb 9 15:40:44 2001 -->
<pre>Test CLC Crate After Partial Recabling (Feb 08th) 
------------------------------------------------- 
 
All the signal cables are now connected to TBs. However 
the cables for TDC are not connected yet. Perform tests 
to check on the connections for amplitude measurement. 
 
1) Qietest report two channels with problems : 
 
      Admem 10, Qie 2 -> warning 8, Sigma(slope)/slope too big 
      Admem 3,  Qie 5 -> failure 14, Sigma(offset) too big 
 
Although we have a failure on one of the channel, we went ahead 
to download the new calibration constants into FRAM because we 
wanted to perform LED test to check if there is any big problem 
in the cablings. 
 
2) LED test: 
 
All channels registered non-pedestal like amplitude except 
channel 69. Not sure what is the problem .</pre>
<!-- Author: Ming and Dmitri -->


<!-- Date: Fri Feb 9 15:44:41 2001 -->
<pre>Test perform on Channel 69 
-------------------------- 
 
1) Fire LED, connect signal cable to scope. Did not 
   see any signal. 
 
2) Sent pulse from signal generator to look at the time 
   duration it takes to reflect back the signal. 
 
   Did not observe any reflection in the signal. For a good 
   channel, the time duration for reflecting the signal is 
   about 572 ns. 
 
   Maybe channel 69 has a bad connector at the end that is 
   connected to the TB. 
 
</pre>
<!-- Author: Ming -->


<!-- Date: Mon Feb 12 15:03:14 2001 -->
<pre>Found the Problem to Channel 69 
------------------------------- 
 
It is finally concluded that the problem with ch 69 is 
due to a bad contact in the connector (to the TB). Somehow 
the positive end and negative end are in contact. The resistance 
between these two ends for good channels are approx 1 Mohm, 
but for ch 69, it measures ~0 ohm. I was able to break this 
contact if I wiggled the connector. And furthermore I was able 
to observe the reflected pulse (after breaking the contact) 
when I sent a pulse down the cable, with a duration time about 
570 ns. Fred Lewis will have someone to replace the connector 
tomorrow.  
</pre>
<!-- Author: Ming -->


<!-- Date: Thu Feb 15 14:24:53 2001 -->
<pre>Ch 69 is fixed ! 
----------------- 
 
Fred had a technician fixed ch 69 by replacing with a new 
connector on Tuesday. I reconnected back all the cables and 
took a LED run just now. So now I can see that all the 
96 channels are showing amplitudes above pedestal. 
 
 
</pre>
<!-- Author: Ming -->


<!-- Date: Thu Mar 1 10:45:21 2001 -->
<pre>CLC Standalone Readout Using Global 2nd-Level Trigger 
----------------------------------------------------- 
I did several tests this morning and was able to get 
the clc readout using L-2 trigger working. The Ext. delay 
trigger in the TS has to be changed from 2 (which was the 
value used at the end of commissioning run) to 3. I think 
this might have to do with the 1 clock change that occur 
recently in the CDF trigger system. 
</pre>
<!-- Author: Ming -->


<!-- Date: Mon Mar 5 18:14:43 2001 -->
<pre>We looked into the high noise channels and found that 
many of them corresponded to TB in slot #7. We replaced 
the TB with one of the spares, and the noise went down. 
</pre>
<!-- Author: Sasha, Alexei -->


<!-- Date: Mon Mar 19 09:10:40 2001 -->
<pre>More proton beam data 
--------------------- 
 
Last Friday Alexei suggested that one can use the proton 
beam data to calibrate the relative time offset between channels 
on each single CLC module. I took some data (~70k events 
from the MB trigger w/o time gate) yesterday. The beam was at 150 
GeV. Unfortunately the beam was not coalesced and both CDF and 
Tevatron clocks were not synchronized. The main injector will 
only begin to provide coalesced beam later this week, and that 
the two clocks will only be synchronized when the beam energy is 
higher than 150 GeV. Until now Tevatron has only been operating 
at 150 GeV when there are beams in it. 
 
The data (with the ntuples) are stored in 
/data1/smwang/pbeam/mar18 in the online machines. 
</pre>
<!-- Author: Ming -->


<!-- Date: Fri Mar 23 23:10:07 2001 -->
<br><b>BSC ADMEM problems:</b> 
<br>After attempting to configure the BSC ADMEMs, the shift 
crew discovered visionREAD errors coming from the CLC crate. 
I learned that slots 16,17 were responsible for the errors 
and correspond to the ADMEMs I attepmted to configure. 
<p> 
Below are the results from attempting to map the crate 
and identify the CAFE cards for the ADMEM in slot 17. 
<pre> 
 In Slot2   IDPROM = 0105 001 TRACER__V2.1A           
 In Slot3   IDPROM = 0354 003 ADMEM_V4.0          460 
 In Slot4   IDPROM = 0350 003 ADMEM_V4.0          460 
FISION: S_errno_EIO (0x5): VME BERR received! 
 In Slot6   IDPROM = 0356 003 ADMEM_V4.0          460 
 In Slot7   IDPROM = 0358 003 ADMEM_V4.0          460 
FISION: S_errno_EIO (0x5): VME BERR received! 
 In Slot9   IDPROM = 0357 003 ADMEM_V4.0          460 
 In Slot10   IDPROM = 0352 003 ADMEM_V4.0          460 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
 In Slot16   IDPROM = 0068 003 ADMEM_V4.0          470 
 In Slot17   IDPROM = 0349 003 ADMEM_V4.0          460 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
 In Slot21   IDPROM = 0360 008 MICHIGAN TDC  ECL Rev D 
 
QIE ID table: 
QIE    ADMEM: 17      
  0         64817 
  1         64568 
  2         64547 
  3         64512 
  4         64547 
  5         65416 
  6         64547 
  7         56355 
  8         65433 
  9         64512 
 10         64512 
 11         65420 
 12         65409 
 13         65416 
 14         65468 
 15         64547 
 16         64547 
 17         64568 
 18         64547 
 19         64512 
<pre> 
Calibration yields similar garbled information. Below are information from qietest giving sample calibration data.  Note 
that we always end up with CAPID=3 and range=7.  The data 
also don't look right. 
<pre> 
iadmem 17 qie  0 np   0 ns    0 val 0x   6 raw 0xfd34 cap 3 range 7 data  308 buffer 0 
iadmem 17 qie  0 np  20 ns    0 val 0x  f6 raw 0xfd34 cap 3 range 7 data  308 buffer 0 
iadmem 17 qie  0 np  40 ns    0 val 0x 2dd raw 0xfd30 cap 3 range 7 data  304 buffer 0 
iadmem 17 qie  0 np  60 ns    0 val 0x 6a5 raw 0xfd34 cap 3 range 7 data  308 buffer 0 
iadmem 17 qie  0 np  80 ns    0 val 0x e37 raw 0xfd34 cap 3 range 7 data  308 buffer 0 
iadmem 17 qie  0 np 100 ns    0 val 0x1d5b raw 0xfd34 cap 3 range 7 data  308 buffer 0 
iadmem 17 qie  0 np 120 ns    0 val 0x3ae8 raw 0xfd30 cap 3 range 7 data  304 buffer 0 
iadmem 17 qie  0 np 140 ns    0 val 0x6879 raw 0xfd34 cap 3 range 7 data  308 buffer 0 
iadmem 17 qie  0 np 160 ns    0 val 0xeaeb raw 0xfd30 cap 3 range 7 data  304 buffer 0 
iadmem 17 qie  5 np   0 ns    0 val 0x   6 raw 0xff88 cap 3 range 7 data  904 buffer 0 
iadmem 17 qie  5 np  20 ns    0 val 0x  f6 raw 0xff88 cap 3 range 7 data  904 buffer 0 
iadmem 17 qie  5 np  40 ns    0 val 0x 2dd raw 0xff88 cap 3 range 7 data  904 buffer 0 
iadmem 17 qie  5 np  60 ns    0 val 0x 6a5 raw 0xff88 cap 3 range 7 data  904 buffer 0 
iadmem 17 qie  5 np  80 ns    0 val 0x e37 raw 0xff88 cap 3 range 7 data  904 buffer 0 
iadmem 17 qie  5 np 100 ns    0 val 0x1d5b raw 0xff88 cap 3 range 7 data  904 buffer 0 
iadmem 17 qie  5 np 120 ns    0 val 0x3ae8 raw 0xff88 cap 3 range 7 data  904 buffer 0 
iadmem 17 qie  5 np 140 ns    0 val 0x6879 raw 0xff88 cap 3 range 7 data  904 buffer 0 
iadmem 17 qie  5 np 160 ns    0 val 0xeaeb raw 0xff88 cap 3 range 7 data  904 buffer 0 
iadmem 17 qie 10 np   0 ns    0 val 0x   6 raw 0xfc00 cap 3 range 7 data    0 buffer 0 
iadmem 17 qie 10 np  20 ns    0 val 0x  f6 raw 0xfc00 cap 3 range 7 data    0 buffer 0 
iadmem 17 qie 10 np  40 ns    0 val 0x 2dd raw 0xfc00 cap 3 range 7 data    0 buffer 0 
iadmem 17 qie 10 np  60 ns    0 val 0x 6a5 raw 0xfc00 cap 3 range 7 data    0 buffer 0 
iadmem 17 qie 10 np  80 ns    0 val 0x e37 raw 0xfc00 cap 3 range 7 data    0 buffer 0 
iadmem 17 qie 10 np 100 ns    0 val 0x1d5b raw 0xfc00 cap 3 range 7 data    0 buffer 0 
iadmem 17 qie 10 np 120 ns    0 val 0x3ae8 raw 0xfc00 cap 3 range 7 data    0 buffer 0 
iadmem 17 qie 10 np 140 ns    0 val 0x6879 raw 0xfc00 cap 3 range 7 data    0 buffer 0 
iadmem 17 qie 10 np 160 ns    0 val 0xeaeb raw 0xfc00 cap 3 range 7 data    0 buffer 0 
iadmem 17 qie 15 np   0 ns    0 val 0x   6 raw 0xfc23 cap 3 range 7 data   35 buffer 0 
iadmem 17 qie 15 np  20 ns    0 val 0x  f6 raw 0xfc23 cap 3 range 7 data   35 buffer 0 
iadmem 17 qie 15 np  40 ns    0 val 0x 2dd raw 0xfc23 cap 3 range 7 data   35 buffer 0 
iadmem 17 qie 15 np  60 ns    0 val 0x 6a5 raw 0xfc23 cap 3 range 7 data   35 buffer 0 
iadmem 17 qie 15 np  80 ns    0 val 0x e37 raw 0xfc23 cap 3 range 7 data   35 buffer 0 
iadmem 17 qie 15 np 100 ns    0 val 0x1d5b raw 0xfc23 cap 3 range 7 data   35 buffer 0 
iadmem 17 qie 15 np 120 ns    0 val 0x3ae8 raw 0xfc23 cap 3 range 7 data   35 buffer 0 
iadmem 17 qie 15 np 140 ns    0 val 0x6879 raw 0xfc23 cap 3 range 7 data   35 buffer 0 
iadmem 17 qie 15 np 160 ns    0 val 0xeaeb raw 0xfc23 cap 3 range 7 data   35 buffer 0 
</pre> 
This yields the following fits for the different ranges: 
<pre> 
geo32:/slot=17   0    0    0    0      0    0.000000   0.000000        0.00      0.00 
geo32:/slot=17   0    0    0    1      0    0.000000   0.000000        0.00      0.00 
geo32:/slot=17   0    0    0    2      0    0.000000   0.000000        0.00      0.00 
geo32:/slot=17   0    0    0    3      0    0.000000   0.000000        0.00      0.00 
geo32:/slot=17   0    0    0    4      0    0.000000   0.000000        0.00      0.00 
geo32:/slot=17   0    0    0    5      0    0.000000   0.000000        0.00      0.00 
geo32:/slot=17   0    0    0    6      0    0.000000   0.000000        0.00      0.00 
geo32:/slot=17   0    0    0    7      0    0.000000   0.000000        0.00      0.00 
</pre> 
If I had to guess, I would say that the CAFE FRAMs were completely erased and overwritten. 
<p> 
Replacing the ADMEM appears to fix the problem.
<!-- Author: R.J. Tesarek -->


<!-- Date: Fri Mar 23 23:49:25 2001 -->
<br><b>BSC ADMEMs:</b> 
<br>Removed all the CAFE cards from the CLC style ADMEM and 
places a single, new CAFE card into channel 0.  Was unable to 
read the ID of this CAFE card.  Problem is likely with the  
ADMEM somewhere.   
<br> 
<br>Replaced both BSC ADMEMs in CLC crate (slots=16,17) for calorimeter style ADMEMs.  Calibrated both and all appears 
ok for the most part.  Configured the ADMEMs as follows: 
<ul> 
 <li><b>slot=16:</b> CEM summing algorithm (7DEC00), Et table 
  loaded with a discriminator pattern, trigger sum threshold=1000 
  ADMEM counts. Trigger output below threshold = 0x000.  Trigger 
  output above threshold = 0x3ff. 
 </li> 
 <li><b>slot=17:</b> PEM summing algorithm (7DEC00), Et table 
  loaded with a discriminator pattern, trigger sum threshold=1000 
  ADMEM counts. Trigger output below threshold = 0x000.  Trigger 
  output above threshold = 0x3ff. 
 </li> 
</ul> 
Again, after the configuration, I believe that everything is 
working correctly.  Below is a mapping of the entire crate. 
<br> 
<pre> 
 In Slot2   IDPROM = 0105 001 TRACER__V2.1A           
 In Slot3   IDPROM = 0354 003 ADMEM_V4.0          460 
 In Slot4   IDPROM = 0350 003 ADMEM_V4.0          460 
FISION: S_errno_EIO (0x5): VME BERR received! 
 In Slot6   IDPROM = 0356 003 ADMEM_V4.0          460 
 In Slot7   IDPROM = 0358 003 ADMEM_V4.0          460 
FISION: S_errno_EIO (0x5): VME BERR received! 
 In Slot9   IDPROM = 0357 003 ADMEM_V4.0          460 
 In Slot10   IDPROM = 0352 003 ADMEM_V4.0          460 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
 In Slot16   IDPROM = 0068 003 ADMEM_V4.0          470 
 In Slot17   IDPROM = 0118 003 ADMEM_V4.0          470 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
FISION: S_errno_EIO (0x5): VME BERR received! 
 In Slot21   IDPROM = 0360 008 MICHIGAN TDC  ECL Rev D 
 
QIE ID table: 
QIE    ADMEM:  3       4       6       7       9      10      16      17      
  0          2556     200    2439    2185    2489     274     311    2892 
  1          2320    2464    2477    2572    2355    2573    3614    4428 
  2          2377    2242    2321    4813    3373    4758    3622    1499 
  3          2337     263    2380    2144    2308    2530     444    4407 
  4          2515    2309     215    3156    2529    3515    2411    3072 
  5          2402     248    2332    6140    2149    2213     292    4243 
  6          2437     201     240    2519     262    2312     269    4213 
  7          4919    2397    2175    2510    2132    2250     321    4307 
  8          4955    2542    2128    2209    2120    2578     312    5134 
  9          2401    2583     276    2172    2589    2194     431     994 
 10          2338    2371    2236    2173    2432    2584     307     433 
 11          2392    2413     302    6315    2188    2543     264    1055 
 12          2544    2539     339    4890    2462    2343    1032    6573 
 13          2137    2200    2448    4948    2396    2197    4457     679 
 14          2554    2440     405    4912    2429    2187    2506     384 
 15          2260     253     479    5897    2291    2522    2368    3812 
 16          3332       0       0       0       0       0     239    1773 
 17          1370       0       0       0       0       0    2374    4360 
 18          1473       0       0       0       0       0    2568    1822 
 19          5400       0       0       0       0       0    2561    4333 
</pre> 
  
<!-- Author: R.J. Tesarek, K, Terashi -->


<!-- Date: Tue Mar 27 10:18:04 2001 -->
<pre>Fixing Bad Channels in Time Measurement 
--------------------------------------- 
Using the proton beam data collected last week Sasha 
was able to identify a few channels that have problem 
in time measurements. These are the channels (starting from 
1 to 96) and the location of the problem : 
 
ch 16 : stretcher 
ch 35 : stretcher 
ch 51 : stretcher 
ch 66 : transition board (truncated width in the ECL output) 
ch 77 : paddle board (a small fraction of events with 0 width) 
ch 79 : paddle board 
ch 86 : paddle board 
 
We replaced the "broken" stretcher electronics for those corresponding channels with parts taken from another partial 
completed stretcher box. The TB in which ch 66 is located was replaced by another TB which was repaired in Feb. We also 
replaced with another paddle board and the problem seen in 
ch 77,79,86 were gone. 
 
</pre>
<!-- Author: Sasha and Ming -->


<!-- Date: Tue Mar 27 13:42:08 2001 -->
<pre><br><b>b0wcal02:</b> 
<br>Matt Jones noted problems with crate the above crate responding (or more appropriately a lack of response). Again, 
tried to get the crate to respond appropriately. 
<ul> 
  <li> vxlogin <i>--> Unresponsive</i></li> 
  <li> minicom <i>--> Unresponsive</i></li> 
  <li> LV power<i>--> OK</i></li> 
</ul> 
Reset the crate and now everything appears ok. 
<br></pre>
<!-- Author: R.J. Tesarek -->


<!-- Date: Thu Mar 29 19:17:49 2001 -->
<pre>We timed in the CLC trigger signal into Pre-Fred and Fred. 
We used the B0 signal froma tracer in the 2nd floor, delayed 
it [by 3 micro-seconds, at the end] using the pulse generator 
[with a ~66 ns width] and put it into the NIM0 Pre-Fred input. 
With these conditions Carla programmed the following: 
 
Pre-Fred: 
 
 B0_offset = 23 
 Fine B0 = 110 
 
Fred: 
  
 coarse Fred delay = 1 CLK cycle 
 fine FRED delay = 66 ns 
 
 ===> This configuration worked well and the CLC trigger is 
       seen by both Fred and Pre-Freed</pre>
<!-- Author: Ming/Jaco -->


<!-- Date: Sun Apr 1 18:11:19 2001 -->
<pre>Timing Adjustment for CLC Data  
------------------------------  
Took data with coalesce proton beam using Trigger Table  
INTEGRATION_MINBIAS_CAL_TRIGGERS_v-2. Several sets of  
data taken early this morning and this afternoon in early  
Myron mode with different settings of ADMEM pipeline length  
and pipeline offset. The final setting to time in CLC is :  
 
Pipeline length = 28  
Pipeline offset = 7  
</pre>
<!-- Author: Ming -->


<!-- Date: Tue Apr 10 19:23:24 2001 -->
<pre>NEW Power supply for the CLC00 crate 
------------------------------------ 
 
This new power supply was installed this morning. It has the 
special voltage output that is required by the TDC  
(? am I right ?). So from now on we don't need two separate 
power supplies any more. Note: At the back of the crate the 
plastic protection cover has not been put on yet (to cover the 
expose area of the power cables) because the old cover cannot 
be fit in due to the new power cables. A new cover will be put 
in a day or two. 
 
We took a qie calibration run after we put back all the electronic boards into the clc00 crate. The calibration showed two bad channels : 
 
Admem #3, Qie #4 
Admem #10, Qie #15 
 
Both of them have very high raw pedestal (~300 - 350 ADC). 
The final pedestal after using the LUT from FRAM is about 
~ 100 ADC. 
 
Then we took a LED run and found that the modification that we did to solve the channel id offset problem does not solve the problem at all.</pre>
<!-- Author: Sasha and Ming -->


<!-- Date: Wed Apr 11 12:02:47 2001 -->
<pre>Try to fix the bad qie calibration problem in Admem 3 and 10. 
In Admem 3 qie 4, we saw raw ped value about 300 ADC. And when 
we remove the TB, the raw ped from this channel is ok, and it 
passed the calibration test. When we put back the TB, but remove 
the corresponding signal cable, we still observe the large 
raw ped for this channel. This seems to indicate that the is 
a problem in the TB for this channel. 
 
We have replaced TB in slots 3 and 10 and that fix qie calibration problem. Now the raw ped values are: 
	~100 in qie 4 slot 3 and 
	~200 in qie 15 slot 10 
</pre>
<!-- Author: Ming and Sasha -->


<!-- Date: Tue Apr 17 09:27:50 2001 -->
<pre><pre>There is an access to the collision hall today from 6am to 10pm. 
I have switched off the CLC HV for safety reason. 
</pre></pre>
<!-- Author: Ming -->


<!-- Date: Wed Apr 18 09:20:29 2001 -->
<pre>There is a 24-hr torture test for the Level-3 system today until 
mid-night. However CLC00 crate is not included in this test, so 
this means that we can do any studies with the crate today. 
 
I also talked to Del just now about finding out what gas is being 
filled in CLC East (Isobutane or N2). He said that most likely the 
papers (filled while the modules were filled) will indicate that CLC East 
was being filled with Isobutane. He will look into whether there is any 
way to test if the gas in CLC East is flammable. 
 
While we were discussing, we found that the CLC West pressure was 
gradually decreasing since last week. Now it is reading about 3.1 psi. 
However CLC East is still at about 3.6 psi. We decide to look at one case 
at a time (first check CLC East, then CLC West). 
</pre>
<!-- Author: Ming -->


<!-- Date: Wed Apr 25 12:56:05 2001 -->
<pre>We took standalone LED calibrations for various voltage 
settings. Alexei had to make some changes to the source 
code to get it to work. The output files show up on 
fcdfsgi2...</pre>
<!-- Author: Jaco/Sasha -->


<!-- Date: Sun May 13 15:06:05 2001 -->
<pre>TEST NEW CLC CLLD BANK 
---------------------- 
Operate CLC in standalone mode to test if the new 
CLC CLLD bank is correctly filled with online luminosity 
values. The test indicates that the bank is being filled 
properly. 
 
</pre>
<!-- Author: Ming -->


<!-- Date: Thu May 24 16:36:33 2001 -->
<pre>ONLINE clcreceive PROBLEM FIXED 
------------------------------- 
 
I think I have fixed the problem in the clcreceive program. The 
"problem" which I found is that the clcsend will only send new 
data to the 9U crate after it has received the acknowledgement 
from clcreceive that it had received the previous online lumi 
data from clcsend. Also there is no "time-out" for clcreceive to 
wait for new data from clcsend. So when the RTserver crashed the 
lumi data which was sent by clcsend right before the crash would 
not be received by clcreceive. And when the connection to 
Rtserver was restored (usually within a few sec) the clcreceive 
would still be waiting for the next lumi data from clcsend. In 
the mean time clcsend stopped sending data because it had not 
received any acknoeledgement from clcreceive that it had received 
the data which was sent right before Rtserver crashed. So both 
sides just keep waiting for new-data/acknowledgement. 
 
I have modified the receive.c code and have copied both the 
source file and the binary file into ~cdf_clc/online/clcdaq . 
 
 
</pre>
<!-- Author: Ming -->


<!-- Date: Fri May 25 18:39:12 2001 -->
<pre>We took out transition board #3 from ADMEM in slot #3 
because it was not responding to the amplitude gate. 
Its pedestals (rms and mean raw) were not changing 
when we applied the gate. Sasha had tested this board 
and found that the pedestals did change according to 
the gate, a couple of days earlier... so something 
happened... we need to give it to Charlie. 
 
We put back transition board #8 in that slot. This transition 
board is the one that has raw pedestals that shift UP when 
the gate is applied... otherwise it seems "calibratable". 
We need to get the board back from Charlie asap. 
 
	Jaco/Ming/Sasha</pre>
<!-- Author: Jaco/Ming/Sasha -->


<!-- Date: Mon Jun 4 18:52:42 2001 -->
<pre>Include Loose Min. Bias Trigger in CLC Coincidence Unit 
------------------------------------------------------- 
 
We re-programmed the FPGA in the CLC coincindence unit (CU) 
so that it can also output loose min. bias trigger for 
CDF Level-1 trigger. Previously the coincidence unit only 
output tight min. bias trigger, which requires at least 
two channels in each CLC East and CLC West to register 
signals above threshold, to PreFRED. The loose min. bias 
trigger only requires at least one channel in each 
CLC East and CLC West to register signals above threshold. 
 
We tested the outputs from CU by firing LED into CLC East and West, 
and only had the HV for one channel in CLC East and West turned on. 
In this case there was only trigger signal from the loose min. bias 
trigger. When we had HV for two channels in each east and west side 
turned on, we observed trigger signals from both loose and tight 
min. bias trigger.</pre>
<!-- Author: Ming, Sasha, Valentin -->


<!-- Date: Sat Jun 16 12:19:26 2001 -->
<pre>FIX CLC Bad Channels 
-------------------- 
 
This morning Sasha and I checked on those few bad channels that 
we observed from LumMon yesterday. We found that these channels 
were bad in the transition board. Initially we took qie calibration 
and found that channel 19,26, and 35 had zero pedestal values. 
When we removed the transition boards, we observed normal pedestal 
values for these channels. So we replaced these two broken 
transition boards (4,7) with the two repaired spares (1,3). 
This seems to have fixed the problem. We double checked with LED  
data. We will really need to get the two broken TB fix next week. 
</pre>
<!-- Author: Ming and Sasha -->
<!-- Comment: Sat Jun 23 10;13;44 comment by...Ming -->
<pre>STARTED OPERATING CLC IN NEW CONFIGURATION (SINCE JUNE 15th).
CLC E/W Pressure = 8 PSI
AMPLITUDE GATE width = 110 ns</pre>


<!-- Date: Sat Jun 23 14:58:01 2001 -->
<pre>CHECK EAST/WEST Amplitude GATES 
------------------------------- 
 
We looked at the amplitude gate signals after Tevatron 
dumped the beams this morning. The scope showed that the gates 
for east and west channels are of the same width, and they 
start at the same moment. We then took some LED runs with 
various delay set in the BNC to study the effect of the gate 
on the LED amplitude.</pre>
<!-- Author: Ming and Sasha -->


<!-- Date: Sat Jun 23 15:28:38 2001 -->
<pre>Operate CLC at 8 Psi and without amplitude gate 
----------------------------------------------- 
 
When we looked at the ratio of the single-particle-peak (spp) of 
the data taken with pressure=8psi and gate-width=110ns, and with 
spp of the data taken with pressure=3.5psi, and no gate, we 
noticed that there are greater variation in the ratio of the spp 
values on the west side than the east. Also the ratio is lower 
on the east side too. Since we found that the gates that were 
applied to the east/west channels are identical, then it is 
possible that there have been changes in the gains of the west 
channels. In order to further understand this problem, we decide 
to operate CLC without gate (at 8 psi). 
 
We re-calibrate the Qie without gate. However in this case one of the channel (qie 7, ch3) failed the calibration and its qie calibration constants could not be downloaded into its FRAM. 
This channel now has a ped of about 100-150 ADC. 
 </pre>
<!-- Author: Sasha and Ming -->
<!-- Comment: Sat Jun 23 15;29;58 comment by...Ming -->
<pre>GAS Pressure (@ 10:00 am June 23rd)
WEST : 7.9 Psi
EAST : 8.1 Psi
</pre>


<!-- Date: Fri Jun 29 08:48:21 2001 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-19&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-20  width='300' align='top'></td><td>The west still leaks.</a></td></tr></table>
<!-- Author: Steve Gordon -->


<!-- Date: Sat Jun 30 14:19:17 2001 -->
<pre>APPLY 50 ns gate on amplitude signal for the June29/30 store 
------------------------------------------------------------ 
 
At the TB input level : 
 
-------------+    /-------------- 
             |   / 
             |  / 
             | / 
             |/ 
 
    &lt;--30ns--&gt; 
    +---------------+ 
    |               | 
----+               +------------- 
    &lt;------50ns-----&gt; 
 
Qie was re-calibrated with this gate. 
 
We plan to have this gate only for a single store. 
During the 1st half of the store, the PMT signal will 
arrive 30ns after the leading edge of the gate. For 
the 2nd half of the store, the pmt signal will arrive 
20 ns after the gate's leading edge. 
</pre>
<!-- Author: Sasha, Ming -->
<!-- Comment: Sun Jul  1 16;16;20 comment by...Ming -->
<pre>For the first half of the store (run 119092 -&gt; 119112) the
leading edge of the gate arrives 30ns ahead of the PMT signal
(ch 48). For the second half of the store the gate was then
delayed by 10 ns (leading edge of the gate arrives 20ns ahead
of the PMT signal) starting from run 119113 -&gt; 119130.
</pre>
<!-- Date: Sat Jun 30 17:49:43 2001 -->
<pre>Perform CLC amplitude gate study by shifting the gate  
+10ns w.r.t. the CLC PMT signal. This new gate set  
applies to run starting from 119113. Initial observation  
shows that this new gate offset does not have significant  
effect on the online instantaneous luminosity value.  
</pre>
<!-- Author: Ming -->


<!-- Date: Sun Jul 1 13:10:28 2001 -->
<pre>Tevatron dumped p/pbar beams around 12 noon. We took out 
the amplitude gates, put back channel 48 (East layer 1, 1st 
channel), and re-calibrate the QIE. 
 
Check the gas pressure (@ 12:50 pm) : 
West : 7.7 Psi 
East : 7.9 Psi</pre>
<!-- Author: Sasha, Ming -->



<!-- Date: Sun Jul 1 17:23:03 2001 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-25&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-25  width='300' align='top'></td><td>(Top plots): The leading edge of the 50 ns gate is about 30 ns ahead w.r.t. the PMT signal (from ch48). (Bottom plots): The leading edge of the gate is about 20 ns ahead w.r.t. the PMT signal.  </a></td></tr></table>
<!-- Author: Ming -->


<!-- Date: Sun Jul 1 17:24:52 2001 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-26&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-26  width='300' align='top'></td><td>The amplitude distribution of ch 48 from proton beam. A small peak (after pulse) can be observed at about 330 ns.</a></td></tr></table>
<!-- Author: Ming -->


<!-- Date: Tue Jul 3 15:04:15 2001 -->
<pre>CLC Gas pressure 
---------------- 
The gas pressure measured this morning : 
 
West : 7.7 psi 
East : 8.0 psi 
 
This is similar to what was measured two days ago. 
It seems that there is almost no leakage. Dean checked 
the panel at the 730 platform just now and counld not 
find any leak. The pressure was then brought up again 
this afternoon : 
 
West : 8.1 psi 
East : 8.0 psi 
</pre>
<!-- Author: Ming -->


<!-- Date: Wed Jul 11 09:34:00 2001 -->
<pre>CHECK GAS LEAK IN COLLISION HALL (07/10/01) 
------------------------------------------- 
 
Sasha, me and K.C. Cahill went down to the collision hall 
to check if there was any gas leak in CLC west. No leak 
was detected along the gas lines (input and output). However 
when we checked the backplane of the CLC, we were able to 
detect flammable gas. The detection signal became very strong 
at the top of the CLC west back plane (at 12 o'clock). The 
detection signal grew weaker when we moved the gas sniffer 
away from the 12 o'clock position. The detection signal was 
as strong when the gas sniffer was moved along the vertical 
line of the 12 o'clock position.  
 
                     _______ 
                   /    O    \  
                  /     O     \ 
                 |      O      | 
                 |             | 
                 |             | 
                  \           / 
                   \         / 
                    --------- 
 
"O" marks the position that we detected strong signal 
of flammable gas. We tighten the bolts around this 
region. Hoping that this will stop the leak. 
 
The gas pressures measured after the tightening were: 
 
(07/10/01 15:25) 
West = 7.93 Psi 
East = 8.19 Psi 
 
 </pre>
<!-- Author: Sasha, Ming -->


<!-- Date: Wed Jul 11 09:38:02 2001 -->
<pre>CLC GAS PRESSURE (07/11/01) 
--------------------------- 
This morning the pressure values were : 
 
@ 07:40 
West = 7.80 psi 
East = 8.10 psi 
 
Comparing to the values measured on 07/10/01, it seems 
that the drop in east pressure is likely due to the effect 
from the changing of the atmospheric pressure. If we use this 
to correct the west pressure, then it seems to indicate that 
the west pressure had dropped by about 0.04 psi since 
yesterday afternoon. 
 
</pre>
<!-- Author: Ming -->


<!-- Date: Mon Jul 23 11:23:41 2001 -->
<pre>Perform test to check the Xilinx Threshold 
------------------------------------------ 
 
Offline simulated values of the online lumi measurements 
(using 500 ADC threshold) is found to be lower than the 
online. One possible explanation is that the actual threshold 
in the Xilinx may be lower than 500 ADC. 
 
We use Qietest to inject specific amount of charge into CAFE 
card of the ADMEM, and observe the number of hits recorded by 
the online lumi DAQ program in the 6U. The threshold levels 
that we observed are :  
 
ADMEM                        Threshold (ADC) 
---------------------------------------------------- 
  3 (W L1)                       500 
  4 (W L2)                       200 
  6 (W L3)                       500 
  7 (E L1)                       500 
  9 (E L2)                       450 
 10 (E L3)                       500 
 
We will use these values offline to see if we can reproduce 
the online lumi values. 
</pre>
<!-- Author: Sasha & Ming -->


<!-- Date: Tue Jul 24 10:30:47 2001 -->
<pre>Download the Xilinx program (with 500 ADC threshold) into 
ADMEM slot #4. 
 
The Xilinx program with threshold 500 ADC is : 
clc_6_23_00.exo . 
 
This program can be found in Jaco's directory (online) or 
in my directory (/cdf/people3/smwang/clc/xilinx). 
 
Test performed using Qietest indicates that the threshold now 
is 500 ADC.</pre>
<!-- Author: Ming -->


<!-- Date: Tue Jul 24 10:41:53 2001 -->
<pre>Instruction to download Xilinx into ADMEM 
----------------------------------------- 
 
1) Logon to online machine. Go to  
   /cdf/people1/cdf_cal/admem/bin . 
 
2) Type "./rklein_login.xpt b0clc00" and hit enter. 
 
   This will automatically download anadmem_ppc.o into 
   b0clc00, log into b0clc00, and execute the program. 
 
3) You will see a menu "anadmem_menu". 
 
     - Choose 3 for "Addmem" 
     - Hit Enter for "Controller" input 
     - For entering "Slot", enter the slot number of 
       the Admem that you want to download the Xilinx 
       program. 
 
4) Enter "Q" to exit this menu. 
 
5) In the new menu choose "4" to goto "Admem Checkout Menu". 
 
6) Choose "10" for "Pipeline Download S-Record Test". 
 
7) Enter the filename (full path) of the Xilinx program 
   (e.g. /cdf/people3/smwang/clc/xilinx/clc_6_23_00.exo). 
 
    The old Xilinx program in the FRAM of the ADMEM will 
    first be erased before the new Xilinx code can be 
    downloaded into the FRAM. I think one would then need to 
    either reboot the crate or power-cycle the crate so 
    that the Xilinx chip can be re-programmed with this 
    new code. 
 
8) Enter "Q" to exit this menu. 
 
9) Enter "Q" to exit this program. 
 
</pre>
<!-- Author: Ming -->


<!-- Date: Fri Jul 27 15:42:19 2001 -->
<pre>CLC GAS PRESSURE 
---------------- 
 
The gas pressure for both modules are set at 8 Psi. We 
will operate at this mode so that we can compare the SPP 
from the coming new data (this weekend) to the SPP from 
early July taken under the same pressure. 
 
Pressure: 
West = 8.0 psi 
East = 7.9 Psi 
 
Ming</pre>
<!-- Author: Ming -->


<!-- Date: Fri Jul 27 15:43:38 2001 -->
<pre>Modify Send Program 
------------------- 
 
 ***  Update        July 27th 2001    (Ming)                 *** 
 ***       -&gt; Modify CLC Inst. Lumi per bunch :              *** 
 ***          o Using approx 8.8 hits per side (2 layers)    *** 
 ***            obtained from the 36x36 0-bias data          *** 
 ***            collected in April 2001.                     *** 
 ***          o Using Simga_effective = 38.9 mb              *** 
 ***            Obtained from simulation using MBR           *** 
 ***            (EL+SD+DD+HC) with 3X0 material infront      *** 
 ***            from CLC to reproduce roughly                *** 
 ***            the same hit multiplicity as in the data.    *** 
 ***       -&gt; Change the coincidence requirement from        *** 
 ***               (N_East &gt; 1) && (N_West &gt; 1)              *** 
 ***                           to                            *** 
 ***               (N_East &gt; 0) && (N_West &gt; 0)              *** 
</pre>
<!-- Author: Ming -->


<!-- Date: Sat Jul 28 18:15:45 2001 -->
<pre>New bad CLC channels 
-------------------- 
 
This afternoon Tevatron started a shot. Initially they injected a lot of 
p/pbar beams into Tevatron (P-&gt; 3500 E09, A-&gt;300 E09). But as they rumped 
up the beams to 980 GeV they lost a lot of p/pbar (down to P-&gt; 800 E09, 
A-&gt;100 E09). And at the same time the iFix report an alarm from CLC which 
indicate that the HV of CLC had tripped. This alarm went away quickly as  
the HV was turned back on again automatically. However when I was looking 
at the LumMon plots I found that ch 19, 26 showed zero amplitude and       
ch 35 showed amplitude at 50 ADC. These channels were ok yesterday 
(7/27/01) observed from LED data. It is possible that the tripped in the 
HV might have killed these three channels in the TB. We will need to 
investigate this after the beams are dumped. 
 
Ming 
</pre>
<!-- Author: Ming -->


<!-- Date: Sun Jul 29 10:43:44 2001 -->
<pre>Replace TBs 
----------- 
The three bad channels were found to be in TBs of 
slot 4 and 6 (TB Id 1,7). Although we have 3 spare TBs, 
only one is completely OK (Tb 4), the other two (TB 0,5) 
had failed QIE calibration. We decided to swap TB 1,7 
with TB 4,5.  (TB 4 in slot 4, and TB 5 in slot 6). We 
then performed Qie calibration on these two TBs. Channel 
38 and 43 failed the calibration, and thus no new calibration 
constants are downloaded for these channels. 
 
I don't know whether channel 38 and 43 are still Ok using 
the old calibration constant. This is because the pedestal 
values are now at about 130 ADC and not 50. So, the conversion 
from charge to ADC may not be done correctly if the pestestal 
baseline is not subtracted properly. 
</pre>
<!-- Author: Ming -->


<!-- Date: Tue Jul 31 10:31:11 2001 -->
<pre>Update the constants used in the ONLINE LUMI Calculation 
-------------------------------------------------------- 
in SEND program 
--------------- 
 
 ***  Update        July 31th 2001    (Ming)                 *** 
 ***   -&gt; Readjust the Effective cross-section, and average  *** 
 ***        number of hits due to drop in PMT gains          *** 
 *** Ave Num of Hits = 13.8 hits for E+W L2+L3               *** 
 ***        (at 500 ADC). This value obtained from the 36x36 *** 
 ***        0-bias/LMB data collected on July 28-29 2001     *** 
 *** Simga_effective = 36.5 mb                               *** 
 ***   Obtained from simulation using MBR (EL+SD+DD+HC)      *** 
 ***   with 3X0 material infront from CLC. Normalized MC to  *** 
 ***   data based on the fitted SPP measured in data         *** 
 ***   (July 28-29)                                          *** 
 ***                                                         *** 
 
</pre>
<!-- Author: Ming -->


<!-- Date: Wed Aug 8 18:05:38 2001 -->
<pre>Increased the West CLC pressure from7.40 PSI to 8.0 PSI, 
Steve did it. Collision Hall closed. 
Shasha taking calibrations in normal configuration and 
also with less electronic boards (no east ADMEMs nor 
 transition boards)</pre>
<!-- Author: Jaco -->


<!-- Date: Fri Aug 10 14:45:57 2001 -->
<pre> 
 Investigating "noise" on the crate associated with DAQ 
 ======================================================= 
 
 Aug 9th, Jaco noticed that the rate on ACNET associated with 
 the West layer 1 SUM, was of the order of 5*E5 and there  
 was no other rate diff. than zero! there was no beam in the 
 machine but the CDF DAQ was taking data with the physics 
 trigger table. 
 
 We asked the ACE to PAUSE the run and the rate went away! 
 when the run restarted the rate came back. We managed to 
 do a few investigations but needed quiet time and we've gotten 
 very little so far. 
 
 * We unplugged the cable from the transition board corresponding 
    to that middle West layer from the coincidence unit and 
     we saw the rate go to zero. We think therefore that the 
     problem might be uspstream of the c.u., although it could 
     also be a bad connection at the coincidence unit. 
      
 * We looked on the scope at the flat cable and saw a 132 ns 
    frequency but did not have much time to understand this. 
    what was the amplitude? etc. 
 
 * The 5*E5 frequency is suspiciously close to the B0 rate ! 
 
 * We measured the voltages on the crate (Fred Lewis) and they 
    are OK. We also measured the drawn currents and they are also     
   fine: 
 
	Voltage		Drwan curr		Supply max curr, 
       ---------	-----------		--------------- 
	+5DD		48.9 Amp		120 
	+5A		10.9			 80 
	-5.2		23.5			 30 
	+15		10.9			 26.6 
	-15		 4.3			 13.3 
	+12		 1.0			  4.3 
	-12		 0.9			  4.3 
 
 * We also asked the BSC people if anything was done on the 
    crate. Apparently not. 
 
 * we need to keep debugging it w/o beam. Perhaps change the 
   c.u. and see if it it still there. We can also swap cables 
   from the transition boards. Would be good to debug standalone 
   and see if the standalone CLC readout produces this "noise"</pre>
<!-- Author: Jaco -->


<!-- Date: Sat Aug 11 11:48:34 2001 -->
<pre> 
 * Sasha took an LED calibration w/no beam, mostly (at some 
   points there was proton beam in the machine and he took 
   care that the data was not taken when this ocurred) 
 
   Preliminary: the West showed a small drop on avg. and 
   perhaps a larger rms than usual. The East seems to have 
    the same gain as a few days ago. 
 
 * We tried to debug the "noise" in the crate by taking standalone data and seeing if we could see the 500 KHz noise 
 in the middle West layer. We did not see this noise but  
 saw a very low 1-4 Hz rate that came and went when we started 
 or paused the standalone DAQ. We then swapped the cable from 
 thi middle layer T.B. to the outer layer input on the C.U. 
  and saw no rate... this would mean that the problem might 
 be in the C.U. However when we switched this cable back to 
 its original connector we did not see the rate come back! 
 &gt;&gt; maybe some problem on the connector itself or on the 
    cable. 
 
 * We switched over the crate to the ACES because proton beam is 
    imminent and also to see if the 500 KHz rate comes back 
 when they take data.</pre>
<!-- Author: Jaco/Sasha -->


<!-- Date: Sat Aug 11 11:54:43 2001 -->
<pre> 
 Ok, we see now a low rate in the *inner West* layer 
 when the DAQ is running, and the rate goes away when they pause. 
 There might also be a low rate in the East (1 Hz). The West 
 rate is a few Hz (2-6). We no longer saw the 500 KHz but 
 we should keep an eye on this. 
 
 &gt;&gt;&gt; for now: CLC SHIFT PERSON SHOULD CHECK THESE RATES A FEW 
      TIMES A DAY! 
 
 We suspect something flaky with the C.u. ?</pre>
<!-- Author: Jaco/Sasha -->


<!-- Date: Tue Aug 14 09:31:36 2001 -->
<pre>CLC GAS PRESSURE 
---------------- 
 
The gas pressure has dropped to : 
 
West : 7.55 psi 
East : 7.76 psi   (measured @ 08:30 08/14/01). 
 
The rate of drop for the west side is still about 0.06-0.07 psi 
per day. Asked Del to bring pressure back up to 8 again before 
shot start. 
</pre>
<!-- Author: Ming -->


<!-- Date: Fri Aug 17 18:10:49 2001 -->
<pre> 
 Work on the CLC electronics during no beam down time 
 
 1- Took LED calibrations with system as it is 
 2- swapped channels 48 and 32 (from 0) 
     last calibration Gain(32)~2.5 10**5 
                      Gain(48)~3.2 10**5 
 
 &gt; we want to check if gain stays with the cable or 
    with the electronics 
 
 3- We are changing two transition boards on the West side 
    because of bad channels, inner and outer layer. 
    * Channels 14 and 33 (from zero) are blown 
    * Channels 38 and 43 (from zero) have large pedestals. 
 
 4- We re-calibrated 
 
 5- We unplugged channels 48 and 0 (first channels on each side) 
    so we can monitor thei signals directly. Does not affect 
    the onlne luminosity 
  
 </pre>
<!-- Author: jaco/ming/sasha -->


<!-- Date: Sun Aug 26 17:40:20 2001 -->
<pre>CLC Send Program not running 
---------------------------- 
 
Tevatron started a new store of collision at about 
17:00 today (08/26/01). However I noticed that the send 
program was not running. I rebooted the crate to restart 
the process. I should have checked whether the process had 
been downloaded into b0clc01. 
 
</pre>
<!-- Author: Ming -->


<!-- Date: Fri Aug 31 23:04:11 2001 -->
<pre>Ming swapped tracer earlier. Even though we had a very short run 
I looked at the rates from the inner and middle West layers 
to see if DAQ noise was present. Seems like it is... 
Look at next picture</pre>
<!-- Author: Jaco -->


<!-- Date: Fri Aug 31 23:06:04 2001 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-27&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-27  width='300' align='top'></td><td>see entry above</a></td></tr></table>
<!-- Author: Jaco -->


<!-- Date: Fri Aug 31 23:34:12 2001 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-28&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-28  width='300' align='top'></td><td>Same pi as above but shows that ONLY inner and middle west layers have DAQ noise pickup, all other layers are smooth</a></td></tr></table>
<!-- Author: Jaco -->


<!-- Date: Sat Sep 1 20:18:16 2001 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-29&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-29  width='300' align='top'></td><td>We still see DAQ influence on the inner and middle West layers... (new tracer). Maybe the backplane is suspect? Maybe the C.U. (do we see any effect on the timing?)</a></td></tr></table>
<!-- Author: Jaco -->


<!-- Date: Sun Sep 2 16:47:26 2001 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-30&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-30  width='300' align='top'></td><td>Seems like Do's Lum changed in between stores. the B0ILUM  to B0C09 ratio is more or less the same. I will chak the LUMMON plots to make sure nothing changed with the CLC. </a></td></tr></table>
<!-- Author: Jaco -->


<!-- Date: Tue Sep 4 19:47:26 2001 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-31&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-31  width='300' align='top'></td><td>Luminosity during CLC timing scans (CAFE) Ming and Sasha</a></td></tr></table>
<!-- Author: Jaco -->


<!-- Date: Wed Sep 5 19:14:14 2001 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-32&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-32  width='300' align='top'></td><td>I see correlation between the live-time fraction and the degree of change in the West layers 1 and 2 rates!</a></td></tr></table>
<!-- Author: Jaco -->


<!-- Date: Wed Sep 5 20:00:03 2001 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-33&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=clc&action=view&page=-33  width='300' align='top'></td><td>Tested if the West rate problem goes away if we unplug the L2 global trigger cable from the "T". Id does not. I unplugged i at about 19:00 and it is now 20:00 and we see the problem keeps happening...</a></td></tr></table>
<!-- Author: Jaco -->