<!-- Title: 13:41:53  Wed Sep 13 2000 -->
<!-- Crewchief: Steve Nahn -->
<!-- Op1: Mary Bishai -->
<!-- Op2: Steve Blusk -->
<!-- Op3: Matt Herndon -->
<!-- Op4: &nbsp; -->
<!-- Op5: &nbsp; -->
<!-- Op6: &nbsp; -->
<!-- Notes: -->
<pre>Barrel 4 preparation for Commissioning run  
</pre>


<!-- Date: Wed Sep 13 15:10:24 2000 -->
8/31/00 B4 in assembly hall 
  
SVX EAST 
========= 
 
Wedges 2 and 3 all ladders init. Wedge 3 HDI2 Z side dropping readout I_dvdd > 200mA 
 
SVX WEST 
======== 
 
Wedge 2 HDI0 readout errors. Idvdd = 20mA but turns out power 
supply has 50mA offset. 
 
 
Wedge 2 HDI3 chip id problems as seen at Sidet 
 
ISL  
==== 
 
All 4 HDIs init : 
 
HDI	DVDD 	I-DVDD 
0	5.61	215 
1	5.62	185 
2	5.64	330 
3	5.62	315 
 
SVX EAST BIAS 
============== 
 
wedge 2 
 
HDI	Bias	Current 
0	20	0 
1	20	0 
2	20	2.0micro 
3 	20 	0 
4	20	280 micro and decreasing 
0	90	13 -> 11micro 
1	80	48micro 
2	35	18 
3	85	0 
4	58	245 after 3 mins 222 after 15 mins 
 
EAST WEDGE 3 
------------ 
 
HDI	Bias	Current after 2 mins	After 10mins 
0	90	0			0 
1	90	243<			287 
2	35	79			52 
3	85	0			1.0 
4	36	0			0 
 
SVX WEST WEDGE 2 
----------------- 
 
HDI	Bias	I microamps after about 2 mins 
0	90	5 
1	90	100 
2	55	3 
3	85	1 
4	58	53 
 
SVX WEST WEDGE 3 
================= 
 
HDI	Bias	I(microA) after 2 mins 
0	90	4 
1	90	122 
2	35	567 
3	80	9 
4	40	725 
 
		9/1/00 
 
Adjusting PS 001 for SVX EAST WEDGE 3 at FCC: 
 
DVDD2 = 5.56	I=125mA 	DVDDelco = 5.43 
DVDD2 = 5.70	I=145mA		DVDDelco = 5.64 
DVDD2 = 5.85    I=165mA		DVDDelco = 5.70 
 
Adjusting PS 004 for SVX WEST WEDGE 2 at FCC 
 
DVDD0=5.31	I=15mA		DVDDelco = 5.23 
DVDD0=5.59	I=21mA (+50)	DVDDelco = 5.51 
 
SVX EAST PS 001 DVDD2 overvoltage in B0 had to turn down DVDD 
to 5.72V from 5.85V - ladder still drops readout. 
 
WEST SVX WEDGE 2 
-================= 
 
After PS adjusted for DVDD0 HDI0 still has readout errors and now 
HDI2 also has similar errors. 
 
 
Run all east with RC unbiased: 
 
b0dau30:/data1/svxData/B4_east.trybos 
 
WEST LAYER 00 
------------- 
 
HDI 0 inits successfully after failing several times. Currents are strange: 
 
DVDD = 5.33	I=292mA 
AVDD = 7.75	I=2mA	 
  
<!-- Author: Mary Bishai -->


<!-- Date: Wed Sep 13 15:33:43 2000 -->
<table><tr><td><a href=/elog/notebooks/barrel4/Wed_Sep_13_2000_153258.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>B4 SVX EAST Wedge 2 biased - Assembly hall</a></td></tr></table>
<!-- Author: Mary Bishai -->


<!-- Date: Wed Sep 13 16:06:47 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=barrel4&action=view&page=-3&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=barrel4&action=view&page=-3  width='250' align='top'></td><td>B4 SVX WEDGE 3 EAST BIASED</a></td></tr></table>
<!-- Author: Mary Bishai -->


<!-- Date: Wed Sep 13 16:07:58 2000 -->
<table><tr><td><a href=/elog/notebooks/barrel4/Wed_Sep_13_2000_160754.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>B4 SVX WEDGE 3 EAST BIASED</a></td></tr></table>
<!-- Author: Mary Bishai -->


<!-- Date: Wed Sep 13 16:10:05 2000 -->
<table><tr><td><a href=/elog/notebooks/barrel4/Wed_Sep_13_2000_160955.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>B4 ISL BIASED Assembly Hall</a></td></tr></table>
<!-- Author: Mary Bishai -->


<!-- Date: Wed Sep 13 16:12:05 2000 -->
<table><tr><td><a href=/elog/notebooks/barrel4/Wed_Sep_13_2000_161057.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>B4 SVX WEST WEDGE 2 BIASED</a></td></tr></table>
<!-- Author: Mary Bishai -->


<!-- Date: Wed Sep 13 16:12:37 2000 -->
<table><tr><td><a href=/elog/notebooks/barrel4/Wed_Sep_13_2000_161231.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>B4 SVX WEST WEDGE 3 BIASED</a></td></tr></table>
<!-- Author: Mary Bishai -->


<!-- Date: Fri Sep 15 07:57:34 2000 -->
<pre>Power supply and cabling progress. 
 
All CAEN crates now installed 
All power supplies now installed. 
  SVXII power supplies on east side have 5V DOIM adjusted(+200mV) 
Power supply cables connected. 
CAENNet and 5V enables are connected. 
Junction cards configured for collision hall running. 
 
PS and FIB map 
 
Collision hall 
 
System     Slot  Bulkhead  Wedge  FIB Rack    PS Slot  Fib  Crate 
East                                                        ID 
SVX        025   3         2      NE Top      0        9A   FIB04 
SVX        042   3         3      SE Bottom   0        9B   ??  
 
West 
SVX        041   2         2      NW Top      0        11A  ?? 
SVX        042   2         3      SW Bottom   0        12B  FIB02 
ISL        039   Cen West  ?      SW Top      1        11A  FIB01 
ISL(SOC)   052   SOC       ?      SW Top      3        11B 
L00        045   West      ?      SW Top      5        16A 
 
 
 
 
Things to do: 
Bring 4th CAENNet controller to B0. 
Test chaining of SVXII and ISL crates in South West. 
Check that AB designations in this FIB slot map are correct.</pre>
<!-- Author: matt herndon -->


<!-- Date: Sat Sep 16 08:02:50 2000 -->
<pre> 
System  Slot    Bulkhead Wedge  FIB Rack PS Slot Fib Slot Fib Crate 
======  ====    ======== =====  ======== ======= ======== ========= 
East 
SVX     025     3        2      NE Top   0       9A       B0FIB04 
SVX     042     3        3      SE Bot   0       8B       B0FIB06 
 
West 
SVX     041     2        2      NW Top   0       18A      B0FIB00 
SVX     042     2        3      SW Bot   1       17B      B0FIB02 
ISL     039     C. West  ?      SW Top   1       11A      B0FIB01 
SOC     052     SOC      ?      SW Top   3       11B      B0FIB01 
L00     045     West     ?      SW Top   5       16A      B0FIB01 
 
</pre>
<!-- Author: Mary bishai -->


<!-- Date: Sat Sep 16 08:12:00 2000 -->
<pre>Temporary instructions for running DAQ standalone in B0 
1. crate files are on ncdf79 ~bishai/daq_devel/rundaq_b0 
2. must use setup file on b0da* 
                ~bishai/cvs/setup.csh 
3. to run CAEN 
        java CAEN.PSControlForm</pre>
<!-- Author: Mary Bishai -->
<!-- Comment: Sat Sep 16 09;30;10 comment by...Jean Slaughter -->
also redirect $CAENCONTROL_DIR 
 setenv CAENCONTROL_DIR ~bishai/cvs/rundaq_b4
<!-- Date: Sat Sep 16 08:13:53 2000 -->
<pre>Test of SVX NW wedge 
    1. No current on DVDD L0 
    2. rest of HDI's init</pre>
<!-- Author: Mary Bishai -->



<!-- Date: Sat Sep 16 13:35:45 2000 -->
<pre>Summary of West side work: Running in SVXDAQ mode 
    crate files are in  
        /cdf/code-common/cdfonline/svxii/devel/b0crates/b4 
 
  1. SVX 
      a. hdi 3 on NW top still doesn't work 
      b. hdi 4 gives z side pipe cap errors occasionally 
              also illegal channels.  - should try incresing DVDD 
      c. common mode noise seems to have disappeared in  
              collision hall - WHY! 
       d. hdi 0 and 2 were helped by raising  5 V DOIM by 150 mv 
              on the portcard. 
  2. SOC  
       a. 6, 7 init and take data, 8 won't init, really 
               doesn't init as currents don't change - didn't 
               try biasing today. On September 15 it was biased 
               and runs given to Dave Stuart ( 100 V on 6 
               not enough for full depletion, 95 on 7 was fine- 
               fully depleted as seen in noise/dnoise. 
       b. can only run 5 minutes at a time. 
   3. L00 
        a. Wrong fib channel, now fixed.  it is hdi 0  
        b. AVDD ground found to be dis-connected, somewhere 
             between junction card and ladder. Attached hdi0 
             avdd ground to hdi 3 avdd gnd at the small part 
             of junction card.  Now draws small amount of 
             35 ma on AVDD, but DVDD is styill high, 232- 
              is this because of transceivers?  
             current 
       </pre>
<!-- Author: jean slaughter -->
<!-- Comment: Sat Sep 16 14;58;04 comment by...Jean Slaughter -->
Run Summary for previous entry<br>
   /cdf/code-common/cdfonline/svxii/devel/b0crates/b4/data<br>
<br>
SVX WEST<BR>
laser100.svx  ungrounded, unbiased  <BR>
laser110.svx  grounded, biased <BR>
laser111.svx  ungrounded, biased (we think) <BR>
<BR>
SOC <BR>
laser106.svx  unbiased, hdi 6,7 <BR>

<BR>
SVX east <BR>
 laser114.svx unbiased,  ungrounded<br>
	 laser115.svx biased, ungrounded
<!-- Date: Sat Sep 16 14:10:13 2000 -->
<pre>Summary SVX east side 
   1. all 10 channels init 
   2. pipe 7 drops readout - we should try reaising DVDD 
   3. Looks same as in assembly hall - NO common mode noise 
   4. laser114.svx unbiased 
      laser115.svx biased</pre>
<!-- Author: Steve Nahn -->



<!-- Date: Sat Sep 16 17:51:59 2000 -->
<pre>The SVX DAQ was experiencing strange problems when trying to run 
with the CDF_CLK, including garbage from the TS and VRBs not 
getting anything beyond the FIB header (no chip data). 
 
The beam structure changed twice since we run the  
last time, so the hypothesis is that the 53 MHz clock 
phase was shifted with respect to CDF_CLK.  On Saturday 5:30pm 
I moved the 53 MHz setting from 7 to B (on the clock fanout B) 
which moved the 53 MHz rising edge by about 10 ns (hard to tell 
on a LA), which is where I think it should be. 
 
On the LA connected to the SRC, MC0 = CDF_CLK, MC1 = CDF_CLK_BC, 
MC2 = CDF_CLK_GAP.  The lines SYNC, BX, BZ and GAP are after 
processing by the SRC. 
 
In Champaign, I can be reached at (217) 244-3667 and 367-6043. 
May the Xilinx be with you! 
</pre>
<!-- Author: Petar (SRC maintenance) -->


<!-- Date: Sat Sep 16 19:29:39 2000 -->
<pre>Wedge 2, west end, has been grounded to front face of COT</pre>
<!-- Author: 
att HerndonWest side, wedge 2 is grounded at the juMatt Herndon -->


<!-- Date: Sun Sep 17 11:13:09 2000 -->
 
    Briefly, here is the status of things in barrel 4 
<ol> 
<li>L00 AGND or AVDD appear to be really disconnected and it 
will not be in the commissioning run.  We checked that it 
is really a problem at the cable our from the port card and 
not a junction card problem (andhence not fixable). 
 
<li>Unfortunately, the ISL components of barrel 4 all went missing 
and did not initialize after the move to the collision hall. 
We were unable to recover these after extensive debugging efforts 
at the junctioncard, FIB, crate, power supply, and cable level, 
although all of the analog, digital and  DOIM voltages appear to 
be connected and do draw roughly the expected amount of current 
that they should when the chips are not initialized.  (Since the 
currents do not change when the initialization commands are given, 
we have to conclude that they are not receiving or correctly processing 
these intializations.)  We are not totally out of options here, but 
have done as much as we can imagine doing right now at the end of the 
COT at the present time. 
 
<li>2 out of 3 ladders of the SOC (silicon outside the COT) do 
initialize. 
 
<li>All 20 half-ladders of the SVX initialize,and 18 of these 
20 appear to read out correctly.  There were some bit errors on 
some of the laddersont eh West end (I think), but these should 
improve or go away when the temperature of the cooling can be 
lowered to the desired values...this is basicxally what we expected 
for these ladders based on what we saw from running at SiDet. 
 
<li>On the "good news" front we can add that we did tests of 
the cooling system and interlocks today that appear to show that 
there is plenty of headroom -- more han we had been accounting 
for up to now -- for running the system sub-atmospheric with good 
flow rates.  If we can implement this improved understanding as 
expected, then both for barrel 4 and the real silicon we should be 
able to operate well away from trip points and have adequate headroom 
for very reliable operation.  We have some further work to 
do on the CAEN enable wiring terminations and on tuning up the 
interlocks and related code before we can get to routine conditions, 
but based on the previously implemented mods and progress plus 
documentation submittred by Rich Stanek, we have already received 
the official ORC clearance for unattended operation. 
</ol>  
<!-- Author: Alan Sill -->


<!-- Date: Mon Sep 18 10:29:03 2000 -->
<pre>Status of cooling: 
 
Yesterday cooling was started again to B4 by Rob Roser with the same setpoint as in Saturday's tests (12.5 degrees C).  It has been running stably since then.  COT people want to do a check of variation of their temperatures monitored at various locations as we change the setpoint of the silicon cooling.  As a first step on this, I have changed the chiller setpoint upwards to 15 degrees (silicon power is presently off).  Morris Binkley took a snapshot of COT temperatures just before I did this, and we will compare these to subsequent temperature readings after giving the system time to warm up for a while.  Then we will lower the setpoint and repeat the test after giving the system more time to equilibrate.  Power will be off to the silicon for the duration of this test.</pre>
<!-- Author: Alan Sill -->
<!-- Comment: Tue Sep 19 09;17;56 comment by...SCN -->
Repeated in better format next entry
<!-- Date: Mon Sep 18 10:30:52 2000 -->
<pre><pre>Status of cooling: 
 
Yesterday cooling was started again to B4 by Rob Roser with the 
same setpoint as in Saturday's tests (12.5 degrees C).  It has 
been running stably since then.  COT people want to do a check 
of variation of their temperatures monitored at various locations 
as we change the setpoint of the silicon cooling.  As a first 
step on this, I have changed the chiller setpoint upwards to 15 
degrees (silicon power is presently off).  Morris Binkley took a 
snapshot of COT temperatures just before I did this, and we will 
compare these to subsequent temperature readings after giving the 
system time to warm up for a while.  Then we will lower the 
setpoint and repeat the test after giving the system more time to 
equilibrate.  Power will be off to the silicon for the duration 
of this test.</pre></pre>
<!-- Author: Alan Sill -->


<!-- Date: Mon Sep 18 18:08:59 2000 -->
<pre>5V enable and CAEN net information 
 
Corner   CEAN net    Crate   Supply            5V enable 
                     number 
SW       ISL SWT 1   01      ISL               L00 SWT En2 
                             SOC               L00 SWT En2 
                             L00               not enabled 
         ISL SWT 1   02      SVX West Wedge 3  SVX SWB En3 
         (note svx is daisy chained off ISL caen net line) 
 
 
NW       SVX NWT 1   03      SVX West Wedge 2  SVX NWT En1 
 
NE       SVX NET 1   05      SVX East Wedge 2  SVX NET En1  
 
SE       SVX SEB 1   07      SVX East Wedge 3  SVX SEB En1  
 
</pre>
<!-- Author: Matt Herndon and Rob Napora -->


<!-- Date: Mon Sep 18 18:19:29 2000 -->
<pre>Silicon cooling test of effect on COT is now done.  Set point on 
the chiller is now set to 8 degrees C, and enables on SVX II 
power supplies have been turned on.  OK to run this portion of 
B4 power; do NOT run ISL B4 until further notice.</pre>
<!-- Author: Alan SIll -->


<!-- Date: Mon Sep 18 18:43:18 2000 -->
<pre>From COT people: 
Our coldest spot is the bottom of the inner cylinder about 2 feet from the 
West endplate.  It is now about 1.6 deg C lower than when we started the test, a 
nd we don't think that this is a problem.  Please go ahead and run power if you 
wish. 
 
Bob  
</pre>
<!-- Author: Bob Wagner -->


<!-- Date: Mon Sep 18 22:59:38 2000 -->
Status as of 10:40 pm 18 Sep 2000: 
 
<P> We got a rack protection trip on SVXSE1 = unused SE top earlier this evening, see <A HREF="/cgi/elog/elog.pl">CDF E-Log -- Eve shift. Mon Sep 18, 2000</A>.</P> 
 
Checked out system in emulation mode, then tried to run with CDF clock --> no good, timing probably still not right.  Abandoned attempt to run with RC and switched to running standalone.  Were not able to turn on any of the power supplies except for West 2, despite having enabled both the East and West interlocks via Steve B.'s new IFIX displays.  Therefore, just took data for 
West 2 as an exercise. 
 
West wedge 3 keeps appearing and disappearing (this is the one that is daisy-chained with the ISL).  Probably we should not daisy-chain it. 
 
Lots of things to fix tomorrow: 
<UL> 
<LI> CAEN enables and/or interlock code for SVX II wedges</LI> 
<LI> Timing of CDF clock </LI> 
<LI> Remove daisy-chaining (will disable ISL unless we get more controllers) or figure out why daisy-chaining the CAEN enables doesn't work (requires access)</LI> 
<LI> Rack protection trips (flaky SVX SW bottom, hard trip on unused SVX SE top)</LI> 
</UL> 
 
For more, see hardcopy silicon logbook.
<!-- Author: Alan Sill and Mary Bishai -->
<!-- Comment: Tue Sep 19 09;20;16 comment by...SCN -->
1) SE TOP has no Rack Protection and will not be powered for
the commissioning run.
2) What does "failed w/ RC" mean?  Emulating Clock or not, which
is possible with RC and standalone...
<!-- Date: Mon Sep 18 23:06:21 2000 -->
We take it back about the daisy-chaining on the SW side.  What was taking it down was apparently a rack protection trip -- the flaky fan in SW bottom seems to finally have failed.  (Yet another thing to fix in an access!).
<!-- Author: Alan and Mary -->




<!-- Date: Tue Sep 19 09:23:33 2000 -->
<pre>Switched on SVSW2 (SW Bottom) which is reported to have fan failures.  It has been up for about 15 minutes, will report 
when it fails again...</pre>
<!-- Author: SCN -->


<!-- Date: Wed Sep 20 02:11:36 2000 -->
<pre>What happened today: 
 
1) SRC clock problems fixed by new version of master clock which synchs 
all clock signal edges to 53 MHz. SRC was sending spurious 
halt-recover-runs for no reason. 
 
2) RC coldstart of fibs failed in daqmsg.java from messanger.java. This is 
where we are trying to send HDI download bitstreams as messages to 
fibs. S. Nahn will debug this in the morning. 
 
3) Could run successfully with SEVB + DAQ in stand alone mode but rate is 
extremely slow. svxcrate_checkFormat process that reads VRBs in VME crate 
(much faster than Java control) failing with both DEMS and B4 - suspect 
user error in properly starting process. 
 
4) Problem with histograming using test stand code when have more than 2 
Fibs. First time we have tried to read this many fibs out. Have to spend 
some time debugging Histo.c. 
 
5) Dropping bit 3 on HDI9 West side. Saw this problem when CPCs were hot 
but we are running very cold now. Need to look at light output next access 
or try raising DOIM 5V by 100mV. 
 
6) Took following runs on West wedge 2 HDI0,1,2 in complete teststand 
standalone mode: 
 
scan160 
laser161 
cal168 
 
On B4 area in fcdfsgi2 with a .readme for each run. 
 
7) No SVX power trips or interlock failures for most part of the 
evening. Also no rack failures on SW. 
 
8) Beam was on and off so couldn't bias ladders for more detailed studies. 
 
9) Noticed when we process non-fatal errors on SRC that it continuosly 
tries to reset VRBs (every few microsecs). Need to investigate why unless 
its a known problem. 
 
 
</pre>
<!-- Author: Mary Bishai -->


<!-- Date: Wed Sep 20 10:35:35 2000 -->
Cooling system work: 
 
Noticed that the measurement provided by the differential pressure transducer of the water level in the air separator has been dropping slowly over the past few days even though the actual coolant level (as indicated by the visual sight gauge) seems to be more or less stable.  This transducer yields a calculated height of about 8.8 inches now, was 9 inches yesterday and 9.8 inches on Sep. 17th.  The actual level in the tank is about twice that amount.  Rich Stanek is now working on this to see whether this can be fixed, so the measured air sep tank water level will not be reading correctly for the next hour or so.  (Should not trip cooling flow.) 
<!-- Author: Alan Sill -->


<!-- Date: Wed Sep 20 10:38:06 2000 -->
<pre>Rack protection for SW bottom fan failure happened again, 
apparently at about 4:00 am.  Steve and I reset it at about 
10:00 am.</pre>
<!-- Author: Alan Sill -->


<!-- Date: Thu Sep 21 00:57:02 2000 -->
<pre>Rebooted SVX crates (for sevb), CSL had to be restarted, sevb very 
unstable in rc. Despite that here is what I found out: 
 
1) Read out only b0fib04 east wedge 2 - this is a completely good wedge. 
 
2) Tried both partition 3 and 4 in rc. Same behaviour 
 
3) Src sends lots of triggers - up to 200 - 300 at a time sometimes 
readout from b0svx03 crate at 35 Hz then the vrb in b0svx03 that we are 
reading out raises scan busy (not read busy) and system hangs - readout 
from crate ceases. 
 
4) Seems coupled to having sevb server side actually connected to 
CSL. When csl was down I could continue reading out 35Hz at a time on 
b0svx03 without going into scan busy. 
 
5) When I end then abt+reset and partition again - sevb is off. I have to 
go to proxy stop and restart to get going again - why. 
 
Take all this with a grain of salt .... I am not quite coherent sometimes 
these days. I will leave the power off. Alan now knows how to restart PS 
GUI so he can switch power on for Steve to play (if Steve is not bedridden). 
 
</pre>
<!-- Author: Mary Bishai -->