<!-- Title: 20:27:41  Sun May  7 2000 -->
<!-- Crewchief: R.J. Tesarek -->
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<!-- Notes: -->
<pre>New File for new week.</pre>


<!-- Date: Sun May 7 20:34:43 2000 -->
<BR><B>Software upgrade:</B> 
<BR>Upgraded ckcrate.xpt software to improve error reporting and to better integrate with automatic checkout scripts.  Also introduced new scripts (ckcentral, ckwall) to check all the central and wall crates and provide a brief summary (ok, pedestal, calibration, FRAM problems). 
<p> 
Tried to log into SW arch crates without success. Tried looking into problems with ethernet, but labels on optical fibers between 1st and 3rd floor are inconsistent.  Crate reset also doesn't appear to work correctly.  Wait until Monday to address these problems. 
<br>  
<!-- Author: R.J. Tesarek -->


<!-- Date: Sun May 7 21:00:06 2000 -->
<pre><br><b>Motor Generator 2:</b> 
<br>MG set 2 appears to have tripped ;off sometime between 20:00 and now. 
<br></pre>
<!-- Author: R.J. Tesarek -->


<!-- Date: Mon May 8 08:41:13 2000 -->
<br><b>Motor Generator 2:</b> 
<br> Turned on motor generator set #2 at 0815.  All crates came up with the PIE supplies in fault.  Reset the faults by power cycling the supplies at the circuit breaker for each arch/wall. 
<br>
<!-- Author: R.J. Tesarek -->


<!-- Date: Mon May 8 09:39:30 2000 -->
<br><b>EndWall Monday Maintainance:</b> 
<br> In order to check the ADMEMs, turn off the HV to the endwalls.  This removes problems in calibration/pedestal checking due to large pedestals and pedestal RMS. 
<p> 
Use the new script to determine the status of the EndWalls today.  Below is the first report from ckwall: 
<pre> 
/cdf/people1/cdf_cal/admem/tmp/b0ecal00.tmp: ### Crate: b0ecal00 -- All ok! 
/cdf/people1/cdf_cal/admem/tmp/b0ecal01.tmp: ### Crate: b0ecal01 -- All ok! 
/cdf/people1/cdf_cal/admem/tmp/b0ecal02.tmp: ### Crate: b0ecal02 -- All ok! 
/cdf/people1/cdf_cal/admem/tmp/b0ecal03.tmp: ### Crate: b0ecal03 -- All ok! 
/cdf/people1/cdf_cal/admem/tmp/b0ecal04.tmp: ### Crate: b0ecal04 -- All ok! 
/cdf/people1/cdf_cal/admem/tmp/b0ecal05.tmp: ### Crate: b0ecal05 -- Pedestal problem(s)  
/cdf/people1/cdf_cal/admem/tmp/b0ecal06.tmp: ### Crate: b0ecal06 -- Calibration problem(s)  
/cdf/people1/cdf_cal/admem/tmp/b0ecal07.tmp: ### Crate: b0ecal07 -- Calibration problem(s) 
</pre> 
Only crates 5,6,7 have any problem.  
<ul> 
  <li><b>b0ccal05:</b>  Known shorted channel in transition board. 
  </li> 
  <li><b>b0ccal06:</b>  ADMEM slot 19, chan=4,10 have large sigma (offsets), 1.72(capid=0,range=5), 14.28(capid=0,range=0), respectively.  ADMEM slot=21, chan=7 shows no fitting (0) 
  <br>==> Problems are all upstream of the ADMEM and vanish when the transition boards are unplugged from the ADMEM. 
  </li> 
  <li><b>b0ccal07:</b>  ADMEM slot=20, chan=3 has large sigma(offset) and sigma(slope)/slope for 1.60(capid=1,range=0), 0.0032(capid=1,range=0), respectively.  ADMEM slot=17, chan=6 has a large sigma(offset) 26.0(capid=0,range=0). 
  <br> ==> Problems are upstream of the ADMEM, they go away when the transition board is removed. 
  </li> 
</ul> 
The problems observed in crates b0ecal06,07 should be investigated further. 
<br>  
<!-- Author: R.J. Tesarek -->
<!-- Comment: Tue May  9 18;11;10 comment by...R.J. Tesarek -->
The crate references should be "ecal" rather than "ccal"
<!-- Date: Mon May 8 11:09:58 2000 -->
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<B>Weekly Central Crates checkings:</B> 
<BR><B></B>&nbsp; 
<UL> 
<LI> 
<B>b0ccal00: </B>ok.</LI> 
 
<LI> 
<B>b0ccal01: </B>ok.</LI> 
 
<LI> 
<B>b0ccal02: </B>not responding (Walter Stuermer is working on it)</LI> 
 
<LI> 
<B>b0ccal03: </B>not responding (Walter Stuermer is working on it)</LI> 
 
<LI> 
<B>b0ccal04: </B>not responding (Walter Stuermer is working on it)</LI> 
 
<LI> 
<B>b0ccal05: </B>not responding (Walter Stuermer is working on it)</LI> 
 
<LI> 
<B>b0ccal06: </B>ok.</LI> 
 
<LI> 
<B>b0ccal07: </B>ok.</LI> 
 
<LI> 
<B>b0ccal08: </B>ok.</LI> 
 
<LI> 
<B>b0ccal09: </B>ok.</LI> 
 
<LI> 
<B>b0ccal10: </B>off.</LI> 
 
<LI> 
<B>b0ccal11: </B>off.</LI> 
 
<LI> 
<B>b0ccal12: </B>off.</LI> 
 
<LI> 
<B>b0ccal13: </B>off.</LI> 
 
<LI> 
<B>b0ccal14: </B>ok.</LI> 
 
<LI> 
<B>b0ccal15:</B></LI> 
</UL> 
<B>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </B>*******************&nbsp;&nbsp; 
Start of WARNING messages&nbsp;&nbsp; ************** VALUE&nbsp;&nbsp;&nbsp; 
CAP RANGE** 
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * ADMEM=16 QIE= 6 Warning 
10: Slope low&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
(&nbsp;&nbsp;&nbsp; 1.5739) ( 1) ( 1) * 
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; *******************&nbsp;&nbsp; 
End of WARNING messages&nbsp;&nbsp; ************************************* 
<UL>&nbsp; 
 
<P>*********************************************** 
<BR>Total Warnings: 1. 
<BR>Total Failures: 0. 
<BR>***********************************************<B></B> 
 
<P>All ok except this warning.</UL> 
 
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<!-- Author: Ph.Gris -->


<!-- Date: Mon May 8 15:45:35 2000 -->
<br><b>b0ecal06:</b> 
<br>Fixed shorted channel in transition board (slot=19,chan=0). Remaining problems are as follows: 
<pre> 
*******************   Start of FAILURE messages   ************** VALUE    CAP RANGE** 
* ADMEM=19 QIE=10 Failure 14: Sigma(offset) too big          (    7.3611) ( 0) ( 0) * 
* ADMEM=21 QIE= 6 Failure 14: Sigma(offset) too big          (   12.1021) ( 0) ( 0) * 
*******************   End of FAILURE messages   ************************************* 
</pre> 
Both of these problems disappear when the respective transition boards are unplugged.  This means that the problem is likely due to a PMT (the transition boards appear to be fine). 
<br>
<!-- Author: R.J. Tesarek -->


<!-- Date: Mon May 8 15:58:01 2000 -->
<table><tr><td><a href=/elog/notebooks/wedge/Mon_May__8_2000_155749.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>Figure 1:  Pedestal distributions for b0ecal06, ADMEM  slot=19, chan=10.  Note that there are no overflow or underflow events in any of these histograms.  Transition  boards are plugged in and HV is applied to the PMTs.  These  distributions are to be compared with Figure 3.</a></td></tr></table>
<!-- Author: R.J. Tesarek -->


<!-- Date: Mon May 8 15:59:40 2000 -->
<table><tr><td><a href=/elog/notebooks/wedge/Mon_May__8_2000_155934.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>Figure 2: Pedestal distributions for b0ecal06, ADMEM  slot=21, chan=6. Note that there are no overflow or underflow events in any of these histograms. Transition  boards are plugged in and HV is applied to the PMTs. These distributions are to be compared with Figure 4. </a></td></tr></table>
<!-- Author: R.J. Tesarek -->


<!-- Date: Mon May 8 16:02:41 2000 -->
<table><tr><td><a href=/elog/notebooks/wedge/Mon_May__8_2000_160238.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>Figure 1: Pedestal distributions for b0ecal06, ADMEM  slot=19, chan=9. Note that there are no overflow or underflow events in any of these histograms. Transition  boards are plugged in and HV is applied to the PMTs. These distributions are to be compared with Figure 1.   </a></td></tr></table>
<!-- Author: R.J. Tesarek -->
<!-- Comment: Mon May  8 16;03;16 comment by...R.J. Tesarek -->
This is really Figure 3.


<!-- Date: Mon May 8 16:04:34 2000 -->
<table><tr><td><a href=/elog/notebooks/wedge/Mon_May__8_2000_160426.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>Figure 4: Pedestal distributions for b0ecal06, ADMEM  slot=21, chan=7. Note that there are no overflow or underflow events in any of these histograms. Transition  boards are plugged in and HV is applied to the PMTs. These distributions are to be compared with Figure 2. </a></td></tr></table>
<!-- Author: R.J. Tesarek -->


<!-- Date: Mon May 8 16:10:40 2000 -->
<table><tr><td><a href=/elog/notebooks/wedge/Mon_May__8_2000_161031.ps align=top><img src=/elog/gifs/ghost64.gif  width='56' align='top'></td><td>Figure 5: Pedestal distributions for b0ecal06, ADMEM  slot=19, chan=10. Note that there are no overflow or underflow events in any of these histograms. Transition  boards are UNPLUGGED.  These distributions are to be  compared with Figure 1.   - R.J. Tesarek </a></td></tr></table>
<!-- Author: R.J. Tesarek -->


<!-- Date: Mon May 8 16:28:55 2000 -->
<br><b>b0ecal06 study:</b> 
<br> Perform a quick study of pedestal events in b0ecal06.  Recall that ADMEMs slot=19,chan=10 and slot=21,chan=6 show problems in their respective calibrations which disappears when the transition boards are unplugged.  The plots show that the pedestals are not unreasonable and are uneffected by the PMT signals.  
<br>
<!-- Author: R.J. Tesarek -->



<!-- Date: Tue May 9 18:21:10 2000 -->
<br><b>SW arch, power outage:</b> 
<br>This morning the SW arch was found to have tripped off around 2320 last night.  The reason for the trip was due to a -100F temperature reading for the lowest temperature probe in CASEB-2.  The faulty reading came from a bad connection at the crate.  Peter Wilson, Bill Wickenberg and I fixed the problem and the arch was reset. 
<br>
<!-- Author: P.J. Wilson, W. Wickenberg,R.J. Tesarek -->


<!-- Date: Tue May 9 19:03:29 2000 -->
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<UL> 
<LI> 
<B>NW arch, Calcard:</B></LI> 
</UL> 
Attempt to make some source calibrations (EM and HAD). Lost connections 
with the crates a few times. Had a lot of problems with the software event 
builder. Then b0dau30 crashed. Then Oracle did not come back: 
 
<P>*** FATAL ERROR opening Hardware Database *** 
<BR>java.sql.SQLException: ORA-01033: ORACLE initialization or shutdown 
in progress 
 
<P>Fetching from HdwDb... java.lang.NullPointerException 
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; at hdwdb.BoardType.fetchAll(BoardType.java:91) 
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; at hdwdb.HdwDb.fetchAll(HdwDb.java:184) 
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; at rc.rcBase.&lt;init>(rcBase.java:84) 
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; at rc.rcGUI.&lt;init>(rcGUI.java:121) 
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; at rc.rcGUI.main(rcGUI.java:48) 
<BR>&nbsp; 
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<!-- Author: The Calcard team -->


<!-- Date: Wed May 10 09:20:37 2000 -->
<br><b>b0ecal03 - Transition board:</b> 
<br> Fixed intermittant short in transition board for slot=18,chan=11. 
<br> 
<br><b>b0ecal05 - Transition board:</b> 
<br>Looked into problems with short in transition board for slot=16,chan=2 and found that the short appears to be at the PMT end.  I measure 16 ohms between shield and center conductor on the RG174 at the transition board. 
<br>The apparent short in slot=18,chan=11 no longer appears.  The solder joints at the transition board look quite good.   The resistance between the RG174 center conductor and shield is greater that 10M ohm.  Further, the channel checks out ok when pedestals are taken.  More investigation is warrented to determine why this channel made it on the list of bad transition boards. 
<br>
<!-- Author: R.J. Tesarek -->


<!-- Date: Wed May 10 19:45:27 2000 -->
<br><b>SouthWest arch:</b> 
<br>Replaced a blown F3(+5V analog) fuse on the ADMEM in slot 20. 
<br> 
<br>Running the standard crate checkout yields the following results: 
<ul> 
  <li><b>b0ccal02:</b>  All ok! 
  </li> 
  <li><b>b0ccal03:</b>  All ok! 
  </li> 
  <li><b>b0ccal04:</b>  Problems loading FRAM for ADMEM slot=21,chan=16.  This problem occured after loading the FRAM twice.  When I try to calibrate and load this channel alone the 
problem persists. 
  </li> 
  <li><b>b0ccal05:</b>  Pedestal for ADMEM slot=16, chan=0 is 960 counts. 
  </li> 
</ul> 
<br>Since both of these problems are in the lower crates, I will attack them both early tomorrow morning. 
<br> 
  
<!-- Author: R.J. Tesarek -->


<!-- Date: Wed May 10 19:47:51 2000 -->
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<UL> 
<LI> 
<B>NW arch, Calcard:</B></LI> 
</UL> 
Oracle is now back. Could not choose a partition from b0dau30, though. 
Tried from b0dap00. Have some bus errors with Calcard in b0ccal06 (no 3). 
<BR>Made a had source calibration. Had some 0 in the L2 buffers for b0ccal06 
and b0ccal07. QIE calibrated b0ccal06. Seems to cure the problem. 
<BR>Successfully calibrated EM and HAD calorimeters. The files are located 
on the following area: 
<BR>/mdc1/csl/04/A20000510190657.test ---> EM 
<BR>/mdc1/csl/04/A20000510193934.test ---> HAD 
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<!-- Author: The Calcard Team -->


<!-- Date: Thu May 11 09:04:30 2000 -->
<br><b>b0ccal05:</b> 
<br>Investigating pedestal problem observed yesterday.  Unplug transition board and problem persists.  Swap out the CAFE card 
and the problem disappears.  Everything is ok after the CAFE swap.  Below is the new crate map. 
<pre> 
 In Slot2   IDPROM = 0127 001 TRACER__V2.1A           
 
 In Slot7   IDPROM = 005............................. 
 In Slot8   IDPROM = 0.0............................. 
 In Slot9   IDPROM = 0.0.7.....e...................O. 
 
 In Slot16   IDPROM = 0208 003 ADMEM_V4.0          470 
 In Slot17   IDPROM = 0241 003 ADMEM_V4.0          470 
 In Slot18   IDPROM = 0214 003 ADMEM_V4.0          460 
 In Slot19   IDPROM = 0227 003 ADMEM_V4.0          460 
 In Slot20   IDPROM = 0039 003 ADMEM_V4.0          470 
 In Slot21   IDPROM = 0078 003 ADMEM_V4.0          470 
 
QIE ID table: 
QIE    ADMEM: 16      17      18      19      20      21      
  0          2470    4935     786     773     686     849 
  1           903    4662    5929    3231    6238    4423 
  2           704    1951    6381    5469    6232    6558 
  3          5769    6101    6319    3285     999     770 
  4           730    4611    5898    3315    6296     687 
  5          5789    3351    6405    5194    1141    4365 
  6          4314    4708    3387    1961    4321     728 
  7           841    1842    3224    3370    6240     748 
  8           941    3289    5286    5226     996    1040 
  9          1150    1971    3334    5236     921    4513 
 10          1013    3161    5455    2081    1038     837 
 11          4285    3150    3265    3220     684    6446 
 12          1122    4727    5333    5224    1106    6329 
 13          1109    5207    2029    3343     992     917 
 14          6216    1983    5266    3269     741    6480 
 15          6382    6102    3307    6367     880    4441 
 16          4210    4617    3384    3248    1016    1117 
 17          6244    3435    1868    5278    1077     988 
 18          6191    3392    3205     916     776    1096 
 19          6361    3202    3164    5927    1143    5785 
</pre>
<!-- Author: R.J. Tesarek -->


<!-- Date: Thu May 11 10:37:19 2000 -->
<br><b>b0ccal04:</b> 
<br>Investigating FRAM problem observed yesterday (ADMEM slot=21, chan=16).  Swap out CAFE card and the problem persists.  Swap CAFE cards chan=16 <--> chan=17.  Problem persists in chan=16. 
Swap CAFE cards back to their original positioins and then swap CAFE cards chan=16 <--> chan=15. Problem persists.  At this point, Walter Stuermer arrives and wants to finish his tests.  Postpone debugging until after his tests are complete. 
<br>
<!-- Author: R.J. Tesarek -->


<!-- Date: Thu May 11 11:43:22 2000 -->
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<UL> 
<LI> 
<B>NW arch, Calcard</B></LI> 
</UL> 
Yesterday put the new calcard code in the "official" area. Tried it this 
morning. Seems to work (LED). 
<BR>Had some problems with partition, though: had to detach partition after 
abort. 
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<!-- Author: Ph.Gris -->


<!-- Date: Thu May 11 12:36:29 2000 -->
<br><b>b0ccal04:</b> 
<br>Swap ADMEM and find problem with FRAM in ADMEM slot=21, chan=19.  Swap CAFE card and all is ok.  Configure the crate for central and download the appropriate ET look-up tables.  
<br> 
<br>Here is the new crate map. 
<pre> 
 In Slot2   IDPROM = 0138 001 TRACER__V2.1A           
 
 In Slot5   IDPROM = 0006 007SMXR_VA ................ 
 
 In Slot7   IDPROM = 0.0.>........................... 
 In Slot8   IDPROM = 0.0.3.0.5...D.....U............. 
 In Slot9   IDPROM = 0.0.........D._............. ... 
 
 In Slot16   IDPROM = 0200 003 ADMEM_V4.0          470 
 In Slot17   IDPROM = 0201 003 ADMEM_V4.0          470 
 In Slot18   IDPROM = 0199 003 ADMEM_V4.0          470 
 In Slot19   IDPROM = 0064 003 ADMEM_V4.0          470 
 In Slot20   IDPROM = 0097 003 ADMEM_V4.0          470 
 In Slot21   IDPROM = 0262 003 ADMEM_V4.0          470 
 
QIE ID table: 
QIE    ADMEM: 16      17      18      19      20      21      
  0          1017    1027    4410    1654    5755    3140 
  1          6565    6463    6332    1669    5547    5235 
  2          6501    6532    4167    1710    5717    3419 
  3          4127    4447    6444    1155    1012    4800 
  4          6159    6518    6569    6372    1073    1794 
  5          4176    6138     991    6530    1110    5307 
  6          1761     924    5790    6579     968    6106 
  7          6528    1129     893    4305    1033    3534 
  8          1071    1098     886     982    1039    3169 
  9          6594    1752    6461     942     868    6088 
 10          6141     769    6470    4221    1135    5220 
 11          4435    6280    1670    1001     785    5427 
 12          6593    6442    6572    6128    4061    5363 
 13          6415    6578    6222    6146     697    3552 
 14          6190    1775    1812    5628    6409    1996 
 15          4204     989    4197     733     926    1995 
 16          4509    1133    4160    4223     720    4544 
 17          1146    6276    6288     685    1070    5404 
 18          6426    6494    6421    6344     731    4593 
 19           892    6456    6583     915    1108    2157 
</pre> 
I can now sign off on the initial ADMEM checkout of the SW arch. 
The last thing to do before releasing the arch to others is check the trigger outputs for at least one ADMEM in all crates except for b0ccal04.  In b0ccal04, we want to check 2 ADMEMs.  First the newly installed ADMEM and then another ADMEM chosen at random. 
<br>
<!-- Author: R.J. Tesarek -->


<!-- Date: Thu May 11 15:48:00 2000 -->
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<UL> 
<LI> 
<B>NW arch, Calcard:</B></LI> 
</UL> 
From the yesterday run and thanks to Run I informations provided by Steve, 
Youngdo computed the voltages so as to adjust the pmt gains at their Run 
I value. Changed the voltages on one wedge (21W) and made an EM source 
calibration to observe the effects. The file is: 
<BR>/mdc1/csl/04/A20000511153716.test 
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<!-- Author: The Calcard Team -->


<!-- Date: Fri May 12 18:21:21 2000 -->
<pre><br><b>SW arch Trigger tests:</b> 
Finished off the trigger tests for the SW arch. 
<br></pre>
<!-- Author: R. Erbacher -->


<!-- Date: Fri May 12 18:23:18 2000 -->
<pre><br><b>E wall power fault:</b> 
<br>The rack protection for the East wall tripped off today at approximately 1600.  The DMACS system did not ascribe a reason for the trip.  Power will remain off for the E wall until experts can address the problem on Monday. 
<br> 
</pre>
<!-- Author: R.J. Tesarek -->


<!-- Date: Fri May 12 18:25:57 2000 -->
<br><b>PEI faults b0ecal02, b0ecal03:</b> 
<br>Discovered a fault on V4 (+5V analog) for crates b0ecal02.  The fault was reset and the same state reappeared approximately 15 min later.  Reset again.  If a third fault occurs, the crate should be powered down. 
<br>  
<!-- Author: R.J. Tesarek -->


<!-- Date: Sat May 13 23:44:02 2000 -->
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