<!-- Title: Day shift. Wed Sep 27, 2000 -->
<!-- Leader: Bill Carithers -->
<!-- Ace: Mike Kirby -->
<!-- Co1: Hiro Matsunaga -->
<!-- Co2: Heather Gerberich -->
<!-- Co3: &nbsp; -->
<!-- Co4: &nbsp; -->
<!-- Co5: &nbsp; -->
<!-- Notes: -->
<pre>Run plan for Day shift: 
CLC min bias trigger studies (Ming, Greg, Alexei) 
L2 integration (Monica) 
L3 EVB studies (Ilya) 
Endwall crate (Rick) 
</pre>


<!-- Date: Wed Sep 27 09:12:47 2000 -->
<pre>SVX rad information (near) beginning of shift: 
West Inner BLM		.4461 
West Outer BLM		.476 
East Inner BLM		16.89 
East Outer BLM		22.8</pre>
<!-- Author: Bill Carithers :: (run NA) -->


<!-- Date: Wed Sep 27 09:26:58 2000 -->
<pre>Ran a QIE calibration on all of the cal crates (clc not included) 
and had a plethora of erros.  QIEs 0->18 on Admem 21 in pcal00 
gave this error: 
 
b0pcal00:  Readout_Calib : 9:11:31 AM 
 -> ADMEM=21 QIE=0 Fial 25: Self calib Fail (0.0) (0) (0) 
 
where the QIE number is all of the above listed values. 
 
also, b0pcal00 Admem 14,QIE=7 had a Fail 10, and didn't fit. 
 
pcal02 also had the same problem as pcal00 where ADMEM 19 had all 
of the QIEs (0-19) with a self calib failure. 
</pre>
<!-- Author: Kirby :: (run 99621) -->
<!-- Comment: Wed Sep 27 09;44;48 comment by...Kirby -->
Contacted Rick Tesarek, and we found the three known problems that we should have found.  Otherwise, everything looks fine.


<!-- Comment: Wed Sep 27 10;00;21 comment by...Kirby -->
Looking at the DBANA for this run, we saw that wedges 15,16,and 17 for both EM and HAD were completely missing.  This corresponds to clock problems that Rick has seen in crate b0ccal05.  We should add either warning codes in the front end, or instructions to the ACE to check in DBANA for such things.  Otherwise, they will slip by.
<!-- Date: Wed Sep 27 09:58:12 2000 -->
LED Calibration for CEM.  Look in the binder for the list of bad channels.  Note that all of 15W, 16W, 17W, and 18W were listed bad.
<!-- Author: Kirby :: (run 99622) -->



<!-- Date: Wed Sep 27 10:23:20 2000 -->
Took two Xenon calibrations for CEM.  The two runs for in order to diagnose a problem with the calibration consumer generating both LED and XEF entries in the online_prod database.  The list of bad channels is in the folder, noting that again we saw that ccal05 ain't working.
<!-- Author: Kirby :: (run 99625,99626) -->
<!-- Comment: Wed Sep 27 11;03;28 comment by...rvidal -->
<pre>my test of new commenting options</pre>


<!-- Date: Wed Sep 27 12:49:10 2000 -->
<pre>In order to more extensively diagnose and test COT TDC crates, 
started to  calib continuous runs this morning.  The first run 
contained only b0htdc00 which was filled with 17 tdcs, a TRACER 
and a 1-3 fanout.  The crate was setup to use globalDone for 
readout, and appears to have no real problems.  Currently, the TS 
has sent 18,553,290 triggers.  I'll leave this running as long as 
possible just to see what happens. 
	The other run was to determine if once the TDCs that 
suffered from "VME non-response" were removed, if the crate would 
then remain stable.  Here's the list of crates and readout 
status: 
 
crate	slots			readout problem 
-----	-----			-------------- 
01	2 -> 16         	17 not responding 
02	2 -> 16 
03	7 -> 15, 17 -> 21 
07	6,7,9 -> 13,15, 18->21  8,14,16,17 not responding 
08	2 -> 17 
11	4->6,8->18 
12	4->18			have to use localDone, ???? 
13	5->19 
18	4,6->16,18,19		5,17 
19	6->11			not sure what's missing 
 
The run has been going for 242,500 triggers so far, and doesn't 
look like it's gonna stop.</pre>
<!-- Author: Kirby -->
<!-- Comment: Wed Sep 27 14;59;46 comment by...Kirby -->
The run on the full set of crates timed out after 248157 triggers.  The crate that died was b0cot19, but I was unable to diagnose the problem as VISIONdemo couldn't map the crate at all.  


<!-- Comment: Wed Sep 27 15;09;32 comment by...Kirby -->
The run with the hadron TDC crate was finally ended with 38.5
million triggers and no errors.  we ended so that Steve Nahn could test the SVX.
<!-- Date: Wed Sep 27 15:04:41 2000 -->
<pre>We took the SVT and included it into a runSet "ACE_MEDIUM_SVT" 
and sent data through the VRBs, hardware event builder, and L3. 
</pre>
<!-- Author: Kirby :: (run 99649, 5758 events) -->



<!-- Date: Wed Sep 27 15:24:52 2000 -->
<pre>Interem release 3.8.1,  
for testing in preparation for release 3.9.0,  
is installed on b0dap30. 
 
3.8.1 will be installed on b0dau30 this afternoon, 
as soon as the build had finished on fcdfsgi2. 
 
We will try to run the consumers from this frozen release. 
</pre>
<!-- Author: Frank Chlebana -->


<!-- Date: Wed Sep 27 16:26:19 2000 -->
<font color=red>Shift Summary: </font><pre>Ran calibrations--see above for details (many CEM failures) 
Included SVT as test 
Still working on CLC (no conclusions yet) 
SVX radiation at end of shift: 
West inner		.4737 
West outer		.5274 
East inner		17.05 
East outer		22.91</pre> 
<br><b>End of Shift Numbers</b>
<table><tr><td width=60% align=left>
<b>CDF Run II <p></b>                       
<pre>
Runs                   thru 99657
Delivered Luminosity   0  pb-1
Acquired Luminosity    0  pb-1
Efficiency             0
   
</td></tr></table></pre>
<!-- Author: Bill Carithers -->