<!-- Title: Eve shift. Fri Oct  6, 2000 -->
<!-- Leader: Yoshi Seiya -->
<!-- Ace: Aaron Dominguez -->
<!-- Co1: Simon Waschke -->
<!-- Co2: Hideaki Takano -->
<!-- Co3: Doug Benjamine (SOS) -->
<!-- Co4: &nbsp; -->
<!-- Co5: &nbsp; -->
<!-- Notes: -->
<pre></pre>


<!-- Date: Fri Oct 6 16:22:43 2000 -->
<pre>Collisions expected have been postponed to Sunday. 
We are recovering from HEVB problems (?) 
CSL is still having some problems.</pre>
<!-- Author: Y. Seiya -->


<!-- Date: Fri Oct 6 16:43:46 2000 -->
<pre>Steve H, Robin, Mike L went down to cycle  
all the WEST crate power supplies.</pre>
<!-- Author: Y. Seiya -->


<!-- Date: Fri Oct 6 16:46:55 2000 -->
<pre>Ivan working on HEVB/L3.  L3 was complaining about a failed 
tcl file distribution. 
</pre>
<!-- Author: Aaron Dominguez -->


<!-- Date: Fri Oct 6 16:48:09 2000 -->
<pre>The problem in "setup cdfsoftb0" as recorded by 
the previous CO's: Pasha called and is looking  
into it.</pre>
<!-- Author: Y. Seiya -->
<!-- Comment: Fri Oct  6 19;36;40 comment by...Pasha Murat -->
consumers are running OK, use 
>setup cdfsoftb0
to get the right environment. If event display stops on ROOT prompt, use
root[..] continue(1)
command to get GUI popped up.
<!-- Date: Fri Oct 6 16:48:40 2000 -->
<pre>Ivan says that there was a disk file full from log files. 
He cleaned it up and says that an automatic cleaner is in 
the works.</pre>
<!-- Author: Aaron Dominguez -->


<!-- Date: Fri Oct 6 17:35:53 2000 -->
<pre>Run 100604: 
 
Using HEVB.  Including pcal10 now. 
 
All consumers not working, but there is still a hot tower 
according to the trigger monitor.</pre>
<!-- Author: Aaron Dominguez :: (run 100604) -->


<!-- Date: Fri Oct 6 17:43:22 2000 -->
<pre>Run 100604: 
 
CSL display shows receiver is getting events, but findfile 
doesn't show the file is getting to disk 
</pre>
<!-- Author: Aaron Dominguez :: (run 100604) -->


<!-- Date: Fri Oct 6 17:53:34 2000 -->
<pre>WCAL02 recovered after power recycling.</pre>
<!-- Author: Y. Seiya -->


<!-- Date: Fri Oct 6 18:12:37 2000 -->
<br><b>Power cycling the west wall:</b><br> 
As noted in the morning log, I discovered that the b0wcal02 power 
supply had been in fault since about 11:30am on 10/5.  I discovered this 
due to a log entry from owl shift regarding calibration errors, so I appreciate the note.   
<p>It turns out, the only current way to reset that crate was 
to cycle the entire wall, COT, CAL, and all.  Buttons in iFix 
were promised earlier in the week (and exist in the plug) but 
have not been implemented. 
Steve Hahn, professor Ops, managed to cycle and reset the power 
(<i>with Sondra's --known as Shauna by Steve-- help</i>).  All of the 
cal crates came back up smootly and checked out ok.  We hope the 
same is true for the COT crates.  
<!-- Author: R. Erbacher, S. Hahn, M. Lindgren -->


<!-- Date: Fri Oct 6 18:14:48 2000 -->
<pre>Run 100611: 
 
Switched to partition 6 and data is now getting to disk. 
 
Look for hot towers now... 
 
Next run include scalars again and add SVX.</pre>
<!-- Author: Aaron Dominguez -->


<!-- Date: Fri Oct 6 18:34:04 2000 -->
<table><tr><td><a href=/cgi/elog/elog.pl?nb=2000&action=view&page=-262&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/elog.pl?nb=2000&action=view&page=-262  width='250' align='top'></td><td>This shows what happened when we attempted to recycle the  power on the west wall.  I first attempted to do this  following Sondra's (yes, Sondra's) recommendation that I  try setting the power permit to COSWB to FALSE.  Despite  following the right steps, it did not appear to change from TRUE to FALSE.  On some reflection (and calling up Sondra), we both thought this was a read-only variable.  We did not see the racks go red on the west wall.  However, Morris  Binkley then came in and said that he had seen the low voltage trip off, which is a sign of the 60 Hz momentarily turning off and on.  The worry is that the 400 Hz did the  same thing, and the TDCs were turned on and off in less than a minute.  With Sondra's help, we then tripped off the  racks by artificially setting one of the rack temps to 200 F.  This tripped all 60 and 400 Hz on the entire west wall. We then used the RESET button for the COxWx crates to turn them all back on.  These plots of the ON and FAULT state to seem to verify there was a brief OFF/ON transition before  we turned the crates OFF via the temperature, and ON via RESET.  As Robin said, b0wcal02 did get reset by the  recycling, and the last word from Bill Orejudos is that he sees no TDC problems except from b0cot06, which has given TRACER-VRB related problems before.  He is still looking at the COT crates.</a></td></tr></table>
<!-- Author: Steve Hahn -->


<!-- Date: Fri Oct 6 18:40:59 2000 -->
<pre>There is a dead L3 output node.  Restart L3. 
 
Trying to include SVX.  Can't cold start the FIBs. 
Tried a three times, still same problem. 
 
Remove SVX for the time being and try later tonight when 
Steve N is here.</pre>
<!-- Author: Aaron Dominguez -->
<!-- Comment: Fri Oct  6 21;29;21 comment by...SCN -->
I Fixed the Fibs- look<a href=/cgi/elog/det-system-elog.pl?nb=barrel4&action=view&page=14&anchor=21:26:55 target=_top> here </a>
<!-- Date: Fri Oct 6 18:46:46 2000 -->
<table border=0><td><tr><td bgcolor=#e0e030><pre>Steve Chappas came to load a special clock file that gives  
the BC marker only on the B0 marker.  This is for 1x8  
operation due on Christmas Day or possibly Sunday. 
YKK, Yoshi, Willis, Greg F, Steve Hahn have received 
training in how to switch to this special clock file. 
Serguei Borouv know's how to do this a well, of course. 
</pre></td></tr></td></table>
<!-- Author: Greg F -->


<!-- Date: Fri Oct 6 19:07:50 2000 -->
<pre>Run 100628: 
 
Taking data again.  Now with new clock. 
Released PCAL for sourcing. 
No SVX, COT or CLC. 
 
Next run, include CLC.</pre>
<!-- Author: Aaron Dominguez :: (run 100628) -->


<!-- Date: Fri Oct 6 19:09:40 2000 -->
<pre>The scaler server code (package STRUCK) has been updated to 
avoid opening the handles on each cold start which appears 
to be the source of a memory leak that has been trouble 
for this crate.  I have updated the code in the ups area 
so that it is automatically loaded on a reboot.  B0TSI03 
has been rebooted and the code appears to run fine in 
a stand alone partition and also now under ACE control.  </pre>
<!-- Author: Michael Schmidt -->


<!-- Date: Fri Oct 6 19:16:20 2000 -->
<pre>CMP/CMX/BMU HVs tipped off an hour ago. 
Doug said CMP/CMX did it twice before. 
I'm giving a 3rd try. They are brought 
up and OK right now.</pre>
<!-- Author: Y. Seiya -->


<!-- Date: Fri Oct 6 19:23:37 2000 -->
<br><b>Hot towers in plug:</b><br> 
Hadron phi=23 eta~16 showed a large number of triggers.  I translated this to pcal06 slot 15.  I looked at the FRAMs but 
things looked normal.  I recalibrated and downloaded anyways, 
but don't know yet if this will make the problem go away. 
<p>Em phi=17 eta=16-23 was also hot, which corresponded to  
the infamous pcal10 slot 18 (see this morning's log book entries).  This had had bad FRAMs loaded, and then looked like it 
had a blown fuse, and then now has recovered.  It contained 
0033 in each of the addresses I looked at, but I recalibrated 
and downloaded and now it looks normal.  I hope this fixes things.  I'm now giving the plug (late!) to Alexei to do sourcing.
<!-- Author: R. Erbacher -->



<!-- Date: Fri Oct 6 19:56:07 2000 -->
<pre>Looked at COT crates after endwall power was taken down. 
We seem to have lost the TRACER-TS link for b0cot06. 
Also, the TDC's in slot 9, b0cot09 and slot 19, b0cot18 
were removed from the bankSet. Both of these TDC's  
can be "recovered" with a bus reset but "drop out" during 
a run. I am not sure if these problems are related 
to the power being but, since one of the crates in question 
is on the east side and one on the west. Here is the 
list of COT crates for tonite: 
 
  all except b0cot00,04,05,6,15 
 
   make sure the b0cot09 and b0cot18 use the localDone! 
 
</pre>
<!-- Author: Bill Orejudos :: (run 100630) -->


<!-- Date: Fri Oct 6 19:57:27 2000 -->
<pre>Another note: DO NOT include empty COT crates when 
running COT Calibrations! For some reason it seems 
to prevent the constants from being written to the 
database. The cause of this is still being investigated. 
 
 
 
                                            </pre>
<!-- Author: Bill Orejudos -->


<!-- Date: Fri Oct 6 20:22:24 2000 -->
<pre>Plan (Steve): 
- 1930-2130(?) - Alex, plug sourcing 
	       - COMMISS_ 2 V5 40 without plug 
- Calibration 
- 2130-0030(?) - Satoru Uozumi, SMX code testing 
	       - COMMISS_ ... with plug 
</pre>
<!-- Author: Y. Seiya -->


<!-- Date: Fri Oct 6 20:32:47 2000 -->
<pre>Run 100633: 
 
FIB code recompiled.   
 
rc restarted.  Able to cold start FIBs! 
 
Getting VRB event mismatches from reformatter in SIXD bank.</pre>
<!-- Author: Aaron Dominguez :: (run 100633) -->


<!-- Date: Fri Oct 6 20:43:17 2000 -->
<pre>David was in around 8pm for SOS.</pre>
<!-- Author: Y. Seiya -->


<!-- Date: Fri Oct 6 20:47:30 2000 -->
<pre>Run 100636: 
 
Cleanup of EVB, and start again. 
 
Seeing errors about "Unable to find event 1025 for sending to L3" 
from eb17 and eb14. 
 
Also event 1025 has had a "load pending" for a long time. 
</pre>
<!-- Author: Aaron Dominguez :: (run 100636) -->
<!-- Comment: Fri Oct  6 21;04;39 comment by...AD -->
Same error with event 38185 and eb13.


<!-- Date: Fri Oct 6 21:23:03 2000 -->
<pre>Run 100636, 67.5k events: 
 
Nice long run with no VRB/reformatter errors. 
 
SVX was not biased, so data is not that useful, it's just 
nice that the run didn't stop. 
 
Include SVT now.</pre>
<!-- Author: Aaron Dominguez :: (run 100636) -->


<!-- Date: Fri Oct 6 21:29:19 2000 -->
<pre>Run 100640: 
 
(using partition 6) 
 
Included SVT.</pre>
<!-- Author: Aaron Dominguez :: (run 100640) -->



<!-- Date: Fri Oct 6 21:51:27 2000 -->
<pre>Run 100640, 47k events: 
 
Run finally ended with event id mismatch. 
 
It all started with "Unable to find event 34711 for sending" 
and then there is an event id mismatch on every event after 
that.</pre>
<!-- Author: Aaron Dominguez :: (run 100640) -->


<!-- Date: Fri Oct 6 22:09:10 2000 -->
<pre>Special Myron mode run to check L1 early. 
Running with commissioning_table_1, which 
is the zero bias (BC) trigger with a prescale  
of 1 (actually 2 now! -- this will be fixed in  
FRED firmware ...) 
------------------------------------------------ 
Ignore BC has been clicked.  
Run number = 100645 (0x18925) 
8,000 events. 
--------------------------------------------------</pre>
<!-- Author: Aaron, Greg, Michael :: (run 100645) -->
<!-- Comment: Sat Oct  7 11;08;12 comment by...Michael Schmidt -->
***** L1 Early Myron Mode is ready for prime time. *****

I have looked at the relationship between the contents
of the TSID and TFRD banks for these two Myron mode runs
and find that things are basically working as expected.  The
BC trigger is quite hot (36/159 * 7.6 MHz /2) so this
is at a higher rate than we have tried in the past
(the prescale was usually 1000 rather than 2).  There
are some errors at about the 1% level which I will document
shortly.  But for now I would claim that L1 Early is
ready for use (don't forget to ask for Ignore BC when
asking for L1 Early).  Note: Myron Mode L1 Normal will
have the triggered event in L2Buffer0 followed a sample
of the tail in Buffers 1,2,3.  Myron Mode L1 Early will
have the triggered event in L2 Buffer 1 with a sample
of the front porch in Buffer 0 and a sample of the tail
in Buffers 2 and 3.
<!-- Date: Fri Oct 6 22:09:18 2000 -->
<pre>Run 100645: 
 
See Greg's entry about run conditions. 
 
Strange thing is when I hit END RUN, I get an error from VRB 
about not getting an event: 
"Error reading VRB in slot 12 for event 8143. 
The VRB had no event."</pre>
<!-- Author: Aaron Dominguez :: (run 100645) -->


<!-- Date: Fri Oct 6 22:13:47 2000 -->
<pre>Normal myron mode run. 
2000 events. 
Run number 100647 (0x18927) 
Ignore early not clicked! 
------------------------------- 
</pre>
<!-- Author: Aaron :: (run 100647) -->
<!-- Comment: Sat Oct  7 13;41;37 comment by...Michael Schmidt -->
More information on the tests of the Myron mode
runs.  

For both the L1 Normal and L1 Early runs I find that a few
percent of the time we get 3 instead of 4 events in a row.
Looking in detail it appears that when this happens, it is
buffer 3 that is missing AND the the assignment of the L2
buffer numbers and Myron mode flags appears to be slipped
by one with respect to the FRED trigger and the appearance
of BC.  For example for L1 Normal we occasionally see TSID
bank report L2 buffer 0 and 1 without BC and buffer 2 with
BC and the FRED BC trigger failing the prescale.
No event is associated with a FRED trigger passing the
prescale and no event for buffer 3.  
We expect and usually see L2 buffer 0 with BC and FRED
trigger, L2 buffer 1 and 2 without BC, and L2 buffer 3 with
BC but the FRED BC trigger fails the prescale as expected.
<!-- Date: Fri Oct 6 22:22:51 2000 -->
<pre>Plug sourcing done. Plug crates back.</pre>
<!-- Author: Y. Seiya -->


<!-- Date: Fri Oct 6 22:29:06 2000 -->
<pre>Run 100648, 16k: 
 
Done timeout in SVT_TRACKING_01. 
</pre>
<!-- Author: Aaron Dominguez :: (run 100648) -->


<!-- Date: Fri Oct 6 22:31:48 2000 -->
<pre>Found two disagreements between S.O.S. "Knowledge Sheet". 
 
1. BABS reads 90 PSIG instead of 130 
2.  Solenoid cooldown setting and actual disagree (88 vs 62) 
by more than "a few degrees" 
 
Techs on 1st floor say this is okay so no further action is 
taken.</pre>
<!-- Author: David Saltzberg (SOS) :: (run 100648 (less in hex)) -->


<!-- Date: Fri Oct 6 22:46:21 2000 -->
<pre>Run 100649: 
 
Qie calibration (including CLC). 
 
During calibration many errors from clc about wrong event numbers 
Logged into b0clc00 and seeing this error (paraphrasing): 
	Tracer_enableDone: ... tracer done not set 
	event id not sequential 
	 
 
WCAL02 Fail 10: No fitting. 
 
Reset b0clc00 and try again.</pre>
<!-- Author: Aaron Dominguez :: (run 100649) -->
<!-- Comment: Fri Oct  6 22;51;05 comment by...AD -->
WCAL02 reporting a heap error.  Will reset it and try again.


<!-- Date: Fri Oct 6 22:57:43 2000 -->
<pre>Run 100651: 
 
Removed CLC from Qie calib. 
 
Again with the heap error from WCAL02. 
Reset it and remove it from the run config for Qie calib.</pre>
<!-- Author: Aaron Dominguez :: (run 100651) -->


<!-- Date: Fri Oct 6 23:01:06 2000 -->
<pre>Run 100652: 
 
Qie calib without WCAL02 or CLC. 
 
Successfully made it into the database.</pre>
<!-- Author: Aaron Dominguez :: (run 100652) -->


<!-- Date: Fri Oct 6 23:06:42 2000 -->
<pre>Run 100653, LED calibration: 
 
Successfully made it into the database.</pre>
<!-- Author: Aaron Dominguez :: (run 100653) -->


<!-- Date: Fri Oct 6 23:20:37 2000 -->
<pre>Run 100655: 
 
Xe calibration made it to database ok.</pre>
<!-- Author: Aaron Dominguez :: (run 100655) -->
<!-- Comment: Fri Oct  6 23;31;02 comment by...Y. Seiya -->
23E: known problem. 02W: IMON=0.


<!-- Date: Fri Oct 6 23:35:43 2000 -->
<pre>Run 100657, COT calibration: 
 
Had to reset COT17 on previous attempt. 
Slot 18 is in bank set, but the address of this card is always 0. 
 
Remove slot 18 from bank set and try again. 
</pre>
<!-- Author: Aaron Dominguez :: (run 100657) -->


<!-- Date: Fri Oct 6 23:40:10 2000 -->
<pre>Run 100660, COT calibration: 
 
COT17 giving error (which I see was in previous calib attempts too) 
about No valid header for TDC in slot 10. 
 
Try removing slot 10 and try again.</pre>
<!-- Author: Aaron Dominguez :: (run 100660) -->


<!-- Date: Fri Oct 6 23:50:06 2000 -->
<pre>Run 100663, COT calibration: 
 
After removing slot 10 from bankset of COT17, 
the calibration finished and made it to the database. 
 
COT calibrations sure are fun!</pre>
<!-- Author: Aaron Dominguez :: (run 100663) -->


<!-- Date: Fri Oct 6 23:59:29 2000 -->
<font color=red>Shift Summary: </font><pre>Did all the calibration just before the end of 
shift, did not really have time to investigate 
the results.</pre> 
<!-- Author: Y. Seiya -->