Release 8.1.02i - platgen EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: platgen -p xc2vp30ff1152-6 -lang vhdl -toplevel no -ti system -st
xst system.mhs 

Parse system.mhs ...

Read MPD definitions ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...

Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...
Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0x73e00000-0x73e0ffff) opb_dp_mem_1	plb->plb2opb->opb
  (0x73e20000-0x73e2ffff) opb_dp_mem_0	plb->plb2opb->opb
  (0x7d800000-0x7d80ffff) opb_dp_mem_1	plb->plb2opb->opb
  (0x7d820000-0x7d82ffff) opb_dp_mem_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 101 - 1
master(s) : 4 slave(s)

Check port drivers...

Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Modify defaults ...

Creating stub ...

Processing licensed instances ...
Completion time: 0.00 seconds

Creating hardware output directories ...

Managing hardware (BBD-specified) netlist files ...
opb_dp_mem (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Copying
(BBD-specified) netlist files.
opb_dp_mem (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Copying
(BBD-specified) netlist files.

Managing cache ...
ppc405 (ppc405_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:46 -
Copying cache implementation netlist
ppc405 (ppc405_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:63 -
Copying cache implementation netlist
jtagppc_cntlr (jtagppc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:69 - Copying cache
implementation netlist
proc_sys_reset (reset_block) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:76 - Copying cache
implementation netlist
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:92 - Copying
cache implementation netlist
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:101 -
Copying cache implementation netlist
plb2opb_bridge (plb2opb) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:109 - Copying cache
implementation netlist
opb_uartlite (rs232_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:122
- Copying cache implementation netlist
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:139 - Copying cache
implementation netlist
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:150 - Copying cache
implementation netlist
opb_intc (opb_intc_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:156
- Copying cache implementation netlist
dcm_module (dcm_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:167 -
Copying cache implementation netlist
opb_dp_mem (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Copying cache
implementation netlist
opb_dp_mem (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Copying cache
implementation netlist

Elaborating instances ...
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:150 - elaborating IP

Writing HDL for elaborated instances ...

Inserting wrapper level ...
Completion time: 0.00 seconds

Constructing platform-level signal connectivity ...
Completion time: 0.00 seconds

Writing (top-level) BMM ...
Writing BMM - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system.bmm

Writing (top-level and wrappers) HDL ...

Generating synthesis project file ...

Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
opb_dp_mem_0_wrapper (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Running XST synthesis
opb_dp_mem_1_wrapper (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Running XST synthesis

Running NGCBUILD ...
opb_dp_mem_0_wrapper (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Running NGCBUILD
opb_dp_mem_1_wrapper (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Running NGCBUILD

Rebuilding cache ...

Writing (stub) BMM ...
Writing BMM -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system_stub.bmm

Writing (stub) HDL ...
Total run time: 43.00 seconds