<!-- Title: 18:36:29  Mon Jan 17 2000 -->
<!-- Crewchief: Richard Hughes -->
<!-- Op1: Brian Winer -->
<!-- Op2: Phil Koehn -->
<!-- Op3: Jay Dittman -->
<!-- Op4: &nbsp; -->
<!-- Op5: &nbsp; -->
<!-- Op6: &nbsp; -->
<!-- Notes: -->
<center> 
<h1>XFT Fast Tracker Log Book</h1> 
</center>


<!-- Date: Mon Jan 17 18:37:00 2000 -->
This is a test...only a test.
<!-- Author: Steve Hahn -->


<!-- Date: Mon Jan 17 20:00:34 2000 -->
Can I make an entry?
<!-- Author: {Quick_Entry} -->


<!-- Date: Mon Jan 17 20:01:43 2000 -->
<pre>This is another test message</pre>
<!-- Author: Richard Hughes -->


<!-- Date: Tue Jan 18 10:05:47 2000 -->
This is yet another 
<!-- Author: {Quick_Entry} -->


<!-- Date: Tue Jan 18 10:29:19 2000 -->
Howdy do neighbor?
<!-- Author: Brian Winer -->
<!-- Comment: Tue Jan 18 14;31;23 comment by...Phillip Koehn -->
Very well thankyou.


<!-- Date: Tue Jan 25 22:09:10 2000 -->
<pre>Summary of linker boards retested at B0 
using Linker Tester #3: 
 
Board #			Results/Comments 
------- 	        ---------------- 
4,1,2,21,10,5,11,19	Pass ALL tests*. 
 
			(board 1 Passes ALL tests with 
			Linker tester #2 as well, and is 
			now in the 14th floor XTRP teststand 
			with linker board 8.) 
 
16			Passes all tests with the exception 
			of 1 bit error in 33ns throughput test. 
			( link10find1 has bit 6 stuck LOW )			 
 
12			Passes all tests with the exception 
			of 2 bit errors in the Input Cable Test. 
			( bits 20,21 stuck low on Input Formatter 5 )			 
 
14			Fails only Trackfinding: 
			 2458 errors/Linker Chip 
 
7			Fails Trackfinding: ~500 total errors 
 
			Fails Input Cable Test:  
			  Input Formatter 0 Ram 0 many bits stuck low  
			  Input Formatter 0 Ram 1 Timing 'out of sync' 
			  Input Formatter 2, Ram 1 bit 16 low 
 
			Passes all other tests. 
 
15			Fails Trackfinding: ~500 total errors 
 
			Fails Input Cable Test:  
			  Input Formatter 1 Ram 1 bits 0->7 stuck 
 
			Passes all other tests.</pre>
<!-- Author: Phillip Koehn -->
<!-- Comment: Tue Jan 25 22;14;39 comment by...PTK -->
The "Suite o' Tests" performed are the following:
    1) Linker Internal Test
    2) Input Cable Test
    3) Trackfinding
    4) Output Cable Test
    5) 33ns Throughput Test


<!-- Date: Thu Jan 27 09:41:39 2000 -->
<pre>Testing of pre-production board "P0" that was previously 
in the XTRP teststand on the 14th floor. 
 
I swapped in the newest vme interface EPROM. 
 
Ran the "Suite o' Tests" with allst111_old.rbf, 
allxt133.rbf, and all33tst.rbf. 
 
Test Results: The board PASSES ALL TESTS with the exception 
of 1 stuck bit in the Input Cable Test: Input Chip 4 RAM 0 has bit 9 stuck high. 
</pre>
<!-- Author: Phillip Koehn -->


<!-- Date: Fri Jan 28 13:47:01 2000 -->
Rearranged order of cards in the Linker crates (b0xft01, b0xft05).  Now have Linker cards in every even slot from slot 4 and ending at slot 18.  The Linker output module for each Linker will be in the slot which is 1 less than the Linker card module (i.e. Linker in slot 18 has Linker output module in slot 17).
<!-- Author: Richard E. Hughes -->


<!-- Date: Fri Jan 28 14:03:31 2000 -->
Installed backplane jumpers in b0xft01 and b0xft03.  Jumpers 
are installed between the following slots in both crates. 
 
	Slots 4-3 
	Slots 8-7  (temporary jumper) 
	Slots 10-9 
	Slots 14-13 
	Slots 18-17 
 
See previous message for slot assignment for the Linkers and 
the Linker Output Modules (LOMs)  
<!-- Author: Brian Winer -->


<!-- Date: Fri Jan 28 14:33:28 2000 -->
<pre> 
Looking at Linker Board #7 We found only one problem with 
board.  A disconnected pin on the Channel Link U405. Pin 33 
needs to be reconnected.</pre>
<!-- Author: BW,RH,PK -->


<!-- Date: Fri Jan 28 14:51:45 2000 -->
<pre>Linker Board #7 is now fixed.  Track finding reports no errors.</pre>
<!-- Author: RH, PK, BW -->


<!-- Date: Fri Jan 28 15:02:00 2000 -->
<pre>Checking Linker Board #5 we found a damaged connector 
on the second channel link cable that feeds U403.  A 
pin is bent and the spring connection is not being made. 
Need to see if we can repair the connector. 
</pre>
<!-- Author: BW, RH, PK -->
<!-- Comment: Tue Feb  1 08;05;29 comment by...PTK -->
I think we mean Linkerboard #15.


<!-- Date: Tue Feb 1 17:41:39 2000 -->
<pre> 
Testing of Linker Boards (Diagnostics Test) 
		Diag R/W  In R/W  Out R/W  In Cable  33ns Test       
  Linker 07       P	    P	    P	      F*	P 
  Linker P0	  P	    P	    P         F*	P 
  Linker 10	  p	    P	    P         P		P 
  Linker 16	  P	    P	    P	      P		P 
  LInker 15	  P	    P	    P	      P		P 
  Linker 12       P	    P	    P         F*	P 
  Linker 21       P         P	    P	      P		P 
  Linker 05       P         P	    P	      P		P 
 
	P = Pass;  F = Fail 
 
      **Linker 12: Input Chip 5 Ram 0 bit 20 stuck low 
 
      **P0: Input Chip 4 Ram 0 bit 9 Stuck High 
	    Input Chip 5 Ram 0 bits 0 stuck high 
				    3 stuck low 
				    4 high 
				   11 low 
				   20 high 
				   21 low 
				   22 high 
				   23 low 
	    (Problem with Input Chip 5,0 showed up on only 
	     one 33ns word and does not show up on  
	     AAA/555/AAA/555 and FFF/000/FFF/000 patterns.). 
	     
	 ** Linker 7 Input 2 Ram 1 Bit 16 stuck low 
 
   Run Track Finding on a few select boards: 
 
	Linker 16:   passes track finding 
	Linker 15:   passes track finding 
</pre>
<!-- Author: BW, PK -->


<!-- Date: Fri Feb 4 16:52:09 2000 -->
<pre> 
  Looked at 4 other linker boards to perform internal 
  tests  (Single R/W or VME,Input,Output Chips and 33ns 
   test).   Linker boards 02, 19, 04, 11 passed all tests. 
 
   Linker board 04 has an interesting problem with the 
   front panel lights.  When the Altera chips configure, 
   all lights come on.  The VME EPROM is the new style with 
   the yellow light indicating the board is being addressed. 
   One guess is that one of the output chips' debug-enable  
   lines is shorted to ground.  Need to check this. 
 
   </pre>
<!-- Author: PK, BW -->


<!-- Date: Fri Feb 11 16:00:37 2000 -->
<pre>Problem with Linker 12 traced to a solder bridge between vias near channel link 10.  Board now passes input cable test.</pre>
<!-- Author: BLW -->


<!-- Date: Sun Feb 13 16:02:29 2000 -->
<pre>Running "Suite O' Tests" on linkerboards @B0 
 
Board#			Results/comments 
 
11			Passes internaltests 
			Fails Input Cable test: Input 4 Ram0:bits 17,22,23 stuck, Ram1: bits 4,5,11 
                        Fails Trackfinding ~ 1500 total errors over all linker chips(probably due to bits above) 
                        Passes 33ns test, but fails the Output cable test: bit 10 stuck in FIFO 1. 
			Very unsavoury. 
 
 
04			Passes Internal tests 
			Passes Input Cable Test and Track finding. 
			Passes 33ns test and Output cable test. 
			 
 
 
15			Fails internal check of output formatters bit 18 stuck low. 
			Passes input cable test and trackfinding. 
			Fails 33ns test(due to internal output test failure ?). Unsavoury. 
			Passes output cable test. 
 
 			 
 
07			Passes all internal tests. 
			Fails input cable test: bit 16 in Input formatter 2 ram 1 
			Fails trackfinding ~300 total error spread out across 5 linker chips(due to stuck input chip bit?). 
			Passes 33ns test and Output cable test. 
 
 
19			Passes internal tests, input cable test, and trackfinding. 
			Passes 33ns and output cable test. 
			That's the way I like it.</pre>
<!-- Author: Phillip Koehn -->


<!-- Date: Mon Feb 14 09:52:21 2000 -->
<pre>Examining the timing of the 33ns/Output Cable test designs.  
Looking at the timing on the Linker Tester card.  We trigger 
on the FIFO write clock and look at Word 0 bit coming out of 
the LVDS drivers.  Measure the delay between the rising edge 
of write clock to the edge of the data transition. 
 
	all33oc.rbf  (Output data clocked on outclk) 
 
		delay = 4.5 ns  (hold time) 
		       27.3 ns  (setup time) 
 
	all33oc1.rbf  (output data clocked on !outclk) 
 
		delay = 20 ns (hold time) 
			12 ns (setup time) 
 
   The second design has better timing characteristics.  We 
   need to change the fifo offset in NOUTPUT_FMT_PANEL.java 
   to account for the different edge timing.</pre>
<!-- Author: CN,BW -->


<!-- Date: Mon Feb 14 10:27:17 2000 -->
<pre>Investigating some of the board problems: 
 
	Linker 07:  Input Chip 2 Ram 1 Bit 16 comes in on 
		    line 113.  Output of Channel Link 5 bit 
		    4. (pin 33)   Pin 33 on channel link U405 
		    needs to be connected (Previous fix did 
		    not work) 
 
	</pre>
<!-- Author: CN,BW -->
<!-- Comment: Fri Feb 18 16;02;13 comment by...PTK -->
Fixed the above cold solder joint. Boards now passes all tests
eith the exception of Input Cable test. Stuck bits on input formatter 1, Rams 0 and 1. Looks like a timing problem.
<!-- Date: Mon Feb 14 11:11:26 2000 -->
<pre>   Looking at Linker Board #15:  Now passes all tests. 
 
   Looking at Linker Board  #11:  Passes Internal Tests 
				  Passes Input Cable Test 
				  Fails Output Cable test 
					Fifo #1 Bit 11 Stuck high 
				  Fails Track finding in a way  
				  that is consistent with a 
				  bit failure on output. 
 
</pre>
<!-- Author: CC,BW -->
<!-- Comment: Sun Feb 20 14;23;00 comment by...PTK -->
Passes ALL tests with the exception of the Output Cable Test. The output is 180 degrees out of phase. Looks like a timing problem.

<!-- Comment: Sun Feb 20 14;24;11 comment by...PTK -->
I was referring to Board #11.

<!-- Comment: Sun Feb 20 15;50;59 comment by...PTK -->
After xftmod update, board 11 PASSES ALL TESTS!


<!-- Date: Fri Feb 25 11:33:00 2000 -->
<pre>Tested new EPROMS which have the latest VME control chip program. 
There are two of these at FNAL - they are marked with the "Altera" logo crossed out with blu permanent marker. 
 
Used the new EPROM on board #19.  Needed to bring over allstb07.rbf for use with this new EPROM as well.  No errors in track finding , input cable test, or internal tests.  There were no errors seen in the previous version of EPROM/rbf file. 
 
Used the new EPROM/rbf file on Board #1.  This is a board that has previously shown errors on the input capture test.  There 
are still errors, but now they appear in a different input chip - Input chip #3, ram 0.</pre>
<!-- Author: Evelyn, Richard -->


<!-- Date: Fri Feb 25 16:15:14 2000 -->
<pre>Modified Input Chip #3 tdf file, to try to fixe problems 
seen in Board #1.  Now use rising edge of enb lines to 
clock data into L2 buffers, instead of clk33.  addr's are  
still used as enables.   This new design is allstb0a.rbf. 
 
With this new design, there are no errors in Board #1, 
for all patterns, for all buffers.  </pre>
<!-- Author: Richard, Evelyn -->


<!-- Date: Fri Feb 25 18:21:05 2000 -->
Made mods to Input chips 0,1, and 3.  Ran test on Board #4, 
need to make pipeline offset=33.  Still problems in I.C. 3. 
Damn.
<!-- Author: richard, evelyn -->


<!-- Date: Tue Mar 7 16:55:05 2000 -->
<pre>B0 crate setup for both b0xft01 and b0xft05 
-------------------------------------------- 
 
All linkerboards have new VME chip EPROMs programmed 
with file R:\Linker Production\Vme Control\vme_cntl.pof 
 
Both linkertesterboards have new VME chip EPROMs programmed 
with file R:\input board\version 2\vme_in30.pof 
 
Try to keep linkerboards in even slots. 
Move Linker Output Module and backplane connectors if necessary 
in order to test different boards. 
 
------------------------------- 
Board			Slot 
------------------------------- 
CPU			 1 
Tracer			 2 
Linkertester		 3 
Testclock		11 
 
Linkerboards		 x	(where x is an even number) 
Linker Output Module	(x-1)	 
 
Backplane connectors 	7&8, 9&10, 13&14, 15&16 
 
----------------------------- 
b0xft01 crate linkers 
----------------------------- 
Linkerboard 05		 6			  
Linkerboard 01		 8  
Linkerboard 15		10 
Linkerboard 17		14 
Linkerboard 19		16	 
Linkerboard 24		18 
Linkerboard 16		20	 
----------------------------- 
b0xft05 crate linkers 
------------------------------ 
Linkerboard 28		 6			  
Linkerboard 02		 8  
Linkerboard 04		10 
Linkerboard 10		14 
Linkerboard 23		16	 
Linkerboard 21		18 
Linkerboard 07		20	 
------------------------------- 
</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Tue Mar 7 17:13:29 2000 -->
<pre>Standard design 		= ~rklein/software/allstnw1.rbf 
33ns + output cable test	= ~rklein/software/all33oc.rbf</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Thu Mar 9 09:42:29 2000 -->
<pre>Things needed to be added to the code: 
 
	1) Check Flashram Button on flash ram load panel should 
           be reactivated. 
	2) Multilinker Internal test should have a box for 
           what design file we have loaded so the code can 
           check against that file. 
        3) Should be able to do the following with a single 
	   diagnostic rbf file: 
		a) Input/Output Single R/W 
		b) Channel Link Clock test 
	 	c) 33ns test. 
            (This almost works...it works on some boards but 
             not all...this might be due to a bad version of 
	     the input chip design.) 
 
</pre>
<!-- Author: Brian -->


<!-- Date: Fri Mar 10 15:16:06 2000 -->
<pre>All the items on Brian's to-do list have been done. 
 
Results of tests carried out on March 9th and March 10th. 
Standard design is allstnw3.rbf & 33ns/output cable design is all33oca.rbf 
 
************************************************************************************ 
CRATE b0xft05 
==================================================================================== 
TEST		Slot--->| 	 6	 8	10	14	16	18	20 
                -------------------------------------------------------------------- 
		Board-->|	28	 2	 4	10	23	21	07 
==================================================================================== 
FlashRam 0		|	T	T	T	T	T	T	T 
FlashRam 1		|	T	T	T	T	T	T	T 
0 contains allstnw3.rbf	|	T	- 	T	T	T	T	T 
1 contains all33oca.rbf |	T	-	T	T	T	T	T 
------------------------------------------------------------------------------------ 
Diagnostic Registers	|	T	T	T	T	T	T	T 
Input Formatters	|	T	T	T	T	T	T	T 
Output Formatters	|	T	T	T	T	T	T	T 
Channel Links		|	T	T	T	T	T	T	T 
33ns Test	 10	|	T	T	T	XXX	XXX	XXX	T 
------------------------------------------------------------------------------------ 
Output Cable	100	|	T	-	T	T	T	T	T 
Input Cable	100	|	T	T	T	T	T	T	XXX	 
TrackFinding	100	|	T	-	T	XXX	XXX	XXX	T 
TrackFinding 25,000	|		-	T 
------------------------------------------------------------------------------------ 
Comments: 
========= 
Board 2 is back at OSU to investigate FLASHRAM loading problem.  Board 02 works 
	perfectly at OSU.  So does board 21 here, which could not be successfully 
	loaded either yesterday.  Is it possible that the server software was out  
	of date?  Only difference is that the crate had been powered off and on  
	in order to remove board 02, which would redownload the crate cpu with fresh 
	software... 
 
Board 10 fails trackfinding due to errors on linkers 0, 1 & 2. 
	 fails 33ns test due to problems with bit 6 on LINK0FIND2 for linker0  
					      bit 6 on LINK0FIND2A for linkers 1 & 2. 
 
Board 23 fails trackfinding due to pT errors on linkers 0, 1 & 2. 
	 fails 33ns test due to problems with bit 1 on LINK2FIND2A for linker 0,1 & 2:  
	 				      bits 0-11 on LINK7FIND2 for linker 9 only. 
 
Board 21 fails trackfinding due to errors on linker 9. 
	 fails 33ns test due to problem with bit 1 on LINK8FIND1C for linker 9 only. 
	 *** Pin 99 on chip U109 is loose and needs to be fixed. 
 
Board 7 fails the input cable test because of our old friend Input chip 1 RAM 0 & 1. 
	Sorry Richard!  The words read compared to those expected are shown below: 
 
	Buffer 0 (555/000/AAA/000) 
	--------------------------- 
	Input Formatter chip 1, RAM 0:  
	Read: 0   Expect: 0 
	Read: 555555   Expect: 555555 
	Read: 0   Expect: 0 
	Read: 555555   Expect: aaaaaa 
 
	Input Formatter chip 1, RAM 1:  
	Read: 0   Expect: 0 
	Read: 555   Expect: 555 
	Read: 0   Expect: 0 
	Read: 555   Expect: aaa 
 
	Buffer 2 (counter) 
	------------------- 
	Input Formatter chip 1, RAM 0:  
	Read: 40001   Expect: 40001 
	Read: 80002   Expect: 80002 
	Read: 40001   Expect: c0003 
	Read: 80002   Expect: 100004 
 
	Input Formatter chip 1, RAM 1:  
	Read: 40   Expect: 40 
	Read: 80   Expect: 80 
	Read: 40   Expect: c0 
	Read: 80   Expect: 100 
 
	Buffer 3 (counter) 
	------------------- 
	Input Formatter chip 1, RAM 0:  
	Read: 140005   Expect: 140005 
	Read: 180006   Expect: 180006 
	Read: 140005   Expect: 1c0007 
	Read: 180006   Expect: 200008 
 
	Input Formatter chip 1, RAM 1:  
	Read: 140   Expect: 140 
	Read: 180   Expect: 180 
	Read: 140   Expect: 1c0 
	Read: 180   Expect: 200 
 
 
</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Fri Mar 10 16:37:57 2000 -->
<pre>Board 07's problem with the input capture test is due to a loose pin (45) on input chip 1 U201.</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Mon Mar 13 09:24:14 2000 -->
<pre>Over 95,000 loops of the TrackFinding test were ran on boards 28 
& 15 over the weekend: no errors were found!  No ROBIN errors on 
the cpus either.</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Tue Mar 14 16:23:28 2000 -->
Boards 01, 04 and 05 have received their front panel switches and appear to be working properly.  There are possibly two more Linker boards without the switches; they are on the 14th floor at the XTRP test stand. 
 
As for the problem boards from above entry last friday: 
	 
	Board 10:  Found unconnected pins.   
		Soldered pins U200 227 and U201 196.  Now this 
	 	board passes the 33ns test and 	trackfinding 
	Board 21:  Soldered U201 pin 45.  Now this board passes 			the 33ns test and trackfinding 
	Board 7:  Soldered pin 45 on U201.  Now this board passes 			all tests. 
	Board 23:  Removed solder bridge to cure single bit 				error.  Link7Find2 problem remains. 
	Board 15:  Found an open pin 185 U900.  Will fix 				tomorrow. 
 
Board 23 will be looked at closely tomorrow.  The control lines looked all connected.
<!-- Author: Chris Neu -->


<!-- Date: Mon Apr 3 12:25:43 2000 -->
<pre>Ran 100,000 loops (259 million events) of Finder to Linker test (1 linker 0 event, 2 linker 2 events per 16 event block) with no errors. </pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Thu Apr 20 18:36:05 2000 -->
<pre> 
   Tested all the boards in B0xft05. 
   Linker Boards: 25,10,14,22,26,23,05,21 
   All boards find tracks when looping on 
   L2 buffers.   
 
   When running the output cable test with  
   board 21 I see 2 bit errors in red fifo. 
   Track finding through to LT card shows  
   errors on Linker 11.  These don't show up 
   when testing with L2 buffers. 
 
   Running track finding through to LT with 
   Linker board 05 I do not see any errors.</pre>
<!-- Author: Brian -->


<!-- Date: Thu Apr 20 18:53:48 2000 -->
Vectors have been generated for the 1miss designs for 
finderchips SL 3 and 4 from: acdfos::USR$DISK:[PKOEHN.XFT.TESTVECTORS]MASKS_AXIAL_031000.DAT  
the new mask file updated for geometry corrections in the xft simulation. 
 
They have been tested in finderboards in b0 and pass w/o error. 
<!-- Author: phillip koehn -->


<!-- Date: Fri Apr 21 15:29:48 2000 -->
Two finder 1/3 boards (crate 2 slots 7 and 8) brought 
back to 14th floor. Will not reprogram.
<!-- Author: ptk -->


<!-- Date: Fri Apr 21 15:35:19 2000 -->
All masks for both the 1miss and 2miss designs for finder 
SL3 and SL4 have been tested in the SoloFinder test using the 
masterclock and TS. 
 
This test used events based on the newly updated Mask set - 
referred to above. 
 
All events pass w/o error. 
  
<!-- Author: ptk -->
<!-- Comment: Fri Apr 21 16;53;05 comment by...ptk -->
SL4 3miss design tested with ~6600 events generated from
30 masks from the update set.

All events pass the SoloFinder test using the TS without
error!


<!-- Date: Wed Apr 26 13:01:24 2000 -->
<pre>New Mask set Finder Test Update. 
 
The new mask set is in cdf online cvs repository in: 
 
xftdaq/Findertestvectors/masks_axial_031000.dat. 
This file just contains the masks for the axial 
superlayer taken from findermasks_031000.dat that 
is used in the XFT Simulation(see the appropriate cvs 
repository). 
 
Events containing prompt and delayed hit information 
are generated from the mask set. They are generated 
in three different miss modes: All cominations of 1,2, and 
3 missed wires of the 12 in a COT cell.   
 
Finder board Input Alignment/Finder/Pixel PLD's in crate b0xft02 
are programmed in Driver/Finder/Capture mode. 
 
We run the Finder cdfvme "solo test panel". The above events are 
downloaded into the Input Alignment chips, run through 
the finder chips at speed, and fired pixels are captured 
in the pixel chips and compared to what is expected. 
This test uses Masterclock and started with Halt-Recover-Run 
control signals delivered by the Trigger Supervisor. 
 
SL	#miss		test status 
 
3	1,2,3		PASS and Finished 
 4	1,2,3		PASS and Finished 
 1	1,2		PASS and Finished 
 1	3		testing in progress 
 2	1,2		PASS and finished 
 2	3		testing in progress</pre>
<!-- Author: ptk -->
<!-- Comment: Thu Apr 27 14;24;51 comment by...ptk -->
The 3miss design for SL1 is now fully tested.

ALL events PASS w/o error.
<!-- Comment: Thu Apr 27 16;36;09 comment by...ptk -->
The 3 miss design for SL2 is now fully tested. ALL events PASS w/o error.
<!-- Date: Wed Apr 26 13:06:16 2000 -->
hibrianiamusingthelo
<!-- Author: {Quick_Entry} -->




<!-- Date: Mon May 1 11:32:31 2000 -->
<pre>Received and tested the following files generated by 
BLW for the XFT Hardware Sim: 
 
/cdf/code-common/cdfonline/xftdaq/InAlign_SL13_00_042800.dat 
/cdf/code-common/cdfonline/xftdaq/InAlign_SL24_00_042800.dat 
/cdf/code-common/cdfonline/xftdaq/PixelDrv_SL13_00_042800.dat 
/cdf/code-common/cdfonline/xftdaq/PixelDrv_SL24_00_042800.dat 
 
In the FinderSolo test, these files are renamed as: 
 
/cdf/code-common/cdfonline/xftdaq/iac_exptd_sl13_00_042800.dat 
/cdf/code-common/cdfonline/xftdaq/iac_exptd_sl24_00_042800.dat 
/cdf/code-common/cdfonline/xftdaq/iac_input_sl13_00_042800.dat 
/cdf/code-common/cdfonline/xftdaq/iac_input_sl24_00_042800.dat 
 
These files are for the 1 miss design based on the new mask set. 
 
All events therein pass the FinderSolo test w/o error. 
</pre>
<!-- Author: ptk -->


<!-- Date: Mon May 1 15:28:50 2000 -->
Testing Linkerboards in crate b0xft03. 
 
Board#	Internal Test	Input Cable Test 
04	PASS		PASS 
01	PASS		PASS 
28	PASS		PASS 
07	PASS		PASS 
11	PASS		FAIL  
	(Chip0-Ram0&1, chip1-Ram0&1, chip2-Ram1 
	many bits are stuck. Looks like timing. 
	This should be fixed with allst111.rbf.) 
15	PASS		PASS 
12	PASS		PASS 
06	PASS		PASS 
 
 
  
<!-- Author: ptk -->
<!-- Comment: Mon May  1 16;44;58 comment by...ptk -->
Let me rephrase the above entry in the next entry...


<!-- Date: Mon May 1 16:58:48 2000 -->
<pre>Testing Linkerboards in crate b0xft03.  
 
 
Board# Internal Test Input Cable Test  
 
04 	PASS		PASS 
 
01	PASS		PASS 
 
28	PASS		PASS 
 
07	PASS		PASS 
 
11	PASS		FAIL 
 
		(Chip0-Ram0&1, chip1-Ram0&1, 
		chip2-Ram1 many bits are stuck.  
		Looks like timing. This should  
		be fixed with allst111.rbf.) 
 
15	PASS		PASS 
 
12	PASS		PASS 
 
06 	PASS		PASS 
</pre>
<!-- Author: ptk -->


<!-- Date: Wed May 3 17:52:40 2000 -->
<pre> 
Ran tests on all linkerboards in crate with b0xft05. 
Checked internal test, input cable test (10 loops),  
trackfinding with new geometry  
(100 loops linkertester & level 2 buffer checking),  
33ns test (10 loops) and output cable test (10 loops). 
------------------------------- 
Board #		All tests 
------------------------------- 
18		PASS 
------------------------------- 
8		FAILs input capture and trackfinding completely	   
                Correct VME chip design? 
------------------------------- 
14		PASS 
------------------------------- 
22		PASS 
------------------------------- 
26		PASS 
------------------------------- 
23		FAILs 33ns test.  link7find2 bits 0-11 stuck. 
		Same problem as on March 14. 
		Checked U203 pins 172-158 & U109 pins 75-88  
		and control lines 94,95. ??? 
------------------------------- 
5		PASS 
------------------------------- 
21		FAILs output cable test with 2 bits in read FIFOs 
		stuck.  Changed linkertester...same problem. 
		FIFO 2 bit 11 and FIFO 3 bit 13. 
		Checked U900 pins 161-162 and U901 pin 158. ??? 
------------------------------- 
 
</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Thu May 4 12:40:43 2000 -->
<pre>Follow-up to yesterday's tests: 
======================================== 
Board 8: Swapped VME EPROM with Board 23. 
	 Now works perfectly, so it was an old VME chip design 
	 that was to blame.  Suspect that this board was returned 
	 recently from the XTRP teststand. 
---> 
--->     Need to make new VME EPROM for board 23, which now has 
--->	 the problem! 
========================================= 
Board 23: Only fails 33ns for link7find2 on linker chip 9. 
-------------------------------- 
Eg	Phase	Expect	Observe 
	0	fff	4 
	1	000	4 
	2	fff	4 
	3	000	4 
-------------------------------- 
	  By looking at Altera tdf file, this corresponds 
	  to finder chip 8.  In the 33ns test each finder chip 
	  is specified by 4 control lines. Finder chip 8 
 	  corresponds to control line linker_ctl3 being set. 
	  Finder chip 9 is unused on this linker so finder chip 8 	 
	  is the only thing for which linker_ctl3 has to be set. 
	  Pin 212 on U109 seems solid.  Perhaps there is an  
	  internal problem?  Since this control line is only used 	 
	  in the 33ns test, we'll live with this for now. 
=========================================== 
Board 21:  Only fails output cable test with  
	   2 stuck bits in fifos on linkertesterboard. 
	   Problem same with different linkertesterboard. 
	   Moved board from slot 20 to slot 16 and stuck bits 
	   disappeared.  No problems seen for board now in slot 
 	   20 either. Swap back...no problems seen now either. 
	   Therefore, suspect loose connection caused the 
 	   problem. 
============================================ 
Status of boards in crate with b0xft05 
-------------------- 
Board		Status 
-------------------- 
18		PASS 
8		PASS 
14		PASS 
22		PASS 
26		PASS 
23		PASS (except 33ns test, suspect int. linker_ctl3) 
5		PASS 
21		PASS 
--------------------- 
Board 23 also needs a new VME EPROM.</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Thu May 4 16:22:14 2000 -->
<pre>Ran all tests (see entry above) on all linkerboards 
in crate with b0xft01: all passed! 
====================== 
Board		Status 
====================== 
29		PASS 
27		PASS 
2		PASS 
0		PASS 
16		PASS 
19		PASS 
24		PASS 
17		PASS 
======================	</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Thu May 4 18:29:42 2000 -->
<pre>Testing crate b0xft03. 
 
All Linkers pass internal tests + 33ns tests: 
 
	04, 01, 28, 07, 11, 15, 12, 06 
 
Board#		Trackfinding 
06		24 errors in linker chip 1 
12		PASS 
15		PASS 
11		FAILS (Also major failures on Input Capture) 
07		PASS  
28		PASS 
01		PASS 
04		PASS 
25		PASS 
10		PASS</pre>
<!-- Author: ptk, blw -->


<!-- Date: Fri May 5 12:11:00 2000 -->
<pre>I swapped the vmechip EPROM on boards 11 and 4. 
 
Rerun a suite o' tests. 
 
Board 11 passes internal tests, 33ns test, output cable 
test, input cable test, and trackfinding. 
 
Board 04 passes internal tests, 33ns test, output cable 
test. But now fails the input cable test as board 11 did 
previously. 
 
The EPROM is old in board 04 and must be replaced. 
 
</pre>
<!-- Author: ptk -->
<!-- Comment: Mon May  8 15;20;43 comment by...ptk -->
The EPROM in board 04 was replaced.

This board PASSES ALL TESTS!


<!-- Date: Fri May 12 16:23:20 2000 -->
<pre>New Timing settings for Linker Tester ("LT") and linker boards 
in crate b0xft05. 
 
 
LT sw502=01000000 sw501=00111100 (0==GND,1==true) 
 
 
Linker		sw701			sw702 
 
26		01110000		00001100 
 
21		01110000		00001100 
 
22		01110000		00001100 
 
05		01110000		00001000 
 
04		01110000		00001100 
 
	(FTL: time diff from chl_clk to 33ns clk = 11ns) 
 
        (LTL: time diff from chl_clk to 33ns clk = 18ns) 
 
11		01010000		00011100 
 
14		01110000		00000100 
 
	(FTL: time diff from chl_clk to 33ns clk = 18ns) 
 
        (LTL: time diff from chl_clk to 33ns clk = 11ns) 
 
08		01110000		00000100 
 
Also tried the "suite o' tests" on board 05 in both slots 8  
and 20 to check for slot dependence. PASSES all FTL and LTL 
tests. 
</pre>
<!-- Author: ptk & et -->


<!-- Date: Mon May 15 08:32:02 2000 -->
<pre>Ran trackfinding on linkerboard 05 in slot 20 and Linker Tester 
 
in slot 04 in b0xft05. Both have the new timing dip-switch   
 
settings(please see previous entry) that Evelyn and I found to  
 
work with Finder to Linker to Linker Tester. 
 
This test ran for 200000 loops for over 491 million events without error! 
 
</pre>
<!-- Author: ptk -->


<!-- Date: Mon Jun 5 17:12:24 2000 -->
<pre>Finder-to-Linker integration test is working with the TS for a 
full crate of 16 finderboards to a full crate of 8 linkerboards!   
This corresponds to 120 degrees in phi.  The test loads the 
finders with simulated XTC hit data.  TS commands are used to 
start, send L1As and stop all the finders and linkers 
simultaneously.  The contents of the L2 buffers are then  
compared with simulated files.  
------------------------------------------------------------- 
Running an overnight test with 20,625 loops, checking 4 events 
per board per loop...</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Wed Jun 7 14:44:09 2000 -->
<pre>Problem with board 18: blows fuse when powered on.  Probably 
caused by probing when timing in board...</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Mon Jun 12 11:38:30 2000 -->
<pre>Over the weekend, ran 30,000 loops of the finder to linker test 
with the TS for a full crate of 16 finderboards to a full crate 
of 8 linkerboards.  1,059,836 events were read from the level 2 
buffers and checked, with NO errors.  This was in addition to 
3,000 loops on Friday afternoon. 
=================================================================  
Ran 9,000*6 loops of the finder to linker test with the testclock 
for board 4 in crate b0xft03.  218,400 event were read from the 
level 2 buffers and checked, with NO errors. 
================================================================= 
24/26 boards timed for finder to linker test. 
--------------------------------------------- 
Board 	SW701	SW702	FTL(ns)	IC(ns) 
------------------------------------- 
0	567	4	19	11 
1	567	3	18	9 
2	567	4	17	8 
3	----@ OSU or Wilson Hall---- 
4	567	3	19	11 
5	567	4	 
6	567	34	18	8 
7	567	3	18	8 
8	567	3 
9	----@ OSU or Wilson Hall---- 
10	567	4	19	8 
11	5-7	345	 
12	567	34	19 	9 
13	----@ OSU---- 
14	567	3 
15	567 	3	18	8 
16	567	4	19	11 
17	567	-	19	11 
18					*fuse blows 
19					*missing fuse 
20	----@OSU or Wilson Hall----- 
21	567	34			*33ns test fails 
22	567	34 
23	567 	4	18	10 
24	567	3	18	10 
25	567	-	17	9 
26	567	4	18	8	*33ns test fails 
27	567	-	 
28	567	4	18	8 
29	567 	34 
---------------------------------------------------------- 
The delay between the channel link clock and the on-board clock 
is measured in ns for both the finder to linker test (FTL) and 
the input cable test (IC).  On Input formatter chip 0 (U200), 
pin 90 is the clock signal from channel link 0 and pin 91 is  
the onboard 33ns clock.  Pin 29 on U400 is a data bit. 
 
</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Mon Jun 12 16:34:46 2000 -->
<pre>+++++++++ 
Board 26 had 2 problems 
++++++++++ 
Input cable test: 
Input FMT 1 RAM 0 bits 5 and 6 stuck occasionally 
555575 != 555555 
aaaaaa == aaaaaa 
100464 != 100444 
------ 
Finder to linker test: 
Event 29 Finder 2a finder pixels = c0 but linker pixels = e0 
-----> 
Phil found a solder blob on channel link U402, which shorted 
2 of the pins.  U402 passes information to Input FMT 1. 
----- 
	33ns test problem 
Finder #1 linker chip 2 link0find2a bit 0 stuck for all patterns. 
-----> 
This is pin 61 on chip U102.  Phil noticed that the trace for 
this pin doesn't seem to be connected to the via.   
We're going to ask Scott about the best way to fix this. 
-------- 
This board worked fine on May 2nd, but problems were noted  
(but not fixed) on May 11th. 
 	   </pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Mon Jun 12 16:36:52 2000 -->
<pre>Board 26, linker chip 2 also had an error on the finder to linker 
test. Event 27 had a pt of 37 instead of 36.  Probably also  
due to trace-via problem for pin 61 on U102.</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Tue Jun 13 10:31:35 2000 -->
<pre>Ran another 10,000 loops over boards in crate b0xft00 and 
b0xft01 with the TS overnight.  320,100 events checked from  
Level 2 buffers with no errors.  This time a board was in slot 4, and everything still worked, whereas last week there were problems with having a board in slot 4.   
 
</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Mon Jun 26 17:14:09 2000 -->
<pre>Altered linkertester delay switches so that channel  
link clocks arrive at the linker at roughly the same  
time as those from the real finders: 
******************************************************** 
RE Finder clink clock to RE onboard 33ns clock = 18-19ns 
******************************************************** 
LT Before: SW501=6543 SW502=7 => delay = 62+20=82ns 
RE Channel link to RE onboard 33ns clock = 8-10ns. 
RE data to RE write clock = 17ns   
-------------------------------------------------------- 
Adjust LT delay switches 
-------------------------------------------------------- 
LT:	SW501=6543 SW502=65 => delay = 54+20=74ns 
RE Channel link to RE onboard 33ns clock = 16-18ns. 
RE data to RE write clock = 25ns  ****OC & TF fail**** 
-------------------------------------------------------- 
Since adjusting the delay switches moves both the 
read clock (->channel link clock) and the write clock, 
the number of LCELLs delaying the write clock in the VME  
chip design for the linkertester was changed.   
u:\pkoehn\input board\version 2\vme_inbd.tdf 
Before, the number of LCELLs was 3.  
--------------------------------------------------------- 
# of LCELLs 	RE data to RE write clock(ns)   
0		20 
1		20	 
2		24 
5		02 (+33) 
6		LT board hangs CPU! 
--------------------------------------------------------- 
Even with 0 LCELLs, the TrackFinding test still fails while 
the Output cable test passes for 0 or 1. 
Therefore, remove 4ns from delay switch 
--------------------------------------------------------- 
FINAL:	SW501=653 SW502=65 => delay = 50+20=70ns 
RE Channel link to RE onboard 33ns clock = 20-22ns. 
RE data to RE write clock = 16ns  ****OC & TF pass**** 
--------------------------------------------------------- 
PS. Standard Linker delay switch settings are: 
SW701 = 567 
SW702 = 3 or 4 or 34</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Wed Aug 9 10:47:58 2000 -->
<pre>Found a few problems with some linkerboards on Monday 8/7/2000 
 
Running 33ns test on all boards @ B0 
 
Lnk 17:  had a few single bit errors  
Lnk 23:  fails on linker 9 link7find2 all bits consistently 
Lnk 07:  catastrophic failure on all bits, all linkers 
Lnk 15:  a few intermittent single bit problems 
Lnk 20:  two single bit errors link5find1A bit 5 
			       link5find2B bit 0 
Lnk 09:  catastrophic failure on all bits, all linkers 
 
***I will look into these problems further next week after DPF***</pre>
<!-- Author: neu -->


<!-- Date: Wed Aug 23 16:23:27 2000 -->
<pre>Tested all 25 boards in all 3 linker crates using testclock 
and linkertester vme_i50a.pof.  Only 2 boards have problems: 
 
Linker board 6: linker chip 1 finds phi ok, but pt is 7c, 
tfnd4 and shrt are 0.  This happens when checking the L2 buffers 
and the linkertester. Problem with input to linker chip?  
Problem in linker chip?  Board passes 33ns test. 
 
Linker board 4: removed to spare crate.  Board doesn't seem to  
start!  Eg input cable test - don't see alternating pattern of 
555/aaas. Problem with chip-enable? 
 
----------------- 
 
All other linkers pass 50 loops of the input cable test, 
1 loop of 33ns and level 2 buffer checking of trackfinding. 
Some of the boards have bit errors when checking the  
linkertester => timing of wrt_clock not quite right yet. 
 
Boards in crate b0xft01 were tested with LOM 00. 
</pre>
<!-- Author: Evelyn Thomson -->


<!-- Date: Wed Aug 23 16:25:25 2000 -->
<pre>Suspect problems Chris found were due to TS and LT timing</pre>
<!-- Author: Evelyn Thomson -->