<!-- Title: 07:44:52  Fri May 25 2001 -->
<!-- Crewchief: Gino Bolla -->
<!-- Op1: Vladimir Nagaslaev  -->
<!-- Op2: Francesco Palmonari -->
<!-- Op3: &nbsp; -->
<!-- Op4: &nbsp; -->
<!-- Op5: &nbsp; -->
<!-- Op6: &nbsp; -->
<!-- Notes: -->
<pre>Followed new procedures to turn ON CAEN P.S. 
Blinky light test PASSED 
Load in a BOX test PASSED 
Wedge in a BOX test PASSED with the following problems: 
	Chs 1 and 4 of the OFTM do not receive any data. 
	As a consequence running all 5 layers together we get  
	the C4 problem. Running one layer at the time using only 
	the ch 0,2,3 of the OFTM we finished the WIB test. 
Connected real Wedge. 
	Now problems are in OFTM ch 2 while ch 1 and 4 are 
 	working fine.  
	THIS IS A GOOD EXAMPLE OF EITHER 
		Light mismatch or 
		Instability of the receiver connection on the  
		socket 
Anyway we made sure that all the 5 ladders are working correctly: 
	Unbiased Laser410.svx L0,L1,L3,L4 
		 Laser419.svx L2 (read in ch 1) 
	BIASED	 Laser413.svx L0,L1,L3,L4 
		 Laser418.svx L2 (read in ch 1) 
 
The Layer 2 is a little grassy. 
 
Applied RTV and retested successfully.</pre>


<!-- Date: Wed May 30 10:27:31 2001 -->
<pre>I put HDI 2 back on FTM chan 2, and HDI 1 back on FTM Chan 1</pre>
<!-- Author: SCN -->


<!-- Date: Tue Jul 24 18:41:15 2001 -->
<pre>Pre integration test: 
 
L2,4: init ok, bxing byte, not chip ID, PcA byte errors, no read        out 
 
L0,1,3 OK to integrate</pre>
<!-- Author: Sinead,Sehban -->


<!-- Date: Thu Nov 8 16:22:53 2001 -->
<pre>summary from the access for L4 
============================== 
Drops readout after 4th phi chip and drops the last channel on  
that chip. Set last chip=8a. Get 4/214,500 errors on HST all  on L4 dropped R0  
</pre>
<!-- Author: Petra -->
<!-- Comment: Fri Nov  9 12;06;47 comment by...Petra -->
<pre>more on L4
----------
currents (before init / after init / during RO):
AVDD = 655 / 1100 / 1100 mA
DVDD = 370 /  165 /  165 mA
this ladder inits
bias applied, histos look fine, but it's a relatively crappy ladder...
normal running: 1000 events, 0 errors
HST: 200.000 events, 0 errors

this ladder is fine!</pre>


<!-- Date: Fri Nov 9 12:16:42 2001 -->
<pre>summary from the access for L1 
============================== 
Steve:  channels, no data 
 
Petra:  currents (before init / after init / during RO): 
	AVDD = 282 / 504 / 504 mA 
	DVDD = 222 /  98 /  97 mA 
	it draws 8.4uA @ 100V, Imax = 20uA ok. 
	this ladder inits 
	normal running: 1000 events, 0 errors 
	(in a previous run I got a few empty events in between normal events, 
	but I think that was a DAQ problem...) 
	bias applied, histos look fine 
	HST: 200.000 events, 0 errors 
 
	this is a fine ladder!</pre>
<!-- Author: Petra -->


<!-- Date: Fri Nov 9 12:20:06 2001 -->
<pre>summary from the access for L3 
============================== 
Steve:  drops RO last chip / last channel 
 
Petra:  currents (before init / after init / during DAQ crash / during RO): 
	AVDD = 550 / 825 / 600 / 825 mA 
	DVDD = 205 / 100 / 190 / 100 mA 
	this ladder inits 
	bias applied, histos look fine 
	normal running: 1000 events, 0 errors 
	(in a previous run I got a few empty events in between normal events,  
	but I think that was a DAQ problem...) 
	HST: 200.000 events, 0 errors 
 
	this is a fine ladder!</pre>
<!-- Author: Petra -->