<!-- Title: 11:28:45  Fri Mar 16 2001 -->
<!-- Crewchief: Captain Jean -->
<!-- Op1: Laverne -->
<!-- Op2: Shirley -->
<!-- Op3: Laurel -->
<!-- Op4: Hardy -->
<!-- Op5: Fred -->
<!-- Op6: Barney -->
<!-- Notes: -->
<pre>Next File for Silicon activity since 
I screwed up some HTML for the previous one. 
 
We're mostly working on integrating what we got 
until the next access, when we may or may not 
plug in some more stuff.</pre>


<!-- Date: Fri Mar 16 15:18:10 2001 -->
<B> Integrated!</B><BR> 
We are running with Run Control SVXII BH 3 Phi Wedge 6. 
<ul> Problems encountered 
<li>  Nibble shifting (once) 
<li> SRC-TS communication: went spontaneously to Halt once 
after 40 kEvent, missed a L1A after 50 kEvents once.  Both resulted in a DONE timeout, recoverable from HRR.  Also 
I changed the Taxi-Clock phase shift from 96 to 64, we'll 
see if that helps 
</ul> 
We are running SiliMon and SVXMon and they seem to work. 
 
Next we'll add the L00 PC, but there is worry about ISL cooling 
so that is about as far as we can go...Someone get those damn  
quadlogs working!
<!-- Author: SCN, PLM, AJS, LHM -->


<!-- Date: Fri Mar 16 16:32:07 2001 -->
I have put some instructions for running SiliMon online 
in case you want to use it over the weekend. Go to the SiliMon 
web page (<a href="http://www-cdf.fnal.gov/internal/people/links/TaraShears/SiliMon/Intro.html">here</a>) and click on "How to run SiliMon".
<!-- Author: Tara -->


<!-- Date: Tue Mar 20 19:28:26 2001 -->
<pre>We swapped a OFTM for ISLB5W2, it has missing bits in channels 0  
and 4: 
 
old OFTM: #104, FNAL#562400 
new OFTM: #125, FNAL#563646</pre>
<!-- Author: Petra/Dave -->
<!-- Comment: Tue Mar 20 20;28;43 comment by...Jean -->
<pre>Petra says this is probably not the OFTM, but the fib
She just swapped the "bad one" (SN 141 550950) for the one
in the trigger room rack (131 560616).</pre>

<!-- Comment: Tue Mar 20 20;41;59 comment by...SCN -->
<pre>I just tested this "bad" fib with a DEM, and it
behaves fine, i.e. reads out on all channels.  I
suggest checking the light output at the crate or the 
backplane for bent pins.

PS This fib was in SVSET Slot 9</pre>


<!-- Date: Tue Mar 20 22:21:56 2001 -->
<pre>Turns out, Slot 9 was not the correct Slot.  We swapped the 
FTM out of slot 11, and now all Channels initialize properly 
at least by WIB standards. 
 
Bad FTM is 108 PREP 564033, Chan 0 and 4, and I did not 
have time to attempt to reseat and recheck.  FTM 104, PREP 562400 
is now in Slot 11, FTM 125, FNAL 563646 is in Slot 9.</pre>
<!-- Author: SCN -->


<!-- Date: Wed Mar 21 00:07:01 2001 -->
<pre>Finished connection for ISL B5W2. It took 8 hours! We lost 1 hour due to cabling problem on supply. We lost 3 because I got the wrong slot for the OFTM swap (see above). 
 
In the end, all worked fine. Details are in the <A HREF="http://ncdf17.fnal.gov/cgi-bin/lgbk?user=stuart&ent=10837">checklist.</A> 
</pre>
<!-- Author: David Stuart -->


<!-- Date: Wed Mar 21 02:49:50 2001 -->
<pre>We plugged SVX B3W5 in. Almost everything went relatively  
smoothly. A few remarks though: 
 
MATT: Why are the power supplies not daisy-chained??? We lost about 20 minutes to find that out! 
 
STEVE W.:Why are the ground wires not on the right junction cards? Takes Paul now 40 minutes or so! 
 
STEVE N.:Why had the HDI9 file still the 13 chips from the  
commissioning run in it??? We lost about 40 minutes with that! 
 
I would like to have convincing answers to these questions before  
I do any nightshift for this project again!  
 
Why do we still see the rails although we are operating with  
the final grounding now?</pre>
<!-- Author: Petra/Gino -->
<!-- Comment: Wed Mar 21 08;10;59 comment by...SCN -->
On 13 vs. 14 chips: <BR>
In fact, I had changed this to 14 chips on February 21 in the
Hardware database (there is a timestamp), but somehow
I managed to not regenerate the teststand file-since at that
point we were "focusing on the West", it is possible that I
ran out of time and left it on a "to-do" list from whence it
disappeared.  In any case, it is fixed for the online cluster
<B> but not for the laptop since it is off </B>, please see
the file /cdf/code-common/cdfonline/svxii/devel/b0crates/chips/c689.cfg.
<BR>
Hope this convinces you to keep plugging.
<!-- Date: Wed Mar 21 08:09:28 2001 -->
<pre>Tested b4w5. Layer2 grassy, large leakage current see log book 
 
M. Bishai's added list of whys 
 
S. Blusk: How come we are supposed to be able to activate 
and deactivate bulkheads when NOBODY on shift on 1st floor OR 
2nd floor has access privilages. Wasted 1 hr and woke you up. 
 
Somebody: How do we know what the right load settings are for 
bias testing with the load box. Its not like the dials have 
arrows on them, and nobody rights down on the sheets what they 
were when they were tested. </pre>
<!-- Author: Mary Bishai. P. Shepard -->
<!-- Comment: Wed Mar 21 12;18;55 comment by...Saverio -->
<pre>Somebody writes the value of resistors..
A dial knob on each switch would be helpful.
We shoud agree on a value, but one can easily check
if the current is the one expected.</pre>
<!-- Comment: Wed Mar 21 13;20;24 comment by...Petra -->
<pre>We usually write down the number of clicks you need to see a 
current, which should usually be 2 for layer 2 and 4 and 0 for the others.</pre>
<!-- Date: Wed Mar 21 09:22:14 2001 -->
<pre>Enables are now connected for SB3W6, SB3W5 and  SB4W5.  I apologize that they were not in place last night.  I used the 
last of the enable parts.  Time to get more. 
 
Now some comments on enables.  I think that moving enables should 
only be done in consultation with an expert(Either Steve Blusk 
or myself).  For instance,  last night Gino and Petra properly 
moved the enable from SB3W6 to SB3W5.  However, Mary and Paul 
then moved the enable to SB4W5.  At this point a bulkhead 4 
wedge was connected to the enable for bulkhead 3 leaving that 
ladder unprotected! 
 
</pre>
<!-- Author: herndon -->
<!-- Comment: Wed Mar 21 13;19;29 comment by...Petra -->
<pre>That was my fault, I moved that enable and should have known 
better. Sorry from that. From now on I will always call 
the expert on call (Jean, when will we get that list???) for 
any of the problems...</pre>
<!-- Date: Wed Mar 21 09:36:38 2001 -->
<pre>Plug Face: 
 
Brenna and I finished dressing the plug face.(only 5 minutes 
after the dead line Rob gave us!)  The only problems are some 
spots where the cooling tube/cable routing could use some 
improvement.  We might want to consider this in April. The area 
where our pluggers had plugged things in was very well dressed 
and didn't require any rework. 
 
David, Chris, Petra, Gino, Mary and Paul did a great job to get 
three components plugged in and still leave things in good shape 
for the plug closing. 
 
  - matt</pre>
<!-- Author: herndon -->



<!-- Date: Wed Mar 21 12:35:42 2001 -->
<pre>SB0W6: power supply tested with SVX Load box and  
spare (short) cables, it looks ok. Channel 2  
did not show current on bias, but correctly tripped with 
low resistive load. DVDD-4 correctly set at 100 mV higher. 
</pre>
<!-- Author: Sehban, Saverio -->


<!-- Date: Wed Mar 21 12:39:56 2001 -->
<pre>SB1W7: PRD2 shorted to PRD2* 
Single-end drive test: 
- PRD2 only connected: laser154.svx (4 cells are on) 
- PRD2* only connected: laser155.svx (one cell is hit) 
So, it does not cure the problem, but we may have some indication 
The two configuration produce different results, that indicates that the chip is probably still alive.</pre>
<!-- Author: Saverio and Sihban -->




<!-- Date: Wed Mar 21 14:22:12 2001 -->
<pre>Silicon cables hit by muon personnel on South East side.  Ouch! 
Cable is either a SVXII or L00 cable. Damage was minimal. One 
conductor in one LV cable sheared  through.  Cable fixed with 
butt splice.  Shield and jacket on one bias cable damaged. 
Conductors not obviously damaged, but may have been stressed. 
Shield and jacket fixed with electrical tape.  Dervin will add 
protection to bottom of cable trays in April. 
</pre>
<!-- Author: herndon -->


<!-- Date: Wed Mar 21 18:02:02 2001 -->
<pre>Trying to check the svx wedges.  We start up the CAEN GUI 
and realize it has only one crate.  We stop it, edit the file, 
and re-start.  Now we cannot get GUI to start.  we reboot  
crate twice with no luck.  Petra has sent email to andrew  
with more of the various symptoms. 
 
            
Looks like at least part of the problenm is not typing  
PS -east or PS -west.  Need to see this with Andrew. 
 
 
 
</pre>
<!-- Author: Jean, Petra -->


<!-- Date: Thu Mar 22 18:22:52 2001 -->
<p> 
I modified the SVX and ISL interlocks iFix pages (the pages with all the green boxes).  Now if the historically confusing "coupled interlocks" situation arises (e.g. ISL trips off because L00 is > 25 C) the appropriate boxes will turn red.  You'll love it.</p> 
 
<p> 
I just finished testing these pages out by forcing SVX_TE_BHW1_1, ISL_TE_CCW1L6_1IN, and L00-R-01 to 26 degrees (one at a time).  So, if 30 days from now you're looking at a historical temperature plot and you see momentary spikes up to 26, that's why.</p>  
<!-- Author: Andy H. -->


<!-- Date: Thu Mar 22 18:40:34 2001 -->
<p>Also, all SVX and ISL return temperatures are currently showing 850 degrees (or -200 degrees) because the Quadlog wiring work is going on.  Don't fret about it.</p>
<!-- Author: Andy H. -->
<!-- Comment: Thu Mar 22 18;41;53 comment by...Andy H. -->
<p>Sorry... I meant just the <b>manifold</b> return temperatures.</p>