<!-- Title: 07:30:43  Tue Feb 20 2001 -->
<!-- Crewchief: Si -->
<!-- Op1: &nbsp; -->
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<!-- Op3: &nbsp; -->
<!-- Op4: &nbsp; -->
<!-- Op5: &nbsp; -->
<!-- Op6: &nbsp; -->
<!-- Notes: -->
e260 - BH 2 W 6 - b0fib02 Slot 18 Chan 0-4<BR> 
<B> From SiDet:  L2 has 3 counts of CM noise</B>


<!-- Date: Sun Mar 4 08:14:37 2001 -->
<pre>SB2W6 cables tested ok, plug-on ok, smoothly. 
fib slot 9, crate 02, ps 30 tagged.</pre>
<!-- Author: A. Foland, S. D&#39;Auria -->


<!-- Date: Sun Mar 4 08:22:25 2001 -->
<pre>Currents at operating voltage: 
3.25  L0 
0.68 
5.00 
1.11  L4 
<1 uA</pre>
<!-- Author: Saverio, Andy -->


<!-- Date: Wed Mar 14 13:14:16 2001 -->
<pre>Testing B2W6 full bias:  
 
1) 1st run dropped bit 1 (infrequently) on Layer 4 
 
2) LAYER 1 ILLEGAL CELL IDS ON PHI CHIPS 1 AND 2 !!!!: 
 
R40 E12 Error: CAP ID           F 0 P 1 C 0 = 26 F 0 P 1 C 1 = 60 
R40 E12 Error: CAP ID           F 0 P 1 C 1 = 60 F 0 P 1 C 2 = 26 
R40 E32 Error: CAP ID           F 0 P 1 C 0 = 1 F 0 P 1 C 1 = 52 
R40 E32 Error: CAP ID           F 0 P 1 C 1 = 52 F 0 P 1 C 2 = 1 
R40 E60 Error: CAP ID           F 0 P 1 C 0 = 30 F 0 P 1 C 1 = 52 
R40 E60 Error: CAP ID           F 0 P 1 C 1 = 52 F 0 P 1 C 2 = 30 
R40 E98 Error: CAP ID           F 0 P 1 C 0 = 26 F 0 P 1 C 1 = 188 
R40 E98 Error: CAP ID           F 0 P 1 C 1 = 188 F 0 P 1 C 2 = 26 
R40 E102 Error: CAP ID           F 0 P 1 C 0 = 6 F 0 P 1 C 1 = 60 
R40 E102 Error: CAP ID           F 0 P 1 C 1 = 60 F 0 P 1 C 2 = 6 
R40 E151 Error: CAP ID           F 0 P 1 C 0 = 37 F 0 P 1 C 1 = 188 
R40 E151 Error: CAP ID           F 0 P 1 C 1 = 188 F 0 P 1 C 2 = 52 
R40 E151 Error: CAP ID           F 0 P 1 C 2 = 52 F 0 P 1 C 3 = 37 
</pre>
<!-- Author: Slave of the Nile -->


<!-- Date: Wed Mar 14 13:15:43 2001 -->
<table><tr><td><a href=/elog/notebooks/silicon_pc/e260-SVX-C-BRL-W-End-P-6/Wed_Mar_14_2001_131530.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=e260-SVX-C-BRL-W-End-P-6&action=view&page=-2  align='top'></td><td>B2W6 SVX Layer 1 bad cellids on phi side chips!!</a></td></tr></table>
<!-- Author: M Bishai -->


<!-- Date: Wed Mar 14 14:01:11 2001 -->
<pre>Examined data from this wedge. What is reported as a cellid is  
actually a pedestal where bit 7 is stuck high when channel number 
is read out. Parseerrors thinks its a chip id and reads out 
following ped as a cell id. Sometimes bit 8 is high also for 
the pedestal. Here is an event which reported a cellid 188: 
 
f2616cfc 850900bd 81bc023f 033e0435 053e063c 073d0834 09370a37 0b3c0c3c  
0d3c0e3c 0f3d103c 113c123d 1334143d 153d1634 173f183c 193d1a3c 1b341c3c  
1d3f1e3f 1f3d203c 213e223d 233c243d 253a2634 273c283f 293c2a3e 2b3d2c3f  
2d3f2e3e 2f34303d 313f3213 333d343c 3535363d 373d383c 393a3a3c 3b3e3c3d  
3d3d3e3e 3f3d4035 413d4234 433c443d 453f463a 47344834 493e4a3c 4b3a4c34  
4d3d4e3d 4f3c503e 513a523d 533d543d 553d563d 573d583e 593d5a3d 5b3c5c3a  
5d345e3e 5f3e603f 613d623a 633c6435 653e663a 673c683f 693d6a3d 6b3d6c35  
6d3d6e3a 6f3d703c 7134723c 733d743d 753d7635 773a783c 793e7a34 7b3f7c3c  
 
And another event with a purported cellid = 60 
 
e26187fc 850200bd 813c0237 033d0434 053d063c 073c0834 093d0a3f 0b3d0 
 
NEED TO CHECK DOIM LIGHT OUTPUT ON BIT 7 MAKE SURE ITS < 800 microwatts. Could explain bit high first couple of channels. 
</pre>
<!-- Author: Slave of the Nile -->
<!-- Comment: Wed Mar 14 14;03;26 comment by...M. Bishai -->
<pre>Remember that light output is also temperature dependant so
although DOIM voltages are the same as at Sidet, if we are
running slightly cooler we could have crossed that edge.</pre>

<!-- Comment: Wed Mar 14 18;54;45 comment by...Slave of the Nile + Seargent Slaughter -->
<pre>Went down to pit to check light output. Was unable to reproduce
error observed earlier. DOIM MNTP connector broken off on both
sides where pins fit (am not sure this didn't happen while
attempting to connect to octupus for probing). As a result 
alignment with probing octupus was flaky and it was difficult
to reliably measure light output on various bits. At the time
bit7 and bit1 where highest approx 640 microwatts. Occasionally
got readings higher than 800 microwatts on bit 7.</pre>


<!-- Date: Wed Mar 14 19:01:19 2001 -->
<pre>Retesting B2W6 after measuring light output and reconnecting 
DOIM cable to OFTM. New readout errors have appeared:  
 
R 55 E 10 Error: OO Sequence      Fib 0 Pipe 0 Chip 0: .. 111, 80 .. 
R 55 E 10 Error: OO Sequence      Fib 0 Pipe 4 Chip 9: .. 109, 78 .. 
R 55 E 11 Error: OO Sequence      Fib 0 Pipe 2 Chip 1: .. 57, 26 .. 
R 55 E 21 Error: OO Sequence      Fib 0 Pipe 2 Chip 2: .. 32, 1 .. 
R 55 E 30 Error: OO Sequence      Fib 0 Pipe 0 Chip 2: .. 61, 30 .. 
R 55 E 30 Error: OO Sequence      Fib 0 Pipe 4 Chip 11: .. 59, 28 .. 
R 55 E 40 Error: OO Sequence      Fib 0 Pipe 0 Chip 3: .. 36, 5 .. 
R 55 E 40 Error: OO Sequence      Fib 0 Pipe 4 Chip 12: .. 34, 3 .. 
R 55 E 41 Error: OO Sequence      Fib 0 Pipe 2 Chip 3: .. 111, 80 .. 
R 55 E 60 Error: OO Sequence      Fib 0 Pipe 1 Chip 0: .. 111, 80 .. 
R 55 E 60 Error: OO Sequence      Fib 0 Pipe 4 Chip 13: .. 113, 82 .. 
R 55 E 61 Error: OO Sequence      Fib 0 Pipe 2 Chip 5: .. 61, 30 .. 
R 55 E 71 Error: OO Sequence      Fib 0 Pipe 0 Chip 0: .. 62, 31 .. 
R 55 E 71 Error: OO Sequence      Fib 0 Pipe 2 Chip 6: .. 36, 5 .. 
R 55 E 80 Error: OO Sequence      Fib 0 Pipe 1 Chip 2: .. 61, 30 .. 
R 55 E 81 Error: OO Sequence      Fib 0 Pipe 0 Chip 1: .. 37, 6 .. 
 
See online:~svxii/daq/svx/sw/ParseErrors55.log and laser55.svx 
 
HOW CAN WE BE DROPPING THE EXACT SAME BIT ON SEVERAL CHANNELS? 
Fib/Vrb test is OK so its not the Glink? 
 
Also noticed the error appears at the same events even on  
different runs: Check the files ParseErrors53 and 54 taken  
with different consecutive runs! 
 
Is this related to the earlier cell id error? Note that errors  
don't appear on channel 3.</pre>
<!-- Author: Same character as above -->
<!-- Comment: Fri Mar 30 11;17;19 comment by...Not so bad Mary -->
<pre>Steve Nahn points out that its possible that the data pushed
in for the fib/vrb test may not be large enough to populate all 
the VRB memory that is populated by the real data, therefore
some area of memory may not be tested. Repeat Fib/Vrb with 
larger data file and see if this problem appears.</pre>
<!-- Date: Thu Mar 15 12:21:05 2001 -->
<pre>tested from upstairs.  
found fission errors in VRB slot 12 b0svx02, reset button didn't  
work, power crate. We got only two errors in 2000 events, pipe 1, 
bit 5. We see rails (1 count) in all five layers. Saved histos  
and raw data (laser60.svx).</pre>
<!-- Author: Mary/Petra -->


<!-- Date: Thu Mar 15 12:22:39 2001 -->
<table><tr><td><a href=/elog/notebooks/silicon_pc/e260-SVX-C-BRL-W-End-P-6/Thu_Mar_15_2001_122225.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=e260-SVX-C-BRL-W-End-P-6&action=view&page=-4  align='top'></td><td>histos from biased wedge, seeing the rails</a></td></tr></table>
<!-- Author: Petra -->


<!-- Date: Mon Mar 26 18:14:30 2001 -->
<pre>Rechecked from B0 control room. R0 errors persist 
 
1) L4 drops bit 1  
 
2) Much rarer stuck bit5 on several channels.</pre>
<!-- Author: Slave of the nile -->



<!-- Date: Sun Apr 1 18:40:22 2001 -->
<pre>I believe OFTM was replaced BUT, readout problems still there 
 
1) Bit 5 dropped on several channels: 
 
R 103 E 15 Error: OO Sequence      Fib 0 Pipe 4 Chip 3: .. 108, 77 .. 
R 103 E 30 Error: OO Sequence      Fib 0 Pipe 4 Chip 9: .. 53, 22 .. 
R 103 E 31 Error: OO Sequence      Fib 0 Pipe 3 Chip 3: .. 60, 29 .. 
R 103 E 45 Error: OO Sequence      Fib 0 Pipe 1 Chip 1: .. 125, 94 .. 
R 103 E 45 Error: OO Sequence      Fib 0 Pipe 3 Chip 1: .. 97, 66 .. 
 
2) L0 data is major screwed up see  
 
~svxii/daq/svx/sw/data/laser105.svx and laser107.svx 
</pre>
<!-- Author: M. Bishai -->
<!-- Comment: Sun Apr  1 18;42;38 comment by...M. Bishai -->
<pre>Made ~svxii/daq/svx/sw/fib_mrb.fifo with 16 chips worth of data and ran fib2vrb test - no errors. This was to find out whether
bit5 errors on several channels were a bug in the VRB output
fifo which hadn't been picked up before because we were
running tests with fib1k.fifo which only had 5 chips worth of
data.

Don't have any idea now what may be wrong.  </pre>


<!-- Date: Tue Apr 10 12:55:50 2001 -->
I did some standalone testing on this wedge, check this entry  
in the <a href= 
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=19&frame=2&anchor=21:20:17'>silicon e-log. 
</a> 
<!-- Author: Petra -->


<!-- Date: Wed Apr 11 10:31:39 2001 -->
<pre>swapped the OFTM: 
 
old: serial #117, FNAL #563177 
new: serial #113, FNAL #564032 
 
 
the old one had intermittend OBDV on ch.0 and no OBDV on ch.7,8</pre>
<!-- Author: Mary -->
<!-- Comment: Wed Apr 11 11;59;02 comment by...Mary -->
<pre>Actually channel's 7,8 data was 0 - no fib headers or EOR 
characters. </pre>


<!-- Date: Wed Apr 11 12:03:28 2001 -->
<pre>After changing OFTM. Layer 0 reads out fine BUT Layer 2 now  
drops bit 6 (0x40). No readout errors from channels  
0,1,3,4,5,6,8,9. reading out simultaneously in standalone mode. </pre>
<!-- Author: Mary B. Tony F. -->


<!-- Date: Wed Apr 18 15:02:32 2001 -->
<pre>Layer 2 does not work due to lower light level (30-90uW) on data bit 6.  The light level measured depends on the connection.  The ladder will work or not depending on the connection, the particular receiver, and the CPC temperature. 
 
 
Layer 0 has really high light output (>1mW for data bits 2, 4, and 7).  This was probably the cause of the previous problems with this channel.  If it goes bad in the run we should turn it off and ignore it. 
 
</pre>
<!-- Author: tony -->


<!-- Date: Sat May 12 07:56:00 2001 -->
<pre>cable bundle plugged back into power supply after cratezilla  
effect, crate 5, slot 2. 
 
Retested already plugged wedge: currents ok, histos ok, all init. 
        Bias tested ok. L2 still shows RO errors as before (low  
        light output).</pre>
<!-- Author: Petra -->


<!-- Date: Sat May 12 07:58:01 2001 -->
<pre>I also RTVed that wedge into the slot.</pre>
<!-- Author: Petra -->


<!-- Date: Tue May 29 10:00:45 2001 -->
Pre Plug Close Checkout: 
<ul> 
<li> All Channels Init ok 
<li> Chan 0 reads back only c4s (Light output too high is known) 
Reading out alone with new firmware it truncates, but with other channels gives c4c4c4c4 
<li> Chan 2 drops bits (Light output too low is known) 
<li> Above problems also cause c4 problem in other channels, 
which is fixed by new firmware 
<li> L1, L3, L4 ok Unbiased Run: laser392.svx  Biased Run laser393.svx (Rails!) 
</ul>
<!-- Author: SCN -->


<!-- Date: Fri Jun 22 13:29:52 2001 -->
<pre>Retested for integration. 
 
L0 trips overvoltage on bias (2V demand) 
L2 bit 6 low occasionally. 
 
Otherwise OK</pre>
<!-- Author: Lester -->
<!-- Comment: Thu Oct 25 13;15;21 comment by...herndon -->
<pre>Layer 0 bias seems broken, will remove power supply when one is available.</pre>
<!-- Date: Tue Jun 26 23:37:20 2001 -->
<pre>Pre-access test: 
SB2W6: confirm that L2 has bit 6 low </pre>
<!-- Author: Saverio -->
<!-- Comment: Tue Jun 26 23;39;07 comment by...Sav -->
Sometimes, not all chips, probably not all events.


<!-- Date: Tue Jun 26 23:46:38 2001 -->
<pre>Running with the other "good" wedges I find something strange: 
FIB related, looks like. Did not find direct reference to this 
so I report it here, it is probably a known problem. 
 
R 346 E 99 Error:Not Chip ID      Fib 0 Pipe 0  Chip 0  0 received 
R 346 E 99 Error: PcA Byte         Fib 0 Expect c4, Recieve e2 Pipe 1 
R 346 E 99 Error: Bxing Byte       Fib 0 Expect c4, Recieve 5 Pipe 1 
R 346 E 99 Error: PcA Byte         Fib 0 Expect c4, Recieve e2 Pipe 3 
R 346 E 99 Error: Bxing Byte       Fib 0 Expect c4, Recieve 5 Pipe 3 
R 346 E 99 Error: PcA Byte         Fib 0 Expect c4, Recieve e2 Pipe 4 
R 346 E 99 Error: Bxing Byte       Fib 0 Expect c4, Recieve 5 Pipe 4 
</pre>
<!-- Author: Saverio -->


<!-- Date: Sun Oct 21 09:09:48 2001 -->
new but historical problems<br> 
 
<a href= 
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=72&frame=2&anchor=16:08:44'> 
Oct 16 FTM access survey </a>  
 
<br> 
sb2w6l2 - bit 6 low  - vdoim 
<!-- Author: jean -->



<!-- Date: Mon Oct 29 20:29:44 2001 -->
<pre>SB2W6L0 Undervoltage on Bias.</pre>
<!-- Author: Saverio -->


<!-- Date: Thu Nov 8 16:45:34 2001 -->
<pre>summary from the access for L0 
============================== 
Pretest: Bias overvoltage 
	*	Not true! but a lot of FIB/FTM problems are reported on the PC elog  
 
%%% shows bias UV trip ! 
CHECK QUALITY OF CABLES (resistance measurements) OF DVDD AND AVDD 
replace PS and do LIB test... 
Now it has only OFTM ploblems left...</pre>
<!-- Author: Petra -->


<!-- Date: Thu Nov 8 19:57:24 2001 -->
<pre>Looking for cause of bad bit on L2 by checked light levels in bore 
 
1. flashlight test Ok 
2. measurements (octopus numbering) 
  9    8  7   6   5    4  3  2   obdv 
 324 444 400 380 364 320 50 460 360 
 
this is consistent  with reported bit problem</pre>
<!-- Author: jean, Lester -->


<!-- Date: Tue Nov 13 22:44:26 2001 -->
<h>CAN SOMEONE PLEASE MAKE THE DAMN <I>BOOKMARKS CHANGED ON DISK<\I> GARBAGE GO AWAY</B>
<!-- Author: hah -->


<!-- Date: Fri Feb 1 13:41:48 2002 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=e260-SVX-C-BRL-W-End-P-6&action=view&page=-5&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=e260-SVX-C-BRL-W-End-P-6&action=view&page=-5  width='300' align='top'></td><td>Plot from SB2W6L0PC0, "stuckbit3chipSB2W6L0PC0(180)"</a></td></tr></table>
<!-- Author: Steve Wolbers -->


<!-- Date: Fri Feb 1 13:43:48 2002 -->
<pre>This error showed up in Silimon -- talked to Gino who asked us to enter this in the logbook.  Many other stuckbit and unbiasedchip and zeroADC errors as well.</pre>
<!-- Author: Steve Wolbers -->