<!-- Title: Eve shift. Fri Apr 13, 2001 -->
<!-- SciCo: Steve Tether -->
<!-- DAQAce: Valdimir Nagaslaev -->
<!-- MonAce: Ben Kilminster -->
<!-- CO: Youngdo Oh -->
<!-- OpManager: &nbsp; -->
<!-- Notes: -->
<pre>We have to do all calibrations except CLC QIE and LED, then a Rick run. Afterward we run cosmics with L2 processors and Si if possible.</pre>


<!-- Date: Fri Apr 13 16:07:34 2001 -->
<table><tr><td><a href=/cgi/elog/elog.pl?nb=2001&action=view&page=-635&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/elog.pl?nb=2001&action=view&page=-635  width='300' align='top'></td><td>Something weird happened to the trigger rate of run 111959.  The Low Pt Muon stub trigger just sky-rocketed it's acceptance as if it were OR'ed with the ZERO BIAS trigger. </a></td></tr></table>
<!-- Author: Ben -->


<!-- Date: Fri Apr 13 16:10:05 2001 -->
Run 111959 with CMU_noise_test_04_13, inherited from 
the previous shift stopped. Muon people do not seem happy... 
326K events.  
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?111959' target=_top>111959</a>) -->


<!-- Date: Fri Apr 13 16:11:39 2001 -->
<table><tr><td><a href=/cgi/elog/elog.pl?nb=2001&action=view&page=-636&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/elog.pl?nb=2001&action=view&page=-636  width='300' align='top'></td><td>What happened here ? Why is CMU LOW PT Stub all of a sudden looking like the ZERO BIAS trigger?  Greg ...</a></td></tr></table>
<!-- Author: Ben -->


<!-- Date: Fri Apr 13 16:34:09 2001 -->
giving up b0ccal13 used for the fer tests with new run control. 
Led/Xef calibrations should be working now.  
<!-- Author: Andrew K. -->


<!-- Date: Fri Apr 13 16:36:51 2001 -->
<pre>Trying to run integrate with new silicon.  
Run crashes into BUSY condition after the VRB header dump: 
(MLE) b0l3gate1.fnal.gov:main:4:25:09 PM->Host b0eb17.fnal.gov, task tRec_0
SCPU-P0-E-BadVrbByteCount: Event 421 total byte count is lt 32, gt 65528, or not divisible by 8 for VRB in slot 16.
Count = 3618.                                                                                                           
(MLE) b0l3gate1.fnal.gov:main:4:25:09 PM->Host b0eb17.fnal.gov, task tRec_0 
SCPU-P0-E-VrbHeader: Dump of header words for event 421 from VRB in slot 16: 
0x0e220a1a 0x00000000 0x00000000 0xe0610000 0x85287cfc 0x012c002e 0x03290229 0x05270429 
(MLE) b0l3gate1.fnal.gov:main:4:25:10 PM->Host b0eb19.fnal.gov, task tRec_0 
SCPU-P0-E-VrbReadFailed: Error reading VRB in slot 16 for event 423.                                
                     (MLE) b0l3gate1.fnal.gov:main:4:25:10 PM->Host b0eb18.fnal.gov, task tRec_0 
SCPU-P0-E-VrbReadFailed: Error reading VRB in slot 16 for event 423. 
The VRB had no event. 
(MLE) b0l3gate1.fnal.gov:main:4:25:10 PM->Host b0eb21.fnal.gov, task tRec_0 
SCPU-P0-E-VrbReadFailed: Error reading VRB in slot 12 for event 423. 
The VRB had no event. 
(MLE) b0l3gate1.fnal.gov:main:4:25:10 PM->Host b0eb20.fnal.gov, task tRec_0 
SCPU-P0-E-VrbReadFailed: Error reading VRB in slot 12 for event 423. 
The VRB had no event. 
(MLE) b0l3gate1.fnal.gov:main:4:25:10 PM->Host b0eb25.fnal.gov, task tRec_0 
SCPU-P0-E-VrbReadFailed: Error reading VRB in slot 10 for event 423. 
The VRB had no event. 
(MLE) b0l3gate1.fnal.gov:main:4:25:11 PM->Host b0eb19.fnal.gov, task tRec_0 
SCPU-P0-E-VrbReadFailed: Error reading VRB in slot 18 for event 423. 
The VRB had no event. 
(MLE) b0l3gate1.fnal.gov:main:4:25:11 PM->Host b0eb20.fnal.gov, task tRec_0 
SCPU-P0-E-VrbReadFailed: Error reading VRB in slot 16 for event 423. 
   HRR does not recover the run.  Mary is looking at it now.

</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?111962' target=_top>111962</a>) -->
<!-- Comment: Fri Apr 13 16;47;11 comment by...Ben -->
<pre>First Error points to bad data from silicon.

(MLE) b0l3gate1.fnal.gov:main:4:25:09 PM->Host b0eb17.fnal.gov, task tRec_0
SCPU-P0-E-BadVrbByteCount: Event 421 total byte count is lt 32, gt 65528, or not divisible by 8 for VRB in slot 16.
Count = 3618.                                                                                                           </pre>


<!-- Comment: Sat Apr 14 20;14;02 comment by...Vladimir -->
<pre>The other byte counts from this and neighbor runs, as requested by Mary:
errorfile111931.log:Count = 3618.   *
errorfile111931.log:Count = 3618.   *
errorfile111962.log:Count = 3618.   *
errorfile111962.log:Count = 2586.
errorfile111973.log:Count = 1038.   *
errorfile111973.log:Count = 2586.   *
errorfile111973.log:Count = 3618.   *
errorfile111973.log:Count = 1804.</pre>
<!-- Date: Fri Apr 13 16:47:58 2001 -->
<table border=0><td><tr><td bgcolor=#e0e030><pre>I just updated run control with Andrew's fixes to the LED/XEF 
calibration code. This means: if there is a chance, please 
reboot the ccal crates (so that they pick up the new code), and 
take LED/FLASHPED/XEF calibration runs with the new run control. 
 
If successfull, please use the new run control from now on. 
</pre></td></tr></td></table>
<!-- Author: Arnd -->


<!-- Date: Fri Apr 13 16:53:59 2001 -->
<pre>CCAL13 returned. We integrated it back, but it fail with DONE. 
It seems that configuration does not match real map... dropping... 

  We are running
</pre>
<!-- Author: Vladimir -->


<!-- Date: Fri Apr 13 17:07:25 2001 -->
<pre>Got the same error after 35K events. Now HRR helped.</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?111973' target=_top>111973</a>) -->


<!-- Date: Fri Apr 13 17:16:13 2001 -->
<pre>Again the same SCPU complain: byte count 2586 from VRB (eb21) 
not divisible by 8. BUSY after 83K events. Continue after HRR. 
</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?111973' target=_top>111973</a>) -->


<!-- Date: Fri Apr 13 17:22:21 2001 -->
<pre>Continuing error from b0eb17,  vxb svx 00. 

(MLE) b0l3gate1.fnal.gov:main:5:18:00 PM->Host b0eb17.fnal.gov, task tRec_0 
SCPU-P0-E-BadVrbByteCount: Event 100032 total byte count is lt 32, gt 65528, or not divisible by 8 for VRB in slot 16. 
Count = 3618.                                                                                                            
 
count = 3618 is not divisible by 8. 



Mary is here and we are trying to give her some input as to
what the problem could be.  Since they are in readout all mode,
the count should always be the same.  We are seeing that
this count is different each time the error repeats.  Also, 
the error comes from different event builders, and different
vrb svx crates. 

This error repeats itself ~ n*10 K events.


</pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111973' target=_top>111973</a>) -->


<!-- Date: Fri Apr 13 17:38:36 2001 -->
<pre>Silicon people are sparsifying data to see if it has any effect 
on the "count not divisible by 8" error.</pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111976' target=_top>111976</a>) -->


<!-- Date: Fri Apr 13 17:47:14 2001 -->
<pre>JC called and talked me through disabling GAMMA display on 
IFIX.</pre>
<!-- Author: Ben -->


<!-- Date: Fri Apr 13 17:51:01 2001 -->
<pre>Reformatter errors from FIB 16,CHANNEL 3: 
 
(MLE) b0l3gate2.fnal.gov:main:5:46:24 PM->Error on L3 node b0l3111 (partition 0) Fri Apr 13 17:46:23 2001 l3_node 
  in refoInt_reformatProc (l3_refevt.c:610) 
  @L3_REFORMAT_ERROR 
  
RAWREF Error - UTILSILDEC - with code 38 -- START 
 Line -  299 in: src/library/rr_rawevt.c 
 Buffer position: 18619 
 Error count: 1 of 1 
 Reject rate: 0.090 percent 
  
 Detector ID not known (yet?). 
 FIB id found: 
  0xc4e26338 
  
 Error location code: 0x00008010 
  
  
 Crate Id?: 0x00000000 
  
 Error during scanning MINI structure! 
 Last Unit prob. worked on (all counts from 0): 
  SCPU: 8 
  VRB : 0 
  LINK: 1 
  MINI: 0 
  
 Buffer (18599 until posi+2=18621) 
 0x76652055  0x20746e65  0x67617266  0x746e656d  0x2a2a2a20  0x0000002a 
 0x01000000  0x00000000  0x014f5800  0x00000000  0x00000000  0x10000000 
 0x26000000  0x00000000  0x00000000  0x00000000  0xfc3861e2  0xaa00aaff 
 0xf3fff305  0xc1c1aa7f  0x3863e2c4  0x005510fc  0x17f33f18 
  
  
 NOTE: Event rejected! 
  
RAWREF Error - UTILSILDEC - with code 38 -- FINISHED: L<  835 
  
                                                                                                                       </pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111976' target=_top>111976</a>) -->


<!-- Date: Fri Apr 13 18:03:45 2001 -->
<pre>HRR did not help in previous run. Run ended and Coldstarted. 
We ran now 32K events until a reformatter error. 
(MLE) b0l3gate2.fnal.gov:main:5:58:53 PM->Error on L3 node b0l3114 (partition 0) Fri Apr 13 17:58:49 2001 l3_node 
  in refoInt_reformatProc (l3_refevt.c:610) 
  @L3_REFORMAT_ERROR 
  
RAWREF Error - UTILSILDEC - with code 38 -- START 
 Line -  299 in: src/library/rr_rawevt.c 
 Buffer position: 17453 
 Error count: 1 of 1 
 Reject rate: 0.143 percent 
  
 Detector ID not known (yet?). 
 FIB id found: 
  0xc2e36e3c 
  
 Error location code: 0x00008010 
  
  
 Crate Id?: 0x00000000 
  
 Error during scanning MINI structure! 
 Last Unit prob. worked on (all counts from 0): 
  SCPU: 8 
  VRB : 0 
  LINK: 1 
  MINI: 0 
  
 Buffer (17433 until posi+2=17455) 
 0x08180717  0xf3220219  0x02240523  0x06270426  0x022a0328  0x072c072b 
 0xf33b022d  0x033d073c  0xf33f063e  0x08420441  0x0644f343  0xf3570245 
 0x07590758  0xf368015a  0xf36a0b69  0x026c066b  0x05730372  0xf37ff374 
 0x0000c1c1  0x00000000  0x3c6ee3c2  0x031084f9  0x131884f8 
  
  
 NOTE: Event rejected! 
  
RAWREF Error - UTILSILDEC - with code 38 -- FINISHED: L<  835 
  
  </pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?111977' target=_top>111977</a>) -->


<!-- Date: Fri Apr 13 18:18:41 2001 -->
<pre>Uncoalesced proton beam in Tevatron. 
</pre>
<!-- Author: Ben -->


<!-- Date: Fri Apr 13 18:24:22 2001 -->
We take b0svt06, b0svt07, XTRP, and XFT, for XTRP/SVT readout test.
<!-- Author: Ashmanskas, Belforte, Eddy -->
<!-- Comment: Fri Apr 13 20;52;13 comment by...Ashmanskas -->
Done.  Some notes in L2 logbook.  Please include XTRP and
SVT (crates 6 and 7) in integration tests when possible.
<!-- Comment: Fri Apr 13 20;55;20 comment by...Ashmanskas -->
Correction: Nathan is still reloading some flash memories, for 
the next 30-45 minutes, so this statement does not apply until
he is done.  (He'll unbook the crates when he's done.)
<!-- Date: Fri Apr 13 18:25:59 2001 -->
Concerning the reformatter errors caused by Si vrb: 
 
This is the nibble shifting problem caused by out of date 
VRB firmware in b0svx02 slot 16 (VRB had been swapped with one 
with an older firmware) I downloaded the latest firmware that should fix this error. 
<!-- Author: Mary Bishai -->


<!-- Date: Fri Apr 13 18:27:42 2001 -->
<pre>Rebooted CCAL crates before attempting calibrations 
as per Arnd's request. 
 
Problem with CCAL 13 goes away after reboot, 
and is now included in the run.</pre>
<!-- Author: Ben -->


<!-- Date: Fri Apr 13 18:33:51 2001 -->
<pre>Trigger DB problems:  
 
b0dap23:23:~>setup fer devel 
ERROR: Error occurred for product 'UPSACT: ' 'TriggerDB' 'devel' 'NULL'. 
ERROR: Invalid number of parameters for action sourceRequired, must be between 2 
 and 3 (found 1) 
WARNING: UPS_SHELL not set using SHELL or default, value = (unknown) 
 
Calling Alexei.</pre>
<!-- Author: Ben -->
<!-- Comment: Fri Apr 13 18;37;15 comment by...Ben -->
<pre>Changes must have been made, now RC starts,
but there is still an error from TriggerDB setup.

b0dap23:21:~>setup fer
CDFVME_COMMON: Last updated by nahn on Thu Mar 23 13:03:15 CST 2000
/cdf/code-common/cdfonline/TriggerDB/devel/ups/alpha_check.csh: No such file or directory.
</pre>


<!-- Comment: Fri Apr 13 18;51;00 comment by...Ben -->
<pre>New error setting up fer: 

b0dap23:21:~>setup fer
CDFVME_COMMON: Last updated by nahn on Thu Mar 23 13:03:15 CST 2000
Permission denied.
IMPORTANT !!!
you DO NOT  have access to build level 2 executables on alpha
when you creare a new trigger table,
ask Stephen Miller to compile level 2 executables for you

Alexei must still be working.</pre>
<!-- Date: Fri Apr 13 18:39:36 2001 -->
<pre>Strange but not Fatal errors: 
 
Crate CCAL 15 is missing SMX READOUT 45 in slot 3 
Crate CCAL 15 is missing SMX READOUT 46 in slot 4 
Crate CMX 01 is missing   TDC CMX 12  in slot 3</pre>
<!-- Author: Ben -->



<!-- Date: Fri Apr 13 19:13:58 2001 -->
  We are starting L2 torture test with L2_torture_v1[101] <br>
Mary believes she's fixed the problem of reformatter (note above) 
We're going to run in silicon sparse mode. 
XFT and XTRP are released on request. WCAL is booked by Ivan.<br> 
 
  RC seems to have died. It stopped responding in the ColdStart <br>
transition. No action is possible (Abort, Ab/Rst, Reset). <br>
Exited and started RC again.  <br>
 
  RC hangs after 4 events, errors reading VRB. b0tsi2 is in <br>
a funky state. Reboot it. <br>
 
  DArn!  <br>
 
Vrb read errors and BUSY timeout after 18 events: <br>
(MLE) b0l3gate1.fnal.gov:main:7:09:34 PM->Host b0eb15.fnal.gov,<br> task tRec_0 
SCPU-P0-E-VrbReadFailed: Error reading VRB in slot 10 for event 1. 
The VRB had no event. <br>
eb15 is b0vrb04.  <br>
  
9'44" 3 crate/s: b0ccal03(3), b0ccal05(5), b0svx02(112),  busy.[RXPT]                        
                            
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?111988' target=_top>111988</a>) -->


<!-- Date: Fri Apr 13 19:57:11 2001 -->
<pre>Not clear what's wrong with VRB04. It reads out calorimeters. 
Trying 3 things: we've invluded missing wcal02, corrected 
configuration in ccal15 and rebooted ccal again (there 
is a chance that when rebooting them I've missed one) 
Cleaned up vrb and L3. 
Starting again. The run froze at 7 L2 accepts. No errors.</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?111992' target=_top>111992</a>) -->


<!-- Date: Fri Apr 13 19:59:05 2001 -->
We are looking at CES/CCR/CPR calibrations from run 111921, 
taken on day shift April 13.  It looks like the wedge addresses 
are now fixed on the east- I see 36-44 which corresponds to 
12-20 east, which we have instrumented. However the west 
wedges in DBANA are now 0-1 and 15-23, not 9-17 which 
should be present. 
<!-- Author: wicklund :: (run <a href='/cgi-bin/runSummaryRun.cgi?111921' target=_top>111921</a>) -->


<!-- Date: Fri Apr 13 20:07:30 2001 -->
<pre>Level 2 is choking in state 14 after 2 events. 
 
Here is the output from  ~jsm/alpha/alpha_check : 
 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
Info: Alpha is okay. Currently at spot 7: Started Handshake with TSI 
 TSI handshake bits are 4fff0006 
 TSI startload bits are 10101b4 
 TSI MODDONE bits are 4007ffff 
 Number of words for TL2D, buffer 0: 8b000000 
 Number of words for TL2D, buffer 1: 8b000000 
 Number of words for TL2D, buffer 2: 8f000000 
 Number of words for TL2D, buffer 3: 8f000000 
 Address for DMA buffer 0 is  8f000000 
 Address for DMA buffer 1 is  8f000000 
 Address for DMA buffer 2 is  8f000000 
 Address for DMA buffer 3 is  8f000000 
 Address for DMA buffer 4 is  8f000000 
 Address for DMA buffer 5 is  8f000000 
 Address for DMA buffer 6 is  8f000000 
 Address for DMA buffer 7 is  8f000000 
 Address for DMA buffer 8 is  8f000000 
 Address for DMA buffer 9 is  8f000000 
 Executable name is  l2exe/L2_TORTURE_v-1_B0L2PR00                                                                       
 
</pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111994' target=_top>111994</a>) -->


<!-- Date: Fri Apr 13 20:14:09 2001 -->
<pre>STATE 14 Level 2 -- contents of error registers on GL2 board: 
 
    SELECTED SLAVE = gl2 
 
     0    =     Exit VISIONdemo 
     1    =     New VISION slave 
     2    =     Select VISION slave 
     3    =     Set Options for slave 
     4    =     Single-word (interactive) Read/Write 
     5    =     Write-Read-Compare test 
     6    =     Dump (read) Block from slave 
     7    =     Fill (write) Block to slave 
     8    =     Map crate 
     9    =     Set Master Options 
    10    =     Install Interrupt Handler 
    11    =     Scope loop 
 
    VISIONdemo-> 4 
To abort an operation, use a period (.) 
Single read/write operations on gl2 
   Offset? [0000200C] (hex):  200c 
                 [000083FE]  Change to: 
   Offset? [0000200C] (hex):  2010 
                 [000083FE]  Change to: 
   Offset? [00002010] (hex):  2014 
                 [00008025]  Change to: 
   Offset? [00002014] (hex): 
                 [00008025]  Change to: 
   Offset? [00002014] (hex): 
                 [00008025]  Change to: 
   Offset? [00002014] (hex): 
                 [00008025]  Change to: 
   Offset? [00002014] (hex):  2018 
                 [00008274]  Change to: 
   Offset? [00002018] (hex):  201c 
                 [00008270]  Change to: 
   Offset? [0000201C] (hex):  . 
Operation ended.                                                                                                        </pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111994' target=_top>111994</a>) -->


<!-- Date: Fri Apr 13 20:19:22 2001 -->
<pre>After 3 HRR's : 
 
    VISIONdemo-> 4 
To abort an operation, use a period (.) 
Single read/write operations on gl2 
   Offset? [0000201C] (hex):  200c 
                 [000083FE]  Change to: 
   Offset? [0000200C] (hex):  2010 
                 [000083FE]  Change to: 
   Offset? [00002010] (hex):  2014 
                 [00008005]  Change to: 
   Offset? [00002014] (hex):  2018 
                 [00008274]  Change to: 
   Offset? [00002018] (hex):  201c 
                 [00008270]  Change to: 
   Offset? [0000201C] (hex): 
                 [00008270]  Change to: 
   Offset? [0000201C] (hex):  . 
Operation ended.                                                                                                        </pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111994' target=_top>111994</a>) -->


<!-- Date: Fri Apr 13 20:20:36 2001 -->
<pre>After another HRR:  
 
    VISIONdemo-> 4 
To abort an operation, use a period (.) 
Single read/write operations on gl2 
   Offset? [0000201C] (hex):  200c 
                 [000083FE]  Change to: 
   Offset? [0000200C] (hex):  2010 
                 [000083FE]  Change to: 
   Offset? [00002010] (hex):  2014 
                 [00008025]  Change to: 
   Offset? [00002014] (hex):  2018 
                 [00008274]  Change to: 
   Offset? [00002018] (hex):  201c 
                 [00008270]  Change to: 
   Offset? [0000201C] (hex):                                                                                            </pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111994' target=_top>111994</a>) -->


<!-- Date: Fri Apr 13 20:26:38 2001 -->
<pre>Because the number of events after each HRR was not constant, 
we thought it was worth noting: 
 
ACTIVATE  :  2 events 
first HRR :  6 additional events 
2nd HRR   :  4 additional  
3rd HRR   :  5 additional 
4th HRR   :  1 additional 
 
 </pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111944' target=_top>111944</a>) -->


<!-- Date: Fri Apr 13 20:27:09 2001 -->
<pre>Going to the L2_Rate_test[1,101] table now.</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?1111995' target=_top>1111995</a>) -->


<!-- Date: Fri Apr 13 20:28:03 2001 -->
<pre>TOF Calib signal Timing in. 
 
 
We succeeded doing a first rought Time to Amplitude Converter 
with the DDG. 
 
- DDG fired one every five buch crossings (interval1 = 4) 
 
- Readout with standalone program the content of the  
  L1 pipeline buffers  
 
- Scanning trought different Calib signals delays (from -20ns 
  to 30ns) We compared the L1 buffer value and the DDG setting. 
  and overall time resolution of ~20 ps	 
 
- Scanning the CalibInterval setting from 1 to 5. Run 
  numbers 111978-111981 and 11983 ( we could not find where 
  the data is stored in the pipeline) 
 
- Scanning DDG delay in multiple of 132  and keeping 
  CalibInterval to one (We read out not zero TDC values) 
  Run number 111985 
	 
 
</pre>
<!-- Author: Ivan & Rolf :: (run <a href='/cgi-bin/runSummaryRun.cgi?111985' target=_top>111985</a>) -->
<!-- Comment: Fri Apr 13 20;29;05 comment by...Ivan -->
We did not make a TAC, we calibrated the TAC....;-)


<!-- Date: Fri Apr 13 20:29:40 2001 -->
<pre>Level2_rate_test. 
 
Level 2 turns state 14 with zero events triggered 
 
output of jsm/alpha/alpha_check > & ~/level2.alpha_check.apr13.b : 
 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
FISION: Input/output error (0x5): VME BERR received! 
Info: Alpha is okay. Currently at spot 7: Started Handshake with TSI 
 TSI handshake bits are 4fff0002 
 TSI startload bits are 10101a4 
 TSI MODDONE bits are 4007ffff 
 Number of words for TL2D, buffer 0: 8f000000 
 Number of words for TL2D, buffer 1: 8b000000 
 Number of words for TL2D, buffer 2: 8f000000 
 Number of words for TL2D, buffer 3: 8f000000 
 Address for DMA buffer 0 is  8f000000 
 Address for DMA buffer 1 is  8f000000 
 Address for DMA buffer 2 is  8f000000 
 Address for DMA buffer 3 is  8f000000 
 Address for DMA buffer 4 is  8f000000 
 Address for DMA buffer 5 is  8f000000 
 Address for DMA buffer 6 is  8f000000 
 Address for DMA buffer 7 is  8f000000 
 Address for DMA buffer 8 is  8f000000 
 Address for DMA buffer 9 is  8f000000 
 Executable name is  l2exe/L2_RATE_TEST_v-1_B0L2PR00                                                                    </pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111955' target=_top>111955</a>) -->


<!-- Date: Fri Apr 13 20:30:52 2001 -->
<pre>From GL2 Board:  
 
    VISIONdemo-> 4 
To abort an operation, use a period (.) 
Single read/write operations on gl2 
   Offset? [0000201C] (hex):  200c 
                 [000083FE]  Change to: 
   Offset? [0000200C] (hex):  2010 
                 [000083FE]  Change to: 
   Offset? [00002010] (hex):  2014 
                 [00008005]  Change to: 
   Offset? [00002014] (hex):  2018 
                 [00008274]  Change to: 
   Offset? [00002018] (hex):  201c 
                 [00008270]  Change to: 
   Offset? [0000201C] (hex):  . 
Operation ended.                                                                                                        </pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111995' target=_top>111995</a>) -->


<!-- Date: Fri Apr 13 20:39:39 2001 -->
<pre>Effect of HRR: 
 
ACTIVATE:  0 events 
1st HRR :  0 events 
2nd HRR :  0 events 
3rd HRR :  4 events 
4th HRR :  1 additional event 
 
After 4 HRR,  here are the registers: 
 
Single read/write operations on gl2 
   Offset? [0000200C] (hex):  200c 
                 [000083FE]  Change to: 
   Offset? [0000200C] (hex):  2010 
                 [000083FE]  Change to: 
   Offset? [00002010] (hex):  2014 
                 [00008005]  Change to: 
   Offset? [00002014] (hex):  2018 
                 [00008274]  Change to: 
   Offset? [00002018] (hex):  Partition Flushed: 0 event_id:4 
201c 
                 [00008270]  Change to: 
   Offset? [0000201C] (hex): 
                 [00008270]  Change to: 
   Offset? [0000201C] (hex):  . 
Operation ended. 
  </pre>
<!-- Author: Ben :: (run <a href='/cgi-bin/runSummaryRun.cgi?111995' target=_top>111995</a>) -->




<!-- Date: Fri Apr 13 21:02:06 2001 -->
<pre>I have changed just the trigger table back to DRY_RUN_TABLE_1[3,83], all the configuration stays the same. 
No it runs, trigger rate is 200Hz.</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?111997' target=_top>111997</a>) -->


<!-- Date: Fri Apr 13 21:20:13 2001 -->
<pre>Stephen Miller calls in and we explain the level 2 situation. 
He suggests switching the Alpha from  
 
NOT in tagging mode  to   In tagging mode.  
 
We will try this when we are done with calibrations.</pre>
<!-- Author: Ben -->


<!-- Date: Fri Apr 13 21:29:23 2001 -->
<pre>Done QIE calibrations. IT take LONG time for data to get 
into the database. Tables appear in the browser 15-20 minuts later. 
</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?111998,111999' target=_top>111998,111999</a>) -->


<!-- Date: Fri Apr 13 21:35:59 2001 -->
<pre>Ran LED calibrations. Calibrations ended with no error 
messages. We'll keep going and check later if they appear 
in the DB.  
  Well, it's there! The first DBANA plot I selected looks fine. 
</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?112000' target=_top>112000</a>) -->


<!-- Date: Fri Apr 13 21:50:22 2001 -->
<pre>Went to check on WARNING on PSM that had been here since 
at the beginning of the shift. 
 
End Plug Power Supply Monitoring: 
	smdpw 06 
	communication error:  no response from PS. 
 
This timed in at around 2:30 pm today and has been a warning  
since. 
</pre>
<!-- Author: Ben -->


<!-- Date: Fri Apr 13 21:57:23 2001 -->
<pre>Turning CMU HV off for a noise check.</pre>
<!-- Author: hyunsoo -->


<!-- Date: Fri Apr 13 22:00:13 2001 -->
<pre>XEF pedestals   112001 
XEF		112002 
CEMFLASHPED is in DB, CEMXEF is not yet... 
</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?112002' target=_top>112002</a>) -->


<!-- Date: Fri Apr 13 22:16:32 2001 -->
<pre>Thanks Ben for reading the GL2 registers. 
For what it is worth I looked at the results 
and the GL2 itself is not detecting any 
L2P <-> TS protocol problem.  With only one 
L2Processor active (3rd one, bit mask entry = 4) 
the only problem that GL2 could detect would 
be if the L2P was sending L2A=L2R=1.  Mismatch 
L2 buffer detection has to take place in the 
TS and one would have to look at the TS error 
register page. 
 
If one is inclined to check the GL2 registers 
in the again in the near future it is sufficient 
to first check offset 201c; if the result is not 
odd the GL2 has not detected a problem.  If the 
result is odd then it is worth checking the address 
offset corresponding to the L2Processors in use: 
 
offset 200c	Processor 1 (mask entry =1) 
offset 2010     Processor 2 (mask entry =2) 
offset 2014     Processor 3 (mask entry =4) 
offset 2018     Processor 4 (mask entry =8) 
(the result has to be odd for a processor in 
use, otherwise the result is irrelevant). 
 
Probably more information than you wanted to 
know, but at least now the shift crew can 
make an informed decision as to whether to 
look (prior to issuing Recover, of course).</pre>
<!-- Author: Michael Schmidt -->
<!-- Comment: Fri Apr 13 22;30;47 comment by...Michael Schmidt -->
<pre>Added note: the contents of offset 2014 in
each case indicated that a L2R was being received
from the L2P for either L2 buffer 0 or 1.
So I hope `NOT tagging' means that the L2P
was supposed to be sending rejects.
</pre>
<!-- Date: Fri Apr 13 22:19:20 2001 -->
<pre>Five minutes after XEF calibration, CHA, CEN and WHA HV are  
not yet being reported on IFIX. 
 
10 minutes after XEF,  CHA is finally reported on IFIX, 
but not others yet...</pre>
<!-- Author: Ben -->
<!-- Comment: Fri Apr 13 22;29;21 comment by...Ben -->
<pre>20 minutes after CEM shows up on High Voltage Monitor.
</pre>
<!-- Comment: Fri Apr 13 22;29;51 comment by...Ben -->
<pre>Shortly after noticing CEM,  WHA shows up.</pre>
<!-- Date: Fri Apr 13 22:20:41 2001 -->
<pre>COT pulser calibrations done. No errors. Don't see data in DB. 
</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?112003' target=_top>112003</a>) -->


<!-- Date: Fri Apr 13 22:26:42 2001 -->
Muon calibrations. No error messages.
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?112004' target=_top>112004</a>) -->


<!-- Date: Fri Apr 13 22:29:01 2001 -->
<pre>CMU back on standby.</pre>
<!-- Author: hyunsoo -->





<!-- Date: Fri Apr 13 22:59:09 2001 -->
<pre>SMX calibrations- seem to end fine. 
This is odd: Error display is absolutely happy, but 
no data appears in the database! No XEF, no COT, no SMX. 
</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?1120 -112008' target=_top>11205 -112008</a>) -->


<!-- Date: Fri Apr 13 23:16:59 2001 -->
<pre>TOF calibrations. Changed partition, restarted RC. 
This calibration is better- at least "Fail" messages. 
Part of messages: 
b0wcal04) QIE calib: slot 05, qie 00:Fail 14: Sigma(off) big     , val 01.0668, cap 0, rng2. 
(b0wcal04) QIE calib: slot 05, qie 02:Fail 14: Sigma(off) big     , val 01.1050, cap 0, rng1. 
(b0wcal04) QIE calib: slot 05, qie 06:Fail 14: Sigma(off) big     , val 01.3054, cap 0, rng4. 
(b 
 
(b0wcal01) QIE calib: slot 10, qie 00:Fail 25: Self Calib Fail    , val 00.0000, cap 0, rng0. 
(b0wcal01) QIE calib: slot 10, qie 01:Fail 25: Self Calib Fail    , val 00.0000, cap 0, rng0. 
(b0wcal01) QIE calib: slot 10, qie 02:Fail 25: Self Calib Fail    , val 00.0000, cap 0, rng0.                            

This calibration has shown up in the DB.
 
</pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?112009' target=_top>112009</a>) -->



<!-- Date: Fri Apr 13 23:40:20 2001 -->
<pre>Started Rick's run. 
After 11K events BUSY timeout: 
(MLE) b0l3gate1.fnal.gov:main:11:36:37 PM->Host b0eb16.fnal.gov, task tRec_0 
SCPU-P0-E-TracerEventId: Event 11412, crate 0, channel 0 has either bad Tracer ID or bad markers around Tracer word. 
 Tracer word event ID is 14, should be 4. 
Tracer word = 0x7e7e0500 (I think). 
Channel data = 0x000000bb 0x7e240029 0x50484144 0x000c0007 0x00000000 0x00000049 0x00000001 0x0dd60034 ... 
... 0x00000002 0x02000000 0x00000000 0xaa000000 0x55aaaaaa 0x29555555 0x7e7e0500 0x80000000 
(MLE) b0l3gate1.fnal.gov:main:11:36:37 PM->Host b0eb16.fnal.gov, task tRec_0 
SCPU-P0-E-TracerEventId: Event 11412, crate 0, channel 3 has either bad Tracer ID or bad markers around Tracer word. 
 Tracer word event ID is 4, should be 4. 
Tracer word = 0x54540500 (I think). 
Channel data = 0x000000bb 0x5424002c 0x50454d44 0x000c000a 0x00000000 0x00000051 0x00000001 0x0ad40031 ... 
... 0x00000002 0x02000000 0x00000000 0xaa000000 0x55aaaaaa 0x2c555555 0x54540500 0x80000000 
(MLE) b0l3gate1.fnal.gov:main:11:36:37 PM->Host b0eb16.fnal.gov, task tRec_0 
SCPU-P0-E-VrbHeader: Dump of header words for event 11412 from VRB in slot 12: 
0x00000000 0x00001688 0x00130093 0x04f4031c 0x032004f4 0x03180320 0x00000000 0x00000000 
36'50" 5 crate/s: b0ccal04(4), b0ccal05(5), b0ccal12(12), b0ccal13(13), b0ccal14(14),  busy.[RXPT]          
 
 continue after HRR. 
             </pre>
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?112012' target=_top>112012</a>) -->


<!-- Date: Fri Apr 13 23:41:17 2001 -->
The clock on b0dap29 is an hour behind, so of course kinit always fails.  
<!-- Author: Steve Tether -->


<!-- Date: Fri Apr 13 23:42:44 2001 -->
Rick's run stopped with 40K events.
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?112012' target=_top>112012</a>) -->


<!-- Date: Fri Apr 13 23:50:40 2001 -->
We ran SMX calibration again, this time checking the CSL 
logs. CSL received and sent the bank of 9.5Mbyte size, with 
no complaints. Front end messages do not appear in the 
RC error display.  
<!-- Author: Vladimir :: (run <a href='/cgi-bin/runSummaryRun.cgi?112013' target=_top>112013</a>) -->


<!-- Date: Fri Apr 13 23:52:23 2001 -->
<font color=red>Shift Summary: </font><pre>New RC used for everything. 
 
Si integration early in the shift: 
  Intermittent invalid byte counts in some event headers. 
    Cured by turning on sparsification. 
  Nibble-shifting errors in one VRB. 
    Cured by updating the VRB's firmware. 
 
Trial of new L2-testing trigger tables: 
  L2_TORTURE-V1 got L2 stuck in state 14 right away. HRR ineffective. 
  L2_RATE_TEST-V1 got L2 stuck in state 14 right away. HRR ineffective. 
  
Calibrations attempted: 
  Cal-QIE - OK 
  Cal-LED - OK 
  Cal-XEF - apparently OK but never showed up in DB 
  COT - apparently OK, no DB 
  MUON - OK 
  SMX - apparently OK, no DB 
  TOF - one bad crate, DB 
 
Rick run OK 
</pre> 
<br><b>End of Shift Numbers</b>
<table><tr><td width=60% align=left>
<b>CDF Run II <p></b>                       
<pre>
Runs                   111959-112013
Delivered Luminosity   0  pb-1
Acquired Luminosity    0  pb-1
Efficiency             0
   
</td></tr></table></pre>
<!-- Author: Steve Tether -->


<!-- Date: Sat Apr 14 00:12:30 2001 -->
<pre>The L2 rate test and L2 torture test can be run in 
L2 tagging mode or non-tagging mode. To switch between 
modes, run ~jsm/alpha/alphatag_linux  anytime before coldstart. 
 
Try running the L2 rate test in non-tagging mode. This will 
likely give the state 14 errors again. I have emailed 
cdf-aces@fnal.gov to give further instructions on handling 
this error.   
Also, keep doing HRR a few times and then record the L1 and L2 
rates from the trigger rate monitor window. This will help 
us in changing the physics table to a more reasonable L1 rate 
if necessary. 
 
Then put the alpha in tagging mode and run the L2 torture test. 
Record if there are state 14 errors. If it runs fine, take 
20k - 50K events, if the time is reasonable. 
 
Thanks.</pre> <font color=red><cite>(entry outside this shift's time range )</cite></font>
<!-- Author: Stephen Miller -->