<!-- Title: 10:31:20  Sun Nov  5 2000 -->
<!-- Crewchief: TDC Task Force -->
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<pre>Note problems with installed TDCs; access plans, actions taken</pre>


<!-- Date: Mon Nov 6 09:54:54 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-1&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-1  width='250' align='top'></td><td>This is the hit time distibution for COT TDC module id 422 (b0cot07 slot 18) from the first 1000 events of run 103512. This TDC is responsible for the "funny bump" at large hit  times in recent SL6 YMON plots. Note that the shape of this  distrbution looks OK. The shift from the expected times  (t0 should be ~140 ns) is consistent with time bit 9 stuck  high, i.e. the reported times are 2^9 = 512 ns larger than  the actual times. </a></td></tr></table>
<!-- Author: Ron Moore -->
<!-- Comment: Mon Nov  6 09;57;03 comment by...Ron -->
<pre>The TDC currently there is a large-via board.

This crate/slot has had previous problems, so perhaps there is
a problem with the slot and not the TDCs that went there.  We
should investigate more when the opportunity arises.</pre>


<!-- Date: Fri Nov 10 12:57:43 2000 -->
<pre>Using 11 ECL TDCs borrowed from muon crates, I ran XTC->Finder tests for 
crates b0cot00, b0cot04, and b0cot15.  There were no errors that would 
be caused by bent pins, bad cables, or faulty transition boards.  This 
is really good news.  However, I did find that there was a dropped data 
bit for one of the ECL TDCs (#214).  The dropped bit moved with the 
board when I tested it in a different slot with a different XTC, so it 
is a problem with the TDC itself. 
 
I installed one LVDS board in each of the following three crates: 
  b0cot00   slot 5   TDC #609   XTC #123 
  b0cot04   slot 14  TDC #653   XTC #228 
  b0cot15   slot 5   TDC #697   XTC #219 
These three boards came from Ron, with modifications up through ECO-4.   
Now every TDC crate contains at least one TDC. 
 
I also had a chance to investigate a couple of XTC->Finder tests errors 
seen in b0cot05, slots 13 (TDC #677) and 17 (TDC #718).  I had been 
unable to capture valid data from the TDCs in these two slots since they 
were installed during the commissioning run.  Today I tried ECL boards 
in these two slots with the same XTC cards and the test ran without 
errors.  Early next week, I request that we swap out these two TDCs 
and replace them. 
 
  
 
</pre>
<!-- Author: Jay Dittmann -->


<!-- Date: Mon Nov 13 11:19:53 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-5&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-5  width='250' align='top'></td><td>Investigating TDC board hangs in UMICH teststand...  probing VME_DATA(25) at testpoint very near component S1; probing DSP_RESET* at DSP_DC; reading 6K consecutive words starting at FRAM 0 address  0x02400000; triggering on DSP_RESET* going low; GOT IT!</a></td></tr></table>
<!-- Author: Ron Moore -->


<!-- Date: Mon Nov 13 14:29:13 2000 -->
<pre>On Nov 10, we studied the TDC_CALIB signal on on the backplane of 
b0cot18.  Like the CDF_CLK signal this is a differential PECL 
signal driven by the TRACER.  Also like CDF_CLK the lines are 
terminated as single ended TTL lines.  GTDC_CALIB is currently 
only used by the COT TDCs. 
 
The standard COT calibration pulser was replaced with a NIM 
pulser at the pulser crate.  The pulse width was about 70ns. 
The scope was triggered using an output from the 1-3 Fanout for  
reference (top trace of following scope pictures).  Note that  
a long cable amkes this reference appear to come after the  
backplane signals.  The middle trace on the scope pictures is 
the SPY output from the TRACER.  This is the output of a PECL  
receiver which is SPYing on the crate backplane.  The bottom  
trace is from a differential probe looking directly at the backplane. 
 
There are some confusing results of these tests.  It looks like 
the termination should be changed but it should be studied further.  Preferably in a test crate at B0 or WH14.   
</pre>
<!-- Author: Peter Wilson and Bob DeMaat -->


<!-- Date: Mon Nov 13 14:31:23 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-8&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-8  width='250' align='top'></td><td>TDC_CALIB signal in b0cot18 with original termination.   Differential probe is in slot 20.  Note steps in trailing edge from relections.</a></td></tr></table>
<!-- Author: Peter Wilson -->


<!-- Date: Mon Nov 13 14:36:48 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-9&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-9  width='250' align='top'></td><td>TDC_CALIB signal in b0cot18 with 56 ohm termination at Slot 2.  Differential probe is in slot 20.  Note that steps at trailing edge are gone.  Leading edge of pulse  shifts by less than 1ns.</a></td></tr></table>
<!-- Author: Peter Wilon -->


<!-- Date: Mon Nov 13 14:38:25 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-10&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-10  width='250' align='top'></td><td>TDC_CALIB signal in b0cot18 with original termination.   Differential probe is in slot 2.   Again note stir steps  on trailing edge.</a></td></tr></table>
<!-- Author: Peter Wilson -->


<!-- Date: Mon Nov 13 14:41:06 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-11&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-11  width='250' align='top'></td><td>TDC_CALIB signal on b0cot18 with 56 ohm terminator in Slot 2. Differential probe in Slot 2.  Again the terminator has removed  the stair step at the trailing edge.  Note the odd reflection edge in the TRACER SPY output.  This goes away if the  differential probe is reomved from Slot 2 but the terminator is in.</a></td></tr></table>
<!-- Author: Peter Wilson -->


<!-- Date: Wed Nov 15 12:27:44 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-12&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-12  width='250' align='top'></td><td>An example of the RD_SRAM* glitch which can eventually lead to spurious TDC resets.  (RD_SRAM* is an output of the strobes pal.)  Scope triggered on LD(25) glitch during a VME read of FRAM 0.  You see EN_SRAM* and RD_SRAM* asserted  because the DSP is fetching its instructions from SRAM. DATA(25) is driven low by SRAM until RD_SRAM* is deasserted, and then DATA(25) goes tristate.  The  RD_SRAM* glitch allows the SRAMs to momentarily drive the  DATA bus again.  By that time, the famous buffer chips  were already enabled, so the glitch on DATA(25) appears on LD(25).  The VME output drivers were already enabled also, so the glitch made its way onto VME_DATA(25), and could have crosstalked onto SYSRESET*.</a></td></tr></table>
<!-- Author: Ron Moore -->


<!-- Date: Wed Nov 15 12:30:29 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-13&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-13  width='250' align='top'></td><td>spurious board reset (DSP_RESET* asserted low) preceded by a RD_SRAM* glitch</a></td></tr></table>
<!-- Author: Ron Moore -->


<!-- Date: Mon Nov 20 17:16:38 2000 -->
<pre>This afternoon, Peter and I tried to reproduce the VME latchup symptoms 
that were observed regularly in several COT TDC crates last August. 
Since we've not observed the problem recently, we "undid" some 
modifications to configure crates b0cot08 and b0cot09 like they were 
back then.  We: 
 
  - installed TRACERs in b0cot08 and b0cot09 without any 
    modifications to account for grounding at the front panel 
  - temporarily removed the crate grounding 
 
Unfortunately, the test was unsuccessful.  We were unable to observe any 
of the latchup symptoms in either crate -- even with 18 TDCs (+ CPU, 
TRACER, and DAC) installed in b0cot09.  We power-cycled b0cot09 five 
times with the crate full of boards. 
 
</pre>
<!-- Author: Peter Wilson & Jay Dittmann -->


<!-- Date: Tue Dec 12 14:26:34 2000 -->
<pre>EJ brought 9 boards back from PREP today. I installed them into the hadron crate to update FRAM0 (to dsp v31) and run tracktest. While programming boards #336 & #132 either a problem with the db connection occured, or something else. It used calib constants = 0.</pre>
<!-- Author: dan -->


<!-- Date: Wed Dec 13 20:59:16 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-15&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-15  width='300' align='top'></td><td>Reading 8 data words from TDC FIFO using block transfer on a PPC controller.  Yes, there is an extra (9th) DBE0* pulse which causes an additional clocking of the FIFO.  (The data word 0x2100088E is the header word for the next event - it would be lost.)  The block transfer is indicated by address modifier am = 0x0B.  Note that the extra (9th) DBE0* pulse occurs under am = 0x09.</a></td></tr></table>
<!-- Author: Ron Moore -->


<!-- Date: Wed Dec 13 21:11:14 2000 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-16&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=tdc&action=view&page=-16  width='300' align='top'></td><td>For comparison to the above picture, here's a similar block transfer read on a 68K controller.  No extra DBE0* pulse -  the data word 0x80000015 is the last data word of the current event.</a></td></tr></table>
<!-- Author: Ron Moore -->


<!-- Date: Sat Dec 16 11:26:13 2000 -->
<pre>Here's a transcipt of a message that I sent to Eric James: 
 
Hi Eric, 
        I was continuing to have trouble with one fo the modified boards 
while trying to install it in b0cot17.  The board is serial number 634, 
and seems t ohave some serious problem.  The difficult is in programming 
FRAM1.  Whenever you try to program FRAM1, the process proceeds as normal 
and even displays the message: 
 
 FRAM_1 programming complete. 
 
but is then immediately followed by a something around 300 lines of: 
 
FISION: S_errno_EIO (0x5): VME BERR received! 
 
And the board is no longer recognized by tdctstand.  I tried to reprogram 
FRAM0 with the DSP turned off, and this seemed to work fine.  But as soon 
as I tried to reload FRAM1 again, it died.  I've left this board in the 
diagnostic crate and so b0cot17 is missing a card in slot 8 and 19.  Note 
though that slot 8 may be the slot with the missing pin? 
</pre>
<!-- Author: Kirby -->