Xilinx Platform Studio (XPS)
Xilinx EDK 8.1.02 Build EDK_I.20.4

Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

At Local date and time: Fri Nov 03 12:49:58 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make netlist; exit;" started...

****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc2vp30ff1152-6 -lang vhdl  -toplevel no -ti system -st xst system.mhs



Release Xilinx EDK 8.1.02 - platgen EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Command Line: platgen -p xc2vp30ff1152-6 -lang vhdl -toplevel no -ti system -st
xst system.mhs 

Parse system.mhs ...

Read MPD definitions ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...

Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...


Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 77 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 86 - 1
master(s) : 1 slave(s)

Check port drivers...

Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 40 - tool overriding c_num_slaves value 4 to 1
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Modify defaults ...

Creating stub ...



Processing licensed instances ...
Completion time: 0.00 seconds

Creating hardware output directories ...

Managing hardware (BBD-specified) netlist files ...

Managing cache ...

Elaborating instances ...
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:134 - elaborating IP



Writing HDL for elaborated instances ...

Inserting wrapper level ...


Completion time: 0.00 seconds

Constructing platform-level signal connectivity ...


Completion time: 1.00 seconds

Writing (top-level) BMM ...
Writing BMM - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system.bmm

Writing (top-level and wrappers) HDL ...

Generating synthesis project file ...



Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
ppc405_0_wrapper (ppc405_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:32 - Running XST synthesis


ppc405_1_wrapper (ppc405_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:48 - Running XST synthesis


jtagppc_0_wrapper (jtagppc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:54 - Running XST synthesis


reset_block_wrapper (reset_block) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:61 - Running XST synthesis


plb_wrapper (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:77 -
Running XST synthesis


opb_wrapper (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:86 -
Running XST synthesis


plb2opb_wrapper (plb2opb) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:94 - Running XST synthesis


rs232_1_wrapper (rs232_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:107 - Running XST synthesis


plb_bram_if_cntlr_1_wrapper (plb_bram_if_cntlr_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:123 - Running XST synthesis


plb_bram_if_cntlr_1_bram_wrapper (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:134 - Running XST synthesis


dcm_0_wrapper (dcm_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:140
- Running XST synthesis



Running NGCBUILD ...

Rebuilding cache ...



Writing (stub) BMM ...
Writing BMM -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system_stub.bmm

Writing (stub) HDL ...
Total run time: 149.00 seconds


Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"


Release 8.1.02i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> 


TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff1152-6
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Hierarchy Separator                : /

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort                : 1

=========================================================================

=========================================================================
*                          HDL Compilation                              *
=========================================================================


Compiling vhdl file "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" in Library work.


Entity <system> compiled.


Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <system> (Architecture <STRUCTURE>).


Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================



Synthesizing Unit <system>.
    Related source file is "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd".
Unit <system> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================




=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================


Loading device for application Rf_Device from file '2vp30.nph' in environment c:\cad\Xilinx.



Optimizing unit <system> ...



Mapping all equations...


Building and optimizing final netlist ...



=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 4

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# Others                           : 11
#      dcm_0_wrapper               : 1
#      jtagppc_0_wrapper           : 1
#      opb_wrapper                 : 1
#      plb2opb_wrapper             : 1
#      plb_bram_if_cntlr_1_bram_wrapper: 1
#      plb_bram_if_cntlr_1_wrapper : 1
#      plb_wrapper                 : 1
#      ppc405_0_wrapper            : 1
#      ppc405_1_wrapper            : 1
#      reset_block_wrapper         : 1
#      rs232_1_wrapper             : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff1152-6 



=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)



=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1263 / 1263
-------------------------------------------------------------------------
Delay:               0.000ns (Levels of Logic = 0)
  Source:            rs232_1:TX (PAD)
  Destination:       fpga_0_RS232_1_TX_pin (PAD)

  Data Path: rs232_1:TX to fpga_0_RS232_1_TX_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    rs232_1_wrapper:TX     0   0.000   0.000  rs232_1 (fpga_0_RS232_1_TX_pin)
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================
CPU : 10.77 / 10.84 s | Elapsed : 11.00 / 11.00 s
 
--> 

Total memory usage is 175260 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)





Done!

At Local date and time: Fri Nov 03 13:06:49 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make netlist; exit;" started...

****************************************************


Creating system netlist for hardware specification..
****************************************************
platgen -p xc2vp30ff1152-6 -lang vhdl   -st xst system.mhs



Release Xilinx EDK 8.1.02 - platgen EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Command Line: platgen -p xc2vp30ff1152-6 -lang vhdl -st xst system.mhs 

Parse system.mhs ...

Read MPD definitions ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...

Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...


Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 78 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 87 - 1
master(s) : 2 slave(s)

Check port drivers...

Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 40 - tool overriding c_num_slaves value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 44 - tool overriding c_num_intr_inputs value 2 to 1
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000001
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000001
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Modify defaults ...

Processing licensed instances ...
Completion time: 0.00 seconds

Creating hardware output directories ...

Managing hardware (BBD-specified) netlist files ...

Managing cache ...


ppc405 (ppc405_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:32 -
Copying cache implementation netlist
ppc405 (ppc405_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:49 -
Copying cache implementation netlist
jtagppc_cntlr (jtagppc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:55 - Copying cache
implementation netlist
proc_sys_reset (reset_block) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:62 - Copying cache
implementation netlist
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:78 - Copying
cache implementation netlist
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:136 - Copying cache
implementation netlist



Elaborating instances ...
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:136 - elaborating IP



Writing HDL for elaborated instances ...

Inserting wrapper level ...


Completion time: 0.00 seconds

Constructing platform-level signal connectivity ...


Completion time: 0.00 seconds

Writing (top-level) BMM ...
Writing BMM - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system.bmm

Writing (top-level and wrappers) HDL ...

Generating synthesis project file ...



Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
opb_wrapper (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:87 -
Running XST synthesis


plb2opb_wrapper (plb2opb) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:95 - Running XST synthesis


rs232_1_wrapper (rs232_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:108 - Running XST synthesis


plb_bram_if_cntlr_1_wrapper (plb_bram_if_cntlr_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:125 - Running XST synthesis


opb_intc_0_wrapper (opb_intc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:142 - Running XST synthesis


dcm_0_wrapper (dcm_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:152
- Running XST synthesis



Running NGCBUILD ...

Rebuilding cache ...
Total run time: 93.00 seconds


Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"


Release 8.1.02i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff1152-6
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Hierarchy Separator                : /

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort                : 1

=========================================================================



=========================================================================
*                          HDL Compilation                              *
=========================================================================


Compiling vhdl file "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" in Library work.


Entity <system> compiled.
Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================


Analyzing Entity <system> (Architecture <STRUCTURE>).


WARNING:Xst:766 - "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" line 1597: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" line 1603: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" line 1609: Generating a Black Box for component <IBUFG>.
WARNING:Xst:766 - "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" line 1615: Generating a Black Box for component <IBUF>.


Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================



Synthesizing Unit <system>.
    Related source file is "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd".
Unit <system> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================




=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================


Loading device for application Rf_Device from file '2vp30.nph' in environment c:\cad\Xilinx.



Optimizing unit <system> ...



Mapping all equations...


Building and optimizing final netlist ...





=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 4

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# IO Buffers                       : 4
#      IBUF                        : 2
#      IBUFG                       : 1
#      OBUF                        : 1
# Others                           : 12
#      dcm_0_wrapper               : 1
#      jtagppc_0_wrapper           : 1
#      opb_intc_0_wrapper          : 1
#      opb_wrapper                 : 1
#      plb2opb_wrapper             : 1
#      plb_bram_if_cntlr_1_bram_wrapper: 1
#      plb_bram_if_cntlr_1_wrapper : 1
#      plb_wrapper                 : 1
#      ppc405_0_wrapper            : 1
#      ppc405_1_wrapper            : 1
#      reset_block_wrapper         : 1


#      rs232_1_wrapper             : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff1152-6 

 Number of bonded IOBs:                  4  out of    644     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 3.241ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1374 / 1374
-------------------------------------------------------------------------
Delay:               3.241ns (Levels of Logic = 1)
  Source:            rs232_1:TX (PAD)
  Destination:       fpga_0_RS232_1_TX_pin (PAD)

  Data Path: rs232_1:TX to fpga_0_RS232_1_TX_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    rs232_1_wrapper:TX     1   0.000   0.390  rs232_1 (fpga_0_RS232_1_TX)
     OBUF:I->O                 2.851          obuf_1 (fpga_0_RS232_1_TX_pin)
    ----------------------------------------
    Total                      3.241ns (2.851ns logic, 0.390ns route)
                                       (88.0% logic, 12.0% route)

=========================================================================
CPU : 10.59 / 10.67 s | Elapsed : 10.00 / 10.00 s
 
--> 

Total memory usage is 175260 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    0 (   0 filtered)





Done!

At Local date and time: Fri Nov 03 13:10:03 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make netlist; exit;" started...

****************************************************
Creating system netlist for hardware specification..


****************************************************
platgen -p xc2vp30ff1152-6 -lang vhdl  -toplevel no -ti system -st xst system.mhs



Release Xilinx EDK 8.1.02 - platgen EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Command Line: platgen -p xc2vp30ff1152-6 -lang vhdl -toplevel no -ti system -st
xst system.mhs 

Parse system.mhs ...

Read MPD definitions ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...

Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...
Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 78 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 87 - 1
master(s) : 2 slave(s)

Check port drivers...



Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 40 - tool overriding c_num_slaves value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 44 - tool overriding c_num_intr_inputs value 2 to 1
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000001
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000001
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Modify defaults ...

Creating stub ...

Processing licensed instances ...
Completion time: 0.00 seconds

Creating hardware output directories ...

Managing hardware (BBD-specified) netlist files ...

Managing cache ...
ppc405 (ppc405_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:32 -
Copying cache implementation netlist
ppc405 (ppc405_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:49 -
Copying cache implementation netlist
jtagppc_cntlr (jtagppc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:55 - Copying cache
implementation netlist
proc_sys_reset (reset_block) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:62 - Copying cache
implementation netlist
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:78 - Copying
cache implementation netlist
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:87 - Copying
cache implementation netlist


plb2opb_bridge (plb2opb) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:95 - Copying cache
implementation netlist
opb_uartlite (rs232_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:108
- Copying cache implementation netlist
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:125 - Copying cache
implementation netlist
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:136 - Copying cache
implementation netlist
opb_intc (opb_intc_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:142
- Copying cache implementation netlist
dcm_module (dcm_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:152 -
Copying cache implementation netlist

Elaborating instances ...
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:136 - elaborating IP



Writing HDL for elaborated instances ...

Inserting wrapper level ...


Completion time: 1.00 seconds

Constructing platform-level signal connectivity ...


Completion time: 0.00 seconds

Writing (top-level) BMM ...
Writing BMM - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system.bmm

Writing (top-level and wrappers) HDL ...

Generating synthesis project file ...



Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.

Running NGCBUILD ...

Rebuilding cache ...

Writing (stub) BMM ...
Writing BMM -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system_stub.bmm

Writing (stub) HDL ...
Total run time: 7.00 seconds


Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"


Release 8.1.02i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> 


TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff1152-6
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Hierarchy Separator                : /

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort                : 1

=========================================================================

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" in Library work.


Entity <system> compiled.


Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================


Analyzing Entity <system> (Architecture <STRUCTURE>).


Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================



Synthesizing Unit <system>.
    Related source file is "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd".
Unit <system> synthesized.




=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================




=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================


Loading device for application Rf_Device from file '2vp30.nph' in environment c:\cad\Xilinx.



Optimizing unit <system> ...



Mapping all equations...


Building and optimizing final netlist ...



=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 4

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# Others                           : 12
#      dcm_0_wrapper               : 1
#      jtagppc_0_wrapper           : 1
#      opb_intc_0_wrapper          : 1
#      opb_wrapper                 : 1
#      plb2opb_wrapper             : 1
#      plb_bram_if_cntlr_1_bram_wrapper: 1
#      plb_bram_if_cntlr_1_wrapper : 1
#      plb_wrapper                 : 1
#      ppc405_0_wrapper            : 1
#      ppc405_1_wrapper            : 1
#      reset_block_wrapper         : 1
#      rs232_1_wrapper             : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff1152-6 



=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1374 / 1374
-------------------------------------------------------------------------
Delay:               0.000ns (Levels of Logic = 0)
  Source:            rs232_1:TX (PAD)
  Destination:       fpga_0_RS232_1_TX_pin (PAD)

  Data Path: rs232_1:TX to fpga_0_RS232_1_TX_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    rs232_1_wrapper:TX     0   0.000   0.000  rs232_1 (fpga_0_RS232_1_TX_pin)
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================


CPU : 10.52 / 10.59 s | Elapsed : 11.00 / 11.00 s
 
--> 

Total memory usage is 175260 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)





Done!

Warning - opb_intc_0 port Intr width does not match RS232_1_Interrupt&net_sys_irq

Warning - opb_intc_0 port Intr width does not match RS232_1_Interrupt&net_sys_irq&aaa

Warning - opb_intc_0 port Intr width does not match RS232_1_Interrupt&net_sys_irq

At Local date and time: Fri Nov 03 13:22:35 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make netlist; exit;" started...

****************************************************
Creating system netlist for hardware specification..


****************************************************
platgen -p xc2vp30ff1152-6 -lang vhdl  -toplevel no -ti system -st xst system.mhs



Release Xilinx EDK 8.1.02 - platgen EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Command Line: platgen -p xc2vp30ff1152-6 -lang vhdl -toplevel no -ti system -st
xst system.mhs 

Parse system.mhs ...

Read MPD definitions ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...



Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...
Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 73 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 82 - 1
master(s) : 2 slave(s)

Check port drivers...



Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 40 - tool overriding c_num_slaves value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Modify defaults ...

Creating stub ...

Processing licensed instances ...
Completion time: 0.00 seconds

Creating hardware output directories ...

Managing hardware (BBD-specified) netlist files ...

Managing cache ...


ppc405 (ppc405_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:27 -
Copying cache implementation netlist
ppc405 (ppc405_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:44 -
Copying cache implementation netlist
jtagppc_cntlr (jtagppc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:50 - Copying cache
implementation netlist
proc_sys_reset (reset_block) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:57 - Copying cache
implementation netlist
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:73 - Copying
cache implementation netlist
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:82 - Copying
cache implementation netlist
plb2opb_bridge (plb2opb) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:90 - Copying cache
implementation netlist
opb_uartlite (rs232_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:103
- Copying cache implementation netlist
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:120 - Copying cache
implementation netlist


bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:131 - Copying cache
implementation netlist


dcm_module (dcm_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:148 -
Copying cache implementation netlist

Elaborating instances ...
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:131 - elaborating IP



Writing HDL for elaborated instances ...

Inserting wrapper level ...


Completion time: 1.00 seconds

Constructing platform-level signal connectivity ...


Completion time: 0.00 seconds

Writing (top-level) BMM ...
Writing BMM - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system.bmm

Writing (top-level and wrappers) HDL ...

Generating synthesis project file ...



Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
opb_intc_0_wrapper (opb_intc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:137 - Running XST synthesis



Running NGCBUILD ...

Rebuilding cache ...

Writing (stub) BMM ...
Writing BMM -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system_stub.bmm

Writing (stub) HDL ...
Total run time: 23.00 seconds


Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"


Release 8.1.02i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.


--> 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff1152-6
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Hierarchy Separator                : /

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort                : 1

=========================================================================

=========================================================================
*                          HDL Compilation                              *
=========================================================================


Compiling vhdl file "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" in Library work.


Entity <system> compiled.
Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <system> (Architecture <STRUCTURE>).


Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================



Synthesizing Unit <system>.
    Related source file is "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd".
Unit <system> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================




=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================


Loading device for application Rf_Device from file '2vp30.nph' in environment c:\cad\Xilinx.



Optimizing unit <system> ...



Mapping all equations...


Building and optimizing final netlist ...



=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 5

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# Others                           : 12
#      dcm_0_wrapper               : 1
#      jtagppc_0_wrapper           : 1
#      opb_intc_0_wrapper          : 1
#      opb_wrapper                 : 1
#      plb2opb_wrapper             : 1
#      plb_bram_if_cntlr_1_bram_wrapper: 1
#      plb_bram_if_cntlr_1_wrapper : 1
#      plb_wrapper                 : 1
#      ppc405_0_wrapper            : 1
#      ppc405_1_wrapper            : 1
#      reset_block_wrapper         : 1
#      rs232_1_wrapper             : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff1152-6 



=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1375 / 1375
-------------------------------------------------------------------------
Delay:               0.000ns (Levels of Logic = 0)
  Source:            rs232_1:TX (PAD)
  Destination:       fpga_0_RS232_1_TX_pin (PAD)

  Data Path: rs232_1:TX to fpga_0_RS232_1_TX_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    rs232_1_wrapper:TX     0   0.000   0.000  rs232_1 (fpga_0_RS232_1_TX_pin)
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================


CPU : 10.77 / 10.84 s | Elapsed : 11.00 / 11.00 s
 
--> 

Total memory usage is 175260 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)





Done!

At Local date and time: Fri Nov 03 13:34:02 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make libs; exit;" started...

*********************************************
Creating software libraries...


*********************************************
libgen -mhs system.mhs -p xc2vp30ff1152-6  system.mss


libgen
Xilinx EDK 8.1.02 Build EDK_I.20.4
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.



Command Line: libgen -mhs system.mhs -p xc2vp30ff1152-6 system.mss 



Output Directory (-od)		: C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\
Part (-p)			: virtex2p

Software Specification file	: system.mss


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...

Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...
Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 73 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 82 - 1
master(s) : 2 slave(s)

Check port drivers...



Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 40 - tool overriding c_num_slaves value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...


INFO:MDT - List of peripherals addressable from processor instance ppc405_0 : 
  - plb
  - opb
  - RS232_1
  - opb_intc_0
  - plb_bram_if_cntlr_1
INFO:MDT - List of peripherals addressable from processor instance ppc405_1 : 



Building Directory Structure for ppc405_0



Generating platform libraries and device drivers ...

Running CopyFiles ...



Copying files for os standalone_v1_00_a from
C:\cad\EDK\sw\lib\bsp\standalone_v1_00_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\standalone_v1_00_a\ ...



Copying files for driver plbarb_v1_01_a from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\plbarb_v1_01_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\plbarb_v1_01_a\ ...



Copying files for driver opbarb_v1_02_a from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\opbarb_v1_02_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\opbarb_v1_02_a\ ...



Copying files for driver uartlite_v1_01_a from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\uartlite_v1_01_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\uartlite_v1_01_a\ ...



Copying files for driver intc_v1_00_c from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\intc_v1_00_c\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\intc_v1_00_c\ ...



Copying files for driver cpu_ppc405_v1_00_a from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\cpu_ppc405_v1_00_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\cpu_ppc405_v1_00_a\ ...



Running DRCs for OSes, Drivers and Libraries ... 



Running generate for OS'es, Drivers and Libraries ... 



Running post_generate for OS'es, Drivers and Libraries ... 

Running make for Drivers and Libraries ... 

Configuring make for target include using:

make -s include "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 



Configuring make for target libs using:

make -s libs "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 
Compiling common


powerpc-eabi-ar: creating ../../../lib/libxil.a


Compiling bsp


Compiling plb_arbiter


Compiling opbarb


Compiling uartlite


Compiling intc


Compiling cpu_ppc405



Libraries generated in C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\lib\
directory

Running execs_generate for OS'es, Drivers and Libraries ... 

Building Directory Structure for ppc405_1

Generating platform libraries and device drivers ...

Running CopyFiles ...



Copying files for os standalone_v1_00_a from
C:\cad\EDK\sw\lib\bsp\standalone_v1_00_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_1\libsrc\standalone_v1_00_a\ ...



Copying files for driver cpu_ppc405_v1_00_a from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\cpu_ppc405_v1_00_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_1\libsrc\cpu_ppc405_v1_00_a\ ...



Running DRCs for OSes, Drivers and Libraries ... 

Running generate for OS'es, Drivers and Libraries ... 



Running post_generate for OS'es, Drivers and Libraries ... 



Running make for Drivers and Libraries ... 

Configuring make for target include using:

make -s include "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 



Configuring make for target libs using:

make -s libs "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 
Compiling common


powerpc-eabi-ar: creating ../../../lib/libxil.a


Compiling bsp


Compiling cpu_ppc405



Libraries generated in C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_1\lib\
directory

Running execs_generate for OS'es, Drivers and Libraries ... 

LibGen Done. 




Done!

Xilinx Platform Studio (XPS)
Xilinx EDK 8.1.02 Build EDK_I.20.4

Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

Assigned Driver generic 1.00.a for instance opb_ctrl_tables_0

opb_ctrl_tables_0 has been added to the project
Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bram_if_cntlr_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_bridge_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cntlr_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_1_0.tcl ...



Overriding IP level properties ...

bram_block (plb_bram_if_cntlr_1_bram) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p

opb_intc (opb_intc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.mpd line 36 - tool overriding c_family value virtex2 to virtex2p

jtagppc_cntlr (jtagppc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cntlr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 

dcm_module (dcm_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 76 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 76 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x00000000-0x0001ffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Trying to assign some memory to PowerPC reset address.

INFO:MDT - PowerPC reset address is set to plb_bram_if_cntlr_1.

INFO:MDT - Trying to assign some big memory to address 0x0.

INFO:MDT - There is no memory found can be addressed at 0x0.

INFO:MDT - Standard address map is applied.

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Address map generated successfully.

Address generator neglects the following cores because they are not connecting to an addressable bus:ppc405_1


INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format

Overriding IP level properties ...

bram_block (plb_bram_if_cntlr_1_bram) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p

opb_intc (opb_intc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.mpd line 36 - tool overriding c_family value virtex2 to virtex2p

jtagppc_cntlr (jtagppc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cntlr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 

dcm_module (dcm_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x00000000-0x000007ff) opb_ctrl_tables_0	plb->plb2opb->opb

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 76 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 76 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x00000000-0x0001ffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Trying to assign some memory to PowerPC reset address.

INFO:MDT - PowerPC reset address is set to plb_bram_if_cntlr_1.

INFO:MDT - Trying to assign some big memory to address 0x0.

INFO:MDT - There is no memory found can be addressed at 0x0.

INFO:MDT - Standard address map is applied.

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0x77200000-0x7720ffff) opb_ctrl_tables_0	plb->plb2opb->opb

  (0x77220000-0x7722ffff) opb_ctrl_tables_0	plb->plb2opb->opb

  (0x77240000-0x7724ffff) opb_ctrl_tables_0	plb->plb2opb->opb

  (0x77260000-0x7726ffff) opb_ctrl_tables_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Address map generated successfully.

Address generator neglects the following cores because they are not connecting to an addressable bus:ppc405_1


Make instance opb_ctrl_tables_0 port p_mem0_addr external with net as port name

Instance opb_ctrl_tables_0 port p_mem0_addr connector undefined, using opb_ctrl_tables_0_p_mem0_addr

Make instance opb_ctrl_tables_0 port p_mem0_clk external with net as port name

Instance opb_ctrl_tables_0 port p_mem0_clk connector undefined, using opb_ctrl_tables_0_p_mem0_clk

Make instance opb_ctrl_tables_0 port p_mem0_data external with net as port name

Instance opb_ctrl_tables_0 port p_mem0_data connector undefined, using opb_ctrl_tables_0_p_mem0_data

Make instance opb_ctrl_tables_0 port p_mem0_ena external with net as port name

Instance opb_ctrl_tables_0 port p_mem0_ena connector undefined, using opb_ctrl_tables_0_p_mem0_ena

Make instance opb_ctrl_tables_0 port p_mem1_addr external with net as port name

Instance opb_ctrl_tables_0 port p_mem1_addr connector undefined, using opb_ctrl_tables_0_p_mem1_addr

Make instance opb_ctrl_tables_0 port p_mem1_clk external with net as port name

Instance opb_ctrl_tables_0 port p_mem1_clk connector undefined, using opb_ctrl_tables_0_p_mem1_clk

Make instance opb_ctrl_tables_0 port p_mem1_data external with net as port name

Instance opb_ctrl_tables_0 port p_mem1_data connector undefined, using opb_ctrl_tables_0_p_mem1_data

Make instance opb_ctrl_tables_0 port p_mem1_ena external with net as port name

Instance opb_ctrl_tables_0 port p_mem1_ena connector undefined, using opb_ctrl_tables_0_p_mem1_ena

Make instance opb_ctrl_tables_0 port p_mem2_addr external with net as port name

Instance opb_ctrl_tables_0 port p_mem2_addr connector undefined, using opb_ctrl_tables_0_p_mem2_addr

Make instance opb_ctrl_tables_0 port p_mem2_clk external with net as port name

Instance opb_ctrl_tables_0 port p_mem2_clk connector undefined, using opb_ctrl_tables_0_p_mem2_clk

Make instance opb_ctrl_tables_0 port p_mem2_data external with net as port name

Instance opb_ctrl_tables_0 port p_mem2_data connector undefined, using opb_ctrl_tables_0_p_mem2_data

Make instance opb_ctrl_tables_0 port p_mem2_ena external with net as port name

Instance opb_ctrl_tables_0 port p_mem2_ena connector undefined, using opb_ctrl_tables_0_p_mem2_ena

Make instance opb_ctrl_tables_0 port p_mem3_addr external with net as port name

Instance opb_ctrl_tables_0 port p_mem3_addr connector undefined, using opb_ctrl_tables_0_p_mem3_addr

Make instance opb_ctrl_tables_0 port p_mem3_clk external with net as port name

Instance opb_ctrl_tables_0 port p_mem3_clk connector undefined, using opb_ctrl_tables_0_p_mem3_clk

Make instance opb_ctrl_tables_0 port p_mem3_data external with net as port name

Instance opb_ctrl_tables_0 port p_mem3_data connector undefined, using opb_ctrl_tables_0_p_mem3_data

Make instance opb_ctrl_tables_0 port p_mem3_ena external with net as port name

Instance opb_ctrl_tables_0 port p_mem3_ena connector undefined, using opb_ctrl_tables_0_p_mem3_ena

At Local date and time: Fri Nov 03 21:04:45 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make netlist; exit;" started...

****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc2vp30ff1152-6 -lang vhdl  -toplevel no -ti system -st xst system.mhs



Release Xilinx EDK 8.1.02 - platgen EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Command Line: platgen -p xc2vp30ff1152-6 -lang vhdl -toplevel no -ti system -st
xst system.mhs 

Parse system.mhs ...

Read MPD definitions ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...

Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...
Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0x77200000-0x7720ffff) opb_ctrl_tables_0	plb->plb2opb->opb
  (0x77220000-0x7722ffff) opb_ctrl_tables_0	plb->plb2opb->opb
  (0x77240000-0x7724ffff) opb_ctrl_tables_0	plb->plb2opb->opb
  (0x77260000-0x7726ffff) opb_ctrl_tables_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 89 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 98 - 1
master(s) : 3 slave(s)

Check port drivers...



Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 40 - tool overriding c_num_slaves value 4 to 3
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Modify defaults ...

Creating stub ...



Processing licensed instances ...
Completion time: 0.00 seconds

Creating hardware output directories ...

Managing hardware (BBD-specified) netlist files ...
opb_ctrl_tables (opb_ctrl_tables_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:186 - Copying
(BBD-specified) netlist files.

Managing cache ...
ppc405 (ppc405_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:43 -
Copying cache implementation netlist
ppc405 (ppc405_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:60 -
Copying cache implementation netlist
jtagppc_cntlr (jtagppc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:66 - Copying cache
implementation netlist
proc_sys_reset (reset_block) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:73 - Copying cache
implementation netlist
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:89 - Copying
cache implementation netlist
plb2opb_bridge (plb2opb) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:106 - Copying cache
implementation netlist


opb_uartlite (rs232_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:119
- Copying cache implementation netlist
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:136 - Copying cache
implementation netlist


bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:147 - Copying cache
implementation netlist


opb_intc (opb_intc_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:153
- Copying cache implementation netlist


dcm_module (dcm_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:164 -
Copying cache implementation netlist

Elaborating instances ...
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:147 - elaborating IP



Writing HDL for elaborated instances ...

Inserting wrapper level ...


Completion time: 0.00 seconds

Constructing platform-level signal connectivity ...


Completion time: 1.00 seconds

Writing (top-level) BMM ...
Writing BMM - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system.bmm

Writing (top-level and wrappers) HDL ...

Generating synthesis project file ...



Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
opb_wrapper (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:98 -
Running XST synthesis


opb_ctrl_tables_0_wrapper (opb_ctrl_tables_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:186 - Running XST synthesis



Running NGCBUILD ...
opb_ctrl_tables_0_wrapper (opb_ctrl_tables_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:186 - Running NGCBUILD



Rebuilding cache ...

Writing (stub) BMM ...
Writing BMM -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system_stub.bmm

Writing (stub) HDL ...
Total run time: 45.00 seconds


Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"


Release 8.1.02i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> 


TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff1152-6
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Hierarchy Separator                : /

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort                : 1

=========================================================================

=========================================================================
*                          HDL Compilation                              *
=========================================================================


Compiling vhdl file "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" in Library work.


Entity <system> compiled.
Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================


Analyzing Entity <system> (Architecture <STRUCTURE>).


Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================



Synthesizing Unit <system>.
    Related source file is "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd".
Unit <system> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================




=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================


Loading device for application Rf_Device from file '2vp30.nph' in environment c:\cad\Xilinx.



Optimizing unit <system> ...



Mapping all equations...


Building and optimizing final netlist ...



=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 129

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# Others                           : 13
#      dcm_0_wrapper               : 1
#      jtagppc_0_wrapper           : 1
#      opb_ctrl_tables_0_wrapper   : 1
#      opb_intc_0_wrapper          : 1
#      opb_wrapper                 : 1
#      plb2opb_wrapper             : 1
#      plb_bram_if_cntlr_1_bram_wrapper: 1
#      plb_bram_if_cntlr_1_wrapper : 1
#      plb_wrapper                 : 1
#      ppc405_0_wrapper            : 1
#      ppc405_1_wrapper            : 1
#      reset_block_wrapper         : 1
#      rs232_1_wrapper             : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff1152-6 





=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1608 / 1608
-------------------------------------------------------------------------
Delay:               0.000ns (Levels of Logic = 0)
  Source:            rs232_1:TX (PAD)
  Destination:       fpga_0_RS232_1_TX_pin (PAD)

  Data Path: rs232_1:TX to fpga_0_RS232_1_TX_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    rs232_1_wrapper:TX     0   0.000   0.000  rs232_1 (fpga_0_RS232_1_TX_pin)
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================
CPU : 11.30 / 11.39 s | Elapsed : 12.00 / 12.00 s
 
--> 

Total memory usage is 175324 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)





Done!

At Local date and time: Fri Nov 03 21:24:52 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make libs; exit;" started...

*********************************************
Creating software libraries...
*********************************************
libgen -mhs system.mhs -p xc2vp30ff1152-6  system.mss


libgen
Xilinx EDK 8.1.02 Build EDK_I.20.4
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.



Command Line: libgen -mhs system.mhs -p xc2vp30ff1152-6 system.mss 



Output Directory (-od)		: C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\
Part (-p)			: virtex2p

Software Specification file	: system.mss


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...

Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...


Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0x77200000-0x7720ffff) opb_ctrl_tables_0	plb->plb2opb->opb
  (0x77220000-0x7722ffff) opb_ctrl_tables_0	plb->plb2opb->opb
  (0x77240000-0x7724ffff) opb_ctrl_tables_0	plb->plb2opb->opb
  (0x77260000-0x7726ffff) opb_ctrl_tables_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 89 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 98 - 1
master(s) : 3 slave(s)

Check port drivers...

Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 40 - tool overriding c_num_slaves value 4 to 3
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...


INFO:MDT - List of peripherals addressable from processor instance ppc405_0 : 
  - plb
  - opb
  - RS232_1
  - opb_intc_0
  - opb_ctrl_tables_0
  - plb_bram_if_cntlr_1
INFO:MDT - List of peripherals addressable from processor instance ppc405_1 : 



Building Directory Structure for ppc405_0



Generating platform libraries and device drivers ...

Running CopyFiles ...

Copying files for os standalone_v1_00_a from
C:\cad\EDK\sw\lib\bsp\standalone_v1_00_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\standalone_v1_00_a\ ...



Copying files for driver plbarb_v1_01_a from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\plbarb_v1_01_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\plbarb_v1_01_a\ ...



Copying files for driver opbarb_v1_02_a from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\opbarb_v1_02_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\opbarb_v1_02_a\ ...



Copying files for driver uartlite_v1_01_a from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\uartlite_v1_01_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\uartlite_v1_01_a\ ...



Copying files for driver intc_v1_00_c from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\intc_v1_00_c\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\intc_v1_00_c\ ...



Copying files for driver cpu_ppc405_v1_00_a from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\cpu_ppc405_v1_00_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\libsrc\cpu_ppc405_v1_00_a\ ...



Running DRCs for OSes, Drivers and Libraries ... 

Running generate for OS'es, Drivers and Libraries ... 



Running post_generate for OS'es, Drivers and Libraries ... 

Running make for Drivers and Libraries ... 

Configuring make for target include using:

make -s include "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 



Configuring make for target libs using:

make -s libs "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 
Compiling common


powerpc-eabi-ar: creating ../../../lib/libxil.a


Compiling bsp


Compiling plb_arbiter


Compiling opbarb


Compiling uartlite


Compiling intc


Compiling cpu_ppc405



Libraries generated in C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_0\lib\
directory

Running execs_generate for OS'es, Drivers and Libraries ... 

Building Directory Structure for ppc405_1



Generating platform libraries and device drivers ...

Running CopyFiles ...



Copying files for os standalone_v1_00_a from
C:\cad\EDK\sw\lib\bsp\standalone_v1_00_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_1\libsrc\standalone_v1_00_a\ ...



Copying files for driver cpu_ppc405_v1_00_a from
C:\cad\EDK\sw\XilinxProcessorIPLib\drivers\cpu_ppc405_v1_00_a\src\ to
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_1\libsrc\cpu_ppc405_v1_00_a\ ...



Running DRCs for OSes, Drivers and Libraries ... 

Running generate for OS'es, Drivers and Libraries ... 

Running post_generate for OS'es, Drivers and Libraries ... 

Running make for Drivers and Libraries ... 

Configuring make for target include using:

make -s include "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 



Configuring make for target libs using:

make -s libs "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 
Compiling common


powerpc-eabi-ar: creating ../../../lib/libxil.a


Compiling bsp


Compiling cpu_ppc405



Libraries generated in C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\ppc405_1\lib\
directory

Running execs_generate for OS'es, Drivers and Libraries ... 

LibGen Done. 




Done!

Xilinx Platform Studio (XPS)
Xilinx EDK 8.1.02 Build EDK_I.20.4

Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

Assigned Driver generic 1.00.a for instance opb_ctrl_tables_0

opb_ctrl_tables_0 has been added to the project
Xilinx Platform Studio (XPS)
Xilinx EDK 8.1.02 Build EDK_I.20.4

Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

Assigned Driver generic 1.00.a for instance opb_dp_mem_0

opb_dp_mem_0 has been added to the project
Make instance opb_dp_mem_0 port mem_out_ena external with net as port name

Instance opb_dp_mem_0 port mem_out_ena connector undefined, using opb_dp_mem_0_mem_out_ena

Make instance opb_dp_mem_0 port mem_out_data external with net as port name

Instance opb_dp_mem_0 port mem_out_data connector undefined, using opb_dp_mem_0_mem_out_data

Make instance opb_dp_mem_0 port mem_out_clk external with net as port name

Instance opb_dp_mem_0 port mem_out_clk connector undefined, using opb_dp_mem_0_mem_out_clk

Make instance opb_dp_mem_0 port mem_out_addr external with net as port name

Instance opb_dp_mem_0 port mem_out_addr connector undefined, using opb_dp_mem_0_mem_out_addr

Make instance opb_dp_mem_0 port mem_in_ena external with net as port name

Instance opb_dp_mem_0 port mem_in_ena connector undefined, using opb_dp_mem_0_mem_in_ena

Make instance opb_dp_mem_0 port mem_in_data external with net as port name

Instance opb_dp_mem_0 port mem_in_data connector undefined, using opb_dp_mem_0_mem_in_data

Make instance opb_dp_mem_0 port mem_in_addr external with net as port name

Instance opb_dp_mem_0 port mem_in_addr connector undefined, using opb_dp_mem_0_mem_in_addr

Make instance opb_dp_mem_0 port mem_in_clk external with net as port name

Instance opb_dp_mem_0 port mem_in_clk connector undefined, using opb_dp_mem_0_mem_in_clk

Assigned Driver generic 1.00.a for instance opb_dp_mem_1

opb_dp_mem_1 has been added to the project
Make instance opb_dp_mem_1 port mem_in_addr external with net as port name

Instance opb_dp_mem_1 port mem_in_addr connector undefined, using opb_dp_mem_1_mem_in_addr

Make instance opb_dp_mem_1 port mem_in_clk external with net as port name

Instance opb_dp_mem_1 port mem_in_clk connector undefined, using opb_dp_mem_1_mem_in_clk

Make instance opb_dp_mem_1 port mem_in_data external with net as port name

Instance opb_dp_mem_1 port mem_in_data connector undefined, using opb_dp_mem_1_mem_in_data

Make instance opb_dp_mem_1 port mem_in_ena external with net as port name

Instance opb_dp_mem_1 port mem_in_ena connector undefined, using opb_dp_mem_1_mem_in_ena

Make instance opb_dp_mem_1 port mem_out_addr external with net as port name

Instance opb_dp_mem_1 port mem_out_addr connector undefined, using opb_dp_mem_1_mem_out_addr

Make instance opb_dp_mem_1 port mem_out_clk external with net as port name

Instance opb_dp_mem_1 port mem_out_clk connector undefined, using opb_dp_mem_1_mem_out_clk

Make instance opb_dp_mem_1 port mem_out_data external with net as port name

Instance opb_dp_mem_1 port mem_out_data connector undefined, using opb_dp_mem_1_mem_out_data

Make instance opb_dp_mem_1 port mem_out_ena external with net as port name

Instance opb_dp_mem_1 port mem_out_ena connector undefined, using opb_dp_mem_1_mem_out_ena

INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format
Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bram_if_cntlr_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_bridge_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cntlr_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_1_0.tcl ...



Overriding IP level properties ...

bram_block (plb_bram_if_cntlr_1_bram) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p

opb_intc (opb_intc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.mpd line 36 - tool overriding c_family value virtex2 to virtex2p

jtagppc_cntlr (jtagppc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cntlr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 

dcm_module (dcm_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x00000000-0x0001ffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Trying to assign some memory to PowerPC reset address.

INFO:MDT - PowerPC reset address is set to plb_bram_if_cntlr_1.

INFO:MDT - Trying to assign some big memory to address 0x0.

INFO:MDT - There is no memory found can be addressed at 0x0.

INFO:MDT - Standard address map is applied.

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Address map generated successfully.

Address generator neglects the following cores because they are not connecting to an addressable bus:ppc405_1,opb_dp_mem_1


INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format

Overriding IP level properties ...

bram_block (plb_bram_if_cntlr_1_bram) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p

opb_intc (opb_intc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.mpd line 36 - tool overriding c_family value virtex2 to virtex2p

jtagppc_cntlr (jtagppc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cntlr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 

dcm_module (dcm_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x00000000-0x0001ffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Trying to assign some memory to PowerPC reset address.

INFO:MDT - PowerPC reset address is set to plb_bram_if_cntlr_1.

INFO:MDT - Trying to assign some big memory to address 0x0.

INFO:MDT - There is no memory found can be addressed at 0x0.

INFO:MDT - Standard address map is applied.

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Address map generated successfully.

Address generator neglects the following cores because they are not connecting to an addressable bus:ppc405_1,opb_dp_mem_1


Xilinx Platform Studio (XPS)
Xilinx EDK 8.1.02 Build EDK_I.20.4

Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format
INFO:MDT - Converting address to hexadecimal format
Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bram_if_cntlr_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_bridge_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cntlr_v2_1_0.tcl ...


Sourcing tcl file C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_1_0.tcl ...



Overriding IP level properties ...

bram_block (plb_bram_if_cntlr_1_bram) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p

opb_intc (opb_intc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.mpd line 36 - tool overriding c_family value virtex2 to virtex2p

jtagppc_cntlr (jtagppc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cntlr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 

dcm_module (dcm_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x00000000-0x000007ff) opb_dp_mem_0	plb->plb2opb->opb

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x00000000-0x0001ffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Trying to assign some memory to PowerPC reset address.

INFO:MDT - PowerPC reset address is set to plb_bram_if_cntlr_1.

INFO:MDT - Trying to assign some big memory to address 0x0.

INFO:MDT - There is no memory found can be addressed at 0x0.

INFO:MDT - Standard address map is applied.

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0x73e00000-0x73e0ffff) opb_dp_mem_0	plb->plb2opb->opb

  (0x7d800000-0x7d80ffff) opb_dp_mem_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Address map generated successfully.

Address generator neglects the following cores because they are not connecting to an addressable bus:ppc405_1,opb_dp_mem_1



Overriding IP level properties ...

bram_block (plb_bram_if_cntlr_1_bram) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p

opb_intc (opb_intc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.mpd line 36 - tool overriding c_family value virtex2 to virtex2p

jtagppc_cntlr (jtagppc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cntlr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 

dcm_module (dcm_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0x73e00000-0x73e0ffff) opb_dp_mem_0	plb->plb2opb->opb

  (0x7d800000-0x7d80ffff) opb_dp_mem_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\_xps_tempmhsfilename.mhs line 92 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\_xps_tempmhsfilename.mhs line 92 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x00000000-0x0001ffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Trying to assign some memory to PowerPC reset address.

INFO:MDT - PowerPC reset address is set to plb_bram_if_cntlr_1.

INFO:MDT - Trying to assign some big memory to address 0x0.

INFO:MDT - There is no memory found can be addressed at 0x0.

INFO:MDT - Standard address map is applied.

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0x73e00000-0x73e0ffff) opb_dp_mem_0	plb->plb2opb->opb

  (0x7d800000-0x7d80ffff) opb_dp_mem_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Address map generated successfully.

Address generator neglects the following cores because they are not connecting to an addressable bus:ppc405_1,opb_dp_mem_1



Overriding IP level properties ...

bram_block (plb_bram_if_cntlr_1_bram) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p

opb_intc (opb_intc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.mpd line 36 - tool overriding c_family value virtex2 to virtex2p

jtagppc_cntlr (jtagppc_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cntlr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 

dcm_module (dcm_0) - C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x00000000-0x000007ff) opb_dp_mem_1	plb->plb2opb->opb

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0x73e00000-0x73e0ffff) opb_dp_mem_0	plb->plb2opb->opb

  (0x7d800000-0x7d80ffff) opb_dp_mem_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

WARNING:MDT - plb2opb_bridge (plb2opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - ADDRESS specified by PARAMETER C_RNG0_BASEADDR is ignored

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x00000000-0x0001ffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Trying to assign some memory to PowerPC reset address.

INFO:MDT - PowerPC reset address is set to plb_bram_if_cntlr_1.

INFO:MDT - Trying to assign some big memory to address 0x0.

INFO:MDT - There is no memory found can be addressed at 0x0.

INFO:MDT - Standard address map is applied.

Address Map for Processor ppc405_1

Address Map for Processor ppc405_0

  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb

  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb

  (0x73e00000-0x73e0ffff) opb_dp_mem_1	plb->plb2opb->opb

  (0x73e20000-0x73e2ffff) opb_dp_mem_0	plb->plb2opb->opb

  (0x7d800000-0x7d80ffff) opb_dp_mem_1	plb->plb2opb->opb

  (0x7d820000-0x7d82ffff) opb_dp_mem_0	plb->plb2opb->opb

  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb

INFO:MDT - Address map generated successfully.

Address generator neglects the following cores because they are not connecting to an addressable bus:ppc405_1


ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

At Local date and time: Sun Nov 05 15:21:45 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make netlist; exit;" started...

****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc2vp30ff1152-6 -lang vhdl  -toplevel no -ti system -st xst system.mhs



Release Xilinx EDK 8.1.02 - platgen EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Command Line: platgen -p xc2vp30ff1152-6 -lang vhdl -toplevel no -ti system -st
xst system.mhs 

Parse system.mhs ...



Read MPD definitions ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...



Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...


Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0x73e00000-0x73e0ffff) opb_dp_mem_1	plb->plb2opb->opb
  (0x73e20000-0x73e2ffff) opb_dp_mem_0	plb->plb2opb->opb
  (0x7d800000-0x7d80ffff) opb_dp_mem_1	plb->plb2opb->opb
  (0x7d820000-0x7d82ffff) opb_dp_mem_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 89 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 98 - 1
master(s) : 4 slave(s)

Check port drivers...

Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Modify defaults ...

Creating stub ...



Processing licensed instances ...
Completion time: 0.00 seconds

Creating hardware output directories ...

Managing hardware (BBD-specified) netlist files ...
opb_dp_mem (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:186 - Copying
(BBD-specified) netlist files.
opb_dp_mem (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:206 - Copying
(BBD-specified) netlist files.

Managing cache ...
ppc405 (ppc405_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:43 -
Copying cache implementation netlist
ppc405 (ppc405_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:60 -
Copying cache implementation netlist
jtagppc_cntlr (jtagppc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:66 - Copying cache
implementation netlist
proc_sys_reset (reset_block) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:73 - Copying cache
implementation netlist
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:89 - Copying
cache implementation netlist
plb2opb_bridge (plb2opb) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:106 - Copying cache
implementation netlist
opb_uartlite (rs232_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:119
- Copying cache implementation netlist


plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:136 - Copying cache
implementation netlist
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:147 - Copying cache
implementation netlist


opb_intc (opb_intc_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:153
- Copying cache implementation netlist


dcm_module (dcm_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:164 -
Copying cache implementation netlist

Elaborating instances ...
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:147 - elaborating IP



Writing HDL for elaborated instances ...

Inserting wrapper level ...


Completion time: 1.00 seconds

Constructing platform-level signal connectivity ...


Completion time: 0.00 seconds

Writing (top-level) BMM ...
Writing BMM - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system.bmm

Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
opb_wrapper (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:98 -
Running XST synthesis


opb_dp_mem_0_wrapper (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:186 - Running XST synthesis


opb_dp_mem_1_wrapper (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:206 - Running XST synthesis



Running NGCBUILD ...
opb_dp_mem_0_wrapper (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:186 - Running NGCBUILD


opb_dp_mem_1_wrapper (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:206 - Running NGCBUILD



Rebuilding cache ...

Writing (stub) BMM ...
Writing BMM -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system_stub.bmm

Writing (stub) HDL ...
Total run time: 60.00 seconds


Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"


Release 8.1.02i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.


--> 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff1152-6
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Hierarchy Separator                : /

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort                : 1

=========================================================================

=========================================================================
*                          HDL Compilation                              *
=========================================================================


Compiling vhdl file "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" in Library work.


Entity <system> compiled.
Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <system> (Architecture <STRUCTURE>).


Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================



Synthesizing Unit <system>.
    Related source file is "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd".
Unit <system> synthesized.




=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================




=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================


Loading device for application Rf_Device from file '2vp30.nph' in environment c:\cad\Xilinx.



Optimizing unit <system> ...



Mapping all equations...


Building and optimizing final netlist ...



=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 129

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# Others                           : 14
#      dcm_0_wrapper               : 1
#      jtagppc_0_wrapper           : 1
#      opb_dp_mem_0_wrapper        : 1
#      opb_dp_mem_1_wrapper        : 1
#      opb_intc_0_wrapper          : 1
#      opb_wrapper                 : 1
#      plb2opb_wrapper             : 1
#      plb_bram_if_cntlr_1_bram_wrapper: 1
#      plb_bram_if_cntlr_1_wrapper : 1
#      plb_wrapper                 : 1
#      ppc405_0_wrapper            : 1
#      ppc405_1_wrapper            : 1
#      reset_block_wrapper         : 1
#      rs232_1_wrapper             : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff1152-6 



=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis


  Total number of paths / destination ports: 1717 / 1717
-------------------------------------------------------------------------
Delay:               0.000ns (Levels of Logic = 0)
  Source:            rs232_1:TX (PAD)
  Destination:       fpga_0_RS232_1_TX_pin (PAD)

  Data Path: rs232_1:TX to fpga_0_RS232_1_TX_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    rs232_1_wrapper:TX     0   0.000   0.000  rs232_1 (fpga_0_RS232_1_TX_pin)
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================
CPU : 11.30 / 11.38 s | Elapsed : 11.00 / 11.00 s
 
--> 

Total memory usage is 176284 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)





Done!

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

At Local date and time: Sun Nov 05 15:23:04 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make netlist; exit;" started...

make: Nothing to be done for `netlist'.




Done!

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

At Local date and time: Sun Nov 05 15:23:10 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make hwclean; exit;" started...

rm -f implementation/system.ngc


rm -f implementation/system.bmm
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm 
rm -rf implementation synthesis xst hdl


rm -rf xst.srp system.srp




Done!

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

At Local date and time: Sun Nov 05 15:23:15 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make netlist; exit;" started...

****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc2vp30ff1152-6 -lang vhdl  -toplevel no -ti system -st xst system.mhs



Release Xilinx EDK 8.1.02 - platgen EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Command Line: platgen -p xc2vp30ff1152-6 -lang vhdl -toplevel no -ti system -st
xst system.mhs 



Parse system.mhs ...

Read MPD definitions ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...

Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...


Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0x73e00000-0x73e0ffff) opb_dp_mem_1	plb->plb2opb->opb
  (0x73e20000-0x73e2ffff) opb_dp_mem_0	plb->plb2opb->opb
  (0x7d800000-0x7d80ffff) opb_dp_mem_1	plb->plb2opb->opb
  (0x7d820000-0x7d82ffff) opb_dp_mem_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 89 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 98 - 1
master(s) : 4 slave(s)

Check port drivers...

Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Modify defaults ...

Creating stub ...



Processing licensed instances ...
Completion time: 0.00 seconds

Creating hardware output directories ...

Managing hardware (BBD-specified) netlist files ...
opb_dp_mem (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:186 - Copying
(BBD-specified) netlist files.


opb_dp_mem (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:206 - Copying
(BBD-specified) netlist files.

Managing cache ...

Elaborating instances ...
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:147 - elaborating IP



Writing HDL for elaborated instances ...

Inserting wrapper level ...


Completion time: 1.00 seconds

Constructing platform-level signal connectivity ...


Completion time: 0.00 seconds

Writing (top-level) BMM ...
Writing BMM - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system.bmm

Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
ppc405_0_wrapper (ppc405_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:43 - Running XST synthesis


ppc405_1_wrapper (ppc405_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:60 - Running XST synthesis


jtagppc_0_wrapper (jtagppc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:66 - Running XST synthesis


reset_block_wrapper (reset_block) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:73 - Running XST synthesis


plb_wrapper (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:89 -
Running XST synthesis


opb_wrapper (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:98 -
Running XST synthesis


plb2opb_wrapper (plb2opb) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:106 - Running XST synthesis


rs232_1_wrapper (rs232_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:119 - Running XST synthesis


plb_bram_if_cntlr_1_wrapper (plb_bram_if_cntlr_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:136 - Running XST synthesis


plb_bram_if_cntlr_1_bram_wrapper (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:147 - Running XST synthesis


opb_intc_0_wrapper (opb_intc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:153 - Running XST synthesis


dcm_0_wrapper (dcm_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:164
- Running XST synthesis


opb_dp_mem_0_wrapper (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:186 - Running XST synthesis


opb_dp_mem_1_wrapper (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:206 - Running XST synthesis



Running NGCBUILD ...
opb_dp_mem_0_wrapper (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:186 - Running NGCBUILD


opb_dp_mem_1_wrapper (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:206 - Running NGCBUILD



Rebuilding cache ...

Writing (stub) BMM ...
Writing BMM -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system_stub.bmm

Writing (stub) HDL ...
Total run time: 187.00 seconds


Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"


Release 8.1.02i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.


--> 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff1152-6
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Hierarchy Separator                : /

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort                : 1

=========================================================================

=========================================================================
*                          HDL Compilation                              *
=========================================================================


Compiling vhdl file "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" in Library work.


Entity <system> compiled.
Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================


Analyzing Entity <system> (Architecture <STRUCTURE>).


Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================



Synthesizing Unit <system>.
    Related source file is "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd".
Unit <system> synthesized.




=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================




=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================


Loading device for application Rf_Device from file '2vp30.nph' in environment c:\cad\Xilinx.



Optimizing unit <system> ...



Mapping all equations...


Building and optimizing final netlist ...



=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 129

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# Others                           : 14
#      dcm_0_wrapper               : 1
#      jtagppc_0_wrapper           : 1
#      opb_dp_mem_0_wrapper        : 1
#      opb_dp_mem_1_wrapper        : 1
#      opb_intc_0_wrapper          : 1
#      opb_wrapper                 : 1
#      plb2opb_wrapper             : 1
#      plb_bram_if_cntlr_1_bram_wrapper: 1
#      plb_bram_if_cntlr_1_wrapper : 1
#      plb_wrapper                 : 1
#      ppc405_0_wrapper            : 1
#      ppc405_1_wrapper            : 1
#      reset_block_wrapper         : 1
#      rs232_1_wrapper             : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff1152-6 



=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1717 / 1717
-------------------------------------------------------------------------
Delay:               0.000ns (Levels of Logic = 0)
  Source:            rs232_1:TX (PAD)
  Destination:       fpga_0_RS232_1_TX_pin (PAD)

  Data Path: rs232_1:TX to fpga_0_RS232_1_TX_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    rs232_1_wrapper:TX     0   0.000   0.000  rs232_1 (fpga_0_RS232_1_TX_pin)
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================


CPU : 11.11 / 11.19 s | Elapsed : 11.00 / 11.00 s
 
--> 

Total memory usage is 176284 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)





Done!

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

At Local date and time: Sun Nov 05 15:35:02 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make hwclean; exit;" started...

rm -f implementation/system.ngc
rm -f implementation/system.bmm
rm -f implementation/system.bit


rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm 
rm -rf implementation synthesis xst hdl


rm -rf xst.srp system.srp




Done!

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

At Local date and time: Sun Nov 05 15:35:07 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make netlist; exit;" started...

****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc2vp30ff1152-6 -lang vhdl  -toplevel no -ti system -st xst system.mhs



Release Xilinx EDK 8.1.02 - platgen EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Command Line: platgen -p xc2vp30ff1152-6 -lang vhdl -toplevel no -ti system -st
xst system.mhs 

Parse system.mhs ...

Read MPD definitions ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...

Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...
Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0x73e00000-0x73e0ffff) opb_dp_mem_1	plb->plb2opb->opb
  (0x73e20000-0x73e2ffff) opb_dp_mem_0	plb->plb2opb->opb
  (0x7d800000-0x7d80ffff) opb_dp_mem_1	plb->plb2opb->opb
  (0x7d820000-0x7d82ffff) opb_dp_mem_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 101 - 1
master(s) : 4 slave(s)

Check port drivers...



Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Modify defaults ...

Creating stub ...



Processing licensed instances ...
Completion time: 0.00 seconds

Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...
opb_dp_mem (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Copying
(BBD-specified) netlist files.
opb_dp_mem (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Copying
(BBD-specified) netlist files.

Managing cache ...

Elaborating instances ...
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:150 - elaborating IP



Writing HDL for elaborated instances ...



Inserting wrapper level ...


Completion time: 1.00 seconds

Constructing platform-level signal connectivity ...


Completion time: 0.00 seconds

Writing (top-level) BMM ...
Writing BMM - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system.bmm

Writing (top-level and wrappers) HDL ...

Generating synthesis project file ...



Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
ppc405_0_wrapper (ppc405_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:46 - Running XST synthesis


ppc405_1_wrapper (ppc405_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:63 - Running XST synthesis


jtagppc_0_wrapper (jtagppc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:69 - Running XST synthesis


reset_block_wrapper (reset_block) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:76 - Running XST synthesis


plb_wrapper (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:92 -
Running XST synthesis


opb_wrapper (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:101 -
Running XST synthesis


plb2opb_wrapper (plb2opb) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:109 - Running XST synthesis


rs232_1_wrapper (rs232_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:122 - Running XST synthesis


plb_bram_if_cntlr_1_wrapper (plb_bram_if_cntlr_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:139 - Running XST synthesis


plb_bram_if_cntlr_1_bram_wrapper (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:150 - Running XST synthesis


opb_intc_0_wrapper (opb_intc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:156 - Running XST synthesis


dcm_0_wrapper (dcm_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:167
- Running XST synthesis


opb_dp_mem_0_wrapper (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Running XST synthesis


opb_dp_mem_1_wrapper (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Running XST synthesis



Running NGCBUILD ...
opb_dp_mem_0_wrapper (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Running NGCBUILD


opb_dp_mem_1_wrapper (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Running NGCBUILD



Rebuilding cache ...

Writing (stub) BMM ...
Writing BMM -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system_stub.bmm

Writing (stub) HDL ...
Total run time: 190.00 seconds


Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"


Release 8.1.02i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff1152-6
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Hierarchy Separator                : /

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort                : 1

=========================================================================



=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" in Library work.


Entity <system> compiled.


Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <system> (Architecture <STRUCTURE>).


Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================



Synthesizing Unit <system>.
    Related source file is "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd".
Unit <system> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================




=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================


Loading device for application Rf_Device from file '2vp30.nph' in environment c:\cad\Xilinx.



Optimizing unit <system> ...



Mapping all equations...


Building and optimizing final netlist ...





=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 129

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# Others                           : 14
#      dcm_0_wrapper               : 1
#      jtagppc_0_wrapper           : 1
#      opb_dp_mem_0_wrapper        : 1
#      opb_dp_mem_1_wrapper        : 1
#      opb_intc_0_wrapper          : 1
#      opb_wrapper                 : 1
#      plb2opb_wrapper             : 1
#      plb_bram_if_cntlr_1_bram_wrapper: 1
#      plb_bram_if_cntlr_1_wrapper : 1
#      plb_wrapper                 : 1
#      ppc405_0_wrapper            : 1
#      ppc405_1_wrapper            : 1
#      reset_block_wrapper         : 1
#      rs232_1_wrapper             : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff1152-6 



=========================================================================


TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1717 / 1717
-------------------------------------------------------------------------
Delay:               0.000ns (Levels of Logic = 0)
  Source:            rs232_1:TX (PAD)
  Destination:       fpga_0_RS232_1_TX_pin (PAD)

  Data Path: rs232_1:TX to fpga_0_RS232_1_TX_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    rs232_1_wrapper:TX     0   0.000   0.000  rs232_1 (fpga_0_RS232_1_TX_pin)
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================
CPU : 11.91 / 11.98 s | Elapsed : 12.00 / 12.00 s
 
--> 

Total memory usage is 176284 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)





Done!

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

ERROR:MDT - Can not get list of netlist files for core opb_dp_mem 1.00.a

At Local date and time: Sun Nov 05 16:46:46 2006
 xbash -q -c "cd /cygdrive/c/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/; /usr/bin/make -f system.make netlist; exit;" started...

****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc2vp30ff1152-6 -lang vhdl  -toplevel no -ti system -st xst system.mhs



Release Xilinx EDK 8.1.02 - platgen EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.




Command Line: platgen -p xc2vp30ff1152-6 -lang vhdl -toplevel no -ti system -st
xst system.mhs 

Parse system.mhs ...



Read MPD definitions ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl
...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cnt
lr_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tc
l ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_br
idge_v2_1_0.tcl ...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bra
m_if_cntlr_v2_1_0.tcl ...


Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/dcm_module_v1_00_a/data/dcm_module_v2_
1_0.tcl ...

Overriding IP level properties ...
jtagppc_cntlr (jtagppc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cnt
lr_v2_1_0.mpd line 36 - tool overriding c_device value X2VP4 to 2vp30
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 42 - tool overriding c_family value virtex2 to virtex2p
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 36 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_
1_0.mpd line 60 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Sourcing tcl file
C:/cad/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cnt
lr_v2_1_0.tcl ...


Address Map for Processor ppc405_0
  (0x40600000-0x4060ffff) RS232_1	plb->plb2opb->opb
  (0x41200000-0x4120ffff) opb_intc_0	plb->plb2opb->opb
  (0x73e00000-0x73e0ffff) opb_dp_mem_1	plb->plb2opb->opb
  (0x73e20000-0x73e2ffff) opb_dp_mem_0	plb->plb2opb->opb
  (0x7d800000-0x7d80ffff) opb_dp_mem_1	plb->plb2opb->opb
  (0x7d820000-0x7d82ffff) opb_dp_mem_0	plb->plb2opb->opb
  (0xfffe0000-0xffffffff) plb_bram_if_cntlr_1	plb
Address Map for Processor ppc405_1

Check platform configuration ...
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 92 - 2
master(s) : 2 slave(s)
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs line 101 - 1
master(s) : 4 slave(s)

Check port drivers...

Check platform address map ...

Overriding system level properties ...
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 42 - tool overriding c_plb_num_masters value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 43 - tool overriding c_plb_num_slaves value 4 to 2
plb_v34 (plb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mp
d line 44 - tool overriding c_plb_mid_width value 2 to 1
opb_v20 (opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mp
d line 39 - tool overriding c_num_masters value 4 to 1
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 51 - tool overriding c_plb_num_masters value 4 to 2
plb2opb_bridge (plb2opb) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_br
idge_v2_1_0.mpd line 52 - tool overriding c_plb_mid_width value 4 to 1
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 43 - tool overriding c_num_masters value 8 to 2
plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bra
m_if_cntlr_v2_1_0.mpd line 50 - tool overriding c_plb_mid_width value 3 to 1
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 38 - tool overriding c_memsize value 2048 to 0x20000
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 39 - tool overriding c_port_dwidth value 32 to 64
bram_block (plb_bram_if_cntlr_1_bram) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_
1_0.mpd line 41 - tool overriding c_num_we value 4 to 8
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 45 - tool overriding c_kind_of_intr value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 46 - tool overriding c_kind_of_edge value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000011
opb_intc (opb_intc_0) -
C:\cad\EDK\hw\XilinxProcessorIPLib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_1_0.
mpd line 47 - tool overriding c_kind_of_lvl value
0b11111111111111111111111111111111 to 0b00000000000000000000000000000000

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Modify defaults ...

Creating stub ...



Processing licensed instances ...
Completion time: 0.00 seconds

Creating hardware output directories ...

Managing hardware (BBD-specified) netlist files ...
opb_dp_mem (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Copying
(BBD-specified) netlist files.
opb_dp_mem (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Copying
(BBD-specified) netlist files.

Managing cache ...
ppc405 (ppc405_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:46 -
Copying cache implementation netlist
ppc405 (ppc405_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:63 -
Copying cache implementation netlist
jtagppc_cntlr (jtagppc_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:69 - Copying cache
implementation netlist
proc_sys_reset (reset_block) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:76 - Copying cache
implementation netlist
plb_v34 (plb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:92 - Copying
cache implementation netlist
opb_v20 (opb) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:101 -
Copying cache implementation netlist


plb2opb_bridge (plb2opb) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:109 - Copying cache
implementation netlist


opb_uartlite (rs232_1) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:122
- Copying cache implementation netlist


plb_bram_if_cntlr (plb_bram_if_cntlr_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:139 - Copying cache
implementation netlist


bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:150 - Copying cache
implementation netlist


opb_intc (opb_intc_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:156
- Copying cache implementation netlist


dcm_module (dcm_0) - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:167 -
Copying cache implementation netlist
opb_dp_mem (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Copying cache
implementation netlist


opb_dp_mem (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Copying cache
implementation netlist



Elaborating instances ...
bram_block (plb_bram_if_cntlr_1_bram) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:150 - elaborating IP



Writing HDL for elaborated instances ...

Inserting wrapper level ...


Completion time: 0.00 seconds

Constructing platform-level signal connectivity ...


Completion time: 0.00 seconds

Writing (top-level) BMM ...
Writing BMM - C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system.bmm

Writing (top-level and wrappers) HDL ...

Generating synthesis project file ...



Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
opb_dp_mem_0_wrapper (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Running XST synthesis


opb_dp_mem_1_wrapper (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Running XST synthesis



Running NGCBUILD ...
opb_dp_mem_0_wrapper (opb_dp_mem_0) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:189 - Running NGCBUILD


opb_dp_mem_1_wrapper (opb_dp_mem_1) -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\system.mhs:209 - Running NGCBUILD



Rebuilding cache ...

Writing (stub) BMM ...
Writing BMM -
C:\wjalmuzn\simcon_tree\SIMCON_31_SC\ppc\implementation\system_stub.bmm

Writing (stub) HDL ...
Total run time: 43.00 seconds


Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"


Release 8.1.02i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> 


TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff1152-6
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Hierarchy Separator                : /

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort                : 1

=========================================================================

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd" in Library work.


Entity <system> compiled.


Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <system> (Architecture <STRUCTURE>).


Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================



Synthesizing Unit <system>.
    Related source file is "C:/wjalmuzn/simcon_tree/SIMCON_31_SC/ppc/hdl/system.vhd".
Unit <system> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================




=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================


Loading device for application Rf_Device from file '2vp30.nph' in environment c:\cad\Xilinx.



Optimizing unit <system> ...



Mapping all equations...


Building and optimizing final netlist ...



=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 129

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# Others                           : 14
#      dcm_0_wrapper               : 1
#      jtagppc_0_wrapper           : 1
#      opb_dp_mem_0_wrapper        : 1
#      opb_dp_mem_1_wrapper        : 1
#      opb_intc_0_wrapper          : 1
#      opb_wrapper                 : 1
#      plb2opb_wrapper             : 1
#      plb_bram_if_cntlr_1_bram_wrapper: 1
#      plb_bram_if_cntlr_1_wrapper : 1
#      plb_wrapper                 : 1
#      ppc405_0_wrapper            : 1
#      ppc405_1_wrapper            : 1
#      reset_block_wrapper         : 1
#      rs232_1_wrapper             : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff1152-6 



=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1717 / 1717
-------------------------------------------------------------------------
Delay:               0.000ns (Levels of Logic = 0)
  Source:            rs232_1:TX (PAD)
  Destination:       fpga_0_RS232_1_TX_pin (PAD)

  Data Path: rs232_1:TX to fpga_0_RS232_1_TX_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    rs232_1_wrapper:TX     0   0.000   0.000  rs232_1 (fpga_0_RS232_1_TX_pin)
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================
CPU : 11.47 / 11.56 s | Elapsed : 11.00 / 11.00 s
 
--> 

Total memory usage is 176284 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)





Done!