<!-- Title: Owl shift. Wed Oct 25, 2000 -->
<!-- Leader: G. Pauletta -->
<!-- Ace: M. Kirby -->
<!-- Co1: Sunjong Woo -->
<!-- Co2: Igor Chirikov -->
<!-- Co3: Kevin Burkett (S.O.S.) -->
<!-- Co4: &nbsp; -->
<!-- Co5: &nbsp; -->
<!-- Notes: -->
<pre>Running with COMMISSIONING_COLLISIONS_LUM1 
(run 102325)</pre>


<!-- Date: Wed Oct 25 00:19:59 2000 -->
<pre>finished 102325 with ~150k events 
We had a "return crosspoint timeout on cmxwest00" 
Moving on to Si "latency scan"</pre>
<!-- Author: G. Pauletta -->


<!-- Date: Wed Oct 25 00:23:50 2000 -->
<pre>Begin run 102326 
Si latency 42  
COMMISSIONING_MIN_BIAS (L3 tag 58, early Myron Mode)</pre>
<!-- Author: G. Pauletta :: (run 102326) -->


<!-- Date: Wed Oct 25 00:25:21 2000 -->
<pre>forgot to set COT Thresholds 
End run to restart a new one with correct thresholds.</pre>
<!-- Author: G.Pauleta :: (run 102326) -->


<!-- Date: Wed Oct 25 00:49:17 2000 -->
<pre>Problems with VX crates 
SVX02 did not respond on cold start 
SVX05 and 06 also have problems 
Rebooted svx05 and 06</pre>
<!-- Author: G. Pauletta. :: (run 102328) -->
<!-- Comment: Wed Oct 25 07;51;54 comment by...patrick -->
The problem was with b0svt02, in the SVT trigger,
not with b0svx02. This seems to happen on significant
fraction (10-20%?) of the runs.
<!-- Date: Wed Oct 25 01:01:36 2000 -->
<pre>The previous run had an SVX latency of 42, but this is being 
changed to 41 by Alan.</pre>
<!-- Author: Kirby :: (run 102329) -->


<!-- Date: Wed Oct 25 01:32:07 2000 -->
<pre>Did several changes from the last couple of runs.  Fixed the 
bankSet for b0cot01, and instead of listing slot 16 twice, 
changed the last entry to slot 17.  Also including the IMU00 and 
HTDC00 crates after Eric James fixed problems with blown buffers 
on TDCs in the crate.  b0ccal06 also had a corrupted heap and so 
had to be rebooted.  When trying to partition, had a timeout from 
b0htdc00, and so may need to reboot.  gonna try and figure this 
out.	</pre>
<!-- Author: Kirby :: (run 102330) -->
<!-- Comment: Wed Oct 25 01;42;13 comment by...Kirby -->
So looked at the bankSet for the htdc crate, and about 10 TDCs
had been removed from the crate, but not removed from the readout
so I removed the cards from the bankSet and saved it with only 1
card (slot 4)


<!-- Date: Wed Oct 25 01:53:08 2000 -->
<pre>After modifying the bankSet, all of the new crates seem to work 
fine.  We do have a problem with the clc00 crate.  It keeps 
sending Bunchcounter mismatch errors for slots 3 and 19.  This
occurs exactly every 500 events.  (i.e. event 500, 1000, 1500, 
2000, 2500, ....  give this error)  Were reading out of Level 2 
at a rate of ~80Hz while the Fred prescaled rate averages ~163Hz. 
Why are these numbers so different?  Shouldn't the autoL2 accept 
translate into L1 rate being the same as L2 rate?</pre>
<!-- Author: Kirby :: (run 102332) -->
<!-- Comment: Wed Oct 25 02;12;48 comment by...Kirby -->
On event 120697, got a rxtp busy timeout from VRB_SVX_02 and an
error that said that a read from the VRB in slot 12 failed.
HRR was issued and the run continued.


<!-- Date: Wed Oct 25 02:48:43 2000 -->
<pre>Begin SRC delay/bandwidth studies. 
 
Standard delay is 38 ns 
Standard BW is 4 
 
For this run, delay is 19 
	      bandwidth is 4</pre>
<!-- Author: G. Pauletta :: (run 10233) -->


<!-- Date: Wed Oct 25 03:04:46 2000 -->
<pre> 
delay 19 ns 
Bandwith 5</pre>
<!-- Author: G.Pauletta :: (run 102334) -->


<!-- Date: Wed Oct 25 03:14:25 2000 -->
<pre>Delay 19 ns 
Bandwidth 6</pre>
<!-- Author: G. Pauletta :: (run 102335) -->


<!-- Date: Wed Oct 25 03:26:14 2000 -->
<pre>Delay 19 ns 
Bandwidth 7</pre>
<!-- Author: G. Pauletta :: (run 102336) -->


<!-- Date: Wed Oct 25 03:51:13 2000 -->
<pre>Using default parameters: 
 
Latency 41 
Delay 38ns 
BW 4 
 
Begin voltage scans for Micron chips
</pre>
<!-- Author: G. Pauletta :: (run 102337) -->


<!-- Date: Wed Oct 25 04:13:42 2000 -->
<pre>continuing with Micron chip 
voltage scans</pre>
<!-- Author: G. Pauletta :: (run 102338) -->
<!-- Comment: Wed Oct 25 04;20;36 comment by...Alan Sill -->
Run 102338 has all Micron bias voltages set to 35V, overriding the default volts.dat file for these layers (L2, L4), except for East phi 3 L2, which is off as usual.  For further details, see the <a href=/cgi/elog/det-system-elog.pl?nb=barrel4&action=view&page=34&anchor=04:14:48 target=_top> Barrel 4 logbook page</a> for this shift.


<!-- Date: Wed Oct 25 04:29:00 2000 -->
<pre>More of the same 
All Micron Voltages to 45 V</pre>
<!-- Author: G. Pauletta :: (run 102339) -->


<!-- Date: Wed Oct 25 04:55:07 2000 -->
<pre> Micron chip voltages at 55 V 
 </pre>
<!-- Author: G. Pauletta :: (run 102340) -->


<!-- Date: Wed Oct 25 05:16:56 2000 -->
<pre>default settings 
Read all, DPS off</pre>
<!-- Author: G. Pauletta :: (run 102341) -->


<!-- Date: Wed Oct 25 05:31:38 2000 -->
<pre>MCR has been waiting on us for a while. 
They want to do some beam studies which involve 
"tckling the beam just a little". We've been holding 
them off untill the Si studies are over. 
However, after encountering a problem with crate b0xtrp00, 
we decided to give them the green light even though Si is not 
altogether finished. 
After a H/W reboot of xtrp00, we continue with the 
Si' studies  (Read all, DPS on) with a wary eye on eventual 
beam perturbations.</pre>
<!-- Author: G. Pauletta :: (run 102343) -->


<!-- Date: Wed Oct 25 05:39:05 2000 -->
<pre>Si parameter variatins done. 
Back to normal: "Neighbor mode, DPS on, latency 41 
		 bandwidth 4, SRC delay 38 ns"</pre>
<!-- Author: G. Pauletta :: (run 102344) -->


<!-- Date: Wed Oct 25 05:51:55 2000 -->
<pre>ccal crates has recurring corrupt heap problems. 
Problems are not fatal, but they do require a reboot. 
Run 102344 was aborted and we are retrying with run 102345</pre>
<!-- Author: G. Pauletta :: (run 102345) -->
<!-- Comment: Wed Oct 25 06;40;48 comment by...R.J. Tesarek -->
Which crates?  All of them?
<!-- Date: Wed Oct 25 06:31:06 2000 -->
<pre>The difference betweem prescaled fred rates 
and the event rate is now only 3% 
 
MCR says they will drop the store at 7 am 
so we have 30 minutes until access. 
We decide to do start calibrations at 6:30.</pre>
<!-- Author: G. Pauletta -->


<!-- Date: Wed Oct 25 06:32:30 2000 -->
<pre>We end 10234 with about 100k events 
to begin calibrations.</pre>
<!-- Author: G. Pauletta :: (run 102345) -->


<!-- Date: Wed Oct 25 06:34:45 2000 -->
<pre>QIE calibration</pre>
<!-- Author: G. Pauletta :: (run 102346) -->



<!-- Date: Wed Oct 25 06:41:36 2000 -->
<pre>Cal Xenon Calibration</pre>
<!-- Author: G. Pauletta :: (run 102347) -->


<!-- Date: Wed Oct 25 07:04:28 2000 -->
<pre>
102350 CAL Led</pre>
<!-- Author: G. Pauletta -->


<!-- Date: Wed Oct 25 07:17:24 2000 -->
<pre>We are plagued by the usual problem that some calibrations 
never get transferred by the CSL. So we lost all the QIE 
calibrations we attempted so far.</pre>
<!-- Author: G. Pauletta -->


<!-- Date: Wed Oct 25 07:20:57 2000 -->
<pre>Xenon calibration</pre>
<!-- Author: G. Pauletta :: (run 102351) -->


<!-- Date: Wed Oct 25 07:35:36 2000 -->
<pre>CLC calibration. ox18fd0</pre>
<!-- Author: G. Pauletta -->
<!-- Comment: Wed Oct 25 07;42;52 comment by...Kirby -->
the file name was  ar018fd0.0001cali


<!-- Date: Wed Oct 25 07:45:34 2000 -->
<pre>Muon Calibration</pre>
<!-- Author: G. Pauletta :: (run 102353) -->



<!-- Date: Wed Oct 25 07:53:12 2000 -->
<font color=red>Shift Summary: </font><pre>ook 150 K with COMMISSIONING_COLLISIONS_LUM1  
(Early Myron Mode, tag 58): run 102135 
Then switched to COMMISSIONING_MIN_BIAS for 
Si timing studies and Si voltage scans. 
 
CLC crate has been sending "bunchcounter  
mismatch" errors for slots 3 and 19 every 500 
events and event rate has consistently been 
larger than prescaled Fred rates (but apparently, that's 
normal -- see M. Schmidt's note in last shift's log). 
 
Beam was dumped at 7 am as planned. 
We started doing calibrations at ~6:30. Persistent 
problems with CSL. Unable to record QIE calibration. 
 
Detector Status:   
 
COT:	00-05, 07-19  
CAL: 	all  
SVX: 	FIB_00,FIB_02,fib_04,fib_06, 
	vrb_svx_00->05, vrb_isl_06->08   
Muon: 	CMU00,CMU01,CMP00,CMX00,CMX01, 
      	IMU00,IMU01,MUSC00,MUTR00        
XFT:	DAQ_XFT*_00->05  
XTRP:	DAQ_XFT*_XTRP_OO  
SVT: 	b0svt01,02,06; b0l2de01  
CLC: 	clc00  
 
	L1CAL00-05  
	L2CAL00-05  
	 
L3: 	16 Farms   
 
Runs 102325 -  102353 
 
</pre> 
<br><b>End of Shift Numbers</b>
<table><tr><td width=60% align=left>
<b>CDF Run II <p></b>                       
<pre>
Runs                   102325-102353
Delivered Luminosity   7 hours x 5x10**27  pb-1
Acquired Luminosity    ~ 5 hrs x 10**27  pb-1
Efficiency             70%
   
</td></tr></table></pre>
<!-- Author: G. Pauletta -->