<!-- Title: 11:14:37  Mon Jul 19 1999 -->
<!-- Crewchief: Steve Vejcik -->
<!-- Op1: Steve Hahn -->
<!-- Op2: &nbsp; -->
<!-- Op3: &nbsp; -->
<!-- Op4: &nbsp; -->
<!-- Op5: &nbsp; -->
<!-- Op6: &nbsp; -->
<!-- Notes: -->
Begin including B0 Scheduling information here.  


<!-- Date: Mon Jul 19 11:15:10 1999 -->
<pre>Please remember to use rlogin as a lockout mechanism and use the 
 logbooks (/e-log ). 
 Note also that a reorganization of logbooks will likely be 
 proposed in the near future. Send ideas, etc. to Steve & Steve. 
 This information is also being put into the e-log book  
 
Crate Contention: 
 My understanding of outstanding requests for the wedge & other 
 contended crates is as follows: 
=========================== 
 
 Wedge & TS crate 
 ---------------- 
 
 Monday until 1PM : Nathan Eddy with Wedge Crate, TS Crate (2-27T), 
		    and TDC Crate (2-25T) 
 Monday 3:00 until Tuesday AM: A. Meyer Wedge Crate 
 Tuesday 7:30 AM until 
	10:00 AM    Power supply change over (again). 
 Tuesday 10:00 AM until Thursday Noon Chicago L1 Trigger 
 
 Thursday Noon  until 4:00 PM Philippe Gris Wedge Crate 
 Friday All Day : Frank/Kirk &-or Frank/Ilya/Kris Wedge Crate 
             (note that a new crate is being rigged on the 1st 
              floor for clc & software development) 
 
 Wednesday 9 AM to 1:00 PM Vejcik TS crate 
 Thursday 9 AM to 1:00 PM Vejcik TS crate 
 Friday 9 AM to 2:00 PM Vejcik TS Crate 
 
 
 Other 
 ----- 
 
 There's also a potential contention for one of the "wide" test 
 crates. These are the 23B,25B,26B,27B,28B,23T, and 27T (the TS 
 crate). Pedro et al have been using 26B and the SVX group is 
 using 25B sporadically. Until Friday Morning, they will have 
 first priority for those crates they're using.   
</pre>
<!-- Author: Steve Vejcik -->


<!-- Date: Mon Jul 19 11:15:56 1999 -->
<pre><pre>Please remember to use rlogin as a lockout mechanism and use the 
 logbooks (/e-log ). 
 Note also that a reorganization of logbooks will likely be 
 proposed in the near future. Send ideas, etc. to Steve & Steve. 
 This information is also being put into the e-log book  
 
Crate Contention: 
 My understanding of outstanding requests for the wedge & other 
 contended crates is as follows: 
=========================== 
 
 Wedge & TS crate 
 ---------------- 
 
 Monday until 1PM : Nathan Eddy with Wedge Crate, TS Crate (2-27T), 
		    and TDC Crate (2-25T) 
 Monday 3:00 until Tuesday AM: A. Meyer Wedge Crate 
 Tuesday 7:30 AM until 
	10:00 AM    Power supply change over (again). 
 Tuesday 10:00 AM until Thursday Noon Chicago L1 Trigger 
 
 Thursday Noon  until 4:00 PM Philippe Gris Wedge Crate 
 Friday All Day : Frank/Kirk &-or Frank/Ilya/Kris Wedge Crate 
             (note that a new crate is being rigged on the 1st 
              floor for clc & software development) 
 
 Wednesday 9 AM to 1:00 PM Vejcik TS crate 
 Thursday 9 AM to 1:00 PM Vejcik TS crate 
 Friday 9 AM to 2:00 PM Vejcik TS Crate 
 
 
 Other 
 ----- 
 
 There's also a potential contention for one of the "wide" test 
 crates. These are the 23B,25B,26B,27B,28B,23T, and 27T (the TS 
 crate). Pedro et al have been using 26B and the SVX group is 
 using 25B sporadically. Until Friday Morning, they will have 
 first priority for those crates they're using.   
</pre></pre>
<!-- Author: Steve Vejcik -->


<!-- Date: Tue Jul 20 12:33:41 1999 -->
Peter Wilson says that the reinstallation of the PEI power supply 
in the wedge test rack (NW Arch) is having difficulties again.  He has directed that if it cannot be immediately installed, then it will be removed to a different rack to test installation with load cards rather than taking up time at the wedge test. The wedge test would then be reconfigured with the old power supplies. Has anyone seen the movie "Midway" where one side in the battle keeps changing from torpedoes to bombs and back again?  
<!-- Author: Steve V. -->


<!-- Date: Wed Jul 21 08:46:56 1999 -->
The Wedge Test rack is back in operation.  
<!-- Author: Steve V. -->


<!-- Date: Fri Jul 23 10:29:54 1999 -->
Message in trigger room from Wayne says that power is out 
 while some type of fuse change is going on. No idea what 
 this is about. Also, water cooling seems a lot noisier 
 than usual (from control room).
<!-- Author: s -->


<!-- Date: Mon Jul 26 11:46:04 1999 -->
Power supply may be put in NW arch again later this week which 
will mean a half day shutdown.   
Steve Chappa is supposed to have clock reconfiguration work 
done by midweek. 
Steve Hahn is formulating a makeover of the logbook. 
Procedure for recovering from trip is to page ops manager 
(Steve Hahn) and let him deal with it. 
Fuse in Protection system went out last week. The power consumption per rack appears to be higher than was expected. 
Andrew Martin will do work with SRC and with Steve Hahn. 
smxr will not need wedge crate this week. 
  
<!-- Author: Steve Vejcik -->


<!-- Date: Mon Aug 9 10:49:00 1999 -->
Reminder: Please use "rlogin" to connect when using a  
  crate cpu.  Also, please try to make use of the  
  electronic logbook at /e-log 
 
Monday Update Items: 
1. TSI System will move from 2RR27C to 2RR22H/G  
   Andrew Martin will be here to help bring system up 
   on Tuesday 
2. SVX will be testing TS-SRC link 
3. Steve Kuhlmann asks (and gets) Wedge Crate for SMXR 
   testing on Tuesday 11:00-6:00 and maybe Friday 
4. Testclocks are walking away-need a couple for 
   semi-permanent residence on 2nd Floor (b0cmu00) 
5. Expect periodic early AM downtimes for b0dau30 as 
   new disk space is added over next week or two. 
6. Expect 10-30 minutes interrupts as move to real 
   ethernet cables takes place. 
7. Sometime in the near future the CLC crate will become 
    more exclusively a CLC crate and a new long term 
    solution for SW development will need to be found. 
8. Steve Vejcik will start collating and leavening of 
   cpu startup scripts again. 
9. Non-SMXR competition for Wedge Crate: 
	Steve Hahn will need a few 10' noise tests accesses. 
	Phillipe Gris needs time but also needs the power 
        to the phototubes up.  Through today this is not 
        possible because of pt modifications by argonne. 
        Steve Hahn's testing also needs HV at times. 
10. A second Clock fanout crate is expected shortly on the 
    2nd Floor.  
<!-- Author: Steve Vejcik -->


<!-- Date: Wed Aug 11 09:39:16 1999 -->
<pre>Racks on 1st and 2nd Floor tripped around 9:30 AM. 
 
Paged Steve Hahn who said to: 
	1. find keith schuh,  
        2. talk to folks in cryo area 
        3. Find Jim Schallenberger. 
Keith not around. 
Jim S. and Sondra were in cryo area. Sondra 
brought up rack status pages. 
Jim determined that fuse in protection PS (5A) blew. 
Could not install new one so there is fault somewhere else. 
Jim and Wayne are trying to find source of fault. 
3rd Floor racks not under protection nor is clock rack. 
</pre>
<!-- Author: Steve Vejcik -->
<!-- Comment: Wed Aug 11 09;40;29 comment by...s.v. -->
Also, very little work going on at time.  Only myself and Andrew on 2nd Floor and not doing any hardware work.  A technician was doing something on 1st floor but Dervin Allen says it wasn't anything related (hm...)



<!-- Date: Wed Aug 11 10:11:51 1999 -->
<pre>Jim S. and Wayne tracked down trip to rack 21G on 1st 
floor. This is an SVX VRB rack. SVX folks weren't working 
on it. Jim S. seems convinced problem was a cut cable from 
rack to the protection rack. Crate is isolated now until 
problem can be cured (pull a cable) and rest of racks 
are reset from Fuse boxes. Why didn't clock rack go off? 
</pre>
<!-- Author: Steve V. -->


<!-- Date: Wed Aug 11 12:49:01 1999 -->
dap00 turned off!?
<!-- Author: {Quick_Entry} -->


<!-- Date: Mon Aug 16 10:41:39 1999 -->
<pre>From I&I 9:00 Meeting- 
              	Fanpack suspected of being cause of last week's 
 	trip appears to be ok.  
		Mike Lindgren is "95%" sure that HV to arches  
	used in wedge test can be turned on.  Steve Hahn is 
  	on vacation until this Wednesday. 
From Scheduling Meeting: 
	Expect maybe 5 Testclocks shortly (via WH->Peter->Fred) 
	New cpu names ordered. 
	2nd SVT crate requested-maybe? 
	Expect 7-8 AM shutdowns of b0dau30 occasionally this 
	week. 
	Philippe Gris says he cannot operate HV in wedge test- 
	he suspects Steve Hahn did some mods to cabling. 
	Actually, the Wedgetest logbook from Thursday, Aug 18 
 	has the entry appended at the end of this entry. 
	Jonathan Lewis is coordinating cabling from MVME's 
	to patch panels and floor tile cuts that will be 
	needed. 
	Arnd Meyer just needs clc1 this week. Would like 
	more TDC's. There is only one Rev B TDC in cmu00 
	at the moment. 
	No other explicit requests at the moment. Unless 
	P. Gris says otherwise, we'll assume he gets crate 
	time after Steve Hahn returns on Wednesday. 
		That's all. 
============ 
Entry from Steve Hahn in wedgetest logbook 
Thu Aug 12 18:24:02  Today at about 4:00 PM, I rewired the HV cables on the NW arch such that only wedges 21W, 22W, and 23W have HV. Thus, the CEM PMT modifications can 
proceed on the other wedges (these wedges are completed) while we run on these wedges which are connected to the wedge test crate.  
 
I did this by disconnecting the CEM and CHA HV inputs from the movable cable tray into the Pisabox for wedge 05W at the beginning of the HV daisy chain, adding long HV cables 
with SHV barrels to these cables, and connecting the long cables at the other end into wedge 23W. Then I unplugged the connections between 21W and 20W. I checked that only 
wedges 23W, 22W, and 21W were receiving HV. - Steve Hahn  
	</pre>
<!-- Author: Steve Vejcik -->


<!-- Date: Tue Aug 24 10:33:00 1999 -->
<pre>Update from Monday Meeting: 
	Wedge Balancing this week between: 
	Philippe, SMX, and Korean group 
        Day of SW development and CLC reckoning is approaching 
        Would like another SW development crate in maybe two weeks. 
	Hope to keep 4 TS spread a bit: 2 in "real" crate, 2 in the older racks until real operational use of partitioning is ready. 
	Issue of COT prototype connection to DAQ unsettled until COT group decides what it wants-at least two voices of opinion on this issue at present. It would be a real hurdle at B0 mainly because of cable needed from clock to putative clock fanout crate. 
	More progress on accessing wedge data at L3 but not perfect yet. 
	Crates expected to be coming up in near future include NE arch and elements of plug. 
	Several Testclocks are at B0 (see any combinatin of Peter Wilson, Steve Hahn, Fred Lewis, and Steve Vejcik to "rent" one). 
	Motherhood statement: use logbooks and rlogin. 
</pre>
<!-- Author: Steve Vejcik -->
<!-- Comment: Tue Aug 24 10;36;38 comment by...Steve V. -->
Steve Hahn now has a greatly improved crate scheduling page at
http://hahn.fnal.gov/schedule.html



<!-- Date: Wed Aug 25 08:56:59 1999 -->
Working with Greg Feild yesterday found some odd things with clock signals as appear in crate 2RR26C(Top)  
Logic Analyzer shows weird time structure for CDF clock. 
This AM, I verified that this was still there. I then 
 looked at Tracer front panels for crates 2RR22I and did not 
see the same thing so it may have to do with cabling  and fanouts.  The scope shows the signals (even in the 22I rack) as being only about 2.5 V out of the tracer fp. This is awfully low.  
<!-- Author: Steve V. -->
<!-- Comment: Wed Aug 25 09;02;18 comment by...Steve V -->
I verify that clock is in 132 nsec mode (BC up and down every 132 nsec while no abort gap and low during abort gaps). Scope shows clock with Vpp=3.0V and 132nsec on tracer fp.

<!-- Comment: Wed Aug 25 09;40;07 comment by...Steve Vejcik -->
Even "good" crate (22G) looks a bit funny. Good Vpp on
clock (from Tracer FP) about 6 V with some undershoot, but
 the period as measured by the scope seems to occasionally
fluctuate high (mean=140nsec).
Look on "bad" crate (26C):Probed cdf_clock looks good but
the cdf_clk on pin3 of the tracer fp (which is used by logic
analyzer) is small (but cleaner) Vpp is about 3.2 V now which
should be fine. Put logic analyzer back on and it too looks fine.
I know it was *NOT* fine earlier. What's going on?


<!-- Date: Tue Aug 31 10:57:29 1999 -->
Steve Nahn reported around 10:00 that a first floor rack 
(21I) was tripping. First trip reported was drip sensor. 
Wayne looked at it and determined it was really a trip and 
 not a problem with rack protection fuse or power (as was 
 the case in the past). We then found Bill Wickenberg who 
 cleaned the drip sensor. The rack appears to now be okay. 
 The upper fanpack failure LED still is observed to be "faintly" 
 on. When fully on, this indicates failure. These are driven 
 by Tachometers so its not clear what's going on. Dervin 
 will keep an eye on it and perhaps change the fanpack 
 in a bit.
<!-- Author: Steve Vejcik -->


<!-- Date: Tue Aug 31 15:31:28 1999 -->
Yet another trip: 
	The L1 cables coiled up in Rack 26 have metal 
 covers which were coming into contact with exposed 
 parts of the AC on the (Fastbus) power supply. I 
 shut the power off at the breaker so as to safely 
 move the cables and this tripped the whole back wall.  
<!-- Author: Steve V. -->


<!-- Date: Tue Sep 7 10:01:16 1999 -->
<pre>Electrical work in Rack 31 required it be shut down. This 
 tripped off the whole row in back of trigger room (Row C). 
Not clear whether this is a feature or a bug. Not clear 
 length of shutdown. Peter Wilson agrees to track down 
details shortly (before lunch).</pre>
<!-- Author: Steve V -->


<!-- Date: Wed Sep 8 15:07:15 1999 -->
We have 2 partitions running auto L2A. One goes to Wedge Crate and one goes to b0cmu00 (muon tdc crate).
<!-- Author: Steve V. -->


<!-- Date: Sat Sep 11 21:45:31 1999 -->
<pre>How do I get an elogbook for SVX/ISL daq?</pre>
<!-- Author: Steve -->
<!-- Comment: Tue Sep 14 11;20;25 comment by...Steve V. -->
Talk to Rick Vidal...
<!-- Date: Mon Sep 13 19:06:32 1999 -->
<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> 
<html> 
<head> 
   <meta name="Author" content="Steve Hahn"> 
   <meta name="GENERATOR" content="Mozilla/4.51 (Macintosh; I; PPC) [Netscape]"> 
</head> 
<body> 
Greg Feild and I made a count of all TESTCLKs we could find active in crates 
in B0: 
<br>&nbsp; 
<br>&nbsp; 
<table BORDER BGCOLOR="#CCFFCC" > 
<tr> 
<td> 
<div align=right>VME Crate Location</div> 
</td> 
 
<td> 
<div align=right>MVME name</div> 
</td> 
 
<td> 
<div align=right>Slot</div> 
</td> 
 
<td> 
<div align=right>Type</div> 
</td> 
 
<td> 
<div align=right>Serial #</div> 
</td> 
</tr> 
 
<tr> 
<td> 
<div align=right>2RR25C-U</div> 
</td> 
 
<td> 
<div align=right>b0cmu00</div> 
</td> 
 
<td> 
<div align=right>19</div> 
</td> 
 
<td> 
<div align=right>V7</div> 
</td> 
 
<td> 
<div align=right>45</div> 
</td> 
</tr> 
 
<tr> 
<td> 
<div align=right>2RR25C-L</div> 
</td> 
 
<td> 
<div align=right>b0l1cl02</div> 
</td> 
 
<td> 
<div align=right>7</div> 
</td> 
 
<td> 
<div align=right>V7</div> 
</td> 
 
<td> 
<div align=right>66</div> 
</td> 
</tr> 
 
<tr> 
<td> 
<div align=right>2RR26C-U</div> 
</td> 
 
<td> 
<div align=right>b0cot03</div> 
</td> 
 
<td> 
<div align=right>18</div> 
</td> 
 
<td> 
<div align=right>V7</div> 
</td> 
 
<td> 
<div align=right>64</div> 
</td> 
</tr> 
 
<tr> 
<td> 
<div align=right>1RR27E-L</div> 
</td> 
 
<td> 
<div align=right>b0clc1</div> 
</td> 
 
<td> 
<div align=right>4</div> 
</td> 
 
<td> 
<div align=right>V7</div> 
</td> 
 
<td> 
<div align=right>57</div> 
</td> 
</tr> 
 
<tr> 
<td> 
<div align=right>CANWB-L</div> 
</td> 
 
<td> 
<div align=right>b0ccal00</div> 
</td> 
 
<td> 
<div align=right>3</div> 
</td> 
 
<td> 
<div align=right>V7</div> 
</td> 
 
<td> 
<div align=right>41?</div> 
</td> 
</tr> 
 
<tr> 
<td> 
<div align=right>XFT Test Crate</div> 
</td> 
 
<td> 
<div align=right>b0xfttst</div> 
</td> 
 
<td> 
<div align=right>6</div> 
</td> 
 
<td> 
<div align=right>V7</div> 
</td> 
 
<td> 
<div align=right>58</div> 
</td> 
</tr> 
</table> 
 
<p>To my surprise this does not seem like many.&nbsp; In fact, we just 
added 64 in b0cot03 to replace one of the two missing TESTCLKs checked 
out to Greg (43 and 44).&nbsp; I think the number of the wedge test crate 
(CANWB-L) is correct, but I have not checked it yet. 
<br>&nbsp; 
</body> 
</html>  
<!-- Author: Steve Hahn -->



<!-- Date: Tue Sep 14 11:21:36 1999 -->
Steve Chappa will be adding fanouts and cables this afternoon. It 
 is not clear whether this affects anyone other than 2nd floor but expect the worst.
<!-- Author: Steve V. -->


<!-- Date: Mon Sep 20 11:04:57 1999 -->
<pre>Scheduling: 
    Power out on 2nd floor racks Wed & Thu 
    B0Dau30 out for 1-2 hours on Monday 
    Sergei did 10 Tracer->1VRB with 2nd floor crates. 
    Other tests may continue with these crates but at 
    lower priority. 
    Arnd working on TS-RC integration. Will likely  
    want b0cot02 and b0cmu00 afternoons and evenings. 
    No other requests. No one from calibration tests around. 
    TDC test folks not around either. 
</pre>
<!-- Author: Steve Vejcik -->
<!-- Comment: Mon Sep 20 11;05;28 comment by...Steve V. -->
Andrew Martin expected after lunch today.


<!-- Date: Mon Oct 11 10:58:49 1999 -->
<pre>Scheduling Meeting Oct. 11 
1. Summary of recabling process: 
     1st & 2nd Floor 
Clock Fanout->Tracer       currently kluged. multiple weeks away 
TS Fiber              kluged. multiple weeks away 
VRB<->Tracer Fiber    kluged .  multiple weeks away. 
Return Copper         Being implemented over this week. 
Serial Cables            "         "             " 
Reset Cables             "          "             " 
 Clock Triax            Multiple weeks away. 
 Fanout Cards           Multiple weeks away 
 
Clock components are here but are in a "testing" stage. 
 
2. Rack protection: completing failsafe connection will 
 begin sometime this week. This means powering down a rack 
 for an hour (estimated).  First comes entire 2nd floor South 
 Wall. Then one rack at a time with a days notice from Peter. 
 Racks being actively used will be worked on from 7-9 AM 
 only. 
 
3. Scheduling:  
    While Partitioning is possible, it is not likely to 
 be very smooth. For the moment, the convention is to schedule 
 the TSI crate in its entirety.  If more than one person wants 
 to try and use a TS at the same time, it could work but the 
 convention is to reach an agreement with the bookee first. 
 
</pre>
<!-- Author: Steve Vejcik -->


<!-- Date: Fri Oct 15 09:05:40 1999 -->
<pre>I've made a new test "default scripts". 
They differ solely in the custom startups, 
not in the configurations.  The custom 
startups correspond to 4 separate versions 
of vxboot: 
   trialfred    : Loads smartsockets,fer_smart_feild,spawns 
                  FER_dummy_setup 
   trialtest    : Loads TS,Monitoring, and debugging code. 
   trial        : Loads smartsockets,fer_smart_current,spawns 
                  FER_dummy_setup                   
   trialrcdevel : Loads smartsockets,fer_smart_devel, spawns 
                  FER_dummy_setup 
</pre>
<!-- Author: Steve V. -->


<!-- Date: Mon Oct 18 15:17:10 1999 -->
Hans Jensen has asked me to make a log entry regarding the details of the problems with the FRED 10U VME crate, the scaler 6U VME crate, and the scaler boards.  It now appears this is a problem local to the scaler crate, which is part of the TSI system (as are the FRED crate, the TS crate, the trigger XPT crate, and the return XPT crate), so I will post these details there.
<!-- Author: Steve Hahn -->


<!-- Date: Wed Oct 20 21:24:32 1999 -->
We were able to readout three crates using the trigger supervisor and run control. We read out two TDC crates and the Central CAL crate, send data through the entire chain and wrote data to disk. Events were cut at Level 3.  
 
In a seperate test we ran with two partitions, one partition had the Central CAL crate and one TDC crate and we sent data through the entire chain. The second partition used the other TDC crate and sent data to the software event builder.  
 
We could not use the Plug crate because the power supply was not yet repaired. Also we are missing functional adaptor cards for the scanner CPUs. 
<!-- Author: Frank Chlebana -->


<!-- Date: Thu Oct 21 11:07:32 1999 -->
<pre>The TS firmware has been upgraded this morning, tests indicate success. 
 
The trigger XPT boards were moved to their correct slot assignments, the even numbered slots starting at 2. 
 
The return XPT firmware was modified slightly to make the powerup state be easier to use.   
They now powerup with the reset bits cleared. 
 
Additional Return Fan-In boards were installed in slots 
12-15 and 21.</pre>
<!-- Author: Andrew Martin -->


<!-- Date: Thu Oct 21 20:44:52 1999 -->
We continued our 3 component readout tests. When we started the Trigger Supervisor crates and clock crates were powered off. It took some time to reconfigure the clock. Cooling water to the VRB crates on the first floor got turned off. No alarms went off to indicate this. We did manage to take a run with four crates. 
Two TDC crates and the Plug and Central CAL crates were included. We were unable to recompile the consumer code due to changes to the offline software distribution - these should be now fixed. We were unable to send data to the event display. A file was generated and the problem can be debugged offline. We tried to include the SRC in the readout but encountered problems which are being looked at. 
 
After the cooling problem were had problems reading out some of the TDCs. We are not sure if this is related to the VME access problem already reported. We should get fixed TDCs to avoid wasting time tracking down known bugs.  
 
It will be useful to have an SRC expert on hand when doing the readout tests.
<!-- Author: Frank Chlebana -->
<!-- Comment: Fri Oct 22 11;03;23 comment by...Steve Tether -->
Speaking of the VME lockup, here's what we know about the problem (I've sent this to Mark Bowden):
<p>The problem appeared when the event builder tried
to keep up with an ADMEM crate that was being triggered at roughly 1.5
KHz according to Arnd. The only way we found to clear things up was to
cause a SYSRESET in the crate. After several futile attempts to run this
way, Arnd reduced the trigger rate to about 300 Hz, after which we had
no problem.
<p>
We read using D64 BLT transfers in supervisor mode, starting at the fast
FIFO base address. For each event we first do an eight-byte read to get
the byte count, then we read the rest of the event (a fev KB in this
case). The Universe II VME DMA controller is set to hold onto the bus
until each DMA is complete (VON DONE) and, if it ever does release, to
rerequest immediately (VOFF 0). The U-II doesn't have DMAs with
non-incrementing VME addresses, so our second read for each event covers
a range of addresses.



<!-- Date: Mon Oct 25 23:48:38 1999 -->
<pre>TS->SRC communication status: please see the TSI e-log.</pre>
<!-- Author: Petar -->


<!-- Date: Tue Oct 26 00:00:35 1999 -->
<pre>SVXDAQ->DAQ: working, from one DEM (@ FIB in b0svx5, slot12), 
via one VRB (b0svx04, slot 12), through the switch to the 
converter node.</pre>
<!-- Author: Ilya and Petar -->


<!-- Date: Tue Oct 26 00:21:52 1999 -->
<pre>We ran a couple of tests reading out 1 SVX VRB,  
sending data to level3. We tried 1 channel (3k event size) 
and 10 channels (31k event size). Event rate was  
10s of Hz. L3 executable dies on these events. Reformatter 
seems to run, but gives warnings. I have saved raw data 
file that is accessible from the online cluster  
~ikrav/junk/dat/svx-102699.raw and will look at it  
tomorrow. Next in the list is to try to read 2 crates. 
</pre>
<!-- Author: Petar and Ilya -->


<!-- Date: Tue Oct 26 23:35:17 1999 -->
<pre><pre>Some more tests of SVX->EVB->Level3. Setup is similar 
to what it was yesturday. Using Auto-SRC trigger. Today 
we succeeded in reformatting SVX data from a single VRB, 
using latest Christoph's reformatter. (Several VRBs 
did not work yet). More details can be found in level3 
e-log. 
   Scanner SPUs of event builder are now using the new 
CDF adapters that are finally working. 
</pre></pre>
<!-- Author: Petar and Ilya -->


<!-- Date: Tue Oct 26 23:43:55 1999 -->
<pre>Quick note: if a scanner is polling the VRBs in the SRCs crate, 
avoid any VME access to the SRC (read or write) -- it almost 
certainly hangs the system.</pre>
<!-- Author: Ilya and Petar -->


<!-- Date: Fri Oct 29 00:24:34 1999 -->
<pre>TS->SVX WORKS: after a couple of trips to FCC to reimplement 
the firmware, and a few more trips to the high-rise to burn 
proms, we've found and fixed a bug in the SRC, having to do 
with the bits 5 and 6 stuck high in our TAXI decoder, thereby 
resulting in a L1A and L2A buffer mismatch, which the SRC 
(correctly) refused to process.  After that, the SRC was 
able to get L2As from the TS with and without the DONE 
handshake, and we were able to read the events *by hand* 
from the VRB scan buffer.</pre>
<!-- Author: Stephen and Petar -->


<!-- Date: Fri Oct 29 00:32:07 1999 -->
<pre>TS->SVX->DAQ: with the old DAQ code polling the VRBs, 
we were able to read the SVX events while the data taking was controlled by the TS.  
 
Note: since the DAQ does something to the VRBs at init, we 
found that starting various pieces of the system does not 
commute:  
	1. start the DAQ first 
	2. SVX DAQ can be up and running (and even in the TS 
	   mode), but at this point we do a HRR to clear the 
           state of the VRB. 
	3. activate the Run Control. 
 
There still were some bus errors, though, but the data is  
flowing out of the SVX DAQ, the VRB is deasserting SCAN_BUSY, 
the SRC is asserting DONE, and the TS is issuing new L2As... 
 
</pre>
<!-- Author: Ilya and Petar -->


<!-- Date: Sat Oct 30 21:20:07 1999 -->
I got a call at home about 6:30 PM from the main control room, telling me (as the operations manager) that there would be an unscheduled power outage from 10:00-10:50 PM tonight so that Com Ed could repair a breaker.  Rich Schmidt and Rob Roser are notified; they have arranged for someone to bring cryo back up after the outage.  I have turned off all VME and clock power supplies on the 1st and 2nd floor, and in the pit.  I turned off some SGIs in the control room and pit, also. 
<p> 
Peter Wilson showed up to check that things were off.  Julie Whitmore told him that the KTeV logbook says there will be another outage tomorrow to return to the correct feeder.  Certainly, we should turn nothing on until the water cooling is verified to be working correctly.
<!-- Author: Steve Hahn -->


<!-- Date: Mon Nov 1 20:40:50 1999 -->
Feynman Computing Center, CDF, and cryo will have to endure another power outage tomorrow morning 8:00-8:30 AM for Com Ed work.  Fred Lewis will power down the racks.
<!-- Author: Steve Hahn -->


<!-- Date: Fri Nov 5 09:42:35 1999 -->
A time recording has been added to the rack first fault message for each rack.  The format is MM:DD:HH:MM:SS.  
<!-- Author: RLS -->


<!-- Date: Wed Nov 10 09:34:34 1999 -->
Brought power back up for crates in Southwest of Trigger Room (I think these are 23-26).  Breakers were off, probably from trip on Monday.
<!-- Author: Steve Vejcik -->


<!-- Date: Wed Nov 17 11:21:32 1999 -->
It appears that quite a few of the racks tripped at 13:32 Tuesday which was coincident with pulsing the valves.  I staggered the pulse times.  The new power supplies are being mounted in the shop in preparation for installation.  They will be initially set at 26 VDC.  
<!-- Author: RLS -->


<!-- Date: Wed Nov 17 13:32:00 1999 -->
Greg Feild complained about the TSI racks (2RR22F, 2RR22G, 2RR22H) being off.  We checked DMACS, which said these racks had been down since 1:30 PM yesterday.  So why wasn't anybody complaining about this earlier?  As usual, DMACS gave no clue to the actual problem, just said the FIRST FAULT was POWER OFF.  But the breakers for these racks were actually tripped.  As usual, the clock rack stayed up, no problem.
<!-- Author: Steve Hahn -->


<!-- Date: Thu Nov 18 20:12:48 1999 -->
<pre>I installed the last two trigger crosspoints this evening into 
the correct slots.  This means all 10 boards are installed at  
this time. 
 
In addition I updated the TS firmware in all four boards and 
verified that they were functioning correctly.</pre>
<!-- Author: Andrew Martin -->


<!-- Date: Tue Nov 23 16:21:56 1999 -->
New rack protection power supplies installed.  Voltage at rack 2RR35F is 23.7.  Tested South wall contiguous racks as follows:  Powered 2RR22C, 29C, 30C, 31C.  Unplugged small power supplies in 29C and 30C.  Those racks tripped individually but the others remained on.  Sprayed smoke in 31C, all four tripped.  Powered 32C and wet the drip sensor.  All four tripped and all four valves closed.  First fault worked correctly. 
 
We found that the smoke detector did not reset and further investigation found that when power is interrupted there is still nineteen volts on the line.  Investigating.
<!-- Author: RLS -->
<!-- Comment: Tue Nov 23 18;19;52 comment by...Peter Wilson -->
Also tested undervoltage release on 2RR35F and 2RR32C.  With 23.8V applied they reset correctly on the first try.  We are now ready to install on all counting room relay racks.
<!-- Date: Tue Nov 23 16:28:08 1999 -->
Also pulsed valves without incident.  The first and second floor valves do not pulse simultaneously anymore.
<!-- Author: RLS -->


<!-- Date: Tue Nov 23 17:11:07 1999 -->
In fact there was a logic problem with the water valve testing that caused power to trip.  This was corrected with a time delay on the valve position.  THere is no delay on the drip detection, which will still trip power and close the valves.
<!-- Author: RLS -->


<!-- Date: Tue Nov 23 17:18:08 1999 -->
Checked all smoke detectors.  Power is being fed back from the smoke detector in 2RR24C.  That rack will also not reset.  Will look into the wiring tomorrow.  Peter is going to test the south racks individually.
<!-- Author: RLS -->


<!-- Date: Tue Nov 23 18:11:15 1999 -->
Tested rack protection for each rack in the Trigger Room.  Unplugged the fans for each rack and observed the power tripping off for that rack and ONLY that rack.  The system is ready to use.
<!-- Author: Peter Wilson -->


<!-- Date: Tue Nov 23 18:17:21 1999 -->
Turned on power to all racks in the Trigger room EXCEPT 2RR22C-2RR28C which need to have power supply cables redressed.  Turned on power supplies for SVT, L1 Decision, TS, TXPT, DXPT.  FIB crates can be turned on when desired.  DO NOT TURN ON L1CAL or L2CAL crates until manila tags have been removed indicating rewiring is complete.  Sergei will turn on and redownload the clock this evening. 
 
Turned on power to all racks in 1st floor counting room EXCEPT 1RR18D, 1RR27F, 1RR27G all of which need rack protection or power supply work.  All VRB crates are on.  XFT, TDC and CLC may be turned on when desired. 
 
IP addresses have changed.  Do not expect anything 2301 to work immediately. 
 
  
<!-- Author: Peter Wilson -->



<!-- Date: Wed Nov 24 10:45:00 1999 -->
Still investigating rack protection for 2RR24C.  The smoke and drip sensors are forced off to avoid tripping contiguous racks during testing.  2RR24C must not be powered until problem is corrected and tested.
<!-- Author: RLS -->


<!-- Date: Wed Nov 24 14:35:55 1999 -->
<pre>b0tsi00, b0tsi01, b0tsi02 have been restored. 
All use network booting, not the new flash ram image. 
A few other processors have had their address converted, 
however with the power off most have not.</pre>
<!-- Author: patrick -->


<!-- Date: Wed Dec 1 22:00:01 1999 -->
Today, the network performance of b0dau30 became very sluggish. 
Rebooting did not fix the problem. It was finally traced 
to b0dap09 sending it corrupt tcp packets. Rebooting b0dap09 
fixed the problem.
<!-- Author: patrick -->


<!-- Date: Mon Dec 6 15:23:09 1999 -->
<pre>Rack 2RR27C found with tripped circuit breakers 
(LEVEL2_CAL_01 and LEVEL1_CAL_01).  Reset breakers  
and powered on LEVEL2_CAL_01 (LEVEL1 left off) 
</pre>
<!-- Author: W. Badgett -->


<!-- Date: Wed Dec 8 13:19:58 1999 -->
There appears to be a problem with one of the NW (wedge test) crate's power supplies.  See the wedge logbook for more details.
<!-- Author: Steve Hahn -->


<!-- Date: Wed Dec 8 17:21:28 1999 -->
NW crate power supply problem seems to have cured itself (?) at the expense of several ADMEM channels.  See wedge logbook.
<!-- Author: Steve Hahn -->


<!-- Date: Thu Dec 9 16:07:09 1999 -->
Today we made the first attempt to control the hardware event builder using Run Control.
<!-- Author: Steve Tether -->
<!-- Comment: Thu Dec  9 16;10;52 comment by...Steve Tether -->
<a href=/cgi/elog/det-system-elog.pl?nb=evb&action=view&page=6&anchor=16:03:45 target=_top><img src='/elog/gifs/gr_menu.gif' width=19 height=10 border=0></a> See EVB log entry.


<!-- Date: Fri Dec 10 17:55:31 1999 -->
Much progress in Run Controlling the EVB proxy.
<!-- Author: Steve Tether -->
<!-- Comment: Fri Dec 10 17;56;37 comment by...Steve -->
 <a href=/cgi/elog/det-system-elog.pl?nb=evb&action=view&page=6&anchor=17:53:32 target=_top><img src='/elog/gifs/gr_menu.gif' width=19 height=10 border=0></a>See EVB log entry.


<!-- Date: Fri Dec 17 09:03:12 1999 -->
A test of the communication protocol between the TS and the L2 Processor was run.  Stephan Miller and I were able to get the 
two boards to talk to accept and reject events based on commands sent from the L2 Processor.  The board connections and placement 
have been returned to their nominal locations as of this morning.
<!-- Author: Andrew Martin -->


<!-- Date: Fri Dec 17 17:37:34 1999 -->
Rack 1RR27I tripped.  First fault indicated was Drip Sensor.  Wiped drip sensor with Kimwipe and fault cleared.  No moisture was present.  Must have been dust.
<!-- Author: Peter Wilson -->


<!-- Date: Sat Dec 18 09:28:14 1999 -->
Following the power outage, the online computers are back up, 
except for the data logger machine (b0dau31). I leave that 
for the experts. The Oracle database appears to be OK.
<!-- Author: J. Patrick -->


<!-- Date: Tue Dec 21 15:04:28 1999 -->
INstallation of undervoltage release units in counting room relay racks completed by electricians this afternoon.  Tested all racks in the Trigger room and undervoltage releases trip for AC power off and for fan failures.  All racks are ready for use.
<!-- Author: Peter Wilson -->


<!-- Date: Mon Jan 3 11:28:30 2000 -->
Turned on all counting room relay rack power at 9:30am this morning.  At 9:55 all racks were at or below 60 degrees F.  Approved for power up of power supplies.  Two racks have funny temperature readings on the upper sensors: 2RR26C reads 39 degrees and 2RR35I read 51 degrees.
<!-- Author: Peter Wilson -->


<!-- Date: Thu Jan 6 14:10:10 2000 -->
<pre>Problem: b0l2cl05 spontaneously reboots while setting up for  
a run.  Usually during "Setup/Config" transition.  Does not  
happen when Tracer interrupts are disabled. 
 
MVME and Tracer swapped separately with b0l2cl04 crate, and  
problem stays with the crate itself => MVME and Tracer are  
not at fault. 
 
Swapped l2cl04 and l2cl05 TXPT outputs at TXPT crate, slot 20  
inputs 04 and 05 (numbering from zero).  Problem then moved  
to the l2cl04 crate =>  Suspect that the TXPT output 05 in  
slot 20 has some problem. 
 </pre>
<!-- Author: badgett -->


<!-- Date: Fri Jan 7 13:47:17 2000 -->
<pre>Crates on 1st floor tripped off last night (21:58) for unknown  
reasons, Roser investigating.  Crates on 2nd floor tripped 
off about 10:30 today for known reason.  All Crates turned back on. 
Inform your friends... 
</pre>
<!-- Author: SCN -->


<!-- Date: Mon Jan 10 22:58:31 2000 -->
<pre>All Crates on 1st floor and (apparently) the Clock Rack on 
the 2nd floor tripped off at the Rack Protection Fuses, 
today, 22:21.  First Fault was "Power", whatever that means. 
Experts sent email, crates remain off for the time being.</pre>
<!-- Author: SCN -->


<!-- Date: Tue Jan 11 10:52:43 2000 -->
Crates on 1st floor are back on, according to Steve Nahn they were powered up by Rob Roser.  I powered up the clock rack (via the breaker in the back of the rack), and reinitialized the clock about 10:20 this morning.
<!-- Author: Steve Hahn -->


<!-- Date: Tue Jan 11 17:12:37 2000 -->
Found cable in TS Crate from Scramnet module is crushed between Tracer, CPU, and Crate Frame. I held off pulling out until this afternoon to avoid conflicting with other work. Am powering down now to pull it out (but not replace the cable). It is the upper of the two Receive cables for the SCRAMnet module.
<!-- Author: Steve Vejcik -->


<!-- Date: Wed Jan 12 08:30:14 2000 -->
Didn't do the cable extraction   last night-smx people using it. 
Doing it this am (fiber from scramnet). It's really jammed tight 
 so I'm extracting tracer completely.  
Cable hookup: 
 Return: Red Datalink 
 Clock: green datalink 
  
 optical fibers (from top): 
    blue 
    green 
    brown 
CPU appears to have started back up on power up successfully. 
The crushed (green) cable is still there.  Although it is 
mangled, the cover doesn't appear to have been broken. 
The "lock" rail above the cpu was mildly bent during the 
extraction. 
  
<!-- Author: Steve Vejcik -->


<!-- Date: Thu Jan 13 21:51:38 2000 -->
b0dau30 was rebooted to kill off a process using network 
port 8000. This is reserved for use by the web server, 
and with the other process running the web server was 
not operable.
<!-- Author: Jim Patrick -->


<!-- Date: Thu Jan 20 09:33:19 2000 -->
<pre>Crates on 1st floor and 2nd floor all tripped off at 
about 9:20, 01/20/00 - trip being investigated, power should 
be back within the 1/2 hour... 
  
</pre>
<!-- Author: SCN -->
<!-- Comment: Thu Jan 20 09;34;29 comment by...SCN -->
Faulty lug in a 24 V power supply for the shunt trip found,
explains trip...


<!-- Date: Tue Jan 25 11:38:39 2000 -->
<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> 
<html> 
<head> 
   <meta name="Author" content="Steve Hahn"> 
   <meta name="GENERATOR" content="Mozilla/4.51 (Macintosh; I; PPC) [Netscape]"> 
</head> 
<body> 
As of yesterday, all clock fanout crates on the central detector are up 
and running.&nbsp; Clock fanout cables are run to all the central, endwall, 
and COT crates, but not the plug crates.&nbsp; These were meant to be the 
production cables, but due to changes in the how far the north arches need 
to pulled, all these 65' cables must be replaced with 85' cables.&nbsp; 
However, this will not happen until at least the middle of February, so 
I have decided to set up these cables for installation until then.&nbsp; 
Shown below is the layout I have used for each fanout card, each of which 
has two fanout outputs.&nbsp; One card in the SW crate did not light its 
A/B LED correctly, but all other LEDs were correct, so I believe it is 
just a bad LED. 
<br>&nbsp; 
<table BORDER=3 CELLSPACING=3 CELLPADDING=3 BGCOLOR="#CCFFFF" > 
<caption>NW Clock Fanout Crate</caption> 
 
<tr ALIGN=CENTER BGCOLOR="#FFCC66"> 
<td>&nbsp;Slot</td> 
 
<td>Card 
<br>Serial #</td> 
 
<td>Upper 
<br>Fanout</td> 
 
<td>Lower 
<br>Fanout</td> 
</tr> 
 
<tr> 
<td>7&nbsp;</td> 
 
<td>FNT073</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>8&nbsp;</td> 
 
<td>FNT074&nbsp;</td> 
 
<td>CONWT-3</td> 
 
<td>CONWT-4</td> 
</tr> 
 
<tr> 
<td>9&nbsp;</td> 
 
<td>FNT075</td> 
 
<td>CONWT-1</td> 
 
<td>CONWT-2</td> 
</tr> 
 
<tr> 
<td>10&nbsp;</td> 
 
<td>FNT076&nbsp;</td> 
 
<td>CANWT-1</td> 
 
<td>CANWT-1</td> 
</tr> 
 
<tr> 
<td>11 
<br>12&nbsp;</td> 
 
<td>RCVR07</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>13&nbsp;</td> 
 
<td>FNT077</td> 
 
<td>CANWB-1</td> 
 
<td>CANWB-2</td> 
</tr> 
 
<tr> 
<td>14&nbsp;</td> 
 
<td>FNT078&nbsp;</td> 
 
<td>CONWB-1</td> 
 
<td>CONWB-2</td> 
</tr> 
 
<tr> 
<td>15&nbsp;</td> 
 
<td>FNT079</td> 
 
<td>CONWB-3</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>16&nbsp;</td> 
 
<td>FNT080</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
</table> 
 
<table BORDER=3 CELLSPACING=3 CELLPADDING=3 BGCOLOR="#CCFFFF" > 
<caption>NE Clock Fanout Crate</caption> 
 
<tr ALIGN=CENTER BGCOLOR="#FFCC66"> 
<td>&nbsp;Slot</td> 
 
<td>Card 
<br>Serial #</td> 
 
<td>Upper 
<br>Fanout</td> 
 
<td>Lower 
<br>Fanout</td> 
</tr> 
 
<tr> 
<td>7&nbsp;</td> 
 
<td>FNT064</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>8&nbsp;</td> 
 
<td>FNT065&nbsp;</td> 
 
<td>CONET-3</td> 
 
<td>CONET-4</td> 
</tr> 
 
<tr> 
<td>9&nbsp;</td> 
 
<td>FNT066&nbsp;</td> 
 
<td>CONET-1</td> 
 
<td>CONET-2</td> 
</tr> 
 
<tr> 
<td>10&nbsp;</td> 
 
<td>FNT067&nbsp;</td> 
 
<td>CANET-1</td> 
 
<td>CANET-1</td> 
</tr> 
 
<tr> 
<td>11 
<br>12&nbsp;</td> 
 
<td>RCVR09</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>13&nbsp;</td> 
 
<td>FNT069&nbsp;</td> 
 
<td>CANEB-1</td> 
 
<td>CANEB-2</td> 
</tr> 
 
<tr> 
<td>14&nbsp;</td> 
 
<td>FNT070&nbsp;</td> 
 
<td>CONEB-1</td> 
 
<td>CONEB-2</td> 
</tr> 
 
<tr> 
<td>15&nbsp;</td> 
 
<td>FNT071&nbsp;</td> 
 
<td>CONEB-3</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>16&nbsp;</td> 
 
<td>FNT072</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
</table> 
 
<table BORDER=3 CELLSPACING=3 CELLPADDING=3 BGCOLOR="#CCFFFF" > 
<caption>SW Clock Fanout Crate</caption> 
 
<tr ALIGN=CENTER BGCOLOR="#FFCC66"> 
<td>&nbsp;Slot</td> 
 
<td>Card 
<br>Serial #</td> 
 
<td>Upper 
<br>Fanout</td> 
 
<td>Lower 
<br>Fanout</td> 
</tr> 
 
<tr> 
<td>7&nbsp;</td> 
 
<td>FNT024</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>8&nbsp;</td> 
 
<td>FNT025</td> 
 
<td>COSWT-3</td> 
 
<td>COSWT-4</td> 
</tr> 
 
<tr> 
<td>9&nbsp;</td> 
 
<td>FNT026&nbsp;</td> 
 
<td>COSWT-1</td> 
 
<td>COSWT-2</td> 
</tr> 
 
<tr> 
<td>10&nbsp;</td> 
 
<td>FNT027&nbsp;</td> 
 
<td>CASWT-1</td> 
 
<td>CASWT-1</td> 
</tr> 
 
<tr> 
<td>11 
<br>12&nbsp;</td> 
 
<td>RCVR06</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>13&nbsp;</td> 
 
<td>FNT028</td> 
 
<td>CASWB-1</td> 
 
<td>CASWB-2</td> 
</tr> 
 
<tr> 
<td>14&nbsp;</td> 
 
<td>FNT029&nbsp;</td> 
 
<td>COSWB-1</td> 
 
<td>COSWB-2</td> 
</tr> 
 
<tr> 
<td>15&nbsp;</td> 
 
<td>FNT030</td> 
 
<td>COSWB-3</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>16&nbsp;</td> 
 
<td>FNT031</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
</table> 
 
<table BORDER=3 CELLSPACING=3 CELLPADDING=3 BGCOLOR="#CCFFFF" > 
<caption>SE Clock Fanout Crate</caption> 
 
<tr ALIGN=CENTER BGCOLOR="#FFCC66"> 
<td>&nbsp;Slot</td> 
 
<td>Card 
<br>Serial #</td> 
 
<td>Upper 
<br>Fanout</td> 
 
<td>Lower 
<br>Fanout</td> 
</tr> 
 
<tr> 
<td>7&nbsp;</td> 
 
<td>FNT038</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>8&nbsp;</td> 
 
<td>FNT039&nbsp;</td> 
 
<td>COSET-3</td> 
 
<td>COSET-4</td> 
</tr> 
 
<tr> 
<td>9&nbsp;</td> 
 
<td>FNT040&nbsp;</td> 
 
<td>COSET-1</td> 
 
<td>COSET-2</td> 
</tr> 
 
<tr> 
<td>10&nbsp;</td> 
 
<td>FNT041</td> 
 
<td>CASET-1</td> 
 
<td>CASET-1</td> 
</tr> 
 
<tr> 
<td>11 
<br>12&nbsp;</td> 
 
<td>RCVR10</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>13&nbsp;</td> 
 
<td>FNT043</td> 
 
<td>CASEB-1</td> 
 
<td>CASEB-2</td> 
</tr> 
 
<tr> 
<td>14&nbsp;</td> 
 
<td>FNT060&nbsp;</td> 
 
<td>COSEB-1</td> 
 
<td>COSEB-2</td> 
</tr> 
 
<tr> 
<td>15&nbsp;</td> 
 
<td>FNT061</td> 
 
<td>COSEB-3</td> 
 
<td>&nbsp;</td> 
</tr> 
 
<tr> 
<td>16&nbsp;</td> 
 
<td>FNT062</td> 
 
<td>&nbsp;</td> 
 
<td>&nbsp;</td> 
</tr> 
</table> 
 
</body> 
</html>  
<!-- Author: Steve Hahn -->


<!-- Date: Fri Jan 28 12:06:23 2000 -->
Previous problem with crate b0l2cl05 with the TXPT  
connection is no longer present.   We don't know why. 
Watch for future problems.  
<!-- Author: W. Badgett -->


<!-- Date: Thu Feb 17 20:55:34 2000 -->
Preparing for scheduled power outage tomorrow morning.  Power turned off on all VIPA crate power supplies in 1st and 2nd floor counting rooms.  Also turned off Clock Fanout crates and VIPA crate in COT teststand in clean room.  
<!-- Author: Peter Wilson -->


<!-- Date: Fri Feb 18 10:14:04 2000 -->
All counting room racks powered up.  All crates that were powered up at 20:00 last night (2/17) have been turned on.  
<!-- Author: Peter Wilson -->


<!-- Date: Thu Feb 24 15:23:47 2000 -->
We have had repeated clock rack trips this morning and into the early afternoon.  The first occurred about 1100 and was a drip alarm.  The second occurred at 1105 and also was a drip alarm.  At this point, we opened up the clock rack from the side and wiped the drip sensor.  There was some bluish-green residue on it, but no clear indication of a drip.  About 1200, the next trip occurred.  We again looked for any indication of a drip but found nothing damning.  We checked all connections for AC power and on the DIN rail.  The next trip occurred about 1230.  At this point, I waited until Roberto (and later Bill Wickenburg) showed up.  Bill hypothesized that vibration in the rack was causing the drip sensor to creep up toward an anti-vibration grommet around the chilled water pipe to the heat exchanger located directly above the sensor.  This grommet consists of a rubber piece with an inset metal piece, and conceivably the metal was shorting the drip sensor.  Bill and Roberto lowered the drip sensor. 
<p> 
I reset the clock (for the fourth time).  So far we have not had additional trips. 
<p>
<!-- Author: Steve Hahn -->


<!-- Date: Mon Mar 6 15:40:49 2000 -->
I have updated the trialflash.table vxboot 
file.  It now sets up the current version of 
 tracer cdfvme code-which is in a public/official 
 area now. 
<!-- Author: Steve Vejcik -->


<!-- Date: Tue Mar 7 13:00:59 2000 -->
<pre>VxWorks flavors of cdfvme_common have now been deleted from ups. 
Specifically, I have done the following: 
b0dau30.fnal.gov> ups undeclare cdfvme_common v1_0 -fVxWorks+5.3 -q ppc 
b0dau30.fnal.gov> ups undeclare cdfvme_common v1_0 -fVxWorks+5.3 -q 68k 
b0dau30.fnal.gov> ups undeclare cdfvme_common v1_0 -fVxWorks+5.2 -q 68k 
b0dau30.fnal.gov> ups undeclare cdfvme_common devel -fVxWorks+5.3 -q 68k 
b0dau30.fnal.gov> ups undeclare cdfvme_common devel -fVxWorks+5.3 -q ppc 
b0dau30.fnal.gov> ups undeclare cdfvme_common devel -fVxWorks+5.2 -q 68k 
</pre>
<!-- Author: Steve Vejcik -->


<!-- Date: Wed Mar 15 08:58:46 2000 -->
The ethernet ports for the VME processors on the 
first and second floor have been reconfigured 
for fast ethernet. Most but not all were rebooted 
so they are now running in the configuration. 
NOT rebooted were the SVX, tsi, and l1gl00 
systems.
<!-- Author: J. Patrick -->


<!-- Date: Mon Mar 20 08:59:36 2000 -->
<pre>CRATES TRIPPED 
All Crates on 1st and 2nd Floor, potentially 
down in the Hall as well, tripped off this 
morning accidently, at about 830.  Transgressor 
was lashed once with a wet noodle.  It is safe 
to turn your crates back on.</pre>
<!-- Author: SCN -->


<!-- Date: Mon Mar 20 12:27:03 2000 -->
Summary of integration test on Friday, March 17 
(since no one else wrote anything): 
 
Problems were encountered trying to read 
central calorimeter crates with the hardware 
event builder. 
VRB link test failed on all south arch crates 
(2,3,4,5,10,11,12,13) 
Note that the previous evening all had been 
successfully tested, except b0ccal13 had a problem. 
The reason for the south crate failures is unknown. 
b0ccal08 was non-responsive (power supply faulted) 
With b0ccal00, system would take 61 events then 
get a busy timeout. Upon looking at the VRB 
enable mask, it was being set so that all 
channels were enabled, even though only b0ccal00 
was in the partition. This would cause busy 
to be set after about this number of events. 
The problem will have to be investigated by the 
event builder people.
<!-- Author: J. Patrick -->


<!-- Date: Tue Mar 21 19:57:02 2000 -->
ECW is back on for all racks on 1st and 2nd floor.  Rob Roser powered up most racks on 1st and 2nd floor, I powered remainder and checked that there were no trips on DMACS.  I powered up all crates with cards inserted on 1st and 2nd floor.  No trips or problems.  I also initialized clock. 
<p> 
Rick Tesarek and I powered up one rack (CANWB) to see if 400 Hz was being delivered from MG #2 after Dwight Featherstone reported it was up and working.  No problem with power; some problems seen in rack, will deal with them tomorrow morning. 
<p> 
Also, note SW clock fanout crate has no power, needs extension cord from movable cable tray.  And NE clock fanout crate has no power, looks like someone unplugged my extension cord.  Will deal with these also tomorrow morning. 
<p>
<!-- Author: Steve Hahn -->


<!-- Date: Wed Mar 22 19:53:07 2000 -->
With the help of Bill Badgett,  the TS crate has been reconfigured.  Partition (0,1,2,3,4) now corresponds to slot (3,5,7,9,11).  The appropriate changes have been made in the databases as well.  This fixed a misunderstanding which took place during the initial crate configuration.
<!-- Author: Andrew Martin -->


<!-- Date: Thu Mar 23 15:45:26 2000 -->
COSWT tripped this afternoon with a first fault of the upper middle crate temperature.  The historical record showed temperature wandering in the mid eighties and up to ninety-one but not approaching the trip point of one hundred.  The sample rate is about one minute and there is no time delay on overtemperature trips.  Our hypothesis is that a poor connection may exist in the thermometer circuit.  Unless this becomes too much of a nuisance, the connectors will be checked on Tuesday.  We had a subsequent trip from a drip detector which was probably due to someone touching it.  Wiring for the Raychem drip detector cable is being installed nearby.
<!-- Author: Schmitt -->


<!-- Date: Tue Apr 4 10:27:15 2000 -->
Turned on all racks on the 2nd floor, and one or two on the first floor after Bill Wickenburg and company turned off racks to install AC power clips.  Turned on all VME crates with cards in them, and reset the clock.
<!-- Author: S. Hahn -->


<!-- Date: Fri Apr 21 15:58:48 2000 -->
Mask EM channel 3 (counting 0...5) in DIRAC_73 in the hardware database due to a stuck bit causing continuous triggers.  This is the card in slot 14, crate LEVEL1_CAL_04
<!-- Author: badgett -->