<!-- Title: 12:50:41  Sun Mar  4 2001 -->
<!-- Crewchief: Lester -->
<!-- Op1: Petra -->
<!-- Op2: &nbsp; -->
<!-- Op3: &nbsp; -->
<!-- Op4: &nbsp; -->
<!-- Op5: &nbsp; -->
<!-- Op6: &nbsp; -->
<!-- Notes: -->
<pre>loadbox test done successfully 
WIB test done successfully 
connected to wedge. Everything inits; we get a few RO errors  
on layer 4, mostly truncated RO (chips 5,6,13) and some CAP ID  
e.g. from 0x1 to 0x21 to 0x2d and back to 0x1. 
The only obvious things we saw were: 
low DVDD current on layer 0 and on layer 4 (only 90) at a voltage  
of 5.63 ( tested at sidet with 5.72V). Maybe adjustment of the  
DVDD4 helps to get rid of the RO errors.  
The other four layers readout fine.</pre>


<!-- Date: Wed Mar 21 12:47:29 2001 -->
<pre>Power supply tested after adjustment of DVDD4 (+100 mV) 
Looks ok, apart that the layer-2 with SVX loadbox  
appear to draw no bias current. It correctly trips both for overcurrent and for interlock. Volts ok.</pre>
<!-- Author: Sehban and Saverio -->


<!-- Date: Mon Mar 26 17:06:15 2001 -->
<pre>Voltage on dvdd4 adjusted to 5.47 but still getting readout  
errors on layer 4 at a rate of a few percent. When running layer4  
seperately did not get errors but probably did not run for long 
enough. Wrote ~svxii/daq/svx/sw/laser84.svx at around event 560 
starting to see c0 bytes before fib headers: 
 
 
c1c10000 00000000 c0e2671c f98a200d 310c320d 3306340c 3504360c 370d380d  
39053a0d 3b0d3c0d 3d053e0d 3f0c301c 311d3214 3314341e 351d361c 371e381d  
391d3a1d 3b1c3c1c 3d1f3e1f 3f143024 312c322c 3324342c 3525362f 372c382d  
392c3a2c 3b2f3c2c 3d2f3e2c 3f2c303f 3135323c 333c3435 353e363d 373e383d  
393f3a3e 3b343c3d 3d3d3e3d 3f34304f 3144324f 33443444 35493644 3744384c  
394c3a4f 3b4d3c4f 3d443e44 3f4e3054 315d325e 335e3454 355d365d 375e385e 
 
 checked voltages nothing had tripped.</pre>
<!-- Author: Slave of the Nile, Captain Jean -->
<!-- Comment: Mon Mar 26 19;14;48 comment by...Koshka&#39;s pet human -->
<pre>Typo: 5.47 -> 5.74</pre>
<!-- Date: Mon Mar 26 17:12:02 2001 -->
<table><tr><td><a href=/elog/notebooks/silicon_pc/e060-SVX-W-BRL-W-End-P-6/Mon_Mar_26_2001_171151.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=e060-SVX-W-BRL-W-End-P-6&action=view&page=-2  align='top'></td><td>Rails, grassy layer 2 (bias current = 25 microamps)</a></td></tr></table>
<!-- Author: Ha Ha Ha -->



<!-- Date: Mon Apr 2 19:16:52 2001 -->
<pre>1) IGV finds that in integration run taken on 4/1/00 SB0W6 layer0 
FE looke like its dead. 
 
2) Reran SB0W6 - layer 0 has cell id 63 almost all the time! 
z-side all chips always cellid 63. Phi side occasionally get 
legal cell id numbers. 
 
3) took layer 0 data run  
 
/cdf/people2/svxii/daq/svx/sw/data/laser116.svx 
 
4) Gino - try charge injecting. Can see charge inject  
occasionally on phi side only. Lester changed delayed bxing to  
116 more stable charge inject on phi side but still mostly 
cellid 63s.</pre>
<!-- Author: Mad Mary and Calm Gino -->
<!-- Comment: Mon Apr  2 19;27;49 comment by...Mad Mary -->
<pre>Voltages on layer 0 look normal

Voltage		V	I
AVDD0		7.71	335
DVDD0		5.33	30

In case sensing is broken on DVDD and voltage is low at
the hybrid we manually HRR then send L1a then readout to
make sure no DVDD sags because of high duty cycle. Still
get cellid 63.</pre>
<!-- Date: Mon Apr 2 19:18:21 2001 -->
<table><tr><td><a href=/elog/notebooks/silicon_pc/e060-SVX-W-BRL-W-End-P-6/Mon_Apr__2_2001_191807.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=e060-SVX-W-BRL-W-End-P-6&action=view&page=-4  align='top'></td><td>noise plot showing the occasional charge inject on the phi side of L0</a></td></tr></table>
<!-- Author: Mad Mary -->


<!-- Date: Mon Apr 2 19:19:55 2001 -->
<table><tr><td><a href=/elog/notebooks/silicon_pc/e060-SVX-W-BRL-W-End-P-6/Mon_Apr__2_2001_191943.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=e060-SVX-W-BRL-W-End-P-6&action=view&page=-6  align='top'></td><td>Cellid distributions for layer 1 and layer 0 chips running simultaneously. Phi side chips on layer 0 are on log scale.</a></td></tr></table>
<!-- Author: Mad Mary -->



<!-- Date: Wed Apr 11 18:58:07 2001 -->
<pre>Stand-alone testing shows no dropped readout on layer 4. 
 
Layer 0 has cell 63 at all time on both sides.  I would guess l1a or prd1 broken.  </pre>
<!-- Author: tony and lester -->


<!-- Date: Fri Apr 13 15:39:30 2001 -->
<pre>After further testing, it is clear that prd1 is open or stuck high on layer 0.  The ladder always get cell 63, the pedestal moves with the ramp ped value and the pipe read order does not change the pedestal. 
 
The problem will have to be between the channel ddr output and the SVX chips.   I do not see how we can fix this. 
 
</pre>
<!-- Author: tony -->


<!-- Date: Sat Apr 14 10:49:18 2001 -->
<pre>Power supply DVDD0 reduced to 5.24 volts and DVDD4 increased to  
5.95V. Layer 0 still dead FE with cell id 63 problems. Layer 4 
looks like readout is fine. Took  
 
~svxii/daq/svx/sw/data/laser224.svx  
 
with bias on and layers 1,2,3,4 
 
Somewhere around event 90 we had a glitch and system halted. 
Did an HRR (clock problems?) again around event 400. This kept 
happening. 
</pre>
<!-- Author: M.Bishai F. Palmonari -->


<!-- Date: Tue May 1 16:43:40 2001 -->
<pre>Tested unbiased in preparation for access. 
L0 still has cell 63 problem.  
All other layers no readout errors 100 events... 
(i.e. L4, previously reported dropping, has no problems) 
</pre>
<!-- Author: Letser -->


<!-- Date: Wed May 9 15:48:29 2001 -->
This JC was found to be <a href= 
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=25&frame=2&anchor=21:40:23'> 
disconnected</a>!  Hard to believe it worked at all...not clear 
when this happened, and if it can explain the L0 problem.
<!-- Author: SCN -->


<!-- Date: Sat May 12 08:03:18 2001 -->
<pre>Replugged cables into the power supply after cratezilla effect,  
crate 5, slot 0. Retest wedge after found unplugged and plugged  
back in. First test I believe. 
All init, L0 still bad, new errors: 
 
L3 gives the following: 
OO sequence, no EOR, data overrun, truncate !Reproducable effect,  
didn't go away! One event taken: ok up to 7f, then ffd0 d0c2 c2c4 
 
L1,2,4 look ok. 
 
 
Wedge not RTVed into the slot yet.</pre>
<!-- Author: Petra -->
<!-- Comment: Sat May 12 22;26;27 comment by...Paul Shepard -->
<pre>Can we switch this layer3 to a different DOIM cable and FIB and see
if the errors go away?  In this case we could probably forget about
it.   It is also true that this is the inner ring and it probably isn't 
that important to do a full debug on it as it isn't in our way.</pre>

<!-- Comment: Sat May 12 22;29;52 comment by...Paul Shepard -->
<pre>Whether we debug it or let it go for now we should probably put RTV
on it as it apparently has a large propensity for coming unplugged.</pre>

<!-- Comment: Tue May 15 09;25;09 comment by...SCN -->
<pre>This ladder is "dropping readout" meaning at some time
its OBDV goes south and the fib starts putting in 
fill characters ("d0") and then truncates ("c2c2c4").
This either means OBDV is flaky in the PC or FTM, or we
need to bring up some voltages.  Since OBDV is there
sometimes, I would first boost DVDD (I think, ask Mary).</pre>


<!-- Date: Tue May 29 08:08:00 2001 -->
Pre Plug close testing: 
<ul> 
<li> L0 still dead, pipecell 63s 
<li> L3 had tripping on Over Voltage at first, now settled down, 
but potential FTM problem (Chan 127 -> Chan 95 indicates bit 5) 
and "dropping readout".  Turned Channel off (at Fib) for test. 
<li> L1,2,4 fine. laser369.svx Unbiased laser371.svx Biased  
<ul>
<!-- Author: SCN, SW -->
<!-- Comment: Tue May 29 08;08;47 comment by...SCN (only-my screwup) -->
</UL> </UL>
HTML now unscrewed up?


<!-- Date: Fri Jun 22 10:52:28 2001 -->
<pre>retested for integration: 
 
L0 still has cell 63 problem 
L3 is intermittently dropping readout. Some runs fine. 
 
otherwise fine.</pre>
<!-- Author: Lester -->


<!-- Date: Thu Jun 28 08:37:05 2001 -->
During access we investiated L3dropping readout. <br> 
 
Measured light levels:<br> 
<table> <tr> <th> Chan 
</th> <th> OBDV </th> <th> 0 </th> <th> 1 </th> <th> 2 </th> <th> 3 </th> <th> 4 </th> <th> 5 
</th> <th> 6 </th> <th> 7 </th> </tr> <tr> <td> SB0W6-3 </td> <td> 170 </td> <td>190 </td> <td> 180</td> <td> 130 </td> <td>112</td> <td>170 </td> <td> 190 
</td> <td> 120</td> <td>125</td> </tr> </table>  
<br> 
We swapped channels 3,4. The problem moved to channel 4 
but L4 of wedge now seems to have problems as well. 
<br> 
Swapped FTM #134 (565878) out #162 (565879) in. <br> 
Retested, only L4 has problems now. <br> 
The layer four problem seems to involve dropping one byte 
of data after chip 5 which then gets channel/data mixed.  
<!-- Author: Lester & SCN -->


<!-- Date: Sat Jun 30 13:19:19 2001 -->
<pre>Retested this wedge, still had readout problems on Layer3 
but only on last two chips (can readout 8 chips OK). 
 
L4 problem still there. Both will be left out. 
</pre>
<!-- Author: Lester -->


<!-- Date: Tue Jul 17 08:34:32 2001 -->
<pre>Chan 4: No chan bytes   
        light high -&gt; introduced plastic attenuator -&gt; OK 
    CH-4 is now ok for read-out.</pre>
<!-- Author: Lester, Saverio -->


<!-- Date: Thu Jul 19 11:52:53 2001 -->
From FTM debugging. <br> 
Light Levels: <table> <tr> <th> Chan </th> <th> OBDV </th> <th> 0 </th> <th> 1 </th> <th> 2 </th> 
<th> 3 </th> <th> 4 </th> <th> 5 </th> <th> 6 </th> <th> 7 </th> </tr>  
<tr> <td>  
SB0W6-4 
</td> <td>  
880 
</td> <td> 
820 
</td> <td>  
800 
</td> <td>  
900 
</td> <td>  
600  
</td> <td>  
900 
</td> <td> 
400  
</td> <td>  
1000 
</td> <td>  
900 
</td> </tr>  
</table>  
<!-- Author: Lester -->


<!-- Date: Mon Oct 29 20:37:46 2001 -->
<pre>Layer 2 drops readout at the beginning of last chip. A0</pre>
<!-- Author: Lester, Sinead, Saverio -->


<!-- Date: Tue Nov 6 17:32:38 2001 -->
<pre>The initialization stream get stuck between the back end and front end of the 9th chip.  not sure way.</pre>
<!-- Author: affolder -->


<!-- Date: Thu Nov 8 16:00:23 2001 -->
<pre>summary from the access 
======================= 
DOES NOT INIT reads back 0s. When we try to read it out we get only 8 perfect chips  
(all the PHI chips plus 3 Z chips) then the 9th chip reads out but have CAPID out of  
sync and very low noise as if the FE is not powered. we get 705 mA on the AVDD current  
while usually a L2-L3 10 chipper devices are around 800 mA. 
This chip is obviously far from the jumper, I can only 
think of a chip failure. 
 
currents (before init / after init / during RO): 
AVDD = 335 / 700 / 700 
DVDD = 110 / 110 / 110 
doesn't init 
 
TRAVELER:  
F237X   NO REPAIRS starting date 06/06/2000 
Q261x   NO REPAIRS starting date 05/15/2000 
5Z23    date 05/11/2000 
  REPAIRS DONE NONE 
  DIE     110-003 210-059 110-007 110-008 110-011 
5P130   date 05/09/2000 
  REPAIRS DONE Bus 5B open to chip 5 
  DIE     158-017 158-019 158-020 158-021 158-023 
 
GINO: NO HELP FROM HISTORY 
 
SB0W6L2 and SB1W8L2 have the same exact symptoms as sb4w3l2  
and sb5w3l4. In SB1W8L2 the first 5 chip readout properly.   
The 6th chip has a low noise and cell id problems.  In SB0W6L2,  
the first 8 chips  read out properly. the 9th chip has low noise  
and a cell id problem.  Both have the init stream stop in the first problem chip  
between the back end and front end. The chip's back end bits affect its  
performance but the front end bits do not. The problem went away in SB0W6L2 after  
some tests.  The init stream got passed through all chips, the current went to the  
normal values and the readout of the whole ladder is good.  I assume the problem  
is a soft open or short and will return. 
4 of the 8 ladders Gino had me look at had this problem.   
Hopefully we can point the symptoms at a single line problem and can figure out  
if it is something we are doing or not. 
</pre>
<!-- Author: Petra -->
<!-- Comment: Thu Nov  8 16;15;56 comment by...Petra -->
<pre>this entry was for L2</pre>


<!-- Date: Mon Jan 21 21:05:21 2002 -->
Making Summary for L3 DVDD problem: 
<ol> 
<li> This wedge was one of the very first to be run- April 1, 2001 
<li> May 29, 2001 - unspecified over-voltage problem which 
      then settled down. RO errors from the very begining of 
      plugging 
<li> May 30, 2001 - was OK- 9th chip gives trouble 
<li> June 3 - reported with DRO problems 
<li> Jun 30, 2001 - unspecified readout problems on last 2 chips 
 <li>               light level measrements and FTM swaps on Jun 28 
<li> July 10, voltage, current plot report says all OK 
<li> Jyuly 28, L3 not included in .cratematch..pl output 
<li> Aug 8, says to put L3 back in??? 
<li> Aug 16, L3 is in for a calibration 
<li> Aug 30 - vrb swap 
<li> Sep 17, stiill in -  
<li> oct 17 HST - all OK 
<li>  Oct 31 - OK in map of world 
<li>  Nov 13 - DRO is back in HST - chip A0, but wasn't reproducible 
<li> Dec 21 is the first time I see a mention of DVDD over current on this guy. 
</ol> 
Summary - I cannot find in any elog when L3 was taken out because of the DVDD problem. 
  
<!-- Author: Jean -->


<!-- Date: Wed Feb 6 16:18:57 2002 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=e060-SVX-W-BRL-W-End-P-6&action=view&page=-7&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=e060-SVX-W-BRL-W-End-P-6&action=view&page=-8  width='300' align='top'></td><td>Here is the current for SB0W6L3 DVDD (YELLOW)  from turning it ON to when it tripped Due to the color (YELLOW) it is not  so evident but there is a reading at around 1 A before the trip. This is consistent with the software trip that needs a reading before acting...</a></td></tr></table>
<!-- Author: Gino -->
<!-- Comment: Wed Feb  6 16;21;35 comment by...Gino -->
<pre>Jean and I turned ON this ladder SB0W6L3 because it was not clear to us what was wrong with it.
Here you see current vs time on 02/05/2002 for the 20 minutes we were able to keep it STDBY.
THE DAQ was completely IDLE during this time frame.
The current is normal for a while but then it goes to the roof.
We should repeat the exp[eriment when we have the possibility to initialize it and read it out.</pre>