<!-- Title: 18:20:33  Mon Jun 10 2002 -->
<!-- Crewchief: Silicon -->
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<pre>Access in progress</pre>


<!-- Date: Mon Jun 10 18:28:25 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Jun_10_2002_182813.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-536  align='top'></td><td>End of readout for SB0W9L4, which had drop readout last chip last channel. From top to bottom: bit 7, bit 0 and OBDV.</a></td></tr></table>
<!-- Author: Lester -->


<!-- Date: Mon Jun 10 18:29:44 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Jun_10_2002_182941.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-538  align='top'></td><td>Beginning of readout for SB0W9L4, which had drop readout last chip last channel. From top to bottom: bit 7, bit 0 and OBDV. For reference to timing of above entry.</a></td></tr></table>
<!-- Author: Lester -->


<!-- Date: Mon Jun 10 18:44:13 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Jun_10_2002_184411.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-542  align='top'></td><td>Beginning of readout of SB1W5L4 showing internal cause of bit 1 low bit 2 high. Traces from top: bit 2, bit 1, and OBDV.</a></td></tr></table>
<!-- Author: Lester -->


<!-- Date: Mon Jun 10 18:50:38 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Jun_10_2002_185035.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-544  align='top'></td><td>Light of e250. From top, bit 0, bit 1, and OBDV. Seems fine, although this hdi has bit 1 low even after RX swap.</a></td></tr></table>
<!-- Author: Lester -->


<!-- Date: Mon Jun 10 18:59:10 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Jun_10_2002_185902.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-546  align='top'></td><td>Priority passing from chip A1 to A0 of SB4W5L3. Shows internal cause of dropped readout at  Last chip. Traces from top, bit 7, obdv, and bit 0. Note lack of chip ID and strange behaviour of bit 7.</a></td></tr></table>
<!-- Author: Lester -->


<!-- Date: Mon Jun 10 19:00:31 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Mon_Jun_10_2002_190028.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-548  align='top'></td><td>Closeup of above passing priority SB4W5L3 chip A1 to A0. Top trace bit 7, middle trace OBDV. </a></td></tr></table>
<!-- Author: Lester -->


<!-- Date: Mon Jun 10 19:43:20 2002 -->
<pre> 
  ISL Cooling 
 ========================= 
 
  &gt; we've most the stuff to the west, where we ought be 
    targetting epoxy by 0000 Tuesday 
 
  &gt; Bob, Rich and Julia are working to extract the wire 
    stuck in E-3-SUP-B... this affects the 6F-C-2 circuit; 
    they ought move to the west starting at about 2000 and 
    will re-establish the cooling on the east side then 
</pre>
<!-- Author: Doug -->


<!-- Date: Mon Jun 10 19:47:31 2002 -->
<p>SB3W7L2 was re-wired to have symmetric bias splitting.  It has been reinstalled, retested, and recabled.<p>
<!-- Author: Napora and Pursley -->


<!-- Date: Mon Jun 10 20:40:38 2002 -->
<h3>Splitting Hairs</h3> 
Hah-gotcha!  Really we're splitting the DAQ otra vez, 
back to ISL East and Other.  All files updated.  I guess 
the former state of "East" wasn't possibly useful since the SRC/SRCTM/Backplane gave bit 1 stuck high on SRC-FFO Glinks, 
which caused FIb Command Overflows.  Moving the SRC to slot 6 fixed the problem.
<!-- Author: SCN -->


<!-- Date: Mon Jun 10 23:19:14 2002 -->
<pre>Tested the SVXII NW crate after the work Lester and his team did today. 
 
Shortely: 
 
6 RXs swapped  
3 problems solved  
3 problems not present warm before/after the swap 
0 problems introduced 
 
More in details 
 
SB0W0L0		OK 
SB0W0L1		OK 
SB0W0L2		Out AVDD2 chip 87 and 89 
SB0W0L3		OK  
SB0W0L4		OK 
SB0W1L0		OK 
SB0W1L1		OK 
SB0W1L2		IN AVDD2 chip a4 (PHI SIDE OK) 
SB0W1L3	**~	OK 
		did NOT have any problem during the pre-work test 
		Still the RX was swapped for OBDV problems. 
SB0W1L4		Out AVDD UNFIXABLE 
SB0W2L0		OK 
SB0W2L1		OK 
SB0W2L2		IN (PHI SIDE OK) LOST DVDD on Z side 
		   Device still INITIALIZE but from the Z side you see only  
		   Chip IDs, CAP IDs and sometimes channel 0 and its data. 
SB0W2L3		OK 
SB0W2L4		OK 
SB0W3L0		OK 
SB0W3L1		OK 
SB0W3L2	**+	OK 
		The RX was swapped because of OBDV problems, FIXED  
		(Before gave 89d0d0c2 c2c40000 and nothing else) 
		THE SYMPTOMS WERE THERE EVEN IN THE WARM PRE-WORK TESTS. 
SB0W3L3		OK 
SB0W3L4		OUT DVDD UNFIXABLE 
SB0WAL0		OK 
SB0WAL1		OK 
SB0WAL2		OK 
SB0WAL3		OK 
SB0WAL4		OK 
SB0WBL0		OK 
SB0WBL1		Out because there is an open on the BIAS line (UNFIXABLE) 
SB0WBL2		OK 
SB0WBL3		OK 
SB0WBL4		Bit 6 STUCK LOW only on chip 8a. 
		THE SYMPTOMS WERE THERE EVEN IN THE WARM PRE-WORK TESTS. 
		The symptoms are there even in the data but in several other  
		chips in this ladder so I would say BIT 6 STUCK LOW NOT INTRODUCED. 
SB1W0L0		OK 
SB1W0L1		OK 
SB1W0L2		OK 
SB1W0L3		OK 
SB1W0L4		OK 
SB1W1L0		OK 
SB1W1L1		OK 
SB1W1L2		OK 
SB1W1L3		OK 
SB1W1L4		OK 
SB1W2L0	**~	OK  
		SWAPPED BECAUSE OF OBDV PROBLEM  
		did NOT have any problem during the pre-work test 
		DOES NOT HAVE ANY PROBLEM NOW.		 
SB1W2L1		OK 
SB1W2L2		read back ffss probably lost DVDD on Z side PHI SIDE  
		NO HST DONE. 
SB1W2L3		OK 
SB1W2L4	**~	OK 
		SWAPPED BECAUSE OF OBDV PROBLEM  
		did NOT have any problem during the pre-work test 
		DOES NOT HAVE ANY PROBLEM NOW.		 
SB1W3L0		Out open in the BIAS LINE. 
SB1W3L1		OK 
SB1W3L2		OK 
SB1W3L3		OK 
SB1W3L4		CHIP 86 HAS PROBLEMS. NO HST DONE 
SB1WAL0		OK 
SB1WAL1		OK 
SB1WAL2		OK 
SB1WAL3		OK 
SB1WAL4		OK 
SB1WBL0		OK 
SB1WBL1		OK 
SB1WBL2		OK 
SB1WBL3		OK 
SB1WBL4		OK 
SB2W0L0		OK 
SB2W0L1		OK 
SB2W0L2		OK 
SB2W0L3		BIT 6 STUCK HIGH RARELY 
SB2W0L4		OK 
SB2W1L0		OK 
SB2W1L1		OK 
SB2W1L2		OK 
SB2W1L3		OK 
SB2W1L4		OK 
SB2W2L0		OK 
SB2W2L1		OK 
SB2W2L2		OK 
SB2W2L3	**+	OK 
		Swapped the RX because of c2c2 termination without  
		any data. SUCCESSFUL 
SB2W2L4		OK 
SB2W3L0		OK 
SB2W3L1		IN AVDD2 ON CHIP A2 
SB2W3L2		OK 
SB2W3L3		OK 
SB2W3L4	**+	RX SWAPPED NO PROBLEM NOW 
		During the pre-work warm test there was a BIT 6 stuck low 
 
</pre>
<!-- Author: Gino -->


<!-- Date: Tue Jun 11 00:05:29 2002 -->
<center><a href='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-549&button=yes' target='xxx' onclick='jswindow()'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-549' width='300'></a><a href='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-550&button=yes' target='xxx' onclick='jswindow()'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-550' width='300'></a></center>
<!-- Author: Andy H., Rich S. -->
<!-- Comment: Tue Jun 11 00;07;48 comment by...Andy H. -->
ISL E cooling put back together and leak-checked, flow
re-established.  We will probably need to set new default
settings for the supply valves -- you can see where I currently
set them in the picture above.


<!-- Date: Tue Jun 11 03:00:01 2002 -->
<pre>Set the blocked CC trip limits to 25C (which really means 40 because of +15 in PLC) in order to have more protection while we run the no-longer blocked ladders.</pre>
<!-- Author: David and Mircea -->


<!-- Date: Tue Jun 11 03:50:52 2002 -->
<pre>Found SB2W5 in SBY; turned it OFF</pre>
<!-- Author: ADF -->
<!-- Comment: Tue Jun 11 04;36;38 comment by...Gino -->
<pre>My fault.
</pre>


<!-- Date: Tue Jun 11 04:44:37 2002 -->
<pre>SB3W10L3 had a software protection trip on DVDD. 
We should take the FIB OUT, modify it to ISL FIB and put it back IN. 
 </pre>
<!-- Author: Gino -->


<!-- Date: Tue Jun 11 04:54:25 2002 -->
<pre>Tested b0fib04 (NorthEast) in preparation for FIB swaps. 
Took events with SVXDAQ. 
 
All FIB's had at least one RX swap so tested all of them. 
 
For each FIB, took 100 events with SVXDAQ in 3 (or more) sets 
    (a) With ladders with no known problems 
    (b) Adding ladder(s) one at a time which are to 
	       have RX's swapped 
    (c) Adding ladder(s) one at a time which have other 
	       historical problems 
 
These are all saved in the daq/svx/ne/data area;  
ADF / CDF / SVX logbook p. 88-93 contains the  
laserxxx.svx file names. 
 
First, to the candidate RX swaps 
-------------------------------- 
 
SB3W1 L3      Bit 0 high not seen (no errors) 
 
SB3W2 L0      Illegal channels and oo sequence confirmed 
 
SB3WA L1      Bit 4 high 1% not seen (no errors-statistics?) 
 
SB4W0 L1      Bit 1 high confirmed 
 
SB4W2 L1      DRO not seen (no errors) 
 
SB4WA L3      CAPID / Illegal channel confirmed 
SB4WB L2      CAPID / OO Sequence confirmed 
 
SB5W0 L1      Bit 6 apparently high confirmed 
SB5W1 L1      DRO not seen (no errors) 
SB5W1 L3      OBDV problems not seen (no errors) 
 
SB5W3 L0      OBDV problems not seen (no errors) 
 
SB5WA L3      Bit 0 low not seen (no errors) 
 
 
Next, to brand new minty-fresh problems (not in DB) 
--------------------------------------------------- 
 
SB3WA L3      Won't init or read out; gives *SWPT* 
 
SB4W1 L1      Chip 0 no readout (c1c1) 
SB4W1 L2      CAPID errors 
SB4W1	      Bxing byte 
 
SB5W0 L4      CAPID errors 
 
Finally, everything in something like an order 
---------------------------------------------- 
      
 
SLOT	 Ladder		DB		Tonight 
====	========       ====		======= 
8	SB3W0 L0	OK		OK 
	SB3W0 L1	OK		OK 
	SB3W0 L2	Bias		OK (didn't test bias) 
	SB3W0 L3	OK		OK 
	SB3W0 L4	Bias		OK (didn't test) 
	SB3W1 L0	OK		OK 
	SB3W1 L1	OK		OK 
	SB3W1 L2	OK		OK 
	SB3W1 L3	RX		OK 
	SB3W1 L4	Bias		OK (didn't test) 
 
9	SB3W2 L0	RX		RX 
	SB3W2 L1	OK		OK 
	SB3W2 L2	DVDD		Didn't test 
	SB3W2 L3	OK		OK 
	SB3W2 L4	OK		OK 
	SB3W3 L0	OK		OK 
	SB3W3 L1	OK		OK 
	SB3W3 L2	OK		OK 
	SB3W3 L3	OK		OK 
	SB3W3 L4	AVDD2		AVDD2 
 
10	SB3WA L0	OK		OK 
	SB3WA L1	RX		OK 
	SB3WA L2	OK		OK 
	SB3WA L3	OK		No init, no r/o, SWPT 
	SB3WA L4	OK		OK 
	SB3WB L0	OK		OK 
	SB3WB L1	AVDD2		AVDD2 
	SB3WB L2	OK		OK 
	SB3WB L3	OK		OK 
	SB3WB L4	OK		OK 
 
12	SB4W0 L0	OK		OK 
	SB4W0 L1	RX		RX 
	SB4W0 L2	Leading 00	Didn't test  
	SB4W0 L3	OK		OK 
	SB4W0 L4	Unfixable	Didn't test 
	SB4W1 L0	No init		Gives CAPID errors 
	SB4W1 L1	OK		No chip 0 (c1c1) 
	SB4W1 L2	OK		CAPID errors 
	SB4W1 L3	OK		OK 
	SB4W1 L4	AVDD2?		OK 
 
13	SB4W2 L0	Bit 6 high	OK 
	SB4W2 L1	RX		OK 
	SB4W2 L2	OK		OK 
	SB4W2 L3	OK		OK 
	SB4W2 L4	OK		OK 
	SB4W3 L0	Capid		Capid 
	SB4W3 L1	OK		OK 
	SB4W3 L2	AVDD2		AVDD2 
	SB4W3 L3	NN R/o		OK (Didn't test NN) 
	SB4W3 L4	OK		OK 
 
15	SB4WA L0	OK		OK 
	SB4WA L1	OK		OK 
	SB4WA L2	OK		OK 
	SB4WA L3	RX		RX 
	SB4WA L4	OK		OK 
	SB4WB L0	No init		No init / c2c2 
	SB4WB L1	OK		OK 
	SB4WB L2	RX		RX 
	SB4WB L3	OK		OK 
	SB4WB L4	OK		OK 
 
16	SB5W0 L0	OK		OK 
	SB5W0 L1	RX		RX 
	SB5W0 L2	OK		OK 
	SB5W0 L3	OK		OK 
	SB5W0 L4	OK		CAPID errors 
	SB5W1 L0	OK		OK 
	SB5W1 L1	RX		OK 
	SB5W1 L2	OK		OK 
	SB5W1 L3	DRO		OK 
	SB5W1 L4	AVDD2?		Many errors 
 
18	SB5W2 L0	DVDD		CAPID 
	SB5W2 L1	OK		OK 
	SB5W2 L2	DVDD		OK 
	SB5W2 L3	OK		OK 
	SB5W2 L4	OK		OK 
	SB5W3 L0	RX		OK 
	SB5W3 L1	ADC		OK 
	SB5W3 L2	DVDD		OK 
	SB5W3 L3	OK		OK 
	SB5W3 L4	CAPID		CAPID 
 
19	SB5WA L0	OK		OK 
	SB5WA L1	OK		OK 
	SB5WA L2	OK		OK 
	SB5WA L3	RX		OK 
	SB5WA L4	Dup.Chan NN	OK (did not test NN) 
	SB5WB L0	AVDD2		AVDD2 
	SB5WB L1	OK		OK 
	SB5WB L2	OK		OK 
	SB5WB L3	ADC		OK 
	SB5WB L4	OK		OK 
</pre>
<!-- Author: ADF -->


<!-- Date: Tue Jun 11 04:59:55 2002 -->
<P> 
We tested all the newly cooled east ISL.  
26 of 32 ladders had no problems. The problems with the other 6 are: 
<UL> 
 <LI> IB4W2L1 has a bad RX.(We swapped the fiber and the problem stayed with the RX.) 
 <LI> IB4W1L3 bias 0 does not get to the detector 
 <LI> IB3W2L0 bias 0 does not get to the detector 
 <LI> IB3W2L1 bias 0 does not get to the detector 
 <LI> IB3W2L2 bias 0 draws high current and eventually trips at 50uA (max setting). 
</UL> 
These need attention tomorrow. For now, we will retest other parts on the east. 
<P>
<!-- Author: David and Mircea -->


<!-- Date: Tue Jun 11 06:51:06 2002 -->
<pre>SB2W5L0 BIT1 AND BIT 6 LOW. 
	SWAPPED THE FTM CHANNEL WITH SB2W5L1 BIT 1 FOLLOWED THE 
		THE RX AND BIT 6 DISAPPEARED. 
	CLEANED AND GREASED NO IMPROVEMENTS 
	REMOVED FTM AND RESEATED RX (WAS A BIT AT AN ANGLE) 
		WITHOUT ANY IMPROVEMENT. 
	LESTER IS PROBABKY RIGHT. 
		THE FTM BOARD MIGHT BE PROBLEMATIC. 
 
SB3W4L1	CLEANED AND GREASED THE FIBER-FTM CONNECTION 
	BIT 6 LOW PROBLEM WENT AWAY 
 
SB3W5L0	BIT 1 HIGH AFTER SWAP. 
	CLEANED AND REGREASED THE FIBER-FTM CONNECTION 
	WE NOW HAVE A KIND OF "RANDOM" OO SEQUENCE ERROR. 
	BIT 5 is high once per chip per evt for the transition 	 
	3f--&gt;40 that instead is 3f--&gt;60 
	BIT 1 is high once in a while for chip 0 only for the  
		transiton 4f--&gt;50 that instead is a 4f--&gt; 52 
	see laser1101.svx 
	I THINK THIS IS A GOOD SPOT TO TRY THE SUPERFIB.</pre>
<!-- Author: Gino -->
<!-- Comment: Tue Jun 11 07;59;38 comment by...Gino and Jason -->
<pre>SB4W7L2		CLEANED AND GREASED
SB5W7L1		CLEANED AND GREASED
		STILL NOT ABLE TO TEST THEM BECAUSE THE FIB 	
		CRATES ARE RELUCTANT TO COME BACK BACK UP AFTER 
		THE ALARM OF 7:00 AM.
</pre>
<!-- Date: Tue Jun 11 07:51:25 2002 -->
<pre>Tried to test L00 east. Swapped b0svx06 to east, but can't do anything with DAQ now since the gas alaram brought all the power down. Gave up and returned b0svx06 to the west.</pre>
<!-- Author: David -->



<!-- Date: Tue Jun 11 08:37:25 2002 -->
<pre>Out of the 8:00 am meeting. 
 
COT work in the EAST BORE is in progress RIGHT NOW. 
 
Rick Tesarek has to swap TLDs on both bores. He is going to try  
to do it on the east today in the afternoon (not sooner than 3:00  
pm). As soon as this is done Mat Herndon should start the final  
visual inspection and dressing of the cables on the EAST bore.  
 
At 3:00 pm today there will be some CLOCK WORK but I believe it will not affect us as we are running now.</pre>
<!-- Author: Gino -->


<!-- Date: Tue Jun 11 10:08:36 2002 -->
<h3>ISL Mods</h3> 
removed Fibs<table> 
<tr><th>Wedges<th>Crate<th>slot<th>SN<th>PREP</tr> 
<tr><td>SB3WA/B<td>fib04<td>10<td>136<td>560621</tr> 
<tr><td>Spare<td>diagnostic<td>18<td>1126<td>560611</tr></table> 
to take to FCC for ISL Mod.
<!-- Author: SCN -->
<!-- Comment: Tue Jun 11 10;08;58 comment by...SCN -->
1126 should be 126


<!-- Comment: Tue Jun 11 12;50;23 comment by...SCN -->
Fib S/N 136 reinstalled with ISL mod
<!-- Date: Tue Jun 11 12:33:53 2002 -->
<p>Two things: 
<ol> 
<li>SB5W3 Layer 2 DVDD Voltage was set to 5.2 V as per Gino's request. 
<li>IB3W2 Bias 0.1 and Bias 2.0 were jumpered for the coarse current scale as per Chris's request. 
</ol>
<!-- Author: Napora and Pursley -->
<!-- Comment: Tue Jun 11 18;13;35 comment by...CH -->
<pre>Sensitivity scale for IB3W2 0.1 and 2.0 changed in HDWDB.</pre>
<!-- Date: Tue Jun 11 16:02:13 2002 -->
<p>50 Ohm Terminators have been put on the CAENnet lines for those crates that needed them (2, 3, 6, 8, 9, 11, 13, and 15).  Also, the CAENnet line for crate 6 was run in backwards (to the output instead of the input connector), this has been fixed. 
 
<p>This will reduce the noise on these lines and hopefully cut down on the number of communication errors (spontaneous turn-ons, etc.)<p>
<!-- Author: Napora and Pursley -->


<!-- Date: Tue Jun 11 16:18:43 2002 -->
Adjusted Last Chip ID for AVDD2 ladder SB4W3L2 (FIB_22 pipe 7 in hdwdb, b0fib04 Sl 13) just as done <a href= 
'/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=109&frame=2&anchor=15:11:43'>before</a>.  I did not chagne the status 
of the online flag, but someone should make sure 
this gets turned online when reintegrating after the access.   
<!-- Author: SCN -->


<!-- Date: Tue Jun 11 17:01:16 2002 -->
<pre> 
 ISL Cooling Update 
 ======================= 
 
  &gt; Monday eve the wire was removed from the east side and 
    flow was re-established 
 
  &gt; We started targetting epoxy on the west side around 0100 
    Tuesday; we've opened 3 lines since then;  the newly opened 
    lines are: 
       - 6B-C-1 
       - 6B-IN-2 
       - 6B-IN-3 
    These are in addition to the 6B-C-2 line opened last Oct 
 
  &gt; Unless the access is extended, we plan on re-establish flow 
    to the West during Thursday owl so that it's ready by 0800 
    for testing/check-out 
</pre>
<!-- Author: Doug -->


<!-- Date: Tue Jun 11 17:29:48 2002 -->
<pre>ISL East layer 6 commissioning complete, all 16 HDIs are online 
in HDWDB and working fine except 1 half ladder (see below). 
 
26/32 half-ladders worked out of the box, problems below: 
 
1) IB4W1L3: no current drawn on bias 0. 
2) IB4W2L1: garbled data - follows Rx. 
3) IB3W2L0,L1: no current drawn on bias 0  
4) IB3W2L0, trips at 50uA on bias 1. 
5) IB3W2L2, trips at 50uA on bias 0. 
 
All but #1 were solved: 
 
#2 was solved with Rx swap. 
#3 was solved by re-connecting JC in bore. 
#4,5 were solved by changing sensitivity scale in supply. 
 
#1 was investigated in bore, connections were found to be OK. </pre>
<!-- Author: Chris Hill -->



<!-- Date: Tue Jun 11 18:55:54 2002 -->
<h3>DAQ SPLIT</h3> 
I Split the DAQ again, this time into "East" and "west" <B> with L00 VRBS on the EAST </B>.  All files are updated.  Please 
restart your DAQs if they are currently running.
<!-- Author: SCN -->


<!-- Date: Wed Jun 12 00:42:44 2002 -->
Added some insulation to the SVX dew point sensor connectors. 
Hopefully this will cut down on its sensitivity to people 
working in the east bore.
<!-- Author: Andy H., Matt H., Gino B. -->


<!-- Date: Wed Jun 12 01:06:07 2002 -->
<pre>Dressing of the cable on EAST Bore Completed. 
Mat believe it is a good job but it should be rechecked  
tomorrow after the COT finish their job. 
Visual inspection of J.C.s: 
Inspected all but IB4W2 and IB3W2 ( I could NOT find a way there). 
Here are the peculiarities I found (all minor): 
SB3W1, the remote sensing cable was a little out of the female 
     connector. Pushed back in. Not impact expected. 
SB5WB Out a little toward PhI 0, PUSHED BACK with almost 
           negligible impact. 
SB4W8 Out a little toward PhI 0, PUSHED BACK with almost 
           negligible impact. (let's see the bias of layer 1). 
 
We should repeat this in the mid-lower part of the North side after the COT has done tomorrow looking for gross problem. 
</pre>
<!-- Author: Gino and Mat -->
<!-- Comment: Wed Jun 12 09;24;59 comment by...herndon -->
<pre>The COT LV problem is on the upper mid north side.
There are also cages to be replaced on the lower mid north side.</pre>
<!-- Date: Wed Jun 12 08:59:30 2002 -->
<table border=0><td><tr><td bgcolor=#e0e030><H2>Request from Owl shift</H2> 
Please notify owl shift (SciCo) when 
working in the collision hall, especially in the bore.   
This makes life easier for the single person on shift who needs 
to respond to all alarms. 
</td></tr></td></table>
<!-- Author: Jason -->



<!-- Date: Wed Jun 12 12:39:30 2002 -->
<h3>Very very odd</h3> 
Lester asked me to look at SB2W5L4 which was giving the wrong  
Chip IDs, and only 10 Chips.  The feature is the following: 
<ul> 
<li> Chip Ids appear as<BR> 8d 88 83 a6 a5 a4 a3 a2 a1 a0 but should be <BR> 8d 8c 8b 8a 89 88 87 a6 a5 a4 a3 a2 a1 a0  
<li> All the data looks ok (although a few bit errors appeared 
in later running) 
<li> The ladder initializes fine 
<li>This effect comes and goes at low rate but at high L1A rate 
(by changing # of L2R/L1A from 0 to 254 eg) occurs every event 
</ul> 
I swapped the DOIMS Chan 9 and Chan 8, and the problem followed 
the DOIM cable, which implies it is something wrong with 
the Chip/PC, rather than the DAQ.  <B>DOIMS are STILL SWAPPED</B>.  I am told Lester <i>wants</i> to look at 
the length of OBDV streams to see if it is sending enough OBDV.
<!-- Author: SCN -->


<!-- Date: Wed Jun 12 12:47:39 2002 -->
<pre>I re-inspected the EAST BORE with S. Nahn. 
 
We could not see any cable moved. 
The COT people did a very clean job. 
 
Now I'm going to try and get the BAGGY closed ASAP. 
 
Gino</pre>
<!-- Author: Gino -->


<!-- Date: Wed Jun 12 14:53:06 2002 -->
<pre>EAST BAGGY IS INSTALLED. 
 
Steve N. is now starting to TEST the EAST. 
 
</pre>
<!-- Author: Gino -->


<!-- Date: Wed Jun 12 16:12:06 2002 -->
<pre> 
  ISL Cooling Update 
 =============================== 
 
  &gt; another line was opened: 6B-IN-1; we've fully recovered 
    then the 6B-IN "bulkhead" 
 
  &gt; we've opened 5/6 lines on the west;  the remaining line 
    has one open elbow; the second (blocked) elbow is difficult 
    to get to and has a protrusion which makes it difficult to  
    get the prisms into the elbow to target effectively;  we'll 
    keep trying w/ a set of modified prism holders 
 
  &gt; starting at 2300 tonight, rich stanek and andy hocker will 
    re-establish flow to the west side; </pre>
<!-- Author: Doug -->


<!-- Date: Wed Jun 12 21:56:10 2002 -->
<pre>THE EAST side of the silicon has been tested after the Baggy was installed on the EAST BORE. 
No problem were seen and Rob Roser got the go-ahead to close the EAST PLUG. This will happen tomorrow morning. 
 
Steve Nahn is now splitting the DAQ into ISL-WEST and EVERYTHING ELSE. 
</pre>
<!-- Author: Gino -->
<!-- Comment: Wed Jun 12 22;20;07 comment by...SCN -->
<h3>Done DAQ Splitting</h3>To the best of my knowledge there
is now one SRC running the b0svx08 crate as well as b0fib01 and
b0fib03, and the other running everything else.  All system.cfg
files under the ~svxii/daq/[svx,isl]/[ne,nw,se,sw]/ directories
are updated.


<!-- Date: Wed Jun 12 22:39:12 2002 -->
<pre>All the enables have been DISABLED. 
The 5V has been turned OFF. 
 
IN order to LEAK test the ISL cooling on the WEST there is a need 
for a positive pressure GAS test that would fire the interlock system. 
Rob roser is coming up to bypass (in a temporary basis) such interlock. 
 
</pre>
<!-- Author: Gino -->


<!-- Date: Thu Jun 13 02:47:29 2002 -->
The evening crew opened the last blocked ISL cooling circuit on the west!
<!-- Author: Andy H. -->


<!-- Date: Thu Jun 13 02:48:27 2002 -->
<center><a href='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-551&button=yes' target='xxx' onclick='jswindow()'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-551' width='300'></a><a href='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-552&button=yes' target='xxx' onclick='jswindow()'><img src='/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-552' width='300'></a></center>
<!-- Author: Andy H. -->
<!-- Comment: Thu Jun 13 02;49;27 comment by...Andy H. -->
New and inproved ISL W cooling established.  Also opened up CCE1 supply valve a bit more.


<!-- Date: Thu Jun 13 08:19:22 2002 -->
<pre> 
  ISL Cooling Update 
 ============================= 
 
  &gt; the last blocked line on the west was opened last night; 
    we've fully recovered the west ISL 
 
  &gt; flow to the west side was re-established at about 0200 
    this morning;  both sides of ISL now have cooling 
 
  &gt; i'll bug andy/eva to ensure the ilock logic is correctly 
    set-up (ie. very few RTDs now monitor blocked cooling lines) 
 
  &gt; FINAL SCORE:  East - 4/6 lines OPEN 
                  West - 6/6 lines OPEN 
 
  We're confident we can recover the last two lines with a set 
  of modified prism holders, some longer borescopes and about  
  &gt;= 1 week access.</pre>
<!-- Author: Doug -->


<!-- Date: Thu Jun 13 11:59:06 2002 -->
<h3>Ran with TS and EVB</h3><a href= 
'/cgi/elog/elog.pl?nb=2002&action=view&page=491&frame=2&anchor=11:14:50'>Took a few runs</a> with the "we're not ISL West" DAQ and 
the TS and EVB, plus a few wedges.  Things look good.  then 
gave the DAQ back to Lester
<!-- Author: SCN -->


<!-- Date: Thu Jun 13 12:59:06 2002 -->
<pre>Swapped fibers between IB1W5L4 and IB1W5L2 to allow check of a bit error. 
</pre>
<!-- Author: David -->


<!-- Date: Thu Jun 13 13:47:14 2002 -->
<h3>Only One True DAQ</h3> 
With Lester's blessing, I re-integrated the ISL West 
DAQ into the "real DAQ" driven by the SRC in b0svx02. 
There is only one from here on out, so you have to share. 
I thought this better than waiting the weekend until I get 
back because something is screwed up.<P> 
Lester is downstairs working on some RXs or something.
<!-- Author: SCN -->


<!-- Date: Thu Jun 13 13:56:34 2002 -->
<P> 
We tested all the newly cooled ISL on the west (52 half ladders). 
<P> 
The results are: 
<UL> 
<LI> 
One HDI has an AVDD short which probing showed to be downstream of the power supply. We wiggled the LV cables in the bore and found that the resistance increases slightly when we move the cable in the region where it passes from the 30 degree crack into the bore. So, we suspect damage there. Repairing this would take O(1day) of bore access. 
<LI> There is one bad chip on IB1W4L1 which gets garbled if not sparsified. 
<LI> Some bias current scale jumpers may need to be changed, but this should be decided after we go cold and dark. 
<LI> The temperatures behaved well during testing. 
</UL> 
<P> 
So, thanks to the cooling heroes, we can now run 132 of the 152 L6 half ladders (=86%). Of those, 129 (=98%) are good. 
 
<P> 
The details of all this morning's tests are <A HREF="http://nucsb03.fnal.gov/cgi-bin/lgbk?user=stuart&ent=14644">here</A>. 
<P>  
<!-- Author: David and John -->


<!-- Date: Thu Jun 13 15:37:23 2002 -->
<p>Installed a PS for the PitWIB in crate 7 slot 0.  LV, remote sense and enable have been cabled.<p>
<!-- Author: Napora and Pursley -->


<!-- Date: Thu Jun 13 18:11:13 2002 -->
<pre>East BLM's were assembled.</pre>
<!-- Author: Ricardo E., Eva H. -->


<!-- Date: Thu Jun 13 22:40:33 2002 -->
<table><tr><td><a href=/elog/notebooks/silicon/Thu_Jun_13_2002_224025.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-554  align='top'></td><td>RED is STDBY,  BLACK is 40 V,  BLUE is 45 V,  GREEN is 50 V. 45 is already optimal</a></td></tr></table>
<!-- Author: Gino -->


<!-- Date: Thu Jun 13 22:58:49 2002 -->
<pre>REPORT from the EAST SURVEY before closing the plug on the EAST yesterday. 
 
SVXII 
ID	IN/OUT	Description of the problem. 
 
SB3W2L2	 OUT 1	LOW R path between DVDD and GND		 
SB3W3L4	 IN	AVDD2 on chip 8a 
SB3W7L2  OUT 2	Pending testing of BIAS modification 
SB3W8L0	 OUT 3	LOST DVDD ON Z SIDE Trips on AVDD O-C during data taking 
SB3W8L2	 IN	Gives c2c2. Potential OBDV problem 
SB3W10L3 OUT 4	YET TO BE UNDERSTOOD 
 
SB4W0L4  OUT 5	150 mA on AVDD no data at all UNFIXABLE 
SB4W1L4	 IN	Potential AVDD2 on chip a0 
SB4W3L2	 IN	AVDD2 on chip a4 
SB4W4L2	 IN	HIGH BIAS CURRENT 
SB4W4L4	 IN	HIGH BIAS CURRENT 
SB4W5L3	 IN	Digital trouble on the Z side 
SB4W6L2	 OUT 9	AVDD2 on chip 89 REMOVED HDWDB 
SB4W6L3	 IN	BIT 3 STUCK LOW NOT FIXABLE. GIven to the OFFLINE. 
SB4W7L2	 IN	a channel repeat itself. 
SB4W7L4	 IN	DATA OVERRUN 00f3. 
SB4W8L1	 OUT 8	OPEN on bias connection internal REMOVED HDWDB 
SB4W8L2	 OUT 6	YET TO BE UNDERSTOOD 
SB4W9L4	 OUT 7	LOST DVDD on Z side	 
 
SB5W0L2	 IN	BIT 6 HIGH once in a while 
SB5W1L4	 IN	YET TO BE UNDERSTOOD 
SB5W5L3	 IN	BIT 2 STUCK  
SB5W11L0 IN	AVDD2 on chip a1 
</pre>
<!-- Author: Gino and Henri -->


<!-- Date: Thu Jun 13 23:00:55 2002 -->
<pre>Report for SVXII from West survey before closing the West plug: 
 
 
SB2W1L2: 
	Draws 1 uA at the nominal voltage of 40V: file laser729.svx  
	Standby: file 730 
	Changed bias V to 45V: file 731. Still draws 1 uA. 
	bias 50V: file 732. Draws 2 uA. 
	Bias has been changed to 45V in HWDB. 
 
SB2W3L1:	 
	Failed init (0's). Known AVDD2 pb at chip a2. File laser733.svx 
 
SB2W2L4:	 
	Bit 5 low rarely. File laser733.svx 
 
SB2W5L4: 
	File laser197.svx.  
	Init succeeded but draws 700-1200 mA on DVDD. 
	We have removed it from the HWDB. 
 
SB2W4L4: 
	File 197 
	Digital errors. Many chips drop readout. 
	Known pb. We keep it in. 
 
SB2W7L1: 
	Optical pb (known and unfixable). Kept in. File 198. 
 
SB2W9L4:  
	AVDD2 chip. Known pb. Taken out. File 200. 
 
SB2W11L0: 
	Failed init. Read out OK. Unknown pb. File 734. 
 
SB1W0L2: 
	Draws 0 uA. File 735. 
	Standby: file 737. 
	Clearly biased looking at noise. 
 
SB1W0L4: 
	Draws 0 uA. File 735. 
	Standby: file 737. 
	Clearly biased looking at noise. 
 
SB1W1L2: 
	Draws 0 uA. File 735. 
	Standby: file 737. 
	Clearly biased looking at noise. 
 
SB1W3L0: 
	Offline. Known pb. File 737. 
 
SB1W2L2:  
	Does not init: ff. File 737. 
	We will keep it in for more data. 
 
SB1W3L2: 
	Does not init: 0's. File 737. 
	 
SB1W3L4: 
	Chip 88 has capid error and low pedestal. 
	File 737. 
 
 
SB1W4L2: 
	Known DVDD pb. Stays out of HWDB. File 201. 
 
SB1W5L4: 
	Known pb: bit errors (1 low, 2 high). 
	Z side clearly biased looking at noise. File 201. 
 
SB1W6L2: 
	Draws 0 uA. File 202. 
	Standby: file 203. 
	Clearly biased looking at noise in biased/standby. 
 
SB1W8L0: 
	NO INIT 0s back,  
		PIPE 0 has AVDD2 symptoms on chip a1 
			DVDD 0-1 ma 
			AVDD 165 mA 
 
SB0W0L2: 
 	Offline. Known AVDD2. 
 
SB0W1L4: 
	Offline. Known unfixable. 
 
SB0W1L2: 
	Online. AVDD2 on chip a4 
 
SB0W11L1: 
	OFFLINE. open on BIAS line 
 
SB0W3L4: 
	Offline. Known. Kept out of HWDB. 
 
SB0W2L0: 
	Draws 0.27 uA.  
	Clearly biased looking at noise plot. File 748. 
 
SB0W3L1: 
	Draws 0.04 uA.  
	Clearly biased looking at noise plot. File 748. 
 
SB0W4L3: 
	Readout errors. Known pb. Kept in HWDB (Phi side OK). File 205. 
 
SB0W6L0: 
	Offline. Known pb. Kept out. 
 
SB0W6L2: 
	Failed init with 0's. Known pb. Kept in. File 206. 
 
SB0W6L3: 
	Offline. Known pb. Kept out. 
 
SB0W6L4: 
	Failed init with 0's. Known pb. Kept in. File 206. 
 
SB0W7L2: 
	Failed init with 0's. Known pb. Kept in. File 206. 
 
SB0W8L3: 
	Offline. Known pb. Kept out.  
 
SB0W8L2: 
	Failed init with 0's. 
	Bit stream read back was masked a while ago. 
	File 207. 
 
</pre>
<!-- Author: Gino and Henri -->


<!-- Date: Thu Jun 13 23:17:01 2002 -->
<pre>THE WEST Baggy was up around 6:30 pm. 
Henri and myself tested SVXII.  
Not many surprises all the problems were  
already listed in the problem DB 
Implemented changes in HDWDB according to previous 2 entries. 
David and John are starting to test L00 and ISL. 
COT is doing their HV TEST and still do not have  
an estimate for when we will go COLD. 
 
 
</pre>
<!-- Author: Gino -->


<!-- Date: Fri Jun 14 04:21:44 2002 -->
<pre>Changed jumper for IB1W5 in order to change the bias1 current problem. It was drawing a large current close to the limit.</pre>
<!-- Author: David and John -->


<!-- Date: Fri Jun 14 04:41:23 2002 -->
<pre>THE WEST Baggy was up around 6:30 pm. 
Henri and myself tested SVXII.  
Not many surprises all the problems were  
already listed in the problem DB 
Implemented changes in HDWDB according to previous 2 entries. 
David and John are starting to test L00 and ISL. 
COT is doing their HV TEST and still do not have  
an estimate for when we will go COLD. 
 
 
</pre>
<!-- Author: Gino -->


<!-- Date: Fri Jun 14 05:00:32 2002 -->
<pre>Test of L00 and ISL in the west is complete. 
 
We found the following problems: 
1. IB0W4L4 bias0 not on (It's a known problem.) Nothing is done to it. 
 
2. IB1W5L3 draws too much bias1 current. We changed jumper to reset the current limit. It's fine now. 
 
3. IB1W0L1 had a high AVDD current and failed to initialize. We swapped the fib timing cable and they went away. Swapped it back and they came back. Lester has been contacted to look into a fib or FEM swap. 
 
4. IB1W4L3, IB2W2L3, and LB0W4L0 drew no bias0 current and were not depleted. Needs bore access. Cannot do anything about them now. 
 
5. IB2W0 was developed after an swap yesterday morning. Steve suspected that it was due to VRB monitoring program was being initialized at that time. The problem persisted even after sparse mode. Suspect VRB problem. 
 
6. LB0W3L3 drew no bias current but was depleted. 
</pre>
<!-- Author: David & John -->


<!-- Date: Fri Jun 14 09:34:50 2002 -->
We're going cold...
<!-- Author: Andy H. -->


<!-- Date: Fri Jun 14 10:26:37 2002 -->
Cooldown complete.  I have set the temperature trip limits to 
<a href= 
'http://www-cdfonline.fnal.gov/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=107&frame=2&anchor=10:30:12'> 
what were the appropriate values,</a> but we will need to fine 
tune the ISL since we'll have a bigger heat load now.  Also, 
we need to tell the interlocks that a lot of RTDs have moved out 
of the "blocked CC" category. 
<!-- Author: Andy H. -->


<!-- Date: Fri Jun 14 11:33:12 2002 -->
<pre>West side BLM's assembled and everything checked out ok.  HV on, etc.</pre>
<!-- Author: Ricardo E., Eva H. -->