<!-- Title: 15:13:07  Thu Feb 14 2002 -->
<!-- Crewchief: Peter Wilson -->
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<!-- Notes: -->
<pre>Time for a new L1 Logbook </pre>


<!-- Date: Wed Mar 20 16:32:18 2002 -->
<pre>Put Carla's new proms in the track prefred card 
(yesterday) 
</pre>
<!-- Author: Greg -->


<!-- Date: Wed Mar 20 16:46:31 2002 -->
<pre>Taking a test run (141351) with TEST_TWO_TRACK_V30 which has 11 single track triggers defined.  The test run is to verify the new prefred proms & two track trigger DB are compatible.  Success - all 12 programmable two track bits check out through FRED.</pre>
<!-- Author: Peter, Greg, & Nathan -->


<!-- Date: Wed Apr 10 18:06:24 2002 -->
<pre>Last night, the data board in slot 14 (board 8, serial #29) was had some hot bits and then cause bus errors.  Since then, I have been switching boards around to accommodate all errors and the pin testing in the xtrp test crate.  The final configuration in b0xtrp00 is that the board in slot 14 was removed, the board from slot 10 (board 4, serial #?) was placed into slot 14, and the databoard with serial #3 was placed in slot 10.  I hope that this configuration is now stable.</pre>
<!-- Author: James Kraus -->


<!-- Date: Thu Apr 18 18:06:10 2002 -->
<pre>Due to frequent done time outs, the board 23 had to be removed from slot 8.  I replaced it with board 14.</pre>
<!-- Author: James Kraus -->
<!-- Comment: Thu Apr 18 21;09;08 comment by...James Kraus -->
<pre>Board 14 showed the same stuck bits as before, so I replaced it with board 29.</pre>


<!-- Date: Tue Apr 30 17:24:45 2002 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=l1&action=view&page=-15&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=l1&action=view&page=-15  width='300' align='top'></td><td>phi=3,eta=22, bit 0 ( good bit)</a></td></tr></table>
<!-- Author: carla -->


<!-- Date: Tue Apr 30 17:26:18 2002 -->
<table><tr><td><a href=/cgi/elog/det-system-elog.pl?nb=l1&action=view&page=-16&button=yes target='xxx' onclick='jswindow()'; align=top><img src=/cgi/elog/det-system-elog.pl?nb=l1&action=view&page=-16  width='300' align='top'></td><td>phi =3, eta =22, bit 3 (bad)</a></td></tr></table>
<!-- Author: carla -->


<!-- Date: Thu May 2 14:00:11 2002 -->
<pre>Looked at some towers with bits stuck to ground: 
in b0l1cl00 
phi = 0, eta 21 pha,  -&gt; bad cable 
phi = 3, eta 22 pha   -&gt; bad cable 
phi = 3, eta 2  pem   -&gt; two bent pins on back plane, AUX side  </pre>
<!-- Author: carla -->


<!-- Date: Mon May 13 11:26:03 2002 -->
<pre>Summary of Cal bad bits from Carla 
 
Date: Thu, 09 May 2002 12:21:25 -0500 
From: Carla Pilcher &lt;carla@hep.uchicago.edu&gt; 
To: pjw@fnal.gov, feild@fnal.gov, tecchio@fnal.gov, tesarek@fnal.gov, 
     robine@fnal.gov 
Cc: frisch@hep.uchicago.edu, case@hep.uchicago.edu 
Subject: status of trigger bits 
 
This is the state of the dead trigger bits at this moment: 
 
        eta     phi             bit 
 
        22      2       em      5 
 
        11      5       had     0 
        16      19      had     0(both on and off) 
        21      0       had     1 cable bad downstairs 
        22      3       had     4 cable bad downstairs 
 
        16      3       em      bent pins on the backplane, backplane removed 
and fixed, now ok 
 
new problem since May 1, dead bit in energy word between Dirac and Cratesum, 
b0l1cl00, dirac in slot 4, bit2. Not a bent pin on the backplane. 
 
carla 
</pre>
<!-- Author: Peter and Greg -->


<!-- Date: Wed May 22 15:18:28 2002 -->
<pre>I swapped a cratesum board in b0l1cl00, slot 8 (old #3, new #2) 
to look at the missing bit between Dirac and Cratesum. By reading the L2 buffers in CS it doesn't look that the problem is in cratesum, but trigmon doesn't see the error anymore. Swapping Dirac had not fix the problem either.</pre>
<!-- Author: carla -->


<!-- Date: Thu May 23 21:21:41 2002 -->
<pre>I swapped board 10 out of slot six because it seemed to have two-track problems, and replaced it with board 14.  However, board 14 had readout errors, so I replaced it with board 23.</pre>
<!-- Author: James Kraus -->


<!-- Date: Wed May 29 12:16:19 2002 -->
<pre>Changed e-proms im sumet pfred.</pre>
<!-- Author: carla -->


<!-- Date: Fri May 31 01:26:23 2002 -->
<pre>I entered the new XTRP-CMX constants into the database</pre>
<!-- Author: James Kraus -->


<!-- Date: Wed Jun 5 17:06:36 2002 -->
L1 cables <br><br> 
 
June 3-4 2002:<a href=http://hep.uchicago.edu/cdf/smaria/dirac/cable0.txt>diagnostics/pulsing results</a><br><br>  
 
June 4-5 2002 
<a href=http://hep.uchicago.edu/cdf/smaria/dirac/cable.txt>Access,investigation by inspection, fix with Roberto</a>
<!-- Author: spiropulu -->


<!-- Date: Thu Jun 6 16:32:51 2002 -->
<pre>_Peter&Maria June 6__ 
 
***There is also a missing bit (bit 2) between dirac in slot 4 and cratesum in slot 8,  b0l1cl00.  It should correspond to pin 41, column B for Dirac, and pin 42, column A for Cratesum.*** 
Brought the power supply down (cal_00). Slide aux cards slots  
4 5 6 7 .  
 
Check  backplane contunuity between the pins in question. 
Found no problem.  
 
Comments: on slot 4 the J12 backplane connector seemed to have 
wiggled/missaligned pins. Roberto fixed. (same AUX card we changed the handles, it is much better handlable now) 
</pre>
<!-- Author: spiropulu -->
<!-- Comment: Fri Jun  7 16;46;05 comment by...spiropulu -->
<pre>Slot 4  when we changed the handles one channel was disconnected
then we apparently connected it to the wrong channel 5 instead of 7 (these are the channels with the connectors "hidden" in the aux card.-- so 
21 0 had appeared in all events ha[0][21] = 0.  ha_et[0][21] = 1023.  eta = 21, phi = 0

run 145984</pre>
<!-- Date: Fri Jun 7 12:57:59 2002 -->
<pre>&lt;br&gt;&lt;b&gt;Checking admem trigger outputs&lt;/b&gt; 
&lt;br&gt; 
Checked b0pcal06 slot 20, all outputs.  I don't see anything wrong in output 5 as written in the email.  (this is eta22 phi2 
em bit 5, EPNE2 slot 20 ch 5 as in the writing in the email). 
I do, however, see something strange in the 6th output, but I'm 
not sure how real it is. Here is what I get (I expect the first 
number to be zero in the penultimate column): 
 
&lt;pre&gt; 
QIEs 18 18 131  
 Pedestals(before writing):   32000000  32107ffd  32347ffd  323c7fff  3207fdcf  32000000  fe7effff  
     2991              0       0    0    0    0    0    0    3 1023  
       80             64       0    0    0    0    0    0    0 1023  
      284            128       0    0    0    0    0    0    1 1023  
. 
. 
. and 
QIEs 18 19 131  
 Pedestals(before writing):   32000000  32307ffd  32347ffd  323d7fff  3207fdcf  32000000  fe7fffff  
     2987        0              0       0    0    0    0    0    0    2 1023  
       77      201             64       0    0    0    0    0    0    1 1023  
      280      421            128       0    0    0    0    0    0    2 1023  
      494      645            192       0    0    0    0    0    0    3 1023  
      704      875            256       0    0    0    0    0    0    4 1023  
&lt;/pre&gt; 
Here is what a normal channel looks like (3rd column from last): 
&lt;pre&gt; 
QIEs 17 17 131  
 Pedestals(before writing):   32000000  32307ffd  32347ffd  323c7fff  3207fdcf  32000000  fa7fffff  
        0              0       0    0    0    0    0    0    0 1023  
      170             64       0    0    0    0    0    1    0 1023  
      395            128       0    0    0    0    0    2    0 1023  
      615            192       0    0    0    0    0    3    0 1023  
&lt;/pre&gt; 
Sometimes you see leftover charge in the first event and this could be that.  We could try swapping boards but it doesn't match the symptoms you guys (maria, peter, et al) see and it might be a lot of work for nothing.   
 
 
</pre>
<!-- Author: Robin Erbacher, Mark, Zhibin -->


<!-- Date: Fri Jun 7 13:07:16 2002 -->
<pre>&lt;br&gt;&lt;b&gt;ADMEM tests on pcal06 different slot&lt;/b&gt; 
&lt;br&gt;We tested the trigger outputs for EPNE2 slot 14 all 
outputs.  This is eta22 phi23 em bit 7.  Unfortunately we 
don't see anything unusual at all.  The note says that  
"ch. 5" has bit 7 sometimes on, and that it isn't seen 
very often.  Unfortunately I can't saturate the ADC due 
to the sin theta weighting table: can't put enough current 
from the DAC in.  Output 5 particularly in the plug is 
hard because it only uses QIE 17 and there are no other channels in the sum.  So I'm not sure what we should do: we could again 
try swapping admems, or try loading an Et table of 1's so 
I can saturate the ADC in that trigger output.  But in any 
case, the zeroes are all there and there are no bits stuck 
on.  I'm assuming that the problem is that we are missing 
a bit rather than a bit is stuck.  This would be hard for me 
to ever see in these TSCR tests.   
&lt;p&gt; 
Anyway, here is an output for channel (output) 5: 
&lt;pre&gt; 
QIEs 17 17 131  
 Pedestals(before writing):   32000000  32107ffd  32107fff  32107fff  3206fdcf  32000000  ffffffff  
        0              0       0    0    0    0    0    0    0 1023  
       55             64       0    0    0    0    0    0    0 1023  
      270            128       0    0    0    0    0    1    0 1023  
      495            192       0    0    0    0    0    2    0 1023  
      719            256       0    0    0    0    0    3    0 1023  
      940            320       0    0    0    0    0    5    0 1023  
     1167            384       0    0    0    0    0    6    0 1023  
     1388            448       0    0    0    0    0    7    0 1023  
     1611            512       0    0    0    0    0    8    0 1023  
     1838            576       0    0    0    0    0    9    0 1023  
     2063            640       0    0    0    0    0   10    0 1023  
     2284            704       0    0    0    0    0   11    0 1023  
     2509            768       0    0    0    0    0   13    0 1023  
     2736            832       0    0    0    0    0   14    0 1023  
     2957            896       0    0    0    0    0   15    0 1023  
     3179            960       0    0    0    0    0   16    0 1023  
     3405           1024       0    0    0    0    0   17    0 1023  
     3627           1088       0    0    0    0    0   18    0 1023  
     3853           1152       0    0    0    0    0   19    0 1023  
     4084           1216       0    0    0    0    0   21    0 1023  
     4306           1280       0    0    0    0    0   22    0 1023  
     4523           1344       0    0    0    0    0   23    0 1023  
     4749           1408       0    0    0    0    0   24    0 1023  
     4976           1472       0    0    0    0    0   25    0 1023  
     5193           1536       0    0    0    0    0   26    0 1023  
     5424           1600       0    0    0    0    0   27    0 1023  
     5646           1664       0    0    0    0    0   29    0 1023  
     5872           1728       0    0    0    0    0   30    0 1023  
     6094           1792       0    0    0    0    0   31    0 1023  
     6311           1856       0    0    0    0    0   32    0 1023  
     6542           1920       0    0    0    0    0   33    0 1023  
     6780           1984       0    0    0    0    0   34    0 1023  
     6997           2048       0    0    0    0    0   35    0 1023  
     7206           2112       0    0    0    0    0   37    0 1023  
     7433           2176       0    0    0    0    0   38    0 1023  
     7659           2240       0    0    0    0    0   39    0 1023  
     7877           2304       0    0    0    0    0   40    0 1023  
     8094           2368       0    0    0    0    0   41    0 1023  
     8329           2432       0    0    0    0    0   42    0 1023  
     8555           2496       0    0    0    0    0   43    0 1023  
     8782           2560       0    0    0    0    0   45    0 1023  
     8991           2624       0    0    0    0    0   46    0 1023  
     9234           2688       0    0    0    0    0   47    0 1023  
     9452           2752       0    0    0    0    0   48    0 1023  
     9678           2816       0    0    0    0    0   49    0 1023  
     9905           2880       0    0    0    0    0   50    0 1023  
    10122           2944       0    0    0    0    0   51    0 1023  
    10357           3008       0    0    0    0    0   53    0 1023  
    10575           3072       0    0    0    0    0   54    0 1023  
    10801           3136       0    0    0    0    0   55    0 1023  
    11027           3200       0    0    0    0    0   56    0 1023  
    11245           3264       0    0    0    0    0   57    0 1023  
    11471           3328       0    0    0    0    0   58    0 1023  
    11689           3392       0    0    0    0    0   59    0 1023  
    11924           3456       0    0    0    0    0   61    0 1023  
    12142           3520       0    0    0    0    0   62    0 1023  
    12359           3584       0    0    0    0    0   63    0 1023  
    12594           3648       0    0    0    0    0   64    0 1023  
    12812           3712       0    0    0    0    0   65    0 1023  
    13029           3776       0    0    0    0    0   66    0 1023  
    13238           3840       0    0    0    0    0   67    0 1023  
    13473           3904       0    0    0    0    0   69    0 1023  
    13708           3968       0    0    0    0    0   70    0 1023  
    13943           4032       0    0    0    0    0   71    0 1023  
    14161           4096       0    0    0    0    0   72    0 1023  
    14424           4160       0    0    0    0    0   73    0 1023  
    14617           4224       0    0    0    0    0   74    0 1023  
    14845           4288       0    0    0    0    0   75    0 1023  
    15074           4352       0    0    0    0    0   77    0 1023  
    15249           4416       0    0    0    0    0   78    0 1023  
    15513           4480       0    0    0    0    0   79    0 1023  
    15723           4544       0    0    0    0    0   80    0 1023  
    15934           4608       0    0    0    0    0   81    0 1023  
    16180           4672       0    0    0    0    0   82    0 1023  
    16408           4736       0    0    0    0    0   83    0 1023  
    16619           4800       0    0    0    0    0   85    0 1023  
    16830           4864       0    0    0    0    0   86    0 1023  
    17076           4928       0    0    0    0    0   87    0 1023  
    17286           4992       0    0    0    0    0   88    0 1023  
    17497           5056       0    0    0    0    0   89    0 1023  
    17725           5120       0    0    0    0    0   90    0 1023  
    17971           5184       0    0    0    0    0   91    0 1023  
    18182           5248       0    0    0    0    0   93    0 1023  
    18428           5312       0    0    0    0    0   94    0 1023  
    18674           5376       0    0    0    0    0   95    0 1023  
    18867           5440       0    0    0    0    0   96    0 1023  
    19095           5504       0    0    0    0    0   97    0 1023  
    19306           5568       0    0    0    0    0   98    0 1023  
    19517           5632       0    0    0    0    0   99    0 1023  
    19763           5696       0    0    0    0    0  101    0 1023  
    19973           5760       0    0    0    0    0  102    0 1023  
    20202           5824       0    0    0    0    0  103    0 1023  
    20412           5888       0    0    0    0    0  104    0 1023  
    20641           5952       0    0    0    0    0  105    0 1023  
    20869           6016       0    0    0    0    0  106    0 1023  
    21097           6080       0    0    0    0    0  107    0 1023  
    21343           6144       0    0    0    0    0  109    0 1023  
    21536           6208       0    0    0    0    0  110    0 1023  
    21764           6272       0    0    0    0    0  111    0 1023  
    22010           6336       0    0    0    0    0  112    0 1023  
    22239           6400       0    0    0    0    0  113    0 1023  
    22449           6464       0    0    0    0    0  114    0 1023  
    22660           6528       0    0    0    0    0  115    0 1023  
    22888           6592       0    0    0    0    0  117    0 1023  
    23117           6656       0    0    0    0    0  118    0 1023  
    23363           6720       0    0    0    0    0  119    0 1023  
    23591           6784       0    0    0    0    0  120    0 1023  
    23784           6848       0    0    0    0    0  121    0 1023  
    24012           6912       0    0    0    0    0  122    0 1023  
    24241           6976       0    0    0    0    0  124    0 1023  
    24451           7040       0    0    0    0    0  125    0 1023  
    24697           7104       0    0    0    0    0  126    0 1023  
    24908           7168       0    0    0    0    0  127    0 1023  
    25136           7232       0    0    0    0    0  128    0 1023  
    25364           7296       0    0    0    0    0  129    0 1023  
    25575           7360       0    0    0    0    0  130    0 1023  
    25821           7424       0    0    0    0    0  132    0 1023  
    26032           7488       0    0    0    0    0  133    0 1023  
    26243           7552       0    0    0    0    0  134    0 1023  
    26488           7616       0    0    0    0    0  135    0 1023  
    26717           7680       0    0    0    0    0  136    0 1023  
    26927           7744       0    0    0    0    0  137    0 1023  
    27156           7808       0    0    0    0    0  138    0 1023  
    27384           7872       0    0    0    0    0  140    0 1023  
    27595           7936       0    0    0    0    0  141    0 1023  
    27823           8000       0    0    0    0    0  142    0 1023  
    28051           8064       0    0    0    0    0  143    0 1023  
    28280           8128       0    0    0    0    0  144    0 1023  
    28490           8191       0    0    0    0    0  145    0 1023  
    28508           8191       0    0    0    0    0  145    0 1023  
    28508           8191       0    0    0    0    0  145    0 1023  
&lt;/pre&gt;</pre>
<!-- Author: R. Erbacher, Mark Mattson, Zhibin Huang -->


<!-- Date: Fri Jun 7 15:56:14 2002 -->
<br><b>b0wcal07 ADMEM trigger check</b> 
<br>We checked the ADMEM trigger outputs in slot 17 of 
wcal07, corresponding to CONEB3 eta 16 phi 19.  The notes 
say that bit 0 goes on and off sporadically.  In my tests 
I didn't see this in Channel 2 (or any channel) but it would 
be tough to see maybe.  Here is what the output of channel 
2 looks like when summing QIEs 8-11: 
<pre> 
QIEs 8 11 131  
 Pedestals(before writing):   32000000  323cffff  32fcffff  3234ffff  327effff  32000000  ffffffff  
        0        0        0        0              0       0    0    0 1023 1023 1023 1023 1023  
      180      185      182      172             64       0    0    4 1023 1023 1023 1023 1023  
      403      407      407      396            128       0    0   10 1023 1023 1023 1023 1023  
      628      630      630      618            192       0    0   16 1023 1023 1023 1023 1023  
      855      874      848      839            256       0    0   22 1023 1023 1023 1023 1023  
     1073     1083     1081     1070            320       0    0   28 1023 1023 1023 1023 1023  
     1312     1306     1304     1297            384       0    0   34 1023 1023 1023 1023 1023  
 </pre> 
I don't know what other tests we can do except to try swapping 
the board to see if the problem disappears, but we wouldn't know until beam.  This isn't a great scenario.
<!-- Author: R. Erbacher, M. Mattson, Z. Huang -->



<!-- Date: Fri Jun 7 17:25:17 2002 -->
<pre>DIRAC P113 swapped with P079; crate_00 slot 4 (where a bunch of problems show) Did not enter in the MISCOMP 
database until we check- bunch of problems with runs 145885 
through 145990.   
</pre>
<!-- Author: spiropulu -->


<!-- Date: Fri Jun 7 18:24:33 2002 -->
<pre>Dirac 113 swapped with 079- bC error is gone 
swap entered in the miscomp DB</pre>
<!-- Author: spiropulu -->


<!-- Date: Fri Jun 14 19:17:21 2002 -->
<pre>June 12-13 Arnd/Monica cabletest work 
______________________________________ 
 The data file is in 
fcdfsgi2:/cdf/data08/look/icalir/ir023c13.0001cali   (look area)  or 
fcdfsgi2:/cdf/scratch/meyera/ir023c13.0001cali 
 
Some notes: 
 
- The diagnostic FIFO is loaded with 
   0x0000 
   0x0002 
   0x0004 
   0x0008 
   0x0010 
   ... 
   0x1000 
   with 1000 events for each setting. 
 
- "1000 events" may not be 100% accurate, e.g..if buffers are already filled 
   there may be ~4 events with the previous FIFO setting. One could add a 
   marker bank when the settings change, but maybe that's not necessary. 
 
- I found that the diagnostic FIFO cannot easily be reloaded in the middle of 
   the run. My (ugly) workaround was to force a Halt-Recover-Run sequence after 
   each reloading, this appears to make it work. 
 
- As a consequence of the last point, the run has only ~12960 instead of 13000 
   events, due to all the HRR's. 
 
- I used the software EVB, so it was REALLY slow (&gt;30min). With the hardware 
EVB, 
   the run should be at least an order of magnitude faster. 
 
Arnd 
*************************************************************** 
 I have been looking at that file and I am already finding some  
Calorimeter regions taht are consistently not working correctly. 
 
In most cases they have a modularity of 6 consecutive eta tower, which 
points the finger to a malfunctioning whole DIRAC board. 
Two such examples are: 
(*) phi=7, eta=0 thru 6   reads 0x3ff in place of 0x0 
                           or   0x2aa in place of 0x2 
(**) phi=21, eta=18 thru 23   reads always 0xb(eta=18,19,20) or 
                                           0x2(eta=20,21,22) 
                                  
 
Another big problem are in the region covered by the WCAL Admems 
in the West side. While for the East WCAL I see the expected value for HAD 
energies in eta=15 (twice the CHAS tower valuea because of overlap) and  
and eta=16 and 17(same as CHAD towers), the corresponding WCAL West tower 
see only the expected CHAD value for eta=5 (overlap) and constantly  
zero for eta=6 and eta=7. 
 
 
I am also observing some low level single bits erros but I though ADMEM 
and DIRAC experts might ant to get notified about these coarser probems 
first. 
 
Monica 
**************************************************************** 
</pre>
<!-- Author: spiropulu -->


<!-- Date: Fri Jun 14 19:38:59 2002 -->
<pre>June 14 Arnd/Maria cabletest runs 
 
  
Make a set of new cabletest runs after swapping two Diracs one of which was diagnosed sick by Monica; LEVE1_CAL_01 swapped with DIRAC slot 21 (problematic) with slot 20. After some tries we  
got a run (by using the hardware event builder and no L3 filters 
(NULL table) the test is performaed in less than 10 minutes. 
The HRR is as programmed every 1000 events by Arnd in lack of another way to reset the diagnostic FIFO : this must change as possible.   
 
The runs are 146550 (we had to stop it near the end) and 52 
(also here listed the one that Monica looked at)  
-rw-r--r--    1 smaria   cdf       517877347 Jun 14 18:41 ir023c78.0001cali 
-rw-r--r--    1 smaria   cdf       644205119 Jun 14 18:26 ir023c13.0001cali 
-rw-r--r--    1 smaria   cdf       618212431 Jun 14 18:23 ir023c76.0001cali 
 
Will look at these as possible-- Carla explained on the phone  
how to run her program so we compare with Monica. 
 
Enter the swapped DIRAC boards (serial 16 with 96 on slots 21 with 20 respectively) on MISCOMP database 
 
 
 
 
</pre>
<!-- Author: spiropulu -->


<!-- Date: Fri Jun 14 19:42:53 2002 -->
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<!-- Author: spiropulu -->
<!-- Comment: Fri Jun 14 19;43;36 comment by...spiropulu -->
<pre>event displays of the pulsing patterns for the cabletest</pre>


<!-- Date: Thu Jun 27 16:57:46 2002 -->
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<!-- Author: spiropulu -->
<!-- Comment: Thu Jun 27 16;58;30 comment by...spiropulu -->
<pre>cabletest </pre>


<!-- Date: Fri Jun 28 14:37:47 2002 -->
<pre>Cabletest: 
	Arnd found why the west wall crates were not downloaded correctly by the cableteste code:  
  ...in the west endwall crates the TOF ADMEMs are readout 
	and configured before the calorimeter ADMEMs, and the  
	cabletest code would just pick whichever comes first... 
 
A test run with wall only confirmed this hypothesis</pre>
<!-- Author: carla -->