<!-- Title: 15:09:42  Tue Apr 20 1999 -->
<!-- Crewchief: Fred Lewis -->
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Add J3 blackplane


<!-- Date: Tue Apr 20 15:22:18 1999 -->
New J3 backplane was added to upper TDC crate.  The new backplane has J3 connectors in slots 4-12!  I have moved some of the modules in this crate so that slots 4-12 are open.  This is the new configuration: 
 
Slot		Module		Comment 
2		dummy		bad slot do not use 
3		2301 
4		tracer		No J3 connector 
16		vbt-321b 
19		TDC		transition card in back 
21		testclk		 
 
Power has been restorted to both upper and lower crates  
<!-- Author: Fred Lewis -->


<!-- Date: Tue Apr 20 15:28:43 1999 -->
<pre>Plain text format for previous entry 
 
 
slot		module		comment 
 
2		dummy		bad slot, do not use 
3		2301		 
4		tracer		no J3 connector 
16		vbt-321b	 
19		TDC		transition card in back 
21		testclk		</pre>
<!-- Author: Fred Lewis -->


<!-- Date: Thu Apr 22 11:37:38 1999 -->
TDC Rev C Firmware Update 
 
Ron Moore and I have updated several of the Rev C TDC boards  
in the full crate test with the following features: 
 
1) The TDCs now have a faster version of the L2 hit processing code. Timing measurements can now be done on these modules. 
 
2) The Halt-Recover-Run code has been activated, but the instructions executed by the TDC DSP processor may not be  
exactly what we want. (e.g., I think the boards don't answer 
with DONE until the RUN is received.) This can now be tested at B0. 
 
3) We have activated a new feature: By writing a '1' to bit 23 of the Control Register, the DSP should now put 97 words in the FIFO: One header word hit words. This is just a simple way to put data in the FIFO without actually sending pulses to the chips. 
 
The Boards which received this update are serial numbers: 
28 26 18 22 14 17 32 19 12 
 
They are all labeled (on the back) in black felt-tip marker: 
"22 April 99 Firmware Update - mlk" 
 
We have left two boards (serial numbers 21 and 30) in the trigger room with the old firmware, just in case the new boards are too confusing. 
 
Board 33 is going back to Michigan for a VME-buffer repair; It will return next week. 
 
Any other boards (such as those in the COT prototype teststand) have not yet been updated)
<!-- Author: Mike Kelly -->


<!-- Date: Thu Apr 22 11:38:20 1999 -->
<pre>TDC Rev C Firmware Update 
 
Ron Moore and I have updated several of the Rev C TDC boards  
in the full crate test with the following features: 
 
1) The TDCs now have a faster version of the L2 hit processing code. Timing measurements can now be done on these modules. 
 
2) The Halt-Recover-Run code has been activated, but the instructions executed by the TDC DSP processor may not be  
exactly what we want. (e.g., I think the boards don't answer 
with DONE until the RUN is received.) This can now be tested at B0. 
 
3) We have activated a new feature: By writing a '1' to bit 23 of the Control Register, the DSP should now put 97 words in the FIFO: One header word hit words. This is just a simple way to put data in the FIFO without actually sending pulses to the chips. 
 
The Boards which received this update are serial numbers: 
28 26 18 22 14 17 32 19 12 
 
They are all labeled (on the back) in black felt-tip marker: 
"22 April 99 Firmware Update - mlk" 
 
We have left two boards (serial numbers 21 and 30) in the trigger room with the old firmware, just in case the new boards are too confusing. 
 
Board 33 is going back to Michigan for a VME-buffer repair; It will return next week. 
 
Any other boards (such as those in the COT prototype teststand) have not yet been updated)</pre>
<!-- Author: Mike Kelly -->


<!-- Date: Thu Apr 22 11:41:05 1999 -->
<pre>Further remarks on our Firmware update experience: 
 
Powering the e-net connector properly on the lower crate of the test rack enables us to connect to the MVME 167! 
 
 
One of the TDC boards had bent leads on the P2 connector!! Be careful when handling these boards! 
 
I have added L1A terminating resistors to board 28. 
</pre>
<!-- Author: Mike Kelly -->


<!-- Date: Thu Apr 22 19:42:33 1999 -->
Reconfigured lower TDC crate. Testclock in lower crate is now 
driving TSIE and clock signals to TRACER in lower crate.
<!-- Author: Bill Orejudos -->


<!-- Date: Thu Apr 29 16:28:45 1999 -->
<pre>Remark on the Firmware update! 
 
A bug in the DSP code prevents the different Scan Lists from doing anything. The Interrupts should work as described, however. 
 
We will correct this oversight in the near future.</pre>
<!-- Author: Mike Kelly -->


<!-- Date: Fri May 14 16:06:35 1999 -->
<pre>A new DSP software version was programmed into TDCs #12, 14, 19, 
28 and 32.  This version contains a fix for a scanlist-related 
bug.  Now, scanlist 0 will add the calibration constants to the 
pulse start times, while scanlist 1 will *not* add the 
calibration  constants.  The calibration constants for the above 
TDCs will make the reported start times of calibration test 
pulses more or less identical for all channels. 
 
TDC boards #17 and #22 were not functioning and were returned 
to Michigan for repair. 
 
 
 </pre>
<!-- Author: Ron Moore -->


<!-- Date: Mon May 17 08:17:34 1999 -->
<pre>If you think you have a broken TDC Module, see the following web page: 
 
http://umaxp1.physics.lsa.umich.edu/~kelly/broken.htm 
 
My TDC Web page is at: 
 
http://umaxp1.physics.lsa.umich.edu/~kelly/tdcinfo.htm</pre>
<!-- Author: Michael Kelly -->


<!-- Date: Fri May 28 12:17:42 1999 -->
<pre>Jay Dittmann and I worked with two TDCs as part of the XFT 
integration studies.  Here are some questions that came up, and 
the answers that Mike Kelly sent us. 
 
	We had a pretty successful day of XFT testing today -- by the end of 
it, we had two XTCs talking to a single Finder, each XTC sending up randomized 
data that was verified at the Finder end.  So we're pretty happy about that. 
Here are a few things that came up. 
 
	1)  One of the Rev C TDCs that they have seems to have trouble with 
the mezzanine interface -- all of the XTC registers cannot set the highest 
bit (i.e. write FF, read 7F).  I remember that I had this problem on a board 
that you lent me once, and you were able to fix it almost instantly -- there 
was a solder bridge somewhere, or something.  Could you recommend a spot for 
me to look for trouble?  Or would you like me to bring the board to Michigan? 
 
Look for shorts on components Q19 and P19 
 
My best guess: the Short is on Q19-33, Q19-24, P19-44 or P19-13 
 
 
	2)  We had a mix of Rev B and Rev C boards on hand, and the control 
registers need to be handled differently.  The thinking was that we could 
check the TDC serial number to decide how to initialize the board.  What is 
the serial number breakpoint between B and C? 
 
 
Rev B boards are serial numbers 1-10 
 
Rev C boards are serial numbers 11 - 24 
 
	3)  Speaking of the serial numbers, it looks like the TDC has a 
different convention for writing the serial number in the ID PROM than the 
boards made at FNAL do.  The TDC has the actual number written as a number in 
the registers.  The FNAL boards (e.g. Testclk, Tracer) have the serial number 
written as ASCII characters that translate to the number. 
 
I don't understand, doesn't the number make more sense? 
(Note added in proof -- the TDC had moved away from the spec on 
this.  It will be corrected soon.) 
 
	4)  We tried to set the calibration cell registers via block transfers 
to the TDC.  This didn't seem to work -- what we read back was not what we 
tried to write in.  We switched to single word transfers, and everything was 
fine.  I remember that there was some trouble that Frank Chlebana had seen 
with this a long time ago...but I don't remember how it got resolved.  What 
happened? 
 
 
What you are doing is in violation of the spec! The Spec was changed so 
that the only block reads that the TDC will do is from the FIFO. Stick 
with single-word transfers. 
 
</pre>
<!-- Author: Ken Bloom -->


<!-- Date: Thu Jun 10 21:06:45 1999 -->
<pre>TDCs #14, 18, 28, and 32 now have DSP code V22 in flashram.  This 
fixes bugs in the HALT/RECOVER/RUN interrupt service routine and in the formation of the event header word put into the VME FIFO. 
 
 
TDC #19 has a possible problem with its flashram, and I could not 
erase and reprogram it, although the old DSP program still seems 
intact. 
 
</pre>
<!-- Author: Ron Moore -->


<!-- Date: Thu Jun 10 21:08:19 1999 -->
<pre>The TDCs with DSP code V22 should also contain a ID PROM which 
conforms to CDF-2388. 
</pre>
<!-- Author: Ron Moore -->


<!-- Date: Tue Dec 7 16:51:56 1999 -->
<pre>Log entry for TDC checkout performed Nov. 26 - Nov 30. Total 
of 13 TDC's inspected with the commisioning software during 
this time. 
 
 tdc 561586: Failed SRAM read/write test. At first one could  
              still talk with TDC despite this fact. After 
              several trials, though, it became impossible to 
              talk with TDC. This is the current state of the 
              TDC. 
 
 tdc 561587: Two channels on board show problems: channel 73 
              does not output any data at all, and channel 45 
              shows the "split pulse problem". Symptoms of this 
              problem: the boards outputs two hits for some 
              of the events. The second hit begins 1 ns after 
              the first one ends. The sum of the two pulse  
              widths is consistent with the expected output 
              pulse width. It seems that some glitch is causing 
              a single bit to be held low. This problem occurred 
              on channel 45 for 6% of the events.  
 
 tdc 561588: Get many unpaired edges on channels 0 and 1 (and  
             maybe on channel 2 as well; this bears further 
             investigating). 
 
 tdc 561589: Split pulse problem on channel 61 for 1% of the  
             events. 
 
 tdc 561590: No output on channel 47. Also see an unpaired 
             edge and a second hit of correct pulse width 
             for a single event on channel 1. The start times 
             for these pulses do not seem to be correlated with 
             each other.  
 
 tdc 561591: Board passes all tests. 
 
 tdc 561592: Split pulse problem on channel 24 for 80% of the 
             events.  
 
 tdc 561593: Split pulse problem on channel 15 for <0.5% of the 
             events. 
 
 tdc 561594: Board passes all tests. 
 
 tdc 561596: Tail in the distribution of Start_ch45 - Start_ref 
             (where Start_ref is just the start time of channel 
             0). Tail extends out to about -25 ns. Note that the 
             correct distribution is a gaussian-like shape 
             with a rms < 1 ns.  
 
 tdc 561597: Problem in Start_ch50 - Start_ref distribution. 
             We get 2 populations: 80% at -244 ns and 20% 
             at 1804 ns. This problem may be due to a problem 
             with the calibration cell on the TDC - switching 
             to a different pulse caused this problem to go  
             away. Oddly enough, when I run this test with 
             front panel input (via ASDQ pulsing) I see two 
             populations: 80% at the correct value and 20% 
             off by about 240 ns. 
 
 tdc 561605: Board passes all tests. 
 
 tdc 561607: Problem in the Start_ch69-start_ref distribution. 
             There are three populations in this distribution. 
             Each population has rms <1 ns. 
             The means of the populations are seperated from  
             each other by about four ns. Also, the output 
             width of channel 69 has three populations. Each 
             population has the "correct" rms (again, <1 ns), 
             and the means of the populations are seperated by 
             about 4 ns.  
 
  Grand Total : 13 TDC's inspected 
 
                 3 pass all tests 
 
                 1 bad board 
 
                 10 boards with various problems on 1 or 2 (or at 
                 most 3) channels.        
                        
                    </pre>
<!-- Author: Bill Orejudos -->


<!-- Date: Sun Jan 2 23:41:04 2000 -->
<pre>Total of 6 LVDS boards tested over the holiday: 
 
  tdc 212 (prep ID 561603): Passed all tests 
 
  tdc 187 (prep ID 561598): Passed all tests 
 
  tdc 203 (prep ID 561601): Passed all tests 
 
  tdc 188 (prep ID 561599): Passed all tests 
 
  tdc 168 (prep ID 561602): Channels 0 and sometimes 1 have 
                            multiple hits at a very low level 
                            (less than 1% of events). Hits 
                            have the nominally correct width 
                            and are about 1000 ns apart. 
 
  tdc 166 (prep ID 561600)  Dead TDC? TDC did not come up  
                            in correct state (as indicated  
                            by front panel lights)  
                            on power up, when  TDC was reset, 
                            or when CPU was reset.</pre>
<!-- Author: Bill Orejudos -->


<!-- Date: Mon Jan 3 16:39:42 2000 -->
<pre>The entry from Dec. 7 only gives the Prep ID numbers. Here  
are the corresponding Michigan ID numbers: 
 
    561586 --> 193 
     
    561587 --> 169 
 
    561588 --> 155 
 
    561589 --> 209 
    
    561590 --> 189 
 
    561591 --> 151 
 
    561592 --> 178 
     
    561593 --> 181 
 
    561594 --> 186 
 
    561596 --> 190 
 
    561597 --> 167 
 
    561605 --> 201 
 
    561607 --> 185</pre>
<!-- Author: Bill Orejudos -->