<!-- Title: 09:07:11  Fri Mar 23 2001 -->
<!-- Crewchief: Jean Slaughter -->
<!-- Op1: Steve Nahn -->
<!-- Op2: &nbsp; -->
<!-- Op3: &nbsp; -->
<!-- Op4: &nbsp; -->
<!-- Op5: &nbsp; -->
<!-- Op6: &nbsp; -->
<!-- Notes: -->
<pre>Schedule for next few days 
-------------------------- 
  Friday 8:00-15:00  Wiring on cooling system 
                     SRC timing studies 
        15:00-18:00  ISL cooling studies - DAQ + cooling 
  Sat/Sun - exact schedule depends on Friday 
         1. Finish SRC work 
         2. Integration with 1 or 2 ladders 
         3. cycle through allowed ladders 1 by 1 to  
            characterize them and try to understand  
            CAEN GUI problems from the other day 
         </pre>


<!-- Date: Mon Mar 26 17:15:23 2001 -->
<pre>SB0W6 R0 layer 4 - grassy layer 2</pre>
<!-- Author: Slave of the Nile, Captain Jean -->


<!-- Date: Mon Mar 26 19:25:08 2001 -->
<pre>Wedge Tested		Problems		Solutions? 
------------		--------		---------- 
 
SB0W6			1) Layer 4 drops R0	DVDD already 
 						raised check DAQ. 
 
			2) Saw bit shifting	DAQ DAQ DAQ 
 
			3) Layer 2 grassy	A miracle 
 
SB1W6			**********NO PROBLEMS*************** 
 
SB2W6			1) L4 drops bit 1  	Change OFTM 
 
			2) Much rarer stuck 	Change FIB/VRB 
			bit5 on several  
			channels. 
 
SB2W7			1) L4 drops z-side RO	Raise DVDD 100mV 
 
			2) L4 draws almost  
			1 mA when fully biased	Pinhole or scale 
						on PS is set 
						sensitive? 
 
SB2W8			***********NO PROBLEMS**************** 
	</pre>
<!-- Author: Koshka&#39;s pet -->


<!-- Date: Mon Mar 26 19:27:36 2001 -->
<pre>!!!!!!!!!!!!!!ATTENTION ATTENTION ATTENTION!!!!!!!!!!!!!!!! 
 
$CAENCONTROL_DIR/CAENvolts.dat on online machines changed so that 
the right bias voltages are loaded for SB0W6, SB1W6,SB2W6,7,8 
when click on on! Be careful.</pre>
<!-- Author: Koshka&#39;s pet -->


<!-- Date: Mon Mar 26 19:35:39 2001 -->
<pre>I just love making new entries ..... 
 
DEACTIVATED SVX WEST BH INTERLOCKS AND SWITCHED 5V ENABLE OFF. 
 
</pre>
<!-- Author: The Pet -->


<!-- Date: Tue Mar 27 15:37:23 2001 -->
<pre>I deviously slipped the crate on the 2nd floor into the 
system.  It's FFO is connected to the SRC where normally 
the NEB crate would be, and its FIB is connected to the 
VRB for SVX B0W0 and SVX B0W1 (b0svx00,slot 8).  This needs 
to be put back to normal when we start to install North 
Side Wedges.</pre>
<!-- Author: SCN -->


<!-- Date: Wed Mar 28 20:02:41 2001 -->
<pre>Testing SE Wedges 
 
Wedge		Status		Comment 
-----		------		-------- 
SB3W5		OK 		Rails 
 
SB3W6		OK		Layer 2 drawing >100microamps 
 
SB4W5		OK		Grassy Layer 2. Layer 3 
				common mode noise. 
 
 
**SRC running with CDFCLK. Twice this evening, I get readout that 
is consistant with missing PARST (high noise - funny last pulse) 
switching to emulated clock and initing SRC doesn't seem to help 
but initing the whole system restores sanity to DAQ. 
 
***CAENCONTROL GUI changed to better represent orientation of  
wedges, as a result the mapping between GUI and actual wedges 
was off by -1 wedge. Fixed all SVX PSs in CAEN.map and added 
bias setting for the 3 connected SE wedges. NEED TO BE CAREFUL 
WHEN TESTING ISL AND L00 in case there is a shift there too. </pre>
<!-- Author: A descendant of Kenyanthropus Platyops -->


<!-- Date: Thu Mar 29 21:35:23 2001 -->
Todays Silicon Progress 
<ul> 
<LI><B><FONT COLOR=FF0000>SIXP BANKS </FONT></B><BR> 
After <ul> 
<li> Fixing the Software Event Builder code to take into account 
16 more words in an SCPU header (noone told me the EVB was gonna do that) 
<li> Forcing the SciCo Herr Paus to make his reformatter recognize Calibration banks (Handy that he was trapped here) 
<li> fixing up a few more bugs in the bank output 
</ul> 
we managed to put a SIXP bank on fcdfsgi2 in sixP.trybos in 
the silicon area (/data03/s1/hardware/svxii) 
<li> Lester and Steve Chappa arrived at the conclusion that 
the real problem with the SRC is that it cannot handle the 
small duty cycle (~ 5ns up) on the 53 Mhz signal, so Steve will 
lengthen the duty cycle and at the same time give us 
0.5 ns delay resolution 
</ul> 
<i> Queen of the Nile </i> is now taking over to check out 
the L00 ladders.<BR> 
<B><FONT COLOR=FF0000> Tomorrow is Integration Day</FONT></B> (after the access)
<!-- Author: SCN -->


<!-- Date: Thu Mar 29 21:55:49 2001 -->
<p> 
Read about a L00 flow trip <a href= 
'/cgi/elog/elog.pl?nb=2001&action=view&page=163&frame=2&anchor=21:53:02'> 
here.</a> 
<!-- Author: Andy H. -->


<!-- Date: Thu Mar 29 23:00:50 2001 -->
<pre>ANOTHER NASTY ENTRY - SRC COMES UP IN BOGUS STATE, HAVE TO  
SWITCH TO EMULATED CLOCK TO GET IT TO BEHAVE. THEN DURING 
TESTING DAQ SEEMS TO BE ACTING UP AGAIN. BAD 
CLOCKS OR BAD BEAM STRUCTURE - FISION ERRORS ON B0FIB05 -  
rebooted fib crate. 
 
Got this message during init system on b0fib05: 
 
0xc39758 (Messenger): memPartFree: invalid block 0x3 in partition 0x2e0ad4.</pre>
<!-- Author: Mad Mary -->


<!-- Date: Thu Mar 29 23:41:39 2001 -->
<pre>Tested the 2 L00 ladders despite all the silly glitches (flow too low, SRC no clock....) 
 
L00 B1W3 (east) Layer 2 the lowest 4 bits are stuck hi IF SWAPPING TO ANOTHER FIB CHANNEL DOESN'T HELP AND THERE  
IS TIME RECOMMEND MEASURING LIGHT OUTPUT.  
 
L00 B0W3 ( West) is fine. I assume layer 1 low or zero peds 
in NON-DPS mode is normal? 
 
</pre>
<!-- Author: Mad Mary -->


<!-- Date: Fri Mar 30 08:40:08 2001 -->
<pre>B2W6 doim HDI 1 in bad shape.  Plastic broken.</pre>
<!-- Author: herndon and nahn -->


<!-- Date: Fri Mar 30 09:04:41 2001 -->
<pre>In preparation for the impending 1x8 store, we'd like to run the following 
three ISL wedges;  B0W3, B1W3, B5W2. This will be done tomorrow (friday). 
I won't be here since I'm taking the kids out for the day. Could you 
please do this with Jean and Mary when they are ready? 
 
The other connected wedges (B2W1 and B3W1) are 6C and should not be 
powered due to cooling problems. These will hopefully be disabled, but 
beware anyway. 
 
One of the three, B1W3, has cooling problems on the odd numbered channels 
because they are 6INs. These channels should not be powered. Andrew 
and I just modified the Volts.dat file to disable them so they should 
already be unpowerable, but beware anyway. Despite the problems on the 6's 
of this wedge, we want to include it in the pool of runnable wedges 
because it is the only INNER barrel. Running the layer 7's in this wedge could 
provide some SVX+ISL+COT coverage and give us "outside-in" tracks in the 
1x8 while the other wedges really only give stand-alone silicon tracks. 
 
When you run these three wedges, please save the data and put it somewhere 
I can get to (such as ncdf17:/tmp/isl). 
 
Here are the proper bias voltages for the three wedges. 
 
B0W3: 
   Layer0 Bias0=40  Bias1=45 
   Layer1 Bias0=90  Bias1=110  (GUI may not allow over 100V) 
   Layer2 Bias0=45  Bias1=25 
   Layer3 Bias0=100 Bias1=90 
   Layer4 Bias0=48  Bias1=43 
 
B1W3: 
   Layer0 Bias0=50  Bias1=45 
   Layer1 Bias0=90  Bias1=80 
   Layer2 Bias0=35  Bias1=45 
   Layer3 Bias0=80  Bias1=90 
   Layer4 Bias0=45  Bias1=40 
 
B5W3: 
   Layer0 Bias0=32  Bias1=48 
   Layer1 Bias0=90  Bias1=100 
   Layer2 Bias0=38  Bias1=35 
   Layer3 Bias0=90  Bias1=90 
   Layer4 Bias0=35  Bias1=50 
 
One of the things which should be done as part of this testing tomorrow is 
set these values in the volts.dat file and make sure they are correctly 
handled by the GUI. 
 
If you want to see the results of the previous tests, etc. You can see the 
connection checklists in my Entry 10786. 
 
Previously known problems are that B0W3 layer 2 had readout problems and 
had to be dropped to get good data out of that wedge and layer 4 had some 
z side noise. 
 
Feel free to page me at 722-7565 if needed. 
 
 
------------> L00 
 
 
> Where do I get the bias voltages for the L00 E/W ? 
 
L00 B0W3 bias voltages are  L0=65V, L1=65V, L2=65V, L3=140V, L4=140V 
L00 B1W3 bias voltages are  L0=70V, L1=70V, L2=70V, L3=140V, L4=140V 
 
Note that even though there are only 4 hybrids per portcard you do need to 
turn layer 4 on and set its bias to the specified value. This is an 
artifact of the way the cabling was done to make L00 compatible with SVXII 
supplies--L3 uses the L4 bias for some of its silicon. The LV currents 
for layer 4 will be low if not 0. 
 
- David 
 
 
 
 
</pre>
<!-- Author: Jean for David -->


<!-- Date: Fri Mar 30 09:59:58 2001 -->
<pre>ISL B2W1 
ISL B3W1 enables disconnected at power supplies. 
Also entire ISL enable #2 pulled(central barrel).</pre>
<!-- Author: herndon and nahn -->


<!-- Date: Fri Mar 30 10:06:16 2001 -->
<B><FONT COLOR=FF00000 SIZE=10> Silicon Access Activites</FONT></B><BR> 
<ul> 
<li> Matt pulled Enables on ISL power supplies.  See his entry 
when he puts it in. 
<li> We replaced the FTM in B2W6 (b0fib02, Slot 18) b/c of a stuck bit on layer 4.  Layer 4 is now ok, but Layer 0 has 
lots of readout errors- Channels out of Sequence, Cap ID 
errors, etc: see ~svxii/daq/svx/sw/data/laser101.svx and ParsesErrors101.log.  Doesn't look like one single stuck bit. 
Could be (another!) bad FTM or reflections on the DOIM cable. 
Too bad I didn't have time to test it during the access. 
Net result: Gained 14 chips, lost 4. 
<li> Swapped Chan 6 and 7 for L00 B1W3 (b0fib05 slot 16). 
Initialization problem stayed with FTM, so we will swap that one 
too.  Swapped back and expected channels still work. 
<li> <B> News Flash</B>  More access granted.  Will work on 
these problems right now!  Stay tuned 
</ul>  
<!-- Author: SCN -->
<!-- Comment: Sat Mar 31 07;22;26 comment by...SCN -->
<a href=
'/cgi/elog/elog.pl?nb=2001&action=view&page=165&frame=2&anchor=10:59:10'>
Here's</a> what happened during Controlled Access Part II
<!-- Date: Fri Mar 30 20:13:42 2001 -->
<pre>Wedge		Status		Comment 
------		-------		--------- 
 
IB0W3		LAYER 2		OFTM PROBABLY DROPPING OBDV 
		init no		 !!!!!!REPLACE!!!!!!!!!!!!! 
		readout 
 
IB1W3		Can only 
		turn on  
		0,2,4 
		These channels 
		are fine. Raised 
		bias voltages on 
		2,4 from recommended 
		to fully bias ladders 
		New voltages default 
		in CAEN file. 
 
By the time we got to the east ISL wedge the CAEN controller 
was reporting RPC errors (co-incided with some network glitches) 
and the GUI wouldn't pop up. I CALLED IT A DAY. 
</pre>
<!-- Author: M. Bishai for T. Affolder -->


<!-- Date: Fri Mar 30 21:48:28 2001 -->
<table><tr><td><a href=/elog/notebooks/silicon/Fri_Mar_30_2001_214658.ps align=top><img src=/cgi/elog/det-system-elog.pl?nb=silicon&action=view&page=-8  align='top'></td><td>This is how DBANA TreeViewer sees pedestal1 (strip=1) in all chips of both wedges (run 103611). No corrections for precesion bit. Does this looks sensible?</a></td></tr></table>
<!-- Author: Vladimir -->