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[][]\OT1/ptm/m/n/9 This work was sup-ported by the Di-vi-sion of High En-ergy
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\OT1/ptm/m/n/9 Physics of the U.S. De-part-ment of En-ergy un-der Con-tract No.

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\OT1/ptm/m/n/10 sim-u-lated and im-ple-mented in Field Pro-grammable Gate
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\OT1/ptm/m/n/10 sys-tem re-quire-ments for these tasks are very de-mand-ing,
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\OT1/ptm/m/n/10 mak-ing the de-sign of a suit-able sys-tem non-triv-ial. The
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\OT1/ptm/m/n/10 en-vi-ron-ment of the high-luminosity PEP-II ma-chine poses
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\OT1/ptm/m/n/10 de-tec-tor per-for-mance. An-other chal-lenge for the trig-ger
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\OT1/ptm/m/n/10 elec-tron-ics which de-parts sig-nif-i-cantly from pre-vi-ous
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\OT1/ptm/m/n/10 ar-chi-tec-ture [[]], the elec-tron-ics sys-tems col-lect data 
from
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\OT1/ptm/m/n/10 was built with a split-level ar-chi-tec-ture: a fast hard-ware
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[]\OT1/ptm/m/n/10 The Level 1 trig-ger sys-tem must meet five pri-mary
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\OT1/ptm/m/n/10 of the front-end buffers; (4) ro-bust back-ground re-jec-tion
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\OT1/ptm/m/n/10 de-ter-mines whether the tracks rep-re-sent par-ti-cles hav-ing

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\OT1/ptm/m/n/10 Mod-ule (BLTM)[[]], where they are linked into com-plete
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\OT1/ptm/m/n/10 tracks. De-tailed az-imuthal po-si-tion in-for-ma-tion for the
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\OT1/ptm/m/n/10 Cham-ber are sent to 24 hardware-identical TSF mod-ules
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[]\OT1/ptm/m/n/10 Typically, valid seg-ment pat-terns con-sist of hits, close
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\OT1/ptm/m/n/10 time de-ter-mi-na-tion of the Global Trig-ger. The re-sult-ing
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[]\OT1/ptm/m/n/10 The PT-DMs re-ceive ac-cu-rate po-si-tion in-for-ma-tion on
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\OT1/ptm/m/n/10 The re-sult-ing [] turn-on at 600$[]$ is ex-pected to be
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[]\OT1/ptm/m/n/10 The pro-cess-ing on each board is sub-di-vided in eight
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\OT1/ptm/m/n/10 pro-cess-ing en-gines, one for each of the two su-per-lay-ers
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\OT1/ptm/m/n/10 com-po-nents in each chan-nel are an al-go-rith-mic pro-ces-sor

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[]\OT1/ptm/m/n/10 The de-sign of the trig-ger ar-chi-tec-ture and se-lec-tion
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\OT1/ptm/m/n/10 hardware-implementable trig-ger al-go-rithms. Ex-ten-sive
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\OT1/ptm/m/n/10 im-ple-men-ta-tion of the trig-ger al-go-rithms de-scribed abov
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\OT1/ptm/m/n/10 De-sign toolset that in-cluded the VHDL hard-ware de-sign
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\OT1/ptm/m/n/10 out-put data streams of each mod-ule, al-low-ing ar-bi-trar-ily

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\OT1/ptm/m/n/10 com-plex test vec-tors to be ex-er-cised for each board,
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\OT1/ptm/m/n/10 This de-sign fea-ture pro-vides pow-er-ful board-level as well
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\OT1/ptm/m/n/10 re-sults were suc-cess-fully com-pared against the soft-ware
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\OT1/ptm/m/n/10 al-low-ing them to serve as the pro-duc-tion ver-sion for the
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[4]
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[]\OT1/ptm/m/it/12 Impact of Cell In-ef-fi-cien-cies on Trig-ger
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[]\OT1/ptm/m/n/10 Beam re-lated back-grounds are eval-u-ated at the de-sign
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\OT1/ptm/m/n/10 Dif-fer-ent back-ground con-di-tions have been stud-ied, with
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\OT1/ptm/m/n/10 a ``worst-case sce-nario'' de-fined as ten times the nom-i-nal
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\OT1/ptm/m/n/10 con-di-tions. Un-der ``worst-case'' sce-nario back-ground
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[][]\OT1/ptm/m/n/10 The [] Col-lab-o-ra-tion, ``Tech-ni-cal De-sign Re-port'',
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[][]\OT1/ptm/m/n/10 C.T. Day \OT1/ptm/m/it/10 et al., \OT1/ptm/m/n/10 ``The Bab
ar Trig-ger, Read-out and
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\OT1/ptm/m/n/10 Dis-crim-i-na-tor for the [] Level 1 Trig-ger Sys-tem'',
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\OT1/ptm/m/n/10 Tech-nol-ogy), De-sign Ar-chi-tect, Li-brar-ian, Pack-age,
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