![](media/image1.png){width="3.0in" height="0.9791666666666666in"}

**Letter of Intent**

**for the Inclusive**

**Forward Silicon Vertex Detector (iFVTX)**

**14 November 2023**

![](media/image2.jpeg){width="4.4in" height="3.85in"}

**Letter of Intent of the iFVTX for the PHENIX Experiment**

M.L. Brooks, S. Butsyk, G. Grim, H.W. van Hecke, J. Kapustinsky, A.
Klein, G.J. Kunde, D.M. Lee, M.J. Leitch, M.X. Liu, P.L. McGaughey, W.E.
Sondheim

Los Alamos National Laboratory, Los Alamos, NM 87545, USA

Hisham Albataineh, G. Kyle, H. Liu, S. Pate, X.R. Wang

New Mexico State University, Las Cruces, NM, USA

B. Bassalleck, D.E. Fields, M. Hoeferkamp, M. Malik, J. Turner

University of New Mexico, Albuquerque, NM, USA

E.Mannel

Nevis Laboratories, Columbia University, NY, USA

[1 Executive Summary 7](#executive-summary)

[2 Physics Goals of the Inclusive Forward Vertex Detector
12](#physics-goals-of-the-inclusive-forward-vertex-detector)

[2.1 Heavy Flavor Production and the Quark Gluon Plasma
13](#heavy-flavor-production-and-the-quark-gluon-plasma)

[2.1.1 Energy Loss and Flow of Heavy Quarks
13](#energy-loss-and-flow-of-heavy-quarks)

[2.1.2 Charm and Bottom Measurements with the iFVTX
16](#charm-and-bottom-measurements-with-the-ifvtx)

[3 iFVTX Detector Performance 21](#ifvtx-detector-performance)

[3.1 Simulation Code 21](#simulation-code)

[3.2 Distance of Closest Approach Measurement
23](#distance-of-closest-approach-measurement)

[3.3 Heavy Quark Measurements with the iFVTX Using D, B X
25](#heavy-quark-measurements-with-the-ifvtx-using-d-b-x)

[3.4 Expected Count Rates 27](#expected-count-rates)

[3.5 Occupancy in Central AuAu Events
27](#occupancy-in-central-auau-events)

[3.6 Matching Tracks from the Muon Spectrometers to the iFVTX/FVT
29](#matching-tracks-from-the-muon-spectrometers-to-the-ifvtxfvt)

[3.7 Data Analysis for iFVTX/FVTX 30](#data-analysis-for-ifvtxfvtx)

[3.8 Luminosity Assumptions 32](#luminosity-assumptions)

[3.9 Physics Performance 33](#physics-performance)

[4 iFVTX Detector System 33](#ifvtx-detector-system)

[4.1 Overview 33](#overview)

[4.2 Detector Description 37](#detector-description)

[4.2.1 The Readout Chip FPX 2.1 37](#the-readout-chip-fpx-2.1)

[4.2.2 The Silicon Sensor 43](#the-silicon-sensor)

[4.2.3 The High Density Interconnect 45](#the-high-density-interconnect)

[4.2.4 The Module and Assembly 47](#the-module-and-assembly)

[4.2.5 Detector Plane 47](#detector-plane)

[4.2.6 The Cooling Concept and Design
49](#the-cooling-concept-and-design)

[4.2.7 Cable Assembly 50](#cable-assembly)

[4.2.8 Station Layout and Cage Mount 51](#station-layout-and-cage-mount)

[4.3 Readout Electronics Description
51](#readout-electronics-description)

[4.3.1 ROC Design Specifications 53](#roc-design-specifications)

[4.3.2 FEM Design Specifications 54](#fem-design-specifications)

[4.3.3 ROC and FEM Prototype Performance
55](#roc-and-fem-prototype-performance)

[4.4 Radiation Environment and Component Selection
59](#radiation-environment-and-component-selection)

[5 Mechanical Structure and Cooling
59](#mechanical-structure-and-cooling)

[5.1 Structural Support 59](#structural-support)

[5.2 iFVTX Stations 60](#ifvtx-stations)

[5.3 FEA Calculations for modules 61](#fea-calculations-for-modules)

[5.4 FEA Calculations of the support cage
64](#fea-calculations-of-the-support-cage)

[5.5 Analysis of the Full VTX/FVTX Structure
65](#analysis-of-the-full-vtxfvtx-structure)

[5.6 iFTVX Analysis Summary 67](#iftvx-analysis-summary)

[5.7 Assembly and Integration 67](#assembly-and-integration)

[5.7.1 Assembly 67](#assembly)

[*5.7.2* Integration 69](#integration)

[5.8 Q/A procedures 72](#qa-procedures)

[5.8.1 Silicon Sensor Q/A 72](#silicon-sensor-qa)

[5.8.2 FPIX Readout Chip Q/A 72](#fpix-readout-chip-qa)

[5.8.3 High Density Interconnect (HDI)
72](#high-density-interconnect-hdi)

[5.8.4 TPG Support/Heat Spreader 72](#tpg-supportheat-spreader)

[6 Infrastructure Requirements from PHENIX
73](#infrastructure-requirements-from-phenix)

[6.1.1 Detector layout in cage 73](#detector-layout-in-cage)

[6.1.2 Cable plant inside enclosure (size, location)
73](#cable-plant-inside-enclosure-size-location)

[6.1.3 Big wheel space, board configuration
74](#big-wheel-space-board-configuration)

[6.2 Cable Plant from IR, i.e. the Big Wheel to Racks
74](#cable-plant-from-ir-i.e.-the-big-wheel-to-racks)

[6.2.1 LV bundle size 74](#lv-bundle-size)

[6.2.2 HV bundle size 75](#hv-bundle-size)

[6.2.3 Fiber bundle size 75](#fiber-bundle-size)

[6.2.4 Cable tray needs 75](#cable-tray-needs)

[6.3 PHENIX Hall Rack Requirements 75](#phenix-hall-rack-requirements)

[6.3.1 LV crate specification 75](#lv-crate-specification)

[2 PHENIX LV crates will be required with 9 modules each for the planes.
These will deliver 3.2 V digital and 3.0 V analog for 68 channels. This
requirement is iFVTX specific.
75](#phenix-lv-crates-will-be-required-with-9-modules-each-for-the-planes.-these-will-deliver-3.2-v-digital-and-3.0-v-analog-for-68-channels.-this-requirement-is-ifvtx-specific.)

[6.3.2 HV crate specification 75](#hv-crate-specification)

[6.3.3 Fiber patch panel specification
75](#fiber-patch-panel-specification)

[6.3.4 Other? 76](#other)

[6.4 Cooling System Requirements 76](#cooling-system-requirements)

[6.4.1 Wattage that must be removed from within the enclosure, number
and size of cooling lines that must be provided to do this, specify
volume/rate of coolant.
76](#wattage-that-must-be-removed-from-within-the-enclosure-number-and-size-of-cooling-lines-that-must-be-provided-to-do-this-specify-volumerate-of-coolant.)

[6.5 PHENIX Counting House Rack Requirements
76](#phenix-counting-house-rack-requirements)

[6.5.1 FEM crate specification 76](#fem-crate-specification)

[6.5.2 Number of DCMs required 76](#number-of-dcms-required)

[6.5.3 Slow control interface requirements
76](#slow-control-interface-requirements)

[6.6 Technician Needs for Infrastructure and Installation
76](#technician-needs-for-infrastructure-and-installation)

[6.6.1 Cable tray installation 76](#cable-tray-installation)

[6.6.2 Fibers run from CH to IR 77](#fibers-run-from-ch-to-ir)

[6.6.3 Wiring up of rack (need to put in rack monitoring, power to each
crate...)
77](#wiring-up-of-rack-need-to-put-in-rack-monitoring-power-to-each-crate)

[6.6.4 Steve Boose for LV system (?) 77](#steve-boose-for-lv-system)

[6.6.5 Cooling system support (plumbing and integration to PHENIX
monitoring, etc.)
77](#cooling-system-support-plumbing-and-integration-to-phenix-monitoring-etc.)

[6.6.6 Monitoring help from Frank T/ John H
77](#monitoring-help-from-frank-t-john-h)

[6.7 Detector installation 77](#detector-installation)

[7 Schedule, Responsibilities 77](#schedule-responsibilities)

[7.1 Schedule 77](#schedule)

List of Figures

[Figure 1 Schematic of the distance of closest approach (DCA)
measurement for a secondary particle produced in front of the iFVTX
detector. 8](#__RefHeading___Toc196886572)

[Figure 2 Invariant cross section for heavy flavor muons (blue), hadron
decay muons (red) and hadron punch-throughs (pink) contributing to the
single particle spectra in the muon arms. Data are derived from real
data measurements at RHIC, using the PHENIX muon arms.
8](#__RefHeading___Toc196886573)

[Figure 3 Conceptual layout of the PHENIX iFVTX showing the four
stations (shown in green) of the iFVTX, see Figure 1 for the schematic
layout of the four stations. 10](#__RefHeading___Toc196886574)

[Figure 4 - Suppression of high-pT hadrons and pions as seen in Au+Au vs
d+Au collisions, measured by PHENIX and published in PRL.
14](#__RefHeading___Toc196886575)

[Figure 5 -- High-pT suppression of 0's and 's -- indicative of large
partonic energy loss in high density matter; compared to no suppression
of direct photons which indicates that the initial-state is not
modified. 14](#__RefHeading___Toc196886576)

[Figure 6 -- Heavy quark suppression and flow vs pT from PHENIX
measurements using electrons in 200 GeV Au+Au collisions at mid
rapidity. 15](#__RefHeading___Toc196886577)

[Figure 7 Heavy flavor cross section measurements, at forward rapidity
and versus pT, that can be made with (blue) and without (red) the iFVTX
detector. 17](#__RefHeading___Toc196886578)

[Figure 8 Decay length of muons from the semi-leptonic decay of D (red),
B (blue), K and  are shown on the left and the decay angle of the muon
with respect to the parent meson is shown on the right for the same
particle types. 18](#__RefHeading___Toc196886579)

[Figure 9 Muons from thrown charm events (black dots) and beauty (red
crosses) are shown on the left. The x axis is the pT of the
reconstructed muons and the y axis is the total number of counts. The
same simulated spectra are shown on the right, overlaid with the
reconstructed spectra (blue dots are reconstructed charm and blue
crosses are reconstructed beauty). 19](#__RefHeading___Toc196886580)

[Figure 10 Fractional error in extracted D component (black dots) and B
component (red crosses). 19](#__RefHeading___Toc196886581)

[Figure 11 Heavy flavor RCP measurement that can be achieved with 1.1
inverse picobarn AuAu collisions, with the iFVTX detector (blue error
bars) and without the iFVTX detector (red error bars). Theory
predictions which include radiative energy loss (green band), radiative
energy loss plus elastic scattering energy loss (blue band) and
radiative energy loss plus dissociation (yellow band) are shown for
comparison. 20](#__RefHeading___Toc196886582)

[Figure 12 Layout of stations in the Geant simulation on the left and
the close-up view to the right. 22](#__RefHeading___Toc196886583)

[Figure 13 - Principle of operation of the iFVTX detector in the r-z
plane. A D meson is produced at the collision point. It travels a
distance proportional to its lifetime (purple line), then decays to a
muon (green line). The muon's trajectory is recorded in the four
stations of the iFVTX. The reconstructed muon track (dashed line) has a
small, but finite distance of closest approach (dca) to the primary
collision vertex (black line). The primary background is muons from pion
and kaon decays, which have a much larger average DCA because of their
longer lifetime. 23](#__RefHeading___Toc196886584)

[Figure 14 DCA resolution along the small and long dimension of the
pixel as function of the muon momentum.
24](#__RefHeading___Toc196886585)

[Figure 15 Z-vertex resolution of \~180 micron with the iFVTX for 5
GeV/c muons in the North arm acceptance.
24](#__RefHeading___Toc196886586)

[Figure 16 - pT distribution of negative prompt muons (muons from heavy
quarks), decay muons from  and K and punch-through hadrons at pseudo
rapidity () = -1.65. The punch-throughs become the dominant background
for pT values above 3 GeV. The curves are simulations, based on real
data extrapolations, while the data are PHENIX measurement.
25](#__RefHeading___Toc196886587)

[Figure 17 -- Signal to background improvement for Ds (left) and Bs
(right) which decay to + for no vertex cut and successive iFVTX cuts.
Cuts applied are 2 cut, DCA cut in the phi direction, and DCA cut in
the r direction. 26](#__RefHeading___Toc196886588)

[Figure 18 - Signal to background improvement for Ds (left) and Bs
(right) which decay to - for no vertex cut and successive iFVTX cuts.
Cuts applied are 2 cut, DCA cut in the phi direction, and DCA cut in
the r direction. 26](#__RefHeading___Toc196886589)

[Figure 19 Count rates for open heavy flavor reconstruction assuming 1.1
pb-1 AuAu collisions. 27](#__RefHeading___Toc196886590)

[Figure 20 Hit display for a central Au Au collision on the first layer.
The maximum occupancy is smaller than 0.1 percent.
28](#__RefHeading___Toc196886591)

[Figure 21 Distribution of numbers of hit pixels in the module closest
to the beam for central AuAu collisions. An average of 23 pixels out of
2816 respond in this maximum occupancy example. For average numbers see
main text. 28](#__RefHeading___Toc196886592)

[Figure 22 Chi-square distribution for tracks which are correctly
matched and fitted between the muon and FVTX systems (red) and ones
which are incorrectly matched (black). 29](#__RefHeading___Toc196886593)

[Figure 23 Fraction of reconstructed muon tracks which are correctly
matched to an FVTX track versus momentum. Muons from heavy flavor decay
were embedded in minimum bias Au+Au events.
30](#__RefHeading___Toc196886594)

[Figure 24 Expected performance of the iFVTX for the RCP measurement.
33](#__RefHeading___Toc196886595)

[Figure 25 - 3-D model of the full vertex detector showing the barrel
portion and the iFVTX on the right. 34](#__RefHeading___Toc196886596)

[Figure 26 Side view of the iFVTX detector system, all measurements are
in mm. 35](#__RefHeading___Toc196886597)

[Figure 27 Block diagram of the readout system required for the iFVTX
(prototype and therefore very similar to the FVTX). The read out cards
and the front end module are boards which will reside between the FPIX
readout chip and the DCM and are currently under development.
36](#__RefHeading___Toc196886598)

[Figure 28: FPIX2.1 block diagram; arrows represent control and data
flow. 37](#__RefHeading___Toc196886599)

[Figure 29: Pixel unit cell, the analog section is to the left, the
digital section to the right. 39](#__RefHeading___Toc196886600)

[Figure 30: Data Output Interface block diagram.
40](#__RefHeading___Toc196886601)

[Figure 31 Picture of the FPIX 2.1 chip with an overlay of the areas of
power production. 42](#__RefHeading___Toc196886602)

[Figure 32 Pixel layout at the edge of the detector with 600µm instead
of 400µm length long pixels. 43](#__RefHeading___Toc196886603)

[Figure 33 Photograph of the CIS produced sensors after their arrival at
LANL. 44](#__RefHeading___Toc196886604)

[Figure 34 Close-up of the wafer, the eight chip sensors are the 6 long
structures in the center. The wafer holds in addition 2 four and 4 one
chip sensors plus several test structures.
45](#__RefHeading___Toc196886605)

[Figure 35 Cross section of the detector stack up, the flip chip
assembled readout is glued to the HDI which is glued on the TPG carrier.
While the sensor-readout chip connection is achieved via bump bonds, the
chip itself is connected to the HDI via wire bonds.
46](#__RefHeading___Toc196886606)

[Figure 36 CAD drawing of pixel plane with 10 modules. The three
mounting flexures and the two stiffer bars are visible.
47](#__RefHeading___Toc196886607)

[Figure 37 Picture of the prototype printed circuit board for a plane,
the dark area is the TPG insert for the cooling of the modules.
48](#__RefHeading___Toc196886608)

[Figure 38 Photograph of the prototype plane with various test modules.
The extra board mounted in the lower picture was a clock distribution
test board, for the production layout these chips are mounted directly
on the plane. 48](#__RefHeading___Toc196886609)

[Figure 39 CAD drawing of a station build by mounting two planes face to
face. The two planes are offset by the width of one module. The cooling
loop on the TPG is visible. The loop itself is made from PEEK tubing,
precision molded to have one flat surface which is glued to the TPG.
49](#__RefHeading___Toc196886610)

[Figure 40 Drawing of the offset of the two planes, the station is
optimized for an average crossing angle of 22 degrees, matching the muon
arms. 50](#__RefHeading___Toc196886611)

[Figure 41 CAD drawing of the four stations mounted in the cage
developed for the FVTX. The cooling lines, the cables and the strain
relieve is show. 51](#__RefHeading___Toc196886612)

[Figure 42 iFVTX Detector Readout Diagram
52](#__RefHeading___Toc196886613)

[Figure 43 ROC Block Diagram 53](#__RefHeading___Toc196886614)

[Figure 44 The FEM design 54](#__RefHeading___Toc196886615)

[Figure 45 Scope capture of data synchronization for the ROC prototype
55](#__RefHeading___Toc196886616)

[Figure 46 Combining data from 8 chips in ROC prototype
56](#__RefHeading___Toc196886617)

[Figure 47 FEM prototype testing results: Reading back from the correct
beam clock bucket (top) and from an incorrect bucket (bottom)
57](#__RefHeading___Toc196886618)

[Figure 48 Threshold scan for an 8-chiop FPIX module using the ROC
channel prototype. Threshold and noise distribution of each pixel (top)
and fit to the turn-on curve for on of the pixels (bottom) are shown.
58](#__RefHeading___Toc196886619)

[Figure 49 CAD drawing of a station, the cooling tube on the FPG is
clearly visible; the actual modules are on the inside of the station
because the two planes, composing the station, face each other.
60](#_Ref159134842)

[Figure 50 Module dimensions in the FEA analysis.
61](#__RefHeading___Toc196886621)

[Figure 51 Results of the thermal FEA. With a coolant temperature of 7 C
the gradient between TPG and Sensor is about 8.3 C.
62](#__RefHeading___Toc196886622)

[Figure 52 FEA stress plot for the bump bond layer at nominal operating
temperature. The maximum stress is \~ 2 % if the tensile yield.
62](#__RefHeading___Toc196886623)

[Figure 53 FEA stress results for the case of a LV power outage while
cooling is in operation. The maximum stress is \~ 19 % of the tensile
yield. 63](#__RefHeading___Toc196886624)

[Figure 54 FEA results for the deflection of module during normal
operation. The maximum displacement in the Z direction is only \~ 4
microns. 63](#__RefHeading___Toc196886625)

[Figure 55 iFVTX distortion analysis, details see main text.
64](#_Ref184526078)

[Figure 56 iFVTX modal analysis; the first modal frequency is at 156 Hz.
65](#__RefHeading___Toc196886627)

[Figure 57 FEA model of the combined VTX and FVTX. The first modal
frequency is 38.5 Hz 66](#__RefHeading___Toc196886628)

[Figure 58 Full system FEA; the first frequency mode is 24 Hz.
66](#__RefHeading___Toc196886629)

[Figure 59 CAD drawing of the mounting jig for the module assembly. The
HDI is held with a vacuum jig. 68](#__RefHeading___Toc196886630)

[Figure 60 Pixel plane with 10 modules on the mounting jig (in red)
69](#__RefHeading___Toc196886631)

[Figure 61 Grounding schematic for the iFVTX, all supplies are floating.
The sensor, digital and analog ground are only connected together at the
front end pixel planes. All power lines have PTC fuses.
71](#__RefHeading___Toc196886632)

[Figure 62 CAD drawing of the four stations mounted in the cage
developed for the FVTX. The cooling lines, the cables and the strain
relieve is show. 73](#__RefHeading___Toc196886633)

**List of Tables**

[Table 1 - Summary of the parameters of the iFVTX stations.
34](#__RefHeading___Toc196106504)

#   {#section .unnumbered}

# Executive Summary

The study of the properties of the Quark-Gluon Plasma (QGP) predicted by
the fundamental theory of strong interactions and created in collisions
of heavy nuclei is the main goal of the heavy ion program at RHICError:
Reference source not found. Heavy quarks are now becoming the most
important source of new insight largely because theory predictions are
considered safe because of the large quark masses involved. Current
results from single non-photonic electron suppression and flow suggest
that quenching and thermalization and flow of heavy quarks are very
large. This presents the biggest puzzle so far to heavy ion
theory^2,3,4^. The best possible measurements are now necessary to make
further progress and require a detector which can directly identify
heavy quarks. We propose to add a pixel based vertex tracker to upgrade
in front of one muon arm in PHENIX, called the inclusive Forward Vertex
Tracker (iFVTX).

A vast increase of theoretical activity in the past couple of years was
aimed at understanding the interaction mechanisms of heavy quarks with
the plasma. First advances have been made in understanding the
collisional component of heavy quarks to parton energy loss in addition
to the radiative one. Moreover, novel heavy flavor suppression
mechanisms based on heavy flavor dissociation in the QGP have been
proposed and shown to be very successful in describing the quenching of
the non-photonic electrons. In addition arguments have also been made
that insight gained from string theory might be useful in understanding
the properties of strongly coupled systems. It is widely recognized in
the theoretical and experimental communities that progress in this area
requires direct measurements of the charm and beauty meson quenching and
flow with good precision. With the baseline PHENIX detector, these
questions cannot be directly addressed because the heavy flavor
measurements have very large systematic errors due to large backgrounds
and there is no capability for separating charm and bottom. Therefore,
the various model predictions cannot be adequately tested. The iFVTX
detector will provide a first, inclusive, experimental capability to
answer some of the questions albeit with limited acceptance. The iFVTX
will cover one eighth of one muon arm, and is the precursor to a
complete coverage of the muon arms by the FVTX, approved for DOE funding

The iFVTX detector will allow for precision heavy flavor measurements by
adding the capability to identify muons which have a track that doesn't
originate from the primary vertex, i.e. a track originates from the
semi-leptonic decay of a heavy quark. The iFVTX provides precision
tracking of a track's distance of closest approach (DCA) to the primary
vertex. This DCA will typically be non-zero for secondary particles, as
illustrated in Figure 1, and we will use this to tag muons from B and D
decays. Prompt background will have DCA's near zero while long lived
backgrounds will have much larger DCA's.

![](media/image3.png){width="4.125694444444444in"
height="2.1944444444444446in"}

[]{#__RefHeading___Toc196886572 .anchor}Figure 1 Schematic of the
distance of closest approach (DCA) measurement for a secondary particle
produced in front of the iFVTX detector.

The single particle spectra that are accepted by the muon spectrometers,
measured using real data, are shown in Figure 2. Currently, the hadron
backgrounds dominate over the heavy flavor components, especially at low
transverse momentum. The hadron backgrounds are comprised of pions and
kaons that decay to muons before the absorber material, and those that
punch through the absorber material (and may or may not decay in the
muon tracker volume). The idea of the iFVTX is to positively identify
those tracks which come from heavy flavor decay.

![](media/image4.png){width="4.249305555555556in"
height="2.8979166666666667in"}

[]{#__RefHeading___Toc196886573 .anchor}Figure 2 Invariant cross section
for heavy flavor muons (blue), hadron decay muons (red) and hadron
punch-throughs (pink) contributing to the single particle spectra in the
muon arms. Data are derived from real data measurements at RHIC, using
the PHENIX muon arms.

Heavy-quark production in the forward and backward directions has been
measured in PHENIX indirectly via the observation of single muons in p+p
and d+Au collisions. The current measurements are limited in accuracy by
systematic uncertainties resulting from two large contributions to the
single muon spectra: prompt pion and kaon semi-leptonic decays and pion
and kaons which punch through the entire muon system and are mistakenly
tagged as muons The iFVTX detector will provide vertex tracking with a
distance of closest approach (DCA) resolution in r-z that is better than
100 m over a large coverage in rapidity (1.2 \< \|\| \< 2.2). This will
allow for vertex cuts which separate prompt particles from decay
particles and short-lived heavy quark mesons from long-lived light
mesons (pions and kaons). Therefore, with this device several
fundamentally new measurements can be made and current muon measurements
will be significantly enhanced.

-   Study of energy loss and flow of heavy quarks into forward and
    backward rapidity regions using robust charm and bottom measurements
    over a broader x range than available with the barrel VTX detector
    alone and with greater precision than is possible with the muon
    detectors alone. This allows the extension of studies of the
    geometrical and dynamical effects of the hot-dense matter created in
    high-energy heavy ion collisions into the forward and backward
    rapidity regions and will allow us, for the first time, to separate
    measurements for charm and bottom.

```{=html}
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```
-   Precise open charm and bottom measurements will provide a solid
    reference for comparison with production of bound states of heavy
    quarks (J/ψ and ). These will allow for the isolation of several
    physics aspects, e.g. initial-state effects such as gluon shadowing
    and physics that only affects the bound states, for example
    final-state absorption. The new measurements will also provide
    strong constraints on production of J/ψs from recombination by
    determining a precise open-charm cross section over a broad rapidity
    range.

The iFVTX will be composed of 4 stations with silicon pixel detectors,
covering rapidities (1.2 \< \|\| \< 2.2) that match a muon arm, and
provide precision tracking for one octant. The pixel size is 50 by 400
micron and therefore has the resolution for displaced track
measurements. The iFVTX consists of approximately 450,000 pixels per
station that are read out via FPIX2.1 readout chips designed by Fermilab
for the BTeV experiment. Eight of these chips are flip chip assembled to
one silicon pixel sensor. Each station is build from 2 identical planes
with 10 modules each (6 for the smaller first station) that are mounted
to achieve hermetic coverage for an average incident angle of 22
degrees. Figure 3 shows the layout of the iFVTX, where four stations are
mounted in the cage developed for the FVTX.

![](media/image2.jpeg){width="5.700694444444444in"
height="4.3493055555555555in"}

[]{#__RefHeading___Toc196886574 .anchor}Figure 3 Conceptual layout of
the PHENIX iFVTX showing the four stations (shown in green) of the
iFVTX, see Figure 1 for the schematic layout of the four stations.

.

The FPIX readout chip provides analog and digital processing with
zero-suppression and produces a digital output which is \"data-pushed\"
at 150 Mbps to intelligent readout boards (FVTX prototypes) containing
FPGAs. The data is then translated into the standard PHENIX format and
transmitted to the PHENIX DAQ system via fiber optics. For central Au-Au
events an event size of 4.4 KByte is anticipated, where the minimum bias
event size is on average 2.4 Kbyte.

Based on an LDRD Exploratory Research (ER) grant from LANL during
FY02-FY04 we were able to develop a conceptual design of forward silicon
tracking in PHENIX and to settle many of the R&D issues. The current
LDRD Directed Research (DR) project at LANL (FY06-FY08) will produce 4
stations of the pixel detector covering approximately 1/8 of one muon
arm, to be installed in the RHIC beam at the same time as the barrel
pixel detector. As part of this effort we have advanced the R&D for the
FVTX by fully designing the interface electronics that connects the FPIX
read-out chip to the PHENIX Data Collection Modules (DCMs) so that it
will seamlessly provide data to the existing PHENIX DAQ. In addition,
the LDRD DR project will support part of the design of the cooling
system and support structure.

This letter of intend has the following structure:

-   The physics motivation for the iFVTX and the simulated physics
    performance are given in Section 2

-   The general detector simulations and its performance are documented
    in Section 3.

-   Section 4 gives a detailed description of the inclusive forward
    vertex tracker and the technical aspects of the proposed project.

-   Section 5 describes mechanical aspects of the iFVTX.

-   Section 6 describes the infrastructure impact on PHENIX.

-   Section 7 discusses schedule and responsibilities.

# Physics Goals of the Inclusive Forward Vertex Detector

Our motivations for installing the iFVTX detector into PHENIX prior to
installation of the FVTX detector are two-fold:

\(1\) Since the iFVTX detector will provide the same physics measurement
capabilities as the FVTX and shares much of the same readout design,
commissioning of the iFVTX in PHENIX will give us significant learning
experience for commissioning the FVTX detector thereby reducing the
overall time needed to commision the FVTX detector when it is ready to
install in PHENIX.

\(2\) Although the acceptance of the iFVTX detector is significantly
smaller than the FVTX detector, we will still be able to make an early,
significant, heavy flavor physics measurement using single muons, for
any species of collisions. Since heavy flavor measurements have only
been made at forward rapidity with large systematic error bars in p+p
and d+Au collisions, and not at all in Au+Au collisions, a precision
measurement from the iFVTX detector could allow for us to make important
statements about heavy flavor production an in-medium modification at an
earlier stage than when the FVTX detector is available.

The primary physics measurements that the iFVTX detector will be capable
of making are forward rapidity heavy flavor cross section measurements
in p+p collisions, including a decomposition of the D and B
contributions and the first ever heavy flavor R~cp~ measurement in Au+Au
collisions at forward rapidity. The heavy flavor cross section
measurements are quite important to the RHIC program as there is
currently a significant discrepancy between PHENIX and STAR cross
section measurements, which has not been resolved to date. A less
ambiguous measurement made with much less background contributions
should help resolve this issue. We will also be able to make the first
statements about the decomposition of the charm and beauty contributions
-- a decomposition which is critical for the interpretation of heavy ion
flow measurements, for example. In addition, we will be able to make the
first ever forward rapidity heavy flavor measurement in Au+Au
collisions. To date, this has not been possible because the uncertainty
in the single muon background components yielded very large systematic
errors in the heavy flavor measurement.

The PHENIX inclusive Forward Vertex Detector (iFVTX) complements the
barrel vertex detector (VTX) already being built for PHENIX by providing
increased coverage in rapidity (adding one additional unit of rapidity),
providing a broad reach in transverse momentum, and allowing a larger
portion of the dynamical geometry of the hot dense matter created in
heavy ion collisions to be explored.

## Heavy Flavor Production and the Quark Gluon Plasma

The main goal of the RHIC heavy ion program is the identification and
study of the hot high-density matter created in heavy ion collisions,
i.e. the Quark Gluon Plasma (QGP). The energy loss of fast quarks or
gluons traversing this dense matter is very large, leading to the
observed suppression of high transverse momentum light hadrons. This,
along with large elliptic flow, large suppression of J/, and other
signatures observed by the RHIC experiments point to rapid
thermalization, extremely high energy density, and partonic rather than
hadronic interactions. The iFVTX detector coupled with a muon detector
system will allow for precision measurements of open charm and bottom
versus rapidity, pT and reaction plane in an inclusive data sample. We
expect that these precision measurements will help solve the uncertainty
in the total heavy flavor cross section at RHIC energies, provide a
mechanism for separating the charm and beauty components in the single
lepton spectra, and allow a first understanding of heavy quark energy
loss and flow in heavy ion collisions.

### Energy Loss and Flow of Heavy Quarks

One of the most significant physics results produced in the first
several years of RHIC operations was the measurement of strong
suppression of high-p~T~ light particle production in Au+Au collisions.
This is illustrated by measurements with the PHENIX detector, shown in
Figure 4 and Figure 5. Figure 4 shows the suppression factor for charged
and neutral pion production in Au+Au and d+Au collisions, with respect
to p+p collisions. The suppression factor for d+Au is typically greater
than 1 while the suppression for Au+Au collisions is approximately 0.2,
indicating that the large suppression seen in Au+Au collisions comes
from final state interactions with the produced medium and is not due to
initial state interactions or interactions within the Au nuclei. This
statement is further supported by the data shown in Figure 5 where the
light meson suppression factor for Au+Au collisions is shown compared to
a direct photon measurement. The direct photons, which do not interact
with the medium, show no suppression with respect to p+p collisions. The
strong suppression observed for the light mesons is interpreted as
energy loss of the outgoing particles or jets[^1]^,^[^2]^,^[^3] in dense
matter, with densities up to 15 times normal nuclear matter inferred.
This energy loss shifts the produced particle spectra to lower energy,
effectively suppressing the production at a given p~T~. These densities
are much larger than what is needed to dissociate nuclear matter into
quarks and gluon.

![](media/image5.png){width="4.278472222222222in"
height="2.9319444444444445in"}

[]{#__RefHeading___Toc196886575 .anchor}Figure 4 - Suppression of
high-pT hadrons and pions as seen in Au+Au vs d+Au collisions, measured
by PHENIX and published in PRL.

![](media/image6.png){width="4.4625in" height="3.620833333333333in"}

[]{#__RefHeading___Toc196886576 .anchor}Figure 5 -- High-pT suppression
of 0's and 's -- indicative of large partonic energy loss in high
density matter; compared to no suppression of direct photons which
indicates that the initial-state is not modified.

More recent measurements of heavy flavor measured via single leptons at
central rapidityError: Reference source not found indicate that heavy
quarks (charm and bottom) also suffer substantial suppression (see top
half of Figure 6). The heavy quarks even appear to flow, though the flow
measurements at high pT are rather imprecise (see bottom half of Figure
6).

![](media/image7.png){width="4.625694444444444in"
height="4.486111111111111in"}

[]{#__RefHeading___Toc196886577 .anchor}Figure 6 -- Heavy quark
suppression and flow vs pT from PHENIX measurements using electrons in
200 GeV Au+Au collisions at mid rapidity[^4].

The measurement of large suppression of heavy flavor production came as
a surprise because theoreticians predicted that heavy quarks would not
lose much energy in the hot-dense matter due to the \"dead-cone\"
effect[^5] \-- seemingly inconsistent with the recent results. This
dead-cone effect refers to the reduction in phase space that is
available for radiated gluons as you move to higher quark mass, thus
resulting in less predicted radiative energy loss for heavy quarks than
for light quarks. A number of different theoretical models now attempt
to explain the unexpected large suppression of heavy quarks:

-   Some studies suggest that the magnitude of the
    dead-cone[^6],[^7],[^8] may be similar between heavy quarks and
    light quarks, unlike the predictions in reference Error: Reference
    source not found, which would lead to an energy-loss for heavy
    quarks closer to that for light quarks.

-   M. Djordjevic11 suggests that collisional energy loss accounts for
    the extra suppression that is seen in the measurements. In this
    model, the charm suppression reaches approximately the levels of the
    measured inclusive heavy quark suppression and the bottom
    suppression would be much less than the charm suppression.

-   A. Adil, I. Vitev [^9] take into account the formation time which is
    long for light quark mesons (relative to the lifetime of the medium)
    but short for heavy quark mesons. Because of the short formation
    time, dissociation of the heavy quark mesons formed inside the
    medium is calculated to contribute to suppression of heavy meson
    production in addition to the heavy quark energy loss. In this
    model, the bottom component suffers less suppression than the charm
    component at low pT, but the two become comparable at as low as 10
    GeV.

-   Cold nuclear matter (CNM) effects will provide additional
    suppression of heavy flavor production, especially at forward
    rapidity. A rapidity dependence measurement helps allow separation
    of CNM effects and dense medium effects.

The predictions of these models for charm plus bottom production,
relative to p+p production, are indicated in Figure 11 and will be
described in the next section. To distinguish among these various models
higher precise measurements of heavy quark production are required.
Separation of charm and bottom will allow the collisional energy loss
and formation time models to be clearly distinguished, and a measurement
across a large rapidity range further distinguishes the models and helps
understand the cold nuclear matter effects. We will now show the heavy
flavor measurement precision that we expect to obtain with the iFVTX
detector.

### Charm and Bottom Measurements with the iFVTX

The signal to background improvements in charm and bottom that are
obtained with the iFVTX are discussed in Section 3.3. These improvements
will allow for a clean heavy flavor cross section measurement in p+p
collisions, a heavy flavor Rcp measurement in Au+Au collisions, and
separation of the charm and beauty components from the single muon
spectra. We discuss these iFVTX capabilities below.

#### Cross Section Measurements in p+p

The cross section measurements that can be made with the iFVTX detector
(compared to without the iFVTX) in p+p collisions are shown in Figure 7
for an integrated luminosity of \_\_\_\_\_\_\_\_\_\_. As can be seen,
the iFVTX provides a significant improvement in the error bars compared
to a measurement without the iFVTX.

![](media/image8.png){width="5.935416666666667in"
height="2.798611111111111in"}

[]{#__RefHeading___Toc196886578 .anchor}Figure 7 Heavy flavor cross
section measurements, at forward rapidity and versus pT, that can be
made with (blue) and without (red) the iFVTX detector.

**\*\*\*MAKE ABOVE PLOTS WITH IFVTX STATISTICS\*\*\***

#### Separating Charm and Bottom with the iFVTX Detector

To date, there has been no way to separate the charm and beauty
components contributing to the single lepton spectra. With the iFVTX
detector, the charm and beauty components in the single muon spectra can
be separated from each other by using the measured distance of closest
approach of the tracks. The DCA distributions for muons from the
semi-leptonic decay of D and B mesons differ not only because the
lifetimes for the different D and B particles are on average different,
but also because the decay angle of the muon coming from D particles is
on average smaller than the decay angle of muons coming from Bs. This
increases the measured difference in DCAs for the two sources of muons.
These differences are illustrated in Figure 8 where the decay distance
of D and B decay muons and the decay angle of the muons are shown (along
with the same distributions for  and K mesons).

![](media/image9.png){width="2.9902777777777776in"
height="2.354861111111111in"}![](media/image10.png){width="2.6215277777777777in"
height="2.286111111111111in"}

[]{#__RefHeading___Toc196886579 .anchor}Figure 8 Decay length of muons
from the semi-leptonic decay of D (red), B (blue), K and  are shown on
the left and the decay angle of the muon with respect to the parent
meson is shown on the right for the same particle types.

The method of evaluating DCA distributions to separate the D and B
components from the single muon spectrum is outlined in the following:
a) in a Monte Carlo individual D and B events are generated and the
reconstructed DCA values and p~T~ for each reconstructed decay muon are
recorded. For each set of events, for different p~T~ bins, one records
the fraction of decay muons that are kept (out of the total thrown) for
N different DCA bins. These fractional amounts
($f_{D,p_{T},\text{DCA}_{\text{bin}}}$,$f_{B,p_{T},\text{DCA}_{\text{bin}}}$)
are recorded for use in separation of D/B within a single muon spectrum.
b) a mixed sample of D and B events is generated, and for the same p~T~
and DCA bins as in (a) on obtains:

$$N_{\text{total},p_{T},\text{DCA}_{'\text{bin}}} = f_{D,p_{T},\text{DCA}_{'\text{bin}}}D_{\text{total},p_{T}} + f_{B,p_{T},\text{DCA}_{'\text{bin}}}B_{\text{total},p_{T}}$$

where $N_{\text{total},p_{T},\text{DCA}_{\text{bin}}}$ is the total
number of counts you have in a given DCA, p~T~ bin,
$f_{D,p_{T},\text{DCA}_{\text{bin}}}$ and
$f_{B,p_{T},\text{DCA}_{\text{bin}}}$are the fraction of Ds and Bs you
previously found (in a) to be retained when a DCA bin cut was placed on
the full set.$D_{\text{total},p_{T}}$and $B_{\text{total},p_{T}}$ are
the values one is interested in determining: the total number of D and B
events in a given p~T~ bin. This gives N equations (number of DCA bins)
and if one can minimize (N~total~-f~D~\*D+f~B~\*B)^2^, with respect to
the two desired unknowns, $D_{\text{total},p_{T}}$and
$B_{\text{total},p_{T}}$, one can extract the number of D and B mesons
versus p~T~ from your spectra. The analysis was carried out using our
multi-million event samples of fully simulated and reconstructed D, B
events. The results are shown in Figure 9 (left) where generated D and B
spectra are shown, and in Figure 9 (right) where the same spectra are
presented, overlaid with the extracted D and B components, based on the
method described above.

![](media/image11.png){width="3.004166666666667in"
height="2.0125in"}![](media/image12.png){width="2.995138888888889in"
height="2.025in"}

[]{#__RefHeading___Toc196886580 .anchor}Figure 9 Muons from thrown charm
events (black dots) and beauty (red crosses) are shown on the left. The
x axis is the pT of the reconstructed muons and the y axis is the total
number of counts. The same simulated spectra are shown on the right,
overlaid with the reconstructed spectra (blue dots are reconstructed
charm and blue crosses are reconstructed beauty).

The next figure, Figure 10, shows the fractional error one obtains when
taking the difference between the thrown and reconstructed spectra,
divided by the thrown spectra.

![](media/image13.png){width="5.24375in" height="3.5236111111111112in"}

[]{#__RefHeading___Toc196886581 .anchor}Figure 10 Fractional error in
extracted D component (black dots) and B component (red crosses).

As can be seen from the figures, one can extract the relative amounts of
charm and beauty yields to better than 10% over most of the pT range.

#### Heavy Flavor Rcp in AuAu Collisions

Heavy flavor R~AA~ measurements can only be made if both p+p and Au+Au
running take place while the iFVTX detector is installed. Since we do
not know if this will be possible, we look at the capabilities of making
R~CP~ (peripheral to central collision ratios) in Au+Au collisions.

![](media/image14.png){width="3.7916666666666665in"
height="3.6666666666666665in"}

[]{#__RefHeading___Toc196886582 .anchor}Figure 11 Heavy flavor RCP
measurement that can be achieved with 1.1 inverse picobarn AuAu
collisions, with the iFVTX detector (blue error bars) and without the
iFVTX detector (red error bars). Theory predictions which include
radiative energy loss (green band), radiative energy loss plus elastic
scattering energy loss (blue band) and radiative energy loss plus
dissociation (yellow band) are shown for comparison.

Taking our improved signal:background ratios that we achieve with the
iFVTX detector, and the expected luminosity (\_\_\_\_), we get the
predicted measurement capabilities shown in Figure 11. The red error
bars indicate the measurement precision that can be obtained without the
iFVTX detector, using RHIC Run 5 p+p statistics and the blue error bars
indicate the precision that can be obtained with the same integrated
luminosity run but using the iFVTX in the analysis. Also shown are
theory predictions which include radiative energy loss (green band),
radiative energy loss plus elastic scattering energy loss (blue band)
and radiative energy loss plus dissociation (yellow band).

> **SUMMARY**

# iFVTX Detector Performance

In this section we will discuss the general performance of the iFVTX and
its simulation.

The requirements in designing the iFVTX were:

-   Sufficient position accuracy so that the displacement resolution of
    a track with respect to the collision point is significantly less
    than the displacement produced by the c of charm and bottom decays

-   Low enough occupancy to allow accurate track finding in Au+Au
    central collisions.

-   Ability to match tracks from the muon arm (muon tracker and muon
    identifier) to those in the iFVTX silicon mini-strips, even in Au+Au
    central collisions.

-   2 values for tracks passing through the silicon will be large if
    the momentum is small and has been mis-reconstructed to a large
    value. Therefore, cutting on the 2 should discriminate against
    mis-reconstructed tracks.

The discussion of the above requirements and the simulations that
establish the iFVTX performance to satisfy these requirements follows.

## Simulation Code

The iFVTX detector sensitive and non-sensitive volumes have been
simulated in the PHENIX GEANT framework, PISA. The simulation includes
the beam pipe, the central silicon barrels, support structures, and the
forward silicon tracker. The radiation length per station in the forward
region is 0.96% of Silicon and 0.65% of Graphite and 0.42 % for the
Copper from the HDI traces. This includes sensor, readout chips, readout
bus, and support TPG panels. This small radiation length is achievable
because we are implementing a design that has minimized the readout bus
and the mechanical structure and have moved the support structure
outside of the active area. The output of the PISA simulation includes a
description of the materials and detector volumes in the GEANT
simulation (to be used by the offline code) and the x, y and z positions
of simulated tracks that hit sensitive silicon volumes.

![](media/image15.png){width="3.926388888888889in"
height="2.1805555555555554in"}
![](media/image16.png){width="1.4479166666666667in" height="2.53125in"}

[]{#__RefHeading___Toc196886583 .anchor}Figure 12 Layout of stations in
the Geant simulation on the left and the close-up view to the right.

The left side of Figure 12 shows a close-up view of the iFVTX
implementation in Geant. The right side of the figure shows the first
station, 2 layers of six staggered modules, each 73.6 by 6.4 mm, 250um
thick, with 5.6 mm gaps in between. The center-to-center spacing of the
front 6 and back 6 modules is 2mm. The bottom edge of the Silicon is
35mm from the nominal beam axis. Each pink rectangle depicts an \'8-chip
module\', which consists of a Si sensor and 8 FPIX2.1 readout chips

The detector volume description and the x,y,z positions are fed into the
offline code (Fun4All) where the detector response is simulated and
track reconstruction takes place. The simulation includes a full
digitization of the PISA hits into hit silicon strips. The cluster
finding of strips which belong to one hit, and a centroid fit is applied
to each cluster. The centroid positions of the clusters belonging to a
given track are then used in a Kalman Filter track fit. The parameters
from the track fit are used to project the track to the event vertex and
extract the distance of closest approach (DCA) of the track to the
primary vertex. This DCA value is then used to discriminate among tracks
which originate from the primary vertex and tracks which come from a
displaced secondary vertex. In the simulations that include the muon
spectrometers, tracks are found in the muon system and matched with
tracks in the iFVTX and a complete Kalman Filter track fit is applied to
get the correct track in the iFVTX. Missing in this full track
reconstruction is a track finding algorithm for the iFVTX tracks. While
this algorithm will most likely be patterned after the MuTR track
finding algorithm, we have not implemented this yet primarily because
the occupancy in the iFVTX is much less than that in the MuTR, so iFVTX
track finding should be much easier. At this point, we use Monte Carlo
information to combine hits together into tracks.

## Distance of Closest Approach Measurement

Figure 13 shows again the basic principle of using the iFVTX endcap
silicon detector to detect secondary tracks which have been produced at
a displaced vertex. A D meson is created at the primary vertex where the
two beams collide. It travels a distance proportional to its lifetime
and then decays semi-leptonically into a muon. The muon travels off at a
modified angle (due to the decay process), passing through four silicon
detector stations. The reconstructed muon track has a small but non-zero
*distance of closest approach* (DCA) to the primary vertex -- typically
200-300μm - unlike particles from pion and kaon decays, which have a
much larger average DCA and prompt particles which have a DCA that is
nominally zero.

![](media/image3.png){width="4.125694444444444in"
height="2.7555555555555555in"}

[]{#__RefHeading___Toc196886584 .anchor}Figure 13 - Principle of
operation of the iFVTX detector in the r-z plane. A D meson is produced
at the collision point. It travels a distance proportional to its
lifetime (purple line), then decays to a muon (green line). The muon's
trajectory is recorded in the four stations of the iFVTX. The
reconstructed muon track (dashed line) has a small, but finite distance
of closest approach (dca) to the primary collision vertex (black line).
The primary background is muons from pion and kaon decays, which have a
much larger average DCA because of their longer lifetime.

Reconstructed DCA distributions have been produced for prompt, single
muons of various momenta using our simulation code, to establish the DCA
resolution of the detector. Figure 14 shows the resolution along the
short and long dimension of the pixel. The top part shows that the
resolution is better than 100 micron above a momentum of 2 GeV/c while
the resolution along the long dimension stays around 300 micron. Figure
15 shows the z-vertex resolution for 5 GeV/c muons in the North arm
acceptance, the fit shows a resolution of approximately 180 micron,
appropriate for heavy quark measurements.

![](media/image17.png){width="3.6166666666666667in"
height="3.767361111111111in"}

[]{#__RefHeading___Toc196886585 .anchor}Figure 14 DCA resolution along
the small and long dimension of the pixel as function of the muon
momentum.

![](media/image18.png){width="3.7506944444444446in"
height="2.682638888888889in"}

[]{#__RefHeading___Toc196886586 .anchor}Figure 15 Z-vertex resolution of
\~180 micron with the iFVTX for 5 GeV/c muons in the North arm
acceptance.

## Heavy Quark Measurements with the iFVTX Using D, B X

Charm and bottom measurements can be made with the iFVTX and muon arms
using the semi-leptonic decay channels DX, BX. Figure 16 shows the
contributions from charm+bottom decays ("Prompt" in the figure), light
meson decays, and punch through hadrons to the single muon spectrum
(based on real Run 2 p+p data). The light meson decays dominate the
spectrum below pT of 2 GeV/c and the punch-throughs become comparable to
the heavy quark meson decays at \~3 GeV/c. These light meson
contributions to the single muon spectrum must be rejected if a
precision charm or bottom measurement is to be made. A DCA cut requiring
DCA\<DCAmax will reduce the muons from light meson decays, making a
charm measurement possible at low pT. A DCA cut requiring DCA\>DCAmin
will reduce the punch-throughs since the punch-throughs come from the
primary vertex, allowing a heavy flavor measurement at moderate to high
pT.

![](media/image4.png){width="4.249305555555556in"
height="2.8979166666666667in"}

[]{#__RefHeading___Toc196886587 .anchor}Figure 16 - pT distribution of
negative prompt muons (muons from heavy quarks), decay muons from  and
K and punch-through hadrons at pseudo rapidity () = -1.65. The
punch-throughs become the dominant background for pT values above 3 GeV.
The curves are simulations, based on real data extrapolations, while the
data are PHENIX measurement.

We have looked at the signal to background improvement for D and B
measurements by running full D, B and minimum bias PYTHIA events through
our simulation and seeing what fraction of each particle type survives
DCA cuts. and show how the signal to background for charm (D) and bottom
(B) measurements improves when DCAmin\<DCA\<DCAmax cuts are applied.
shows the signal to background improvement for particles decaying to +
and shows the improvement for particles decaying to -. There are more
background muons for + signals than for - signals.

![](media/image19.png){width="5.43125in" height="2.727777777777778in"}

[]{#__RefHeading___Toc196886588 .anchor}Figure 17 -- Signal to
background improvement for Ds (left) and Bs (right) which decay to +
for no vertex cut and successive iFVTX cuts. Cuts applied are 2 cut,
DCA cut in the phi direction, and DCA cut in the r direction.

![](media/image20.png){width="5.176388888888889in"
height="2.6131944444444444in"}

[]{#__RefHeading___Toc196886589 .anchor}Figure 18 - Signal to background
improvement for Ds (left) and Bs (right) which decay to - for no vertex
cut and successive iFVTX cuts. Cuts applied are 2 cut, DCA cut in the
phi direction, and DCA cut in the r direction.

For both charm and bottom, an improvement in the signal to background of
about a factor of 10 is attained over most of the pT range accessible by
the iFVTX and muon systems when DCA cuts are employed. These figures
will enable us to determine which pt ranges we can use to enhance either
B or D. Generally, D's dominate below 2 GeV and B's dominate above 3
GeV.

## Expected Count Rates 

We performed generator level simulation talking into account RHIC-I
luminosities and the acceptance of the iFVTX for 1.1 pb^-1^ *WHY is B\>D
?*

![](media/image21.png){width="3.2181102362204723in"
height="1.999212598425197in"}![](media/image22.png){width="2.841732283464567in"
height="2.2791338582677168in"}

[]{#__RefHeading___Toc196886590 .anchor}Figure 19 Count rates for open
heavy flavor reconstruction assuming 1.1 pb-1 AuAu collisions.

## Occupancy in Central AuAu Events

The iFVTX silicon pixels have a dimension of 50 m by 400 (600) m The
simulated hit density at the first silicon layer for central AuAu
collisions, simulated by PISA, is shown in Figure 20 Accounting for
charge sharing and the total yield of soft charged particles, the
maximum occupancy for the innermost module expected to be 0.1 % for
Au+Au central collisions which can be inferred from Figure 20. The
average number of hits in the whole detector for a central event is
about 540, resulting in 1100 pixels sending their data. The average
number pixels above threshold for a minimum bias event is 580 out of a
total of \~ 1,600,000 pixels. We expect this occupancy to be low enough
to allow accurate track finding even in the central-most AuAu
collisions.

##  {#section-1 .unnumbered}

![](media/image23.png){width="3.6979166666666665in"
height="3.5833333333333335in"}

[]{#__RefHeading___Toc196886591 .anchor}Figure 20 Hit display for a
central Au Au collision on the first layer. The maximum occupancy is
smaller than 0.1 percent.

![](media/image24.png){width="3.8854166666666665in" height="3.8125in"}

[]{#__RefHeading___Toc196886592 .anchor}Figure 21 Distribution of
numbers of hit pixels in the module closest to the beam for central AuAu
collisions. An average of 23 pixels out of 2816 respond in this maximum
occupancy example. For average numbers see main text.

## Matching Tracks from the Muon Spectrometers to the iFVTX/FVT 

The following section describes the track matching between the forward
vertex detector and the muon arms. The study was performed for the FVTX
but holds for he iFVTX as the two forward detectors have s similar
resolution and the occupancy for the iFVTX is rather small.

Track matching between the FVTX and muon systems is done by taking all
reconstructed tracks in the muon system, projecting them forward to the
last station of the FVTX system, and gathering any reconstructed FVTX
tracks which fall within a search window determined by the muon tracker
track. The window is nominally 3 cm radius to allow for scattering in
the absorber material between the FVTX and the muon tracker system. All
candidate FVTX tracks are fit together with the muon hits from the track
of interest and the FVTX track that produces the best combined 2 is
selected as a correct match. Figure 22 shows the chi-square
distributions for correctly matched candidates (red) and incorrectly
matched candidates (black) in central Au+Au events.

![](media/image25.png){width="2.9694444444444446in" height="2.44375in"}

[]{#__RefHeading___Toc196886593 .anchor}Figure 22 Chi-square
distribution for tracks which are correctly matched and fitted between
the muon and FVTX systems (red) and ones which are incorrectly matched
(black).

The number of tracks which are correctly matched to FVTX tracks, in
Au+Au events, is shown in Figure 23. As can be seen, we have reasonably
high efficiency for correctly matching the FVTX and MuTr tracks, with an
efficiency of approximately 85% achieved over most of the signal region
of interest.

![](media/image26.png){width="4.2868055555555555in"
height="3.2534722222222223in"}

[]{#__RefHeading___Toc196886594 .anchor}Figure 23 Fraction of
reconstructed muon tracks which are correctly matched to an FVTX track
versus momentum. Muons from heavy flavor decay were embedded in minimum
bias Au+Au events.

###  {#section-2 .unnumbered}

## Data Analysis for iFVTX/FVTX

For a heavy flavor analysis, we assume the following analysis steps must
be taken for real data. The physics plots presented in the proposal are
derived from scaling the simulations performed for the full FVTX by the
expected statistics for the inclusive sample of the iFVTX. This approach
was chosen to take full advantage of the time that went into the
production of the DOE proposal and is valid since the intrinsic
resolutions of the two detectors are the same although they dramatically
differ in size. For each analysis step, we will note how this step is
handled for the FVTX detector in our simulations of physics performance.
For all simulations one runs the full reconstruction chain for the muon
arms that is already in use for real data analyses. We used the PYTHIA
event generator for simulating p+p collisions and the HIJING generator
for simulating Au+Au collisions.

-   A single muon trigger is implemented online to get a reduced data
    set which has an increased level of events that have at least one
    particle which penetrates to the deepest layer of the muon
    identifier system. The same trigger that is currently used in PHENIX
    is assumed, and the efficiency losses are automatically included in
    our simulations, since our particle spectra are normalized based on
    real data signal and background counts that have been obtained with
    this trigger.

-   For simulation data, the digitization of Monte Carlo hits into hit
    pixels and clusters is performed. For both simulation and real data,
    cluster finding, track finding (pattern recognition), track matching
    between the muon tracker (MuTr) and FVTX, and track reconstruction
    are applied to the data and all reconstructed single particles and
    their reconstructed track parameters are stored. The DCA, chi-square
    of the track fit with the FVTX alone and the chi-square for a
    combined MuTR and FVTX fit are stored to allow for later track
    selection cuts. In the simulations the full reconstruction analysis
    for the FVTX system is implemented, from cluster formation to track
    reconstruction. This was done separately for a sample of signal
    events embedded in HIJING events and for very high statistics (of
    order four billion events) sets of PYTHIA-generated and single
    particle generated signals and backgrounds which are not embedded in
    HIJING events. Efficiency and background corrections were determined
    from the full multiplicity sample. These corrections are then
    applied to the high statistics simulation in order to evaluate the
    physics sensitivity. As the simulation time and the reconstruction
    time are long, it is not feasible to simulate billions of HIJING
    events. \[Note that the multiplicity dependence of the
    reconstruction efficiency and purity in PHENIX real data analyses
    are evaluated by embedding simulated signals into real Au+Au
    collision hit data.\]

-   Cuts are placed on the reconstructed single particles to reduce
    background components and thus enhance signal to background for a
    given signal of interest -- in this case, to reduce hadron
    punch-throughs and hadron decay muons with respect to muons from
    heavy flavor decay. The same cuts have been applied to the mixed
    events and to the cleaner PYTHIA events, to understand whether
    additional corrections should be applied to the PYTHIA event samples
    to account for lower efficiency for the signal and/or increased
    background tracks in higher-occupancy events

> .

-   After the above reconstruction steps and single track cuts, the
    remaining single particle spectra now include mainly heavy flavor
    decay muons rather than background particles, and not vice versa as
    is the case without the iFVTX/FVTX. The magnitude of the signal and
    the remaining background in simulations is calculated as follows:
    First, the input distributions for punch-through hadrons, decay
    muons from hadrons, and decay muons from heavy flavor are normalized
    to the real spectra from each source that have already been measured
    with the PHENIX muon arms. (Note that we assume that the relative
    normalization of each component is the same for Au+Au events and p+p
    events. Hadrons have been measured to be suppressed in Au+Au
    collisions with respect to binary scaling, but heavy flavor
    production also appears to be suppressed at a similar level.
    Therefore the fractional amounts of each should be similar in Au+Au
    events and p+p events.) Next, the sum of these components is passed
    through the reconstruction steps described above. After applying all
    cuts, we calculate how much of each type of background and how much
    signal remain. The total signal counts from these simulations are
    corrected for efficiency losses due to the background rejection cuts
    and efficiency losses due to imperfect track finding in HIJING
    events. The background rates are also corrected for any additional
    background which is created from imperfect track finding in HIJING
    events and/or reduction in rejection. We then calculate a signal to
    background ratio and the remaining signal counts. From these the
    statistical and systematic errors for the extracted signal can be
    calculated

-   Any remaining background is handled with the same background
    subtraction techniques used in analysis of the current muon arm
    data. The number of muons from  and K decay is determined from the
    vertex distribution of single particles---more decay muons are
    produced far from the absorber than close to the absorber so the
    vertex distribution can be fit to extract the amount of long-lived
    decay muons contributing to the single particle spectra. The
    punch-through hadrons are estimated by looking at the distribution
    of particles that reach each depth of the muon identifier---muons
    that stop in a given muon identifier layer produce a relatively
    narrow momentum peak (measured by the muon tracker system) for each
    layer, but punch-through hadrons populate a long tail in the
    momentum distribution in a given muon identifier layer since the
    hadrons can shower within the muon identifier. Therefore, the
    momentum distribution at each muon identifier layer can be used to
    extract a relatively clean sample of punch-throughs that are
    reaching each layer. The fraction of these hadrons in the total muon
    sample is extrapolated to beyond the last plane and to higher
    momenta using Monte Carlo. This procedure is significantly improved
    with the introduction of the iFVTX/FVTX, since cuts on the
    iFVTX/FVTX substantially reduce the background. Significantly
    smaller statistical errors are incurred in the signal extraction
    because the background subtracted is smaller. Furthermore, the
    uncertainty in the normalization of the background contributes less
    systematic uncertainty in the extracted signal.

-   Physics plots are produced by scaling the FVTX results with the
    statistical expectations for the inclusive measurements with the
    iFVTX. The physics plots are based on the number of calculated heavy
    flavor muons accepted by the cuts, with error bars taking into
    account the background that must be subtracted (giving an additional
    statistical error component) and the uncertainty in this background
    (giving a systematic error component)

## Luminosity Assumptions

For the plots generated in this document, we have assumed one year
running at RHIC I.

We assumed 2 nb^-1^ delivered luminosity for one year of Au+Au running,
and 70 pb-1 for one year of p+p running the following efficiency
factors:

-   55% for \|z vertex\| \< 10 cm

-   60% PHENIX duty factor

-   79% min-bias p+p trigger efficiency, 90% for Au+Au trigger
    efficiency

-   90% trigger efficiency

-   90% for p+p reconstruction efficiency, 70% for Au+Au efficiency

-   1/16 for the iFVTX active area with respect to the FVTX

Multiplying these together gives for the iFVTX, for instance, the
equivalent of \~1 pb-1 for one year of p+p for RHIC I and \~0.02 nb-2
for Au+Au Some double-counting of inefficiencies are in place since we
also separately correct our simulated data for reconstruction efficiency
of the specific signal of interest.

## Physics Performance

![](media/image27.png){width="3.765277777777778in"
height="3.6013888888888888in"}

[]{#__RefHeading___Toc196886595 .anchor}Figure 24 Expected performance
of the iFVTX for the RCP measurement.

We performed an analysis on the expected performance of the iFVTX for
the measurement of the nuclear modification factor R~CP~ **.**The result
is shown in **Figure 24. *This has to be checked and discussed !***

# iFVTX Detector System

## Overview

The iFVTX detector consists of 4 stations in a cage mounted in the FVTX
space frame in front of the north muon spectrometer. Figure 25 shows a
three dimensional model of the two detectors, the geometrical parameters
are shown in Table 1. The VTX detector and the iFVTX share an
environmental enclosure. The environmental enclosure is needed because
the barrel strip detectors must be operated below room temperature. The
enclosure radius is 25 cm except close to the absorbers (the nose-cone
surface) where the enclosure extends out to at least 45 cm. The larger
radius ends are used for the barrel pixel layer transition electronics
and all of the barrel bus cables, power and cooling lines plus all of
the utilities and cables for the forward vertex system. An ongoing
integration study of these utilities and cable routing is being pursued
for the VTX barrel upgrade. The design of the enclosure and mechanical
structure will include the needs of both the barrel and the FVTX forward
upgrades.

The four iFVTX stations are compatible with the FVTX supports and are
mounted at the same z-positions along beam line. Each station consist of
two identical planes mounted vertically offset to each other to allow
for complete tracking coverage. Each plane has ten 8chip hybrids mounted
on a cooled thermal pyrolytic graphite (TPG) support plane. The TPG is
supported via a printed circuit board made from FR4. The technology for
the pixel sensors is n-on-n detectors, originally developed for the
ATLAS experiment at the LHC. Eight FPIX2.1 readout chips are bump bonded
on sensor. The readout chips are wired bonded to a high density
interconnect (HDI) produced by Dyconex. The total number of readout
pixels in the iFVTX is \~ 1,500,000, the total chip count is 528.

![](media/image28.jpeg){width="4.75in" height="3.125in"}

[]{#__RefHeading___Toc196886596 .anchor}Figure 25 - 3-D model of the
full vertex detector showing the barrel portion and the iFVTX on the
right.

[]{#__RefHeading___Toc196106504 .anchor}Table 1 - Summary of the
parameters of the iFVTX stations.

  --------------- ------------------- ------- --------- --------- ---------
  iFVTX           Station             Z1      Z2        Z3        Z4

  Geometrical     z (mm)              197.7   254.7     309.7     364.2

  Dimensions      R (mm) inner        3.5     3.5       3.5       3.5

                  R (mm) outer        10.6    17.0      17.0      17.0

  Unit Counts     \# of planes        2       2         2         2

                  hybrids/station     2\*3    2\*10     2\*10     2\*10

                  readout chips       2\*24   2\*80     2\*80     2\*80

                  Readout Channels            450k      450k      450k
                  135k                                            
  --------------- ------------------- ------- --------- --------- ---------

In Figure 26 a side view of the detector is show with an indication of
the z position of the 4 stations; all measurements are with respect to
the nominal interaction point. The brownish structures are the 3M
connectors for the readout system.

![](media/image29.jpeg){width="3.8583333333333334in"
height="3.6847222222222222in"}

[]{#__RefHeading___Toc196886597 .anchor}Figure 26 Side view of the iFVTX
detector system, all measurements are in mm.

![](media/image30.png){width="6.25in" height="3.920138888888889in"}

[]{#__RefHeading___Toc196886598 .anchor}Figure 27 Block diagram of the
readout system required for the iFVTX (prototype and therefore very
similar to the FVTX). The read out cards and the front end module are
boards which will reside between the FPIX readout chip and the DCM and
are currently under development.

The data from the readout chips will go through two successive boards at
large radius on the 'big wheel' before going into the PHENIX DCMs, as
indicated in Figure 27. The first board, the ROC, will reside inside the
enclosure and will perform the functions of: stripping the sync words
out of the data, collecting the data of several FPIX chips together,
serializing it and sending it out on optical fiber to the FEM.
Additionally, the ROC will provide calibration pulses for the FPIX chips
and route download and read back lines to and from the chips

The second board, the FEM will reside inside the counting house and will
receive data from the ROC(s), buffer it until a Lvl-1 accept is
received, retrieve the data of interest for the Lvl-1 accepts and
package the data for the DCMs. It will also perform the function of an
overall slow-controls manager: passing data to and receiving data from
the ROCs/FPIXs and the PHENIX DAQ system

## Detector Description

In the following we discuss the readout chip, the sensor, the module,
the detector plane and the full station.

[]{#__RefHeading___Toc196886599 .anchor}Figure 28: FPIX2.1 block
diagram; arrows represent control and data flow.

### The Readout Chip FPX 2.1

The iFVTX uses the FNAL developed chip FPIX 2.1, the result of an R&D
project for the now defunct BTeV experiment. It was designed to readout
ATLAS developed modified p-spray n-on-n silicon pixels with a cell
dimension of 50 micron by 400 micron (600 micron on the chip edge).

The FPIX features a 'data push' architecture. It incorporates
simultaneous read/write in a dead time free configuration. The FPIX
output provides a 7 bit address, a 6 bit time stamp, and 3 bits of ADC
for each hit. The chip will also output sync words comprised of 19 zeros
followed by a one, which are used by the downstream acquisition to
synchronize word boundaries. The functionality of the chip is separated
into four distinct phases; analog process the hit, zero suppress,
serialize1 and serialize2. The four-phase architecture assures that up
to four hits from a single event can be processed and delivered within
four beam crossing periods.

FPIX2.1 consists of four logical sections: the core, the programming
interface, the programmable registers and digital to analog converters,
and the data output interface. A block diagram of the chip is shown in
Figure 28.

The core consists of the pixel unit cells, each of which contains an
amplifier and a flash ADC, end-of-column logic associated with each
column of pixels, and core logic, which controls the flow of data from
the core to the data output interface. The programming interface accepts
commands and data from a serial input bus, and, in response to commands,
provides data on a serial output bus.

The programmable registers are used to hold input values for the DAC's
that provide currents and voltages required by the core, such as the
discrimination threshold and the threshold levels for each of the FADC
bits. The data output interface accepts data from the core, serializes
the data, and transmits it off chip using a point-to-point protocol. All
I/O (except the test signal inject and the analog output signal from
pixel 0,0) is differential and uses Low Voltage Differential Signaling
(LVDS). The drivers are designed to drive 10 m of twisted pair cable.

####  FPIX Core

The FPIX Core consists of an array of 22 columns of 128 rows of pixel
unit cells. Each column has associated end-of-column logic. The flow of
data out of the core is controlled by core logic. The BCO (beam
crossing) clock is used to synchronize changes of state in the
end-of-column logic and to provide a time stamp for pixel hits. The read
out of data is controlled by a separate clock. These two clock domains
are logically separate; there is no requirement on the relative phase or
frequency of the BCO clock and the readout clock.

#### Pixel Unit Cell

Figure 29 shows the pixel unit cell with the analog part of the pixel to
the left and the digital part to the right.

![](media/image31.jpeg){width="5.990972222222222in"
height="3.3069444444444445in"}

[]{#__RefHeading___Toc196886600 .anchor}Figure 29: Pixel unit cell, the
analog section is to the left, the digital section to the right.

##### Analog Section

The FPIX2.1 amplifier is a two-stage amplifier. The first stage provides
most of the amplification, and the pulse shaping. Charge is integrated
on a 7.5 fF capacitor. For small signals, the transistor in feedback
acts like a large resistor, with resistance controlled by Vfb. When the
voltage from source to drain of the feedback transistor gets large
enough (either due to leakage current or in response to a large signal),
the transistor goes into saturation and becomes a constant current
source, whose value depends on Iff and the ratio of W/L (channel width W
to the channel length L) of the two FET's. This provides both a sink for
sensor leakage current and a "continuous time reset" for large signals.
The output of the preamplifier is buffered by an approximately unity
gain stage, and is AC coupled to the second amplifier stage. With
nominal settings, the rise time (to 90%) of typical signals is about 40
ns.

The second stage of the amplifier is intended as a gain stage only, with
a gain of four, determined by the ratio of the feedback capacitor to the
coupling capacitor. The threshold of each of the eight comparators is
determined by the voltage difference between Vref and Vth0 -- Vth7. A
hit is registered whenever the output of the second stage (a
negative-going signal) goes below Vth0. The seven other comparators,
together with an encoder, form a three bit flash ADC.

#### Programming Interface

The programming interface provides a means for the user to control the
operation of FPIX2, and to load and read back the contents of any of the
programmable registers. Serial commands are input to the programming
interface using the "shift control" and "shift in" lines. The
programming interface will respond to all broadcast (wild chip address =
10101) commands, and to all commands in which the chip address matches
the contents of the "chip address register".

#### Kill and Inject Registers

Kill and Inject are serpentine registers running up and down the pixel
columns. Each register has one bit in each pixel unit cell (22 x 128 =
2816 bits in each register). Kill=1 opens a switch at the output of the
pixel discriminator, effectively killing the pixel. Inject=1 closes a
switch connecting the Test Signal Inject line to the charge injection
capacitor associated with a pixel.

####  Data Output Interface

There are four functional blocks in the data output interface: the clock
control logic, the next word block, the word serializer, and the
steering logic. The relationship between these blocks are shown in
Figure 30 .

[]{#__RefHeading___Toc196886601 .anchor}Figure 30: Data Output Interface
block diagram.

The (nominally 140 MHz) Serial Clock is used for data read out and
transmission. The clock control logic block uses the serial clock to
derive the two clocks used internally to control read out (RCLK and
SCLK), as well as the output Data Latch Clock (DLCLK), which is output
along with the serialized data.

.

The word serializer block serializes the data for output. On the falling
edge of RCLK, the word held in the flip flops at the output of the next
word block is latched into the serializer flip flops. This data is
output serially to the steering logic in 1, 2, 4, or 6 parallel paths
depending on the status of the "active lines" register (Alines), which
controls the data output configuration.

#### Resets

The FPIX2 has one hardware reset ("fire fighter reset") and two software
resets ("smart core reset" and "smart programming reset"). It is
expected that all chips on a sensor module will share the hardware reset
lines, so that all chips will be reset at once. The software reset
commands may be broadcast to all chips on a module, or sent to one chip
only. If an FPIX2 loses BCO synchronization, then a 'smart core reset'
will recover synchronization without requiring the DOI or programmable
registers to be reset.

#### Thresholds

The readout chip can have the threshold set in a collective mode were
all chips in the module are set to the same threshold our in an
individual mode were each chip can have a different threshold set. The
minimal collective threshold achieved is 2000 electrons while the
minimal individual threshold achieved is 1700 electrons.

#### Power Consumption

Figure 31 show the power budget for the FPIX 2.1 and the areas of heat
load on the chip surface. The power per chip is about 500 mW, i.e. about
12 micro Watt per pixel on average.

![](media/image32.jpeg){width="5.11259842519685in"
height="5.859055118110236in"}

[]{#__RefHeading___Toc196886602 .anchor}Figure 31 Picture of the FPIX
2.1 chip with an overlay of the areas of power production.

### The Silicon Sensor

The silicon detector used in the iFVTX is the BTeV silicon pixel sensor
that is based on rectangular 50µm x 400µm pixel elements, and it is
connected via bump bonds to the read out FPIX chip, developed at
Fermilab. The pixel is n^+^-diffusion on an n-type substrate having
p^+^-diffusion on the other side. This structure allows pixel operation
under partial depletion after substrate type inversion, thus increasing
the detector's lifetime. However, a special isolation technique between
pixels must be used in order to avoid electrical shorting of n^+^/n
pixels due to the electron accumulation layer induced by the oxide
charge. ATLAS developed the moderated p-spray isolation technique, which
improves the high voltage stability of the device. Here the nitride
layer is opened only in the middle of the gap between two pixel
implants, leading to a step in effective p-spray dose along the gap
since the nitride layer shadows the region beneath during the p-spray
implantation.

The sensors are made on 4 inch diameter, 250µm thickness, \<111\>
orientation, n-type, double side polished, 1-2.5KΩcm resistivity silicon
wafers. They were produced by the company CIS Mikrosensorik in Germany.

All tiles contain uniform arrays of rectangular 50µm x 400µm pixel
elements. Considering the readout chip dimensions, each group of pixels
that is read out by one FPIX chip has the 'first' and 'last' columns
with longer pixels (600µm instead of 400µm length) as can be seen in
Figure 32. The bump pad, normally at one end of the pixel, is 12.5 µm in
diameter.

![](media/image33.wmf){width="3.8645833333333335in"
height="0.5416666666666666in"}

[]{#__RefHeading___Toc196886603 .anchor}Figure 32 Pixel layout at the
edge of the detector with 600µm instead of 400µm length long pixels.

The pixel cells have an n+ diffusion width of 30µm, with a distance
between diffusions of 20µm. Half of this distance is p-implanted in
addition, for better pixel isolation purposes, using a 10µm opening in
the nitride mask. This is the so-called moderated implant feature of the
design. Since this p implantation has a gap of 5µm to the n+ pixel, the
breakdown voltage of pixel's junction is not decreased too much by the
p-type implantation. Each pixel has four n+-metal contacts and the metal
covers basically the full pixel's diffusion area, up to a distance of
2µm from its edge. An 83µm bias ring surrounds all pixels inside a tile,
with pad openings for external bias. On the outside of the bias ring a
large n+ guard ring is extended to the tile's scribe line. Both bias and
guard rings have pad openings for external bias and bump pads for
eventual bias through the readout chip. In the 15µm isolation gap
between these rings there is also a 5µm wide opening in the nitride
layer for moderated p-spray implantation.

The p-side or junction-side of the sensor consists of one large
p+-diffusion aligned with the full matrix of pixels from the other side.
A p+-metal contact ring at the periphery is used and the metal is
covering all the p+-diffusion area. Laser shining holes aligned with
pixels are provided for testing purposes. For high voltage and module
assembly reasons, each tile has one large-opening square pad for
external bias, located in the center of the first corresponding readout
chip. This HV pad has an area of 3 x 3mm2 and will be electrically
connected with HDI cable using a wire bond.

In order to increase the breakdown voltage of the sensor and also to
minimize the danger of sparks from the edge of p-side to the pixel side,
a structure containing 16 guard rings surrounds the p+-junction. The
width of all rings is 10µm. For the first 11 guard rings, the gap
increases from 10.5µm to 15µm in increments of 0.5µm. The last 5 guard
rings have gaps from 41.5µm to 49.5µm in steps of 2µm. The metal line on
top of all these rings is wider than the diffusion width and extends
more toward the inside of the structure. The full guard ring structure
can thus be modeled as a chain of PMOS transistors with the metal gate
shorted to source with no overlap over the drain. The breakdown voltage
of the bias p+ junction is thus the sum of the drain-source punch
through breakdown voltage of each PMOS transistor in the chain.

![](media/image34.jpeg){width="4.354861111111111in"
height="4.573611111111111in"}

[]{#__RefHeading___Toc196886604 .anchor}Figure 33 Photograph of the CIS
produced sensors after their arrival at LANL.

![](media/image35.jpeg){width="4.355555555555555in" height="4.14375in"}

[]{#__RefHeading___Toc196886605 .anchor}Figure 34 Close-up of the wafer,
the eight chip sensors are the 6 long structures in the center. The
wafer holds in addition 2 four and 4 one chip sensors plus several test
structures.

### The High Density Interconnect

The pixel hybrid module shown as a cross section in Figure 35 is
composed of three layers (the forth shown is the cooling substrate TPG),
the high density interconnects (HDI) flex circuit forms the bottom layer
of the module and provides support for the back of the readout IC that
is in thermal contact with the ground plane on the top layer of the HDI
by means of an 2μm thick silicon based tape, while the other side of the
readout IC is flip-chip bonded to the silicon pixel sensor through
spherical solder bumps (PbSn) 12.5 μm diameter. The clock, control, and
power pad interfaces of FPIX2.1 readout chip extend beyond the edge of
the sensor and are wire bonded to the HDI. The HDI then extends to one
end of the module where a set of wire bond pads interfaces to the HDI
for the data acquisition system and in the other end a set of pads
interfaces with power and high voltage lines through wire bonds.

[]{#__RefHeading___Toc196886606 .anchor}Figure 35 Cross section of the
detector stack up, the flip chip assembled readout is glued to the HDI
which is glued on the TPG carrier. While the sensor-readout chip
connection is achieved via bump bonds, the chip itself is connected to
the HDI via wire bonds.

The large density of signals in this design imposes space constraints
and requires aggressive design rules, such as 50μm trace width and pads
of 150μm. This module uses a "sandwich" structure HDI with four layers
were the two inner layers are signal layers and the external layers are
power and ground layers. The data, control and clock signals as well as
trigger out signal use the two inner layers, these signal layers are
differential and the HDI lines are built with controlled impedance to
match 100Ω. The power uses the bottom layer, while a single ground uses
the top layer. The power plane is split in two, one analog and one
digital. The HDI also carries decoupling capacitors for both analog and
digital power and they are sitting in both sides of the HDI, close to
the sensor. The trace lengths and vias that connect the capacitors to
the chips are minimized to reduce the interconnection inductance. All
the traces are copper.

In order to minimize coupling between digital and analog elements
signals are grouped together into two different regions. The digital and
analog traces are laid out on top of the digital and analog power supply
traces, respectively. Furthermore, a ground trace runs between the
analog set and the digital set of traces. The high voltage trace has a
clearance of 1mm from any other trace and it is connected to a round pad
on the top layer of the HDI , which is then wire bonded to the sensor. A
high voltage capacitor and a resistor were placed on the PCB plan in
order to filter the high voltage line and limit the maximum current.

The pixel module posses testing taps on both ends of the HDI, it is very
useful during the certification phase of the module on the later
mentioned port card and is only used for the tests of the module, it
will be disposed after the testing is done by simply cutting it off
before placing the module on the plane.

The HDI is glued to a piece of thermal pyrolytic graphite (TPG) to
transport the heat to the cooling lines, see Figure 35.

### The Module and Assembly

The module contains an array of 22528 pixels with a density of around
3000 pixels/cm2, covering an area of approximate 5.6 cm^2^ and a volume
of 0.14 cm^3^ as the thickness of the sensor is 250 μm. The eight-chip
module is an array of 1024 rows and 176 columns and each individual
readout chip instruments 128 rows and 22 columns. The pixel size is 400L
× 50W × 250T μm^3^ for the 20 internal columns and 600L × 50W × 250T
μm^3^ for the columns on the edge.

### Detector Plane

![](media/image36.png){width="3.5133858267716533in"
height="3.5507874015748033in"}

[]{#__RefHeading___Toc196886607 .anchor}Figure 36 CAD drawing of pixel
plane with 10 modules. The three mounting flexures and the two stiffer
bars are visible.

The detector plan is constructed from a multi layered printed circuit
board that carries the connectors for LV, bias, inject and signals plus
two LVDS clock repeaters. In the center cutout the TPG is located that
carries the 10 modules. Figure 36 shows the CAD drawing of the plane,
the first prototype of the pixel plane is shown in Figure 38.

![](media/image37.jpeg){width="5.617361111111111in"
height="2.959722222222222in"}

[]{#__RefHeading___Toc196886608 .anchor}Figure 37 Picture of the
prototype printed circuit board for a plane, the dark area is the TPG
insert for the cooling of the modules.

![](media/image38.jpeg){width="5.079861111111111in"
height="3.8097222222222222in"}

[]{#__RefHeading___Toc196886609 .anchor}Figure 38 Photograph of the
prototype plane with various test modules. The extra board mounted in
the lower picture was a clock distribution test board, for the
production layout these chips are mounted directly on the plane.

### The Cooling Concept and Design

The proposed cooling uses the same coolant as the VTX/FVTX at room
temperature. With 1 cooling line per plane made from PEEK tubing, see
Figure 39, there is a total of 8 cooling loops total, they will be
attached via silicon tubing to a manifold, designed my HYTEC, that is
located in the support cage. With a heat load of 4 Watt per module the
total heat load will be about 300 W, small compared with the VTX
requirements.

![](media/image39.png){width="6.008333333333334in"
height="4.258333333333334in"}

[]{#__RefHeading___Toc196886610 .anchor}Figure 39 CAD drawing of a
station build by mounting two planes face to face. The two planes are
offset by the width of one module. The cooling loop on the TPG is
visible. The loop itself is made from PEEK tubing, precision molded to
have one flat surface which is glued to the TPG.

![](media/image40.png){width="2.5216535433070866in" height="3.0in"}

[]{#__RefHeading___Toc196886611 .anchor}Figure 40 Drawing of the offset
of the two planes, the station is optimized for an average crossing
angle of 22 degrees, matching the muon arms.

### Cable Assembly

Each plane has a signal, power, Bias and inject connector. The signal
cables are made from twisted ribbon cable and connected via 50 pin 3M
connectors. They are held via strain relieves that can be seen in Figure
41 in yellow. Hirose connectors for power, bias and injection signals
are used. The cables for power are bundled 18 gauge wires, the inject
lines will be shielded flat ribbon and we will use a shielded single
wire cable per plane to carry the bias voltage. It will be filtered and
fanned out on a small board that connects to the Hirose connector.

### Station Layout and Cage Mount

![](media/image2.jpeg){width="5.992361111111111in"
height="5.243055555555555in"}

[]{#__RefHeading___Toc196886612 .anchor}Figure 41 CAD drawing of the
four stations mounted in the cage developed for the FVTX. The cooling
lines, the cables and the strain relieve is show.

## Readout Electronics Description

The design of the readout electronics for the iFVTX detector is based on
three major constraints, imposed by the detector:

-   Large instantaneous bandwidth 2(out lines)\*150(MHz)\*576(chips) =
    172 Gb/s

-   Radiation hardness of readout components near the interaction point

-   Large amount of I/O lines 2.5\*576(chips) 1,440 LVDS pairs

As a result, the readout electronics are logically divided into two
independent blocks\
(see Figure 42 ):

-   Read Out Card (ROC) -- module which is located close to the detector
    and:

    -   Receives LVDS data over a twisted pair cable

    -   Combines and synchronizes data stream from several FPIX chips

    -   Sends the data to the counting house (CH) over optical fiber

-   Front End Module (FEM) -- module, which is located in the counting
    house and:

    -   Receives data from ROC over a fiber link

    -   Sorts the incoming data according to the Beam Clock Counter(BCO)

    -   Buffers the data from the last 64 Beam Clocks

    -   Upon LVL1 trigger decision, ships the data from the Beam Clock
        of interest to the output buffer which ships data to the PHENIX
        Data Collection Modules

The output of the FEM connects to the standard PHENIX DAQ board -- Data
Collection Module (DCM II) and from this point on the data stream
becomes a part of the standard PHENIX DAQ.

![](media/image30.png){width="6.25in" height="3.920138888888889in"}

[]{#__RefHeading___Toc196886613 .anchor}Figure 42 iFVTX Detector Readout
Diagram

![](media/image41.png){width="3.6694444444444443in"
height="4.872222222222222in"}

[]{#__RefHeading___Toc196886614 .anchor}Figure 43 ROC Block Diagram

#  {#section-3 .unnumbered}

### ROC Design Specifications

The ROC board design utilizes radiation hard FLASH-based ACTEL FPGAs in
order to be not susceptible to single-event-upsets. The proposed ROC
board diagram is shown in Figure 43. The board contains 4 medium scale
ACTEL A3PE1500-FG676 FPGAs, 17 16-bit Serializer/Deserializer chips
(TLK2711) and two 12 optical fiber transmitters (HFBR-772BEZ) to send
the data to 2 FEM boards. Each FPGA holds two completely independent
"ROC channels" which send out 32 bit data at the Serial Clock frequency
(135 MHz). The outgoing data is logically split into two hi/lo 16-bit
data portions which are each sent to separate Ser/Des chips and one
single fiber channel. A separate small scale ACTEL FPGA is dedicated to
distribute Slow Control signals to appropriate chips. Slow Control data
are being sent by the FEM to the ROC over a single fiber interface.

> ![](media/image42.png){width="3.6479166666666667in"
> height="3.6791666666666667in"}

[]{#__RefHeading___Toc196886615 .anchor}Figure 44 The FEM design

### FEM Design Specifications

The FEM board is going to be located in the Counting House and thus has
no radiation tolerance requirements. As the design of the FEM requires a
lot of memory management, we propose to use the VSX series Xilinx
Virtex-4 FPGAs for the main FEM logic. Optimization of cost/FPGA
suggested us to use one of the largest possible FPGA devises (XC4VSX55)
and combine 4 FEM channels onto a single FPGA. An alternative solution
of using 4 smaller FPGA devices (XC4VSX35) on a board increases the
overall cost of a FEM board by 50%.

One FEM board receives 8 optical fibers (½ of a ROC board). The incoming
16-bit data nibbles from the ROC are aligned and combined into 32-bit
data words ("comma" bits are planned to be used in transmission). Data
are buffered for 64 Beam Clocks in one of 4 FEM channels.

A separate small-scale FPGA (Spartan3 XC3S200) processes incoming timing
signals and slow control commands. Timing in PHENIX is distributed
through a specially designed Granular Timing Module (GTM). The GTM
signals include a 9.4 MHz Beam Clock, a Level-1 Trigger and Control Mode
Bits. These signals are copied to the main FEM FPGA and also sent to the
ROC board.

The Slow Control FPGA also controls download of initial register values
into each FPIX chip that a given FEM controls. Initial values for
registers are stored in a 1Mb EEPROM on the FEM board. The content of
the EPROM is transferred to the FPIX chips, as is, upon request and
individual values are modified via the slow control interface.

Upon receiving of a Level-1 trigger, the FEM channels start sending the
data from a particular "clock bucket" to the output sub-event buffer.
This process should be as fast as possible so the data from beam
crossing X+64 do not arrive until the bucket for clock X has been
emptied. The current speed for the read is set to 300 MHz. The resulting
sub-events are combined and packetized in the "Channel Combiner" into
16-bit wide packets. Packets carry fixed data (Event Counter, BCO
Counter and Longitudinal Parity) in header and trailer words.

A single FEM channel design has been successfully implemented on an
ML402 VSX35 evaluation board and has been proven to work at our
specified input and output data rates. The design of a full 4 channel
FEM module is coded and ready to be implemented (except for Channel
Combiner block).

![](media/image43.png){width="5.215972222222222in"
height="3.9118055555555555in"}

[]{#__RefHeading___Toc196886616 .anchor}Figure 45 Scope capture of data
synchronization for the ROC prototype

### ROC and FEM Prototype Performance

The design of the FEM and ROC channels was tested using a single FPIX2.1
and an 8-chip FPIX2.1 hybrid module.

Tests of the proposed designs included testing signal propagation
throughout the design using "fake" data and real data generated through
injection of the test pulse into a particular FPIX pixel, cosmic data.
All the components have been optimized and tested to perform at proposed
design speed levels. The ultimate test for the ROC and FEM design was a
full calibration scan of a particular detector at full speed, which was
performed successfully.

The ROC channel data combiner block was tested by implementing a 24-chip
combiner (8 input channels were connected) on an ACTEL ProASIC3 Starter
Kit board (with A3PE600 FPGA). The serial data word from an FPIX chip
consists of 24 bits and we used single line readout for testing. Figure
45 shows the serial output (yellow) from the one of 8 chips, Sync Word
detection flag (blue) and "ring counter to 24" threshold output (green).
One can clearly see the Data Word in the data stream and it is
identified with 100% efficiency.

![](media/image44.png){width="5.247916666666667in"
height="3.935416666666667in"}

[]{#__RefHeading___Toc196886617 .anchor}Figure 46 Combining data from 8
chips in ROC prototype

Figure 46 shows the data combining from different chips. One can clearly
see a packet of 7 hits is being written into an output FIFO at full
speed (green). Each chip is sampled only once per 24 clocks and we
combine the data correctly (one chip out of 8 had a broken LVDS line and
could not be read-out). The yellow line shows those data being read out
from the Output FIFO by the NI DAQ card at 20 MHz to the PC memory. The
read and write clock are running at 135 MHz, which is close to the limit
for FPIX chip. We need to wait for the FPHX chip to test the readout
chip operation and data writing at 200 MHz, but for reading, we've
reached the design goal.

The FEM channel was prototyped on an ML402 Veirtex-4 evaluation board
and only a single FPIX chip was used for testing. The prototype included
imbedded deserializer and slow control parts, which will not be present
in the final FEM core. In order to run the design, a "fake" trigger
signal was created from the "fast OR" of all the pixels analog signals
(so called GOT_HIT signal). The GOT_HIT was delayed by a specified
number of clocks to simulate PHENIX Level-1 decision latency. The data
was requested for read from a calculated Beam Clock bucket. One can see
on Figure 47 that we read the data out of the array to the output buffer
only if the readout delay is correctly adjusted. Whenever, we are off,
the data does not show on the output. One can also see that data does
not stay in the bucket forever, but has a 64 Beam Clock expiration time
(otherwise we would observe random hits, written way back in time, while
reading from an incorrect bucket). The FEM design functioned reliably at
up to 150 MHz for writing and 300 MHz for reading.

![](media/image45.png){width="4.3283464566929135in"
height="3.245275590551181in"}

![](media/image46.png){width="4.202755905511811in"
height="3.1535433070866143in"}

[]{#__RefHeading___Toc196886618 .anchor}Figure 47 FEM prototype testing
results: Reading back from the correct beam clock bucket (top) and from
an incorrect bucket (bottom)

Figure 48 shows the results of full calibration scan of 8 FPIX chip
module performed with the ROC prototype. During the scan, fully
controlled from slow control FPGA, one pixel is being enabled on the
chip and then we send 100 pulses of fixed amplitude, gradually
increasing the amplitude in 64 steps. Once the pixel is tested, the next
one turns on, etc. As a result, we count the number of recorded hits,
with the given amplitude. One can clearly see the threshold behavior of
hit detection probability. The results clearly indicate that 100% of the
signal propagates through the design and the signal is being transmitted
without errors.

![](media/image47.png){width="5.0625in" height="3.796527777777778in"}

![](media/image48.png){width="2.8125in" height="1.9076388888888889in"}

[]{#__RefHeading___Toc196886619 .anchor}Figure 48 Threshold scan for an
8-chiop FPIX module using the ROC channel prototype. Threshold and noise
distribution of each pixel (top) and fit to the turn-on curve for on of
the pixels (bottom) are shown.

## Radiation Environment and Component Selection

The evaluation of the FPGA technology available for use on the FVTX
Read-out Controller (ROC) primarily considers the effects of the
radiation on the performance of the overall system. Additional
considerations included I/O configurations, serial communication
capabilities and reconfiguration of the device within the system. The
choice of technology is primarily the choice of configuration memory
technology as logic implementation and density do not really impact our
application.

In consideration of all factors the Actel ProASIC 3 Flash based FPGA
provides the best solution to the FVTX ROC FPGA requirements because it
is immune to radiation problems, it provides the I/O capabilities
required, it allows reprogrammability.

# Mechanical Structure and Cooling

The mechanical structures and cooling are part of the integrated design
of the barrel and FTVX endcaps. The iFVTX uses one half cage designed
for the FVTX. The majority of the support structure has been designed as
part of the barrel effort. Kinetic flexture mounts are use to precisely
place the detector stations in the half cage assembly.

A conceptual design of the silicon vertex detector was commissioned by
the LANL group

to HYTEC, Inc. HYTEC provided the mechanical designs for the ATLAS
silicon pixel group and has 15 years of design experience with silicon
vertex detectors. For PHENIX they have also designed the station-1 muon
detectors and the station-2 spider and they also did the finite element
analysis for the station-3 octants. The VTX/FVTX mechanical conceptual
design was completed and a report written.

<http://p25ext.lanl.gov/~hubert/phenix/silicon/HTN-111003-0001.pdf>

In September 2005, the original concept was reanalyzed to incorporate
changes that have occurred over the intervening 2-½ years, a report was
issued in October 2005.

<http://pvd.chm.bnl.gov/twiki/pub/VTX/HYTEC/HTN-111004-0001.pdf>

## Structural Support

The selection of materials for the support structure is based upon the
above criteria where the most important material properties are low
radiation length, low density, high stiffness, and availability. Out of
three candidates (i) beryllium, (ii) graphite fiber reinforced plastic
(GFRP), and (iii) Carbon-Carbon, GFRP was chosen for the study because
of its wide availability. It works well in sandwich composites, and has
good radiation length and strength properties.

Structural Analysis

The structural analysis includes two studies, a first study using finite
element analysis models and the resulting modal frequencies to look at
dynamic stiffness of tracker concepts and a second study to look at the
static stiffness with mass loaded structures. The lower modal frequency
limit is set at 70 Hz on a fully loaded structure so that the natural
frequencies due to environmental conditions such as pumps, traffic, etc.
do not couple into the structure and cause instabilities greater than 25
microns.

## iFVTX Stations

The forward regions consist of 4 stations constructed of 8-chip of
modules oriented normal to the beam pipe. Conceptually, we have chosen a
PCB 'picture frame' structure that holds the TPG structure for mounting
and cooling of the modules.

![](media/image49.wmf){width="5.99375in" height="2.8895833333333334in"}

[]{#_Ref159134842 .anchor}

Figure 49 CAD drawing of a station, the cooling tube on the FPG is
clearly visible; the actual modules are on the inside of the station
because the two planes, composing the station, face each other.

The CAD drawing of a station depicting its cooling lines is shown in
Figure 49. The FPIX chip has a heat load of about 0.5 Watt per hybrid so
the total for each plane is 40 W. In comparison to the barrel this is a
very small heat load and greatly simplifies the removal of heat. The
support/cooling panel structure consists of TGP with cooling tubes
mounted on 3 of the outer edges. Heat generated by the hybrids is
conducted through the graphite to the outer edges cooling tubes. The
difference in CTE between the station panels and the support cage is
absorbed by mounting each station on three flexures. The flexures are
arranged so that the center of expansion (zero motion point) is the
center of the detector plane. The flexures are machined as one piece
from G10 stock.

## FEA Calculations for modules

In order to understand the thermal behavior a series of FEA calculations
was completed. We addressed the thermal gradients, the stress on bump
bonds due to flexing and the worst case scenario of thermal stress
induced under power failure and the z-displacement. The module
dimensions are as shown in Figure 50.

![](media/image50.jpeg){width="4.879861111111111in"
height="3.654166666666667in"}

[]{#__RefHeading___Toc196886621 .anchor}Figure 50 Module dimensions in
the FEA analysis.

Figure 51 shows the temperature gradients for nominal running at a
cooling temperature of 7 degrees C. This temperature was chosen to
minimize the flex of the module due to ct mismatch by stetting the
operating point of the system such, that the HDI is at assembly
temperature. It results in a maximum temperature of the module, in the
center, of 29 degrees C. These results in a maximal stress for the bump
bonds of 0.9 Mpa, which is about 2 percent of the maximum tensile
stress, see Figure 52.

![](media/image51.jpeg){width="5.129861111111111in"
height="3.8472222222222223in"}

[]{#__RefHeading___Toc196886622 .anchor}Figure 51 Results of the thermal
FEA. With a coolant temperature of 7 C the gradient between TPG and
Sensor is about 8.3 C.

![](media/image52.jpeg){width="4.879861111111111in"
height="3.6597222222222223in"}

[]{#__RefHeading___Toc196886623 .anchor}Figure 52 FEA stress plot for
the bump bond layer at nominal operating temperature. The maximum stress
is \~ 2 % if the tensile yield.

The case of the highest stress on bump bond is occurring in the scenario
in which there is a power outage, i.e. no head load of the chips, but
continuing cooling. The FEA calculations show that in this situation
there is a stress of about 8.2 Mpa maximum at the bump bonds closest to
the chip edge, still only about 20 percent of the maximum tensile stress
and therefore save.

![](media/image53.jpeg){width="4.539583333333334in"
height="3.404861111111111in"}

[]{#__RefHeading___Toc196886624 .anchor}Figure 53 FEA stress results for
the case of a LV power outage while cooling is in operation. The maximum
stress is \~ 19 % of the tensile yield.

The displacement (or bow) of a module under normal operating conditions
is about 4 microns in z (beam) direction, see Figure 54.

![](media/image54.jpeg){width="3.709722222222222in"
height="2.783333333333333in"}

[]{#__RefHeading___Toc196886625 .anchor}Figure 54 FEA results for the
deflection of module during normal operation. The maximum displacement
in the Z direction is only \~ 4 microns.

## FEA Calculations of the support cage 

A finite element model of the support cage was built to calculate the
stiffness of the support cage with the iFVTX detector stations
installed. The support cage was modeled using plate elements that
simulate the stiffness and mass of the laminate. The detector stations
were modeled as lumped masses. The mass of a detector station was
estimated as 500g, and another 500g was added to each station to account
for the portion of the cabling that would be supported by each station.
The first station with cabling was assumed to be 600g. The flexures were
modeled as spring elements using equivalent stiffness generated from
Cosmosworks models of the individual flexures.

![](media/image55.jpeg){width="5.9840277777777775in"
height="4.604166666666667in"}

[]{#_Ref184526078 .anchor}

Figure 55 iFVTX distortion analysis, details see main text.

The static deflections of each station were calculated at the center
point of the detector area for a 1 G gravity load, and were found to be
relatively small as compared to the desired positional stability of 30
μm or better. shows the deformations of the support cage due to gravity
sag. The first station has a deformation of 6.3 μm, the other three
stations sag around 4 μm.

![](media/image56.jpeg){width="5.9840277777777775in"
height="4.604166666666667in"}

[]{#__RefHeading___Toc196886627 .anchor}Figure 56 iFVTX modal analysis;
the first modal frequency is at 156 Hz.

The natural frequency of the detector was calculated, assuming the
stations behaved as rigid bodies. The first mode is a drum shaped mode
with most of the strain energy in station 1 as shown in Figure 56. The
frequency for this mode is 156 Hz. Based on vibration measurements taken
from the PHENIX experiment (see Vibration Test Report HTN-111008-0002)
this should be stiff enough to prevent any significant deformations due
to the vibration environment.

## Analysis of the Full VTX/FVTX Structure

Finite element analysis of the combined VTX and iFTVX has not been
performed. However, the iFVTX has been designed to obey the space
restrictions imposed on the FVTX and it has less masse. The following
VTX/FVTX analysis should be valid for the VTX/iFTVX.

Since the VTX design effort has been proceeding and construction is now
beginning, it was important for the FVTX to keep pace with its design so
that we could insure that the two projects could coexist in the same
enclosure without interference. A complete mechanical study has been
completed. The results of the FEA of the complete structure demonstrate
that the FVTX introduces no change in the VTX first mode and does not
change the VTX deformation. The FEM model is shown in Figure 57

![](media/image57.png){width="4.25in" height="3.245833333333333in"}

[]{#__RefHeading___Toc196886628 .anchor}Figure 57 FEA model of the
combined VTX and FVTX. The first modal frequency is 38.5 Hz

A full system level analysis has also been finished for the combined
system. The model is shown in Figure 58.

![](media/image58.png){width="2.4277777777777776in"
height="3.497916666666667in"}

[]{#__RefHeading___Toc196886629 .anchor}Figure 58 Full system FEA; the
first frequency mode is 24 Hz.

## iFTVX Analysis Summary

######## The conceptual design studies revealed the following: {#the-conceptual-design-studies-revealed-the-following .unnumbered}

######## Single phase cooling is well suited to the iFVTX. 

-   One cooling tube is used per plane; the planes are operated in
    parallel.

-   3mm PEEK cooling tubes and panel thickness are adequate.

-   The iFVTX and VTX coexist in the enclosure without interference.

## Assembly and Integration 

### Assembly

We can categorize the assembly into a several distinct categories: flip
chip assembly, module & wire bonding, plane & wire bonding, station,
cage, electronics.

#### Flip Chip Assembly

After the QA for the readout chips and the silicon sensors is completed,
they are flip chip assembled by the vendor VTT in Finland. Each sensor
will carry 8 bump bonded read out chips FPX2.1. The yield achieved in
the pre-production run and the production so far is close to 100
percent. In the following this assembly will be call hybrid.

#### Module Production and Wire Bonding

Figure 59 show the assembly jig for the module production. In order to
produce a detector module the 8-chip hybrid needs to be glued to the HDI
after the passive components have been mounted. The assembly jig is
designed to use a vacuum to hold the HDI in place while the hybrid is
placed. The alignment is done with an optical alignment system utilizing
marks on both the HDI and the silicon sensor. We achieve a precision of
about 4 microns. The next step is placing the module on a port card
which is used as carrier and test bed. The ends of the HDI are glued to
the port card. After that the port card is transferred to Silicon
Detector Facility at FNAL, where the wire bonding is performed. Four
wire bonding tasks have to be completed, the control lines of the
readout chips have to be wire bonded to the HDI, the chip ids have to be
set, the sensor bias has to be connected and then the HDI ends are wire
bonded to connect to the port card. After that the port card is placed
in a plastic box for further QA.

![](media/image59.png){width="4.590944881889763in"
height="3.416535433070866in"}

[]{#__RefHeading___Toc196886630 .anchor}Figure 59 CAD drawing of the
mounting jig for the module assembly. The HDI is held with a vacuum jig.

#### Plane Production and Wire Bonding

In order to produce a readout plane the printed circuit board (PCB)
needs to be machined, to allow for the mounting of the TPG cooling plate
and the cooling lines. After completion of the cooling system the
passive and active components and connectors are mounted on the PCB. The
modules are then transferred from their individual port cards by cutting
the tabs near the ends of the HDIs and then using the assembly jig,
depicted in Figure 60, is used to precisely mount the modules with the
aid of an optical alignment system. After placing the modules the HDI
end taps are wire bonded to the pixel plane traces. We are considering
encapsulating the wire bonds between the HDI and the PCB in order to
protect them. Current experience with testing transparent compounds is
very promising.

![](media/image60.png){width="2.7333333333333334in" height="3.25in"}

[]{#__RefHeading___Toc196886631 .anchor}Figure 60 Pixel plane with 10
modules on the mounting jig (in red)

#### Station Assembly

Two planes will then be assembled into a station by mounting the
stiffener bars and using precision pins to bring the two TPG planes into
a known position better that 25 micron accuracy. Finally the flexures
are attached to allow for mounting into the cage. After that the station
assembly will be optically surveyed to accurately locate the sensors to
\~10 micron.

#### Cage

The assembly of the stations into the cage is started at the largest z
location. The stations have three tabs at the outer boundary for
attachment to the cage assembly. The general procedure for the cage
assembly will be to attach the stations in the order 4,3,2 and
finally 1. As each station is mounted the cable are routed via the
strain reliefs to the rear of the cage and fixed in their respective
cable mounts. It has not been determined whether the cage and back plate
will be assembled as a unit (preferred) and then inserted into the VTX
enclosure or if the cage is first inserted into the VTX enclosure and
then the back plate is attached.

### Integration 

Integration involves coordinating the mechanical and electronic
activities within the iFVTX/FVTX project and across subsystem boundaries
with the VTX, NCC, and the rest of PHENIX. We have put in place
integration engineers who are responsible for ensuring that the
iFTVX/FVTX integrates seamlessly into the VTX and other subsystems. The
two integration engineers, Eric Mannel and Walt Sondheim, have identical
responsibilities in the VTX and the FVTX projects. In addition, Robert
Pak is working with both projects as the responsible person for
infrastructure and mechanics and provides the interface to the BNL
engineering team and the external subsystems.

#### Mechanical Integration

The mechanical integration has been an ongoing task for the iFTVX/FVTX
since FY2006. Two concurrent contracts (iFTVX/FVTX) with HYTEC ensured
that while the FVYX was designed, the iFTVX was conforming to the
requirements set for the FVTX. The FVTX design has matured to the point
where we have been able to do the thermal and finite element analysis of
the entire VTX-FVTX system to ensure that the two projects coexist
without interference. The iFTVX is housed in the FVTX support structure.

#### Electronic Integration

Electrical Integration:

The tight space constraints of the VTX enclosure and the close proximity
of the electronics for the VTX detector requires that close attention be
paid to the electrical integration of the detector. To facilitate this,
the project electrical engineer Eric Mannel will develop a set of plans,
with the assistance of the subsystem managers from both the VTX and FVTX
projects, along with members of the PHENIX experimental team responsible
for overall electronics at PHENIX. The integration can be broken into
three separate sub-tasks; power and ground, systems control, and
electrical design review.

Power and Ground:

The power for the iFVTX will be distributed via the ROC cards. The input
to that card will be standard PHENIX LV supplies which allow the
measurement of voltage and current and have a slow control
infrastructure in place. Each module has a regulator for VDDD (2.5 V)
and VDDA (2.3V) on the PCB plane, the current plan foresees routing
power to each of those regulators separately to allow for a sequenced
power-on to ensure stable initialization of the detector. A total of 68
lines are required for VDDA and VDDD respectively. The connector count
is rather modest; each ROC slice will have two sets of 8 Hirose 20
pin-connectors for the power distribution. One set outside the enclosure
for input and one set inside for the actual distribution. The voltages
required after IR losses are 2.8 V for VDDD and 2.6 V for VDDA.

The grounding plan for the VTX and iFVTX projects requires that the
three sub detectors, VTX pixels, VTX stripixels, and iFVTX be
electrically isolated from each other to minimize crosstalk and noise.
Each of the three systems will provide the means for all grounds to be
tied together at a single point, most likely at the power supplies. It
is envisioned that the detectors will have several independent grounds
within the detector - digital, analog, and shield - which will be
specific to each of the detectors and requirements of the electronics
chosen in the design. During the design phase of the electrical
components, each detector system needs to insure that their grounding
plans are appropriate and provide the flexibility to connect or isolate
grounds at different points to allow for studies of crosstalk and noise
issues, if necessary.

Current discussion include how to efficiently ground carbon structures,
prior solutions at FNAL indicate that one best incorporates a cupper
layer in the carbon assembly which is the grounded. The grounding scheme
for the stations is illustrated in Figure 61. All supplies are floating.
The figure shows that digital, analog and sensor grounds are separated
throughout and only connected to the pixel plane ground at the front end
of the system. The chassis ground will probably connected to the cage
and the planes directly.

![](media/image61.jpeg){width="5.9944444444444445in"
height="4.631944444444445in"}

[]{#__RefHeading___Toc196886632 .anchor}Figure 61 Grounding schematic
for the iFVTX, all supplies are floating. The sensor, digital and analog
ground are only connected together at the front end pixel planes. All
power lines have PTC fuses.

Systems Control and PHENIX Integration:

Overall electrical integration into PHENIX requires the coordination of
the VTX and iFVTX and FVTX design teams and various teams from PHENIX
responsible for the overall operations of PHENIX. The project electrical
engineer will be responsible for coordinating with the electrical group
responsible for power and ground within PHENIX, the DAQ group
responsible for data readout of all PHENIX detectors, and the Online
Computing Group (ONC) that oversees the slow control and monitoring
systems. The project engineer will work with each of these groups to
ensure that when the FVTX detector is ready for installation, the
detector can be quickly integrated into the PHENIX DAQ and Control
systems.

## Q/A procedures

The iFVTX is a complex assembly of silicon sensors, electronics,
mechanical support and thermal management components. The individual
pieces that comprise the final complete assembly will be designed,
tested and produced at different stages of the project. The Q/A plan
will contain a detailed set of test procedures, along with specific
pass/fail criteria, to guide the various stages of the project from
prototype to Q/A test, from Q/A test to production, and from production
to Q/A acceptance for assembly.

### Silicon Sensor Q/A

The acceptance criteria given to the vendor CIS for each sensor are
included in the appendix.

All the acceptance criteria tests that the vendor performs have been
repeated at UNM. The sensor depletion voltage and breakdown voltage has
been measured on each individual sensor. The overall sensor leakage
current/voltage characteristic has also been measured for each sensor.

### FPIX Readout Chip Q/A

The Q/A of the readout chips started with basic vendor test. After that
we performed extensive automated probe station test before the dicing of
the wafers. These tests included the measurement of the analog and
digital current, writing and reading the control register and a inject
scan of the chips. The results are stored in a data base and the vendor
for the flip chip assembly was given 'known good die' tables to select
the right chips for module assembly.

### High Density Interconnect (HDI)

The Dyconex produced HDIs are tested by the vendor with a flying probe
test. This has been a sufficient Q/A to ensure their quality prior to
assembling the modules. The conclusive HDI test is done by testing the
hybrid on the port card.

### TPG Support/Heat Spreader

The production of the 8 TPG boards will be done at FNAL and will include
a measure of their planarity.

# Infrastructure Requirements from PHENIX

![](media/image2.jpeg){width="5.992361111111111in"
height="5.243055555555555in"}

[]{#__RefHeading___Toc196886633 .anchor}Figure 62 CAD drawing of the
four stations mounted in the cage developed for the FVTX. The cooling
lines, the cables and the strain relieve is show.

### Detector layout in cage

We repeat here Figure 41, now labeled Figure 62, to summarize the
layout. The iFVTX is using a half cage identical to the FVTX half cage
and the four stations are mounted on identical tabs. The mounting of the
half cage to the VTX cage and the support structure is identical to the
FVTX scheme.

### Cable plant inside enclosure (size, location)

.

Figure 61 shows the connection to and from the ROC cards (4 of them will
be used) for the iFVTX.

There are 6 signal cables per plane with 50 0.025'' twisted pair cables
(tray rated), they connect the planes to the ROC card, they are depicted
in blue in Figure 62. The cables are strain relieved via clamps,
depicted in yellow. There is a bundle above and below the beam pipe
respectively, each holding a total of 24 cables.

There are 8+8 cable bundles (VDDA and VDDD \~ 3V, 0.25 A) of tray rated
22 gauge cables (one pair per plane). Each bundle uses a Hirose
connector with 20 pins to connect to the plane and ROC card
respectively.    

There are 8 tray rated HV cables with SMA connectors for the Bias (\<125
V) that connect from the planes to the ROC cards.

There are 8 cables (one per plane) with 10 .025\" twisted pair cables
(tray rated), flat and shielded to the ROC cards (2 per card), Hirose
connectors. The signal is generated on the ROC cards.

### Big wheel space, board configuration

There are 4 ROC cards (45 degree wide) on the big wheel. The FPGA
section of these boards is identical to the FVTX, the connector section
is modified for the bigger 3M connectors.

Big wheel connections to outside world (outside enclosure seal)

The connections from the big wheel to the racks on top of the magnet are
discussed in the next section, all low voltage and hv connections for
the planes are routed straight through the ROC card and therefore
through the enclosure. The ROC cards require 8 LV supply lines each, see
Figure 61. Each ROC card requires 2 lines of 5V 1 A max, one line 3.3 V
4 A max, and 5 lines for the FPGAs with 4 A max. The data will be sent
from the ROC via two 12x fiber bundles of which 8 fibers will be used.

## Cable Plant from IR, i.e. the Big Wheel to Racks

### LV bundle size

There is a total of 160 low voltage lines for the planes plus 32 lines
of LV for the four ROC cards. They will be bundled in groups of 10 to
match the LV supplies, there will be 20 bundles of tray rated 16 gauge
wire (because of the greater length).

### HV bundle size

There will be on HV bundle of 8 shielded, tray rated HV cables going to
the HV supplies.

### Fiber bundle size

There will be a total of eight 12x fiber bundles connecting the ROCs
with the fiber patch panel on the magnet. Each fiber bundle has a
diameter of approximately 3 mm. In addition there will be four 2x fibers
and two 1x fibers for slow control I./O, beam clock and sync start.

### Cable tray needs

The above mentioned connections from the Big Wheel require the use of a
cable tray from the Big Wheel up to the rack space on the magnet. The
FVTX trays will suffice.

## PHENIX Hall Rack Requirements

### LV crate specification 

### 2 PHENIX LV crates will be required with 9 modules each for the planes. These will deliver 3.2 V digital and 3.0 V analog for 68 channels. This requirement is iFVTX specific.  {#phenix-lv-crates-will-be-required-with-9-modules-each-for-the-planes.-these-will-deliver-3.2-v-digital-and-3.0-v-analog-for-68-channels.-this-requirement-is-ifvtx-specific. .unnumbered}

> The 4 ROC cards will require 4 modules in an additional crate, this
> requirement is a subset of the FVTX requirement.

### HV crate specification 

The IFTV will require for the bias only one bias module (negative 8
channel \<125vV) in a rack that is designated for VTX/FVTX.

### Fiber patch panel specification

8 connectors for a 12x fiber patch panel will be required, this is a
subset of the FVTX requirement of 24 connectors.

Four 2x fibers patch panels and two 1x panels are required for slow
control I/O, beam clock and sync start.

### Other?

## Cooling System Requirements

### Wattage that must be removed from within the enclosure, number and size of cooling lines that must be provided to do this, specify volume/rate of coolant.

The iFVTX requires a cooling **power** of 300 W at 7 C plus 300 W for
the ROC cards.

The cooling system for the three proposed upgrade detectors that will be
in the PHENIX vertex region will be cooled off the same system. This
system will have the capacity to cool the four layers of silicon
detectors in the VTX barrel, two pixel layers followed by two
strip-pixel layers -- which need to operate at zero degrees Centigrade
in order to prevent increase in leakage current. This system will also
be sized to cool the two forward vertex detector systems (FVTX). Each of
the forward vertex detectors has four double sided planes of silicon
mini-strip detectors. In place of the FVTX, during the initial year of
operation -- the cooling system will provide coolant to the iFVTX
detector. This detector will only occupy one half of one end region and
have a heat load of 40.0 watts. It will be operated at room temperature
or slightly below.

The coolant used, in this closed loop system, is 3M NOVEC 7000. It has
similar heat transfer properties as C5F12, which has been used in
several collider detector vertex systems.

## PHENIX Counting House Rack Requirements

### FEM crate specification

The iFVTX requires one 6U VME create for 8 FEM boards and one FEM
interface board.

### Number of DCMs required

The iFVTX requires one DCM II board, assuming it has 8 DCM channels.

### Slow control interface requirements

The iFVTX requires one 100 Mb Ethernet node for slow control

## Technician Needs for Infrastructure and Installation

### Cable tray installation

These will be installed for the FVTX, see needs there.

### Fibers run from CH to IR

These will be installed for the FVTX, see needs there.

### Wiring up of rack (need to put in rack monitoring, power to each crate...)

These will be installed for the FVTX, see needs there.

### Steve Boose for LV system (?)

These will be installed for the FVTX, see needs there.

### Cooling system support (plumbing and integration to PHENIX monitoring, etc.)

This will be installed for the VTX/FVTX, see needs there.

### Monitoring help from Frank T/ John H

This is under discussion.

## Detector installation

In discussion with W.Sondheim we anticipate 40 hours of tech time
needed.

# Schedule, Responsibilities

## Schedule

The LDRD grant started in FY06 and ends in FY08 with the delivery of 4
detector stations, completely tested and internally surveyed by 9/30/08.
The installation of the iFVTX is coupled to the VTX and not driven by
the project, see below. The completed iFVTX will be stored at BNL until
installation into the IR.

Since the iFVTX is the prototype for the FVTX and will be added to the
existing barrel vertex detector, VTX, much of the needed infrastructure,
cooling, enclosure, cable routing, installation procedures, etc. will
already have been done and be in place.

The current installation schedule for the VTX pixel planes shows a
milestone in Summer 09 for the infrastructure completion and
installation in the IR , requiring 10 days. One week of a tech for
installation and one week of survey. The iFVTX will add approximately 30
percent.

Institutional Responsibilities

Los Alamos National Laboratory

LANL coordinate work to design and procure the silicon sensors and
readout chips, work with FNAL on the construction of the stations,
development of the interface to PHENIX DAQ, and on the simulation effort
with NMSU. Los Alamos is currently leading the mechanical engineering
and the integration effort for the barrel detector, and will continue
those efforts for the FVTX and iFVTX.

Columbia University

Columbia is responsible for the overall electronic integration.

New Mexico State University

NMSU will work on comprehensive simulations for the iFVTX effort and
participate in the QA of hybrids and modules.

University of New Mexico

UNM has experience in testing, Q/A and has laboratory for
characterization of sensors. They will assist with sensor and module QA
and testing.

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