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**SVX II Silicon Strip Detector Upgrade Project**

**BERT:**

**Bit Error Rate Tester**

22 February, 1995

Author

D. Husby

Document \# ESE-SVX-950222

**Introduction**

The BERT module is a general purpose pattern generator and checker for
testing high speed data links. It is designed specifically for testing
the DOIM (Dense Optical Interconnect Module) and the G-Link, but it can
be easily adapted for other uses.

The BERT is controlled by a host PC and uses adapter cards (XMIT and
RCV) that are specific for each type of link.

## 

## OPERATION

The BERT consists of an independent transmitter and receiver, each with
its own pattern buffer. During normal operation, data words from the
transmit pattern buffer are sent through the transmit port (X-Port),
through the link under test, and received via the R-Port. The receiver
compares each word against its own pattern buffer and, if it finds a
discrepancy, halts and allows the PC-Host to readout the errant
pattern\'s address and data.

**Other features:**

**Statistics Mode**: In this mode, errors are counted internally and do
not require host intervention. Error count and cycle count can be read
out by the host.

**Remote Mode**: In this mode, two BERTs can be used to test links whose
ends may not be in the same room. One BERT is used as a transmitter, the
other as a receiver. The receiver can control the transmitter via a
single twisted-pair cable.

**Loopback:** A loopback cable will allow the BERT to be tested without
a data link present.

**[Hardware Installation]{.underline}**

The BERT comes packaged with a power supply, PC interface card, and
cable. The PC interface uses I/O port addresses from 310h to 317h. The
software expects the card to be at this location and will not work
otherwise.

There is an 8-pin jumper block on the BERT card that configures the
handshake signals. Normally, a single BERT will be used in the LOCAL
configuration. The Loopback mode is used when a single BERT is used with
a cable between X-Port and R-Port.

When two BERTs are used for remote tests, one should be configured as a
transmitter, and the other as a receiver. The remote configurations
require two BERTs to be connected via the Auxilliary connector.

**Software**

The software requires a minimal MS-DOS system with 512K of memory and a
color display. The interface program, BERT.EXE, can be run from a floppy
disk or can be copied to the hard disk. The interface program controls,
configures, and monitors the BERT. The main display page (right) shows
the current status and other useful information:

**Keys**: The following keys have special meaning:

F1 Print a short help message.

F2 List all .BIT and .PAT files in the current directory.

F3 Print a histogram of errors.

F4 Print a histogram of the current Rpattern buffer.

F5-F8 Set the BERT state.

Alt-X Exit the program.

Scroll through configuration options.

SPACE Toggle configuration options.

ESC Cancel configuration option.

**Running a test:**

Start Bert.exe:

Make sure the BERT is connected properly and then run the bert.exe
program. The program should load the xilinx chip software, do a simple
sanity check, and enter the command mode.

Set the link type:

Use the cursor keys to scroll to the Link type configuration line.

Use the space bar to select the desired link type. Use the ENTER key to
confirm the selection. A new Xilinx file will be loaded and the data
width field will be set appropriately.

Set the clock speed:

Using the up/down arrow keys, scroll till the frequency is highlighted.
Enter the desired test frequency. Note that the BERT allows clock
frequencies from 16MHz to 63.5MHz. The BERT is design to run at a
maximum of 60mhz under worst-case conditions. Higher frequencies may
cause errors. Also, some links may not run at slower speeds. The DOIM,
for example, is specified by Hitachi to run no slower than 50MHz.

Load a pattern file:

Press the up arrow key until the transmit pattern file name (Xpattern)
is highlighted. Enter the name of a pattern file and press ENTER. To
view a list of available files, press F2. When the pattern name is
entered, press the F8 key to load it.

Run the test:

Press the F6 key to start the test.

# 

# Pattern File Format

#  A pattern file must be exactly 65536 longwords (256K bytes). The lower 20 bits of each longword are loaded into the pattern buffers. For the DOIM, only bits 1-9 are used. Bit 0 and bits 10-19 are masked off.

Special consideration must be made for patterns that are loaded for
testing the DOIM. Since the DOIM has no DATA-AVAILABLE signal, it uses
bit 1 in the data word to signal the start of the test. This means that
the word at address 0 must have Bit1=0 and address 1 must have Bit1=1.

# INTERFACE SPECIFICATIONS

## Link Ports

The link to be tested is connected between the X-Port (Transmit port)
and R-Port (Receive port). These are general-purpose 20-bit parallel
ports as shown in the pinout. Signals are differential 10K ECL. The
standard 50-pin connectors are intended to be used with adapter cards
that are specific to each link being tested. The ideal adapter card will
make it look like there is a solid cable from X-port to R-port. In
addition to the 20 data bits, there are 5 control signals:

**[Signal X-port R-Port Function]{.underline}**

STB Output Input Data rate clock. Some links require that this is a
constant clock source qualified by DAV. Others prefer that the clock
transitions only for valid data words. The Xilinx chip may have to be
customized for some links. See **Timing**.

DAV\* Output Input This active-low signal indicates that data is valid
for the current STB.

Fault\* Input Input This active-low signal indicates that the link
hardware has detected a fault. It is intended to be connected to the
LOCKED pin on the G-link transmitter and the STAT1 pin on the G-link
receiver.

SYNC\* Output Input This is used for PLL synchronization. For the
X-Port, a low on this signal indicates that the transmitter should send
sync frames. It is intended to be connected to the FF signal on the
G-link transmitter. For the R-port, a low on this signal indicates that
the receiver is trying to lock its PLL. It is intended to be connected
to the G-link STAT0 pin.

Reset\* Output Output The BERT drives this low to reset the transmitter
and receiver. For the R-Port, this is connected to the Xfault signal so
that the receiver is reset when the transmitter asserts fault.

### 

### DOIM adapter cards

The DOIM (Dense Optical Interconnect Module) is a simple synchronous
10-bit parallel optical link. Bit 0 is a strobe signal and bits 1-9 are
data. Bits D1-D9 and the STB are sent directly from the BERT (through
ECL buffers) to the DOIM. On the receiver, bit D0 is inverted before
being driven on the STB line (see timing). Note that Fault\* is tied
high on both cards. On the receiver, data bit D1 is inverted and driven
out as DAV\*. The first high-to-low transition on DAV is used by the
BERT to start its own internal receiver. This means that any data
pattern used with the DOIM must have D1=0 (D1=0 =\> DAV\*=1) at address
0 and D1=1 at address 1.

Note from the timing diagram that the skew between STB and the other
outputs is about 1ns.

### 

### 

### 

###  

### G-link adapter card

The G-link is a serial optical link that converts 20-bit words into a
serial bit stream. The transmitter requires a constant data-rate clock
on the STB input while data words are validated by the DAV\* signal..
Several signals are used to establish and maintain synchronization
between the transmitter and receiver.

**Handshake**

When a test starts, the BERT releases XReset and allows the transmitter
to run. When the transmitter has locked its PLL on to STB, it releases
XFault. XFault is echoed back to release RReset and the receiver begins
its synchronization. When the receiver is ready, it releases Rfault
which is echoed back as Xsync which tells the transmitter to begin
sending FF1 frames. When the receiver receives FF1s, it asserts RSync.
When BERT detects RSync, it starts sending test data.

## Host Interface

The host PC controls the BERT via a PDMA-16 parallel port interface card
(Available from CyberResearch). In addition to 16 data lines, the host
interface uses 4 control signals to control the BERT:

.

**DIR_A** Direction of lower 8 bits (A-Bus) (1 =\> Write to BERT)

**DIR_B** Direction of upper 8 bits (B-Bus) (0 =\> Read from BERT)

**STB** Data strobe (Aux-1 on PDMA card).

**Reset\*** Reset (Aux-2 on PDMA card)

In order to minimize noise on the cable between the PC and the BERT, the
signals have been re-arranged slightly. An adapter converts the PDMA
connector pinout to the BERT connector pinout.

**Access Protocol**

Each transfer between the BERT and the Host consists of an 8-bit
register number and a 24-bit data word. Each transfer requires a
positive and negative transition on the strobe. The register address and
upper byte are transferred on the rising STB. The lower two bytes are
transferred on the falling edge. State changes inside the BERT do not
take place until the falling STB.

**[Registers]{.underline}**

There are 9 registers.

The **XPattern** and **RPattern** registers are only available when the
BERT is in the LOAD state. Each access to one of these registers
transfers a data word to or from the pattern buffer and increments the
corresponding address pointer. The address pointers are 16 bits and wrap
around after 64K transfers. They get reset when the BERT enters the IDLE
state. The pointer to the receive pattern buffer can be read via
**Erraddr**.

When an error occurs, the BERT enters the HALT state and increments its
error counter. The word that caused the error is available via
**Errword** and the receive pattern pointer is available via
**Erraddr**. The error counter can be read via **N_Errs**.

Each time the BERT cycles through its pattern buffer, it increments a
cycle counter. The value of this counter can be read via **N_Cycles**.
Both the cycle counter and error counter are 16 bits wide and wrap to 0.
They can be cleared by setting bit 19 of the control word.

## 

##  The BERT can be set to one of four states via the Control register. Only one of bits 23:20 should be set at a time and the BERT must be set to IDLE before it can enter the RUN or LOAD state: 

## Auxilliary Connector

The auxilliary connector is used for remote operation and triggering. It
has 3 signals:

TRIG Goes low for one clock cycle when an error is detected. This is
available as a standard TTL level signal or as a differential RS485
output.

HALT_IN Stops the transmitter and resets its address pointers. This is
an RS485 input.

HALT_OUT Goes high when an error is detected and remains high until the
receiver is re-started. This is an RS485 output.

## Logic Analyzer Ports

There are three ports for connecting directly to Hewlett Packard logic
analyzer pods. Pin 3 is the pod clock and pins 4-19 are the data bits.
The RD bus contains data that is coming from the receive port. RSTB is
the strobe from the receive port. RCLK is the internal clock signal
generated from RSTB. RA is the current address of the receive pattern
buffer.

## 

## Power Connector

# Power is supplied to the BERT and its adapter cards via 4-pin molex connectors.