**HET Command List**

**07/23/03**

**Command Register Bit Assignments (Rick Cook) for PHASIC Chip**

**category PHA# bit names \# of bits**

Scope-mux n/a scopesel7,\...,0, scope-enable 9

Preout-mux n/a presel3,2,1,0, preout-enable 5

Test pulse/feedback PHA0,\...,15 test-enable, testsel3,2,1,0,
fbsel3,2,1,0 9\*16

Input resistance, etc. PHA15,\...,0 rdgsel2,1,0, indac9,\...,0 13\*16

Threshold setting PHA0H,\...,15L ioff9,\...,0 10\*32

PHA control PHA15,\...,0 hg-adc-en, lg-adc-en, verbose, power-on 4\*16

rndn-gor-0 n/a enable-rndn15L,\...,enable-rndn0H 32

rndn-gor-1 n/a enable-rndn15L,\...,enable-rndn0H 32

rndn-gor-2 n/a enable-rndn15L,\...,enable-rndn0H 32

Total \# of bits: 846

**HET Ground Commands for PHASIC Chip Command Register**

  ------------- -------- ----------------- --------- -------- -----------------------------------
  **Command**   **Chip   **PHA/rndn-or**   **HEX     **\# of  **Description**
                \#**                       Bytes**   bits**   

                                                              

  scopesel      0-1                        xxx       9        scopesel7,\...,0, scope-enable

  presel        0-1                        xx        5        presel3,2,1,0, preout-enable

  tpfbsel       0-1      0-15              xxx       9        test-enable, testsel3,2,1,0,
                                                              fbsel3,2,1,0

  inresel       0-1      0-15              xxxx      13       rdgsel2,1,0, indac9,\...,0

  lgthrsel      0-1      0-15              xxx       10       ioff9,\...,0

  hgthrsel      0-1      0-15              xxx       10       ioff9,\...,0

  phacont       0-1      0-15              x         4        hg-adc-en, lg-adc-en, verbose,
                                                              power-on

  lgorsel       0-1      0-2               xxxx      16       enable-rndn15L,\...,enable-rndn0L

  hgorsel       0-1      0-2               xxxx      16       enable-rndn15H,\...,enable-rndn0H

                                                              

  dump          0-1                                  846      dump command registers for
                                                              specified chip\*

  testp         0-1                        xx                 test pulser
  ------------- -------- ----------------- --------- -------- -----------------------------------

> \* Command registers for both chips to be dumped into the command
> response packets in ASCII HEX format, command echo should contain,
> dump 0 or dump 1 to differentiate the 2 chips, followed by the command
> register contents in ASCII HEX (846 bits ) + (18 bits pad).

The following table contains a list of commands for various registers
for the CPU24. Full description of the bit assignments can be found in
the CPU 24 Microprocessor User\'s Manual.

**Register Commands**

  ------------- -------------- ---------- -------- -----------------------------------
  **Command**   **Register**   **Hex      **\#     **Description**
                               Bytes**    bits**   

  gwrite        3              xx         8        Test port

  gwrite        4              xxxxxx     24       PHA ASIC Control Signals

  gwrite        5              xxx        10       Test Pulser Period

  gwrite        7              xxx        11       DAC Control Signals

  setdac                       xxxxxx     20       20-bit shift register
  ------------- -------------- ---------- -------- -----------------------------------

The following table shows miscellaneous commands:

  ----------------------- ----------------------- -----------------------
  **Command**             **Hex Bytes**           **Description**

  tmode                   x                       

  immed                   x                       
  ----------------------- ----------------------- -----------------------