2/10/04

BLM Data Structures and General Information

The BLM data is handled by the current BPM Processor board via the EDB
(External Device Bus).

The EDB is an 8-bit address, 8-bit data bus designed by C. Wegner.

Almost all BLM data logging is linked to the BPM data being logged.
Almost all BPM data is tied to TeV Clock events.

The BLMs have an internal integrator with a 63 mS time constant. So
virtually all BLM data is logged as the most recent reading. By this I
imply that if a "Flash" event happens, I copy the most recent BLM snap
shot frame into the flash frame, etc. The only time I read data from the
BLM is when I am doing a BPM snap shot. These BPM snap shots typically
happen every 2 to 8 mS.

## The BLM uses EDB addresses E0H-FFH

E0H = Status Read

> Status Bit 0 = Abort
>
> Status Bit 1 = Alarm
>
> Status Bit 2 = HV Bad Over
>
> Status Bit 3 = HV Bad Under
>
> Status Bit 4 = +15V Bad
>
> Status Bit 5 = -15V Bad
>
> Status Bit 6 = 5V Bad
>
> Status Bit 7 = ADC Not running

E0H = Clear status bits write

E1H = Status Mask Rd/Wr

E2H = Alarm/Abort Mask Low Byte Rd/Wr

E3H = Alarm/Abort Mask High Byte Rd/Wr

E4H = Alarm Level Set Low Field

E5H = Alarm Level Set High Field

E6H = Abort Level Set Low Field

E7H = Abort Level Set High Field

E9H-ECH not used

EDH = High/Low Field select (Bit 0)

EEH = MADC Channel select

EFH = High Voltage Setting

F0H-FBH = 12 Channels of BLM readings

FCH = ADC reading of Vref (1 lsb = 78.125 mV)

FDH = ADC reading of +15V (1 lsb = 117.2 mV)

FEH = ADC reading of -15V (1 lsb = -117.2 mV)

FFH = ADC reading of HV (1 lsb = 13.02 V)

### BLM Data Structures

Each BLM data entry has 16 bytes defined as follows:

12 bytes containing the 12 Loss Monitor's data

# 1 Status Byte

> Status Bit 0 = Abort
>
> Status Bit 1 = Alarm
>
> Status Bit 2 = High Field
>
> Status Bit 3 = HV Bad Over/Under
>
> Status Bit 4 = +15V Bad
>
> Status Bit 5 = -15V Bad
>
> Status Bit 6 = 5V Bad
>
> Status Bit 7 = ADC Not running

#### Note: Bit 3 is "OR" of status 2 and 3, then bit 2 is replaced by Field

3 bytes of time stamp where 1 LSB = 1 mS

Different BLM Data Types:

BLM Snapshot Buffer (512x16)

> Written at time of BPM Snapshot, circular buffer

BLM Profile Buffer (128x16)

> Written at time of BPM Profile clock event, linear buffer

##### BLM Alarm Frame

> Written when ever the BLM Alarm bit is set

BLM Flash Frame (15x16)

> Written at time of BPM Flash clock event, linear buffer

##### BLM Display Frame-BPM linked

> Written at time of BPM Display clock event

##### BLM Display Frame-BLM only

> Written at time of BLM Display clock event

The only time I read data from the BLM is when I am doing a BPM snap
shot. These BPM snap shots typically happen every 2 to 8 mS.

Other Functions:

## There are built-in test functions for the BLM

These include a test of the HV supply for the BLMs

And an ADC/Continuity test which checks out the BLM detectors as well as
the ADCs etc. These tests require timing events measured in ¼ sec and
1/15 sec.

NOTE: The EDB is also used to support the TIM (Test Interface Module)
for the BPM system. If the TIM remains the EDB will have to support it
as well. The TIM is used to test the BPM functionality by injecting RF
into the front-ends.

Modified EDB for New BLM:

E0H-FFH Same as current system

Except E9-EC Time stamp

If 8 bit BLM data then

00H -- Readback mode

01H -- 02H TBT pointer

03H -- 04H Snapshot Pointer

05H -- Profile Pointer

06H -- Flash Pointer

10H -- 1FH 8 additional sets of Alarm/Abort values

70H -- 7FH BLM TBT frames

80H -- 8FH BLM Snapshot frames

90H -- 9FH BLM Profile frames

A0H -- AFH BLM Flash frames

B0H -- BFH -- BLM Display frame

C0H -- CFH -- BLM Alarm frame

If 16 bit BLM data then

00H -- Readback mode

01H -- 02H TBT pointer

03H -- 04H Snapshot Pointer

05H -- Profile Pointer

06H -- Flash Pointer

10H -- 2FH 8 additional sets of Alarm/Abort values

###### 30H -- 4CH BLM TBT frames

4DH -- 68H BLM Snapshot frames

69H -- 84H BLM Profile frames

85H -- A0H BLM Flash frames

A1H -- BCH -- BLM Display frame

BDH -- D8H -- BLM Alarm frame

Questions:

1)  Is 12 channels/Crate enough? (Yes)

2)  Can a microprocessor be involved in Abort? (Yes)

3)  Is a TBT for the BLM useful? (Yes)

4)  Should the BLM have its own clock decoder? (Yes)

5)  Is 8 bits good enough or do we need 16? (?)

6)  Do we need a different HV for each channel? (No)

7)  Do we need different Alarm/Abort settings for each channel? (?)

8)  How many different types of aborts do we need? Fast? Slow? Really
    Slow? Etc (?)

9)  Do we need Crate-to-Crate Data Links? (No)

New BLM Crate would have

1)  EBD interface

2)  TeV Clk decoder

3)  12 channels

4)  8 or 16 bits

5)  Approximately 8 different Alarm/Abort settings

6)  Aux PC104 or similar Card slot for future Non-EDB communications

New 2/10/04

Features of the new BLM:

1)  64 machine "States" each with its own Abort settings (Masks,
    Multiplicity, Thresholds)

2)  4 types of aborts, a) Instantaneous Loss, b) Fast Loss, c) "Slow"
    Loss, d) Very slow (time over threshold) Loss

3)  Each abort type has an "Abort Multiplicity"

4)  Each Abort type has its' own abort output, so that the abort
    concentrator can enable/disable each type separately. An "Or" of
    these is also available.

5)  Each Channel has an abort mask for the 4 types of aborts.

6)  Real Time Clock with timestamps at 1uSec resolution

7)  Each channel has its own MADC output

8)  14 bit ADC (16k:1 dynamic range per reading)

9)  At least 16k of Turn-By-Turn loss data

10) At least 4k of 1mSec "snapshot" circular buffer

11) Flash, Display, Profile, and Alarm frames as current system.

12) TeV clock decoder

13) EDB interface at startup

14) 10/100 Ethernet included but not supported at startup.

15) The selectable MADC output is removed as not used

16) The HV is the same.

17) 2 Channels per card

18) 3U card cage for easier maintenance

19) The CPU board is upgradeable, with the startup CPU being an eZ80.

New 2/10/04

Abort Types:

1)  Instantaneous: any ADC reading above a set threshold

2)  Fast: The sliding sum of N readings being greater than a set
    threshold. N [\<]{.underline} 1024 (note: if CPLD space permits,
    there might be 2 of these each having a different N value)

3)  Slow: The sliding sum of M readings being greater than a set
    threshold. M [\<]{.underline} 1024 and where M is set to measure
    losses during 1 mSec. This loss is used to maintain the snapshot
    buffer.

4)  Very Slow: This is a time (in mSec) over threshold.

Note: The Sliding Sums are 32 (24) bit numbers, as is the snapshot
buffer.

Are Flashes, Profiles, Display frames, etc also 32 bits?

Card / Slot Count:

6 slots BLM daughter cards

1 slot clock decoder/EDB interface

2 slots CPU card

3 slots AC Power

2 slots HV

Total of 14, 6-hp card slots