**Barrier Coatings and Stability of Thin Film Solar Cells**

**4th Quarterly Report - Phase I:**

**June 1, 2003 \-- August 31, 2003**

**NREL Subcontract: 44575A**

**Subcontractor: Pacific Northwest National Laboratory**

**Principal Investigator: Larry C. Olsen**

**1. OBJECTIVES/APPROACH**

The key objectives of this program are to develop low cost barrier
coatings for CdTe and CIS solar cells and to develop an improved
understanding of mechanisms affecting the stability of CdTe solar cells.
The scope of this work entails investigation of multilayer, barrier
coatings for solar cells and studies of stability issues for CdTe solar
cells. The work is structured into three main tasks: (1) Barrier layer
coatings for CdTe and CIS solar cells; (2) Modeling of mechanisms
influencing CdTe stability; (3) Experimental studies of CdTe cells
supporting Tasks 1 and 2.

**2. PROGRESS THIS REPORTING PERIOD**

Two circuits with barrier coatings were returned to SSI for illuminated
I-V measurements and testing with UV. The effect of damp heat testing on
bare SSI circuits was investigated and further characterization of
coated SSI circuit surfaces discussed.

**2.1 Measurements By SSI**

Two of the coated (barrier coatings) circuits that were subjected to
1000 hours of damp heat testing were sent to SSI for examination. These
circuits exhibited essentially no degradation when characterized at PNNL
after being exposed to 60/90 conditions for 1000 hours. Results obtained
by SSI are summarized in Table 1 and Figure 1. Illuminated I-V
properties measured at SSI for bare circuits prior to sending them to

**Table 1 - SSI Measured I-V Properties For Circuits**

**Circuit Isc Voc FF Pmax**

**(Amps) (Volts) (Watts)**

**Bare Circuit 22 - 4 0.184 5.633 0.508 0.525**

**Coated Circuit 22 - 4 0.192 5.420 0.561 0.582**

**(1000 hr \@60/90)**

**After UV Test 22 - 4 0.183 5.275 0.515 0.498**

**Bare Circuit 22 - 9 0.180 5.652 0.581 0.592**

**Coated Circuit 22 - 9 0.189 5.495 0.608 0.631**

**(1000 hr @ 60/90)**

**After UV Test 22 - 9 0.183 5.750 0.653 0.688**

![](media/image1.png){width="5.083333333333333in" height="3.15625in"}

**Figure 1.** Summary of SSI measured results before two circuits with
PNNL barrier coatings.

PNNL are listed, along with measured properties for the coated circuits
when returned to

SSI. In both cases, the power produced by the circuits increased. It
should be noted that no light soaking was used for the bare circuit
measurements, whereas light soaking was utilized when testing the coated
circuits. SSI engineers do not believe light soaking accounts for all of
the improvement in circuit efficiency. Thus, we can conclude that for
these two cases, the PNNL multilayer coating actually provides for
improved performance, even after 1000 hours of accelerated testing.

SSI also subjected the two circuits to 10 days of UV testing. In this
case, one circuit degraded with respect to the original bare circuit
performance, while the other circuit actually exhibited improved
performance relative to all previous values. Clearly, further
investigations are needed here, but these results are very encouraging.

**2.2 Characterization of Circuit Surfaces**

Further studies were made of coated surfaces. In particular, SEM
examination of a coated SSI circuit surface was carried out for a case
where the planarizing polymer layer was 3.5 to 4.0 µm, as utilized in
the cases where coated circuits survived 1000 hours at 60/90 without any
degradation. Figure 2 shows a micrograph of a multilayer coating
covering a 5 µm nodule. Note the planarizing effect of the first polymer
layer. This layer provides a smooth surface for deposition of subsequent
oxide and polymer layers.

![](media/image2.png){width="4.522222222222222in"
height="3.6333333333333333in"}

**Figure 2.** Multilayer PNNL barrier coating with a planarizing layer
of 3.5 to 4.0 µm. Similar coatings have been used on SSI circuits that
have survived 1000 hours at 60/90 with essentially no degradation.

**2.3 Effects Of Damp Heat On Bare SSI Circuits**

As reported previously, one SSI circuit was subjected to 60/90
accelerated testing that did not have a barrier \-- that is, a bare
circuit. Values of I-V parameters are plotted versus time in Figure 3.
All parameters are affected significantly with Jsc being affected the
most. It appears that the primary effect is due to the increase in sheet
resistance of the ZnO TCO . However, since Voc decreases significantly
over the first few hundred hours, it would appear that the current-loss
mechanisms associated with the junction are also affected. Investigation
of these effects will continue.

External photoresponse data were also acquired for a SSI cell subjected
to 60/90 testing. The cell was formed by depositing a collector grid
between scribe lines on a SSI circuit. The QE is reduced more at longer
wavelengths than at shorter values. This effect is consistent with the
depletion width being decreased as a result of reverse biasing occurring
(when measuring short circuit current) due to the cell series resistance
increasing.

![](media/image3.wmf){width="2.875in" height="2.3506944444444446in"}

![](media/image5.wmf){width="2.921527777777778in"
height="2.3819444444444446in"}

**Figure 3.** Illuminated properties of a bare SSI circuit verses hours
of exposure to a 60/90 environment.

![](media/image7.wmf){width="3.8201388888888888in"
height="2.620833333333333in"}

**QE (%)**

**Wavelength (nm)**

**Figure 4.** External QE for a small SSI cell subjected to 60/90
environment.