**Online Calibration of VLPC chips**

Jadwiga Warchol

**Introduction**

I evaluate the feasibility of calibrating of VLPC chips during the data
taking run in Run II. Calibration event is an event when LED chips
illuminate all fibers and all SVX II chips connected to VLPC chips are
read out. Calibration data are useful only if at least 10 000 triggers
can be collected. I assume that the calibration events should not exceed
0.1 % of the data taking time.

There are two possible sinks for calibration data: local processors in
the crates containing VRB modules or Level 3 monitoring computers, they
both are evaluated. It turns out that the serious obstacle to the
feasibility of calibrating of VLPC chips is long time required to
initialize SVX II chips while switching from data mode to calibration
mode.

**Data Flow**

The signals from VLPC chips are fed into SVX II chips. Eight SVX II
chips (a stream of data) are read out serially into a VRB (VME Readout
Buffer) module, eight such streams (on four fibers since one fiber is 16
bits wide and SVX data eight bits wide) are input in parallel into one
VRB module. Ten VRB modules can be placed in one VME create. All CFT and
preshower VRB modules occupy three crates (all axial CFT fibers are in
one crate). All three creates are connected to a single data cable
transporting the data to Level 3 System.

**Calibration Using Local Processors**

The VME crate with VRB modules contains an embedded processor on VME
board. The silicon group intends to monitor the silicon tracker with
these embedded processors operating in VxWorks environment. In order to
monitor the data without hampering DAQ system two components are built
or considered: monitoring buffer in VRB module and the IEEE P-1394
high-speed bus. The monitoring buffer in VRB module is 1/8^th^ of the
data buffer, it accepts the data from 1 of total of 8 data streams input
to VRB module, the logic on VRB module programs which data stream gets
into data and monitoring buffer. The embedded processor accesses
monitoring buffer via IEEE P-1394 bus; in such way the data for
monitoring do not use VME bus, which is used entirely by DAQ.

The VLPC calibration event sinking in embedded processor is a Level 1
trigger. The first step is the initialization of SVX II chips. The
initialization for calibration event sets to 1 *Read All Channels* bit
in SVX , this is needed since in the data mode the SVX II chips suppress
hits below the threshold between 1 pe. and about 1.7 pe. . To do that
one needs fully initialize SVX chip, which is a serial operation
involving clocking in of 190 bits, and since chips are daisy chained in
groups of eight altogether 190·8=1520 bits have to be clocked in. The
clocking in of the bits is done by 1553 with the speed of about 1.3
μs/bit, and it has to be done twice since after the calibration event
the SVX chips have to be initialized again for data taking mode, total
initialization time, t~ini*t*~, is then:

*t~init~ =1520 bits·1.3 μs/bit·2 = 4000 µs.*

The time from the trigger to the beginning of readout, t~SVX~, is a few
µs:

*t~SVX~ = 560ns(delay before digitization)+1300ns(after digitization)= 2
µs*.

The time, t~transf,~ needed to transfer the data to VRB is very short:

*t~transf~ =8chips(1 stream of data)·128
channels·19ns/byte·2bytes/channel(address,data)=40 µs.*

Since monitoring buffer in VRB sees only 1/8^th^ of data buffer one
needs eight calibration triggers to obtain a calibration event with the
data from all VLPC chips. To get one full calibration event one needs
32.104 ms; this means that the frequency of calibration events has to be
1 per 32 s or 112 events per hour to use 0.1% of total time.

The maximum speed with which one can clock in bits into SVX is 53 MHz,
leading to t~init~ of 58 µs (1520 bits·19ns/bit·2). In that case the
frequency of calibration events is 4000 per hour.

**Table 1.** Time to read out calibration event with embedded
processors.

+---------------------------------+-------------------+---------------+
|                                 | Initialization by | I             |
|                                 |                   | nitialization |
|                                 | 1553              | by            |
|                                 |                   |               |
|                                 |                   | 53 MHz clock  |
+---------------------------------+-------------------+---------------+
| Initialization of SVX, t~init~  | 4000 µs           | 58 µs         |
+---------------------------------+-------------------+---------------+
| Delay in SVX, t~SVX~            | 2 µs              | 2 µs          |
+---------------------------------+-------------------+---------------+
| Transfer to VRB, t~transf~      | 40 µs             | 40 µs         |
+---------------------------------+-------------------+---------------+
| Pipeline reset, t~pipereset~    | 6 µs              | 6 µs          |
+---------------------------------+-------------------+---------------+
| **Total for 1/8^th^ of VLPC     | **4052 µs**       | **106 µs**    |
| chips**                         |                   |               |
+---------------------------------+-------------------+---------------+
| **Total for all VLPC chips**    | **32.416 ms**     | **0.85 ms**   |
+---------------------------------+-------------------+---------------+

**Frequency of calibration events : 112/hour 4000/hour**

**Frequency of calibration events using Level 3 system: 300/hour**

**Calibration Using Level 3 System**

Now the data buffers of VRB modules are used, the data are transferred
on VME backplane with the speed of 20 Mbytes/s to the data cable of
Level 3 system. The speed on the data cable is 48 Mbytes/s and this is
the effective speed because three VRB crates are connected to the data
cable. The size of calibration event is 400kbytes (100000 VLPC
channels·2 bytes/channel·2 for unused SVX channels) and the time to read
it is 10 ms (400kbytes/48 Mbytes/s). The total time for one calibration
event is 12 ms (10ms for data transfer+2 ms for SXV initialization-the
initialization for data mode can be done in parallel with data
transfer), and the frequency of calibration events is 300 events per
hour.

**Sampling Calibration Event**

This is calibration event when only a fraction of VLPC chips is
calibrated. Here I present an example of such event. We calibrate eight
VLPC chips reading axial fibers in one wedge and two SVX chips to which
these chips are connected are permanently initialized for *Real All
Channels* mode. This adds 2·128·2=0.5kbytes to each data event, and
constitutes about 17% of the size of fiber tracker\'s data
(74240fiber·0.02%occupancy·2=3kbytes).

With embedded processor total time for the fractional calibration event
is 48 µs (t~SVX~ + t~transf~ + t~pipereset~) which would allow us to
take 75000 sampling calibration events per hour (3600sec/hour /48000µs).
Since data size is small one could transfer the data to Embedded
Processor via VME bus increasing somewhat the time.

Using of Level 3 would require illumination of only one wedge by LED.
The size of calibration event would be 2kbytes (960 fibers in one
wedge·2). Total time for transfer of the data of the calibration event
is 50 µs (2kbytes/40 Mbytes/s) and the total time of the sampling
calibration event is 58 µs, which is very close to 48µs in the case of
embedded processor.

**Conclusions**

The present electronics does not allow for Online calibration of VLPC
chips due to very slow initializing time of SVX chips. The calibration
of eight chips is possible by permanently initializing two SVX II chips
for Real All Channels mode, this increases the size of data event by 17
% of the size of fiber data.