![](media/image1.wmf){width="5.607638888888889in" height="0.85in"}

PIXEL DETECTOR PROJECT

Test Beam 2002 Readout Electronics Plan

Document \# ESE-PIX-20011203

Rev 1.6

September 10, 2003

Bradley Hall, Guilherme Cardoso, David Christian, Gabriele Chiodini,
Lorenzo Uplegger, Sergio Zimmermann

Revision History

+----+----------+-------+---------------------------------------------+
| R  | Name     | Date  | Comments                                    |
| ev |          |       |                                             |
+----+----------+-------+---------------------------------------------+
| 1  | B. Hall  | 12/   | Draft                                       |
| .0 |          | 28/01 |                                             |
+----+----------+-------+---------------------------------------------+
| 1  | B. Hall  | 02/   | Original release                            |
| .1 |          | 12/02 |                                             |
+----+----------+-------+---------------------------------------------+
| 1  | B. Hall  | 04/   | Updated PMC/PTA Interface                   |
| .2 |          | 30/02 |                                             |
|    |          |       | Updated waveforms in Fig 7.                 |
|    |          |       |                                             |
|    |          |       | Updated Registers                           |
+----+----------+-------+---------------------------------------------+
| 1  | B. Hall  | 06/   | Updated Registers and Data Formats          |
| .3 |          | 07/02 |                                             |
+----+----------+-------+---------------------------------------------+
| 1  | B. Hall  | 08/   | Updated FPIX Data Formats, waveforms to PTA |
| .4 |          | 05/02 | memory, and register definitions.           |
+----+----------+-------+---------------------------------------------+
| 1  | B. Hall  | 11/   | Updated register definitions, added startup |
| .5 |          | 04/02 | sequence section.                           |
+----+----------+-------+---------------------------------------------+
| 1  | B. Hall  | 9/    | Updated register definitions to include     |
| .6 |          | 10/03 | calibration features.                       |
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+----+----------+-------+---------------------------------------------+
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|    |          |       |                                             |
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+----+----------+-------+---------------------------------------------+
|    |          |       |                                             |
+----+----------+-------+---------------------------------------------+
|    |          |       |                                             |
+----+----------+-------+---------------------------------------------+

Table of Contents

[1 Introduction 6](#introduction)

[2 Assumptions 6](#assumptions)

[3 Electronics Overview 6](#electronics-overview)

[3.1 Scintillation Counters & Coincidence
7](#scintillation-counters-coincidence)

[3.2 PTA/PMC 7](#ptapmc)

[3.3 FPIX0 Planes 8](#fpix0-planes)

[3.4 FPIX1 Planes 8](#fpix1-planes)

[3.5 PreFPIX2 Planes 8](#prefpix2-planes)

[3.6 Module 8](#module)

[3.7 PCI Bus 9](#pci-bus)

[4 Clock Distribution & BCO Count Alignment
9](#clock-distribution-bco-count-alignment)

[4.1 Master PMC 9](#master-pmc)

[4.2 BCO Clock Distribution 9](#bco-clock-distribution)

[4.3 BCO Count Alignment & Reset 10](#bco-count-alignment-reset)

[5 PMC FPGA Firmware 11](#pmc-fpga-firmware)

[5.1 FPIX Interface Block 11](#fpix-interface-block)

[5.2 Extended BCO Counter 11](#extended-bco-counter)

[5.3 Fine Resolution BCO Counter 11](#fine-resolution-bco-counter)

[5.4 Triggers 11](#triggers)

[5.5 Receive Window Counter 11](#receive-window-counter)

[5.6 Data Formatter 13](#data-formatter)

[5.6.1 Data Blocks 13](#data-blocks)

[5.6.2 Triggered Header Word Format 14](#triggered-header-word-format)

[5.6.3 Untriggered Header Word Format
14](#untriggered-header-word-format)

[5.6.4 FPIX0 Data Format 14](#fpix0-data-format)

[5.6.5 FPIX1 Data Format 14](#fpix1-data-format)

[5.6.6 preFPIX2tb Data Format 14](#prefpix2tb-data-format)

[5.6.7 preFPIX2i Data Format 14](#prefpix2i-data-format)

[5.6.8 FPIX2 Data Format 15](#fpix2-data-format)

[5.7 PTA Memory Interface 15](#pta-memory-interface)

[5.8 FPIX Configuration Path 15](#fpix-configuration-path)

[5.9 Startup Sequence 15](#startup-sequence)

[5.10 Pulse Out 16](#pulse-out)

[6 Registers 18](#registers)

[6.1 PMC Standard Registers 18](#pmc-standard-registers)

[6.1.1 Firmware Type: Address 0x0000 (read only)
18](#firmware-type-address-0x0000-read-only)

[6.1.2 Firmware Revision: Address 0x0004 (read only)
18](#firmware-revision-address-0x0004-read-only)

[6.2 PMC Test Beam '02 Specific Registers
18](#pmc-test-beam-02-specific-registers)

[6.2.1 Control Register A: Address 0x0008 (read/write)
19](#control-register-a-address-0x0008-readwrite)

[6.2.2 Control Register B: Address 0x000C (read/write)
19](#control-register-b-address-0x000c-readwrite)

[6.2.3 Control Register C: Address 0x0010 (read/write) -- Not
Implemented
20](#control-register-c-address-0x0010-readwrite-not-implemented)

[6.2.4 Control Register D: Address 0x0014 (read/write) -- Not
Implemented
20](#control-register-d-address-0x0014-readwrite-not-implemented)

[6.2.5 Control Register E: Address 0x0018 (read/write) -- Pulse Out
Control
21](#control-register-e-address-0x0018-readwrite-pulse-out-control)

[6.2.6 Control Register F: Address 0x001C (read/write) -- Pulse Out
Train Length
21](#control-register-f-address-0x001c-readwrite-pulse-out-train-length)

[6.2.7 Control Register G: Address 0x0020 (read/write) -- Calibration
Control
21](#control-register-g-address-0x0020-readwrite-calibration-control)

[6.2.8 Plane A ID Register: Address 0x0030 (read/write)
22](#plane-a-id-register-address-0x0030-readwrite)

[6.2.9 Plane B ID Register: Address 0x0034 (read/write)
22](#plane-b-id-register-address-0x0034-readwrite)

[6.2.10 Receive Window Register: Address 0x0038 (read/write)
22](#receive-window-register-address-0x0038-readwrite)

[6.2.11 Max Data Register: Address 0x003C (read/write) -- Not
Implemented
22](#max-data-register-address-0x003c-readwrite-not-implemented)

[6.3 FPIX0 Specific Registers 22](#fpix0-specific-registers)

[6.4 FPIX1 Specific Registers 23](#fpix1-specific-registers)

[6.4.1 FPIX1 Interface Plane A: Address 0x0100 (read/write)
23](#fpix1-interface-plane-a-address-0x0100-readwrite)

[6.4.2 FPIX1 Interface Plane B: Address 0x0104 (read/write)
23](#fpix1-interface-plane-b-address-0x0104-readwrite)

[6.5 preFPIX2tb Specific Registers 24](#prefpix2tb-specific-registers)

[6.5.1 preFPIX2tb Interface Plane A: Address 0x0100 (read/write)
24](#prefpix2tb-interface-plane-a-address-0x0100-readwrite)

[6.5.2 preFPIX2tb Interface Plane B: Address 0x0104 (read/write)
24](#prefpix2tb-interface-plane-b-address-0x0104-readwrite)

[6.5.3 preFPIX2tb Interface Plane A: Address 0x0108 (read only)
25](#prefpix2tb-interface-plane-a-address-0x0108-read-only)

[6.5.4 preFPIX2tb Interface Plane B: Address 0x011C (read only)
25](#prefpix2tb-interface-plane-b-address-0x011c-read-only)

[6.6 preFPIX2i Specific Registers 26](#prefpix2i-specific-registers)

[6.6.1 preFPIX2i Interface Plane A: Address 0x0100 (read/write)
26](#prefpix2i-interface-plane-a-address-0x0100-readwrite)

[6.6.2 preFPIX2i Interface Plane B: Address 0x0104 (read/write)
26](#prefpix2i-interface-plane-b-address-0x0104-readwrite)

[6.6.3 preFPIX2i Interface Plane A: Address 0x0108 (read only)
27](#prefpix2i-interface-plane-a-address-0x0108-read-only)

[6.6.4 preFPIX2i Interface Plane B: Address 0x011C (read only)
27](#prefpix2i-interface-plane-b-address-0x011c-read-only)

[7 PTA/PMC Interface 28](#ptapmc-interface)

[8 FPIX0 Interface 32](#fpix0-interface)

[9 FPIX1 Interface 32](#fpix1-interface)

[10 PreFPIX2 Interface 33](#prefpix2-interface)

[11 References 33](#references)

Figures and Tables

[*Fig. 1. Test beam electronics schematic.*
7](#__RefHeading___Toc50977024)

[*Fig. 2. PTA card (left) and PMC (right).*
8](#__RefHeading___Toc50977025)

[*Fig. 3. PMC FPGA block diagram.* 10](#__RefHeading___Toc50977026)

[*Fig. 4. Waveforms with locally generated async accelerator clock.*
12](#__RefHeading___Toc50977027)

[*Table 1. Possible data words.* 13](#__RefHeading___Toc50977028)

[*Fig. 5. Triggered header word and four FPIX1 words.*
13](#__RefHeading___Toc50977029)

[*Fig. 6. Untriggered FPIX1 word.* 13](#__RefHeading___Toc50977030)

[*Fig. 7. Triggered header word.* 14](#__RefHeading___Toc50977031)

[*Fig. 8. Untriggered header word.* 14](#__RefHeading___Toc50977033)

[*Fig. 9. FPIX0 data word.* 14](#__RefHeading___Toc50977034)

[*Fig. 10. FPIX1 data word.* 14](#__RefHeading___Toc50977035)

[*Fig 11. preFPIX2tb data word.* 14](#__RefHeading___Toc50977036)

[*Fig. 12. preFPIX2i data word.* 15](#__RefHeading___Toc50977037)

[*Fig. 13. FPIX2 data word.* 15](#__RefHeading___Toc50977038)

[*Fig. 14. Waveforms for PMC to PTA memory interface.*
15](#__RefHeading___Toc50977039)

[*Fig. 15. Example Pulse Train of Length 4.*
17](#__RefHeading___Toc50977040)

[*Table 2. JN1 pin assignment PTA/PMC interface.*
28](#__RefHeading___Toc50977041)

[*Table 3. JN2 pin assignment PTA/PMC interface.*
31](#__RefHeading___Toc50977042)

[*Fig. 16. Pin assignment for FPIX0 interface.*
32](#__RefHeading___Toc50977043)

[*Fig. 17. Pin assignment for FPIX1 interface.*
32](#__RefHeading___Toc50977044)

[*Fig. 18. Pin assignment for FPIX2i and FPIX2tb interface.*
33](#__RefHeading___Toc50977045)

#   {#section .unnumbered}

# Introduction

This document describes the readout electronics implementation plan for
the pixel detector telescope for the 2002 test beam at Fermilab. The
scope of this document includes the hardware from and including the PCI
bus up to and including the pixel telescope planes and the planes under
test. Topics covered include descriptions of the hardware components,
the interface between the Programmable Mezzanine Cards (PMCs) and the
FPIX planes, the interface between the PMC and the PCI Test Adapter
(PTA) cards, the formatting of the data words that will be sent to
memory banks on the PTA cards, the timing signals for synchronizing
multiple planes, and the triggering technique.

# Assumptions

This document assumes the following:

-   Event rate no more than \~100kHz.

-   Beam structure will provide beam for approximately one second
    followed by five seconds of no beam.

-   DAQ software will be capable of reading out all data stored in PTA
    memory and issuing a reset within the beam structure period of
    approximately six seconds (one second of beam followed by five
    seconds of no beam).

# Electronics Overview

The test beam instrumentation will consist of an eight-plane telescope
and up to four planes and/or a module under test (see Fig. 1). Each
telescope plane will consist of an FPIX1 chip bump bonded to a pixel
sensor array and mounted on an inner board. The planes under test will
consist of an FPIX0 or preFPIX2 chip bump bonded to a sensor array and
mounted on an inner board. One scintillation counter upstream and one
scintillation counter downstream will serve as a minimum coincidence
trigger configuration. A PCI based PTA card with a mated PMC card will
serve to control and readout two planes. This section describes each of
the components shown in Fig. 1.

![](media/image2.wmf){width="5.995138888888889in"
height="4.627083333333333in"}

[]{#__RefHeading___Toc50977024 .anchor}*Fig. 1. Test beam electronics
schematic.*

## Scintillation Counters & Coincidence 

Two scintillation counters, one upstream and one downstream, will serve
as the minimum trigger configuration. Coincidence electronics located in
the counting room distribute the coincidence signal to each of the PMCs.
The coincidence signal should be NIM level and connect to one of the
four LEMO header inputs on the PMC. How the PMC card uses this
coincidence signal is described in section 5.

## PTA/PMC

The PTA (PCI Test Adapter)\[1\] and PMC (Programmable Mezzanine
Card)\[2\] (see Fig. 2) are used to control and receive data from the
telescope planes (FPIX1) and the planes under test (FPIX0 or preFPIX2).
Different PMC firmware will be developed for each type of plane.
Firmware in the PTA cards will be common across the entire system. A
single PTA/PMC can control up to two planes. The PTA card has two banks
of 1MByte memory for a total of 2MBytes. Event data from the pixel
planes is stored in the PTA card memory until it is read out from the PC
via the PCI bus. The PTA/PMC cards will be located in the counting room.

![](media/image3.bmp) ![](media/image4.png){width="3.08125in"
height="1.7784722222222222in"}

[]{#__RefHeading___Toc50977025 .anchor}*Fig. 2. PTA card (left) and PMC
(right).*

## FPIX0 Planes

Up to four FPIX0 planes will be under test. FPIX0 planes will consist of
a single FPIX0 chip bump bonded to a sensor and mounted in the center of
the inner board. All signaling to/from the FPIX0 board will be LVDS. The
FPIX0 inner board will have LVDS transmitters/receivers for
driving/receiving signals to/from the PMC boards 30m away in the
counting room. Details of the FPIX0 inner board can be found in
reference \[3\].

## FPIX1 Planes

A total of eight FPIX1 planes will be used to construct the test beam
telescope. FPIX1 planes will consist of a single FPIX1 chip bump bonded
to a sensor and mounted in the center of the inner board. All signaling
to/from the FPIX1 board will be LVDS. The FPIX1 inner board will have
LVDS transmitters/receivers for driving/receiving signals to/from the
PMC boards 30m away in the counting room. Details of the FPIX1 inner
board can be found in reference \[4\].

## PreFPIX2 Planes 

Up to four preFPIX2 planes will be under test. PreFPIX2 planes will
consist of a single preFPIX2i or preFPIX2b chip bump bonded to a sensor
and mounted in the center of the inner board. Jumpers on the preFPIX2
inner board will be used to accommodate either a preFPIX2i or preFPIX2b.
All signaling to/from the preFPIX2 board will be LVDS. The preFPIX2
inner board will have LVDS transmitters/receivers for driving/receiving
signals to/from the PMC boards 30m away in the counting room. Details of
the preFPIX2 inner board can be found in reference \[5\].

## Module

An FPIX module consisting of multiple FPIX chips possibly will be
tested. All signaling to/from the module will be LVDS. The FPIX module
will have LVDS transmitters/receivers for driving/receiving signals
to/from the PMC boards 30m away in the counting room. If an FPIX module
is used in the test beam, a maximum of three FPIX planes under test can
be in the system.

## PCI Bus

The PTA cards plug into a SBS Technologies PCI expansion unit with 13
PCI slots. A PTA/PMC plugs into a single PCI slot, but physically
interferes with the adjacent slot. This interference causes each PTA/PMC
to occupy 2 PCI slots resulting in a maximum of 6 PTA/PMCs in a single
PCI expansion unit. With each PTA/PCI card capable of connecting to two
planes, a single PCI expansion unit is capable of connecting 12 planes.

The PCI bus will be located in the counting room in close proximity to
the PC. Data cables of approximately 30m in length will send/receive
signals to/from the hut and plug into the PMC. Having the PCI bus in the
counting room allows easy access for debugging. If, however, the 30m
cable length results in too many technical challenges the PCI bus can be
placed in the hut allowing for much short cables, but poor access.

# Clock Distribution & BCO Count Alignment

It is important that each of the planes in the telescope and planes
under test be synchronized and phase aligned with the same BCO clock and
BCO count. This section describes the BCO clock and BCO count alignment
technique.

## Master PMC

One of the PMCs will be designated the Master PMC. A PMC is set to a
master by software setting a bit in its control register (see section
6). The Master PMC is responsible for distributing the BCO clock and
reset signal to all PMCs. The master and slave PMCs will have the same
firmware, however, the Master PMC will have the termination resistors at
the *Low Skew General* and *Low Skew Clock Distribute* resources removed
\[2\]. The only time the DAQ software needs to distinguish between a
Master PMC and the Slave PMCs is during the initializing (when setting
the control bit), when issuing a reset (a reset is only wrote to the
Master PMC), and when phase adjusting the BCO clock (in the case where a
synchronous accelerator beam is available).

## BCO Clock Distribution

Either the master accelerator clock will be available in the counting
room for distribution to each PMC or a locally generated BCO clock that
is asynchronous to the beam will be used. In either case, the BCO clock
is sent to the Master PMC. In the synchronous BCO clock case, the Master
PMC uses its Digital Clock Manager (DCM) to phase shift the BCO clock
with PERIOD~BCOCLK~/256 resolution (520ps with 132ns BCO clock). The
magnitude of the phase shift is set via a register and is used to tune
the phase of the BCO clock at the hut relative to the arrival of the
beam. In the case where the master accelerator clock is not available
and an asynchronous locally generated BCO clock is used, the phase
shifting feature on the DCM is unused. The Master PMC distributes the
BCO clock to the other PMCs in the PCI bus via its *Low Skew Clock
Distribute* resource (see Fig. 1). The distributed BCO clock passes
through each FPGA on the PMC and is driven via the data cable to the
each plane in the hut (see Fig. 3). With matched cable lengths each
plane in the hut should receive phase aligned BCO clocks.

If the above technique does not provide adequate phase alignment of the
BCO clocks at the planes, the alignment can be adjusted on a plane to
plane basis by using additional Xilinx Digital Clock Manager resources
to tune each BCO clock phase with PERIOD~BCOCLK~/256 resolution (520ps
with 132ns BCO clock). This fine phase tuning can be done by software
setting PMC registers.

## BCO Count Alignment & Reset

With a BCO clock distributed and in phase at each of the FPIX planes a
common reset signal must be distributed. This common reset signal is
distributed much like the BCO clock distribution technique. The Master
PMC uses the reset bit in a register (see section 6 for register
definitions) to distributed the reset signal to all other PMCs via the
*Low Skew General Distribute* resource (see Fig. 1). The reset signal
then passes through each FPGA on the PMC and is driven via the data
cables to the planes in the hut (see Fig. 3). With match cable lengths,
each plane in the hut should receive the reset signal in phase and
therefore have their BCO counts in phase.

[]{#__RefHeading___Toc50977026
.anchor}![](media/image5.wmf){width="5.999305555555556in"
height="5.093055555555556in"}*Fig. 3. PMC FPGA block diagram.*

# PMC FPGA Firmware

The FPGA on the PMC will function to interface to two FPIX planes, the
trigger, the BCO clock, and the PTA card as shown in Fig. 3. This
section describes the PMC FPGA functional blocks shown in Fig. 3, the
technique used to record coincidence signals, and the format of the data
words. Refer to Fig. 4 for waveforms showing events described in this
section.

## FPIX Interface Block

Fig. 3 shows two *FPIX interface* blocks in the PMC FPGA. The *FPIX
interface* provides all the necessary digital control signals to and
from FPIX and is responsible for receiving the FPIX data. FPIX is
operated in continuous readout mode (free running BCO clock and free
running readout clock). Different FPGA firmware will be used for
interfacing to FPIX0, FPIX1, preFPIX2i, or preFPIX2b. The interface
formats the FPIX data into a word as shown in Fig. 3 that is then sent
to the *Data Formatter* block.

## Extended BCO Counter

The *Extended BCO Counter* in the PMC FPGA is 26 bits and is clock by
the BCO clock. With a 26 bit *Extended BCO Counter* and BCO clock period
of 132ns, there is \~8.8 seconds of unique *Extended BCO Counter*
states. The value of this counter is used in the formatted data words.

## Fine Resolution BCO Counter

The *Fine-Res BCO Counter* is a Gray-code counter clocked by a multiple
of the BCO clock frequency. Fig. 3 shows this as a multiple of 20 of the
BCO clock. The *Fine-Res BCO Counter* is reset to 0 every rising edge of
BCO clock. In the case where the BCO clock is the accelerator clock
synchronous to the beam, the *Fine-Res BCO Counter* ideally should be at
the same count value at each trigger. The *Fine-Res BCO Counter* is
intended to be used in the asynchronous BCO clock case. With the example
frequencies shown in Fig. 3, the counter will give 1/144Mhz = \~7ns
timing resolution to measure the trigger time relative to the BCO edge.

## Triggers

The trigger received by the PMC is used to latch the current count of
the *Extended BCO Counter*, latch the current count of the *Fine-Res BCO
Counter*, to initiate data transfer to the PTA memory starting with the
header word (see Fig. 4), and to start the *Receive Window* counter.

## Receive Window Counter

When a trigger (coincidence signal) is received by a PMC, the *Receive
Window Counter* begins. The *Receive Window Counter* is clocked by the
BCO clock and will count up to the value stored in the *Receive Window
Register* (defined in section 6). If another trigger is received while
the *Receive Window Counter* is counting, the count will restart. This
counter is used to determine if the received FPIX data is tagged as
triggered data, or untriggered data by the *Data Formatter*.

[]{#__RefHeading___Toc50977027
.anchor}![](media/image6.wmf){width="5.281944444444444in"
height="8.73611111111111in"}*Fig. 4. Waveforms with locally generated
async accelerator clock.*

## Data Formatter

The *Data Formatter* is responsible for assembling a data header word
and formatting the incoming FPIX data. All words are 32 bits wide. The
possible word types indicated by the four most significant bits of the
data word are described in Table 1.

[]{#__RefHeading___Toc50977028 .anchor}Table 1. Possible data words.

  ---------- ------------------------------------------------------------
  **Data     **Meaning**
  Type       
  Bits**     

  0000       Illegal

  1XXX       Triggered header word. Triggered Extended BCO Count,
             Fine-Res count

  0001       Untriggered header word. Untriggered Extended BCO Count

  0010       FPIX0 Data

  0011       FPIX1 Data

  0100       preFPIX2tb Data

  0101       preFPIX2i Data

  0110       FPIX2 Data
  ---------- ------------------------------------------------------------

### Data Blocks

![](media/image7.wmf){width="5.986805555555556in"
height="0.8715277777777778in"}When a trigger occurs, the data formatter
immediately creates a data type '1XXX' (most significant bit is '1')
word and sends it to the *PTA Memory Interface*. This data word includes
the 26 bit extended BCO count and *Fine-Res Count* state at the time the
trigger was received. The *Data Formatter* then receives the incoming
FPIX data from the *FPIX Interface* and formats it with the appropriate
data type (data type will be set by the firmware based on the FPIX
interface type) as long as the *Receive Window Counter* has not reached
its value store in the *Receive Window Register*. Fig. 5 shows an
example sequence of words that would appear in the PTA memory that
include a header word with the extended BCO number followed by four
FPIX1 data words.

[]{#__RefHeading___Toc50977029 .anchor}*Fig. 5. Triggered header word
and four FPIX1 words.*

In the event the PMC receives data from an FPIX plane outside the
*Receive Window*, the FPIX data can be passed onto the PTA memory in the
format shown in Fig. 6. A register (described in section 6) controls
whether or not these untriggered FPIX data words are passed onto the PTA
card memory. Untriggered FPIX data words are distinguished from those
that were received after a trigger by their header data word.

[]{#__RefHeading___Toc50977030
.anchor}![](media/image8.wmf){width="5.986805555555556in"
height="0.35694444444444445in"}*Fig. 6. Untriggered FPIX1 word.*

###  Triggered Header Word Format

The format for the Triggered Header Word is shown in Figure 7.

[]{#__RefHeading___Toc50977031 .anchor}*Fig. 7. Triggered header word.*

![](media/image9.wmf){width="5.995138888888889in" height="0.35625in"}

### Untriggered Header Word Format

The format for the Untriggered Header Word is shown in Figure 8.

[]{#__RefHeading___Toc50977033
.anchor}![](media/image10.wmf){width="5.995138888888889in"
height="0.35625in"}*Fig. 8. Untriggered header word.*

### FPIX0 Data Format

The format for the FPIX0 data word is shown in Figure 9. Note that the 8
bit ADC is in the position the BCOs are for FPIX1, preFPIX2tb,
preFPIX2i, and FPIX2 data formats.

[]{#__RefHeading___Toc50977034
.anchor}![](media/image11.wmf){width="5.986805555555556in"
height="0.35694444444444445in"}*Fig. 9. FPIX0 data word.*

### FPIX1 Data Format

The format for the FPIX1 data word is shown in Figure 10. Bit 6 is the
LSB of the four-bit Chip ID. The Chip ID is important if a multi-chip
module is under test.

[]{#__RefHeading___Toc50977035
.anchor}![](media/image12.wmf){width="5.986805555555556in"
height="0.35694444444444445in"}*Fig. 10. FPIX1 data word.*

### preFPIX2tb Data Format

The format for the preFPIX2tb data word is shown in Figure 11.

![](media/image13.wmf){width="5.986805555555556in"
height="0.35694444444444445in"}

[]{#__RefHeading___Toc50977036 .anchor}*Fig 11. preFPIX2tb data word.*

### preFPIX2i Data Format

The format for the preFPIX2i data word is shown in Figure 12. Note that
it is the same as the preFPIX2tb format except for the 4-bit data type.

[]{#__RefHeading___Toc50977037
.anchor}![](media/image14.wmf){width="5.986805555555556in"
height="0.35694444444444445in"}*Fig. 12. preFPIX2i data word.*

### FPIX2 Data Format

The format for the FPIX2 data word is shown in Figure 12.

[]{#__RefHeading___Toc50977038
.anchor}![](media/image15.wmf){width="5.986805555555556in"
height="0.35694444444444445in"}*Fig. 13. FPIX2 data word.*

## PTA Memory Interface

The *PTA Memory Interface* block is responsible for passing the 32 bit
data word from the PMC to the FPGA on the PTA card. The Altera FPGA on
the PTA card receives the 32 bit data word from the PMC and is
responsible for moving the data to the appropriate bank of memory and
the appropriate memory address. Fig. 14 shows example waveforms that the
*PTA Memory Interface* might send to the PTA card. DATA0, DATA1, DATA2,
DATA3, and DATA4 would all be placed in PTA card memory.

![](media/image16.wmf){width="5.996527777777778in"
height="0.9458333333333333in"}

[]{#__RefHeading___Toc50977039 .anchor}*Fig. 14. Waveforms for PMC to
PTA memory interface.*

## FPIX Configuration Path

The FPIX configuration will be accomplished by software toggling the
appropriate SHIFT_IN and Clock signals. Section 6 describes the
registers required to achieve this.

## Startup Sequence

To insure proper synchronization of BCO clocks and counters, the
following startup sequence must be followed:

  ------------- ----------------------------- ----------------- -----------------
  ***General                                                    
  Clocks and                                                    
  Counters                                                      
  Startup                                                       
  Sequence***                                                   

  ***Step***    ***Description***             ***Plane***       ***Register***

  1             Set Master PMC                Master PMC only   0x0008

  2             Set BCO Phase Offsets --      Each PMC          0x0010
                Plane A                                         

  3             Set BCO Phase Offsets --      Each PMC          0x0014
                Plane B                                         

  4             Reset Master Clock Manager    Master PMC only   0x000C

  5             Reset Plane A Clock Manager   Each PMC          0x000C

  6             Reset Plane B Clock Manager   Each PMC          0x000C

  7             Reset and Sync Counters       Master PMC only   0x0008
  ------------- ----------------------------- ----------------- -----------------

An example startup sequence that would be for a single PTA/PMC card
connected to two pixel planes (both Plane A and Plane B) is shown below:

  ------------- ------------------------------ ---------------- -----------------
  ***Example                                                    
  Clocks and                                                    
  Counters                                                      
  Startup                                                       
  Sequence***                                                   

  ***Step***    ***Description***              ***Register***   ***Value***

  1             Set Master PMC and Disable     0x0008           0x000D
                Planes                                          

  2             Set BCO Phase Offset -- Plane  0x0010           0x0028
                A                                               

  3             Set BCO Phase Offset -- Plane  0x0014           0x010C
                B                                               

  4             Assert Master Clock Reset      0x000C           0x1000

  5             De-assert Master Clock Reset   0x000C           0x0000

  6             Wait \>20ms                                     

  7             Assert Plane-A Clock Reset     0x000C           0x2000

  8             De-assert Plane-A Clock Reset  0x000C           0x0000

  9             Wait \>20ms                                     

  10            Assert Plane-B Clock Reset     0x000C           0x4000

  11            De-assert Plane-B Clock Reset  0x000C           0x0000

  12            Wait \>20ms                                     

  13            Assert Counter Reset           0x0008           0x000F

  14            De-assert Counter Reset        0x0008           0x000D

  15            Enable Both Planes             0x0008           0x0001
  ------------- ------------------------------ ---------------- -----------------

Note that the "wait" steps (steps 6, 9, and 12) are to allow the Digital
Clock Managers (DCMs) in the PMC FPGA sufficient time to establish a
stable locked condition. Failure to wait for at least 20ms can cause
erroneous clocks.

##  Pulse Out

Both J1 pin 1 and pin 13 on the PMC offer a TTL pulse that is
synchronous to the BCO Clock and controlled with registers 0x0018 and
0x001C (see section 6). Use register 0x0018 to select the pulse
frequency (119Hz to 3.91Mhz with BCO Clk = 7.8125MHz), edge sensitivity,
and for reset. Register 0x001C is used to set the number of pulses in
the pulse train (1 to 65535). All pulses are of width equal to one BCO
clock cycle.

When register 0x001C (Pulse Train Length) is set to 0x0000, Pulse Out is
free running at a frequency equal to the register 0x0018 Pulse Frequency
selection.

Figure 15 shows an example waveform when the following sequence is used:

  ------------ -------------------------------- ---------------- -----------------
  ***Example                                                     
  Pulse Out                                                      
  Setup***                                                       

  ***Step***   ***Description***                ***Register***   ***Value***

  1            Set Pulse Train Length to '4'.   0x001C           0x0004

  2            Select Pulse Freq to 'BCO        0x0018           0x8002
               Clk/4', Clk Edge to 'Negative',                   
               and set reset '1'                                 

  3            De-assert reset to begin pulse   0x0018           0x0002
               train                                             
  ------------ -------------------------------- ---------------- -----------------

![](media/image17.jpeg){width="5.820138888888889in"
height="4.179166666666666in"}

[]{#__RefHeading___Toc50977040 .anchor}*Fig. 15. Example Pulse Train of
Length 4.*

To restart the pulse train, re-assert the reset by repeating steps 2 and
3 above.

# Registers

All registers in the PMC are read and some read/write via the DAQ
software interface. This section describes the registers in the PMC
FPGA.

## PMC Standard Registers

These registers are standard on all PMC cards regardless of their
function.

### Firmware Type: Address 0x0000 (read only)

+--------+-------------------------------------------------------------+
| ***Bit | ***Meaning***                                               |
| \#***  |                                                             |
+--------+-------------------------------------------------------------+
| 15..0  | PMC Type:                                                   |
|        |                                                             |
|        | 0x0000 = Undefined                                          |
|        |                                                             |
|        | 0x0001 = Cable loop back test                               |
|        |                                                             |
|        | 0x0002 = FPIX0 test beam '02                                |
|        |                                                             |
|        | 0x0003 = FPIX1 test beam '02                                |
|        |                                                             |
|        | 0x0004 = preFPIX2tb test beam '02                           |
|        |                                                             |
|        | 0x0005 = preFPIX2i test beam '02                            |
+--------+-------------------------------------------------------------+

### Firmware Revision: Address 0x0004 (read only)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  7..0      Minor revision number.

  15..8     Major revision number.
  --------- -------------------------------------------------------------

## PMC Test Beam '02 Specific Registers

Registers described in this section are unique to the PMC used in the
2002 test beam. These registers are common to all the 2002 test beam
PMCs.

### Control Register A: Address 0x0008 (read/write)

+--------+-------------------------------------------------------------+
| ***Bit | ***Meaning***                                               |
| \#***  |                                                             |
+--------+-------------------------------------------------------------+
| 0      | 0 = Slave, 1 = Master                                       |
+--------+-------------------------------------------------------------+
| 1      | Master Distributed Reset (clear and re-sync counters)       |
+--------+-------------------------------------------------------------+
| 2      | 1 = Disable Plane A                                         |
+--------+-------------------------------------------------------------+
| 3      | 1 = Disable Plane B                                         |
+--------+-------------------------------------------------------------+
| 4      | Send untriggered FPIX data (not implemented)                |
+--------+-------------------------------------------------------------+
| 5      | Ignore all data (not implemented)                           |
+--------+-------------------------------------------------------------+
| 6      | Generate fake data                                          |
+--------+-------------------------------------------------------------+
| 7      | Clear fake data counter                                     |
+--------+-------------------------------------------------------------+
| 10..8  | Fake data clock selection                                   |
|        |                                                             |
|        | 000 = M/2 = 25Mhz                                           |
|        |                                                             |
|        | 001 = M/4 = 12.5Mhz                                         |
|        |                                                             |
|        | 010 = M/8 = 6.25Mhz                                         |
|        |                                                             |
|        | 011 = M/16 = 3.13Mhz                                        |
|        |                                                             |
|        | 100 = M/32 = 1.56Mhz                                        |
|        |                                                             |
|        | 101 = M/64 = 781kHz                                         |
|        |                                                             |
|        | 110 = M/128 = 391kHz                                        |
|        |                                                             |
|        | 111 = M/256 = 195kHz                                        |
|        |                                                             |
|        | M is the frequency of the PMC on board oscillator           |
|        | (X1)...50Mhz.                                               |
+--------+-------------------------------------------------------------+
| *1     | *Unused*                                                    |
| 4..11* |                                                             |
+--------+-------------------------------------------------------------+
| 15     | TTL pulse out. This bit is connected to pin 11 of TTL       |
|        | header (J5) on the PMC.                                     |
+--------+-------------------------------------------------------------+

### Control Register B: Address 0x000C (read/write)

+--------+-------------------------------------------------------------+
| ***Bit | ***Meaning***                                               |
| \#***  |                                                             |
+--------+-------------------------------------------------------------+
| 0      | Master Clock Source                                         |
|        |                                                             |
|        | 0 = 50Mhz PMC Oscillator                                    |
|        |                                                             |
|        | 1 = NIM1 input                                              |
|        |                                                             |
|        | Master Clk is set to Master Clock Source \*5/8 (31.25Mhz    |
|        | with 50Mhz Oscillator).                                     |
+--------+-------------------------------------------------------------+
| 1      | BCO Clock to FPIX Plane A                                   |
|        |                                                             |
|        | 0 = Send Master Clk/4 to FPIX Plane A (7.81Mhz w/ 50Mhz     |
|        | Oscillator).                                                |
|        |                                                             |
|        | 1 = Send Software Toggle to FPIX Plane A                    |
+--------+-------------------------------------------------------------+
| 2      | BCO Source to FPIX Plane B                                  |
|        |                                                             |
|        | 0 = Send Master Clk/4 to FPIX Plane B (7.81Mhz w/ 50Mhz     |
|        | Oscillator).                                                |
|        |                                                             |
|        | 1 = Send Software Toggle to FPIX Plane B                    |
+--------+-------------------------------------------------------------+
| 3      | Readout Clock Source to FPIX Plane A                        |
|        |                                                             |
|        | 0 = Send Readout Clock equal to Master Clk/2 to FPIX Plane  |
|        | A (15.63Mhz w/ 50Mhz Oscillator).                           |
|        |                                                             |
|        | 1 = Send Readout Clock Software Toggle to FPIX Plane A      |
+--------+-------------------------------------------------------------+
| 4      | Readout Clock Source to FPIX Plane B                        |
|        |                                                             |
|        | 0 = Send Readout Clock equal to Master Clk/2 to FPIX Plane  |
|        | B (15.63Mhz w/ 50Mhz Oscillator).                           |
|        |                                                             |
|        | 1 = Send Readout Clock Software Toggle to FPIX Plane B      |
+--------+-------------------------------------------------------------+
| 5      | Data Latch CLK select Plane A (used to latch incoming FPIX  |
|        | data from Plane A)                                          |
|        |                                                             |
|        | 0 = Data Latch CLK is same as Readout Clk to Plane A        |
|        |                                                             |
|        | 1 = Data Latch CLK is inverse of Readout Clk to Plane A     |
+--------+-------------------------------------------------------------+
| 6      | Data Latch CLK select Plane B (used to latch incoming FPIX  |
|        | data from Plane B)                                          |
|        |                                                             |
|        | 0 = Data Latch CLK is same as Readout Clk to Plane B        |
|        |                                                             |
|        | 1 = Data Latch CLK is inverse of Readout Clk to Plane B     |
+--------+-------------------------------------------------------------+
| 7      | Readout Clock x2 selection                                  |
|        |                                                             |
|        | 0 = Master Clk \* 32/5 (200Mhz with 50Mhz Oscillator).      |
|        |                                                             |
|        | 1 = FPIX readout Clk A doubled via delay element            |
+--------+-------------------------------------------------------------+
| *      | *Unused*                                                    |
| 11..8* |                                                             |
+--------+-------------------------------------------------------------+
| 12     | DCM Reset -- Master Clk Distribute                          |
+--------+-------------------------------------------------------------+
| 13     | DCM Reset -- Plane A Clks                                   |
+--------+-------------------------------------------------------------+
| 14     | DCM Reset -- Plane B Clks                                   |
+--------+-------------------------------------------------------------+
| *15*   | *Unused*                                                    |
+--------+-------------------------------------------------------------+

###  {#section-1 .unnumbered}

### Control Register C: Address 0x0010 (read/write) -- Not Implemented

+--------+-------------------------------------------------------------+
| ***Bit | ***Meaning***                                               |
| \#***  |                                                             |
+--------+-------------------------------------------------------------+
| 7..0   | Phase Adjust Magnitude BCO Clk FPIX Plane A                 |
+--------+-------------------------------------------------------------+
| 8      | Phase Adjust Direction BCO Clk FPIX Plane A                 |
|        |                                                             |
|        | 0 = Positive                                                |
|        |                                                             |
|        | 1 = Negative                                                |
+--------+-------------------------------------------------------------+
| *      | *Unused*                                                    |
| 15..9* |                                                             |
+--------+-------------------------------------------------------------+

### Control Register D: Address 0x0014 (read/write) -- Not Implemented

+--------+-------------------------------------------------------------+
| ***Bit | ***Meaning***                                               |
| \#***  |                                                             |
+--------+-------------------------------------------------------------+
| 7..0   | Phase Adjust Magnitude BCO Clk FPIX Plane B                 |
+--------+-------------------------------------------------------------+
| 8      | Phase Adjust Direction BCO Clk FPIX Plane B                 |
|        |                                                             |
|        | 0 = Positive                                                |
|        |                                                             |
|        | 1 = Negative                                                |
+--------+-------------------------------------------------------------+
| *      | *Unused*                                                    |
| 15..9* |                                                             |
+--------+-------------------------------------------------------------+

###  {#section-2 .unnumbered}

### Control Register E: Address 0x0018 (read/write) -- Pulse Out Control 

+--------+-------------------------------------------------------------+
| ***Bit | ***Meaning***                                               |
| \#***  |                                                             |
+--------+-------------------------------------------------------------+
| 3..0   | Pulse Frequency Selection. Sets frequency of pulses.        |
|        | Formula is BCO freq/(2\^(N+1)) where N is 4 bit value from  |
|        | 0 to 15. Frequencies shown below are with BCO freq =        |
|        | 7.8125Mhz                                                   |
|        |                                                             |
|        | 0000 = 3.91MHz                                              |
|        |                                                             |
|        | 0001 = 1.95MHz                                              |
|        |                                                             |
|        | 0010 = 977kHz                                               |
|        |                                                             |
|        | 0011 = 488kHz                                               |
|        |                                                             |
|        | 0100 = 244kHz                                               |
|        |                                                             |
|        | 0101 = 122kHz                                               |
|        |                                                             |
|        | 0110 = 61kHz                                                |
|        |                                                             |
|        | 0111 = 31kHz                                                |
|        |                                                             |
|        | 1000 = 15kHz                                                |
|        |                                                             |
|        | 1001 = 7.6kHz                                               |
|        |                                                             |
|        | 1010 = 3.8kHz                                               |
|        |                                                             |
|        | 1011 = 1.9kHz                                               |
|        |                                                             |
|        | 1100 = 954Hz                                                |
|        |                                                             |
|        | 1101 = 477Hz                                                |
|        |                                                             |
|        | 1110 = 238Hz                                                |
|        |                                                             |
|        | 1111 = 119Hz                                                |
+--------+-------------------------------------------------------------+
| 4      | Clk Edge Selection. Selects BCO Clock edge Pulse Out is     |
|        | sensitive to                                                |
|        |                                                             |
|        | 0 = Pulse Out on falling edge of BCO Clock                  |
|        |                                                             |
|        | 1 = Pulse Out on rising edge of BCO Clock                   |
+--------+-------------------------------------------------------------+
| *      | *Unused*                                                    |
| 14..5* |                                                             |
+--------+-------------------------------------------------------------+
| 15     | Pulse Out Reset. When Pulse Out Reset transitions from '1'  |
|        | to '0', pulse train count begins.                           |
+--------+-------------------------------------------------------------+

###  {#section-3 .unnumbered}

### Control Register F: Address 0x001C (read/write) -- Pulse Out Train Length

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  15..0     Length (number of pulses) of Pulse Train. When set to 0x0000,
            Pulse Out is free running.
  --------- -------------------------------------------------------------

###  {#section-4 .unnumbered}

### Control Register G: Address 0x0020 (read/write) -- Calibration Control

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  7..0      Number of sequential BCO Clocks sent after Pulse Out if
            Calibration Mode is enabled.

  8         Enable "Calibration Mode"

  *15..9*   *Unused*
  --------- -------------------------------------------------------------

###  {#section-5 .unnumbered}

### Plane A ID Register: Address 0x0030 (read/write)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  3..0      Four bit Plane ID for Plane A

  15..4     *Unused*
  --------- -------------------------------------------------------------

###  {#section-6 .unnumbered}

### Plane B ID Register: Address 0x0034 (read/write)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  3..0      Four bit Plane ID for Plane B

  15..4     *Unused*
  --------- -------------------------------------------------------------

### Receive Window Register: Address 0x0038 (read/write)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  15..0     Size of receive window in terms of readout clock cycles after
            a trigger signal is received.
  --------- -------------------------------------------------------------

###  {#section-7 .unnumbered}

### Max Data Register: Address 0x003C (read/write) -- Not Implemented

+--------+-------------------------------------------------------------+
| ***Bit | ***Meaning***                                               |
| \#***  |                                                             |
+--------+-------------------------------------------------------------+
| 15..0  | Maximum number of sequential FPIX data words allowed to     |
|        | receive in terms of readout clock cycles. If this value is  |
|        | reached, the remaining FPIX data is ignored until a reset   |
|        | is received.                                                |
|        |                                                             |
|        | 0xFFFF = Default. This value indicates no maximum           |
|        | sequential words.                                           |
+--------+-------------------------------------------------------------+

##  {#section-8 .unnumbered}

## FPIX0 Specific Registers

This section TBD.

## FPIX1 Specific Registers

### FPIX1 Interface Plane A: Address 0x0100 (read/write)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  0         Token_In Plane A

  1         Shift_In Plane A

  2         Shift_CLK Plane A

  3         Trigger_Accept Plane A

  4         Program Reset Plane A

  5         Data Reset Plane A

  6         Load Kill Plane A

  7         ReadClk Plane A

  8         *Undefined*

  9         BCOClk Plane A

  10        *Undefined*

  11        *Undefined*

  12        Reg0 Plane A

  13        Reg1 Plane A

  14        Reg2 Plane A

  15        *Undefined*
  --------- -------------------------------------------------------------

###  {#section-9 .unnumbered}

###  {#section-10 .unnumbered}

### FPIX1 Interface Plane B: Address 0x0104 (read/write)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  0         Token_In Plane B

  1         Shift_In Plane B

  2         Shift_CLK Plane B

  3         Trigger_Accept Plane B

  4         Program Reset Plane B

  5         Data Reset Plane B

  6         Load Kill Plane B

  7         ReadClk Plane B

  8         *Undefined*

  9         BCOClk Plane B

  10        *Undefined*

  11        *Undefined*

  12        Reg0 Plane B

  13        Reg1 Plane B

  14        Reg2 Plane B

  15        *Undefined*
  --------- -------------------------------------------------------------

## preFPIX2tb Specific Registers

### preFPIX2tb Interface Plane A: Address 0x0100 (read/write)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  0         Shift_Control Plane A

  1         Shift_In Plane A

  2         *Undefined*

  3         *Undefined*

  4         Program Reset Plane A

  5         Reset Plane A

  6         MasterReject Plane A

  7         ReadClk Plane A

  8         *Undefined*

  9         BCOClk Plane A

  10        *Undefined*

  11        ChipSend Plane A

  15..12    *Undefined*
  --------- -------------------------------------------------------------

#  {#section-11 .unnumbered}

### preFPIX2tb Interface Plane B: Address 0x0104 (read/write)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  0         Shift_Control Plane B

  1         Shift_In Plane B

  2         *Undefined*

  3         *Undefined*

  4         Program Reset Plane B

  5         Reset Plane B

  6         MasterReject Plane B

  7         ReadClk Plane B

  8         *Undefined*

  9         BCOClk Plane B

  10        *Undefined*

  11        ChipSend Plane B

  15..12    *Undefined*
  --------- -------------------------------------------------------------

#   {#section-12 .unnumbered}

#  {#section-13 .unnumbered}

### preFPIX2tb Interface Plane A: Address 0x0108 (read only)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  0         KillShiftOut Plane A

  1         CoreHasData Plane A

  2         CoreHit Plane A

  15..3     *Undefined*
  --------- -------------------------------------------------------------

#  {#section-14 .unnumbered}

### preFPIX2tb Interface Plane B: Address 0x011C (read only)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  0         KillShiftOut Plane B

  1         CoreHasData Plane B

  2         CoreHit Plane B

  15..3     *Undefined*
  --------- -------------------------------------------------------------

## preFPIX2i Specific Registers

### preFPIX2i Interface Plane A: Address 0x0100 (read/write)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  0         Shift_Select Plane A

  1         Shift_In Plane A

  2         Shift Clk Plane A

  3         *Undefined*

  4         Ki Reset Plane A

  5         Reset Plane A

  6         MasterReject Plane A

  7         ReadClk Plane A

  8         *Undefined*

  9         BCOClk Plane A

  10        *Undefined*

  11        ChipSend Plane A

  15..12    *Undefined*
  --------- -------------------------------------------------------------

#  {#section-15 .unnumbered}

### preFPIX2i Interface Plane B: Address 0x0104 (read/write)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  0         Shift_Select Plane B

  1         Shift_In Plane B

  2         Shift Clk Plane B

  3         *Undefined*

  4         Ki Reset Plane B

  5         Reset Plane B

  6         MasterReject Plane B

  7         ReadClk Plane B

  8         *Undefined*

  9         BCOClk Plane B

  10        *Undefined*

  11        ChipSend Plane B

  15..12    *Undefined*
  --------- -------------------------------------------------------------

#  {#section-16 .unnumbered}

### preFPIX2i Interface Plane A: Address 0x0108 (read only)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  0         ShiftOut Plane A

  1         CoreHasData Plane A

  2         CoreHit Plane A

  3         Inj_ShiftOut Plane A

  15..4     *Undefined*
  --------- -------------------------------------------------------------

#  {#section-17 .unnumbered}

### preFPIX2i Interface Plane B: Address 0x011C (read only)

  --------- -------------------------------------------------------------
  ***Bit    ***Meaning***
  \#***     

  0         ShiftOut Plane B

  1         CoreHasData Plane B

  2         CoreHit Plane B

  3         Inj_ShiftOut Plane B

  15..4     *Undefined*
  --------- -------------------------------------------------------------

# PTA/PMC Interface

Tables 2 and 3 describe the pin assignments for the JN1 and JN2
interface respectively.

[]{#__RefHeading___Toc50977041 .anchor}*Table 2. JN1 pin assignment
PTA/PMC interface.*

+---+---------+----------+----+---+------+---------+----------+----+
| * |         |          |    |   |      |         |          |    |
| * |         |          |    |   |      |         |          |    |
| J |         |          |    |   |      |         |          |    |
| N |         |          |    |   |      |         |          |    |
| 1 |         |          |    |   |      |         |          |    |
| o |         |          |    |   |      |         |          |    |
| n |         |          |    |   |      |         |          |    |
| P |         |          |    |   |      |         |          |    |
| T |         |          |    |   |      |         |          |    |
| A |         |          |    |   |      |         |          |    |
| ( |         |          |    |   |      |         |          |    |
| " |         |          |    |   |      |         |          |    |
| o |         |          |    |   |      |         |          |    |
| l |         |          |    |   |      |         |          |    |
| d |         |          |    |   |      |         |          |    |
| " |         |          |    |   |      |         |          |    |
| P |         |          |    |   |      |         |          |    |
| T |         |          |    |   |      |         |          |    |
| A |         |          |    |   |      |         |          |    |
| ) |         |          |    |   |      |         |          |    |
| a |         |          |    |   |      |         |          |    |
| n |         |          |    |   |      |         |          |    |
| d |         |          |    |   |      |         |          |    |
| P |         |          |    |   |      |         |          |    |
| M |         |          |    |   |      |         |          |    |
| C |         |          |    |   |      |         |          |    |
| * |         |          |    |   |      |         |          |    |
| * |         |          |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| * | **Sc    | **Func   |    |   | *    | **Sc    | **Func   | *  |
| * | hematic | tional** |    |   | *Pin | hematic | tional** | *I |
| P | S       |          |    |   | \#** | S       |          | /O |
| i | ignal** | **Signal |    |   |      | ignal** | **Signal | \* |
| n |         | Name**   |    |   |      |         | Name**   | ** |
| \ | *       |          |    |   |      | *       |          |    |
| # | *Name** |          |    |   |      | *Name** |          |    |
| * |         |          |    |   |      |         |          |    |
| * |         |          |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 1 | JN1_S0  | L        |    |   | 2    | -12V    |          |    |
|   |         | AD_IN(0) |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 3 | Ground  |          |    |   | 4    | JN1_S1  | L        | I  |
|   |         |          |    |   |      |         | AD_IN(1) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 5 | JN1_S2  | L        |    |   | 6    | JN1_S3  | L        | I  |
|   |         | AD_IN(2) |    |   |      |         | AD_IN(3) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 7 | J       |          |    |   | 8    | 5V      |          |    |
|   | TAG_TDI |          |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 9 | JN1_S4  | L        |    |   | 10   | JN1_S5  | L        | I  |
|   |         | AD_IN(4) |    |   |      |         | AD_IN(5) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 1 | Ground  |          |    |   | 12   | JN1_S6  | L        | I  |
| 1 |         |          |    |   |      |         | AD_IN(6) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 1 | CLK2    | S        |    |   | 14   | Ground  |          |    |
| 3 |         | HIFT_CLK |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 1 | Ground  |          |    |   | 16   | CLK2LK  |          |    |
| 5 |         |          |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 1 | CLK2FB  |          |    |   | 18   | 5V      |          |    |
| 7 |         |          |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 1 | 3.      |          |    |   | 20   | JN1_S9  | L        | I  |
| 9 | 3V(I/O) |          |    |   |      |         | AD_IN(7) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 2 | JN1_S10 | L        |    |   | 22   | JN1_S11 | L        | I  |
| 1 |         | AD_IN(8) |    |   |      |         | AD_IN(9) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 2 | JN1_S12 | LA       |    |   | 24   | Ground  |          |    |
| 3 |         | D_IN(10) |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 2 | Ground  |          |    |   | 26   | JN1_S13 | LA       | I  |
| 5 |         |          |    |   |      |         | D_IN(11) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 2 | JN1_S14 | LA       |    |   | 28   | JN1_S15 | LA       | I  |
| 7 |         | D_IN(12) |    |   |      |         | D_IN(13) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 2 | JN1_S16 | LA       |    |   | 30   | 5V      |          |    |
| 9 |         | D_IN(14) |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 3 | 3.      |          |    |   | 32   | JN1_S17 | LA       | I  |
| 1 | 3V(I/O) |          |    |   |      |         | D_IN(15) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 3 | JN1_S18 | LA       |    |   | 34   | Ground  |          |    |
| 3 |         | D_OUT(0) |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 3 | Ground  |          |    |   | 36   | JN1_S19 | LA       | O  |
| 5 |         |          |    |   |      |         | D_OUT(1) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 3 | JN1_S20 | LA       |    |   | 38   | 5V      |          |    |
| 7 |         | D_OUT(2) |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 3 | Ground  |          |    |   | 40   | JN1_S21 | LA       | O  |
| 9 |         |          |    |   |      |         | D_OUT(3) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 4 | JN1_S22 | LA       |    |   | 42   | JN1_S23 | LA       | O  |
| 1 |         | D_OUT(4) |    |   |      |         | D_OUT(5) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 4 | JN1_S24 | LA       |    |   | 44   | Ground  |          |    |
| 3 |         | D_OUT(6) |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 4 | 3.      |          |    |   | 46   | JN1_S25 | LA       | O  |
| 5 | 3V(I/O) |          |    |   |      |         | D_OUT(7) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 4 | JN1_S26 | LA       |    |   | 48   | JN1_S27 | LA       | O  |
| 7 |         | D_OUT(8) |    |   |      |         | D_OUT(9) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 4 | JN1_S28 | LAD      |    |   | 50   | 5V      |          |    |
| 9 |         | _OUT(10) |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 5 | Ground  |          |    |   | 52   | JN1_S29 | LAD      | O  |
| 1 |         |          |    |   |      |         | _OUT(11) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 5 | JN1_S30 | LAD      |    |   | 54   | JN1_S31 | LAD      | O  |
| 3 |         | _OUT(12) |    |   |      |         | _OUT(13) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 5 | JN1_S32 | LAD      |    |   | 56   | Ground  |          |    |
| 5 |         | _OUT(14) |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 5 | 3.      |          |    |   | 58   | JN1_S33 | LAD      | O  |
| 7 | 3V(I/O) |          |    |   |      |         | _OUT(15) |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 5 | JN1_S34 | WR_EN    |    |   | 60   | JN1_S35 | ALE      | I  |
| 9 |         |          |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 6 | JN1_S36 | PCI_CLK  |    |   | 62   | 5V      |          |    |
| 1 |         |          |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| 6 | Ground  |          |    |   | 64   | EEDATA  |          |    |
| 3 |         |          |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+
| * |         |          |    |   |      |         |          |    |
| \ |         |          |    |   |      |         |          |    |
| * |         |          |    |   |      |         |          |    |
| R |         |          |    |   |      |         |          |    |
| e |         |          |    |   |      |         |          |    |
| l |         |          |    |   |      |         |          |    |
| a |         |          |    |   |      |         |          |    |
| t |         |          |    |   |      |         |          |    |
| i |         |          |    |   |      |         |          |    |
| v |         |          |    |   |      |         |          |    |
| e |         |          |    |   |      |         |          |    |
| t |         |          |    |   |      |         |          |    |
| o |         |          |    |   |      |         |          |    |
| P |         |          |    |   |      |         |          |    |
| M |         |          |    |   |      |         |          |    |
| C |         |          |    |   |      |         |          |    |
| * |         |          |    |   |      |         |          |    |
+---+---------+----------+----+---+------+---------+----------+----+

[]{#__RefHeading___Toc50977042 .anchor}*Table 3. JN2 pin assignment
PTA/PMC interface.*

+----+----------+----------+----+---+----+----------+----------+----+
| *  |          |          |    |   |    |          |          |    |
| *J |          |          |    |   |    |          |          |    |
| N2 |          |          |    |   |    |          |          |    |
| on |          |          |    |   |    |          |          |    |
| P  |          |          |    |   |    |          |          |    |
| TA |          |          |    |   |    |          |          |    |
| (" |          |          |    |   |    |          |          |    |
| ol |          |          |    |   |    |          |          |    |
| d" |          |          |    |   |    |          |          |    |
| PT |          |          |    |   |    |          |          |    |
| A) |          |          |    |   |    |          |          |    |
| a  |          |          |    |   |    |          |          |    |
| nd |          |          |    |   |    |          |          |    |
| P  |          |          |    |   |    |          |          |    |
| MC |          |          |    |   |    |          |          |    |
| ** |          |          |    |   |    |          |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| *  | **S      | **Func   | *  |   | *  | **S      | **Func   | *  |
| *P | chematic | tional** | *I |   | *P | chematic | tional** | *I |
| in | Signal** |          | /O |   | in | Signal** |          | /O |
| \# |          | **Signal | \* |   | \# |          | **Signal | \* |
| ** | **Name** | Name**   | ** |   | ** | **Name** | Name**   | ** |
+----+----------+----------+----+---+----+----------+----------+----+
| 1  | 12V      |          |    |   | 2  | JN2_S0   | DATA(0)  | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 3  | JN2_S1   | DATA(1)  | O  |   | 4  | JN2_S2   | DATA(2)  | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 5  | JN2_S3   | DATA(3)  | O  |   | 6  | Ground   |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 7  | Ground   |          |    |   | 8  | JN2_S4   | DATA(4)  | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 9  | JN2_S5   | DATA(5)  | O  |   | 10 | JN2_S6   | DATA(6)  | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 11 | JTAG_TCK |          |    |   | 12 | 3.3V     |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 13 | JN2_S7   | DATA(7)  | O  |   | 14 | JTAG_TMS |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 15 | 3.3V     |          |    |   | 16 | JTAG_TDO |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 17 | JN2_S8   | DATA(8)  | O  |   | 18 | Ground   |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 19 | JN2_S9   | DATA(9)  | O  |   | 20 | JN2_S10  | DATA(10) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 21 | Ground   |          |    |   | 22 | JN2_S11  | DATA(11) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 23 | JN2_S12  | DATA(12) | O  |   | 24 | 3.3V     |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 25 | JN2_S13  | DATA(13) | O  |   | 26 | JN2_S14  | DATA(14) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 27 | 3.3V     |          |    |   | 28 | JN2_S15  | DATA(15) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 29 | JN2_S16  | DATA(16) | O  |   | 30 | Ground   |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 31 | JN2_S17  | DATA(17) | O  |   | 32 | JN2_S18  | DATA(18) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 33 | Ground   |          |    |   | 34 | JN2_S19  | DATA(19) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 35 | JN2_S20  | DATA(20) | O  |   | 36 | 3.3V     |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 37 | Ground   |          |    |   | 38 | JN2_S21  | DATA(21) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 39 | JN2_S22  | DATA(22) | O  |   | 40 | Ground   |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 41 | 3.3V     |          |    |   | 42 | JN2_S23  | DATA(23) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 43 | JN2_S24  | DATA(24) | O  |   | 44 | Ground   |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 45 | JN2_S25  | DATA(25) | O  |   | 46 | JN2_S26  | DATA(26) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 47 | Ground   |          |    |   | 48 | JN2_S27  | DATA(27) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 49 | JN2_S28  | DATA(28) | O  |   | 50 | 3.3V     |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 51 | JN2_S29  | DATA(29) | O  |   | 52 | JN2_S30  | DATA(30) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 53 | 3.3V     |          |    |   | 54 | JN2_S31  | DATA(31) | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| 55 | JN2_S32  | D        | O  |   | 56 | Ground   |          |    |
|    |          | ATAVALID |    |   |    |          |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 57 | JN2_S33  | SHIFT_IN | I  |   | 58 | JN2_S34  | S        | O  |
|    |          |          |    |   |    |          | HIFT_OUT |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 59 | Ground   |          |    |   | 60 | JN2_S35  | S        | O  |
|    |          |          |    |   |    |          | HIFT_SEL |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 61 | JN2_S36  | *Unused* |    |   | 62 | 3.3V     |          |    |
+----+----------+----------+----+---+----+----------+----------+----+
| 63 | Ground   |          |    |   | 64 | CLK4     | DATA_CLK | O  |
+----+----------+----------+----+---+----+----------+----------+----+
| *  |          |          |    |   |    |          |          |    |
| \* |          |          |    |   |    |          |          |    |
| Re |          |          |    |   |    |          |          |    |
| la |          |          |    |   |    |          |          |    |
| ti |          |          |    |   |    |          |          |    |
| ve |          |          |    |   |    |          |          |    |
| to |          |          |    |   |    |          |          |    |
| PM |          |          |    |   |    |          |          |    |
| C* |          |          |    |   |    |          |          |    |
+----+----------+----------+----+---+----+----------+----------+----+

# FPIX0 Interface

This section TBD.

[]{#__RefHeading___Toc50977043 .anchor}*Fig. 16. Pin assignment for
FPIX0 interface.*

# ![](media/image18.wmf){width="5.946527777777778in" height="6.2444444444444445in"}FPIX1 Interface

[]{#__RefHeading___Toc50977044 .anchor}*Fig. 17. Pin assignment for
FPIX1 interface.*

# PreFPIX2 Interface

[]{#__RefHeading___Toc50977045
.anchor}![](media/image19.wmf){width="5.905555555555556in"
height="6.444444444444445in"}*Fig. 18. Pin assignment for FPIX2i and
FPIX2tb interface.*

# References

\[1\] PTA documentation

\[2\] PMC documentation

\[3\] FPIX0 inner board documentation

\[4\] FPIX1 inner board documentation

\[5\] FPIX2 inner board documentation