A TECHNIQUE FOR ASSESSING THE MOISTURE RESISTANCE OF PEMs USING MOS TEST
STRUCTURES.

Alexander Teverovsky, Ph.D.

UNISYS / Goddard operations

Alexander.A.Teverovsky.1@gsfc.nasa.gov

ABSTRACT

A new technique for assessing the moisture resistance of PEMs is based
on measurements of a time-varying capacitance of an MOS-structure with a
large perimeter-to-area ratio of the metal electrode. When an inversion
voltage is applied, the capacitance of the structure will increase with
time due to lateral charge spreading. The rate of the charge
redistribution and the magnitude of the change in capacitance depend on
the moisture content on the die surface and on some special features of
the molding compound - die interaction. These conditions can be
characterized by measuring the specific resistivity of the die-molding
compound interface, ρ~s~. The C(t) technique extends the limit of ρ~s~
measurements up to 10^21^ ohms. Experiments with different encapsulating
materials proved the effectiveness of this technique for packaging
evaluations. A good correlation between ρ~s~ and median
time-to-corrosion failures was shown.

INTRODUCTION

Due to moisture permeability of polymeric materials, Plastic
Encapsulated Microcircuits (PEMs) always have a certain moisture content
on the die surface. The mechanisms of PEMs' degradation due to moisture
absorption (such as corrosion, leakage current, charge instability,
etc.) strongly depend on the quality of the die-package interface and
its ability to prevent excessive moisture adsorption. Debonding between
molding compound and die is considered as a major reliability concern
for PEMs used in surface mount applications. Different types of comb
pattern sensors have been commonly used since the 1970s to measure the
surface specific resistivity, ρ~S,~ of oxide films and to find its
relation to corrosion processes \[1-3\]. Use of this technique for PEMs
is hindered due to the surface conductivity of the package and the
volume conductivity of a molding compound which contains moisture.
Normally, leakage currents in plastic packages would not exceed 10^-12^
A at 10 V, but, in some cases, these can be much higher \[4\].
Typically, during ρ~S~ measurements, a low current sensitivity is
10^-12^ A, an equivalent pattern size is 10 μm of width and 100 mm of
length, and an applied voltage does not exceed 100V. With these
parameters, the technique is limited to a maximum sensitivity of 10^18^
ohms for ρ~S~. A low frequency capacitance measurement technique
developed by Merrett, Sim, and Bryan \[5\], is capable of being used
directly with some types of microcircuits but is limited to a
sensitivity of 10^14^ ohms. Besides, changes in the frequency dependence
of the dielectric permittivity of the molding compound (and changes in
the capacitance between the package leads) during humid testing, may
introduce errors in the calculation of ρ~S~

Moisture resistance and reliability of PEMs have been significantly
increased over the last decade. The current trend is toward use of PEMs
in highly reliable applications (military and aerospace) and in a harsh
environments. New packaging systems require a more sensitive technique
for assessing moisture resistance. A new technique, described in this
article, is based on a lateral charge spreading phenomenon and employs a
metal-oxide-silicon (MOS) structure with a large perimeter-to-area
ratio. The charge spreading process had been well known since 70th \[6\]
and was one of the major cause of excessive leakage currents and
failures of the first semiconductor devices and microcircuits
encapsulated in polymers.

When an inversion voltage is applied to an MOS structure, the
capacitance will increase with time due to a lateral spreading of the
inversion layer area. The rate of this process depends on the rate of
charging of the distributed oxide capacitance and is controlled by the
surface resistivity. This allows one to calculate ρ~s~ using C(t)
measurements. The technique uses integration of the surface current on
the distributed oxide capacitance which allows extending the limit of
ρ~s~ measurements to 10^21^ ohms. Experiments with different
encapsulating materials proved the effectiveness of the technique for
packaging quality evaluation. A good correlation between ρ~s~ and median
time to corrosion failure was shown.

TECHNIQUE

Let us consider an MOS structure which is formed on n-type silicon with
a strip metal electrode of the width d (see Figure 1).

![](media/image1.png){width="3.3381944444444445in"
height="1.7506944444444446in"}

Figure 1. MOS-structure with a strip metal electrode.

A second electrode on the oxide surface is placed equidistantly at both
sides from the first at a distance *l* and is connected to the
substrate. Capacitance of this structure as a function of applied
voltage (C-V characteristic) is shown in Figure 2. Let V~0~ be a
negative voltage which is applied to the first electrode. V~0~\<V~i~,
whereV~i~ is the potential which causes formation of an inversion layer.
Due to some conductivity of the oxide surface, the oxide areas around
the first electrode will charge with time to a potential -V(x,t). When
-V(x,t) \> -V~i~, the depletion and inversion layers expand thus
resulting in an increase in capacitance (see Figure 3).

![](media/image2.png){width="4.377083333333333in"
height="2.5479166666666666in"}

Figure 2. MOS-capacitance diagram (a) and capacitance variation with
voltage (b). The flat band capacitance C~fb~ and the corresponding
voltage V~fb~ which are used in C-V technique to calculate the value of
the oxide charge can be used to calculate the inversion voltage V~i~.

![](media/image3.png){width="4.377083333333333in"
height="2.217361111111111in"}

Figure 3. MOS capacitance after charge spreading.

Potential distribution along the surface of the MOS-structure, V(x,t),
can be calculated with the help of an equivalent diagram (see Figure 4)
which is represented as an R-C-G chain, where R is the surface
resistance, C is the capacitance of the oxide film, and G is the
volumetric conductivity of the oxide. Normally, oxide films have very
low volumetric conductivities and can be neglected. Therefore, the
potential distribution can be described by a simple telegraph equation:

$\frac{¶V}{¶t} = (\rho_{s}C_{0}^{0})^{- 1}\frac{¶^{2}V}{¶X^{2}}$, (1)

where C~0~^0^ is the specific (per unit area) capacitance of the oxide.

![](media/image4.png){width="3.7333333333333334in"
height="3.2430555555555554in"}

Figure 4. Equivalent diagram of a MOS-structure.

Using dimensionless coordinates: $c = \frac{X}{l}$,
$u = \frac{V(X,t)}{V_{0}}$, and $t = \frac{t}{J}$, where
$J = \frac{\rho_{s}l^{2}C_{0}^{0}}{p^{2}}$, equation (1) can be
simplified as follows:

$\frac{¶u}{\text{¶t}} = \frac{¶^{2}u}{\text{¶c}^{2}}$ (2)

The initial and boundary conditions are:\
u(χ,0) = 0 at 0 \< χ \< l\
u(0, τ) = 1 (3)\
u(1, τ) = 0

The solution for (2), (3) is:

$u(c,t) = 1 - c + 2\sum_{m = 1}^{¥}{( - 1)^{m}\frac{\text{sin}\left( mp(1 - c) \right)}{mp}\text{exp}( - m^{2}t)}$
(4)

Figure 5 shows potential distributions calculated at different τ. At τ ≥
3, a steady-state condition exists and *θ* is the characteristic time of
this process. Using the plot in Figure 5, the dependence of the
inversion area size on time, X~i~(t), can be obtained from the following
equation:

$V(X_{i},t) = V_{i}$ (5)

![](media/image5.png){width="3.3965277777777776in"
height="2.9208333333333334in"}

Figure 5. Calculated potential distribution along the surface of an
MOS-structure.

An increase in inversion area, X~i,~ results in an increase in the
capacitance of the MOS-structure, C. In the frequency range of 100 Hz to
100 KHz, the resistance of the inversion layer is negligible compared
with the capacitance impedance \[7\]. In this case, the capacitance will
depend only on the size of the inversion area:

$C = \frac{C_{0}C_{d}\left( 1 + 2\frac{X_{i}}{d} \right)}{C_{0} + C_{d}\left( 1 + 2\frac{X_{i}}{d} \right)}$,
(6)

where $C_{d} = \frac{C_{0}C_{i}}{C_{0} - C_{i}}$ is the capacitance of
the depletion layer.

This equation allows one to calculate the size of the inversion area
using the capacitance measurements:

$X_{i} = \frac{d}{2}\frac{C_{0}dC}{C_{i}(C_{0} - C)}$, (7)

where *δC=C-C~i\ ~*(see Figure 3).

The MOS capacitance parameters, C~0~ and C~i~, as well as the potential
of inversion V~i~, can be found from the initial C-V characteristic (see
Figure 2) or from measurements of an additional MOS capacitance
structure with a low perimeter-to-area ratio.

Using the plot of u(χ,τ), which is shown in Figure 5, and the size of
inversion area, X~i~ , which may be calculated using Eq.(7), one can
then determine the corresponding rated time, τ, and calculate the
surface resistivity as follows:

$\rho_{s} = \frac{p^{2}t}{l^{2}{tC}_{0}^{0}}$ (8)

To illustrate, Figure 6 displays the relationship of ρ~s~ and *δC* for
different values of u~i~, where u~i~ = V~i~/V~0~. Calculations have been
made for an MOS-structure consisting of n-type of silicon with 20 ohm-cm
resistivity and an 1100Å film of thermally grown oxide. This MOS
structure featured the following parameters: d = 10 μm, l = 60 μm, C~0~
= 100 pF, C~i~ = 17 pF, V~i~ = -1.5 V. The measurement time, t, was 10
minutes.

![](media/image6.png){width="2.407638888888889in"
height="2.277083333333333in"}

Figure 6. Surface resistivity-capacitance relationship as a function of
the rated inversion potential u~i~.

As can be seen, capacitance changes of several tenths of picofarads
correspond to a ρ~s~ of more than 10^20^ ohms. Similar changes can be
reliably measured using a digital R-C-L bridge. When applied to MOS
structures with larger perimeter-to-area ratios and thinner oxides, the
sensitivity of this technique can be increased to more than 10^21^ ohms.
A software routine has been developed which allows calculation of the
specific resistivity of a silicon oxide-molding compound interface using
the above-described capacitance variance measurements. It allows
calculation of ρ~s~ for any measurement time and for MOS structures with
various dimentional and electrical parameters.

To check how the developed model correlates with experimental data,
measurements, at room ambient conditions (T=22°C, RH=43%), were taken
for unencapsulated MOS structures. These structures had the following
characteristics: d = 15 μm, l =60 μm. C~0~=85 pF, C~i~= 23 pF, V~i~=-2V,
and V~0~=-5V. Experimental and calculated C(t) curves were observed to
be very similar (see Figure 7) conforming the validity of the model
used.

![](media/image7.png){width="4.3909722222222225in"
height="2.7909722222222224in"}

Figure 7. Experimental (solid lines) and calculated (dash lines) C(t)
relationships for\
two MOS structures (22°C and 43% RH).

The results obtained using this technique were also compared with
calculations of surface resistivity using leakage current measurements.
Leakage currents usually decrease slowly with time due to charging of
the distributed capacitance and due to polarization of electrodes and
oxide. To decrease the error caused by polarization, measurements were
made at a steady-state condition after the voltage (5V) had been applied
for 30 minutes. Three groups of samples, each of which was manufactured
at a different time, were tested using both techniques. Results (see
Table 1) were fairly consistent for each sample in which ρ~s~ was less
than 1×10^16^ ohms. For larger resistivities, the C(t) technique
resulted in surface resistivities with values which were 3 to 8 times
higher. This was likely due to the presence of parasitic leakage
currents during the measurements.

Table 1. Comparison Between ρ~s~ Measurements Using C(t)\
and Leakage Current Techniques

  ------------ ------------ ----------------------- -----------------------
  **Group**    **Sample**   **ρ~s~ , ohms\          **ρ~s~ , ohms\
                            \[C(t)\]**              \[leakage current\]**

               1            1.5×10^15^              2×10^15^

  I            2            2×10^15^                2.2×10^15^

               3            3×10^15^                2.6×10^15^

               1            12×10^15^               7.5×10^15^

  II           2            7×10^15^                6×10^15^

               3            7×10^15^                5×10^15^

               1            1×10^17^                0.3×10^17^

  III          2            2.5×10^17^              0.3×10^17^

               3            0.8×10^17^              0.15×10^17^
  ------------ ------------ ----------------------- -----------------------

EXPERIMENT

The C(t) measurement technique was used to evaluate the quality of four
epoxy novolac molding compounds (EN-E11, EN-E91, EN-MP, and EN-HC) which
were obtained from two Japanese manufactures. A layout of the used test
vehicle which was used is shown in Figure 8. The structure contained two
types of MOS capacitors: a test capacitor with a large perimeter-to-area
ratio and a reference capacitor with a small perimeter-to-area ratio.
Aluminum lines were used for corrosion measurements. Thensoresistors,
which can be used to evaluate mechanical stresses, were olso included in
this vehicle, however, these were not used in this experiment. The test
capacitor featured a multiple-fingered electrode with a perimeter of 76
mm and an overall area of 0.65 mm^2^. The reference capacitor featured a
rectangular electrode of the same area and was used to extrapolate C~0~,
C~i~, and V~i~ parameter values for the MOS structure. Meandering
aluminum lines were used to evaluate materials' corrosivity. All test
vehicles were encapsulated in 16-lead DIP packages.

Ten samples with each type of encapsulating material were subjected to
pressure cooker testing (PCT) at 121°C and 100% RH. Additionally, the
samples encapsulated with EN-H were stored at 100% RH and at
temperatures of 20°C, 85°C, and 100°C to check temperature effects on
the interface resistivities. Periodically, the resistances of the
aluminum lines and ρ~s~ values (using C(t) technique) were measured at
room temperature. Resistance changes of more than 10% in the aluminum
lines were considered to be failures. Resistance to corrosion was
evaluated by calculating the median time to corrosion failures using
log-normal plots.

![](media/image8.png){width="4.735416666666667in"
height="3.9930555555555554in"}

Figure 8. Test structure layout.\
1 - MOS capacitance structure with large perimeter-to-area ratio; 19 -
equidistant electrode connected to the substrate (5); 20 - a reference
MOS capacitor;\
6-16, 10-18, and 11-17 - aluminum lines;\
2-3-4, 7-8-9, and 12-13-14-15 - groups of thensoresistors (were not used
during the experiment).

Figure 9 shows the time dependence of the interface resistivity during
humidity aging at different temperatures. At all temperatures, ρ~s~
initially remains high, but then drops approximately 5 to 6 orders of
magnitude. The approximate times, τ~r~, until ρ~s~ drops dramatically,
are shown in Table 2. Calculated times, τ~d~, which are required for
moisture to diffuse to the die surface, are also displayed. τ~d~
=4L^2^/π^2^D where D is the diffusion coefficient and L is the molding
compound thickness above the die. As shown, τ~r~ and τ~d~ are in
reasonably good agreement suggesting that no moisture penetration along
the lead-encapsulating material intrerface occurred.

![](media/image9.png){width="3.9791666666666665in"
height="3.1055555555555556in"}

Figure 9. Effect of temperature on the interface resistivity during
humidity aging\
at 100%RH.

Table 2. Comparison of the times τ~r~ and τ~d~ (hours) for 16-lead DIP
packages.

  ---------------- ---------------- ------------- ------------- -------------
  **Parameter**    **Temperature,                               
                   °C**                                         

                   **20**           **85**        **100**       **120**

  **τ~r~**         10,000           400           120           50

  **τ~d~**         4500             350           95            35
  ---------------- ---------------- ------------- ------------- -------------

Figure 10 shows changes in the interface resistivities obtained for
different encapsulating materials during PCT. All encapsulating
materials initially exhibited similar and high (\>5×10^19^ ohms) values
of ρ~s~ which then dropped after approximately 35-70 hours. This
suggests that all materials had similar diffusivity coefficients.
However, the interface resistivities of these materials, under
steady-state conditions, differed by approximately three orders of
value. This indicates essential differences in conditions at the
die-molding compound interfaces and results in significant differences
in the corrosion resistance of aluminum metallization.

Figure 11 shows the correlation between the median time to corrosion
failures τ~50~ and the interface resistivities for those materials
mentioned above, together with some other materials which were
investigated using the same technique.

![](media/image10.png){width="3.75in" height="2.66875in"}

Figure 10. Effect of molding compound on the interface resistivity.

![](media/image11.png){width="3.5770833333333334in"
height="2.745138888888889in"}

Figure 11. Median life for aluminum corrosion vs. interface resistivity
during PCT at 121°C and 100% RH.

CONCLUSION

-   A C(t) technique for measuring the specific resistivity of
    die-molding compound interfaces has been described. This technique
    utilizes an MOS capacitance structure with a large perimeter-to-area
    ratio as a sensor and is based on the lateral spread charging
    phenomenon.

-   A simple R-C equivalent circuit has been shown to be adequate to
    describe this lateral charge spreading phenomenon and the associated
    capacitance changes in the MOS structure. Calculations and
    experiments have shown that the technique allows calculation of
    specific resistivities up to 10^21^ ohms.

-   Different types of molding compounds exhibited similar times (35-70
    hours) for moisture to penetrate to the die surface during PCT at
    121°C/100%RH. However, these molding compounds exhibited die-molding
    compound interfaces with different specific resistivities ρ~s~
    (4×10^14^ ohms to 2×10^17^ ohms). The results of ρ~s~ calculations
    correlated well with the median life time of aluminum corrosion.

REFERENCES

1\. K.Tsubosaki, Y.Wakashima, N.Nagasima, "Rate-determining factor of
aluminum corrosion and a rapid method of assessing the moisture
resistance of plastic encapsulated LSI", 21st Ann. Proc. Reliab. Phys.,
pp. 83 - 89, 1983.

2\. R.B.Comizzoli, L.K.White, W.Kern, G.L.Schnable, D.A.Peters,
C.E.Tracy and R.D.Vibronek, "Corrosion of aluminum IC metallization with
defective surface passivation layer', 18st Ann. Proc. Reliab. Phys., pp.
282 - 292, 1980.

3\. S.P.Sim and R.W.Lawson, "The influence of plastic encapsulants and
passivation layers on the corrosion of thin aluminum films subjected to
humidity stress", 17st Ann. Proc. Reliab. Phys., pp. 103 - 112, 1979

4\. A.Teverovsky, "Degradation of encapsulating materials and plastic
packages for microcircuits under moisture environments", 6th
International workshop on moisture in microelectronics, NIST, 1996.

5\. R.P.Merrett, J.P.Bryant, and R.Studd, "An appraisal of high
temperature humidity stress tests for assessing plastic encapsulated
semiconductor components', 21st Ann. Proc. Reliab. Phys., pp. 71 - 82,
1983.

6\. E.R.Schlegel, G.L.Schnable, R.F.Schwarz, "Behaviour of surface ions
on semiconductor devices", IEEE Trans. on ED, v. ED-15, N12, p.973,
1968.

7\. A.Teverovsky, B.Omarov, T.Volkova, "Frequency dependence of the
inversion layer channels in MOS-structures", "Electrical relaxation in
microcircuits", pp. 30-34., MIEM, Moscow, 1988.