SUBCONTRACT TITLE**: University of Toledo Subcontract to**

CONTRACT:   RDJ-2-30630-20 (RESEARCH LEADING TO HIGH THROUGHPUT
MANUFACTURING OF THIN-FILM CDTE PV MODULES).

QUARTERLY TECHNICAL STATUS REPORT FOR: Phase 2

SUBMITTED TO: Ulal Harin

National Renewable Energy Laboratory

**PRINCIPAL INVESTIGATORS**: Victor Karpov, Diana Shvydka

University of Toledo,

Department of Physics and Astronomy,

2801 W Bancroft,

Toledo, OH 43606

This progress report covers second quarter of Phase 1 for the period
September 01 through December 30, 2003.

The report describes our activities in mapping and modeling large area
CdTe PV modules. Here we describe our estimate of nonuniformity related
loss.

NONUNIFORMITY LOSSES

In this study we discriminate between nonuniformity losses in individual
cells and large-area modules. In particular, we separately worked on two
problems: estimating nonuniformity losses at a cell and at a model
levels. Currently we are able to quantitatively characterize
nonuniformity losses at a cell level, but have only developed
qualitative understanding of module losses so far.

Shown in Fig. 1 are Voc maps of two modules together with their
corresponding histograms. These data are obtained for finished modules
that were laser scribed into sets of 116 x 56 cells, each square cell of
1 cm linear size. The histogram distribution parameters are interpreted
as follows.

We modeled each cell with a set of many micro-diodes connected in
parallel through a distributed (TCO) resistor, each of the micro-diodes
having its own random Voc. For simplicity, we used a bimodal Voc
distribution representing a mixture of bad (low Voc) and good (high Voc)
entities. Then a histogram gives an estimate of a bad micro-diode Voc as
the lowest cell Voc measured. In both cases the lowest Voc in the system
is found to be by approximately factor of 2 smaller than the highest
one, the latter representing the good micro-diode Voc. The distribution
standard deviation (*sd* in Fig. 1) was used to estimate the fraction
*n* of bad diodes, according to
$\text{sd} = \sqrt{n(1 - n)}{\Delta V}_{\text{oc}}$, where ∆V~oc~ is the
difference between the good and bad diode V~oc~s. Based on the
histograms of Fig. 1 and

![](media/image1.wmf){width="4.125196850393701in"
height="2.113779527559055in"}![](media/image2.wmf){width="2.6251968503937007in"
height="2.204724409448819in"}![](media/image3.wmf){width="4.25in"
height="2.190944881889764in"}![](media/image4.wmf){width="2.5in"
height="2.100787401574803in"}

Fig. 1. Open-circuit voltage maps and their corresponding histograms for
two modules.

other similar histograms we have estimated the typical parameters
∆V~oc~=0.3 -- 0.5 V and n= 0.05 -- 0.1.

Based on the above estimate we modeled an individual cell as a set of
above described diodes with bimodal Voc distribution (V~oc~ =
V~oc,\ max~ or V~oc~ = V~oc,min~) and fraction of bad diodes *n*.
Several parameters in such modeling remain ill defined, such as the
nonideality factor *A* and micro-diode series resistance *Rs*. We put
A=2 to reflect rather general trend in the available data; Rs was chosen
by trial and error to fit the observed I/V curves as close as possible.
Typical modeling results are shown in Fig. 2.

We were able to calculate the cell efficiency relative to that of a
hypothetical uniform cell composed of identical micro-diodes, each
having Voc averaged between V~oc~ = V~oc,\ max~ and V~oc~ = V~oc,min~.
With some degree of uncertainty related to unknown micro-diode
parameters we can assert that the nonuniformity loss for a cell is
always in the range of 10-20%.

![](media/image5.wmf){width="3.0in"
height="2.427952755905512in"}![](media/image6.wmf){width="2.958267716535433in"
height="2.4625984251968505in"}

Fig. 2. Examples of simulated I/V curves of laterally nonuniform cells
for two different Rs (measured in the units of AkT/qJsc, where q is the
electron charge and all other quantities have their standard meaning),
and a variety of bad diode fraction values.

This estimate will be further improved by collecting more detail about
individual micro-diode characteristics. For that purpose we has started
micro I/V mapping by AFM. This work is in progress.

One other nonuniformity diagnostic effort was based on mapping 10x10cm2
plates continuously covered with 5 nm thick Cr with sheet resistance *ρ*
of about 1kOhm. Such a high sheet resistance makes different
micro-regions in a plate electrically insulated. The characteristic size
of "independent" micro-regions was estimated as

$L = \sqrt{\frac{{\Delta V}_{\text{OC}}}{J_{\text{sc}}\rho}}$

And was varying in the range of 0.1mm to 10 cm depending on light
intensity. Our mapping results are shown in Fig. 3.

![](media/image7.wmf)Fig. 3. Ratio of the standard deviation in Voc over
its average value as calculated based on Voc mapping of 81 points taken
in different 10x10cm2 plates.

The dependencies in Fig. 3 have an S-shape, which we interpret as a
result of crossover between the regimes when L is much shorter than the
characteristic distance between bad diodes and the opposite limiting
case. From that we hope to independently estimate the fraction of bad
micro-diodes in a device and their characteristic geometrical
dimensions. This part of project is still in progress.

Finally, at the module level we work on the equivalent circuit explained
in Fig. 4.

Fig. 4. Equivalent circuit of large-area module with interconnects.

We have estimated the nonuniformity dimensions both in perpendicular
direction (\~ 0.5 cm) and along linear cell (\~ 2cm), the latter related
to the characteristic scribe resistance. While semi quantitatively we
can assert that this leads to the relative nonuniformity loss in the
range of 20-30% on the module level, more robust simulations are called
upon to estimate the module nonuniformity loss. We have been developing
software that would allow for more quantitative results. These attempts
were unsuccessful because of generic problems related to iterations of
exponentially strong functions in diode I/V characteristics. Currently
we have obtained more robust SPICE software and started the
nonuniformity loss modeling at the module level based on the equivalent
circuit in Fig. 4. This work is in progress, to be reported later.