### Preliminary report on MASDA wafer testing

## Abstract

This is a preliminary on the testing. It is meant to provide the
Michigan group with enough info to provide further direction and
feedback to the Fermilab group, if needed. The tone of the report is
very informal.

The key issue in the testing of the MASDA chips is to balance the risk
of throwing away good chips because the cuts were set too tight relative
to the performance of the testing setup versus accepting poorly
performing chips because the cuts were set too loose.

This choice must be guided by the numerology of the application- how
many chips are available vs how many chips are desired. We define 3
categories of chips: PERFECT- chips with no detectable abnormalities;
OK- chips with one or two abnormal channels and BAD chips- chips that
draw unusual power currents or show more than 2 abnormal channels. With
very lose cuts (i.e. each channel responds in SOME fashion) and no test
of the direction bit, we find:

  -------------------------- -------------- -------------- --------------
  CHIP TYPE:                 A              B              C

  Number of "perfect" chips  710            747            650

  Number of "bad" chips      48             56             62

  Number of "ok" chips       124            79             170
  -------------------------- -------------- -------------- --------------

The chips will be marked on the wafers with RED dots for bad chips and
GREEN dots for marginal or questionable chips. (These marks do not
affect the performance of the chips). Also a list will be produced with
the actual chip numbers of perfect bad and ok chips. For loose cuts
described in the text, the lists can be found in the attached EXCEL
spreadsheet. (The numbering of the chips on the wafers is also described
in this document)

## Report Body

In total, we tested 18 wafers. The wafers are numbered 1 through 18 for
simplicity, and the list of wafer serial numbers vs. this simple naming
scheme is shown here:

1 = 5902H197SEA0

2 = 5902H267SEA3

3 = 5902H273SEC5

4 = 5902H120SEF1

5 = 5902H118SEF1

6 = 5902H131SEG4

7 = 5902H031SEA0

8 = 5902H205SEB6

9 = 5902H130SEC2

10 = 5902H090SEA5

11 = 5902H051SEB5

12 = 5902H128SEC2

13 = 5902H278SEB6

14 = 5902H050SEE6

15 = 5902H039SEE4

16 = 5902H077SEG5

17 = 5902H024SEA7

18 = 5902H004SEG5

From now on, this report will only refer to the wafers by the simple
number 1 through 18.

For testing purposes, each wafer was divided into 49 reticles, with each
reticle having three variations of the MASDA chip: A, B, and C. Type C
is designed for packaging, with input pads around three sides. Types A
and B are designed for direct wire bonding to a detector, with double
bond rows. The B type has slightly lower bandwidth than the A type. Note
that not all the reticles on a wafer have full chips- in come cases the
reticle does not fit completely on the wafer and for those reticles, one
or more chips maybe bad. This is actually an aid to the testing, in
sense that we know that a particular chip position is not expected to
pass the test. The numbering of the chips on a wafer is illustrated in
Fig1.

  ------- ------- ------- ------- ------- ------- ------- ------- -------
                  46A     47A     48A     49A                     

                  46B     47B     48B     49B                     

                  46C     47C     48C     49C                     

  38A     39A     40A     41A     42A     43A     44A     45A     

  38B     39B     40B     41B     42B     43B     44B     45B     

  38C     39C     40C     41C     42C     43C     44C     45C     

  30A     31A     32A     33A     34A     35A     36A     37A     

  30B     31B     32B     33B     34B     35B     36B     37B     

  30C     31C     32C     33C     34C     35C     36C     37C     

  21A     22A     23A     24A     25A     26A     27A     28A     29A

  21B     22B     23B     24B     25B     26B     27B     28B     29B

  21C     22C     23C     24C     25C     26C     27C     28C     29C

  13A     14A     15A     16A     17A     18A     19A     20A     

  13B     14B     15B     16B     17B     18B     19B     20B     

  13C     14C     15C     16C     17C     18C     19C     20C     

  5A      6A      7A      8A      9A      10A     11A     12A     

  5B      6B      7B      8B      9B      10B     11B     12B     

  5C      6C      7C      8C      9C      10C     11C     12C     

                  1A      2A      3A      4A                      

                  1B      2B      3B      4B                      

                  1C      2C      3C      4C                      
  ------- ------- ------- ------- ------- ------- ------- ------- -------

Fig1

For illustration purposes, chip 1 of type A is colored red, chip 2 of
type B is colored yellow and chip 3 of type C is green.

Reticle 29 is incomplete for all 3 chip types. This chip should ALWAYS
test bad.

Chips 1,2,3,4 and 5 and 12 are incomplete for type C.

Chips 38 and 45 are incomplete for type A.

We have developed a tool for processing the raw data from the testing.
This tool is built in EXCEL using VBA.

The tool reads the raw data files, applies cuts and generates wafer
maps, reports and plots. The plots and reports can then be used to
further refine the cuts. It should be noted, that like most such "tools"
this one is in a permanent state of refinement. It is, however, mature
enough to be quite useful. "BAD CHIP CUTS" represent the limits at which
the entire chip is marked as bad. "BAD CHAN CUTS" represent limits at
which individual channels are marked as defective. The channel cuts are
separated by chip type and correspond to functional features of the
chip. For example, the SELECT1664 A cut is applied to A type chips by
comparing the readout from a given channel in 16 channel mode and 64
channel mode. The difference between the two is required to lie within
the limits indicated (inclusive).

The functional data used for the cuts is derived from the following raw
data, made in a series of 18 measurements (each measurement is itself an
average of 10 acquisition cycles.) The 18 different measurements are
detailed in Table 1 below. Internal settings are MASDA control bits,
external settings are controls on the tester board. The "speed" setting
controls the length of the integration period for the MASDA. The 18^th^
measurement is actually made in a separate sweep, by adding extra
capacitance to only one MASDA channel (ch 128) and repeating M1, M2 and
M3. However, the effect of the capacitance on CH128 is to saturate that
channel- we test for the expected saturation to appear in ONLY the
expected channel.

Table 1

+------+------+-------+------+------+------+-------+------+--------+
|      | # M  |       |      |      |      |       |      |        |
|      | ASDA |       |      |      |      |       |      |        |
|      |  set |       |      |      |      |       |      |        |
|      | ting |       |      |      |      |       |      |        |
+------+------+-------+------+------+------+-------+------+--------+
|      | #    |       |      |      |      | # Ext |      | C      |
|      | Inte |       |      |      |      | ernal |      | omment |
|      | rnal |       |      |      |      |       |      |        |
+------+------+-------+------+------+------+-------+------+--------+
| Meas | BANK | S     | PG   | BW   | DIR  | I     | S    |        |
|      |      | ELECT |      |      |      | nject | peed |        |
+------+------+-------+------+------+------+-------+------+--------+
| M1   | A    | 16    | 0    | 0    | UP   | 0V    | 0    | PED    |
+------+------+-------+------+------+------+-------+------+--------+
| M2   | A    | 16    | 0    | 0    | UP   | 0.8V  | 0    | BANK   |
+------+------+-------+------+------+------+-------+------+--------+
| M3   | B    | 16    | 0    | 0    | UP   | 0.8V  | 0    | BANK   |
+------+------+-------+------+------+------+-------+------+--------+
| M4   | A    | 64    | 0    | 0    | UP   | 0.8V  | 0    | SEL    |
+------+------+-------+------+------+------+-------+------+--------+
| M5   | B    | 64    | 0    | 0    | UP   | 0.8V  | 0    | SEL    |
+------+------+-------+------+------+------+-------+------+--------+
| M6   | A    | 16    | 0    | 0    | UP   | 0.8V  | 0    | PG     |
+------+------+-------+------+------+------+-------+------+--------+
| M7   | A    | 16    | 1    | 0    | UP   | 0.8V  | 0    | PG     |
+------+------+-------+------+------+------+-------+------+--------+
| M8   | A    | 16    | 2    | 0    | UP   | 0.8V  | 0    | PG     |
+------+------+-------+------+------+------+-------+------+--------+
| M9   | A    | 16    | 3    | 0    | UP   | 0.8V  | 0    | PG     |
+------+------+-------+------+------+------+-------+------+--------+
| M10  | A    | 16    | 0    | 0    | UP   | 2V    | 0    | BW     |
+------+------+-------+------+------+------+-------+------+--------+
| M11  | A    | 16    | 0    | 1    | UP   | 2V    | 0    | BW     |
+------+------+-------+------+------+------+-------+------+--------+
| M12  | A    | 16    | 0    | 2    | UP   | 2V    | 0    | BW     |
+------+------+-------+------+------+------+-------+------+--------+
| M13  | A    | 16    | 0    | 3    | UP   | 2V    | 0    | BW     |
+------+------+-------+------+------+------+-------+------+--------+
| M14  | A    | 16    | 0    | 3    | UP   | 2V    | 0    | SPD    |
+------+------+-------+------+------+------+-------+------+--------+
| M15  | A    | 16    | 0    | 3    | UP   | 2V    | 1    | SPD    |
+------+------+-------+------+------+------+-------+------+--------+
| M16  | A    | 16    | 0    | 3    | UP   | 2V    | 2    | SPD    |
+------+------+-------+------+------+------+-------+------+--------+
| M17  | A    | 16    | 0    | 3    | UP   | 2V    | 3    | SPD    |
+------+------+-------+------+------+------+-------+------+--------+
| DIR  | A    | 16    | 0    | 0    | DOWN | 0.8V  | 0    | Se     |
|      |      |       |      |      |      |       |      | parate |
|      |      |       |      |      |      |       |      | file   |
+------+------+-------+------+------+------+-------+------+--------+

These measurements are then used to create differences and ratios that
are better behaved than the raw measurements. The reason is simple- the
value of the charge injection capacitor on the MASDA is not very well
controlled and the values of M2 might vary by 40 counts from chip to
chip and wafer to wafer. But by taking the difference between M2 and M3,
we can detect small offsets between chips- most chips easily fall in the
range of 5 counts. (1 count approximately equal 1mv)

The values that are used then are defined as follows:

PED = M1

BANK = M2 + M4 - M3 - M5

SELECT 16/64 = M2 + M3 - M4 - M5

ProgGain(PG) = 200 \* (M9 - M8) / (M7 - M6)

Bandwidth(BW) = 50 \* (M11 - M12) / (M12 - M13)

Speed (SPD) = 100 \* (M17 - M16) / (M16 - M15)

Note: PG, BW and SPD are scaled to make the values come out to some
reasonable number. Some measurements are not used at all (M10 and M14)
because with large charge injection and large gain, these measurements
were observed to saturate on some chips. The cuts are shown below. The
distributions of the variables are in Figs 2 through Fig 8. A map of all
bad chips is in Fig 9.

The applied "LOOSE" cuts are

  ---------------------------------------------- ------------ ------------
  **Bad Chip Cuts**                                           

  Max bad chan/chip                              2            

  Max weird chan/chip                            128          

  Max current                                    180          

  Min current                                    120          

                                                              

  **Bad Chan Cuts**                                           

                                                 MAX          MIN

  PEDS A                                         15           -15

  PEDS B                                         15           -15

  PEDS C                                         15           -15

  BANK A                                         20           -20

  BANK B                                         20           -20

  BANK C                                         20           -20

  SELECT1664 A                                   20           -20

  SELECT1664 B                                   20           -20

  SELECT1664 C                                   20           -20

  PROG GAIN A                                    150          -10

  PROG GAIN B                                    150          -10

  PROG GAIN C                                    150          -10

  BANDWIDTH A                                    150          -10

  BANDWIDTH B                                    150          -10

  BANDWIDTH C                                    150          -10

  SPEED A                                        150          -10

  SPEED B                                        150          -10

  SPEED C                                        150          -10

  DIRECTION A                                    1000         -500

  DIRECTION B                                    1000         -500

  DIRECTION C                                    1000         -500

  Note:                                                       

  MAX= 1000 means the MAX test is ignored                     
  ---------------------------------------------- ------------ ------------

![](media/image1.jpeg){width="5.990277777777778in"
height="4.002083333333333in"}

Fig 2

![](media/image2.jpeg){width="5.996527777777778in"
height="4.004861111111111in"}

Fig 3

![](media/image3.jpeg){width="5.99375in" height="4.022222222222222in"}

Fig 4

![](media/image4.jpeg){width="5.997222222222222in"
height="4.006944444444445in"}

Fig 5

![](media/image5.jpeg){width="5.9944444444444445in"
height="4.030555555555556in"}

Fig 6

![](media/image6.jpeg){width="5.993055555555555in"
height="3.966666666666667in"}

Fig 7

![](media/image7.jpeg){width="5.997916666666667in"
height="4.031944444444444in"}

Fig 8

  -------- ------- -------- -------- -------- -------- ------- -------- --------
                   **10**   **0**    **0**    **7**                     

                   **3**    **0**    **1**    **3**                     

                   **3**    **1**    **1**    **1**                     

  **18**   **1**   **1**    **1**    **1**    **0**    **0**   **18**   

  **2**    **1**   **1**    **0**    **1**    **0**    **0**   **1**    

  **2**    **1**   **1**    **0**    **1**    **0**    **0**   **0**    

  **3**    **1**   **0**    **0**    **0**    **0**    **0**   **1**    

  **1**    **1**   **0**    **0**    **0**    **0**    **2**   **1**    

  **0**    **0**   **0**    **0**    **0**    **1**    **1**   **1**    

  **1**    **1**   **0**    **1**    **0**    **0**    **1**   **1**    **18**

  **1**    **1**   **0**    **0**    **0**    **0**    **0**   **2**    **18**

  **0**    **1**   **0**    **0**    **0**    **0**    **0**   **2**    **18**

  **0**    **1**   **0**    **0**    **0**    **0**    **0**   **2**    

  **1**    **2**   **0**    **0**    **1**    **0**    **0**   **1**    

  **0**    **3**   **0**    **0**    **0**    **0**    **0**   **0**    

  **2**    **1**   **1**    **0**    **0**    **1**    **0**   **1**    

  **1**    **1**   **1**    **0**    **1**    **2**    **1**   **2**    

  **18**   **0**   **3**    **0**    **0**    **1**    **0**   **18**   

                   **2**    **3**    **1**    **1**                     

                   **2**    **1**    **1**    **0**                     

                   **18**   **18**   **18**   **18**                    
  -------- ------- -------- -------- -------- -------- ------- -------- --------

Fig 9

This is a combined wafer map of all "BAD" chips on all wafers.

In our view, the key problem is to balance the probability that a good
chip is unused against the probability that a flawed chip is
inadvertently used. The line between the perfect chips and the not so
good chips is further blurred by limitations of the testing procedures.
In many cases, it is easy to identify chips that are clearly bad- many
channels don't respond at all, or the chip draws too much current or too
little. In other cases, one or two channels may not respond in the
expected way- or the readings from many channels maybe a little bit off
from what was seen on other chips, or other wafers. The question
remains: where to draw the line between the "good", the "bad" and the
"ugly". Part of the answer lies in the number of chips required. If
there are plenty of chips that test good, we can afford fairly strict
cuts to exclude chips that are potentially bad. If the number of chips
required exceeds the number of chips that showed no problems in testing,
the limits of what chips are considered to "pass" the tests may need to
be expanded.

We have gone through the exercise of applying a set of reasonable cuts.
We present a brief summary of the numbers below. For this exercise, a
chip is called "perfect" if all 128 ch pass all cuts. A chip is called
"bad" if more than 2 channels fail to respond at all in the expected way
or a significant number of channels (more than a dozen) fall outside the
values seen observed from the perfect "chips". Of course this involves
some arbitrary judgment which is not right or wrong -- it is just some
particular choice.

  -------------------------- -------------- -------------- --------------
  CHIP TYPE:                 A              B              C

  Number of "perfect" chips  710            747            650

  Number of "bad" chips      48             56             62

  Number of "ok" chips       124            79             170
  -------------------------- -------------- -------------- --------------