Quarterly Technical Status Report

For

February 2002 -- June 2002

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Monolithically Interconnected Silicon-Film^TM^

Module Technology

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## Prepared by

AstroPower, Inc.

461 Wyoming Road

Newark, DE 19716-2000

USA

NREL Technical Monitor: B. von Roedern

Prepared under Subcontract No. RAT-3-30630-21

June 2002

**1. INTRODUCTION**

AstroPower is developing an advanced thin-silicon based, photovoltaic
module product. This advanced product requires the following features:

-   Silicon layers grown on a low cost ceramic substrate.

-   Total silicon layers ≤100μm thick.

-   Light trapping due to back-surface reflection and random texturing.

-   Back surface passivation.

These performance design features, combined with the use of low-cost
continuous processing equipment, will lead to high performance, low-cost
photovoltaic panels. The thin-silicon device structure allows for the
use of imperfect materials and increased doping levels, and lowers the
cost by minimizing the use of expensive feedstock material.

The solar cell device design incorporates light trapping and back
surface passivation to improve energy conversion efficiency. Light
trapping is achieved by using diffuse reflection from a randomly
textured back surface. This results in enhanced optical absorption of
weakly absorbed light and improved current generation. Diffusion lengths
equal to or greater than twice the device thickness are required to
assure efficient carrier collection through the bulk of the base layer.
The performance of a thin-silicon solar cell is critically dependent on
recombination at the device surfaces, minority carrier diffusion lengths
(L~n~), and optical losses.

**2. APPROACH**

The construction of this thin-silicon device can be broken down to the
following functional areas:

1\. Ceramic Substrate Development

2\. CVD Silicon

3\. Silicon Recrystallization

4\. Solar Cell Processing

This quarterly report details progress in these areas for the Period of
February, 2002 through June 2002.

# Ceramic Substrate Development

When designing a substrate for the thin-silicon growth, the primary
issues that must be addressed are:

-   Mechanical stability at growth temperatures.

-   Coefficient of thermal expansion (CTE) match to silicon.

-   Minimization of impurity diffusion to the active silicon layer.

Structured ceramic substrates that incorporate these properties can be
manufactured in a cost-effective manner using a tape casting process.
The advantage of tape casting, compared to other ceramic forming
processes, such as dry pressing, is that it forms flat pieces with
thickness ranges from 25μm to 1250μm. Currently, AstroPower has the
capability to cast continuous 12.5 inch wide sheets of ceramic.

Work was performed with the goal of more closely matching the
coefficient of thermal expansion (CTE) of our ceramic to that of
silicon. In order to keep the silicon-film layer slightly in
compression, the substrate should have a slightly higher CTE than that
of the silicon-film. The CTE of the ceramic currently being used is
approximately 21% higher than the CTE of silicon at its melting point
which results in cracking if silicon films less than 10μm thick are
deposited onto the substrate. Although the seed layers deposited for our
structures are thicker than 10 μm, and there is no apparent cracking,
the stress at the silicon -- ceramic interface may be limiting the
electrical quality of the device. Characterization efforts are designed
to investigate this possibility.

In order to adjust the CTE of the ceramic closer to silicon, ceramic
modifiers with lower CTE than that of silicon are added to the
formulation and evaluated. If the newly formulated ceramic survives the
firing process without cracking or warping the CTE is then measured from
room temperature to 1500°C using a dilatometer. If the CTE provides a
closer match to that of silicon, then silicon is deposited onto the
substrate and recrystallized, followed by electrical characterization.

Additions of both cordierite (2MgO-2Al~2~O~3~-5SiO~2~) and zircon
(ZrSiO~4~) have been analyzed as CTE modifiers in the standard ceramic
formulation. Cordierite which has a CTE of 1.5 x 10^-6^ /°C was added to
the standard formulation in 10% by weight increments from\
10 to 50%. The addition of the cordierite in amounts less than 30 weight
percent resulted in no significant change in the CTE curve. Additions of
30-50% cordierite results in a shift of the CTE from 21% above silicon
to just below silicon as shown in Figure1 for experimental ceramic A. It
can also be seen in Fig. 1 that the ceramic is shrinking at temperatures
above 1290°C. This shrinkage is due to softening of the sample which
bends under the 350 mN force applied by the dilatometer. Even though the
sample softens above 1290°C a 35μm CVD silicon layer was deposited and
recrystallized using zone melt recrystallization (ZMR). Unfortunately
during the ZMR process the cordierite melted and mixed with the molten
silicon making this formulation unusable as a substrate in epitaxial
growth.

Zircon, which has a CTE of 1.4 x 10^-6^ /°C, was also analyzed as a
modifier. Like the cordierite it was added to the standard formulation
in 10% by weight increments from 10 to 50%. Instead of moving the CTE
curve down closer to silicon it actually increased the CTE of our
standard formulation. The curve for the 50% mixture is pictured in Fig.1
as Experimental Ceramic B. It is believed that the reason for the
increase in CTE is due to the reaction of the zircon with free alumina
in the ceramic. The reaction 2ZrSiO~4~ + 3Al~2~O~3~ ⇒ 2ZrO~2~ +
3Al~2~O~3~^.^ 2SiO~2~ indicates that the zircon and alumina react at
1450°C to form zirconia (ZrO~2~) and mullite (3Al~2~O~3~^.^ 2SiO~2~).
The mullite is not a problem but the zirconia has a higher CTE (7 x
10^-6^/°C), which is acting to increase the overall CTE of the ceramic.
During this reporting period 10 ceramic casts were performed yielding
approximately 210 4"x2" substrates.

![](media/image1.jpeg){width="4.447916666666667in" height="3.40625in"}

Figure 1. Thermal expansion measurements of various AstroPower ceramics
compared\
to mC-Si.

# CVD Silicon 

AstroPower purchased and completed the installation of an atmospheric
pressure CVD silicon deposition system in the period September, 01 to
January, 02, prior to this reporting period. The installed price of this
system was \$592,000. Atmospheric pressure CVD silicon deposition was
chosen because it has the advantages of good thickness control, high
material quality, availability of both epitaxial and polycrystalline
growth modes, and high deposition rates. Also, at production levels, the
cost of silicon in the CVD precursor ranges from \$7 to \$15/kg from
established industrial suppliers. An average of 100 grams of TCS is used
per deposition. This translates to roughly \$0.006 per cm^2^.

The current custom CVD system, shown in Fig. 2, has the following
capabilities:

-   Large deposition area (240cm^2^).

-   High temperature (\>1300°C).

-   In-situ HCl etching (1400Å/min).

-   Both p and n-type doping (0.02 to 5Ω-cm).

-   Fast deposition rates (4-5μm/min).

This system utilizes a square high purity quartz processing tube in
conjunction with a 65kW, 350kHz, RF induction power supply which heats a
graphite susceptor. The substrates are heated to deposition temperature
by thermal contact with the susceptor. All system components, such as
the mass-flow controllers and RF generator, are computer controlled and
can be programmed for various deposition "recipes".

![](media/image2.wmf)

Figure 2. AstroPower custom CVD silicon system.

During this reporting period, experiments to optimize controlled p-type
doping were performed. This was done by utilizing n-type single crystal
wafers as substrates and growing epitaxial layers using different
B~2~H~6~ concentrations. The bulk resistivity was then determined by
4-point probe. It was found that controlled doping from 0.1 to 1 Ω-cm,
with good reproducibility, was achievable. However, it was concluded
that a greater concentration of B~2~H~6~ would be needed to dope the
seed layers to lower resistivity\
(\~0.01Ω-cm) to ensure a strong back surface field (BSF) effect and
provide low resistivity conduction layers. Therefore, a less diluted
B~2~H~6~ source was procured.

The HCl etch rate was also determined for the current HCl/hydrogen mix
and found to be \~600 Å/min. This was done utilizing single crystal
substrates at epitaxy temperatures. A faster etch rate is desired so a
higher concentration HCl source was also ordered. During this reporting
period, 58 Si-CVD runs were performed.

# CVD Seed Layer Growth and Recrystallization

Silicon seed layers are deposited onto the ceramic substrates using
atmospheric pressure CVD. The as deposited CVD silicon layer consists of
sub-micron sized grains that are recrystallized, to enhance grain size
and reduce grain boundaries, using zone melt recrystallization (ZMR).
CVD p^+^ (0.1Ω-cm ) seed layers at thicknesses from 5μm to 100μm were
deposited onto ceramic substrates that had as fired and polished
surfaces, then recrystallized using ZMR. The resulting seed layer on
ceramic structures were analyzed for cracking, wetting, grain size, and
morphology and then CVD epitaxial silicon layers were deposited and
electrical quality analyzed through mesa test devices. In order to
provide wetting of the substrate by molten silicon in the ZMR process,
different capping layers and growth ambients were evaluated. Samples
were capped with 2 μm thick PECVD SiO~2~ layers, 2 μm thick PECVD
SiO~2~/1 μm PECVD Si~3~N~4~ layers, as well as with an in-situ thermal
SiO~2~ layer that was grown by heating the sample in air.

All of the seed layers recrystallized on the polished ceramics would not
wet regardless of thickness or capping layer. Recrystallized seed layers
less than 10 μm thick on unpolished ceramics exhibited cracking due to
the CTE mismatch between the silicon and the ceramic. The PECVD capping
layers were recrystallized in a 95% Ar / 5% O~2~ ambient and provided
wetting on the as fired ceramics, however, the morphology and the
surface texture of the layers were poor. The surface appeared pitted and
wrinkled as though the silicon was wetting the substrate but puddling
and creating peaks or kisses in the film. Experiments were also done
with the PECVD capping layers on CVD layers grown on single crystal
wafers. Similar results were obtained and in some cases the single
crystal substrate was melting. It was determined that our ZMR system did
not provide sufficient bottom heat to allow for a fast enough scan speed
of the top lamp. Since the majority of the heat for melting is being
provided by the top lamp the scan speed is relatively slow, causing the
cap to float and wrinkle as the molten silicon puddles beneath it. Plans
were submitted to build a new ZMR system that will address these
problems.

The best results were obtained with seed layers recrystallized in air to
form in-situ caps. The in-situ cap method is limited to seed layers
greater than 25 μm thick, due to wetting issues, however, the resulting
surfaces and morphology are excellent. After epitaxial growth of a
silicon active layer, test structures were fabricated and the electrical
results analyzed. The results indicated that a 50 μm seed layer yielded
the best results with thicker seed layers showing no electrical
improvements. During this reporting period, 49 recyrstallization runs
were performed.

# Solar Cell Processing 

Figure 3 displays typical silicon-on-ceramic wafers at different stages
of processing. The ceramics are cut to 5 x 5 cm^2^ areas before
deposition. Figure 3 (a) shows an area of as-grown polysilicon and an
area where this layer has been recrystallized in air using a ZMR
process. This produces an elongated grain structure where the long
dimension is typically on the order of centimeters and the width
dimension is usually a few mm. This recrystallized layer is used as a
template for subsequent epitaxial growth of solar cell device layers.
Figure 3 (b) shows a processed mesa array on an epitaxial growth. The
area of the circular mesa emitter is \~0.2 cm^2^ and there is no emitter
metallization or AR-coating used in this test structure. The base and
emitter are isolated after diffusion using plasma etching and the base
is contacted by depositing and alloying evaporated aluminum in the field
around the mesa structures. Masking for this structure can be
accomplished with "blackwax", Kapton tape, or by hand-painted
photoresist. The "power-product", Voc x Jsc, for this simple structure
has often been found to be indicative of the efficiency that a fully
processed device (such as shown in Fig 3 (c)) with an AR coating will
achieve. In general, growths are cut in half so that half can be run
through the test device (mesa) process first and if good electrical
results are obtained the other half can be processed into a single
element or monolithically interconnected device.

![](media/image3.jpeg){width="6.010416666666667in"
height="2.9583333333333335in"}

\(a\) (b) (c)

Figure 3. Examples of silicon-on-ceramic material and devices.

During this reporting period phosphorous gettering was employed in an
attempt to getter any impurities associated with the ceramic that may
have diffused into the seed layer during the ZMR process and may diffuse
to the active layer in further high temperature processing steps.
Gettering was performed on the seed layer on ceramic and the active
layer on seed layer on ceramic for times of 4 and 8 hours. Electrical
results on test structures compared to controls indicated no
improvements due to this gettering process.

As mentioned previously, the "power product" of the mesa structure is
often predictive of the efficiency of a fully processed device. In
general, the P~max~ point of a 1-cm^2^ device with metallization and AR
coating is close to the product Voc and Jsc for a mesa device made from
the same material.

In this reporting period, exceptions to this guideline were found. For
example, in mesa devices made from the first half of CVD-15 the power
product averaged 5.15 mW/cm^2^ over six devices with a high value of 6.2
mW/cm^2^.

Using the other half of this material a 1cm^2^ single element device was
fabricated. Surprisingly, this device exhibited significantly lower real
efficiency. After hydrogenation and antireflective coating the best
1-cm^2^ solar cell parameters were: Voc = 457 mV; Jsc = 19.19 mA/cm^2^;
fill factor = 47.9 %; efficiency = 4.2 %. The IV curve for this device
is shown in Figure 4. Note that the low fill factor is due to the
"softness" of the IV curve (junction leakage) rather than to shunt or
series resistance problems.

![](media/image4.jpeg){width="6.010416666666667in"
height="3.9583333333333335in"}

Figure 4. 1-cm^2^ silicon on ceramic device IV curve.

At first this variation in device performance from one end of the sample
to the other was believed to be due to material quality variations,
however there appeared to be no difference in physical material quality.
Several more test devices were run and this same phenomenon occurred
intermittently. Sometimes both halves of the same sample were bad
sometimes both halves were good, and sometimes there were one of each.
There never seemed to be good and bad test devices within a half of the
sample but only between halves.

We then examined the device processing and determined that the only
processing difference between halves was the diffusion. The first half
of the sample would be diffused for test devices and if it was good the
second half would be diffused in a separate diffusion run and processed
into a 1 cm^2^ single element or submodule device. Because of the low
voltages with fairly high currents it is believed that the phosphorous
may have diffused into the porosity of the ceramic in the diffusion
process to form a junction at the ceramic silicon interface.

To determine if the diffusion process was causing this problem a set of
CVD on ceramic samples were cut in half. Half of the sample was diffused
using the standard tube diffusion and the other half was diffused in a
production based phosphorous spray and continuous belt diffusion, that
prevents the phosphorous spray from getting to the back surface. All of
the halves that were diffused in the production spray process had good
voltages and generally achieved good device results. The tube diffused
halves for the most part achieved poor device results with \~ 10-15 %
achieving reasonable device results. Based on these results all of the
diffusions are performed using the standard silicon-film belt diffusion
process. Work will continue to optimize the belt diffusion process for
the silicon on ceramic material. The EQE data is shown in Figure 5 and
illustrates the inconsistency of the tube diffused samples.

![](media/image5.wmf)

Figure 5. EQE data of tube diffused wafers versus belt diffused wafers.