# **Georgia Institute of Technology/Institute of Energy Conversion HiPerf PV Project**

# **"Thin Film Si Bottom Cells for Tandem Device Structures"**

# **April 2004-- June 2004 Quarterly Report** 

# **A. Rohatgi^1^, V. Yelundur^1^, B. Rounsaville^1^, B. Birkmire^2^, S. Hegedus^2^, R. Aparicio^2^**

# **^1^-University Center of Excellence for Photovoltaics Research and Education, Georgia Institute of Technology, Atlanta, GA**

**^2^-Intstitute for Energy Conversion, University of Delaware, Newark,
DE**

1.  *Introduction*

This report summarizes the progress in the development of deposited
emitter and contact layers for heterojunction a-Si/c-Si solar cells. The
work reported here was performed to meet the objectives of Task 1 in
Phase 1 of the collaborative subcontract titled Thin Film Si Bottom
Cells for Tandem Device Structures as part of the High-Performance
Photovoltaic Project initiated by the Department of Energy. The
objectives of Task 1 addressed in Phase 1 include the fabrication of
thin film Si/c-Si and thin film Si/thick polycrystalline Si
heterojunction cells with deposited emitter and contact layers (p-i and
n-i structures) deposited by PECVD. In this report, HIT-type devices are
fabricated and analyzed using c-Si wafers prepared at Georgia Tech (GT)
with p-i and n-i a-Si layers deposited at the Institute for Energy
Conversion (IEC). In some cases, c-Si and c-Si solar cells are
fabricated with deposited emitter layers and screen-printed back
contacts.

2.  *Fabrication and analysis of heterojunction a-Si/c-Si solar cells*

IEC fabricated HIT-type devices by depositing i-p and i-n contacts on
both n-type and p-type c-Si wafers from GT. The cells were numbered
41049B.22 (p Si) and 41049AC.22 (n-Si), respectively. Initially, they
received ITO/Ni contacts on both sides so we could do bifacial
measurements. All such devices initially had fill factors below 0.25. To
improve the fill factor, the ITO/Ni layers were etched off the back
contact only and replaced with metal contacts. The effect of contacts
and heat treatment on J-V and QE are reported here.

For deposition of a-Si films on c-Si substrates, one inch by one inch Si
samples were prepared from 2.3 Ω-cm p-type and 3.3 Ω-cm n-type Si wafers
using a dicing saw. These samples were then cleaned at GT in the series
of solutions listed below.

1.  Rinse in DI H~2~O for 5 min

2.  HF:H~2~0 (1:10) for 1:30 min

3.  Rinse in H~2~0 for 3 min

4.  H~2~O:H~2~SO~4~:H~2~O~2~ (2:1:1) for 5 min

5.  Rinse in H~2~O for 3 min

6.  HNO~3~:CH~3~COOH:HF (15:5:2) for 2 min

7.  Rinse in H~2~O for 3 min

8.  H~2~O:HCl:H~2~O~2~ (2:1:1) for 5 min

9.  Rinse in H~2~O for 3 min

10. HF:H~2~O (1:10) for 3 min

11. Rinse in H~2~O 30 sec

12. Dry with N~2~ gun

Figure 1 shows the two device structures that were initially fabricated
on p-type and n-type c-Si wafers. The a-Si films were deposited by PECVD
at 175°C with a power of 7 W, a pressure of 0.2 Torr, a SiH~4~ gas flow
rate of 20 sccm, and dopant gas flow rates of 20 sccm for a deposition
time of 40 seconds per layer for a thickness of \~15 nm. The dopant
gases were 2% PH~3~ or B~2~H~6~ in balance H~2~. Thicker layers were
deposited for standard characterization. Bandgap (from Tauc plot), dark
conductivity and conductivity activation energy for the three layers are
shown in Table 1. They are typical of film properties reported by IEC
and others and indicate that very acceptable bulk film properties are
achieved with IEC's new dopant gases and recently cleaned PECVD system.

![](media/image1.wmf){width="3.808333333333333in"
height="2.3583333333333334in"}

+--------------+----------------+-------------------------+------------+
| a-Si layer   | E~TAUC~ (eV)   | Dark conductivity       | E~A~ (eV)  |
|              |                |                         |            |
|              |                | (S/cm)                  |            |
+--------------+----------------+-------------------------+------------+
| n-layer      | 1.72           | 1 x 10^-2^              | 0.18       |
+--------------+----------------+-------------------------+------------+
| p-layer      | 1.56           | 5 x10^-4^               | 0.29       |
+--------------+----------------+-------------------------+------------+
| i-layer      | 1.73           | 6 x 10^-11^             | 0.70       |
+--------------+----------------+-------------------------+------------+

3.  *Dark and illuminated J-V characterization of n-type and p-type
    heterojunction a-Si/c-Si solar cells*

![](media/image2.wmf){width="3.069291338582677in"
height="3.194488188976378in"}Figures 2 and 3 show the JV curves in the
light and dark for devices on the n-type and p-type c-Si wafers,
respectively. Results are shown for illumination through the front
junction (p/n or n/p) and back contact (n/n or p/p) for each. In both
devices, the dark J-V curves are nearly flat in forward bias indicating
poor carrier injection or very high resistance. Illuminated J-V curves
collapse as V approaches 0 V from --0.5 V leading to FF \< 25%. Forward
J-V in the light appears normal. There is slight curvature at very high
currents in AC22, suggesting a blocking contact. Overall, this data
suggests both n-type and p-type Si heterojunction solar cells have a
contact injection problem. Given that the only photoconductive layer is
the 15 nm i-layer, it is not likely that the light-dark crossover is due
to differences in series resistance.

![](media/image3.wmf){width="3.069291338582677in"
height="3.180708661417323in"}

4.  *Quantum efficiency analysis of n-type and p-type heterojunction
    solar cells*

Figures 4 and 5 show the QE for the n-type wafer device for illumination
through the junction and contact, respectively. Measurements were made
with four bias conditions: dark and 1 sun bias light at 0V and --1V.
There is a significant decrease in QE for light through the junction
(Figure 4) with 0V and bias light consistent with the low J~sc~ in
Figure 2. The decrease is nearly wavelength independent beyond 500 nm
suggesting it is due to an interface not a carrier collection effect.
The other three conditions give essentially the same QE curve. For light
entering through the back contact (Figure 5), the QE increases beyond
700 nm as expected for backside illumination for cells in which
diffusion length is less than the device thickness. Note that the bias
light reduces the QE beyond 500 nm for both 0 and --1V bias.

![](media/image4.wmf){width="3.1110236220472443in"
height="3.319291338582677in"}

Figures 6 and 7 show the QE for the p-type wafer device for illumination
through the junction and back contact, respectively. Comparing the QE at
400 nm from Figures 4 and
![](media/image6.wmf){width="3.1110236220472443in"
height="3.319291338582677in"}6 indicates that the QE is much higher for
illumination through the n/p junction (Figure 6) than through the p/n
junction, consistent with the higher bandgap of the deposited a-Si
n-layer (Table 1). Bias light at 0V reduces the QE though not as
drastically as in Figure 4. Bias light increases the QE for illumination
through the back contact (Figure 7), in contrast to results on the
n-type wafer (Figure 5). Also note that the QE at --1V with bias light
is nearly the same for illumination through front or back. This
indicates the diffusion length is comparable to the thickness.

Overall, these results (Figures 2-7) suggest evidence for a band offset
or interface collection problem with both types of devices. At this
point, we could not identify whether the junction or "ohmic" contact is
responsible.

5.  *J-V characterization of heterojunction solar cells after removal of
    ITO/Ni rear grid and deposition of Al*

The ITO back contact was replaced with an Al contact in p- and n-type
devices to improve the contact quality. We etched off the ITO/Ni grids
on the back only and deposited metal contacts by e-beam. For p-type base
devices, 0.5 µm of Al was deposited on the rear a-Si i-p layers. It is
well known that Al alloys with a-Si at \~180°C to form a good Ohmic
contact. For n-type base devices, we deposited Ti(2 nm)/Ag(0.5µm).
Previously we have obtained very good Ohmic contacts with Ti/Ag on
n-type a-Si layers in pin solar cells. Cells were tested initially after
metallization, then given two heat treatments (HT), first 175°C for 30
minutes then 200°C for 15 minutes. J-V was measured after each HT.

Data on the p-Si wafer is shown in the Table 2 and Figures 8 and 9.
Figure 8 compares the ITO/Ni and the Al contact without heat treatment,
and Figure 9 compares initial and heat-treated results. Initially the
light and dark JV curve are essentially the same with Al as with ITO but
significant changes in V~oc~ and dark diode occur with HT. Note that the
V~oc~ steadily increases with HT to 0.720V. Most cells on the piece had
V~oc~\>0.720V. There was a 2-4 mA/cm^2^ increase in reverse bias
photocurrents with HT, up to about 35 mA/cm^2^, but Jsc is limited by
extremely low FF\~12% which is not improved with HT. But HT improves the
dark diode conduction at forward bias. Similar data on the n-Si wafer is
in Table 3 and Figures 10 and 11. In contrast to the p-Si device, there
is substantial difference in lighted and dark JV between ITO/Ni and
Ti/Ag contacts. The illuminated JV moves out further into the power
quadrant and the dark JV has much higher forward bias currents with
TiAg. There is negligible change with HT. As with Al, the reverse bias
photocurrent increase with HT but remains smaller on the n-Si device,
\~28 vs. 35 mA/cm^2^.

Table 2. Performance of GD 41049B.22-3 (p c-Si) with different back
contacts and after different heat treatments. Figures 8 and 9 show the
J-V curves.

+-----------+-----------+-----------+-----------+-----------+-----------+
| **        | **HT**    | **V~oc~   | **J~sc~   | ## FF     | **Eff.    |
| Contact** |           | (V)**     | (mA       |           | (%)**     |
|           |           |           | /cm^2^)** |           |           |
+-----------+-----------+-----------+-----------+-----------+-----------+
| ITO/Ni    | Initial   | 0.54      | 16        | 12        | 1.1       |
+-----------+-----------+-----------+-----------+-----------+-----------+
| Al        | # Initial | 0.54      | 17        | 13        | 1.2       |
+-----------+-----------+-----------+-----------+-----------+-----------+
| Al        | 175°/30'  | 0.65      | 26        | 16        | 2.8       |
+-----------+-----------+-----------+-----------+-----------+-----------+
| Al        | 200°/15'  | 0.72      | 18        | 12        | 1.6       |
+-----------+-----------+-----------+-----------+-----------+-----------+

Table 3. Performance of GD 41049AC.22-2 (n c-Si) with different back
contacts and after different heat treatments. Figures 10 and 11 show the
J-V curves.

+-----------+-----------+-----------+-----------+-----------+-----------+
| **        | **HT**    | **V~oc~   | **J~sc~   | ## FF     | **Eff.    |
| Contact** |           | (V)**     | (mA       |           | (%)**     |
|           |           |           | /cm^2^)** |           |           |
+-----------+-----------+-----------+-----------+-----------+-----------+
| ITO/Ni    | Initial   | 0.50      | 7         | 13        | 0.5       |
+-----------+-----------+-----------+-----------+-----------+-----------+
| Ti/Ag     | # Initial | 0.50      | 21        | 25        | 2.7       |
+-----------+-----------+-----------+-----------+-----------+-----------+
| Ti/Ag     | 175°/30'  | 0.47      | 20        | 26        | 2.5       |
+-----------+-----------+-----------+-----------+-----------+-----------+
| Ti/Ag     | 200°/15'  | 0.49      | 21        | 25        | 2.5       |
+-----------+-----------+-----------+-----------+-----------+-----------+

![](media/image8.wmf){width="3.5in" height="3.513888888888889in"}

![](media/image9.wmf){width="3.388888888888889in"
height="3.486111111111111in"}

![](media/image10.wmf){width="3.333464566929134in"
height="3.486220472440945in"}

6.  *Fabrication of c-Si solar cells with deposited Si emitters*

To study the effect of the heterojunction emitter alone, solar cells
were fabricated with a standard screen-printed Al back contact with
deposited a-Si or µc-Si emitters on the front side of the device. A
schematic of the device structure is illustrated in Figure 12. Solar
cells were fabricated on p-type 1.3 Ω-cm float zone silicon and 1.5 Ω-cm
mc-Si grown by the heat exchanger method (HEM). Samples were initially
cleaned in the following series of solutions.

1.  Rinse in DI H~2~O for 5 min

2.  HF:H~2~0 (1:10) for 1:30 min

3.  Rinse in H~2~0 for 3 min

4.  H~2~O:H~2~SO~4~:H~2~O~2~ (2:1:1) for 5 min

5.  Rinse in H~2~O for 3 min

6.  HNO~3~:CH~3~COOH:HF (15:5:2) for 2 min

7.  Rinse in H~2~O for 3 min

8.  H~2~O:HCl:H~2~O~2~ (2:1:1) for 5 min

9.  Rinse in H~2~O for 3 min

10. HF:H~2~O (1:10) for 3 min

11. Rinse in H~2~O 30 sec

12. Dry with N~2~ gun

An aluminum back contact was applied by screen-printing an Al paste the
backside of all wafers. Wafers were then rapidly annealed in a belt
furnace to form the back contact and
![](media/image14.wmf){width="5.74015748031496in"
height="2.839763779527559in"}μc-Si emitters, and front contact layers at
IEC. Before Si deposition, samples were cleaned at IEC by dipping the Si
substrate (with the Al contact in place) in H~2~S0~4~ for 5 minutes
followed by dilute HF for 30 seconds. The Al contact darkened during the
cleaning steps, but retained a high conductivity. A 10 nm a-Si n-layer
was deposited on selected float zone and HEM wafers in run number GD
41060. For the remaining float zone and HEM wafers, a 20 nm of μc-Si
n-layer was deposited in run GD 4106 at IEC. A 200 nm layer of ITO was
sputtered onto the front of
![](media/image15.wmf){width="5.74015748031496in"
height="1.8326771653543308in"}all samples and Ni/Al layers were
deposited to form the front grid. To prevent collection from outside of
the ITO area, solar cells were isolated by two methods. In some cases,
solar cells were scribed with a diamond tip to define an active cell
area of 0.56 cm^2^. In remaining samples, solar cells were etched in
XeF~2~. The XeF~2~ etches away the deposited emitter and possibly some
of the Si wafer, but does not etch the ITO or Ni grids. Etching was done
for 30 seconds at room temperature for all samples. One was etched for
an additional 30 seconds and little change in cell performance was
observed, indicating that 30 sec was sufficient.

![](media/image16.wmf){width="4.524409448818898in"
height="1.7751968503937008in"}μc-Si deposited emitters on c-Si and mc-Si
base wafers. For devices with either the a-Si or μc-Si emitter, V~oc~
decreased after scribing possibly due to damage to the junction caused
by scribing. J~sc~ was higher before scribing due to collection from
outside of the ITO area. Table 6 shows the solar cell data measured at
IEC after isolation by XeF~2~ etching. The results in Table 6 show that
best results were achieved with the highly doped µc-Si emitter and c-Si
base that resulted in an efficiency of 12.9%. Figure 13 shows the JV
curves in the light and dark for the best c-Si cell before and after
etching. This data shows that J~sc~ decreased, FF increased and V~oc~
was unchanged after etching, indicating that the XeF~2~ etching method
eliminates collection outside the ITO area without damaging the
junction. This method is superior to mechanical scribing for cell
isolation, and it will be used in the future for all devices with
deposited emitters where collection outside of the ITO area is a
possibility. Table 6 also shows that solar cells made on the mc-Si
p-base substrate had an efficiency of only 8.7% for both a-Si and μc-Si
emitters. The relatively low performance of the mc-Si base solar cells
is likely due to the lack of phosphorus gettering and hydrogen bulk
defect passivation step in the process sequence. Conventional mc-Si
solar cell processing includes gettering of impurities from the bulk
during phosphorus diffusion of the n-emitter. Hydrogenation of bulk
defects in mc-Si typically occurs during a rapid anneal of the mc-Si
substrates after PECVD SiN film deposition and contact printing. Both
phosphorus gettering and hydrogen passivation of mc-Si substrate have
![](media/image17.wmf){width="3.177165354330709in"
height="3.3645669291338582in"}been implemented in studies currently
underway, which include mc-Si substrates with deposited Si back contact
layers and PECVD SiN layers on top of an n-emitter.

7\. *Conclusions*

In summary, this set of data indicates that for both the p and n wafer
devices, the back contact has a significant effect on the forward bias
current of the dark diode. But it has only a minor effect, after heat
treatment, on the illuminated JV performance. This suggests the
pathologically low FF is due to the front contact, or the deposited
emitter heterojunction. At sufficient reverse bias the photocurrent
saturates as it should, and at forward bias the diode conducts (perhaps
not as much as a good Si cell). This suggests two junctions in series or
a band misalignment at the heterojunction leading to poor collection.
Our results appear to show that V~oc~\>0.70V can be achieved after
alloying the Al with p a-Si contact. However, further work is needed to
verify these exceptionally high V~oc~ values. Significant improvement in
device behavior was achieved when a screen-printed Al layer was used as
the back contact and XeF~2~ etching was used for cell isolation. This
resulted in a solar cell efficiency of 12.9% for float zone Si with a
μs-Si emitter and 8.7% for mc-Si cells with either an a-Si or μc-Si
emitter. The performance of the mc-Si base solar cells is believed to be
limited by recombination in the mc-Si substrate due to the lack of
significant gettering or hydrogenation in the solar cell process. In
future work, we will incorporate phosphorus gettering and PECVD
SiN-induced hydrogenation to improve the bulk lifetime in the mc-Si
substrate and boost cell efficiency.