# IC Wafer Thinning

## Introduction

The design goal for the thickness of the front-end electronics is 150
microns. The prototype work so far has used mechanical thinning of the
integrated circuit(IC) wafers after deposition of the bumps on the IC
wafers. Dummy wafers and a few active wafers have been thinned
successfully. Bumped wafers processed by Boeing, AMS, IZM and Sofradir
have been thinned. The bumps on the IC wafers are protected by a layer
of photoresist(Jean-Claude confirm this was also the case for
Sofradir\....). Additional protection is provided by tape applied to the
active side(photoresist side) of the wafers. This tape is removed by the
thinning vendor after thinning, leaving the photoresist on the thinned
wafers. The thinned wafers are inspected by the vendor(a quick visual
inspection and the thickness of each wafer is measured). Additional QA
must be provided by ATLAS but is likely not to occur until after dicing.

## Prototype Results

We have prototype experience with wafers processed by four bump bonding
vendors: Boeing(no longer active), AMS, IZM and Sofradir. We summarize
below our experience with mechanical thinning with each of these sources
of bumped wafers. We have also tried non-mechanical thinning(plasma
thinning) but this is currently not planned to be used in
production.[^1]

### Boeing

One-half of a 6\" FE-B wafer was ground successfully by GDSI[^2] to 150
microns thickness after indium bump deposition by Boeing. This wafer was
diced and a 16 chip module made with good success.[^3]

### Alenia Marconi Systems(AMS)

Dummy 4\" wafers and active IC wafers(6\") bumped by AMS have been
thinned by Okamoto[^4]. The results to date are summarized in Table 1.
The target thickness is specified as a minimum. The vendor accuracy is
approximately ± 10 microns. The indium bumps deposited by AMS are
protected by a thin layer of photoresist(5-10 microns thick). The
photoresist-surface of these wafers is covered by UV-releasing tape.[^5]
Dummy modules were constructed from the dummy wafers(Leo\...add more if
needed) and a number of active modules assembled and tested.Error:
Reference source not found

+-------------------------+---------------------+---------------------+
| Wafer Type(s)           | Target              | Measured            |
|                         |                     |                     |
|                         | Thickness(μ)        | Thickness(μ)        |
+-------------------------+---------------------+---------------------+
| 4\" dummy(4 wafers)     | 152(+25, -0)        | 165-166             |
+-------------------------+---------------------+---------------------+
| Active(Wafer 11)(6\")   | 152(+25, -0)        | 156                 |
+-------------------------+---------------------+---------------------+
| Active(Wafer 15)(6\")   | 165(+25, -0)        | 171                 |
+-------------------------+---------------------+---------------------+

Table 1. Wafer thinning results with Alenia Marconi Systems.

### IZM

Dummy 6\" wafers bumped by IZM have been thinned by Okamoto. No active
wafers have yet been thinned(although this will occur soon). The process
used is identical to that employed for the AMS-bumped wafers. However,
the photoresist thickness protecting the bumps has been significantly
thicker(about 30 microns) in the wafers received to date.
Non-uniformities(eg. edge bead) in the photoresist create problems in
the grinding. As the silicon is thinned, it become too weak and the
wafer cracks(if the edge bead is higher than the rest of the wafer) and
cracks or chips are created at the edges of the wafer(if the edge bead
is lower than the rest of the wafer). The protective tape can reduce
these effects, and a thicker tape than for AMS-bumped wafers was used
for IZM wafers. So far we have successfully thinned four IZM-bumped
wafers to about 200-210 microns with their current photoresist
processing. Thinner wafers appear feasible if the thickness of the
photoresist layer is reduced, and this is under development.

Dummy modules with thinned parts(Norbert has to fill in\...\...)

### Sofradir

The results to date are summarized in Table (Jean-Claude\.....I have no
idea)

  ------------ ----------------- -------------------- --------------------
  Wafer        Target            Measured             comments
  Type(s)      Thickness(μ)      Thickness(μ)         

                                                      
  ------------ ----------------- -------------------- --------------------

Table 2. Wafer thinning results with Sofradir.

## Bump Defects After Thinning

\*\*\*\*Do we have any data on this\.....if so fill in Table

We have very limited experience so far with a comparison of the rate of
bump defects before and after thinning. Our results are summarized in

  ----------------------- ----------------------- -----------------------
  Vendor                  Defects before Thinning Defects AFTER Thinning

  AMS                                             

  IZM                                             

  Sofradir                                        
  ----------------------- ----------------------- -----------------------

Table 3. Bump defect rate before and after thinning.

## Preliminary Production Plan

Our limited results so far indicate that it is feasible to mechanically
thin the front-end IC wafers to 150-200 microns. However, we need
considerably more experience to assess the actual yield of the process,
and to evaluate the tradeoffs between reaching the 150 micron goal and
yield. Mechanical thinning(eg. as done by Okamoto) is a standard
industrial process done by robotic machinery, although tape
removal(after UV exposure) for these thin wafers has been done by hand,
as is inspection and reporting. The thinning capacity in this case if
very much larger than our need. The cost, in large quantities, is about
20 chf per wafer(6\").

[^1]: Tru-Si Technologies, 657 Patoria Ave., Sunnyvale CA 94086. A wafer
    was thinned by this process. We are not currently considering this
    process for production for the following reasons: cost, it requires
    first mechanical grinding to about 300 microns thickness for most
    economical results and the wafer temperature can get close to the
    melting point of Indium. We intend to follow the development of this
    method of wafer thinning in case it becomes more practical, since it
    is a non-contact process well suited to bumped wafers.

[^2]: GDSI, 247 Humboldt Court, Sunnyvale CA 94089.

[^3]: \"Results on 0.7% Thick Pixel Modules for the ATLAS Detector\", P.
    Netchaeva et al, submitted to the Proceedings of the Pixel 2000
    Conference.

[^4]: Okamoto Corporation, 2370 Owen St. Santa Clara CA 95054.

[^5]: Furakawa SP-589 or similar.