# Pierre Auger Project

**Front End Board version 3.0 (FEv3.0)**

## Kwame Bowie

### Revised 1/18/02

**Introduction:**

Many things have been learned through the process of developing the
Front End Board. This document was developed with the benefit of all
knowledge gathered through the design iterations of the FEv1 and FEv2
boards. However, as the name suggests, the FEv3.0 boards represent a
significant departure from the previous Front End board designs. Whereas
the previous Front End boards were working designs, they lacked in their
cost and power consumption parameters. This was acceptable for the EA as
the boards were development platforms and they were used to test
different design ideas.

The goal of FEv3.0 board is to strip all unnecessary components off the
board and to make the pre-production Front End hardware as cheap, power
efficient and reliable as possible. The first step in achieving this
goal was to agree on a unified board physical layout. The goal of this
new layout was to place all portions of the local station necessary for
data acquisition on a single board. The one exception to this was the
Front End Board. The interface between the new version of the local
station (unified board) and the FE will have a reduced number of
connectors. The other major simplification of the FE from the last
designs is the incorporation of the PLD trigger board layout into the
FEv3.0 layout. This removes a PGA socket connector and it places all of
the high-speed digital signals directly on the FE board in an attempt to
remove buffer chips which add significantly to both the cost and power
consumption of the FE board.

**Specifications:**

The design specifications have been refined through the design
iterations of the FE board as well as various meetings and telephone
conferences. The starting point for the FEv3.0 specifications is the
technical design review document as that document first discusses in
detail the operation of the pre-production version of the local station.

The specifications for the FEv3.0 boards are as follows:

-   6 analog signals from the PMT bases processed identically on the FE

-   Must use antialiasing filter yet not significantly attenuate desired
    signals

-   Must operate from --20 to +70C

-   Must operate reliably for 10-20 years

-   Must dissipate less than 4W

-   RMS noise must be less than 1 LSB

-   Nonlinearity no larger than that induced by the ADCs

-   

**Development Flow:**

The design of the FEv3.0 board will proceed in parallel down two
separate paths. Each path will be significantly different to enable
begin cost and power optimizations for the different design paths. The
front end hardware triggering will utilize either ASIC or PLD with
external SRAM. Each of these designs should be suitable for the
pre-production quantities of 100 or greater. To produce a more cost
effective front end, we will produce the FEv3.0A for the PLD and SRAM
trigger implementation, and the FEv3.0B for the ASIC trigger
implementation. A third proposed design path is still in the proposal
stages. The FEv3.0C as this third version is called will use 3 Altera
ACEX PLDs for triggering and data transfer.

[FEv3.0A :]{.underline} The FEv3.0A board will include the PLD and the
SRAM memory on the front end board itself. This eliminates connectors
and places the switching digital lines on the FE board where they may be
more effectively bypassed. The initial design will be based upon the
Altera APEX SRAM-based PLD. However, later the design might migrate to
the Altera APEXII PLD. The APEXII is the most recent device in the
Altera APEX family, and boasts lower power consumption and faster
speeds.

[FEv3.0B:]{.underline} The FEv3.0B board will include a PGA socket so
that the prototype ASIC may be tested with the latest front end. A
low-cost PLD must interface with the ASIC to help with the PPC DMA data
transfer protocol. The PLD is from Altera's ACEX series and is much more
cost-effective than the other PLD chips.

[FEv3.0C]{.underline}: The FEv3.0C board will try to take the minimized
risk advantage of the PLD and try to make it come closer to the cost of
the ASIC version. The decision to put effort into FEv3.0C was probably
due to the fact that the FEv3.0B ASIC version still requires a Altera
ACEX series "helper" PLD. The FEv3.0C uses 2 of these Altera ACEX series
PLDs to implement the triggering scheme. By utilizing the same device,
just twice as many, cost savings are possible by buying in bulk.
However, the drawback of the FEv3.0C design is that these cheaper and
slower PLDs would not allow interleaved DMA transfers, and as a result
would require an effort to retrofit the current software to a new DMA
transfer mode. As a result, this option has not had as much development
effort as the other two design options.

**Analog Section:**

The analog section of the FEv3.0 has been totally re-designed. The FE
design specifications were changed for pre-production. It was decided
that all gain control would be handled at the PMT base. As a result,
there are no longer high and low gain channels with respect to the FE
board. All six channels coming in to the FE board will processed
identically at the FE board. The transfer functions of all six channels
should be identical with exception of the variations due to parts
tolerances. The I/O specifications for the FEv3.0 boards are as follows:

-   6 analog input channels

-   analog inputs vary from 0 to --2V with respect to analog ground

-   analog output to ADCs will remain at 0 to 1V with respect to analog
    ground

-   anti-aliasing 3-pole Bessel filter with 3dB cutoff below Nyquist
    rate of 20 MHz

-   spike protection should not degrade with use

Noloberto Martinez's electronics group at UNLP designed an improved
version of the Bessel filter used in the active filter portion of the
front end analog electronics. The new design is an improvement as it
limits overshoot to less than 1%. Previous simulations of the FEv2.2
designs show overshoots on the order of 10% for high-speed pulse
waveforms. Also, Daniel Camin has provided a spike protection circuit
that will be tested on the FEv3.0. This circuit should protect the front
end electronics from spikes of 3KV without degrading itself in the
process.

**ADC Circuit:**

The question had been posed whether or not the pedestal is worthwhile to
keep as a portion of the circuit. The historical significance of the
pedestal is that it was initially in the FE design spec. The reason for
its inclusion was to ensure that the ADCs are indeed active and working
in the absence of an input signal. A secondary benefit is the fact that
it is much easier to diagnose overshoots and ringing with a pedestal
present. The counter-claim is that the offset is zero-mean and will be
subtracted from any statistics, so adding a pedestal is just throwing
away dynamic range. The decision stands to keep the pedestal for the
pre-production FE, but is open for the production version of the FE.

**ADC Bus:**

The ADC bus is an area of the FEv3.0 boards where experimentation is
being done. The prototype FEv3.0A boards route ADC digital output
signals only through resistors before arriving at the PLD for
processing. However, the FEv3.0B boards send these signals through
buffers before sending them to the triggering logic.The removal of the
transceivers from the layout for the FEv3.0A boards saves power
consumption, cost, and a medium lead-time part.

The rationalization behind adding the buffers to the FEv2.2 layout was
that the buffers compensated for low drive capabilities of the low power
ADCs. It was seen on the FEv2.1 boards that with the trigger boards in
place, the ADC outputs were directly tied to signals that were fanned
out to 4 different sets of pads as well as PGA sockets on the trigger
board and the FE board. Each of these individual components adds
parasitic capacitance. By the time all of these parasitic capacitances
are added together, the outputs have been significantly capacitively
loaded. This overloading degrades the accuracy of the analog
measurements

It is believed that since on the FEv3.0A the ADC outputs go directly to
a simple QFP package with small surface mount pads, the ADC outputs may
be routed without buffers. The small resistance in series reduces
ringing by slowing the edges of the output signals and attempting to
match the board impedance.

However, for the FEv3.0B boards, the buffers must be re-inserted. The
FEv3.0B is more heavily capacitively loaded than the FEv3.0A. The traces
cover much more ground than they do for the FEv3.0A since the FEv3.0B
board has the ADCs connected to both the ASIC (through a through-hole
socket) and the "helper" PLD.

**Triggering section:**

The two design paths start a small divergence at the ADC bus, but the
trigger section is where the 2 designs truly differ. One design path
attempts to minimize risk while the other design path attempts to
minimize cost.

The FEv3.0A uses a single high-speed APEX series PLD to handle both the
triggering and the DMA transfer functionality. The benefits of the
FEv3.0A boards are that they are upgradeable and low risk. The FEv3.0A
boards, by using PLDs allow the triggering scheme to be modified and
changed at any time. The only constraint is that pin assignments are
fixed with respect to the PC board. This makes the FEv3.0A a very low
risk design as design flaws or even algorithmic flaws may be fixed or
upgraded at no cost. The drawbacks of the FEv3.0A boards are the cost.
The APEX series part that is being used for the FEv3.0A board may cost
upwards of \$400. While PLD costs are constantly improving, the cost of
the ASIC chip is still roughly a factor of 10 less. Also, the FEv3.0A
board provides a slow buffer using a separate widebus SRAM chip. This
SRAM chip is also quite costly. The cost of the FEv3.0A board becomes
very significant for a production quantity of 1760 boards.

The FEv3.0B uses an ASIC for trigger generation and a PLD for DMA data
transfer. The PLD used for data transfer is from Altera's ACEX series of
low-cost PLDs. The cost of this PLD is of the same order of magnitude as
the ASIC, but is still not as cheap as the ASIC. As a result, the
FEv3.0B triggering module costs a little more than twice the per unit
price of the ASIC. Development of any ASIC is intrinsically a risky
venture. An ASIC may not be re-programmed once it has been fabricated.
Thus any small logic design error may cause an entire group of ASICs to
be useless. Unfortunately, for ASICs to be truly cost effective, they
must be manufactured in large quantities. Therefore, any ASIC design is
a gamble that large quantities will operate perfectly on the first try.

In an effort to find a good tradeoff between cost and risk, the FEv3.0C
has been proposed. The FEv3.0C removes small parts of the triggering
functionality, moves control registers around, and changes the DMA
transfer protocol in an effort to enable the triggering section to be
implemented with only 2 ACEX chips. The drawback of the FEv3.0C is that
acquisition software must be re-designed, both for the new DMA transfer
protocol as well as for the updated FE address map. Also, the triggering
capabilities and modes are reduced slightly.

**Unified Board connectors:**

The connector scheme has been greatly improved by moving all necessary
signals to one connector. However, all signals used by the FE in the
last design will be kept for FEv3.0. In order to accomplish this goal, a
larger connector was selected. The connector chosen is a standard VMEbus
96-pin male DIN41612 connector in a 3x32 format where the center column
is the ground return. By using one connector, all noisy, high-speed,
digital lines may be localized and routed through one section of the
board. This will reduce the EMI shielding requirements that were added
to the layout for this purpose. Hopefully this allows us to move to a 4
or 6 layer board instead of the 8 layers that are used in the FEv2.2.

**Power Supply Section:**

The FE board must derive the voltage for the PLD's 2.5V internal core.
The PLD's I/O buffers still operate off of the +3.3V that is supplied by
the motherboard, but the 2.5V must be supplied by a regulator. This
regulator is necessary to enable the PLD to operate from either a 1.8 or
2.5V core. There is a possibility that the FEv3.0A may use either the
cheaper APEX series PLD or the more costly but faster and low power
APEXII series PLDs. Z. Szadowski performed a power analysis using
Altera-provided tools for the APEX series PLD and determined that in the
very worst case scenario, the PLD would draw 1.6A. However, this
scenario should never actually occur as it would require all inputs and
outputs to be simultaneously switching steadily. The more likely
scenarios assume normal T1 and T2 rates and the power consumption would
then be on the order of 700mA or less. The quiescent power consumption
of the PLD devices is less than 100mA, so care must be taken to ensure
that regulation is maintained at both the high end and low ends of this
power spectrum. For this reason, the LM1086SI-ADJ was selected. The
adjustable version of this regulator was selected to enable the output
voltage to be controlled by a resistor divider network.