##### **Selection and Qualification of Foundries for CMOS Integrated Circuits**

NEPP Task 04-020

**Introduction**

This document discusses the types of semiconductor foundries that may be
involved in the production of radiation-tolerant integrated circuits,
along with the key issues that affect their radiation hardness. Specific
recommendations are made to monitor and control their radiation
performance, particularly for foundries that are adapted for
radiation-tolerant circuits and do not include radiation hardening as
part of their basic process control.

**Foundries and Supplier Relationships**

During the past 15 years the cost of semiconductor production lines has
increased rapidly. A state-of-the-art fabrication line costs more than
\$2B. Consequently many manufacturers have closed down their fabrication
lines, using foundry services from mainstream manufacturers. The high
cost of modern production lines has encouraged the companies which own
them to make them available to circuit design houses in order to
amortize the cost of development and to share the production cost.

The widest access to foundry services is provided by off-shore
manufacturers, such as TSMC and UMC. TSMC has more than 15 processes
available. There is also access to some U.S firms, particularly IBM.
Intel, however, does not make its production facilities available to
other companies.

In addition to mainstream foundries, two hardened foundries are
available in the U.S., Honeywell (an SOI process), and BAE
(bulk/epitaxial process).

We can divide relationships between semiconductor design houses and
foundries into three different categories:

1\. Commercial foundries where the relationship is limited to the
standard information required to design integrated circuits and set up
contracts for production and delivery. Although it is possible to design
radiation-tolerant circuits in this way, the limited information
available about process details increases the risk that the radiation
performance of the circuits will change.

2\. Commercial foundries where additional information is available about
the process, including some specific features that are necessary to
maintain a basic level of radiation tolerance. Periodic radiation
testing may be done in some cases. Examples include

\(a\) Aeroflex, which has a unique relationship with several foundries
allowing them to remove partially fabricated wavers, perform proprietary
processing to improve radiation tolerance, and return the wafers to the
manufacturer to complete the fabrication process.

\(b\) BAE, which has a long-term relationship with IBM that allows them
to use standard IBM processes to fabricate radiation-tolerant circuits.
In this case no special process changes are made, but the information
available from the foundry about the process normally provides
sufficient information to assure end-level success.

\(c\) Xilinx and Actel, which use several different foundries to
fabricate radiation-tolerant FPGAs. Xilinx has a mainstream commercial
process that is sensitive to latchup. They use an epitaxial process for
their radiation-tolerant products.

3\. Dedicated radiation-hardened foundries, including Honeywell (SOI
process) and BAE (bulk/epitaxial process) where radiation hardening is a
key factor in developing the specific processes used Periodic radiation
testing is done on devices from those production lines to ensure that
the radiation specifications are met. The main difficulty with these
foundries is the very high cost, due to limited production for the
aerospace and defense markets.

**The MOSIS Service**

ISI (associated with the University of Southern California) has
developed a brokerage service for commercial foundries that is an
extension of work started in the early 1990's with DARPA funding. The
basic idea is to provide the interface -- design tools, packaging, and
interface with the foundry -- to allow the wafer area to be shared among
several users. This reduces the cost of custom processing by at least
two orders of magnitude. This approach works well for small-volume
circuit manufacturers, but it is not intended to replace direct
interactions between the foundry and circuit manufacturer for
large-volume production runs.

Even though the MOSIS service is unlikely to be used for
radiation-tolerant circuit, they provide a great deal of information
about various foundries, including electrical characterization of test
structures over many different production runs. They provide their
services for more than 20 different foundries, from older production
lines with feature sizes of 2 µm or more, to 130 nm production lines
from IBM and TSMC. Table 1 shows information on some of the processes
that are available through MOSIS.

Parameters that are include in their test structures include gate oxide
thickness, which is an important parameter for radiation applications.
Their test structure data shows that the gate oxide thickness of
different process is extremely well controlled, varying by no more than
5% for most processes.

Table 1

Comparison of Several Processes that Are Available through the MOSIS
Service

+--------+--------+--------+--------+-------+---------+-------------+
| F      | F      | Core   | I/O    | Oxide | Appr    | Comments    |
| oundry | eature |        | V      |       | oximate |             |
|        | Size   | V      | oltage | Thic  |         |             |
|        |        | oltage |        | kness | Cost    |             |
|        | (µm)   |        |        | (Å)   | (\$k)   |             |
+--------+--------+--------+--------+-------+---------+-------------+
| AMI    | 1.5    | 5      | 5      | 305   | 2 - 5   | Process for |
|        |        |        |        |       |         | "tiny chip" |
+--------+--------+--------+--------+-------+---------+-------------+
| AMI    | 0.5    | 5      | 5      | 141   | 7       | 11 runs     |
|        |        |        |        |       |         | annually    |
+--------+--------+--------+--------+-------+---------+-------------+
| TSMC   | 0.35   | 3.5    | 5      | 78    | 14      | 9 runs      |
|        |        |        |        |       |         | annually    |
+--------+--------+--------+--------+-------+---------+-------------+
| TSMC   | 0.25   | 2.5    | 3.3    | 57    | 19      | 7 runs      |
|        |        |        |        |       |         | annually;   |
|        |        |        |        |       |         | epi and     |
|        |        |        |        |       |         | non-epi     |
|        |        |        |        |       |         | available   |
+--------+--------+--------+--------+-------+---------+-------------+
| TSMC   | 0.18   | 1.8    | 3.3    | 40    | 30- 36  | 6 runs      |
|        |        |        |        |       |         | annually;   |
|        |        |        |        |       |         | epi and     |
|        |        |        |        |       |         | non-epi     |
|        |        |        |        |       |         | available   |
+--------+--------+--------+--------+-------+---------+-------------+
| Pere   | 0.50   | 3      | 3.3    | 110   | 20      | SOS Process |
| grrine |        |        |        |       |         |             |
+--------+--------+--------+--------+-------+---------+-------------+
| IBM    | 0.25   | 2.5    | 3.3    | Not   | 17.5    | Non-epi;    |
|        |        |        |        | spec  |         | least       |
|        |        |        |        | ified |         | costly IBM  |
|        |        |        |        |       |         | process     |
+--------+--------+--------+--------+-------+---------+-------------+

On the other hand, no information is available on the isolation
structure, which is of key importance for devices with thin gate oxides.
Many of the processes are available either on bulk or "epi" substrates.
However, the substrate resistivity and epi-thickness are not included in
the characterization parameters. In general it is difficult to get such
information because it is unimportant for conventional circuit design.

The Aerospace Corporation has evaluated the total dose hardness of
several of the TSMC processes that are available through MOSIS, and has
used them to verify hardened-by-design principles, including the use of
annular transistors to eliminate the effects of increased leakage in
isolation regions \[1,2\].

**Processing and Radiation Performance**

This section discusses some basic radiation effects mechanisms and the
way that they are influenced by processing technology. The discussion is
limited to CMOS circuits with bulk (or bulk/epitaxial) substrates. Even
though a limited number of SOI foundries are available, the knowledge
base for SOI process radiation tolerance is too limited at this time.
Edge leakage is potentially a "show stopping" issue for commercial SOI
devices, along with back-channel leakage and snapback.

***Gate Oxides***

Ionizing radiation creates electron-hole pairs within the gate of an MOS
transistor. McGarrity \[3\] showed that the maximum threshold shift that
can occur, assuming 100% hole trapping efficiency, is given by the
equation

${\Delta V}_{T}\  = \  - 0\text{.}\text{036}\ t_{\text{ox}^{2}}\ D$ (1)

where ∆V~T~ is the change in gate threshold voltage due to hole traps,
t~ox~ is the oxide thickness in kÅ, and D is the total dose in krad.
This provides a first-order way to determine whether changes in
threshold voltage are likely to be important for a specific process.
Note that the oxide thickness is a well controlled parameter that is
easily obtained for a specific process. Applying this equation, the
change in threshold voltage at a total dose of 10 krad(Si) is --3.6 V
for a 1000 Å gate oxide, but only 22 mV for the 0.35 µm TSMC process in
Table 1. The point is that as processes scale to smaller dimensions, the
reduced oxide thickness causes changes in threshold voltage to decrease
to the point that threshold shifts are of secondary importance for many
processes.

Note that Eq. 1 represents a limiting case. In practice, only a fraction
of the holes produced within the oxide become trapped at the interface.
For oxide thicknesses \< 100 Å tunneling further reduces the amount of
trapped charge \[4\].

The general trends in gate oxide thickness are shown in Fig. 1 \[5\].
Note, however, that those trends are for mainstream devices with power
supply voltages that are 3.3 V or less for feature sizes below 0.25 µm.
Processes that are intended for higher voltage applications will have
greater gate oxide thickness, and may be significantly degraded by
ionizing radiation.

![](media/image1.wmf){width="3.8854166666666665in"
height="3.002083333333333in"}

Fig. 1. Gate oxide thickness trends with scaling \[5\].

This suggests that gate oxide thickness is an effective monitor for many
ASIC processes, particularly if one can base the application on the
limiting value of the gate oxide shift from Eq. 1. It will not be
effective for very high total dose levels, or for processes where
acceptable radiation performance is dependent on trapping much less
charge than predicted by Eq. 1. However, the general trends of scaling
to reduce oxide thickness -- and the resulting threshold shift -- make
this an effective approach for many processes.

***Isolation Structures***

[LOCOS Isolation]{.underline}

The situation is far more complex for isolation structures. Fig. 2 shows
the lateral isolation structure that results from LOCOS isolation, used
for CMOS circuits with feature sizes as small as 0.25 µm. The isolation
region is much thicker than that of the gate oxide, tapering to a
reduced thickness that extends over the well and the substrate. Because
of the much thicker oxide, these structures are far more sensitive to
charge trapping than gate oxides, and are often the dominant total dose
failure mechanism for CMOS.

![](media/image2.wmf){width="5.354166666666667in"
height="1.9583333333333333in"}

#  {#section .Fig-Cap}

# Fig. 2. LOCOS lateral isolation structure used in CMOS. {#fig.-2.-locos-lateral-isolation-structure-used-in-cmos. .Fig-Cap}

A parasitic MOS transistor is formed by the field oxide, with initial
threshold voltages \> 8 V (process dependent). Ionizing radiation can
cause inversion of the field oxide, which causes the transistor leakage
current to increase by several orders of magnitude, causing failure to
occur once the leakage current becomes comparable to the "on" current of
the transistor.

[Trench Isolation]{.underline}

The LOCOS process cannot be effectively applied unless the spacing
between the various elements is large enough to accommodate the "bird's
beak" extension that occurs during processing. Various methods were
initially developed to provide a more compact isolation structure \[6\],
and such structures may be used in some foundries. However, trench
isolation, shown in Fig. 3, has replaced LOCOS isolation in highly
scaled CMOS. The trench is somewhat more complex than indicated in the
figure, consisting of an oxidized recess (or hole, for trench structures
with high aspect ratio); a liner, which is doped with a relatively high
impurity concentration; and a filler -- usually vapor deposited oxide --
that planarizes the structure.

![](media/image3.wmf){width="5.25in" height="3.401388888888889in"}

Fig. 3. Diagram showing trench isolation in a CMOS structure.

Hole trapping can cause inversion in the trench structure, providing a
leakage path around the trench. The sensitivity of trench structures to
inversion is very sensitive to fabrication details. An early study
showed significant leakage currents in trench structures at about 15
krad(Si), implying that leakage in these isolation structures would
severely limit the performance of advanced devices in a radiation
environment \[7\]. However, later work on highly scaled devices has
shown that the total dose level is much higher, above 200 krad(Si)
\[8\]. The likely reason is that the trench structures used in modern
devices are somewhat different from those studied in \[7\]. Processing
techniques have been added that round the sharp corner, reducing the
electric field. A "cap" region, with high doping, is typically placed
over the top of the trench. Although this implies that trench isolation
leakage will be a less severe issue in practice, the earlier work in
\[7\] clearly shows the potential importance of trench isolation leakage
for commercial devices that are exposed to radiation.

[Characterization and Control]{.underline}

It is clear from the above discussion that LOCOS and trench isolation
structures both have the potential to reduce the radiation hardness of a
CMOS process unless specific controls are placed on the processing that
is related to those structures. There are several ways to do this. The
first approach would be to obtain the processing details from the
foundry relating to those structures, and monitor changes in those
processing steps that could potentially alter the radiation performance,
subjecting test structures to radiation testing whenever a significant
change occurs. The second, and more straightforward, is to periodically
do radiation tests on test structures to verify that the radiation
hardness has been maintained.

***Substrate Technology: Latchup***

Latchup is one of the most critical problems that affects CMOS devices.
Although it has been studied for many years, latchup is inherently
dependent on the specific layout and design techniques that are used
within a circuit \[10\], making it difficult to deal with the latchup
problem in a general way. Latchup trends are somewhat contradictory.
Although many highly scaled technologies are immune to radiation-induced
latchup, many advanced circuits exhibit latchup when they are exposed to
heavy ions or protons. Technology has increased the risk of failure from
latchup because it is possible to produce metallization voids in narrow
metallization regions even when the current is detected and turned off
within a short time after latchup occurs \[11\].

During the early 1990's, epitaxial substrates were expected to eliminate
latchup, even latchup induced by radiation. Although devices fabricated
in this way are more immune to latchup than devices with bulk
substrates, the real purpose of using the epitaxial substrate is to pack
devices closer together. Thus, many devices on epi-substrates are
sensitive to latchup.

It is generally possible to get information about the basic properties
of the substrate -- i.e., whether it is a bulk or epitaxial structure --
from the manufacturer. However, there is usually considerable latitude
in the resistivity of a bulk substrate (typical resistivity
specifications allow a factor of 3-4 variation) as well as in the
thickness of the epitaxial layer in an epitaxial process. Consequently
there is some ambiguity about the degree of control that this
information provides.

A recent experience with parts produced by Xilinx Corporation provides
an interesting example. Xilinx FPGAs that are produced for commercial
applications are fabricated by an outside foundry using a bulk process,
which turns out to be latchup sensitive. The company produces equivalent
devices for space applications by having them fabricated on epitaxial
substrates. Several radiation tests have been done on those devices
showing that they are immune to latchup. However, during a recent
radiation test that was done in cooperation with Xilinx, the parts that
were tested --provided by them for evaluation of fault-tolerant
techniques- exhibited latchup during testing. At first the suspicion was
that parts without the underlying low-resistivity substrate had been
provided by mistake, but spreading resistance measurements on one of the
latchup-sensitive samples showed that it had actually been fabricated on
an epitaxial layer. Fig. 4 shows the carrier concentration of the
substrate. The epitaxial layer extends to 5-6 microns. The carrier
concentration of the earlier devices that were immune to latchup had not
been measured, but this example shows the importance of adding specific
controls to the manufacturing process, as well as selected test
structure measurements, to ensure satisfactory radiation performance
when commercial foundries are used for radiation-tolerant circuits.

Other obvious factors that affect latchup are changes in the feature
size or design rules. It should be relatively easy to monitor those
properties from a commercial foundry, but such processes have to be in
place in order to assure radiation performance for those types of
devices.

It may also be possible to monitor latchup performance by doing
electrical tests on test structures that are specifically designed to be
latchup sensitive. The difficulty with that approach is that
electrically induced latchup involves different paths --essentially
surface paths --within the device, and may not be a reliable indicator
of the sensitivity of the process to radiation-induced latchup.
Electrically induced latchup also fails to monitor charge *collection*,
which is strongly affected by the substrate properties. Nevertheless,
process monitoring with latchup test structures may still be effective,
particularly if the underlying reason for latchup immunity is the
holding voltage. If the holding voltage exceeds the supply voltage,
latchup cannot be sustained.

![](media/image4.wmf){width="3.5104166666666665in"
height="2.9166666666666665in"}

Fig. 4. Carrier concentration vs. distance for a commercial 0.25 µm
process that exhibits latchup.

**Summary**

This report has discussed three different radiation response mechanisms
-- gate oxide trapping, field-oxide inversion, and latchup --that are
the most important issues for advanced CMOS devices. The basic
approaches for monitoring and controlling these effects are listed
below. Controls of this nature are likely in place for
radiation-hardened foundries, but need to be added when commercial
foundries are used.

1\. Geometry and Process Rules

> These two aspects of commercial foundries must be continually
> monitored. Although changes of that nature should be obvious through
> the relationship with the foundry, there is always the possibility
> that the foundry will shield users from those changes by migrating the
> design to a modified process.

2\. Gate Oxide Thickness

> The gate oxide thickness is of less importance for advanced processes,
> but the oxide thickness of all transistors used in the process should
> be known, evaluating the threshold voltage limits with the
> relationship in Equation 1. If the process is acceptable with the
> limiting value of gate oxide shift, then nothing further is required.
> If the process relies on significantly less charge trapping in order
> to meet requirements, then radiation tests should be done on test
> structures to verify that the radiation hardness continues to be
> acceptable.

3\. Field Oxide Inversion

> This is the most critical response mechanism for total dose, and the
> most difficult problem to control for commercial foundries. Although
> obtaining detailed processing information for the steps that are
> involved in fabricating field or trench oxides may help, they cannot
> be guaranteed to be effective. Radiation tests on tests structures are
> recommended.

4\. Latchup

> Latchup is another critical problem for commercial foundries. The
> example discussed earlier illustrates the importance of adding
> specific controls for latchup, and not relying on a general processing
> change to mitigate the problem. There are several ways to apply
> processing controls for latchup, including measurements of electrical
> latchup properties on test structures from each production lot,
> evaluating substrate resistivity, and irradiating latchup test
> structure or complete circuits with ion beams. A pulsed laser may be a
> cost-effective alternative for test structures, provided they are
> fabricated in an "open" structure that allows the laser beam to
> penetrate to the underlying regions.

The most difficult problem for ASIC devices (or for radiation-tolerant
devices on "marginally controlled" foundries is to determine which of
the above controls to apply. It is partly dependent on the relationship
between the circuit supplier (or ASIC designer) and the foundry. If
proprietary agreements are in place that provide the necessary insight
into the processes and design approach used by the foundry, it may be
possible to waive some -- or all -- of these requirements. There are
many successful cases where commercial foundries have been used to
produce radiation-tolerant parts. However, the ability to establish
these relationships may wane as they become dominated by proprietary
barriers and business-related processes.

**References**

\[1\] R. C. LaCoe, *et al*., "Total Dose Tolerance of the Commercial
Taiwan Semiconductor Manufacturing Company," 2001 IEEE Radiation Effects
Data Workshop, pp. 72-76.

\[2\] D. C. Mayer, *et al*., "Reliability Enhancement in
High-Performance MOSFETs by Annular Design," IEEE Trans. Nucl. Sci.,
**51**(6), pp. 3615-3620 (2004).

\[3\] J. M. McGarrity, "Considerations for Hardening MOS Devices and
Circuits for Low Radiation Doses," IEEE Trans. Nucl. Sci., **27**(6),
pp. 1739-1744 (1980).

\[4\] N. S. Saks, M. G. Ancona and J. A. Modola, "Radiation Effects in
MOS Capacitors with Very Thin Oxides at 80 K," IEEE Trans. Nucl. Sci.,
**31**(6), pp. 1249 (1984).

\[5\] D. Takashima and H. Nakano, "A Cell Transistor Scalable DRAM Array
Architecture," IEEE J. of Solid-State Circuits, **37**(5), pp. 587-591
(2002).

\[6\] A. Bryant, W. Hansch and T. Mii, "Characteristics of CMOS Device
Isolation for the ULSI Age," 1994 IEDM Technical Digest, p. 671.

\[7\] M. R. Shaneyfelt, *et al*., "Challenges in Hardening Technologies
Using Shallow-Trench Isolation," ," IEEE Trans. Nucl. Sci., **45**(6),
pp. 2584-2592 (1998).

\[8\] G. M. Swift, *et al*.,

\[9\] P. D. Agnello, "Process Requirements for the Continued Scaling of
CMOS," IBM Journal of Research and Development, **46**(2/3), pp. 299-316
(2002).

\[10\] A. H. Johnston, "The Influence of VLSI Technology Evolution on
Radiation-Induced Latchup," IEEE Trans. Nucl. Sci., **43**(2), pp.
505-521 (1996).

\[11\] H. N. Becker, T. F. Miyahira and A. H. Johnston, "Latent Damage
in CMOS Devices from Single-Event Latchup," IEEE Trans. Nucl. Sci.,
**49**(6), pp. 3082-3089 (2002).