30 August 2005

To: Paul Philp, DOE Project Manager, Run IIb D-Zero Detector Project

From: Vivian O'Dell, Project Manager, Run IIb D-Zero Detector Project

Subject: Run IIb D-Zero Detector Project Report for July 2005

Attached is the monthly report summarizing the July 2005 activities and
progress for the Fermilab RunIIb D-Zero Detector Project.

cc:

M. Abolins

J. Appel

E. Arroyo

L. Bagby

E. Barberis

A. Bean

J. Blazey

A. Bross

J. Butler

W. Cooper

M. Demarteau

D. Edmunds

T. Erickson

H. Evans

S. Fuess

G. Ginther

U. Heintz

M. Hildreth

R. Hirosky

D. Hoffer

K. Johns

M. Johnson

D.  Knapp

> R. Lipton
>
> J. Livengood

P. Lukens

R. McCarthy

H. Montgomery

M. Narain

A. Nomerotski

V. O'Dell

P. Oddone

P. Padley

R. Partridge

V. Pavlicek

TJ Sarlina

R. Sidwell

P. Slattery

K. Stanfield

RP Smith

J. Strait

L. Stutte

E. Temple

C. Trimby

V. White

D. Wood

T. Wyatt

C. Yoshikawa

Fermi National Accelerator Laboratory

Run IIb D-Zero Detector Project

**Fermilab Experiment Number E925**

################################################################################################################################################################################################################################## Progress Report No. 32 {#progress-report-no.-32 .unnumbered}

**July 2005**

############################### Project Description

The Tevatron Collider at Fermilab offers a unique capability to
elucidate many of the major issues currently facing particle physics.
Its high center-of-mass energy and recently upgraded luminosity offer us
the capability of shedding light on the Higgs mechanism - which has the
potential of offering insight into the origin of mass - and pushing the
boundaries of searches for supersymmetry and other new phenomena beyond
the Standard Model. It also makes accessible improved precision
measurements of the W boson and top quark properties that, by further
constraining the Standard Model, provide increasingly stringent tests of
its precepts. The Tevatron offers the most cogent experimental probes of
Standard Model physics, and beyond, during the coming 3+ years.

The Run IIb D-Zero Detector Project has been designed to allow the
D-Zero Experiment to continue operating in the high intensity Tevatron
environment for the remainder of the coming decade. The integrated
exposure of the D-Zero Detector to colliding beam will result in
radiation damage to the silicon detector that will compromise its
efficiency. Adequate b-tagging is an essential ingredient of the Run II
physics program. In order to maintain adequate b-tagging, D-Zero is
adding an inner layer detector of radiation-hard silicon to enhance
tracking efficiency as the Run IIa detector ages. In addition, the
trigger system must be upgraded in order to provide sufficient rejection
and to limit the dead time at the higher instantaneous rates that will
be delivered by the Tevatron as the run progresses. The Run IIb D-Zero
Detector Project provides for the additional D-Zero Layer 0 silicon
detector and the upgrade of the D-Zero trigger, DAQ, and online systems
in order to enable the continued efficient running of the experiment,
and the acquisition of forefront physics data, for the foreseeable
lifetime of the Tevatron collider program.

############################### Overview of Project Status 

In July, work continued on testing and integrating the RunIIb L1Cal
system at Fermilab. Tests of BER, data integrity, trigger performance
and timing were all begun during July and are well advanced. The
prototype ADF Transition Cards were tested and released for production.
The error rate between the TAB and L2/L3 was found to be caused by a
faulty VTM and FIC input channel (neither of which are part of the new
boards for the L1Cal). A project review for the L1Cal trigger has been
scheduled for late August.

The L1 Cal-Track Match trigger was successfully tested in the DZero
system with a full vertical slice and in its final configuration. All of
the boards for the system have been bench tested except for 2/6 of the
crate managers (which are actually spares). Testing with the L1Cal
inputs is expected to happen in August.

Two full crates of DFEA2's for the L1CTT have been powered all month and
individual boards have been tested. 1 board at FNAL had powerup problems
and is dead awaiting a power converter, however there are still plenty
of working boards for the full system. A Technical Readiness Review was
held July 29, and the review was very positive.

For the L2Betas work continues mainly on software tools to run on the L2
processors. The L2 b-tagging algorithm has been coded so that it can be
used online or the trigger simulator and a D0note has been released
describing the tool. In addition work continues on L2 vertexing studies
and a D0note is in progress. Delivery of the hardware has been delayed
to early August.

For the L2STT project, the remaining Buffer Controller Cards have now
been tested and the hardware is complete. Work continues on testing and
modifying the firmware for RunIIb.

The functionality of the L1Cal simulator is now complete and integrated
into the D0 trigger simulator. The L1CalTrack simulator was also
integrated into the D0 trigger simulator during July and work is ongoing
to optimize the CalTrack algorithms both with Monte Carlo and data. Not
much progress was made with the L1CTT simulation during July, but work
is ramping up in August for this.

The 128 L3 nodes arrived at the end of July and were installed by the
vendor. The next step is to burn in the nodes for 30 days, which should
be completed by the end of August. As reported in June, the only
outstanding purchase for the RunIIb online upgrade is for a server for
the DAQ event data-logging chain and this is being ordered now and is
expected to be delivered around the end of August.

The testing strategy for the production TripT chips has been further
defined, and the prototype TripT's have been tested in much more detail,
indicating that the prototype chips meet specifications. The robot
testing hardware has been built but work on the FPGA and tester code was
behind. The AFEIIt prototype design and layout were completed and the
files sent to the board manufacturer. Parts orders began early to ensure
that the parts would be available to the stuffing house as soon as the
boards were there.

############################### Project Milestone Summary (as of 31 July 2005)

The DOE baseline milestones, defined in the modified DOE Project
Execution Plan, are shown in Figure 1 as solid diamonds. Open are the
Project's forecast dates for achieving the milestones. Actual dates of
achieving milestones are shown as solid stars. The Trigger, Online,
Layer 0 Silicon, and AFE milestones are shown separately and sorted by
current forecast date.

Table 1 lists approved DOE milestone dates along with the project's
current, and previous month's, forecast for achieving them. Milestones
with forecast dates that have changed significantly in the last month
are discussed in Section X of this report.

![](media/image1.png){width="8.143055555555556in"
height="6.294444444444444in"}

**Figure 1:** Run IIb D-Zero Detector Project DOE Level 2/Director's
Milestones. Closed (open) diamonds represent baseline (current forecast)
dates. Closed stars represent completed milestones.

  ----------------------------- ------------------ ---------- ---------- ------------------ ----------- -----------
  **L2/Director\'s Milestones                                                                           
  vs Current Forecast**                                                                                 

  **(Sorted by L2/Director\'s                                                                           
  Baseline Date)**                                                                                      

  **Milestone Description**     **L2/Director\'s   **Last     **This     **L2/Director\'s   **Monthly   **Notes**
                                Baseline (7/05)**  Month\'s   Month\'s   Variance in work   Variance in 
                                                   Forecast   Forecast   days**             work days** 
                                                   (6/05)**   (7/05)**                                  

  **WBS 1.2 Trigger**                                                                                    

  L1 Calorimeter Trigger        05/03/04           05/26/04   05/26/04   18                 0           Complete
  TAB/GAB Prototyping Complete                                                                          

  Start Production TAB          02/25/05           10/08/04   10/08/04   \(90\)             0           Complete
  Fabrication                                                                                           

  L2 Silicon Track Trigger      10/17/05           08/09/05   08/09/05   \(48\)             0            
  Production and Testing                                                                                
  Complete                                                                                              

  L1 Trigger Cal-Trk Match      01/03/06           08/16/05   09/15/05   \(68\)             21           
  Production and Testing                                                                                
  Completed                                                                                             

  L1 Calorimeter Trigger        01/05/06           04/29/05   04/29/05   \(167\)            0           Complete
  Production And Testing                                                                                
  Complete                                                                                              

  L2 Beta Trigger Production    01/05/06           08/16/05   08/16/05   \(92\)             0            
  And Testing Complete                                                                                  

  L2 Trigger Upgrade Production 01/05/06           08/16/05   08/16/05   \(92\)             0            
  and Testing Complete                                                                                  

  L1 Central Track Trigger      01/10/06           07/29/05   09/02/05   \(82\)             25           
  Production And Testing                                                                                
  Complete                                                                                              

  L1 Trigger Upgrade Production 04/10/06           08/16/05   09/15/05   \(136\)            21           
  and Testing Complete                                                                                  

  **WBS 1.3 Online/DAQ**                                                                                 

  Online System Production and  10/07/05           05/23/05   05/23/05   \(96\)             0           Complete
  Testing Complete                                                                                      

  **WBS 1.6 Layer 0 Silicon                                                                              
  Detector**                                                                                            

  Freeze Mechanical Parameters  01/06/04           12/15/03   12/15/03   \(9\)              0           Complete

  Release Sensors for           05/26/04           02/26/04   02/26/04   \(63\)             0           Complete
  Production                                                                                            

  Release Hybrids for           06/04/04           03/25/04   03/25/04   \(50\)             0           Complete
  Production                                                                                            

  Release Analog Cables for     06/04/04           03/19/04   03/19/04   \(54\)             0           Complete
  Production                                                                                            

  All Analog Cables Delivered   03/11/05           08/10/04   08/10/04   \(141\)            0           Complete
  and Tested                                                                                            

  All Sensors Delivered and     05/23/05           09/28/04   09/28/04   \(159\)            0           Complete
  Tested                                                                                                

  All L0 Hybrids Delivered,     08/25/05           01/25/05   01/25/05   \(150\)            0           Complete
  Stuffed, and Tested                                                                                   

  All Adapter Cards Delivered   10/17/05           05/20/05   05/20/05   \(98\)             0           Complete
  and Tested                                                                                            

  Silicon L0 Module Production  11/29/05           04/22/05   04/22/05   \(151\)            0           Complete
  Complete                                                                                              

  Layer 0 Silicon Detector      05/25/06           09/16/05   09/20/05   \(166\)            2            
  Ready to Move to DAB                                                                                  

  **WBS 1.7 AFEIIt**                                                                                     

  AFEII Boards Complete         09/29/06           08/17/06   09/12/06   \(12\)             17           

                                                                                            status      7/31/2005
                                                                                            date:       
  ----------------------------- ------------------ ---------- ---------- ------------------ ----------- -----------

> **Table 1:** Run IIb D-Zero Detector Project DOE Level 2/Director's
> Milestones vs. Current Month forecast. Monthly variances are also
> provided.

############################### Management Highlights -- V. O'Dell

The project has begun holding "Technical Readiness Reviews" which are
reviews of subprojects to assess their readiness to install in the DZero
detector. The review covers online and some offline software (an example
is subproject unpacking code), maintenance, full system tests and
commissioning plans. The first subproject to be reviewed was the L1CTT.
Although the review report is not yet public, the review was overall
very positive.

A similar review for the L1 Calorimeter Trigger will be held in
August/September. The review of the Silicon L0 will likely be held in
September.

# Procurement Highlights -- V. O'Dell

All of the large procurements are now over for the IIb project except
for the AFEII-t part of the project. The TripT requisition has gone out
and represents about a \$200k cost to the project. The next large
purchase will be for the production order of parts and boards for the
AFEIIt. The parts are scheduled to be ordered in October '05 (\~\$300k),
the boards in December '05 (\~60k) and the boards will be stuffed early
February '06 (\~\$100k).

############################### Trigger Highlights (WBS 1.2) -- B. P. Padley, D. Wood

At this point, almost all of the remaining work in the trigger upgrade
consists of system tests at Fermilab with bench-tested production
components. The purpose of these tests is to learn as much as possible
about the integrated functioning of the systems before installation and
to exercise the tools that will be used in the installation and final
commissioning of the systems.

Of special note is the Technical Readiness Review (TRR) for the L1CTT
upgrade which was held on July 29th. While each of the major components
of the L1CTT (crates, crate controllers, DFEA2) had been reviewed
individually (with Production Readiness Reviews) before production, this
review was a final opportunity to confirm that the system worked
together as an integrated whole, and that all necessary testing had been
done in preparation for installation. The full results of the L1CTT TRR
should appear in next month\'s report, but it was already clear that the
review was quite positive. A TRR for the L1Cal upgrade is scheduled for
late August.

1.  **Level 1 Calorimeter Trigger (WBS 1.2.1) -- M. Abolins, H. Evans**

> The focus of work on the L1Cal system has shifted almost entirely to
> Fermilab. Work at MSU and Nevis has continued, but is mainly in
> response to features observed during the integration process and is
> described below.
>
> Design and testing of the ADF transition system prototypes were
> finished during the month of July. The remaining card, the ATC, was
> released for production after successful transmission of pseudo-random
> ADF data to a TAB was accomplished. (Extensive tests of the BLS-to-ADF
> input path through this card were completed in June) Some warping has
> been observed on approximately half of the first round of ATC cards
> received from the producer. This is understood as being due to an
> oversight in the fabrication process and will be corrected for the
> next round of boards being made.
>
> The design of a continuity/short tester for the transition system was
> reviewed successfully and is now being fabricated. Finally, a proposal
> for testing the transition system, involving minimal mechanical
> manipulations of the boards and ADF crates, has been drafted and is
> being reviewed by the group. Several sets of transition system
> components have been tested following this procedure and are now being
> installed in the Test Area.
>
> On the system testing side, significant progress has been made on the
> following output paths.
>
> 1\) TAB to L2/L3
>
> a\) The presumed loss of sync and protocol errors observed on the TAB
> G-Link outputs to L2 and L3 turned out to be due to a combination of a
> bad VTM and problems with the FIC input channel number 0.
>
> b\) Sending data to VTM/FIC (L2) and VTM/VRB (L3) has now been
> accomplished with no sync-loss or data errors reported by the
> receiving boards.
>
> c\) BER tests have been performed on the L2 data transmission using an
> L1Accept rate of 6 kHz and transmitting data for \~1/2 hour. No parity
> errors were observed leading to a BER of \<10\^-9. Longer tests of
> this transmission are planned.
>
> 2\) First GAB to L2/L3 data transmission tests were made. No sync-loss
> or data errors were observed in runs of many minutes. This
> transmission mechanism is working well.
>
> 3\) A coherent strategy for adjusted the timing of the TABs and GAB
> has developed and is being pursued. The TAB and GAB have now been
> timed in and are ready for offline tests comparing TT Et\'s to those
> found using the precision readout.
>
> 4\) Trigger terms from the GAB were successfully sent to the TFW with
> the correct timing.
>
> 5\) Modifications are being made to the VRB firmware to allow BER
> tests be on the TAB and GAB data transmissions to L3.
>
> 6\) Special triggers allowing us to compare precision readout and TT
> efficiently are being prepared.
>
> 7\) Final preparation of documents for the L1Cal Test Area ORC are
> being made.
>
> 8\) Daily meetings are now being held at Fermilab to coordinate work
> at the Test Area for the next 24 hours.
>
> At MSU, work continued on integrating the TAB/GAB control software
> into the final L1Cal online framework. Work was also done on this at
> Fermilab by MSU and Columbia people.
>
> At Nevis, most of the month was devoted to developing possible
> solutions to the presumed G-Link data transmission problems. Based on
> this work a slightly modified version of the VME/SCL card has been
> designed, which provides several mechanisms for reducing sources of
> jitter in the distribution of clocks used for G-Link data
> transmission. Even though there is now no indication that these
> improvements are needed, several new VME/SCL boards are being made
> since more spares were required anyway. These boards have now been
> received and the first one is being assembled at Nevis for testing
> next week.
>
> In order to more easily diagnose any problems with the optics that may
> arise in the future, a small G-Link Receiver Test Card has also been
> designed, produced and assembled. It is under test at Nevis now. This
> card will allow quick measurements of loss of sync and of BERs on data
> transmission from the TAB and GAB. It can be used at either Nevis or
> Fermilab and will provide a good way of cross-checking results
> obtained at the two sites.

2.  **Level 1 Calorimeter/Track Matching (WBS 1.2.2) -- K. Johns**

> We successfully tested the L1CalTrack system in its final
> configuration. Namely, triggers were generated in the trigger crate
> and sent to the manager crate. There they were further processed and
> sent to the trigger framework. Both crates were readout into level 3.
>
> All cables needed by the L1CTT system were terminated by Fermilab
> technicians.
>
> We bench tested 16/16 MTCxx\'s including two spares for the L1Mu
> system. We bench tested 14/14 UFB\'s. We bench tested 4/6 MTCM\'s. Two
> of these six are spares for the L1Mu system though. There are a few
> minor problems to fix on a couple of boards but we have enough boards
> successfully tested to populate the full L1CalTrack system.

############################### Level 1 Track Trigger (WBS 1.2.3) -- D. Lincoln, M. Narain

> July was a productive month in the CTT project saga. Two full crates
> of DFEA2\'s have been powered all month. Individual boards have been
> tested. A total of 49 boards were tested extensively again at FNAL.
> Each board was fed about 20K random vectors (3-4 hrs run). With the
> tests at FNAL, 1 board had powerup problems. Thus we now have 56
> working boards. This board will be recovered in the next month, as the
> power converter has to be ordered.
>
> BER tests at BU gave expected rates. With short cables errors, the bit
> error rate has been shown to be less than 10E-16. As of last report,
> with long cables, a specific cable has seen a bit error rate of less
> than 10E-16. Larger statistics tests need the infrastructure on the
> platform.
>
> Software has been written that will help us look at the singlet
> efficiencies. The final debugging of this software is underway.
>
> On July 29th, the L1CTT upgrade had its Technical Readiness Review
> (TRR). This was the final internal project review for the L1CTT, and
> it should declare the upgrade to be technically complete and
> functioning as a system and ready for installation. The review report
> is not yet available, but the review was very positive. Only a few
> issues were raised by the reviewers, and these should be able to be
> resolved quickly.

############################### Level 2 Beta (WBS 1.2.4) -- R. Hirosky

> In algorithm development, work continued on L2 vertexing studies.
> Track selection studies are completed and a D0NOte is in progress. The
> L2 b-tagging algorithm has been coded into a new level-2 tool that may
> be run online or in the trigger simulator. A D0Note has been released
> describing the tool.
>
> On the hardware side, the Run2b Single Board Computers (SBCs) did not
> arrive as expected in July. However, we spoke to the company and the
> board did arrive in the California office and were being test prior to
> shipment at the end of July. Expected deliver is now early August.

############################### Silicon Track Trigger (WBS 1.2.5) -- U. Heintz

> In July the STT hardware production was completed. At the end of June,
> the only task remaining was the test of the Buffer Controllers. These
> were all tested by July 15. This completes the STT hardware production
> complete milestone (1.2.5.15) as of 7/15/2005.
>
> STC firmware tests proceeded (slowly -- as allowed by data taking) at
> Fermilab.

############################### Trigger Simulation (WBS 1.2.6) -- E. Barberis, M. Hildreth

> Functionality of the L1CAL simulator is complete. The L1CAL simulator
> is integrated in the D0 trigger simulator, outputs correctly to the
> data flow, counts the objects passing each trigger defined so far, and
> sets the corresponding trigger bits. Extra parameters have been
> defined to specify the pedestals for the Inter-Cryostat Region towers,
> which, in the hardware, are treated differently from the rest of the
> CAL trigger towers. Testing and optimization of the L1CAL simulator
> will continue within the current D0 trigger groups, in preparation for
> a final Run IIb trigger list. The L1CAL simulator is used as input by
> the L1CalTrack simulator.
>
> The L1CalTrack simulator is integrated in the D0 trigger simulator,
> and work has now concentrated in the optimization, both with Monte
> Carlo and data, of the L1CalTrack electron and Tau algorithms.
>
> There is nothing new to report this month for the L1CTT simulator (for
> which we need to extend the completion date from July 15th to August
> 15th). By the second week in August we expect to see, for the L1CTT
> simulator: implementation of the Run IIb equation parser (which has
> been written), implementation of the track terms, and first rate
> estimates.

I.  **DAQ/Online Highlights (WBS 1.3) -- S. Fuess**

############################### Level 3 Systems (WBS 1.3.1) D. Chapin, G. Watts

> The complete order of 128 Level 3 nodes arrived during the last week
> of July and was installed by the vendor. We are now at the beginning
> of a 30-day burn-in period. We expect this period to complete at the
> end of August. By this time, the new Level 3 nodes should be
> completely integrated into the running DAQ system.

############################### Network and Host Systems (WBS 1.3.2) -- J. Fitzmaurice, S. Krzywdzinski

> **Online/DAQ Network: 1.3.2.1**
>
> An order, managed by the Computing Division Network Group, for a new
> Supervisor module and a 48-port Gigabit module for the Online Cisco
> 6509 was placed 7/7/2005, but has not yet been delivered. This upgrade
> expands the gigabit networking capacity for the core servers. In the
> interim, several host servers are supported on a Gigabit capable
> satellite switch.
>
> **Control and Monitoring systems: 1.3.2.2, 1.3.2.3**
>
> The upgrade of the interactive control room and the event monitoring
> systems is a DØ operations task, and is part of the operations budget.
> A requisition to add 10 new nodes was submitted at the end of July. We
> are in the process of evaluating systems for Control Room
> replacements, and expect to requisition several during August.
>
> **Storage, DAQ Host, ORACLE, & File Server Systems: 1.3.2.4, 1.3.2.6,
> 1.3.2.7, 1.3.2.8**
>
> The RunIIb plan calls for a single additional quad-processor system to
> be purchased as a principal node in the DAQ event data-logging chain.
> An evaluation of the performance of newly installed systems has
> determined that dual-processor systems are adequate and much less
> expensive. A requisition for these remaining systems has been
> submitted \[a purchase order was placed 8/3/2005, with an expected
> delivery of 8/29/2005\], which will complete the only outstanding
> purchase to be made for the Online/DAQ portion of the RunIIb upgrade.

############################### Control Systems (WBS 1.3.3) -- F. Bartlett, G. Savage, V. Sirotenko

> The MVME5500 processor purchase for the control system upgrade is
> complete. We continue the process of installing the new processors.
> There are no outstanding issues.

II. **Silicon Detector Layer 0 Highlights (WBS 1.6) -- A. Bean, R.
    Lipton**

> The 50% test of the Layer 0 "A" layer was completed this month, and
> while some noise was found, it appears to be coherent pickup noise
> which can be corrected for by real time pedestal subtraction. There
> may also be other ways of reducing the noise, and these ideas will be
> explored with the full detector. All the parts were assembled this
> month for reading out the full detector.

############################### Readout (WBS 1.6.2) -- R. Sidwell, K. Hanagaki

> Testing of fully populated A-layer was performed. All the 24 modules
> were successfully read out simultaneously. The total noise is
> typically between 3 and 4 ADC counts, while the differential noise is
> 2 ADC counts. The excess is attributed to coherent pickup noise, which
> can be eliminated by real time pedestal subtraction. The bandwidth
> scan was performed. The result is as expected. The sparse read out was
> tested and worked without problems.
>
> Using the electrical testing support structure, we investigated the
> source of the coherent pickup noise. There are two findings, 1) the
> smaller the isolating resistance between the SVX4 and common ground,
> the smaller the noise , and 2) putting ferrite onto SVX4 power lines
> significantly reduces the noise. These are the clues to improve the
> noise for the real detector.
>
> The preparation for testing the remaining half of the detectors, i.e.
> full read out test, was in progress. We received 18 junction cards and
> 5 adaptor cards from KSU. This gives us enough readout parts for the
> full testing with spares.
>
> Some minor modifications of the adaptor card were proposed, discussed
> and tested. This includes removal of the inverter for change mode,
> which latches the mode 0 and mode 1, and results in the proper timing
> of control signals. The other is proper termination of the change mode
> lines. The modified adaptor card worked without causing read out
> failures.
>
> The prototype modules in the platform, with a mixture of SVX2 and SVX4
> chips, were successfully read out by the global DAQ.

############################### Mechanical Design and Fabrication (WBS 1.6.3) -- W. Cooper

> Sensor -- hybrid module installation on the Layer 0 structure
> continued under coordinate measuring machine control of placement. At
> the end of the month, two modules remained to be installed.
> Measurements made as each module was installed suggested good
> placement precision. Final measurements of module positions and
> orientations will be made after Layer 0 electrical testing has been
> completed.
>
> "Long" and "short" tools for Layer 0 installation were completed by
> the University of Washington and delivered to Fermilab. CMM inspection
> of the long tool remains to be made, but visual examination and
> partial inspections by the University of Washington indicate that both
> tools meet tolerances should be fine. "Intermediate" tools (extensions
> to Layer 0 on which cables would be dressed) are being fabricated by
> both the University of Washington and Lab 3.
>
> Preparations continued for a Layer 0 installation test at Lab 3 using
> mock-ups of the solenoid and calorimeter ends and a mechanical
> prototype of the Layer 0 structure. Lab 3 is adding "dummy" sensors,
> hybrids, and cables to the prototype Layer 0 structure, so that its
> profile and weight will reasonably represent those of a completed
> Layer 0.

############################### Detector Modules and Final Detector Integration (WBS 1.6.4, 1.6.5) -- L. Bagby

> Unattended operation of the L0 detector was decided to be unnecessary.
> All safety review issues have been addressed. All hardware is in place
> to instrument the remaining 50% of the detector for reading out. The
> operation of the interlock system was confirmed after cooling system
> modifications were implemented. RTD cable adapter cards have been
> manufactured. Arrangements are being made to have the connectors
> installed.

III. **Analog Front End Highlights (WBS 1.7) -- A. Bross, P. Rubinov**

```{=html}
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1.  **TripT (WBS 1.7.4) -- L. Bellantoni**

> This month\'s activity was about testing and the preparation
> therefore.  We are taking a two-pronged approach: detailed manual
> (bench) testing of \~5 chips on a bench, and qualification (robot)
> testing for the full sample. The bench test was done; we have data for
> the turn on thresholds for 5 chips, in addition to the 2 that were
> tested earlier sans packages.  The\
> data indicate that the spec will be met.  The automatic test facility
> was under development in July.  The mechanical socket clamp was
> installed and the testing board was received and stuffed.  Some
> hardware modifications have proven to be necessary, but not
> difficult.  As of the end of June, work on the FPGA and tester code
> had not begun, and this was a bit of an issue. There has been
> subsequent progress on this front. The board intended for automatic
> testing was also used for a simple but hopefully effective check of
> prototype chips for use in the prototype\
> boards.

2.  **AFEII-t board (WBS 1.7.5) -- P. Rubinov**

> AFEIIt prototypes design and layout were completed, design files were
> send to the manufacturer of the boards and work has started on the
> necessary documentation for the assembly of the boards. Part orders
> are in progress and on track to have all parts on hand in time for the
> arrival of the bare PCBs, so the boards can move to assembly phase as
> quickly as possible.

3.  **Code Development (WBS 1.7.6)**

> A number of meetings were held with relevant personnel to plan the
> work and finalize the specifications. Some of the required
> documentation was produced.

# Schedule Variance Analysis (as of 31 July 2005)

Schedule variances are reported against director's milestones in section
III. Thirteen milestones have been successfully achieved. All remaining
milestones are projected ahead of the DOE baseline dates.

1.  **D-Zero Run IIb Trigger Upgrade (WBS 1.2)**

> The L1CTT lost 25 days in the last month due to increased testing at
> Fermilab. Although the boards as sent to FNAL are working, more time
> has been devoted for testing at FNAL than originally planned. Some of
> this testing will help shorten the overall time needed for
> installation and commissioning the L1CTT into the D0 detector. Note
> that the Technical Readiness Review for the L1CTT stated that the
> L1CTT was reading to install.
>
> The Cal-Track Match has lost 21 days in the last month due to manpower
> shortage for testing the system. However a full vertical slice is
> being installed into the D0 detector and trigger system and all the
> boards and associated hardware have been bench tested and are ready to
> test in situ. This 21 days is what drives the "L1 Trigger Upgrade
> Production and Testing Complete" which is also delayed by 21 days in
> the last month.

2.  **D-Zero Run IIb Online (WBS 1.3)**

There is no unfavorable schedule variance for this subproject and its
milestone has been met.

############################### D-Zero Run IIb Layer 0 Upgrade (WBS 1.6)

There is no unfavorable schedule variance for this subproject.

############################### D-Zero Run IIb AFEII Upgrade (WBS 1.7)

> The AFEII has lost 17 days in the last month due to delays in the
> design of the hardware/software for the robotic chip tester. This
> should be caught up by the time the devices arrive.

############################### Department of Energy Milestones (as of 31 July 2005)

No DOE milestones were predicted or achieved during the month of July.
Table 2 (below) shows the status of all DOE Milestones.

  --------------------------- ----------- ---------- ---------- ------------------ ----------- -----------
  **L1 DOE Milestones vs                                                                       
  Current Forecast**                                                                           

  **(Sorted by L1 Baseline                                                                     
  Date)**                                                                                      

  **Milestone Description**   **L1        **Last     **This     **L2/Director\'s   **Monthly   **Notes**
                              Milestone   Month\'s   Month\'s   Variance (work     Variance    
                              (7/05)**    Forecast   Forecast   days)**            (work       
                                          (6/05)**   (7/05)**                      days)**     

  **WBS 1.2 Trigger**                                                                           

  L2 Trigger Upgrade          01/05/06    08/16/05   08/16/05   \(92\)             0            
  Production and Testing                                                                       
  Complete                                                                                     

  L1 Trigger Upgrade          04/10/06    08/16/05   09/15/05   \(136\)            21           
  Production and Testing                                                                       
  Complete                                                                                     

  **WBS 1.3 Online/DAQ**                                                                        

  Online System Production    10/07/05    05/23/05   05/23/05   \(96\)             0           Complete 
  and Testing Complete                                                                         

  **WBS 1.6 Layer 0 Silicon                                                                     
  Detector**                                                                                   

  Layer 0 Silicon Detector    05/25/06    09/16/05   09/20/05   \(166\)            2            
  Ready to Move to DAB                                                                         

  **WBS 1.7 AFEIIt**                                                                           

  AFEII Boards Complete       09/29/06    08/17/06   09/12/06   \(12\)             17          

                                                                                   status      7/31/2005
                                                                                   date:       
  --------------------------- ----------- ---------- ---------- ------------------ ----------- -----------

> **Table 2:** Run IIb D-Zero Detector Project DOE Level 1 Milestones
> vs. Current Month and Previous Month's forecast. Entries are sorted by
> DOE L1 Milestone date. Monthly variances are also provided.

############################### Cost Performance Report (as of 31 July 2005)

This report is generated from COBRA and provides a summary of the WBS
1.2-1.4 costs of the Project down to Level 3 of the Work Breakdown
Structure. Silicon detector subproject closeout costs are not tracked
here. Input data originates with the status (% Complete) of the Project
schedules as reported by the Level 2 managers and actual costs extracted
from the Fermilab accounting system. Where possible, costs are accrued
for items that have been delivered, but not yet invoiced. Financial
summaries are shown for this reporting period (columns 2-6) as well as
the project to date (columns 7-11). Column 12 contains our baseline BAC,
and will only be changed after the formal implementation of the Change
Control process. Column 13 is the projected BAC, based on the current
month's schedule.

![](media/image2.png){width="8.3375in" height="6.430555555555555in"}

############################### Obligation Reports (as of 31 July 2005)

The DZero Obligation Reports can be found below. The first report shows
total obligations without the cost of the original Run IIb Silicon and
related closeout costs. The second report shows all obligations.

![](media/image3.png){width="8.707638888888889in"
height="6.716666666666667in"}

![](media/image4.png){width="8.672916666666667in"
height="6.696527777777778in"}