> 11/13/2023
>
> **B.Baldin,**
>
> **I.Churin,**
>
> **D.Wood**

**Specification for muon readout crate software**

**Introduction**

The main task of this specification is to give guidelines for the design
of working program serving

muon readout crates. The specification is based on D0 documents and
other sources describing

-   DAQ Geographic Section GS (synonym of a muon readout crate)

-   D0 Run II online computing system

-   Muon L2 & L3 data formats,

-   MFC, MRC, VBD,

-   MVME162LX,

-   VxWorks real-time OS

-   EPICS

-   Cross software development system for Motorola 68k CPUs

Muon readout crates in the D0 DAQ hardware

D0 detector data streams pass on hardware objects from up to down. These
objects (systems & subsystems) are shown as follows. It is assumed that
the reader is familiar with the abbreviations used.

  ----------- ---------- -------------------------------------------------
  Object      Location   Subsystems

  ----------- ---------- -------------------------------------------------

  ------------- ----------- -------------- -------------- -------------- -------------
  Muon          D0          PDT            MDT            SC             L1 Trigger
  Detectors &   Collision                                                
  L1 Trigger    hall                                                     

  Muon Detector D0          FEB            ADB, MDC       SFE            MTC
  electronics   Collision                                                
                hall                                                     

  Muon          D0          CB             MDRC, M68k CPU SRC, M68k CPU  MTCM
  Front-end     Collision                                                
  Control Unit  hall                                                     

  Muon Readout  MCH         MFC,MRC,VBD,   MFC,MRC,VBD,   MFC,MRC,VBD,   MFC,MRC,VBD
  VME crates                M68k CPU       M68k CPU       M68k CPU       M68k CPU
  ------------- ----------- -------------- -------------- -------------- -------------

+----------+--------+-------------------------------------------------+
| L3       | MCH    | VRC(Vertical Readout Controller), SB(Segment    |
| Readout  |        | Bridge), MPM(Multi Port Memory)                 |
+----------+--------+-------------------------------------------------+
| L3       | DAB2   | PC Farm                                         |
| Filter   |        |                                                 |
| Nodes    |        |                                                 |
+----------+--------+-------------------------------------------------+
| D0       | DAB2   | 1 Gb/s & 100 Mb/s Ethernet Switch, AlphaServer  |
| Central  |        | 4000 UNIX Hosts,                                |
| UNIX     |        |                                                 |
| Hosts    |        | D0 detector control & monitoring, Event         |
|          |        | monitoring, Control room activities             |
+----------+--------+-------------------------------------------------+
| FCC      | F      | Logging to tape, off-line processing.           |
|          | eynman |                                                 |
|          | CD     |                                                 |
|          | Bu     |                                                 |
|          | ilding |                                                 |
+----------+--------+-------------------------------------------------+

Muon subsystem passes data stream separately from its detector to
front-end electronics and to Front-end VME Control Unit for pipelining
and other processing necessary for L2 and L3 Levels. In case of PDT
subsystem the CB (Control Board) performs functions of a Front-end VME
crate. Muon readout crates receive L3 data from front-end Control units,
check for errors and transmit L3 data to the next level of selection and
processing. Data to L3 filter nodes are sent via VBD (VME Buffer
Driver).

Hardware components of the muon readout crate and data links

Each muon readout crate consists of the following modules:

+--------------+------------------------------------------------+------+
| Module type  | Parameters                                     | Nu   |
|              |                                                | mber |
|              |                                                | of   |
|              |                                                | mod  |
|              |                                                | ules |
+--------------+------------------------------------------------+------+
| MV           | CPU MC68040, 32-bit, 25 MHz, 4MB RAM, 128KB    | 1    |
| ME162LX-222a | SRAM with battery backup, 1 Mb Flash memory    |      |
| Embedded     | with MVME162BUG installed, 8K by 8 NVRAM/TOD   |      |
| Controller   | clock, Ethernet AUI port with additional       |      |
|              | transceiver JD50 to 10BaseT (twisted pairs),   |      |
|              | four serial ports, VMEbus interface A32/D32,   |      |
|              | VMEbus interrupter and VMEbus interrupt        |      |
|              | handler                                        |      |
+--------------+------------------------------------------------+------+
| VME Buffer   | 30 Mb/s VME transfer rate, rapid error         | 1    |
| Driver (VBD) | recovery, on-board diagnostic, two buffers of  |      |
|              | 256 KB each. Every buffer has port to VME      |      |
|              | memory and port to external I/O. The I/O port  |      |
|              | works under control of independent readout     |      |
|              | controller with token ring readout             |      |
|              | arbitration.                                   |      |
+--------------+------------------------------------------------+------+
| VBD Bus      | Front panel VBD bus terminator. There are only |      |
| Terminator   | two terminators in the system of Muon Readout  |      |
| (Term)\*     | Crates.                                        |      |
+--------------+------------------------------------------------+------+
| Trigger      | Two modes of operation: internal timing from   | 1    |
| Fanout Card  | sequencer, external timing from Trigger        |      |
| (TFC)\*      | Framework (TFW). It provides both local data   |      |
|              | acquisition from different muon detectors and  |      |
|              | local testing of any part of the muon system.  |      |
|              |                                                |      |
|              | There is only one TFC in the system of Muon    |      |
|              | Readout Crates.                                |      |
+--------------+------------------------------------------------+------+
| Muon Fanout  | Three sources of timing signals: TFW by means  | 1    |
| Card (MFC)   | of SCL (16 bit at 53 MHz), TFC via Lemo and    |      |
|              | built-in timer-sequencer controlled by VME     |      |
|              | master CPU. Fanout all timing to front-end     |      |
|              | crates through VME local dedicated bus and     |      |
|              | MRCs. Hardware for crossing and turn number    |      |
|              | checking based on FIFOs.                       |      |
|              |                                                |      |
|              | Continuous hardware error handling. VMEbus     |      |
|              | interface, VMEbus interrupter.                 |      |
+--------------+------------------------------------------------+------+
| Muon Readout | Two identical interfaces (A and B) to two      | Up   |
| Card (MRC)   | front-end crates (systems). Every interface    | to   |
|              | has 160 Mb/s HOTLink receiver of L3 data from  | 12   |
|              | front-end crates and 8 Kb dual-port memory.    |      |
|              | There are three channels for communicating     |      |
|              | with front-end crates: 1) micro-coax four line |      |
|              | port for RF53MHz, ENC, L3DATA and L2DATA, 2)   |      |
|              | parallel connection for control of the         |      |
|              | front-ends, 3) serial controller for           |      |
|              | communication with front-end DSPs.             |      |
+--------------+------------------------------------------------+------+

<table>
<colgroup>
<col style="width: 5%" />
<col style="width: 4%" />
<col style="width: 4%" />
<col style="width: 4%" />
<col style="width: 4%" />
<col style="width: 4%" />
<col style="width: 4%" />
<col style="width: 4%" />
<col style="width: 4%" />
<col style="width: 4%" />
<col style="width: 36%" />
<col style="width: 5%" />
<col style="width: 4%" />
<col style="width: 4%" />
</colgroup>
<tbody>
<tr class="odd">
<td>MVME162</td>
<td>VBD</td>
<td>TERM*</td>
<td><p>TFC</p>
<p>*</p></td>
<td></td>
<td></td>
<td>MFC</td>
<td>MRC1</td>
<td>MRC2</td>
<td>MRC3</td>
<td>Up to 12 MRCs max…</td>
<td>MRC12</td>
<td></td>
<td></td>
</tr>
<tr class="even">
<td>1</td>
<td>2</td>
<td>3</td>
<td>4</td>
<td>5</td>
<td>6</td>
<td>7</td>
<td>8</td>
<td>9</td>
<td>10</td>
<td>…</td>
<td>19</td>
<td>20</td>
<td>21</td>
</tr>
</tbody>
</table>

Positions of modules in a VME crate are fixed due the predefined
disposition of cables connected to the backplane.

Modules marked with (\*) are not present in all crates.

**Addressing and Data Modes in Muon Readout VME Crates**

All status and control registers have to be accessible via standard
A24:D16 data mode.

Short I/O data addressing mode is specifically required only for VBD
Control memory. Byte wide data access mode D08(OE) is not necessary to
implement as required my the VME standard.

The following is a list of existing data and addressing modes for [Muon
Readout Crates only]{.underline}:

**VME Buffer Driver** is a A24:D32:D16:D08(EO) master. As a master the
VBD works in DMA mode using preprogrammed information in registers
serving as pointers to buffers and word counters. In Run II the standard
addressing mode to program the DMA transfers will be used. VBD's DMA
controller supports block and non-block data transfers. As a slave VBD
has Control memory for CSRs, pointers and error codes in short I/O space
and accepts A16:D16 commands.

**Muon Fanout Card** is a A24:D16 slave. It has 8 Kbyte non-volatile
memory, for errors and configuration information. All MFC's status and
control registers are accessible via standard addressing mode with
16-bit data transfers.

**Muon Readout Card** is a A24:D32:D16 slave. It has 64K bytes of status
registers and memory. MRC's control/status registers can be accessed via
16-bit data transfers and its memory can be accessed via 16- or 32-bit
data transfers.

Readout Crate **VME processor (MVME162LX-222a)** has a default A32:D32
mode for both master and slave interfaces. Since there is no devices in
Muon Readout Crates, which provide A32 mastership, it is changed to a
standard A24 mode. A four Mbyte RAM is placed by default at Slave
addresses \$C00000-\$FFFFFF. MVME162's Master interface is configurable
and will access addresses from \$00000000 to \$00FFFFFF in the standard
address mode. Full memory maps for short I/O and standard addressing
modes are shown in these two tables respectively.

Muon Readout Crate short I/O address map.

+-----------------------+-------------+-------------------------------+
| ##### Address range   | #           | ##### Comment                 |
|                       | #### Module |                               |
+-----------------------+-------------+-------------------------------+
| \$0000-\$9FFF         | N/A         | Reserved                      |
+-----------------------+-------------+-------------------------------+
| \$A000-\$BFFF         | VBD         | Control memory 8 KB           |
+-----------------------+-------------+-------------------------------+
| \$C000-\$FFFF         | N/A         | Reserved                      |
+-----------------------+-------------+-------------------------------+

Muon Readout Crate standard address map

  ------------------------ ------------- --------------------------------
  Address range            Module        Comment

  \$000000-\$1FFFFF        N/A           Reserved

  \$200000-\$20FFFF        TFC           Status registers & memory

  \$210000-\$21FFFF        MFC           Status registers & FIFOs

  \$220000-\$22FFFF        MRC (1)       Event buffers & registers

  \$230000-\$23FFFF        MRC (2)       Event buffers & registers

  \$240000-\$24FFFF        MRC (3)       Event buffers & registers

  ...........              .......       Up to 12 MRCs

  \$300000-\$37FFFF        N/A           Reserved

  \$380000-\$3FFFFF        VBD           Buffer Memory

  \$000000-\$FFFFFF        162LX         VME Master

  \$400000-\$BFFFFF        N/A           Reserved

  \$C00000-\$FFFFFF        162LX         RAM (VME Slave)
  ------------------------ ------------- --------------------------------

**Environment for software development and routine operation**

This environment is based on D0 EPICS (Experimental Physics and
Industrial Control System) that is a set of software tools and
applications developed by EPICS collaboration and maintained at Fermilab
by Computing Division. D0 EPICS project includes VxWorks kit.

As an example of the working environment one may use a combination of
the development system deployed on one of D0 SGI (or LINUX) host
computers running under UNIX-like OS'es and executive real-time VxWorks
kernel in MVME162LX memory.

This system implements a "Host (Server) -- Target (Client-d0olmuoXX)"
model of a development and application system. UNIX gives wide
possibilities for program development and creation of a graphical user
interface as well VxWorks provides wide set of real-time solutions. The
use of two complementary and cooperating operating systems lets each do
what it does best. The development system permits to edit, compile,
link, to store real-time code for 68k CPUs, but then run and debug that
real-time code on VxWorks.

This mode of operation is possible due to the extensive use of the
network.

+-----------------------------------------------------------------------+
| **Requirements to the program**                                       |
+-----------------------------------------------------------------------+
| 1)  There are at least 16 readout VME crates in the muon system.      |
+-----------------------------------------------------------------------+
| 2)  Each one is controlled by a mvme162LX computer running the        |
|     VxWorks kernel.                                                   |
+-----------------------------------------------------------------------+
| 3)  Each one must run the same application program during the data    |
|     acquisition.                                                      |
+-----------------------------------------------------------------------+
| 4)  The differences between muon subsystems are reflected in          |
|     configuration files.                                              |
+-----------------------------------------------------------------------+
| 5)  The storage location for the configuration file is defined as a   |
|     part of the non-volatile memory of MFC residing in a given crate  |
|     and \"protected\" by a checksum.                                  |
+-----------------------------------------------------------------------+
| 6)  Each readout crate allows one telnet session for operator. The    |
|     applications may be loaded and started manually from VxWorks      |
|     shell.                                                            |
+-----------------------------------------------------------------------+
| 7)  Each readout crate is a "target" executing both broadcast and     |
|     target-specific commands of the main D0 coordinating programs.    |
+-----------------------------------------------------------------------+
| 8)  There are two ways to boot: By pushing reset button and by        |
|     operator command from console.                                    |
+-----------------------------------------------------------------------+

Detailed sequence of actions in the muon readout crate programs.

***Program* Mure_run**

**Start point.**

> Disable system interrupts on the working VME IRQ level.
>
> Check MFC NVRAM. (The function vxMemProbe( ) is used here and
> everywhere to probe the existence of memory location.)
>
> Check configuration file checksum using Motorola\'s checksum
> algorithm.
>
> Initialize Last message address Pointer to Error Record 0,
>
> Copy program configuration word PCW to MFC NVRAM.
>
> Print program header, hostname, options and computer date and time.
>
> Log to NVRAM Error Records the beginning of the start-up phase.
>
> Allocate array for L3 Crate Header aligned to four byte boundary.
>
> Initialize L3 Crate Header with default values.
>
> Prepare array mrc_Number\[ \] according to the GS Configuration word.

**Initialize and test MFC.**

> Stop the MFC embedded sequencer
>
> Do MFC software reaset.
>
> Check the presence and do W/R test of Sequencer Memory.
>
> Check the presence of MFC registers.
>
> Initialize MFC by setting the default values to all bits.
>
> Initialize SCL receiver.
>
> Set the MFC to the mode TFW (external control)[.]{.underline}

Initialize and test TFC.

(No action at the moment)

**Initialize and test MRCs.**

> Disable all MRCs (both declared and undeclared in Config file).
>
> Begin loop.
>
> Select MRC section using configuration file.
>
> Check the presence and test Dual Port RAM of the section selected.
>
> Check the presence of CSR and SCC registers.
>
> Initialize the serial Communication controller (SCC) of the section
> selected.
>
> Send \"Break\" character to Front-End Control System via SCC.
>
> Test the presence of the FE-MRC connection, set masks.
>
> Reset MRC: Reframe HOTLink.
>
> Reset SRQ, set DONE, Enable Section.
>
> Check all status bits.
>
> Loop ends when all sections of the MRCs are initialized and tested.

**Initialize and test VBD.**

> Check VBD Control memory is present.
>
> Set Enable Control memory bit in CSR.
>
> Set Crate type.
>
> Set event \# Address, Crate ID Address.
>
> Set data and word count Access Mode by writing D-Control value.
>
> Set event \# and crate ID Access mode by writing P-Control value.
>
> Set I/O Address modifier.
>
> Put list of word count pointers at 0x1000. Terminate it by 0
> terminating word.
>
> Put list of data block pointers at 0x1800.
>
> Disable control memory access.
>
> Reset the VBD by writing 1 into CSR bit 0. Wait for 200 ms. VBD is
> ready to start DMA.

**Initialize the VME interrupt system**

> Link interrupt processing subroutine itr_SRQ to VME hardware
> interrupt.
>
> Link interrupt processing subroutine itr_L2Acc to VME hardware
> interrupt.
>
> Link interrupt processing subroutine itr_VBDdone to VME hardware
> interrupt.
>
> Link interrupt processing subroutine itr_TFWinit to VME hardware
> interrupt.
>
> Set initial values to MFC\'s on-board VME Interrupt Controller.
>
> Set initial values to the Interrupt Master & Slave Controller chips.

**Prepare for main wait loop**

> If we need to store data locally then allocate 1Mbyte buffer in
> mvme162's RAM and prepare header.
>
> Send EOI to reset both interrupt controller chips, reset MFC interrupt
> input registers.
>
> Enable interrupt from TFW init signal.
>
> Wait for the first init-from-TFW interrupt, execute procedure, enable
> other three interrupts.
>
> If the Sequencer mode is selected then load and start MFC sequencer.
>
> Log to NVRAM Error Records the end of the start-up phase and start of
> data aquisition.

**Main waiting loop**

> Repeat main program loop waiting for any of four interrupts and
> checking exit condition.
>
> If there was a new itr_TFWinit then increment its counter.
>
> If the exit condition is found then exit the loop.
>
> Until exit flag in MFC NV RAM is false.
>
> Disable system interrupts on the working VME IRQ level.
>
> Analyse and print the reason of exit.
>
> If sequencer mode is on then stop sequencer.
>
> Clear all interrupts. Disable the interrupt system. Free RAM data
> buffer.
>
> Exit.

**Procedure to record errors in MFC NVRAM.**

> Increment total number of errors.
>
> Update last Error Record Pointer.
>
> Copy time stamp to Error Record.
>
> Form Error Record according to required format.
>
> Set bit in GS status register of MFC.
>
> Exit the program on fatal error.

**TFW INIT Interrupt**

> Store Xing, Turn numbers and status in MFC NV memory (see GS spec)
>
> Set to zero MFC internal L1ACC, L2ACC, L2REJ counters.
>
> Re-frame HOTLink receivers.
>
> Clear error bits in status registers.
>
> Check for front-ends to complete INIT polling MRC Busy1 bits.
>
> Insert INIT_ACK for TFW.
>
> Wait for INIT ends, then store Xing, Turn numbers and status in MFC NV
> memory.
>
> If exist report time-out and other errors to GS status register.
>
> Send EOI; return from interrupt.

**L2Acc Interrupt**

> Increment L2Acc counter.
>
> Send EOI; return from interrupt.

**SRQ Interrupt**

> Disable SRQ interrupts.
>
> Save output of FIFO5 and FIFO6 to separate locations.
>
> Get output FIFO2 and FIFO4 and compare to contents FIFO5 and FIFO6
> correspondingly.
>
> If there is no coincidence, then process the event as an error.
>
> Repeat sequential polling of all SRQ and MRC time-out bits
>
> Until all SRQs are present or a time-out bit is set instead.
>
> If there is time-out error then store patch data in the MRC dual port
> memory.
>
> If all SRQs are present check there are no errors on RVS, T-o,
> connection error.
>
> If there is an error then mark event as erroneous.
>
> Check match of FIFO5 and FIFO6 to the content of XN and TN in all MRC
> dual port memories.
>
> If there is error then report error to NVRAM.
>
> Prepare header and trailer data for L3 event.
>
> Start VBD DMA transfer by setting SLV_Ready bit.
>
> Send EOI bit, return from interrupt.

**VBD DONE interrupt**

> If we are in local mode then store data from MRC buffers to RAM
> buffer.
>
> Enable MRC \"Buffer available\" signals.
>
> Reset SLV_Ready bit.
>
> Enable SRQ interrupt.
>
> Send EOI, return from interrupt.

## Program Mure_stop

> Change the Program End Word (NVPEW) located in MFC NVRAM to stop
> mure_run program.

## Program Mure_errors

> Set working pointer to last NVRAM Error Record, input number of
> records to show.
>
> For every record print time stamp, error code, contents of FIFOs,
> counters and registers.

## Program Mure_event

> Print to screen the content of last event received from the selected
> MRC section (front-end system).

## Program Mure_mon

> Input period of time to show events and errors.
>
> Show periodically the last event received and recorded errors if they
> are present using mure_event and mure_errors subroutines.

## Program Mfc_setup

> Begin main loop.
>
> Print menu with options:
>
> 1\. Show configuration of GS VME Crate in MFC NVRAM
>
> Print current configuration.
>
> 2\. Change configuration of GS VME Crate in MFC NVRAM
>
> Input user name, password, GS ID, time update prompt. Print
> configuration.
>
> Input crate configuration word. Print changed configuration
>
> 3\. Exit
>
> Input user's selection, execute.
>
> End main loop. Exit

# L3 data format

The following table shows an allocation of data words in the arrays for
transmission to L3 processing. To be short as possible the example is
given for two data modules. All additional data modules may be inserted
between the two shown.

Guidelines to L3 data format are as follows:

-   The L3 data consist of L3 Muon Crate Header and a number of L3 Muon
    Modules.

-   L3 Muon Crate Header consists of three 32-bit words.

-   L3 Muon Module that comes from Front-end system consists in its turn
    of L3 Muon Module Header, L3 Muon front-end Data words and optional
    L3 Muon Trailer.

-   L3 Muon Module Header consists of eight 16-bit words.

-   L3 Muon front-end Data Words have the length of 16 bit.

-   L3 Muon Module Trailer is added by Front-end system in case when the
    number of module words is odd.

## L3 Muon Module Header generated by software in case of transfer errors ( Patch data)

  -------------------- ------ -------- -------------------------------------
  Item                 Size   Value    Comments

  Zero word            16     0x0000   According to Muon Data Formats to L2
                       bits            & L3

  VBD Word Count       16     0x0004   According to Muon Data Formats to L2
                       bits            & L3

  Front-end word Count 16     0x0006   According to Muon Data Formats to L2
                       bits            & L3

  Module ID            16     0x03ff   Non-existing Layer, Barrel, Octant
                       bits            (maximum values)

  Crossing Number      16     0x0000   Default value
                       bits            

  Turn Number          16     0x0000   Default value
                       bits            

  Event Status         16     0x0200   Bit 9 is used to indicate patch data
  Register (upper)     bits            

  Event Status         16     0x0000   Default value
  Register (lower)     bits            
  -------------------- ------ -------- -------------------------------------

+-----------+-----------+----+------+---------------------------------+
| Group     | Item      | Si | R    | Description                     |
| Item      |           | ze | ange |                                 |
|           |           | (b |      |                                 |
|           |           | it |      |                                 |
|           |           | s) |      |                                 |
+-----------+-----------+----+------+---------------------------------+
| L3 Muon   | Crate     | 32 | 2    | Length of the muon crate header |
| Crate     | Header    |    |      | in 32 bit words                 |
| Header    | Word      |    |      |                                 |
|           | Count     |    |      |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Crate     | 32 | 0..( | Bits 00-15 Error/Status         |
|           | ID/Status |    | 2^32 |                                 |
|           |           |    | ^-1) | Bits 16-31 Crate ID             |
+-----------+-----------+----+------+---------------------------------+
|           | Number of | 32 | 0    | Number of Muon modules read     |
|           | modules   |    | ..24 |                                 |
|           | read      |    |      |                                 |
+-----------+-----------+----+------+---------------------------------+
| L3 Muon   | Zero word | 16 | 0    | Upper 16 bits of the 32 bit VBD |
| Module    |           |    |      | word count. Always is equal to  |
| Header    |           |    |      | 0 to exclude counts \>          |
|           |           |    |      | (2^16^-1)                       |
+-----------+-----------+----+------+---------------------------------+
|           | VBD Word  | 16 | 0..  | Exclusive total word count to   |
|           | Count     | or | (    | end of module array. If it is   |
|           |           |    | 2^16 | odd, then Padding word is       |
|           |           | 32 | ^-1) | added.                          |
+-----------+-----------+----+------+---------------------------------+
|           | Front-end | 16 | 0..  | Inclusive number of 16-bit      |
|           | Word      |    | (    | words in data block             |
|           | Count     |    | 2^16 |                                 |
|           |           |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Module ID | 16 | 0..( | Defines Layer, Barrel, Octant,  |
|           |           |    | 2^16 | Detector type.                  |
|           |           |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Crossing  | 16 | 0..  | Error bit is set for the TFW if |
|           | Number    |    | (2^8 | the local crossing number       |
|           |           |    | ^-1) | differs from the L1 event       |
|           |           |    |      | crossing number                 |
+-----------+-----------+----+------+---------------------------------+
|           | Turn      | 16 | 0..  | Local Turn number from          |
|           | Number    |    | (    | front-end system                |
|           |           |    | 2^16 |                                 |
|           |           |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Event     | 16 | 0..  | Defined in document on L2 & L3  |
|           | Status    |    | (    | Muon Data formats               |
|           | Register  |    | 2^16 |                                 |
|           | (upper)   |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Event     | 16 | 0..  | Defined in document on L2 & L3  |
|           | Status    |    | (    | Muon data formats               |
|           | Register  |    | 2^16 |                                 |
|           | (lower)   |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
| L2 Muon   | Data      | 16 | 0..  | First Muon front-end subsystem  |
| Data      |           |    | (    | Data Word                       |
|           |           |    | 2^16 |                                 |
|           |           |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Data      |    |      | Muon front-end subsystem Data   |
|           |           |    |      | Words                           |
|           | ......    |    |      |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Data      | 16 | 0..  | Last Muon front-end subsystem   |
|           |           |    | (    | Data Word                       |
|           |           |    | 2^16 |                                 |
|           |           |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
| L3 Muon   | Padding   | 16 | 0x   | Is added only when Front-end    |
| Trailer   | word      |    | AA55 | Word Count is odd               |
+-----------+-----------+----+------+---------------------------------+
| L3 Muon   | Zero word | 16 | 0    | Upper 16 bits of the 32 bit VBD |
| Module    |           |    |      | word count. Always is equal to  |
| Header    |           |    |      | 0 to exclude counts \>          |
|           |           |    |      | (2^16^-1)                       |
+-----------+-----------+----+------+---------------------------------+
|           | VBD Word  | 16 | 0..  | Exclusive total word count to   |
|           | Count     | or | (    | end of module array. If it is   |
|           |           |    | 2^16 | odd, then Padding word is       |
|           |           | 32 | ^-1) | added.                          |
+-----------+-----------+----+------+---------------------------------+
|           | Front-end | 16 | 0..  | Inclusive number of 16-bit      |
|           | Word      |    | (    | words in data block             |
|           | Count     |    | 2^16 |                                 |
|           |           |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Module ID | 16 | 0(2^ | Defines Layer, Barrel, Octant,  |
|           |           |    | 16^- | Detector type.                  |
|           |           |    | 1).. |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Crossing  | 16 | 0..  | Error bit is set for the TFW if |
|           | Number    |    | (2^8 | the local crossing number       |
|           |           |    | ^-1) | differs from the L1 event       |
|           |           |    |      | crossing number                 |
+-----------+-----------+----+------+---------------------------------+
|           | Turn      | 16 | 0..  | Local Turn number from          |
|           | Number    |    | (    | front-end system                |
|           |           |    | 2^16 |                                 |
|           |           |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Event     | 16 | 0..  | Defined in document on L2 & L3  |
|           | Status    |    | (    | Muon Data formats               |
|           | Register  |    | 2^16 |                                 |
|           | (upper)   |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Event     | 16 | 0..  | Defined in document on L2 & L3  |
|           | Status    |    | (    | Muon data formats               |
|           | Register  |    | 2^16 |                                 |
|           | (lower)   |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
| L3 Muon   | Data      | 16 | 0..  | First Muon front-end subsystem  |
| Data      |           |    | (    | Data Word                       |
|           |           |    | 2^16 |                                 |
|           |           |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Data      |    |      | Muon front-end subsystem Data   |
|           |           |    |      | Words                           |
|           | ......    |    |      |                                 |
+-----------+-----------+----+------+---------------------------------+
|           | Data      | 16 | 0..  | Last Muon front-end subsystem   |
|           |           |    | (    | Data Word                       |
|           |           |    | 2^16 |                                 |
|           |           |    | ^-1) |                                 |
+-----------+-----------+----+------+---------------------------------+
| L3 Muon   | Padding   | 16 | 0x   | Is added only when Front-end    |
| Trailer   | word      |    | AA55 | Word Count is odd               |
+-----------+-----------+----+------+---------------------------------+

##  VBD memory map and registers. 

Short VME Addressing (A16:D16) Base Address is 0xFFFFA000

  ----- --------- ------- ------------------------------------ --------------
  \##   Hex       Size    Memory block or register             Write/read
        address                                                

  1     0000              CSR0                                 

  2     0002              CSR1                                 

  3     0004              CSR2                                 

  4     0006              CSR3                                 

  5     0008              Crate Type                           

  6     000A              Event Number                         

  7     000C              Crate ID                             

  8     0010              D-Control                            

  9     0012              P-Control                            

  10    0014              I/O Address                          

  11    0100              ERRCNT                               

  12    0104              ERRORLIST                            

  13    1000              WCPOINTERs list terminated by 0      

  14    1800              DATAPOINTERs list                    
  ----- --------- ------- ------------------------------------ --------------

VME Addressing (A24:D32) VBD base address is 0xF0380000

  ----- ---------- ------- ------------------------------------ --------------
  \##   Hex        Size    Memory block or register             Write/read
        address                                                 

  15    F0380000   256 Kb  Memory Buffer 0                      W/R

  16    F03C0000   256 Kb  Memory Buffer 1                      W/R
  ----- ---------- ------- ------------------------------------ --------------

## Allocation of bits in VBD's CSR0

0xFFFFA000 - CSR0

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| Reset | Reset  | Di    | D      | Tim   | Ti     | Sele  | DMAGO  |
| VBD   | Error  | sable | isable | e-out | me-out | ctDMA |        |
|       | FIFO   | tra   | write  |       |        | B     |        |
|       |        | nsmit | to     | Upper | Lower  | uffer |        |
|       |        | VBD   | c      | Bit   | Bit    | (0/1) |        |
|       |        | b     | ontrol |       |        |       |        |
|       |        | uffer | memory |       |        |       |        |
|       |        | after |        |       |        |       |        |
|       |        | DMA   |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| Error | Re     | Res   | Re     | Res   | Re     | Res   | Re     |
| on    | served | erved | served | erved | served | erved | served |
|       |        |       |        |       |        |       |        |
| CSR   |        |       |        |       |        |       |        |
| write |        |       |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+

## Allocation of bits in VBD's CSR2

0xFFFFA004 - CSR0

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| Res   | Re     | Res   | Re     | DMA   | DMA    | B     | Buffer |
| erved | served | erved | served |       |        | uffer | 0      |
|       |        |       |        | in    | in     | 1     |        |
|       |        |       |        | pro   | pr     |       | Status |
|       |        |       |        | gress | ogress | S     |        |
|       |        |       |        |       |        | tatus | 0 --   |
|       |        |       |        | B     | Buffer |       | VME,   |
|       |        |       |        | uffer | 0      | 0 --  |        |
|       |        |       |        | 1     |        | VME,  | 1-Ex   |
|       |        |       |        |       |        |       | t.Port |
|       |        |       |        |       |        | 1-Ext |        |
|       |        |       |        |       |        | .Port |        |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| DMA   | Re     | Token | Re     | Res   | Re     | Res   | Re     |
| Error | ad-out | Error | served | erved | served | erved | served |
|       | error  |       |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+

## TFC memory map and allocation of bits in registers

VME Addressing (A24:D16), TFC base address is 0xF0200000

  ----- --------- ------- ------------------------------------------ ------------
  \##   Hex       Size    Memory block or register                   Write/read
        address                                                      

  1     0000      16 Kb   Dual Port Pattern Memory                   

  2     4000      2       TFC control register, CSR0                 

  3     4002      2       TFC status/control register, CSR1          

  4     4022      2       TFC HOTLink control register, CSR2         

  5     4024      2       TFC Fine & Coarse FC synchronization       
                          preset register, CSR3                      

  6     4028      2       TFC Channel mask and L2 delay register,    
                          CSR4                                       

  7     402A      2       Crossing number and trigger delay          
                          register, CSR5                             
  ----- --------- ------- ------------------------------------------ ------------

0xF0204000 - CSR0 Control register

<table style="width:100%;">
<colgroup>
<col style="width: 5%" />
<col style="width: 5%" />
<col style="width: 5%" />
<col style="width: 5%" />
<col style="width: 8%" />
<col style="width: 7%" />
<col style="width: 8%" />
<col style="width: 7%" />
<col style="width: 5%" />
<col style="width: 5%" />
<col style="width: 5%" />
<col style="width: 6%" />
<col style="width: 7%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
</colgroup>
<tbody>
<tr class="odd">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>09</td>
<td>08</td>
<td>07</td>
<td>06</td>
<td>05</td>
<td>04</td>
<td>03</td>
<td>02</td>
<td>01</td>
<td>00</td>
</tr>
<tr class="even">
<td>NC</td>
<td>NC</td>
<td>NC</td>
<td>NC</td>
<td><p>SINGL</p>
<p>TRIG</p>
<p>MODE</p></td>
<td><p>EXT</p>
<p>TRIG</p>
<p>ENB</p></td>
<td><p>EXT</p>
<p>TRIG</p>
<p>MODE</p></td>
<td><p>SEQ/</p>
<p>TFW</p>
<p>SEL</p></td>
<td>NC</td>
<td>NC</td>
<td>NC</td>
<td><p>TFC</p>
<p>BRD</p>
<p>RES</p></td>
<td><p>CLR</p>
<p>TRIG</p>
<p>CNTR</p></td>
<td><p>DO</p>
<p>SYN</p>
<p>SEQ</p></td>
<td><p>CLR</p>
<p>TRG</p>
<p>LAT</p></td>
<td><p>SET</p>
<p>FE</p>
<p>INIT</p></td>
</tr>
</tbody>
</table>

0xF0204002 -- CSR1 status/control register

<table>
<colgroup>
<col style="width: 4%" />
<col style="width: 4%" />
<col style="width: 7%" />
<col style="width: 6%" />
<col style="width: 7%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 7%" />
<col style="width: 4%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 7%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 5%" />
</colgroup>
<tbody>
<tr class="odd">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>09</td>
<td>08</td>
<td>07</td>
<td>06</td>
<td>05</td>
<td>04</td>
<td>03</td>
<td>02</td>
<td>01</td>
<td>00</td>
</tr>
<tr class="even">
<td>NC</td>
<td>NC</td>
<td><p>L2</p>
<p>BUSY</p></td>
<td><p>L2</p>
<p>ERR</p></td>
<td><p>L1</p>
<p>BUSY</p></td>
<td><p>L1</p>
<p>ERR</p></td>
<td><p>INIT</p>
<p>ACK</p></td>
<td><p>SCL</p>
<p>ACK</p></td>
<td><p>TFC</p>
<p>BUSY</p></td>
<td>NC</td>
<td><p>TFC</p>
<p>ERR</p></td>
<td><p>SCL</p>
<p>SL</p></td>
<td><p>SCL</p>
<p>DATA</p>
<p>ERR</p></td>
<td><p>SCL</p>
<p>SYN</p>
<p>ERR</p></td>
<td><p>SCL</p>
<p>RDY</p></td>
<td><p>SCL</p>
<p>INIT</p></td>
</tr>
</tbody>
</table>

0xF0204022 -- CSR2 HOTLink control register

  ----- ---- ----- ----- ----- ----- ----- ----- ----- ---- ---- ---- ---- ----- ----- ----- -----
  15    14         13    12    11    10    09    08    07   06   05   04   03    02    01    00

  TD7        TD6   TD5   TD4   TD3   TD2   TD1   TD0   NC   NC   NC   NC   TST   SVS   BSE   TEN
  ----- ---- ----- ----- ----- ----- ----- ----- ----- ---- ---- ---- ---- ----- ----- ----- -----

TD7..TD0 -Test pattern, TST -Test en., SVS -- Send violation symbol, BSE
-- BIST en., TEN -- Transmit en.

0xF0204024 -- CSR3 Fine & Coarse FC synchro preset register

  ----- ----- ----- ----- ----- ----- ----- ----- ---- ---- ---- ---- ---- ----- ----- -----
  15    14    13    12    11    10    09    08    07   06   05   04   03   02    01    00

  FC7   FC6   FC5   FC4   FC3   FC2   FC1   FC0   NC   NC   NC   NC   NC   FF2   FF1   FF0
  ----- ----- ----- ----- ----- ----- ----- ----- ---- ---- ---- ---- ---- ----- ----- -----

FC7..FC0 - First crossing coarse counter preset (18.9 ns step), FF2..FF0
-- First crossing fine delay preset

0xF0204028 -- CSR4 Channel mask and L2 pipeline delay register

  ----- ----- ----- ----- ---- ---- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
  15    14    13    12    11   10   09    08    07    06    05    04    03    02    01    00

  CH4   CH3   CH2   CH1   NC   NC   PD9   PD8   PD7   PD6   PD5   PD4   PD3   PD2   PD1   PD0
  ----- ----- ----- ----- ---- ---- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----

CH1..4 - Channel enable, PD9..PD0 - L2 decision delay preset (1..1023,
132 ns step)

0xF020402A -- CSR5 Crossing number and trigger delay register

  ---- ---- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
  15   14   13    12    11    10    09    08    07    06    05    04    03    02    01    00

  NC   NC   LD5   LD4   LD3   LD2   LD1   LD0   CR7   CR6   CR5   CR4   CR3   CR2   CR1   CR0
  ---- ---- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----

LD5..LD0 -- Extrn. trigger delay (20..63, 132 ns step), CR5..CR0 -
Extrn. trigger crossing \# preset (1..159)

Pattern memory data format (Pointer XN, Pointer TN, Event XN, Event TN,
Terminator Word)

  ----- ----- ----- ----- ------ ----- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
  15    14    13    12    11     10    09   08   07   06   05   04   03   02   01   00

  0     0     0     0     0      0     0    0    X7   X6   X5   X4   X3   X2   X1   X0

  T15   T14   T13   T12   T11    T10   T9   T8   T7   T6   T5   T4   T3   T2   T1   T0

  1     L2R   L2A   L1A   0      0     0    0    X7   X6   X5   X4   X3   X2   X1   X0

  T15   T14   T13   T12   T11    T10   T9   T8   T7   T6   T5   T4   T3   T2   T1   T0

  0     0     0     0     TM=1   0     0    0    0    0    0    0    0    0    0    0
  ----- ----- ----- ----- ------ ----- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----

##  MFC memory map, registers and bits.

MFC base address is 0xF0210000

+---+---------+----+---------------------------------------+----------+
| \ | Hex     | Si | Memory block or register              | Wr       |
| # | address | ze |                                       | ite/read |
| # |         |    |                                       |          |
+---+---------+----+---------------------------------------+----------+
| 1 | 000     | 16 | Sequencer Dual Port Memory            | W/R      |
|   | 0..3FFF | KB |                                       |          |
+---+---------+----+---------------------------------------+----------+
| 2 | 400     | 8  | Error Records and Timekeeping Memory  | W/R      |
|   | 0..5FFF | KB |                                       |          |
|   |         |    | Error record 01                       |          |
|   | 4000    | 2  |                                       |          |
|   |         | 56 | Error record 02                       |          |
|   | 4100    |    |                                       |          |
|   |         | 2  | Error record 03                       |          |
|   | 4200    | 56 |                                       |          |
|   |         |    | Error record 04                       |          |
|   | 4300    | 2  |                                       |          |
|   |         | 56 | Error record 05                       |          |
|   | 4400    |    |                                       |          |
|   |         | 2  | Error record 06                       |          |
|   | 4500    | 56 |                                       |          |
|   |         |    | Error record 07                       |          |
|   | 4600    | 2  |                                       |          |
|   |         | 56 | Error record 08                       |          |
|   | 4700    |    |                                       |          |
|   |         | 2  | Error record 09                       |          |
|   | 4800    | 56 |                                       |          |
|   |         |    | Error record 10                       |          |
|   | 4900    | 2  |                                       |          |
|   |         | 56 | Error record 11                       |          |
|   | 4A00    |    |                                       |          |
|   |         | 2  | Error record 12                       |          |
|   | 4B00    | 56 |                                       |          |
|   |         |    | Error record 13                       |          |
|   | 4C00    | 2  |                                       |          |
|   |         | 56 | Error record 14                       |          |
|   | 4D00    |    |                                       |          |
|   |         | 2  | Error record 15                       |          |
|   | 4E00    | 56 |                                       |          |
|   |         |    | Error record 16                       |          |
|   | 4F00    | 2  |                                       |          |
|   |         | 56 | Last Message Address Pointer          |          |
|   | 5000    |    |                                       |          |
|   |         | 2  | Reserved                              |          |
|   | 5002    | 56 |                                       |          |
|   |         |    | GS ID                                 |          |
|   | 50D0    | 2  |                                       |          |
|   |         | 56 | GS Status                             |          |
|   | 50D2    |    |                                       |          |
|   |         | 2  | GS Mailbox area                       |          |
|   | 50D4    | 56 |                                       |          |
|   |         |    | GS Configuration file                 |          |
|   | 5100    | 2  |                                       |          |
|   |         | 56 | User defined NVRAM area               |          |
|   | 5120    |    |                                       |          |
|   |         | 2  | Reserved                              |          |
|   | 5F00    | 56 |                                       |          |
|   |         |    | DS1643 Control ( W+R bits)            |          |
|   | 5FF8    | 2  |                                       |          |
|   |         |    | Seconds + OSC                         |          |
|   | 5FF9    | 2  |                                       |          |
|   |         | 06 | Minutes                               |          |
|   | 5FFA    |    |                                       |          |
|   |         | 2  | Hour                                  |          |
|   | 5FFB    |    |                                       |          |
|   |         | 2  | Day of week + FT                      |          |
|   | 5FFC    |    |                                       |          |
|   |         | 44 | Date                                  |          |
|   | 5FFD    |    |                                       |          |
|   |         | 32 | Month                                 |          |
|   | 5FFE    |    |                                       |          |
|   |         | 35 | Year                                  |          |
|   | 5FFF    | 62 |                                       |          |
|   |         |    |                                       |          |
|   |         | 2  |                                       |          |
|   |         | 48 |                                       |          |
|   |         |    |                                       |          |
|   |         | 1  |                                       |          |
|   |         |    |                                       |          |
|   |         | 1  |                                       |          |
|   |         |    |                                       |          |
|   |         | 1  |                                       |          |
|   |         |    |                                       |          |
|   |         | 1  |                                       |          |
|   |         |    |                                       |          |
|   |         | 1  |                                       |          |
|   |         |    |                                       |          |
|   |         | 1  |                                       |          |
|   |         |    |                                       |          |
|   |         | 1  |                                       |          |
|   |         |    |                                       |          |
|   |         | 1  |                                       |          |
+---+---------+----+---------------------------------------+----------+
| 3 | 600     | 4  | FIFO Controller and Memory, Trigger   | W/R      |
|   | 0..6FFF | KB | Data Counters                         |          |
|   |         |    |                                       | W/R      |
|   | 6000    | 2  | L1ACC_XN (FIFO 1) push from TFW when  |          |
|   |         |    | L1ACC                                 | W/R      |
|   | 6002    | 2  |                                       |          |
|   |         |    | L2SIM_XN (FIFO 2) push from FIFO1     | W/R      |
|   | 6004    | 2  | when L2ACC                            |          |
|   |         |    |                                       | W/R      |
|   | 6006    | 2  | L1ACC_TN (FIFO 3) push from TFW when  |          |
|   |         |    | L1ACC                                 | W/R      |
|   | 6008    | 2  |                                       |          |
|   |         |    | L2SIM_TN (FIFO 4) push from FIFO3     | W/R      |
|   | 600A    | 2  | when L2ACC                            |          |
|   |         |    |                                       | W/R      |
|   | 600C    | 2  | L2DIR_XN (FIFO 5) push from TFW when  |          |
|   |         |    | L2ACC                                 | W/R      |
|   | 600E    | 2  |                                       |          |
|   |         |    | L2DIR_TN (FIFO 6) push from TFW when  | W/R      |
|   | 6010    | 2  | L2ACC                                 |          |
|   |         |    |                                       | W/R      |
|   | 6012    | 2  | L2DIR_AQ (FIFO 7) push from TFW when  |          |
|   |         |    | L2ACC                                 | W/R      |
|   | 6014    | 2  |                                       |          |
|   |         |    | (this is L3 TRANFER NUMBER)           | W/R      |
|   | 6016    | 2  |                                       |          |
|   |         |    | TFW_XN (FIFO 8) push from TFW when    | W/R      |
|   | 6018    | 2  | L1ACC,                                |          |
|   |         |    |                                       | R        |
|   | 601A    | 2  | L2ACC or L2REJ                        |          |
|   |         |    |                                       | R        |
|   | 601C    | 2  | L1ACC Counter at the time of an error |          |
|   |         |    |                                       | W        |
|   | 601E    | 2  | L2ACC Counter at the time of an error |          |
|   |         |    |                                       | W        |
|   | 6020    | 2  | L2REJ Counter at the time of an error |          |
|   |         |    |                                       | W        |
|   | 6022    | 2  | L1ACC Counter (total number)          |          |
|   |         |    |                                       | W        |
|   | 6024    | 2  | L2ACC Counter (total number)          |          |
|   |         |    |                                       | W        |
|   | 6026    | 2  | L2REJ Counter (total number)          |          |
|   |         |    |                                       | W        |
|   | 6028    | 2  | FIFO Status 1                         |          |
|   |         |    |                                       | W        |
|   | 602A    | 2  | FIFO Status 2                         |          |
|   |         |    |                                       | W        |
|   | 602C    | 2  | FIFO 1 Threshold (bits 0 - 4 are      |          |
|   |         |    | used)                                 |          |
|   | 602E    | 2  |                                       |          |
|   |         |    | FIFO 2 Threshold (bits 0 - 4 are      |          |
|   |         |    | used)                                 |          |
|   |         |    |                                       |          |
|   |         |    | FIFO 3 Threshold (bits 0 - 4 are      |          |
|   |         |    | used)                                 |          |
|   |         |    |                                       |          |
|   |         |    | FIFO 4 Threshold (bits 0 - 4 are      |          |
|   |         |    | used)                                 |          |
|   |         |    |                                       |          |
|   |         |    | FIFO 5 Threshold (bits 0 - 4 are      |          |
|   |         |    | used)                                 |          |
|   |         |    |                                       |          |
|   |         |    | FIFO 6 Threshold (bits 0 - 4 are      |          |
|   |         |    | used)                                 |          |
|   |         |    |                                       |          |
|   |         |    | FIFO 7 Threshold (bits 0 - 4 are      |          |
|   |         |    | used)                                 |          |
|   |         |    |                                       |          |
|   |         |    | FIFO 8 Threshold (bits 0 - 4 are      |          |
|   |         |    | used)                                 |          |
+---+---------+----+---------------------------------------+----------+
| 4 | 700     | 4  | Reserved                              |          |
|   | 0..7FFF | KB |                                       |          |
+---+---------+----+---------------------------------------+----------+
| 5 | 800     | 4  | Interrupt Chip 1 (Master) CA82C59A    | W        |
|   | 0..8FFF | KB |                                       |          |
|   |         |    | ICW1 ( 0x11 )                         | W        |
|   | 8000    |    |                                       |          |
|   |         |    | ICW2 ( 0x50 ) For Interrupt Number 50 | W        |
|   | 8002    |    |                                       |          |
|   |         |    | ICW3 ( 0x80 ) Slave is connected to   | W        |
|   | 8002    |    | Masters input IRQ7                    |          |
|   |         |    |                                       | W/R      |
|   | 8002    |    | ICW4 ( 0x11 )                         |          |
|   |         |    |                                       | W/R      |
|   | 8002    |    | OCW1 ( 0x00 ) Interrupts Mask for     |          |
|   |         |    | Master (1 - DisableIntr)              | W/R      |
|   | 8000    |    |                                       |          |
|   |         |    | OCW2 ( 0x27 )                         |          |
|   | 8000    |    |                                       |          |
|   |         |    | OCW3 ( 0x08 )                         |          |
+---+---------+----+---------------------------------------+----------+
| 6 | 900     | 4  | Interrupt Chip 2 (Slave) CA82C59A     | W        |
|   | 0..9FFF | KB |                                       |          |
|   |         |    | ICW1 ( 0x11 )                         | W        |
|   | 9000    |    |                                       |          |
|   |         |    | ICW2 ( 0x58 ) For Interrupt Number 58 | W        |
|   | 9002    |    |                                       |          |
|   |         |    | ICW3 ( 0x07 ) Slave\'s Number is 7    | W        |
|   | 9002    |    |                                       |          |
|   |         |    | ICW4 ( 0x01 )                         | W/R      |
|   | 9002    |    |                                       |          |
|   |         |    | OCW1 ( 0x00 ) Interrupts Mask for     | W/R      |
|   | 9002    |    | Slave (1 - DisableIntr)               |          |
|   |         |    |                                       | W/R      |
|   | 9000    |    | OCW2 ( 0x27 )                         |          |
|   |         |    |                                       |          |
|   | 9000    |    | OCW3 ( 0x08 )                         |          |
+---+---------+----+---------------------------------------+----------+
| 7 | A00     | 4  | VME Interrupt Controller              | R        |
|   | 0..AFFF | KB |                                       |          |
|   |         |    | Output Interrupt Register             | W/R      |
|   | A000    |    |                                       |          |
|   |         |    | Mode Register ( 0 - Level Triggered,  | R        |
|   | A002    |    | 1 - Edge Triggered)                   |          |
|   |         |    |                                       | W/R      |
|   | A004    |    | Input Interrupt Register              |          |
|   |         |    |                                       | W        |
|   | A006    |    | Edge Selector ( 0 - Rising Edge, 1 -- |          |
|   |         |    | Falling Edge)                         |          |
|   | A004    |    |                                       |          |
|   |         |    | Selective Reset Internal Interrupt    |          |
|   |         |    | Flip-flops ( 1 - Reset)               |          |
+---+---------+----+---------------------------------------+----------+
| 8 | B00     | 4  | Reserved                              |          |
|   | 0..BFFF | KB |                                       |          |
+---+---------+----+---------------------------------------+----------+
| 9 | C00     | 4  | Control, Status & ID Registers        | W/R      |
|   | 0..CFFF | KB |                                       |          |
|   |         |    | MFC Control Register                  | W/R      |
|   | C000    |    |                                       |          |
|   |         |    | HOTLIink Control and Status Register  | R        |
|   | C002    |    |                                       |          |
|   |         |    | Error Register 1                      | R        |
|   | C004    |    |                                       |          |
|   |         |    | Error Register 2                      | R        |
|   | C006    |    |                                       |          |
|   |         |    | MFC Status Register                   | R        |
|   | C008    |    |                                       |          |
|   |         |    | INIT_XN (latched on both rising and   | R        |
|   | C00A    |    | falling edge of INIT)                 |          |
|   |         |    |                                       | R        |
|   | C00C    |    | INIT_TN (latched on both rising and   |          |
|   |         |    | falling edge of INIT)                 |          |
|   | C00E    |    |                                       |          |
|   |         |    | Card ID (bits 15-08) & Serial Number  |          |
|   |         |    | (bits 07-00)                          |          |
+---+---------+----+---------------------------------------+----------+
| 1 | D00     | 4  | Sequencer Controller                  | W/R      |
| 0 | 0..DFFF | KB |                                       |          |
|   |         |    | LW Data Register                      | W/R      |
|   | D004    | 2  |                                       |          |
|   |         |    | HW Data Register                      | W/R      |
|   | D006    | 2  |                                       |          |
|   |         |    | Number Of Words & Control Register    | W/R      |
|   | D008    | 2  | (NOW)                                 |          |
|   |         |    |                                       |          |
|   | D00A    | 2  | Sequencer Address Register            |          |
+---+---------+----+---------------------------------------+----------+
| 1 | E00     | 4  | Error Memory Controller               | R        |
| 1 | 0..EFFF | KB |                                       |          |
|   |         |    | L1&L2_TN Error register               | R        |
|   | E002    | 2  |                                       |          |
|   |         |    | L1&L2_XN Error register               | R        |
|   | E004    | 2  |                                       |          |
|   |         |    | L1&L2_AQ Error register               | R        |
|   | E006    | 2  |                                       |          |
|   |         |    | L1&L2_STAT Error register             | W/R      |
|   | E008    | 2  |                                       |          |
|   |         |    | Data register                         |          |
|   | E00A    | 2  |                                       |          |
+---+---------+----+---------------------------------------+----------+
| 1 | F00     | 4  | Reserved                              |          |
| 2 | 0..FFFF | KB |                                       |          |
+---+---------+----+---------------------------------------+----------+

## Error records in MFC NVRAM

There are three types of errors recorded in the NVRAM Error Records.

[FA:]{.underline} Fatal errors are found during initialization time. The
first error found aborts the execution of the program. The format
includes Time of event (00..07), Error Word (08..09), Empty space
(0A..FF).

[DA:]{.underline} Synchronization errors are found during data
acquisition. The format is as shown in the table with all items filled.

[TF:]{.underline} Errors during TFW initialization are found. Format is
the same as for FA type records.

## 

##  Format of Error records in MFC NV RAM.

  ---------------- ---------------------------------------- --------------
  Hex address      Item                                     Size (bytes)

  00               Time of event in order of DS1643         8

  08               Error Code                               2

  0A               L1ACC Counter                            2

  0C               L2ACC Counter                            2

  0E               L2REJ Counter                            2

  10               L2ACC_TN_LAST                            2

  12               L2ACC_XN_LAST                            2

  14               L2DIR_TN                                 2

  16               L2DIR_XN                                 2

  18               MFC Status Register                      2

  1A               MFC HOTLink CSR                          2

  1C               MFC Error Register 1                     2

  1E               MFC Error Register 2                     2

  20               MRC1A CSRlo Status Register              2

  22               MRC1A XN                                 2

  24               MRC1A TN                                 2

  26               MRC1B CSRlo Status Register              2

  28               MRC1B XN                                 2

  2A               MRC1B TN                                 2

  2C               MRC2A CSRlo Status Register              2

  2E               MRC2A XN                                 2

  30               MRC2A TN                                 2

  ....             ..........                               ....

  9C               MRC22B CSRlo Status Register             2

  9E               MRC22B XN                                2

  A0               MRC22B TN                                2

  A2               MRC23A CSRlo Status Register             2

  A4               MRC23A XN                                2

  A6               MRC23A TN                                2

  A8               MRC23B CSRlo Status Register             2

  AC               MRC23B XN                                2

  AE               MRC23B TN                                2

  B0..FB           Reserved                                 

  FC               Total Number of Errors (Upper part)      2

  FE               Total Number of Errors (Lower part)      2
  ---------------- ---------------------------------------- --------------

**Configuration file format**

The configuration file and operations with it must satisfy the following
rules.

1.  The configuration file is the single place where information on
    difference between crates is stored.

2.  Each Muon Readout Crate must have its fixed configuration because of
    fixed positions of cables connected to backplane in every crate. The
    configuration word is used to inform the program which MRC sections
    are used. It is not intended to be used to change the configuration
    during the Run.

3.  Positions of modules in VME crate slots are fixed.

  ---------------- ------------------ -------------------------------------
  Module           Station Number     Comment

  mvme162LX        1                  

  VBD              2                  

  VBD Bus          3                  Optional. There is one for the VBD
  Terminator                          External Bus

  TFC              4                  Optional. Used for Local Mode.

  MFC              7                  

  MRC              8                  First MRC in the crate. Lowest memory
                                      region

  MRC              9                  Second MRC in the crate. Next to up
                                      memory region

  ......                              Other MRCs in the crate.

  MRC              8+(NumberOfMRCs)   Last MRC in the crate. Upper memory
                                      region

  Must be empty    20                 

  Must be empty    21                 
  ---------------- ------------------ -------------------------------------

4.  The number of MRCs depends on type of subsystem and may be 12
    maximum.

5.  Any access for modification or reading of the configuration files is
    performed by one special subroutine, that considers the
    configuration file as an encapsulated object with predefined
    operations on it.

6.  There must be modal dialog between operator and a configuration
    program to set up configuration.

7.  There must be time, date and name of operator in the configuration
    file.

8.  There must be a general configuration file on some D0 server. This
    file must contain all configuration files for existing muon readout
    crates.

9.  The configuration file for a given crate must be stored in the
    MFC\'s nonvolatile RAM at the starting address Base+5100.

10. The configuration file has the length of 32 bytes and contains Time
    and Date of this file creation, operators name, 32-bit configuration
    word, reserved zone filled with zeros and file checksum.

11. Bit positions of the configuration word are shown in the following.

1^st^ (lower) byte of the configuration word

  --------- ------- ------- ------- ------- ------- ------- ------- -------
  Bits      7       6       5       4       3       2       1       0

  Station   7       6       5       4       3       2       1       N/A
  \#                                                                

  Value     MFC     0       0       TFC     TERM    VBD     162LX   0
  --------- ------- ------- ------- ------- ------- ------- ------- -------

2^nd^ byte of the configuration word

  --------- ------- ------- ------- ------- ------- ------- ------- -------
  Bit       15      14      13      12      11      10      9       8

  Station   11      11      10      10      9       9       8       8
  \#                                                                

  Value     MRC4B   MRC4A   MRC3B   MRC3A   MRC2B   MRC2A   MRC1B   MRC1A
  --------- ------- ------- ------- ------- ------- ------- ------- -------

3^rd^ byte of the configuration word

  --------- ------- ------- ------- ------- ------- ------- ------- -------
  Bit       23      22      21      20      19      18      17      16

  Station   15      15      14      14      13      13      12      12
  \#                                                                

  Value     MRC8B   MRC8A   MRC7B   MRC7A   MRC6B   MRC6A   MRC5B   MRC5A
  --------- ------- ------- ------- ------- ------- ------- ------- -------

4^th^ (upper) byte of the configuration word

  --------- -------- -------- -------- -------- -------- -------- ------- -------
  Bit       31       30       29       28       27       26       25      24

  Station   19       19       18       18       17       17       16      16
  \#                                                                      

  Value     MRC12B   MRC12A   MRC11B   MRC11A   MRC10B   MRC10A   MRC9B   MRC9A
  --------- -------- -------- -------- -------- -------- -------- ------- -------

The value of a given bit is 1 if the module is inserted into crate
station or a section of a MRC is used, otherwise the value is 0.

## GS configuration file.

  -------- ----------------- ------------- --------- ----------------- --------------
  **\#**   **Group Item**    **Item**      **Size    **Range**         **Encoding**
                                           (bit)**                     

  1        Time & Date of    0             8         0                 BCD
           entry                                                       

  2                          Seconds       8         0..59             BCD

  3                          Minute        8         1..59             BCD

  4                          Hour          8         0..23             BCD

  5                          Day of week   8         1..7 (Sunday=1)   BCD

  6                          Date          8         0..31             BCD

  7                          Month         8         0..12             BCD

  8                          Year          8         0..99             BCD

  9        Operators Name    Letter 1      8         A..z              ASCII

  10                         Letter 2      8         A..z              ASCII

  11                         Letter 3      8         A..z              ASCII

  12                         Letter 4      8         A..z              ASCII

  13                         Letter 5      8         A..z              ASCII

  14                         Letter 6      8         A..z              ASCII

  15                         Letter 7      8         A..z              ASCII

  16                         Letter 8      8         A..z              ASCII

  17       Configuration     1^st^ (Lower) 8         0..1 for bits     By bit
           word              byte                    1,2,3,4,7 \*      position

  18                         2^nd^ byte    8         0..1 for bits     By bit
                                                     8..15 \*          position

  19                         3^rd^ byte    8         0..1 for bits     By bit
                                                     16..19 \*         position

  20                         4^th^ (Upper) 8         0                 
                             byte                                      

  21       Reserved Zone                   8         0                 

  22                                       8         0                 

  23                                       8         0                 

  24                                       8         0                 

  25                                       8         0                 

  26                                       8         0                 

  27                                       8         0                 

  28                                       8         0                 

  29                                       8         0                 

  30                                       8         0                 

  31       Check sum         Check sum (L) 8         0..255            Binary

  32                         Check sum (H) 8         0..255            Binary
  -------- ----------------- ------------- --------- ----------------- --------------

\* Remark: other bits must be 0

## Allocation of bits in MFC registers

0xF021601C -- FIFO Status 1 Register

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| F     | FIFO07 | F     | FIFO05 | F     | FIFO03 | F     | FIFO01 |
| IFO08 | EMPTY  | IFO06 | EMPTY  | IFO04 | EMPTY  | IFO02 | EMPTY  |
|       |        | EMPTY |        | EMPTY |        | EMPTY |        |
| EMPTY |        |       |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| F     | FIFO07 | F     | FIFO05 | F     | FIFO03 | F     | FIFO01 |
| IFO08 |        | IFO06 | FULL   | IFO04 | FULL   | IFO02 | FULL   |
|       | FULL   | FULL  |        | FULL  |        | FULL  |        |
| FULL  |        |       |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+

**0xF021601E -- FIFO Status 2 Register**

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| F     | FIFO07 | F     | FIFO05 | F     | FIFO03 | F     | FIFO01 |
| IFO08 | T      | IFO06 | T      | IFO04 | T      | IFO02 | T      |
|       | HR_OVF | TH    | HR_OVF | TH    | HR_OVF | TH    | HR_OVF |
| TH    |        | R_OVF |        | R_OVF |        | R_OVF |        |
| R_OVF |        |       |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| F     | FIFO07 | F     | FIFO05 | F     | FIFO03 | F     | FIFO01 |
| IFO08 |        | IFO06 | BUSY   | IFO04 | BUSY   | IFO02 | BUSY   |
|       | BUSY   | BUSY  |        | BUSY  |        | BUSY  |        |
| BUSY  |        |       |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+

0xF021A004 -- Input Interrupt Control Register ( R )

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| IRQ   | IRQ07  | IRQ06 | IRQ05  | IRQ4  | IRQ3   | IRQ02 | IRQ01  |
|       |        |       |        |       |        |       |        |
| SLAVE | INIT\_ | I     | SRQ    | L2REJ | L2ACC  | L1ACC | VBD\_  |
|       |        | NIT\_ |        |       |        |       |        |
| IN    | FAL    |       |        |       |        |       | DONE   |
| TERR. | LING\_ | RIS   |        |       |        |       |        |
|       |        | ING\_ |        |       |        |       |        |
| CHIP  | EDGE   |       |        |       |        |       |        |
|       |        | EDGE  |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| IN    | IRQ14  | IRQ13 | IRQ12  | IRQ11 | IRQ10  | IRQ09 | IRQ08  |
| IT_AC |        |       |        |       |        |       |        |
| K_VME | MFC    | FIFO  | FIFO   | L2ERR | L1ERR  | L     | L1BUSY |
|       | _INT\_ |       |        |       |        | 2BUSY |        |
|       |        | EMPTY | FULL   |       |        |       |        |
|       | ERROR  |       |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+

0xF021A002 - VME Interrupt Controller Mode Register ( R/W )

  ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
  15    14    13    12    11    10    09    08    07    06    05    04    03    02    01    00

  M15   M14   M13   M12   M11   M10   M09   M08   M07   M06   M05   M04   M03   M02   M01   M00
  ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----

M15..M00 bits select interrupt trigger mode: 0 - Edge triggering, 1 -
Level triggering.

0xF021A006 - VME Interrupt Controller Edge Selector ( R/W )

  ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
  15    14    13    12    11    10    09    08    07    06    05    04    03    02    01    00

  E15   E14   E13   E12   E11   E10   E09   E08   E07   E06   E05   E04   E03   E02   E01   E00
  ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----

E15..E00 bits select interrupt trigger edge: 0 - positive (rising), 1 -
negative (falling).

0xF021A004 - VME Interrupt Controller Edge Flip-Flop Selective Reset
Register ( W )

  ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
  15    14    13    12    11    10    09    08    07    06    05    04    03    02    01    00

  R15   R14   R13   R12   R11   R10   R09   R08   R07   R06   R05   R04   R03   R02   R01   R00
  ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----

R15..R00 bits select edge triggered interrupt flip-flop that is to
reset: 0 -- no action, 1 - reset.

0xF021A000 -- Output Interrupt Control Register ( R )

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| IRQ   | IRQ07  | IRQ06 | IRQ05  | IRQ4  | IRQ3   | IRQ02 | IRQ01  |
|       |        |       |        |       |        |       |        |
| SLAVE | INIT\_ | I     | SRQ    | L2REJ | L2ACC  | L1ACC | VBD\_  |
|       |        | NIT\_ |        |       |        |       |        |
| IN    | FAL    |       |        |       |        |       | DONE   |
| TERR. | LING\_ | RIS   |        |       |        |       |        |
|       |        | ING\_ |        |       |        |       |        |
| CHIP  | EDGE   |       |        |       |        |       |        |
|       |        | EDGE  |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| IN    | IRQ14  | IRQ13 | IRQ12  | IRQ11 | IRQ10  | IRQ09 | IRQ08  |
| IT_AC |        |       |        |       |        |       |        |
| K_VME | MFC    | FIFO  | FIFO   | L2ERR | L1ERR  | L     | L1BUSY |
|       | _INT\_ |       |        |       |        | 2BUSY |        |
|       |        | EMPTY | FULL   |       |        |       |        |
|       | ERROR  |       |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+

0xF021C000 - MFC Control Register

+---------+-------+--------+-------+--------+-------+--------+-------+
| 07      | 06    | 05     | 04    | 03     | 02    | 01     | 00    |
+---------+-------+--------+-------+--------+-------+--------+-------+
| I       | SYS   | EXT    | INT   | CAM    |       |        |       |
| NIT_MSK |       |        |       |        |       |        |       |
|         | BY    | BY VME | BY    | BY VME |       |        |       |
|         | VME   |        | VME   |        |       |        |       |
+---------+-------+--------+-------+--------+-------+--------+-------+
| 15      | 14    | 13     | 12    | 11     | 10    | 09     | 08    |
+---------+-------+--------+-------+--------+-------+--------+-------+
| BU2_MSK | L     | B      | L     | E      | L2ERR | E      | L1ERR |
|         | 2BUSY | U1_MSK | 1BUSY | R2_MSK |       | R1_MSK |       |
+---------+-------+--------+-------+--------+-------+--------+-------+

MSK -- mask, where 0 -- set by MRC, 1 -- set by program (VME). An event
will be program simulated by writing 1 to bits 8,10,12,14 when
corresponding bits 9,11,13,15 are set to 1.

0xF021C002 - HOTLink Control Register

+-------+--------+-------+--------+--------+--------+--------+--------+
| 07    | 06     | 05    | 04     | 03     | 02     | 01     | 00     |
+-------+--------+-------+--------+--------+--------+--------+--------+
| SLV\_ | R      | K28_  | R      | R      | BI     | SVS\_  | REFR\_ |
|       | ESET\_ | SYS\_ | ESET\_ | ESET\_ | STEN\_ |        |        |
| RDY   |        |       |        |        |        | HL     | HL     |
|       | IN     | HL    | HL_ERR | SW     | HL     |        |        |
|       | IT_ACK |       |        |        |        |        |        |
+-------+--------+-------+--------+--------+--------+--------+--------+
| 15    | 14     | 13    | 12     | 11     | 10     | 09     | 08     |
+-------+--------+-------+--------+--------+--------+--------+--------+
| \-    | \-     | \-    | \-     | SYNC\_ | ACK\_  | REFR\_ | TRAN   |
|       |        |       |        |        |        |        | SM_ENA |
|       |        |       |        | LOST   | SCL    | RCVR   |        |
+-------+--------+-------+--------+--------+--------+--------+--------+

0xF021C004 - Error Register 1

+--------+--------+--------+--------+--------+--------+-------+------+
| 07     | 06     | 05     | 04     | 03     | 02     | 01    | 00   |
+--------+--------+--------+--------+--------+--------+-------+------+
| L2DEC  | L1DEC  | L2     | L1     | L      | L      | SRQ   | INIT |
|        |        | BUSY\_ | BUSY\_ | 2ERR\_ | 1ERR\_ |       |      |
|        |        |        |        |        |        |       |      |
|        |        | MRC    | MRC    | MRC    | MRC    |       |      |
+--------+--------+--------+--------+--------+--------+-------+------+
| 15     | 14     | 13     | 12     | 11     | 10     | 09    | 08   |
+--------+--------+--------+--------+--------+--------+-------+------+
| SEQ\_  | SCL\_  | SCL\_  | IN     | CAM    | SYST\_ | EXT   | INTE |
|        |        |        | IT_ACK |        |        | ERN\_ | RN\_ |
| BUSY   | ERR    | RDY    |        |        | VME    |       |      |
|        |        |        |        |        |        | VME   | VME  |
+--------+--------+--------+--------+--------+--------+-------+------+

0xF021C006 - Error Register 2

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| SC    | CV\_   | CLK\_ | F      | E4_   | E2     | E1_   | E0     |
| L_SYN |        |       | RAME\_ | ERR\_ | _ERR\_ | ERR\_ | _ERR\_ |
| C_ERR | E      | ER    |        |       |        |       |        |
|       | RR_TFC | R_TFC | E      | TFC   | TFC    | TFC   | TFC    |
|       |        |       | RR_TFC |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| T     | TOUT\_ | L     | L1BUSY | L2ERR | L1ERR  | SCL\_ | MODE\_ |
| OUT\_ |        | 2BUSY |        |       |        |       |        |
|       | BIST   |       | (M     | (MA   | (M     | DA    | ERR    |
| REFR  |        | (MA   | ASKED) | SKED) | ASKED) | TE_ER |        |
|       |        | SKED) |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+

0xF021C008 - MFC Status Register

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| ID\_  | SEQ\_  | S     | HL\_   | ERR\_ | I      | LO    | STAT\_ |
|       |        | IGN\_ |        |       | NTER\_ | ADER_ |        |
| C     | CNTR\_ |       | CNTR\_ | C     |        | VME\_ | OK     |
| NTR\_ |        | MUX\_ |        | NTR\_ | CNTR\_ |       |        |
|       | OK     |       | OK     |       |        | OK    |        |
| OK    |        | OK    |        | OK    | OK     |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| BISOK | REFD   | DS    | CONN   | RVC\_ | RVC\_  | OVF\_ | RVC\_  |
|       |        | TREAM |        |       |        |       |        |
|       |        |       |        | G     | BIST   | DTSTR | DTSTR  |
|       |        |       |        | LOBAL |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+

0xF021C00A - INIT_XN Register

<table>
<colgroup>
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
</colgroup>
<tbody>
<tr class="odd">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>09</td>
<td>08</td>
<td>07</td>
<td>06</td>
<td>05</td>
<td>04</td>
<td>03</td>
<td>02</td>
<td>01</td>
<td>00</td>
</tr>
<tr class="even">
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td><p>XN</p>
<p>07</p></td>
<td><p>XN</p>
<p>06</p></td>
<td><p>XN</p>
<p>05</p></td>
<td><p>XN</p>
<p>04</p></td>
<td><p>XN</p>
<p>03</p></td>
<td><p>XN</p>
<p>02</p></td>
<td><p>XN</p>
<p>01</p></td>
<td><p>XN</p>
<p>00</p></td>
</tr>
</tbody>
</table>

This register is latched both on INIT rising edge and on INIT falling
edge

0xF021C00C - INIT_TN Register

<table>
<colgroup>
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
</colgroup>
<tbody>
<tr class="odd">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>09</td>
<td>08</td>
<td>07</td>
<td>06</td>
<td>05</td>
<td>04</td>
<td>03</td>
<td>02</td>
<td>01</td>
<td>00</td>
</tr>
<tr class="even">
<td>TN 15</td>
<td>TN 14</td>
<td>TN 13</td>
<td><p>TN</p>
<p>12</p></td>
<td>TN 11</td>
<td><p>TN</p>
<p>10</p></td>
<td><p>TN</p>
<p>09</p></td>
<td><p>TN</p>
<p>08</p></td>
<td><p>TN</p>
<p>07</p></td>
<td><p>TN</p>
<p>06</p></td>
<td><p>TN</p>
<p>05</p></td>
<td><p>TN</p>
<p>04</p></td>
<td><p>TN</p>
<p>03</p></td>
<td><p>TN</p>
<p>02</p></td>
<td><p>TN</p>
<p>01</p></td>
<td><p>TN</p>
<p>00</p></td>
</tr>
</tbody>
</table>

This register is latched both on INIT rising edge and on INIT falling
edge

0xF021C00E - Card ID & Serial Number Register

  ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
  15    14    13    12    11    10    09    08    07    06    05    04    03    02    01    00

  ID7   ID6   ID5   ID4   ID3   ID2   ID1   ID0   SN7   SN6   SN5   SN4   SN3   SN2   SN1   SN0
  ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----

0xF021D008 - Number of Words and Sequencer Control Register

  -------------- ---------- -------- -------- -------- -------- -------- --------
  07             06         05       04       03       02       01       00

  WN07           WN06       WN05     WN04     WN03     WN02     WN01     WN00

  15             14         13       12       11       10       09       08

  INIT_ACK_VME   INIT_VME   MODE     START    WN11     WN10     WN09     WN08
  -------------- ---------- -------- -------- -------- -------- -------- --------

0xF021E002 - L1&L2_TN Register

<table>
<colgroup>
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
<col style="width: 6%" />
</colgroup>
<tbody>
<tr class="odd">
<td>15</td>
<td>14</td>
<td>13</td>
<td>12</td>
<td>11</td>
<td>10</td>
<td>09</td>
<td>08</td>
<td>07</td>
<td>06</td>
<td>05</td>
<td>04</td>
<td>03</td>
<td>02</td>
<td>01</td>
<td>00</td>
</tr>
<tr class="even">
<td>TN 15</td>
<td>TN 14</td>
<td>TN 13</td>
<td><p>TN</p>
<p>12</p></td>
<td>TN 11</td>
<td><p>TN</p>
<p>10</p></td>
<td><p>TN</p>
<p>09</p></td>
<td><p>TN</p>
<p>08</p></td>
<td><p>TN</p>
<p>07</p></td>
<td><p>TN</p>
<p>06</p></td>
<td><p>TN</p>
<p>05</p></td>
<td><p>TN</p>
<p>04</p></td>
<td><p>TN</p>
<p>03</p></td>
<td><p>TN</p>
<p>02</p></td>
<td><p>TN</p>
<p>01</p></td>
<td><p>TN</p>
<p>00</p></td>
</tr>
</tbody>
</table>

0xF021E004 - L1&L2_XN Register

  ---- ---- ---- ---- ---- ---- ---- ---- ----- ----- ----- ----- ----- ----- ----- -----
  15   14   13   12   11   10   09   08   07    06    05    04    03    02    01    00

  \-   \-   \-   \-   \-   \-   \-   \-   XN7   XN6   XN5   XN4   XN3   XN2   XN1   XN0
  ---- ---- ---- ---- ---- ---- ---- ---- ----- ----- ----- ----- ----- ----- ----- -----

0xF021E006 - L1&L2_AQ Register

  ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
  15    14    13    12    11    10    09    08    07    06    05    04    03    02    01    00

  E15   E14   E13   E12   E11   E10   E09   E08   E07   E06   E05   E04   E03   E02   E01   E00
  ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----

0xF021E008 - L1&L2 Status Register

  ---------- -------- --------- ------- --------- -------- --------- --------
  07         06       05        04      03        02       01        00

  0          0        INIT      L2ERR   L1ERR     L2REJ    L2ACC     L1ACC

  15         14       13        12      11        10       09        08

  0          0        0         0       0         0        0         0
  ---------- -------- --------- ------- --------- -------- --------- --------

Information is latched on ERROR Interrupt (on L1ERR or L2ERR)

*MRC memory map, registers and bits.*

MRC base address is 0xF02y0000..0xF02yFFFF, where
y=2,3,4,5,6,7,8,9,A,B,C,D.

  ----- ------------ ------ ------------------------------------- --------------
  \##   Hex address  Size   Memory block or register              Write/read

  1     2000..3FFF   8 KB   Dual-Port RAM Section A (Changed in   W/R
                            January, 2000)                        

  2     4000         0      Reset SCC AM85C30                     W

  3     4010         4      CSR of Section A                      W/R

  4     8000..9FFF   8 KB   Dual-Port RAM Section                 W/R

  5     C000         1      SCC Channel B; Access to Control      W/R
                            Registers                             

  6     C004         1      SCC Channel A; Access to Control      W/R
                            Registers                             

  7     C008         1      SCC Channel B; Access to Data         W/R
                            Registers                             

  8     C00C         1      SCC Channel A; Access to Data         W/R
                            Registers                             

  9     C010         4      CSR of Section B                      W/R
  ----- ------------ ------ ------------------------------------- --------------

## 

## Allocation of bits in MRC CSR registers

0xF02y4010 (0xF02yC010) -- Control/Status Register A (B) Highest 16 bits
Read

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| NOT\_ | NOT\_  | BISOK | REFD   | D     | SRQ\_  | E     | ER     |
|       |        |       |        | ONE\_ |        | RROR2 | ROR1\_ |
| DE    | D      |       |        |       | TEST   | _TEST |        |
| FINED | EFINED |       |        | TEST  |        |       | TEST   |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| E     | ERROR  | BU    | B      | SRQ\_ | NOT\_  | CS    | D      |
| RROR2 | 1_MASK | SY2\_ | USY1\_ |       |        | R_A_B | STR_EN |
| _MASK |        |       |        | MASK  | D      |       |        |
|       |        | MASK  | MASK   |       | EFINED | A=0,  | STATUS |
|       |        |       |        |       |        | B=1   |        |
+-------+--------+-------+--------+-------+--------+-------+--------+

0xF02y4010 (0xF02yC010) -- Control/Status Register A (B) Highest 16 bits
Write

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| SRQ\_ | DONE\_ | BIST  | REF    | D     | SRQ\_  | E     | ERROR  |
|       |        |       |        | ONE\_ |        | RROR2 | 1_TEST |
| RESET | RESET  |       |        |       | TEST   | _TEST |        |
|       |        |       |        | TEST  |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| ERR   | ER     | BU    | B      | SRQ\_ | RESET  | NOT\_ | D      |
| OR2\_ | ROR1\_ | SY2\_ | USY1\_ |       |        |       | STR_EN |
|       |        |       |        | MASK  |        | DE    |        |
| MASK  | MASK   | MASK  | MASK   |       |        | FINED |        |
+-------+--------+-------+--------+-------+--------+-------+--------+

0xF02y4012 (0xF02yC012) -- Control/Status Register A (B) Lowest 16 bits
Read-only

+-------+--------+-------+--------+-------+--------+-------+--------+
| 07    | 06     | 05    | 04     | 03    | 02     | 01    | 00     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| I     | RVS\_  | T     | TOUT\_ | RVS\_ | OVF\_  | RVS\_ | TOUT\_ |
| NTSCC |        | OUT\_ |        |       |        |       |        |
|       | GLB    |       | BIST   | BIST  | DSTR   | DSTR  | DSTR   |
|       |        | REFR  |        |       |        |       |        |
+-------+--------+-------+--------+-------+--------+-------+--------+
| 15    | 14     | 13    | 12     | 11    | 10     | 09    | 08     |
+-------+--------+-------+--------+-------+--------+-------+--------+
| E     | ERROR1 | BUSY2 | BUSY1  | SRQ   | DONE   | DS    | CONN   |
| RROR2 |        |       |        |       |        | TREAM |        |
|       |        |       |        |       |        |       | (M     |
|       |        |       |        |       |        |       | FC-FE) |
+-------+--------+-------+--------+-------+--------+-------+--------+

States and Errors recorded by Muon Readout Crate Software

  --------- ------------------------------------------------ ------------
  *Error    *Error explanation*                              *Action*
  Code*                                                      

  0x0000    No errors                                        Transfer
                                                             data

            **States of the Muon Readout code**              

  0x0001    Mure_run start_up is started                     Test
                                                             hardware

  0x0002    Mure_run data acquisition is started             Tranfer data

  0x0004    Mure_run data acquisition is stopped             Exit

            **Errors detected during program start-up**      

  0x4001                                                     

  0x4002    MFC Sequencer Memory is not found or has errors  Exit

  0x4004    Some registers are not found in the MFC          Exit

  0x4008    MFC SCL synchronization Error                    Exit

  0x4010    MRC Dual Port Memory is not found or has errors  Exit

  0x4020    Some registers are not found in the MRC          Exit

  0x4040    MRC HOTLink has synchronization error or cable   Exit
            is not connected                                 

  0x4080    MRC HOTLink Reframe Error                        Exit

  0x4100    Some VBD registers were not found                Exit

  0x4200    VBD initialization was not successful            Exit

  0x4400    VBD RAM is not found or has errors               Exit

  0x4800    Some interrupt routines were not linked          Exit

  0x5000    MFC NVRAM Configuration file has checksum error  Exit

  0x6000    Reserved                                         

            **Errors detected during data acquisition**      

  0x8001    TFW XN sequence error                            Tranfer data

  0x8002    TFW TN sequence error                            Tranfer data

  0x8004    Software time-out of any SRQ                     Send patch

  0x8008    MRC hardware time-out                            Send patch

  0x8010    Front-End XN sequence error                      Tranfer data

  0x8020    Front-End TN sequence error                      Tranfer data

  0x8040    Event length in L3 Header is greater than 8K     Send patch
            bytes                                            

  0x8080    Reserved                                         

  0x8100    Reserved                                         

  0x8200    Reserved                                         

  0x8400    Reserved                                         

  0x8800    Reserved                                         

  0x9000    Reserved                                         

  0xa000    Reserved                                         

            **Errors detected during TFW initialization      
            procedure**                                      

  0xc001    MRC HOTLink has no connection to FE              Exit

  0xc002    MRC HOTLink Reframe Error during TFW INIT        Exit

  0xc004    Some FE did not set BUSY1 on TFW INIT            Exit

  0xc008    Some FE did not reset BUSY1 during TFW INIT      Exit

  0xc010    TFW did not remove INIT within 5 seconds after   Exit
            IACK reset                                       

  0xc020    Reserved                                         

  0xc040    Reserved                                         

  0xc080    Reserved                                         

  0xc100    Reserved                                         

  0xc200    Reserved                                         

  0xc400    Reserved                                         

  0xc800    Reserved                                         

  0xd000    Reserved                                         

  0xe000    Reserved                                         
  --------- ------------------------------------------------ ------------

# Using the mure_run program

***Starting***

-\> \<Gomu Delete previous task t_mure_run,

Unload previous image of the program mure_run

Load new image of the program mure_run

Spawn new task t_mure_run as separate parallel process

***Monitoring***

-\> mure_mon 5, 0x0022 Monitor data, status and errors

> \| \| \| during data taking

\| \| section number

\| enable section bit

period in seconds

-\> \^C Stop mure_mon.

Let mure_run continue data taking.

Operator may issue shell commands.

-\> mure_errors 3 Show last status/errors records registered in MFC
NVRAM

\|

number of records to show

***Stopping***

-\> mure_stop Stop operation of mure_run

Delete task mure_run

***Configuring***

-\> mfc_setup Run if you need to change configuration in the VME crate

MCH3 Muon readout crates layout, 9/11/00

<table style="width:100%;">
<colgroup>
<col style="width: 1%" />
<col style="width: 0%" />
<col style="width: 8%" />
<col style="width: 0%" />
<col style="width: 8%" />
<col style="width: 0%" />
<col style="width: 8%" />
<col style="width: 0%" />
<col style="width: 8%" />
<col style="width: 0%" />
<col style="width: 8%" />
<col style="width: 0%" />
<col style="width: 8%" />
<col style="width: 0%" />
<col style="width: 8%" />
<col style="width: 0%" />
<col style="width: 8%" />
<col style="width: 0%" />
<col style="width: 8%" />
<col style="width: 0%" />
<col style="width: 8%" />
<col style="width: 0%" />
<col style="width: 8%" />
</colgroup>
<tbody>
<tr class="odd">
<td colspan="2">M314</td>
<td colspan="2">M315</td>
<td colspan="2">M316</td>
<td colspan="2">M317</td>
<td colspan="2">M318</td>
<td colspan="2">M319</td>
<td colspan="2">M320</td>
<td colspan="2">M321</td>
<td colspan="2">M322</td>
<td colspan="2">M323</td>
<td colspan="2">M324</td>
<td></td>
</tr>
<tr class="even">
<td colspan="2">0</td>
<td colspan="2"><p>d0olmuo24</p>
<p>South</p>
<p>FMSM</p>
<p>GS 0x30</p></td>
<td colspan="2"><p>Power Supply</p>
<p>314-0 316-0</p></td>
<td colspan="2"><p>d0olmuo22</p>
<p>South</p>
<p>FMSS</p>
<p>GS 0x32</p></td>
<td colspan="2"><p>d0olmuo11</p>
<p>West</p>
<p>CMWTP</p>
<p>GS 0x34</p></td>
<td colspan="2"><p>d0olmuo12</p>
<p>East</p>
<p>CMETP</p>
<p>GS 0x38</p></td>
<td colspan="2">VRC7</td>
<td colspan="2"><p>Power Supply</p>
<p>319-0 321-0</p></td>
<td colspan="2"><p>d0olmuo20</p>
<p>L1C</p>
<p>GS 0x16 </p></td>
<td colspan="2"><p>d0olmuo18</p>
<p>L1mgr</p>
<p>GS 0x19 </p></td>
<td colspan="2"><p>Power Supply</p>
<p>322-0 324-0</p></td>
<td><p>parallel</p>
<p>processors</p></td>
</tr>
<tr class="odd">
<td></td>
<td colspan="2"></td>
<td colspan="2"> </td>
<td colspan="2"></td>
<td colspan="2"></td>
<td colspan="2"></td>
<td colspan="2"></td>
<td colspan="2"> </td>
<td colspan="2"></td>
<td colspan="2"></td>
<td colspan="2"> </td>
<td colspan="2"></td>
</tr>
<tr class="even">
<td colspan="2">1</td>
<td colspan="2"><p>d0olmuo19</p>
<p>North</p>
<p>FMNM</p>
<p>GS 0x31</p></td>
<td colspan="2"><p> </p>
<p>Terminal </p></td>
<td colspan="2"><p>d0olmuo17</p>
<p>North</p>
<p>FMNS</p>
<p>GS 0x33</p></td>
<td colspan="2"><p>d0olmuoXX</p>
<p>West</p>
<p>CMWSP</p>
<p>GS 0x35</p></td>
<td colspan="2"><p>d0olmuo23</p>
<p>East</p>
<p>CMESP</p>
<p>GS 0x39</p></td>
<td colspan="2"><p>d0olmuo01</p>
<p>East</p>
<p>CMESC</p>
<p>0x3b</p></td>
<td colspan="2"><p> </p>
<p>Terminal</p></td>
<td colspan="2"><p>d0olmuo29</p>
<p>L1S</p>
<p>GS 0x18 </p></td>
<td colspan="2"><p>d0olmuo08</p>
<p>L1N</p>
<p> GS 0x17</p></td>
<td colspan="2">Coaxial Input Cnvtrs (L2)</td>
<td><p> </p>
<p> </p></td>
</tr>
<tr class="odd">
<td colspan="2">2</td>
<td colspan="2"><p>Spare</p>
<p>VME 1</p></td>
<td colspan="2"><p>Power Supply</p>
<p>314-1 316-1</p></td>
<td colspan="2"><p>Spare</p>
<p>VME 2</p></td>
<td colspan="2"><p>d0olmuoXX</p>
<p>West</p>
<p>CMWBP</p>
<p>GS 0x36</p></td>
<td colspan="2"><p>d0olmuoXX</p>
<p>East</p>
<p>CMEBP</p>
<p>GS 0x3a</p></td>
<td colspan="2"><p>d0olmuo06</p>
<p>West</p>
<p>CMWSC</p>
<p>GS 0x37</p></td>
<td colspan="2">Power Supply (blank)</td>
<td colspan="2">CFT PS tmngr R/O</td>
<td colspan="2">VEPA Crate</td>
<td colspan="2"><p>Power Supply</p>
<p>322-1 324-1</p></td>
<td></td>
</tr>
<tr class="even">
<td></td>
<td colspan="2"></td>
<td colspan="2"><p>Power Supply</p>
<p>314-2 316-2</p></td>
<td colspan="2"></td>
<td colspan="2"></td>
<td colspan="2"></td>
<td colspan="2"></td>
<td colspan="2"><p>Power Supply</p>
<p>318-2 318-1</p></td>
<td colspan="2"></td>
<td colspan="2"></td>
<td colspan="2"><p>Power Supply</p>
<p>322-2 324-2</p></td>
<td colspan="2"></td>
</tr>
<tr class="odd">
<td colspan="2">3</td>
<td colspan="2"> </td>
<td colspan="2"><p>Power Supply</p>
<p>317-1 317-0</p></td>
<td colspan="2"> </td>
<td colspan="2"><p>Power Supply</p>
<p>------ 318-0</p></td>
<td colspan="2"> </td>
<td colspan="2"> </td>
<td colspan="2"><p>Power Supply</p>
<p>319-1 319-2</p></td>
<td colspan="2"> </td>
<td colspan="2"> </td>
<td colspan="2"><p>Power Supply</p>
<p>321-2 321-1</p></td>
<td> </td>
</tr>
</tbody>
</table>

\<!\-- The following table was generated by the Internet Assistant
Wizard for Microsoft Excel. \--\>\<!\--
\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-- \--\>\<!\-- START OF
CONVERTED OUTPUT \--\>\<!\--
\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-- \--\>\<!\--
\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-- \--\>\<!\-- END OF
CONVERTED OUTPUT \--\>\<!\--
\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-- \--\>*\
*Last Updated on 9/11/00 by Darien Wood (moved VRC crates, fixed
inconsistent crate numbering (0,1,2 instead of 1,2,3))

Host Names & GS ID added on 8/17/00 by I. N. Churin

#