**SVX II Silicon Strip Detector Upgrade Project**

**SVX II Emulator Board**

**\--PRELIMINARY\--**

December 9, 1994

Revision 2.5

***Note: Changes from version 1.0 are indicated by a change bar at the
left margin.***

John T. Anderson

Electronic Systems Engineering Department

Computing Division

Fermi National Accelerator Laboratory

**Document \# ESE-SVX-941209**

1 GENERAL INFORMATION

1.1 System Introduction

1.2 Description Of Component & How It Fits Into The System

1.3 List Of Component Requirements

2 THEORY OF OPERATION AND OPERATING MODES

2.1 Basic Features & Operation (Including Block Diagram)

2.2 Diagnostic Features

3 EMBEDDED & DIAGNOSTIC/DEVELOPMENT SOFTWARE

3.1 Embedded Software

3.2 Development & Diagnostic Software

3.2.1 Description Of Hardware Test Platform

3.2.2 Description Of Software Test Platform

3.2.3 Software Tools & Methodologies

3.2.4 Test Features

3.2.5 User Interface Examples

4 INTERFACE SPECIFICATIONS

4.1. VME Bus Interface

4.1.1 Physical Characteristics

4.1.2 VME Memory Map

4.1.2.1 The General Control Register

4.1.2.2 The Number of Chips to Emulate Register

4.1.2.3 The Chip Boundary Counter Register

4.1.2.4 The Initialize Mode Clock Counter Register

4.1.2.5 The Acquire Mode Clock Counter Register

4.1.2.6 The Digitize Mode Clock Counter Register

4.1.2.6 The Readout Mode Clock Counter Register

4.1.2.7 The Data Generator FITO register

4.1.2.8 The Data Generator Control Register

4.1.2.9 The Serial Parameter FIFO Register

4.1.2.10 The Serial Parameter Control Register

4.1.2.11 The SVX Power Transient Generator Register

4.1.2.12 A/D Registers

4.1.3. Bus Interface Logic and Timing

4.2. Other Bus Interface (SVX II Bus)

4.2.1. Addressing Modes

4.2.2. Data Cycles Types

4.2.3. Register Descriptions

4.3. Front Panel I/O, Test & Monitoring

4.3.1. SVX Cable Connection

4.3.1.1. Connector Pin Configurations

4.3.1.2. Signal Descriptions

4.3.1.3. Protocols

4.3.2. Other Connectors

5 ELECTRICAL & MECHANICAL SPECIFICATIONS

5.1 Packaging & Physical Size

5.2 PC Board Construction

5.3 Power Requirements

5.4 Cooling Requirements

6 SAFETY FEATURES & QUALITY ASSURANCE PROCEDURES

6.1 Module Fusing & Transient Supression

7 EXAMPLE OF COMPONENT OPERATION WITHIN THE SYSTEM

# 1 GENERAL INFORMATION 

The SVX II Emulator Card is designed to provide emulation of the digital
data transfer functions of the SVX II ASIC[^1]. Some emulation of the
analog functions is provided in that SVX-like data may be generated upon
command for readout through the data acquisition system. The SVX II
Emulator is designed to emulate either a single SVX II or a chained set,
providing the opportunity to exercise system intialization software.

A complete description of the SVX II ASIC is too large to insert at this
point, but a short reminder will provide sufficient grounding to
understand the function of the SVX II Emulator. The SVX II ASIC provides
128 channels of silicon strip A/D conversion with programmable delays
and thresholds. In the SVX system the chip is controlled by a serial
control bus, two mode lines, and a CHANGE-MODE clock. The two mode
select lines are used to encode four operating modes:

> 1\. **Initialize**, in which all operating parameters are loaded in to
> the SVX II chip in serial fashion. Multiple SVX chips may be ganged
> together, and the chip itself passes data on to the next chip in line
> after the correct number of bits have been loaded.
>
> 2\. **Acquire**, in which the SVX chip collects analog data.
>
> 3\. **Digitize**, in which the SVX chip digitizes and sparsifies the
> data collected during **Acquire.**
>
> 4\. **Readout**, in which the digital results are read out over a
> byte-wide bus.

The SVX Emulator board is designed to emulate the **Initialize** and
**Readout** modes of the SVX II ASIC, allowing the rest of the system to
be checked without actually having an SVX II chip. The **Acquire** and
**Digitize** functions are relegated to software emulation, in the form
of software that takes some of the serial data parameters as stored
during the **Initialize** operation, or user-defined parameters, to load
a pattern in to a FIFO which is then read out during the **Readout**
mode. The only function provided by the SVX Emulator during the
**Acquire** and **Digitize** modes is that the number of clocks supplied
to the Emulator by the external system are counted for later readout
over VME.

Since many analog operating parameters are also controlled by voltages
and currents provided on the cable, the SVX II Emulator also provides
coarse A/D conversion of these signals. The intent is not to measure
noise or transients, but merely to determine if the signal is provided
and within +/- 10% of expected values.

## 1.1 System Introduction

(These paragraphs should [briefly]{.underline} describe the system in
which this component is used. This subsection should be identical for
all components of a particular system. This section will be provided for
you at a later date. It has not yet been written.)

## 1.2 Description Of Component & How It Fits Into The System

A single SVX II Emulator is connected to the SVX Port Card, using a 60
pin ribbon cable which plugs in to the front of the Emulator board. The
SVXII Emulator card itself is a 9U X 400 mm VME Slave module. Although
power for the SVX chip in the final system is provided over the cable by
the Port Card, the SVX Emulator will draw all power from the VME
backplane, as the load of the SVX Emulator is envisioned to be
significantly greater than the actual SVX chip.

A simple VME Slave interface is provided which allows access to all
internal registers and memories of the SVX Emulator. The SVX emulator
connection to the Port Card is provided at the front panel of the
module. The SVX Emulator provides three basic functions to the software:

1\) A **Data Generator** which takes data patterns loaded from VME in to
a FIFO and clocks them out over the Port Card interface in response to
Readout cycles. By correct programming of the **Data Generator**, the
SVX Emulator may emulate an arbitrary number of SVX chips, and arbitrary
physics data within each one of those chips. This data generator is used
to emulate the **Readout** mode of the SVX II chip.

2\) A **Serial Parameter Memory** which provides access to the serial
parameters loaded to the SVX Emulator by the rest of the SVX system, to
determine that they were loaded correctly. This memory emulates the
**Initialize** function of the SVX II chip. Some of the parameters
loaded in this block are used to form the data in the **Data
Generator.** The **Serial Parameter Memory** is also made available to
the VME interface, so that data may be checked independent of the rest
of the SVX system, and also so that software may vary the data stored in
the **Data Generator** based upon loaded parameters.

3\) A **Slow A/D Converter Block** which gives the VME bus access to
coarse digitizations of the various bias voltages and currents found on
the SVX chip interface, to allow diagnosis of bad cables or faults in
the analog sections of the Port Card.

In addition to these three basic functions, four **Clock Counters** are
provided which count the number of clock cycles provided to the SVX
Emulator by the rest of the system. It is envisioned that these counters
will be useful in chasing down errors in the controlling hardware
related to improper numbers of channels being digitized. The **Clock
Counters** are initialized by VME software which is presumed to be
synchronized with the rest of the system. Each counter measures the
number of clock pulses received in one of the four operating modes. The
output value of all four counters is always available to VME.

## 1.3 List Of Component Requirements

The general requirements of the SVX II Emulator are:

> 1\) Physical packaging in conformance with VME (for power pickoff),
> and operation in accordance with VME specifications for a simple
> A24/D16 Slave.
>
> 2\) Ability to emulate at least 10 SVX II ASICs, and when emulating
> more than one SVX part, to emulate the daisy-chain logic connecting
> the various SVX chips.
>
> 3\) Ability to correctly emulate the serial parameter load/readout as
> implemented in the SVX II; however, only those bits in the serial
> parameter block which affect the digital data readout will have an
> effect upon the SVX Emulator. All the other parameters will be made
> available to VME so that software, which determines the actual data to
> be read out, can modify the output data patterns in response to
> different control values.
>
> 4\) Ability to count pipeline clocks (which may occur as fast as 53
> MHz) in all four operating modes (Initialize,Acquire, Digitize and
> Readout), and to provide those counts to the VME software.
>
> 5\) Ability to provide SVX-like data to allow exercise of the SVX
> readout system data-value-dependent functions, plus also simple
> pattern data to exercise cable connections, drivers and receivers.
> When emulating actual SVX data, the depth of data and readout values
> must react to parameter values loaded via the serial port.
>
> 6\) Ability to switch the meanings of multi-function pins, in
> accordance with the SVX II specs, for the four major operating modes
> of the SVX II.
>
> 7\) Reasonable adherence to timing specifications as given in SVX II
> documentation, [A Brief Guide to the SVX II]{.underline}.

# 2 THEORY OF OPERATION AND OPERATING MODES

## 2.1 Basic Features & Operation (Including Block Diagram)

The SVX Emulator provides three major functions, the **Slow A/D
Converter Block,** the **Serial Parameter Memory,** and the **Data
Generator** as mentioned above. Each of these is a relatively
independent block of circuitry, connected to the **VME Interface** as a
common reference. Subsidiary blocks are the **Mode Latch,** the **Clock
Buffer/Counter** and the **Bi-directional Buffers,** which provide small
but necessary glue functions within the module. These sections are
connected together as shown in this block diagram, and are detailed
individually in the rest of this section.

The bi-directional buffers provide TTL logic levels on logic signals,
whereas the receiver for the CLOCK signal is PECL. All internal signals
are TTL.

> **Slow A/D Conversion Block**
>
> The Slow A/D conversion block is responsible for the monitoring of any
> analog control signals which the rest of the SVX system provides to
> the SVX II chip. In normal operation with the SVX chip, these signals
> connect directly to the analog circuitry, allowing control over the
> functionality of the ASIC and providing required bias currents. In the
> SVX Emulator, these values are monitored by the slow A/D block but
> actually control no functions. High-impedance op-amp buffers (LM124 or
> equivalent) are used to minimize the resistive and capacitive load
> upon the cable. There are 15 of these signals defined, which may be
> broken in to two categories:
>
> **1) Analog bias signals.**
>
> The bias group is formed from the SET, VI1, COMP-B, RAMP-B, RAMP-RA,
> RAMP-PD, RAMP-RF and CAL signals.
>
> The bias signals are simply monitored by the A/D converter block. When
> a conversion is desired, VME writes a control word to the A/D
> converter selecting the channel of interest and initiating the
> conversion. The conversion takes about 15 microseconds, and so VME
> must poll the results register, looking for the 'done' bit, before
> accepting data. An eight-bit conversion is supplied by a Motorola
> MC14444 multi-channel A/D converter. Since most of the bias signals
> are currents determined by resistances to ground, the SVX Emulator
> measures the resistance by supplying current from a local regulated
> power supply and a 1% resistance to measure the resistance to ground
> provided by the cable and Port Card. Too low a reading indicates a
> possible short in the cable; too high a reading may indicate an open.
>
> The [Beginner's Guide to the SVX II]{.underline} (4/22/94 edition)
> lists the various resistive connections, copied here:

-   SET sets pipeline bias current via an external 25K resistor to GND.

-   VI1 sets preamp bias current via an external 18K resistor to AVDD.

-   COMP-B sets A/D comp bias current via an external 350K resistor to
    GND.

-   RAMP-B sets ramp op-amp bias current via an external 1K resistor to
    GND.

-   RAMP-RA sets current which fixes A/D ramp rate via a 70K resistor to
    GND.

To measure these connections, a resistance equal to that given in the
[Beginner's Guide]{.underline} will be used on the SVX Emulator to
provide a digitized value that should be equal to half that read when
digitizing the AVDD voltage itself. Significant deviations from 1/2 AVDD
should be taken as indicative of an error. Standard 5% resistors will be
used, as only an 8-bit digitization is employed.

The remaining three bias signals - RAMP-PD, RAMP-RF and CAL - will be
simply digitized after scaling to match the 5 volt input range of the
A/D converter. As of this writing, the RAMP-PD and RAMP-RF signals are
expected to range from 0 to +5 volts, but the CAL signal may range
anywhere from -5 to +5 volts. In order to map all voltages to the 5 volt
range of the ADC chip, either a jumper to allow inverting or
non-inverting gain of 1, or a gain of 0.5 with an offset, will be
employed.

**2) Analog and digital power supply signals**

The power supply group includes AVDD2, AGND, QVDD, QGND, DVDD and DGND.
These signals normally would be used to power the SVX chip(s), but are
not used to power the SVX Emulator, due to the larger power consumption
of the Emulator board with respect to the ASIC. All the power supply
signals (hot lines and associated grounds) are connected to input
channels of the A/D block, as listed here:

-   AVDD2 analog power source (+2 to +5 volts nominal)

-   AGND analog ground

-   AVDD amplifier power source (+5 volts nominal)

-   QVDD 'quiet' digital power source (+5 volts nominal)

-   QGND 'quiet' digital ground

-   DVDD 'dirty' digital power source (+5 volts nominal)

-   DGND 'dirty' digital ground

Each power supply and associated ground is wired to a channel of the A/D
block, buffered by a non-inverting voltage follower op-amp. In order to
test any crowbar, trip or other safety features provided on the Port
Card, each of the power supplies (AVDD2, AVDD, QVDD and DVDD) is
connected to the collector of an NPN power transistor which is used to
create momentary (\~100 usec) shorts-to-ground of any individual power
supply under VME software control. To insure that failure of these
transistors does not create an unacceptable safety hazard, the power
supply line inputs of the SVX Emulator are individually fused using 1
Amp fast-blow "pico-fuses", mounted in sockets for easy replacement.

**The Serial Parameter Block**

The serial parameter block stores the serial parameter data as loaded
from the Port Card during the Initialize mode of the SVX system and also
provides serial readout of those same parameters. This section contains
serial-to-parallel conversion, a FIFO to store the parallel data, and a
parallel-to-serial converter to allow readout of the stored data. While
data is being loaded, a bit counter will count which bit position is
being stored in to the FIFO.

The IDT 72103 Serial-Parallel FIFO component is used to implement this
function. Two mode bits control the mode of the input and output
sections of the chip, respectively. Each bit may select either serial or
parallel operation. With this configuration, the serial parameter
functions are easily tested. Each of the four selections has a use:

Input Output Function

Serial Serial Direct emulation of serial shift register of N chips

Serial Parallel Serial input which is then read and checked over VME

Parallel Serial Load test data from VME, shift out to Port Card

Parallel Parallel VME self-test of FIFO chip

A secondary counter will be used to count the number of bits loaded in
to the system. For diagnostic purposes this counter will be made
available to VME whenever the SVX Emulator is in the Acquire, Digitize
or Readout modes. During the Initialize mode the counter is counting,
and so any read during this time cannot be guaranteed to yield correct
data. The lower 4 bits of this counter are also used to count how many
clocks have occurred since the FIFO behind the serial-to-parallel
converter has been written to. Since the serial-to-parallel converter
holds eight bits, a simple decoding scheme may be used to load the FIFO.

To provide a cross-check, and to simplify loading the Data Generator
block, an "n \* 182" comparator circuit is connected to the bit counter.
Every 182 clocks, the comparator will trigger a second chip boundary
counter. This counter will, at the end of the Initialization sequence,
tell how many SVX chip's worth of data was actually sent. This same
value can also be used to determine how much data should be loaded in to
the Data Generator. In accordance with the SVX specifications, the chip
boundary counter will be compared to a register which is programmed with
the number of SVX chips being emulated. Should the boundary counter
become equal to the number of chips being emulated, an internal status
line will be set that enables the serial data to start shifting out of
the FIFO - emulating the fixed-length shift register created by
stringing the SVX chips together.

> **The Data Generator Block**

The **Data Generator** block contains a 8K X 9-bit FIFO which is used to
hold the data patterns representative of SVX data. The FIFO is loaded
from VME prior to using the Emulator, and may be loaded with either
cable-test bit patterns (e.g. walking 1's, walking 0's, A/5, 5/A, etc.)
or simulated detector data. The lower eight bits of the data pattern are
the eight-bit data which is provided by the SVX chip. The 9th bit is
used to mark the 'end of data block', allowing the single FIFO to
actually contain multiple data sets. No marker is required between
emulated chips, as the Port Card is connected only to the Priority Out
of the last chip in the chain. Thus, all the Emulator board has to do is
provide a block of data, followed by Priority Out. This architecture, as
a side benefit, allows the VME software to create error conditions of
either 'too few chips in the chain' or 'too many chips in the chain' on
an as-needed basis.

The ability to contain multiple data sets is necessary to be able to
test the Port Card and readout system at speed. VME bus is probably
incapable of reloading the FIFO with a new data pattern before another
readout cycle would begin, and a single test pattern is not sufficient
to exercise the full data handling and processing capabilities of the
SVX readout system. By loading multiple 'events' in to the SVX Emulator
FIFO, system performance with variable event sizes and identification of
'missed' chips or headers may be tested.

In practical use, the **Data Generator** is loaded with data after a
first Initialize cycle has loaded the **Serial Parameter Block** with
chip ID's. This presumes that the overall system has the ability to halt
after the Initialize cycle, and allow the software which controls the
SVX Emulator the time required to read the chip ID's, calculate the data
pattern, and load the **Data Generator.** Once loaded, the SVX Emulator
may be cycled through multiple Acquire-Digitize-Readout cycles, so long
as the output data pattern (or pattern set) is usable. Should a new data
pattern or pattern set be required, the Acquire-Readout-Digitize
sequence must be halted until the new data has been loaded in to the
**Data Generator.**

Within a single Readout sequence, the **Data Generator** will emit data
with each edge (rising or falling) of the externally supplied clock,
incrementing the FIFO internal read address, until a word with the 9th
bit set is emitted. At this point, further increments of the FIFO
address is halted and an external flip-flop is set, asserting the
PRIORITY-OUT signal (which should cause the port card to cease issuing
clocks). The flip-flop is also set by the empty flag of the FIFO. The
PRIORITY-OUT flip-flop is cleared by the CHANGE-MODE signal, so that
when the port card leaves Readout mode the FIFO is immediately
re-enabled to emit the next data block.

The 4K depth of the **Data Generator** FIFO allows for the storage of
multiple events. A single calibration event (all channels have data)
would require 128 bytes of data storage. To emulate 10 SVX chips in a
chain would need 10 times this amount, or 1280 bytes. The 4K depth
chosen is sufficient to hold any reasonable set of calibration event
plus "normal" events (assuming 10% occupancy of channels in a "normal"
event).

A Synchronous FIFO part is used to manufacture the Data Generator. A
synchronous FIFO differs in use from a more common asynchronous FIFO in
that the Empty Flag and the output data only change in response to a
readout clock. Within the Emulator the readout clock is created by a
clock doubler which may be driven either from the SVX clock or the
internal Software Clock.

Software which uses the Software clock function of the SVX Emulator must
be aware that the Empty flag is not updated until the first read, and so
the programmer must first issue a clock before checking the Empty
status. It should be further noted that, after a reset, the first read
cycle applied to the FIFO will emit no data but merely update the flags.
All subsequent read clocks will emit the correct data in order.

The FIFO Empty flag is not connected to Priority Out and so
responsibility of filling the Data Generator with correct SVX data and
the end-of-event flag value for system testing belongs to the software
which fills the Data Generator.

## 2.2 Diagnostic Features

General diagnosis of failures within the SVX Emulator will be
accomplished by the following techniques:

-   The **Serial Parameter Block** may be exercised from VME by setting
    the FIFO to parallel-in/parallel-out mode and then checking the FIFO
    from VME. By selecting either input or output to be serial (with the
    other side left set to parallel), data received from the Port Card
    may be examined by VME, or test data sent to the Port Card. The
    normal serial-in/serial-out mode may then be used to exercise normal
    operation of the system.

-   Suspected errors in the **Data Generator** may be exercised by
    slowing down the clock rate and sending the data, not to the Port
    Card, but to standard CAMAC memory input modules such as the LeCroy
    4302 or the DYCTI (still in development). What may be required,
    dependent upon signal levels, is a converter, but such are easily
    manufactured in-house as wirewrap prototypes. This loop would test
    that data written to the **Data Generator** by VME actually comes
    out as expected, but is limited by the limited speed of the CAMAC
    memories. If higher speed testing is required, then one of two
    techniques may be employed:

-   Setting up a test with a faster memory such as a VDAS system, or

-   Using a scope/logic analyzer combination to ferret out setup/hold
    timing violations and relegating data checking to the slower speeds.

The actual speed at which the CAMAC memories cycle is usually quoted at
20 MHz- that is, they can accept strobes at up to that speed. Since the
SVX system runs with data transferred at both edges of the clock, this
means that a CAMAC unit could only run at a 10 MHz clock speed, which is
only about 40% of planned system speeds. However, since the CAMAC
memories are 16 bits wide, and the SVX data is only 8 bits wide, the
required level translator could also act as a multiplexer and double the
effective readout rate - at the cost of a somewhat more complicated
translator board.

-   Testing of the **Slow A/D Converter** block is accomplished by
    simply connecting a known reference supply (such as an HP or Lambda
    power supply) or a CAMAC test module (like the LeCroy 1976) to the
    various analog signals and checking that the different channels of
    the A/D actually convert. Neither integral- or
    differential-non-linearity is a critical parameter in this block, so
    all that need be tested is that it provides conversions with a gain
    slope within a few percent of nominal. Should a channel fail,
    isolation of the fault between the A/D and the buffering amplifier
    is easily done with an oscilloscope.

-   **Mode Selection** and the **System Clock** may be exercised from
    VME by accessing bits in the general control register of the module
    which allow the software to either monitor or override the
    externally generated settings. When the override feature is
    employed, the mode may be set as desired from VME, and a slow clock
    (caused by toggling a bit in the control register) may be controlled
    directly from software. This 'software clock' will also allow
    localized testing of all counter circuits within the SVX Emulator.

-   Many internal signals are brought out to the logic analyzer
    connections, which are mounted on the front panel of the module for
    easy access.

# 3 EMBEDDED & DIAGNOSTIC/DEVELOPMENT SOFTWARE

## 

## 3.1 Embedded Software

There is no embedded software in the SVX II Emulator. All functions are
accomplished with simple state machines.

## 3.2 Development & Diagnostic Software

### 3.2.1 Description Of Hardware Test Platform

### 3.2.2 Description Of Software Test Platform

Diagnostics to provide decoding of the diagnostic FIFO and exercise of
all board functions (within reason, limited by clock rates) will be
accomplished by a series of small 'C' programs. A host system based upon
a 68000-family processor in a VME board has been selected. A series of
Emulator routines from which a TCL/TK interface could be based have been
written by Ming-Shen Gao, and a standalone EMU_MENU program has been
written by the author of this document.

Little external hardware other than a scope, pulse generator, bench-type
variable power supply and perhaps a CAMAC memory module is envisioned as
the bench test setup.

### 3.2.3 Software Tools & Methodologies

A software is written in C, using compilers provided for the hardware
test platform. The GNU C compiler under VxWorks or UNIX is presumed.

A simplistic methodology consisting of a single test program per main
block of the Emulator is planned, with a menu-driven interface to allow
selection of any test desired. For using the Emulator to test other
portions of the SVX system, a similar menu-driven program with an
extremely limited number of choices (e.g., one choice per operational
mode of the SVX) appears appropriate.

### 3.2.4 Test Features

The SVX II Emulator will have the usual \'anything which can be written
is readable\' feature, plus embedded test points to facilitate easy
logic analyzer hookup. External commercial test devices should be more
than sufficient to exercise the unit \'in vitro\', save for the 53 MHz
clock rates that may accompany serial parameter data loading. For that
rare case, a special test jig that clocks out serial data at 53 MHz may
have to be wirewrapped if a prototype of the Port Card is not available
at the time the SVX Emulator prototype enters testing.

### 

### 3.2.5 User Interface Examples

Without code in place, all that can be said is that simple arrow-key and
function-key interface will be used, with no fancy stuff. Delivery time
is of utmost importance, and so eliminating a 'pretty' user interface
for the minimal type which provides the necessary functionality is
planned.

# 4 INTERFACE SPECIFICATIONS

## 4.1. VME Bus Interface

### 4.1.1 Physical Characteristics

The SVX II Emulator is envisioned to be a single-width 9U X 400 mm card,
to fit with the rest of the SVX system. Connection of the SVX Bus cable
will be at the front panel, along with indicators for 'clock', 'power
OK' and 'mode'. The SVX Bus cable will connect via a standard 60-pin
header. A simplistic A24/D16 VME interface will be used, with no
interrupts.

### 4.1.2 VME Memory Map

All registers are located in a contiguous block of 64 addresses from the
BASE address, which is selected by a DIP switch. The DIP switch allows
the board to reside at any 16k address boundary. For each register
listed below, the bit map and the location (relative to the setting of
the DIP switch) is given. For the reference of those wishing to program
the SVX Emulator, a short list of addresses is given here:

Address Register

BASE + 0 General Control Register

BASE + 0x02 Number of Chips To Emulate Register

BASE + 0x04 Chip Boundary Counter Register

BASE + 0x06 Initialize Mode Clock Counter Register

BASE + 0x08 Acquire Mode Clock Counter Register

BASE + 0x0A Digitize Mode Clock Counter Register

BASE + 0x0C Readout Mode Clock Counter Register

BASE + 0x0E Data Generator FIFO

BASE + 0x10 Data Generator Control Register

BASE + 0x12 Serial Parameter FIFO

BASE + 0x14 Serial Parameter Control Register.

BASE + 0x16 SVX Power Transient Generator Register

BASE + 0x18 **=\>** BASE + 0x36 Slow A/D Registers

#### 4.1.2.1 The General Control Register

The General Control Register, located at the base address selected by
the DIP switch, provides access to any and all miscellaneous control
bits. The General Control register provides low-level control of various
portions of the module, and contains a MASTER_RESET bit which, when a 1
is written to that bit, will create an initialization pulse identical in
function to the power-on reset.

The General Control register is 16 bits wide. The lower eight bits are
'static control' bits whose state may be read back at any time. The
upper eight bits are 'pulse' bits - that is, writing a 1 to the bits
causes an action to occur within the module, but that action will
complete before a subsequent read of the control register could take
place. Thus, the 'pulse' bits have effects, but they always read back
zero.

A bit map of the General Control Register is shown here:

Writing a '1' to the Master Reset Bit will reset the entire module. This
reset, identical to the power-on reset state, will result in the
following state:

1\) The Number of Chips to Emulate Register will be reset to one.

2\) All four Clock Counters will be reset to zero.

3\) The Serial Parameter FIFO will be reset.

4\) The Data Generator FIFO will be reset.

5\) The Chip Boundary Counter will be reset to zero.

Writing a '1' to any of the four Clear Counter bits will reset the
indicated counter to zero. Since the clear operation occurs faster than
external software, upon read these bits are used to monitor the state of
the four decoded mode lines, internal to the device. Reads of these bits
may be used to determine that the correct operational mode has been
selected.

The source of the clock for the SVX Emulator is normally an external
signal provided by the Port Card. For diagnostic purposes, software may
use the two Software Clock Enable bits to disconnect the external clock
source and use in it's stead a Software Clock Toggle bit in the General
Control Register. The Software Clock Enable bit pair (found at bits 7
and 8 in the register) act as the set and reset of a latch, resulting in
the following truth table:

Value written Action

bit 8 bit 7

0 0 Clock source does not change

1 0 Sets clock source to External

0 1 Sets clock source to Internal

1 1 Not Allowed!

When the clock source is set to Internal, transitions in the clock
signal occur every time a '1' is written to bit 9, the Software Clock
Toggle. Other writes to the General Control Register, with bit 9
[not]{.underline} set, will not change the state of the clock. A toggle
mode is selected to allow testing of the SVX Emulator in the Readout
mode. In Readout mode, a new data word is emitted with each transition
of the clock (dual-edge transfers). The Software Clock Toggle bit may be
used to clock data out of the Data Generator FIFO, one word at a time,
as each write to the Control Register would create one clock edge. To
test the counters in the other three modes, two writes to the Software
Clock Toggle bit are required to increment the counter by one, since the
counters for Initialize, Acquire and Digitize modes only count on the
rising edge of the clock.

Similarly, the operational mode of the SVX Emulator is usually driven by
the external MODE lines and the CHNG-MD signal. However, for testing
purposes, software may disable the external MODE and CHNG-MD signals by
setting the Force Mode bit (bit 2 of the General Control register). When
the Force Mode bit is set, bits 0 and 1 of the General Control register
are interpreted as the 2-bit MODE field[^2], and the board changes
function accordingly with each write to the General Control Register.
However, to maintain the manually set mode, all writes must have the
Force Mode bit high. Should a value be written in which the FORCE_MODE
bit is not set, the last mode loaded in to the Mode Latch by CHNG_MD
will become the active mode.

The Set Mode bits may be written to and read back on any access of the
General Control Register, but writes to the Set Mode bits will only have
effect if the FORCE_MODE bit is set, as described in the above
paragraph. Diagnosis of the MODE and CHNG_MD signals from the Port card
is provided by the read-only bits in bit positions 3-6, which read back
the output and input values of the Mode Latch, respectively. The Live
Mode bits read back the actual state on the MODE lines as presented to
the inputs of the transparent latch. The Latched Mode bits read the
output of the transparent latch, and may or may not equal the Live Mode
bits dependent upon the state of the CHNG-MD signal. Judicious use of
these bits may be used to check that the MODE and CHNG-MD signals are
correctly received by the Emulator.

#### 4.1.2.2 The Number of Chips to Emulate Register

The Number of Chips To Emulate Register, located at address BASE + 0x02,
allows the user to program the number of SVX chips which the Emulator
board should emulate. This value is used during the Initialize mode to
control at what point the SVX Emulator will begin stripping data out of
the Serial Parameter FIFO for output over the serial line. The value in
the Number of Chips to Emulate Register is compared to the Chip Boundary
Counter Register internally, and when these two values match, the serial
data output will begin. The count, a value from 1 to 10, is written in
the low four bits of the word.

Upon power-up, or after a Reset, this register will contain the value
one. Writing a value of zero to this register is internally converted to
the minimum legal value of one. NCHIPS values of 11-15 are internally
converted to the maximum legal value of 10. When writing this register,
the upper 12 bits of the 16-bit data value are ignored. Upon read
access, the 'corrected' value is read - thus, a read immediately after
writing the value 0000 would read back the value 0001, since 0000 is an
illegal value.

#### 4.1.2.3 The Chip Boundary Counter Register

The Chip Boundary Counter Register, located at address BASE + 0x04,
provides access to one side of the N\*182 comparator section within the
Serial Parameter Block. This counter is incremented by the same clock
which increments the Initialize Mode Clock Counter, but is reset every
182 clocks by an internal decoder. Thus, the Initialize Mode Clock
Counter reports the **total accumulation** of clocks received by the
Emulator, whereas the Chip Boundary Counter Register reads back the
number of clocks received **modulo 182.**

Under normal circumstances, after initialization data has been received
from the Port Card, this register should read zero - indicating that the
correct number of clock pulses have been received to initialize an
integer number of SVX chips. Should either too few or too many clocks be
received, a non-zero value will be present, indicative of an error. In
the error situation, the total number of clocks received (as given in
the Initialize Mode Clock Counter) may be compared to the value written
in the Number of Chips to Emulate Register (multiplied by 182) to
determine the magnitude and sign of the error.

#### 4.1.2.4 The Initialize Mode Clock Counter Register

The Initialize Mode Clock Counter Register, located at address BASE +
0x06, allows readout over VME of how many clock cycles were received
while the SVX Emulator was in the Initialize mode. The counter is
enabled by the condition of the latched mode lines being equal to 0
(initialize mode), and so clock edges coincident with the trailing edge
of CHANGE-MODE may not be counted due to propagation delay. The 12-bit
counter increments once per full cycle of the delivered clock, and
clocks on the rising edge. This register may be written to from VME in
order to test the counter, but normally only read operations are
performed. Unused bits of the counter read back zero and have no effect
if written.

Upon power-up, board-reset, or setting the individual reset bit for this
counter (located in the General Control register), the counter is reset
to zero.

#### 4.1.2.5 The Acquire Mode Clock Counter Register

The Acquire Mode Clock Counter Register, located at address BASE + 0x08,
provides a similar readout to the Initialize Mode Clock Counter
Register, save that only clocks delivered during Acquire mode are
counted. This register may also be written to, but in normal operation,
only reads are used. The Acquire Mode Clock Counter is eight bits wide.
Unused bits read back as zeroes, and have no effect if written.

Upon power-up, board reset or setting the individual reset bit of the
General Control register, this counter is reset to zero.

#### 4.1.2.6 The Digitize Mode Clock Counter Register

The Digitize Mode Clock Counter Register, located at address BASE +
0x0A, provides a similar readout to the Initialize Mode Clock Counter
Register, save that only clocks delivered during Digitize mode are
counted. This register may also be written to, but in normal operation,
only reads are used. The Digitize Mode Clock Counter is eight bits wide.
Unused bits have no effect if written and read back zero.

Upon power-up, board reset or setting the individual reset bit of the
General Control register, this counter is reset to zero.

#### 4.1.2.6 The Readout Mode Clock Counter Register

The Readout Mode Clock Counter Register, located at address BASE + 0x0C,
provides a similar readout to the Initialize Mode Clock Counter
Register, save that only clocks delivered during Readout mode are
counted. This register may also be written to, but in normal operation,
only reads are used. The Readout Mode Clock Counter is eight bits wide.
Unused bits have no effect if written and read back zero.

Upon power-up, board reset or setting the individual reset bit of the
General Control register, this counter is reset to zero.register.
Clocking of this register occurs on **both leading and trailing edges of
the clock**, so that the value read is the number of words transmitted,
not the number of clock cycles received.

#### 4.1.2.7 The Data Generator FITO register

The Data Generator FIFO Register, located at address BASE + 0x0E,
provides direct access to the FIFO memory used to generate emulated SVX
data. Writes to this location load 9-bit data values in to the FIFO. The
lower eight bits of the data value will become the 8 data bits read out
as the SVX data in Readout mode. The 9th bit is an 'event separator' bit
which is used to delineate between multiple 'events' in the FIFO memory.

When data is read out of the FIFO memory by the Port Card, new data is
presented with each clock until either the FIFO is empty or a word
appears which has the 9th bit set. Either of these conditions will cause
an external flip-flop to be set, which will both disable the Data
Generator FIFO and assert the Priority Out signal. The flip-flop will
remain set until the SVX Emulator is taken out of the Readout mode. At
that point, Priority Out will be removed, and the FIFO re-enabled. Once
Readout mode is again established, clocks will continue to pull out
data.

#### 4.1.2.8 The Data Generator Control Register

Data Generator Control Register. This register, located at address
BASE+0x10, provides access to the control and status flags of the Data
Generator FIFO. Bits are provided to monitor all status flags, and also
to manually assert any control signals, as shown in the drawing below.
The Priority In and Priority Out SVX tokens are also monitored.

.

![](media/image11.emf)

Writing a '1' to the Reset FIFO bit will reset the Data Generator FIFO
to an empty condition; due to internal timing, this bit always reads
back '0' as the reset operation is completed before a new VME cycle can
begin. The FIFO full and FIFO empty flags are read-only status
indicators. Writes to these bits have no effect.

The End of Event status bit (which is read-only), allows access to the
output of the flip-flop that controls the Priority Out signal. This bit
should read back zero while data is being emitted, and should be set to
one when the data word containing the tag bit (bit 9 set) is read out -
bit 9 is connected to the Clock input of the flip-flop. This bit should
remain at one until the Emulator is set to any mode other than Readout,
at which point the flip-flop is asynchronously cleared.

#### 4.1.2.9 The Serial Parameter FIFO Register

The Serial Parameter FIFO Register at address BASE + 0x12 provides
read/write access to the Parameter FIFO for testing. [The usefulness of
this register is dependent upon the operational mode of the Parameter
FIFO as selected with the Serial Parameter Control
Register.]{.underline}

Writes to this register will load data in to the Serial Parameter FIFO
if and only if the input of the FIFO is set to the Parallel mode. When
the FIFO's input is set to the Serial mode of operation, data may only
be input from the Port Card and writes to the Serial Parameter FIFO
register have no effect.

Similarly, reads from this register will read FIFO data if and only if
the output of the FIFO is set to the Parallel mode. When the FIFO's
output is set to the Serial mode of operation, data is only presented to
the serial link that connects to the Port Card, and reads of the Serial
Parameter FIFO register will read back zero.

#### 4.1.2.10 The Serial Parameter Control Register

The Serial Parameter Control Register, located at address BASE + 0x14,
gives access to all status flags and control bits associated with the
Serial Parameter FIFO. It is presumed that this register will be used to
reset the FIFO's upon initialization, and to check flags should an error
occur. The register map is shown in the drawing below:

In typical operation, the lower four bits of this register are used to
set up the Parameter FIFO operation and to monitor it's status. When
diagnosing the board itself on the bench, especially when using the
Software Clock of the General Control Register, the upper bits may be
used to monitor the operation of the controlling logic.

Each bit in this register has a unique meaning. The definitions are:

-   The Top Neighbor and Bottom Neighbor bits allow VME to monitor the
    status of the two SVX handshake signals. These bits are valid
    independent of the current emulation mode and may be used both for
    Initialize and Readout mode testing.

-   The Depth-Reached/ Reset FIFO bit (bit 5) monitors the decoding
    logic used to determine when the FIFO READ signal should be
    activated. Upon power-up or reset, this signal is a '0'. As clocks
    are received in the Initialize mode, the number of clocks is
    compared to 182 multiplied by the Number of Chips value. When the
    requisite number of clocks have been received, Depth-Reached is set
    to '1', enabling the FIFO to begin the output of data - as the
    variable length of the shift register has now been filled. Once set,
    Depth-Reached stays set (as there is always data in the shift
    register) until the board is reset or the Clear Initialize Mode
    Counter bit is set in the General Control Register. Writing a '1' to
    the Reset FIFO bit creates an internal pulse which resets the Serial
    Parameter FIFO.

-   Writing a '1' to the FIFO Retransmit bit will reset the output
    pointer of the FIFO to internal address zero but still retain the
    information within the FIFO. Since the retransmit action is faster
    than the typical VME cycle, reads of this bit always return '0'.

-   The Parameter FIFO Full and Parameter FIFO Empty bits return upon
    read the status of those flags in the FIFO chip itself. Upon power
    up or after a reset, the Empty flag should read back '0' and the
    Full flag should read back '1'. Reading a '0' in the Full flag is
    indicative of an error, for the depth of the FIFO chip is greater
    than the maximum number of words that could ever be loaded by the
    Port Card.

As these are status bits, writes to them have no effect.

-   The Output and Input Mode bits select whether the Parameter FIFO
    will be connected on output and input to either the Port Card
    (serial interface) or to VME (parallel interface). The two bits
    allow for four modes of operation, decoded here:

Input Mode Output Mode Function

Serial Serial Emulates the SVX chip.

Serial Parallel Take data from Port Card, and check it over VME.

Parallel Serial Load test data over VME to be read via the Port Card.

Parallel Parallel Self test of Emulator via VME read/write to FIFO.

The presumed technique of operation is that the Parallel/Parallel mode
will be used to load data in to the FIFO from VME and then read it out,
to check out the Emulator by itself. Once the Port Card is connected,
Serial In/Parallel Out mode may be used to load data from the Port Card
and then read that data over VME, checking the serial link. Readback of
data via the Port Card is easily exercised using the Parallel In/Serial
Out mode, by loading test pattterns from VME and then sending them to
the Port Card. When the communications link is established and checking
of systemic issues is called for, the Serial/Serial mode is used to
emulate the actions of SVX chips. The Serial/Serial mode may also be
used with a loopback cable to determine which end of the cable is at
fault should Serial/Parallel or Parallel/Serial hookups not function.

**Note: When the Serial Input mode is selected writes to the FIFO from
VME are disabled. When the Serial Output mode is selected reads from the
FIFO from VME are disabled. Similarly, when a Parallel Input or Output
mode is selected, the Port Card serial link will be blocked.**

#### 4.1.2.11 The SVX Power Transient Generator Register

The SVX Power Transient Generator Register located at address BASE +
0x16 provides a mechanism whereby software may cause the SVX Emulator to
turn on power transistors which short selected SVX power supplies to
ground for small amounts of time. Which supply or supplies are affected,
and how long, is controlled by values written to this register.

Unlike other registers in the module, the Transient Generator is
write-only. Software validation of its effects is determined by first
initiating a read of the analog value of the selected power supply by a
write to the correct A/D register, then quickly creating a transient
while the conversion is in progress. Readback of analog values
measurably lower than normal, but not zero, would indicate that the
transient occurred.

The lower four bits of the Transient generator register select which
supply or supplies are to be shorted, and the next four bits determine
the duration. The duration value ranges from 1-15 usec, as programmed in
the four-bit field. [Due to propagation delays in the implementation of
the circuit, a duration value of 0 will result in transients of 16 usec
duration, not zero.]{.underline}

#### 4.1.2.12 A/D Registers

The A/D registers located at addresses 0x18 through 0x36 allow software
to monitor the states of various bias currents and voltages in the SVX
cable. Each address corresponds to a unique analog signal. Writing to an
address initiates the conversion process and selects the channel. The
data written is immaterial.

Having initiated a conversion, the software must poll the register
address to determine when the data is valid. The End of Conversion bit,
located in the MSB of the register, is set to indicate that the 8-bit
digitized value in the lower eight bits is valid. To aid in programming
the SVX Emulator, following is a list of each A/D register, the
associated signal, and notes on normal values.

Address Signal Notes

0x20 SET Pipeline bias current set by external resistor. Typical
readback value should be 1/2 that read for AVDD signal.

0x22 VI1 Preamp bias current set by external resistor. Typical readback
value should be 1/2 that read for AVDD signal.

0x24 COMP-B Comparator bias current set by external resistor. Typical
readback value should be 1/2 that read for AVDD signal.

0x26 RAMP-B Ramp op-amp bias current set by external resistor. Typical
readback value should be 1/2 that read for AVDD signal.

0x18 RAMP-RA Ramp rate bias current set by external resistor. Typical
readback value should be 1/2 that read for AVDD signal.

0x1A RAMP-PD Pedestal comparator offset voltage. Typical readback
valueis anywhere from 0 to full scale.

0x1C RAMP-RF Ramp start reference voltage. Typical readback valueis
anywhere from 0 to full scale.

0x1E CAL Calibration test pulse control voltage. Typical readback
valueis anywhere from 0 to full scale.

0x30 AVDD2 Analog power supply voltage. Typical readback valueis
anywhere from +2 to +5 volts.

0x32 AGND Return ground for AVDD2. Should read back very close to zero.

0x34 AVDD Analog power supply voltage. Typical readback valueis about +5
volts.

0x36 QVDD "Quiet" digital power, nominally +5 volts.

0x28 QGND Ground return for QVDD. Should read back zero.

0x2A DVDD "Dirty" digital power, nominally +5 volts.

0x2C DGND Ground return for DVDD. Should read back zero.

0x2E Internal Vcc Internal loopback of local +5 power.

### 4.1.3. Bus Interface Logic and Timing

VME address sub-cycles are responded to by asynchronous logic
implemented in an Altera 7128 EPLD (along with other Emulator
functions). The address decoding logic waits for the falling edge of
AS\*, at which time the output of the address modifier logic is latched.
Thus, the address modifiers must be presented to the Emulator
approximately 20 nanoseconds before the falling edge of AS\*. All other
facets of address decoding are completely combinatorial. In order for
the module to be addressed, AS\* must be low, the address modifiers must
be those selecting standard access for an A24 slave, and the upper 10
bits of the 24-bit address field must have matched the settings of an
on-board DIP switch.

A jumper on the board enables or disables recognition of address bits
24-31. In the [enable]{.underline} position, an extra 8-bit DIP switch
is compared against address bits 24-31, and a match is required in
addition to the match of the lower address bits for the module to be
enabled. In the [disable]{.underline} (default) position, the upper
eight address bits are ignored.

Upon being correctly addressed, the module asserts the internal ITS_ME
signal, which illuminates a yellow LED on the front panel. ITS_ME also
enables the unit to respond to transitions of the DS0\* and DS1\* data
strobes. The unit is designed to respond to 16-bit data transfers only.
DS0\* and DS1\* are ORed together internally, and the resultant DS\*
signal is fed to the input of a four-step pipeline clocked by the
board-wide master clock. The DS\* falling edge propagates through the
pipeline, creating the internal signals DSA\*, DSB\* and DSC\*, which
are used in conjunction with the WRITE\* line to create ANY_WRITE\*,
ANY_READ\* and individual write and read control signals as needed. The
final step in the pipeline is DTACK\*, which is fed back to the VME bus.

The pipeline is clocked either by the VME SYSCLK signal or a local
oscillator. With a 20 MHz local oscillator, the DS\* to DTACK\* response
time is 200 - 250 nsec, variant due to the lack of synchronization
between the DS\* and the local oscillator. The DS\* trailing edge to
DTACK\* trailing edge propagation delay is identical to the leading edge
timing.

As currently designed the interface pays no attention to the LWORD\*
signal. No separate decoding of the order of the DS0\* and DS1\* strobes
is provided. Thus, only 16-bit data transfers are explicitly supported.

In the current implementation no interrupts can be generated by the
Emulator and no connection to any interrupt lines is made. Similarly, no
connection to BERR\* is provided. All data cycles will generate a
DTACK\* response, and **responsibility for the correct manipulation of
the registers of the module rests with the software.**

## 4.2. Other Bus Interface (SVX II Bus)

### 4.2.1. Addressing Modes

Addressing is accomplished through a clock signal (CHNG-MD) which
latches a two-bit MODE field. The MODE determines how the device will
act, in one of four modes - Initialize, Acquire, Readout or Digitize.
Precisely defined, CHNG-MD is connected to the gate input of a
transparent latch, such that when CHNG-MD is **[not
asserted]{.underline}** the latch is **[transparent]{.underline}**, and
when CHNG-MD **[is asserted]{.underline}** the latch becomes
**[non-transparent]{.underline}** to allow changes to the MODE lines
that do not affect the operation of the Emulator. **Changes in the mode
lines which occur when CHNG-MD is [asserted]{.underline} are ignored
until the trailing edge of CHNG-MD, at which time the MODE lines are
assumed to be stable in their new configuration.**

### 4.2.2. Data Cycles Types

Once the MODE is selected, data may be read out in the READOUT mode. In
this mode, data is shifted out synchronous with the input clock until a
flag bit comes out of the 9th bit of the Data Generator FIFO. Data is
latched on both edges of the clock. When the last data word of an event
is clocked out, the Priority Out signal is asserted.

Once Priority Out has been asserted, no more data will be emitted in
response to clocks until the board is taken out of the Readout mode,
placed in first the Acquire, and then Digitize, modes, and then back to
Readout again.

Typical propagation delays from SVX Clock to data valid in the Readout
mode will be on the order of 20 -25 nsec. The SVX Emulator can handle
clock rates up to 53 Mhz but external readout logic must take in to
account the access time of the module.

Serial data transmission may also occur in the Initialize mode. The
first time the board is placed in to Initialize mode, no data will be
transmitted. In the second and all subsequent entries in to Initialize
mode, data loaded during the last Initialize will be serially clocked
out on one pin while the new data is loaded from another.

### 4.2.3. Register Descriptions

A single-bit-wide serial shift register (currently 183 bits long)
contains all parameter data, in an order described in the SVX II chip
specs. No other registers are available from the SVX port.

## 4.3. Front Panel I/O, Test & Monitoring

### 4.3.1. SVX Cable Connection

This connector mates the SVX II Emulator to the Port Card. A 60-pin
ribbon cable connector is used to carry data, control and power signals
from the Port Card to the SVX II Emulator. The 60-pin header carries
only a subset of all the signals available on the SVX II chip, with many
grounds.

Various ground returns are found in the SVX power supply system, which
are a potential source of ground loops and noise. To allow various
grounding schemes to be tested, the SVX Emulator provides various
connection blocks with shunts. All Port Card digital ground signals
(pins
2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48 and
50) are brought from the connector to a shunt block which allows each
individual digital ground to be either connected or disconnected to a
common Port Card Digital Ground signal. All Port Card analog ground
signals (pins 47,57,58,59 and 60) are similarly brought to a header
which allows each individual analog ground to be either connected or
disconnected to a common Port Card Analog Ground signal.

In addition to the two common Port Card Ground signals, four other
'grounds' are present:

\- DG, pin 23, the return of the 'dirty' SVX chip digital power supply
DVDD;

\- QG, pin 29, the return of the 'quiet' SVX chip digital power supply
QVDD;

\- AG, pin 39, the return of the SVX chip analog power supply AVDD;

\- AVDD2G, pin 43, the return of the SVX chip analog power supply AVDD2.

These six 'grounds' - Port Card common digital, Port Card common analog,
DG, QG, AG and AVDD2G, are brought to a third jumper block which allows
each of them to be either left floating, connected to the ground plane
of the SVX Emulator card (and through there, to VME ground), or to the
center conductor of a LEMO contact on the front of the SVX Emulator
which may be connected to an external earth ground. A pictorial
representation of how this may look on the printed circuit board is
given below.

The other signals presented to the Emulator besides grounds are shown in
this connection diagram:

#### 4.3.1.1. Connector Pin Configurations

#### 4.3.1.2. Signal Descriptions

15 analog bias signals and power supply pins, plus 12 digital I/O, 2 for
the differential clock and 3 for the mode control. The clock is
differential PECL levels, but all other digital signals are CMOS/TTL.

Analog signal inputs are buffered by high-impedance voltage followers.
The clock is received using a PECL receiver part supplied by AT&T.
Digital inputs are received using standard TTL receivers. Digital
outputs are driven using fast TTL 30 ohm line drivers such as the
Signetics 74F3037.

#### 4.3.1.3. Protocols

In all four modes, data is qualified by a clock. Data flow control is
managed by a Priority In (enable receipt of data) and a Priority Out
(all data emitted) signal pair. The change of mode is controlled by the
two-bit Mode field, which is captured in a latch controlled by the
CHANGE-MODE signal.

### 4.3.2. Other Connectors

Internal headers are provided for logic analyzer connection, mating with
popular logic analyzers such as the HP6000 series. Front panel space
provides for three logic analyzer connections. Each analyzer header
allows monitoring of 16 lines of data, for a total of 48 monitored
lines. The selected set of lines are as follows:

Header 'A' - SVX bus protocol

channel Signal

0 Clock as received from Port Card

1 Mode bit 0

2 Mode bit 1

3 Change-Mode signal

4 BN (priority in)

5 TN (priority out)

6-13 SVX data bus bits 0-7

14 Data Generator FIFO bit 9 (event boundary flag)

15 DBL_clock (Readout mode double-speed clock)

Header 'B' : Internal control signals

Channel Signal

0 ITS_ME (module has been addressed over VME)

1 ANY_WRITE

2 ANY_READ

3 VME AS\* (buffered copy)

4 VME DS0\* (buffered copy)

5 VME DS1\* (buffered copy)

6 DTACK\* (as generated by Emulator)

7 SYSCLK (board internal clock)

8-12 VME Address bits 1-5 (buffered copy)

13 Serial Parameter FIFO input mode control bit

14 Serial Parameter FIFO output mode control bit

15 \*\* spare, currently unused \*\*

Header 'C': miscellaneous signals

Channel Signal

0

# 5 ELECTRICAL & MECHANICAL SPECIFICATIONS

## 5.1 Packaging & Physical Size

9UX400 VME, single-slot, in conformance with other FNAL VME designs of
that size.

## 5.2 PC Board Construction

6-layer (4 signal, gnd, power), 0.093\" thick, FR-4.

## 5.3 Power Requirements

Estimated: 3 Amps

## 5.4 Cooling Requirements

Flat on-bench convective, or standard airflow within a crate.

# 6 SAFETY FEATURES & QUALITY ASSURANCE PROCEDURES

## 6.1 Module Fusing & Transient Supression

Fusing at no more than 1.3 X peak current draw, plus Tranzorbs on all
voltages. Multiple decoupling (electrolytic/tantalum/ceramic) in
accordance with high-frequency design will of course be used, such that
in normal operation, transients of no more than 5% of nominal Vcc will
be present.

The analog and digital power supply pins of the SVX cable will also be
fused to protect against cable failure.

# 7 EXAMPLE OF COMPONENT OPERATION WITHIN THE SYSTEM

## 

Still somewhat to be determined. Simplistically, the SVX Emulator will
be connected to the Port Card, and each mode will be exercised. The
counter and FIFO registers of the Emulator, when compared against the
data seen by the Port Card, will determine if data is correctly
transferred.

The ability of the SVX Emulator to provide multiple events, and also
real physics data (if such is loaded in the Data Generator FIFO), should
allow for the testing of event recognition software and/or event
building.

The ability of the Emulator to provide transients on the analog and
digital power supplies should also allow testing of any safety features
in the Port Card.

[^1]: ^1^As described in **[A Beginners Guide to the
    SVXII]{.underline}**, written by R. Yarema, dated 4/94.?

[^2]: With the consistent interpretation of 0= Initialize, 1 = Acquire,
    2 = Readout and 3 = Digitizef, just like the real MODE lines as
    delivered from the Port Card.