LBL Trip Summary and Task List

Thursday, February 21, 2008

On the week of February 18, 2008 Peter Denes, Dionisio Doering and John
Weizeorick worked to test the FCCD's Clock Module. The major
accomplishment of this week is seeing first light out of the 480 x 480
CCD using external voltage bias and the FCCD Clock Module. A more detail
list of tasks completed are listed below.

-   Tested the small 20 x 480 CCD with the Leach controller. Needed to
    modify the clock pin out to match the FCCD clock module. Observed
    the CCD output on a scope while modifying the time an LED is turned
    on during exposure.

-   Tested the small CCD with the Leach controller providing the bias
    voltages and the FCCD detector providing the clocks. This was done
    by using a 10 inch adapter cable from the FCCD Clock Module to the
    DB37 pin connector on the Frame Board. The CCD output behaved the
    same with the faster clocks.

-   Tested out how shorting the vertical and horizontal right and left
    signals affected the clock signals. The waveforms appeared to become
    cleaner.

-   Tested the 480 x 480 CCD with the Leach controller providing all of
    the bias voltages except the VDDOUT, which required -22V at 140mA,
    and used the FCCD's Clock Module to provide the clock signals.
    Observed and plotted how the longer light pulses during the exposure
    increased the CCD output signal.

-   Tried different voltage bias, clock rail voltages, and clock timing
    and observed the effects on the CCD output.

-   Improved the linearity of the CCD output by slowing down the
    horizontal clocks.

In preparation for the next meeting the following task need to be
completed by Argonne.

-   Do not need to fix -25V error on Interface Module. Voltage is never
    used.

-   Need to modify VDDOUT circuit to provide 0 to -25V at 300 mA.

-   Need to change the source of VDDA_AS (regulated 3.3V at ? Amps)
    VDDA_ADC (regulated 3.3V) These voltages are currently coming form
    the Data Module. These voltages will tied together and come from the
    Clock Module.

-   Final Clock Module will also need a connector change. We will be
    making it a larger connector and make the pin out symmetrical.

-   The Data Module will need a connector soldered onto its edge
    connector. This connector will plug into an edge connector coming
    out of the vacuum chamber.

-   Move the single point ground into the Acopian power supply. Argonne
    will do the power supply at Argonne and email a marked up schematic
    so that LBNL can make the same changes.

-   Fix Data Module's FPGA program so that the fCRIC power up reliably.

-   Add more features to GUI to allow greater control over the clock
    signals.

-   Fix state machine problem which is generating fewer clocks on the
    first line.

-   Remove small caps on clock driver outputs.

The tasks that LBNL will need to complete before the next meeting are.

-   Make small adapter boards. One between Data Module and vacuum edge
    connector. One for between Clock Module and vacuum edge connector.
    The adaptor boards are meant to provide a method of connecting the
    original FCCD Clock and Data Modules with the final vacuum edge
    connectors.

-   Do glue test on silicon wafer and PCB board.

-   Assemble vacuum housing with vacuum feed through boards epoxy in
    place.

-   Finnish Assembly and install into vacuum housing.

-   Let Argonne know what the power up voltages should be for NGD, NCON,
    and GUARD. I believe that they currently power up at +10Volts and
    have a range of -10 Volts to +10 Volts.

-   Set up temperature controller for final system.

-   Simulate vertical clocks and determine the optimum RC Network.