Introduction

Researchers have constructed excellent monolithic pixel detectors for
minimum ionizing charged particles in standard CMOS using a three
transistor Active Pixel Sensor (APS) design. These devices, however,
have been limited by readout speed since all of the pixels on the chip
must be readout and compared with prior frames using Correlated Double
Sampling to remove fixed pattern noise and KTC noise before struck
pixels can be identified. It is desirable because of multi event pileup
to improve the readout speed of these devices for particle tracker
applications in high luminosity colliders such as RHIC. In these
applications the fraction of hit pixels vs empty pixels is very low so
significant speed improvement could be realized if one could develop on
chip data sparcification. We report here on two different variations of
the APS pixel that we are exploring in the interest of developing
sparcification. One variation is the photo gate and the other is a clamp
circuit. We address the photo gate first.

Photo gate motivation

As mentioned the limited signal to noise in CMOS pixel detectors
requires CDS to reliably identify hit pixels. The photo-gate potentially
provides a way of locally doing CDS on the chip. The photo gate, shown
schematically in fig. 1) has been developed for optical imagers. It is
basically the last stages of a CCD and can be used for CDS in the
following manner. In one approach the drain is periodically reset to the
rail potential and the transfer gate is held at an intermediate
potential. The photo-gate is cycled above and below the transfer gate
potential keeping the silicon depleted below the gates. The drain
voltage is recorded each time the photo-gate is high. By comparing the
voltage or integrated charge on the drain measured with the source
follower before and after transfer a CDS can be formed without resorting
to an externally stored prior value.

In the standard APS the signal from a track is spread over several
pixels which reduces the signal to noise. This is a consequence of have
small point diodes collecting the diffusing electrons from the field
free epi layer. The photo-gate with a large area covering much of the
pixel region should partially correct this problem. It does this without
adding capacitance to the sense node which would reduce the signal to
noise.

These benefits have motivated us to explore the photo-gate option even
though there are potential problems and previous attempts by others have
run into difficulties. We too have encountered problems which will be
reported.

Photo gate simulation

We have performed a 2D simulation to investigate charge transfer from
the photo-gate to the transfer gate. This is an issue for us where we
are using features that go beyond the normal CMOS process (0.25 micron
TSMC) available to us. To get charge transfer between the photo-gate and
the transfer gate, like CCDs the gates must be very close to have
sufficient transverse field and avoid a potential well between the
gates. This is normally accomplished in CCDs by using a double poly
process, not commonly available in CMOS, where the gate separation can
be made as small as the oxide layer by over lapping adjacent gate
structures. With the small feature sizes of the 0.25 micron process it
may not be necessary to use a double poly process. The 0.25 micron
process permits a gate separation of only 450 nm which may be adequate
for charge transfer. We have done a 2D simulation with the Silvaco ATLAS
package which suggests that charge transfer should work. The geometry is
shown in Fig. 2. The transfer-gate and photo-gate are placed directly
over the weakly doped epi layer where collected electrons are produced
by passing charged particles in a pixel detector application. The
potential along a cut line in the silicon just below the oxide layer is
shown in Fig. 3. In the example shown the voltages are set for transfer
with xx volts on the photo-gate, xx volts on the transfer gate and xx
volts on the drain. The separation between the gates is 400 nm.
Electrons collected under the photo-gate will diffuse along the flat
potential below the gate and drift in the smoothly rising potentials
between the gates and between the transfer gate and drain. The potential
is also shown for an 800 nm separation in Fig. 4. Here there is a dip in
the potential between the two gates which will trap charge, preventing
transfer.

An alternative solution to the single poly problem has been to use a
floating n well between the gates. This work around has been used for
optical APS devices, but image lag is a significant drawback to this
approach. The delay problem is most severe for our application where the
signals are small and leakage current is low. The transfer gate and
floating n well are in effect an FET with a bias that puts it very sub
threshold with a large effective resistance.

Silicon tests of photo-gate

We have implemented the photo gate and transfer gate in a 0.25 micron
CMOS process along with related test structures. The geometry is shown
in Fig. 5. The photo-gate covers much of the 20 micron square pixel with
a small transfer gate and drain adjacent to the photo-gate. The
remainder of the pixel area is a p well with three n channel
transistors, the reset transistor, the source follower and the row
select switch. These three FETs are the same as used for the standard
APS structures. The photo-gate and transfer gate was place directly over
the epi layer so that electrons generated by the passage high energy
charged particles can be collected under the photo-gate. In one of our
test structures we eliminated the transfer gate and positioned the
collection drain directly at the edge of the photo-gate. This was to
allow checking the photo gate with minimum complication and we provide
these results first.

A simple test of photo-gate function was made by histograming the out
put signal amplitude as a function of DC photo gate bias. Signals were
generated with uncollimated X-rays from an Fe55 source which leave small
clusters of \~1600 electrons through out the active silicon volume when
they convert. Signal amplitudes were obtained by CDS, namely recording
the frame by frame change in each pixel voltage. Multiple frames are
recorded after each reset. The results of this test are shown as a 2D
histogram in Fig. 6. The distribution of signals is rather flat out to
350 ADC counts for photo-gate voltages below 1.6 volts. Above 1.9 volts
there are no events with ADC values above 100. This demonstrates that
charge is collected under the photo-gate and transfers to the sense node
when the potential difference is sufficient. It was, however, thought
that more events would have the full signal of the 1600 electrons. A
peak was expected in the distribution rather than the observed shoulder.

Exploring this issue further we have used short LED light pulses and
measured the time dependence of the output signal for a single pixel
with the same photo-gate drain structure. The signal collection time
takes \~2ms which is more then 4 orders of magnitude slower than the
time required to collect the signal using the standard APS point diode
design. More work will be required to understand this.

Another semi quantitative check was made to determine that the collected
charge does indeed come from the epi layer. The concern was that the
gate structure may be over a p-well instead of the more resistive epi
layer. By comparing the measured frequency of X-ray generated pulses at
the output with the frequency of pulses from the standard diode APS
structure with the same X-ray exposure we conclude that the full volume
of the epi layer must be contributing signals. If a p-well was in place
below the photo-gate then the volume where X-ray conversions contribute
signal is significantly smaller.

Figures:

![](media/image1.jpeg){width="5.9944444444444445in"
height="4.946527777777778in"}

Fig 1

**Geometry and composition:**

![](media/image2.png){width="4.3597222222222225in"
height="1.9083333333333334in"}

![](media/image3.png){width="6.055555555555555in" height="4.7125in"}

![](media/image4.png){width="5.995138888888889in" height="4.66875in"}

Fig. 4

![](media/image5.png){width="5.993055555555555in" height="5.98125in"}

**Fig. 5**

![](media/image6.png){width="4.083333333333333in" height="2.6625in"}

Fig. 6