# CCD development R&D

The development of high resistivity, n-type CCDs for SNAP is divided
into two efforts. First, the LBNL in-house fabrication facility is used
to test advanced design concepts and to establish performance benchmarks
for commercial CCDs. Second, these designs and their fabrication recipe
are transferred to a commercial foundry so that large production runs
can be done quickly and inexpensively.

To support the development efforts, a testing facility is being built to
measure CCD electrical and optical performance. For a subset of devices,
we perform pre and post radiation exposure measurements. Prior to
testing, individual CCDs must be packaged to allow thermal and
electrical contact. We are building a clean room for this activity.

The R&D tasks described below are

-   Commercialize CCDs.

-   Build test facility.

-   Test CCDs.

-   Build assembly facility.

-   CD1 planning.

## Commercialize CCDs

In this set of activities we are advancing design ideas in the LBNL
fabrication facility and pushing multiple runs of CCDs through a
commercial foundry.

### LBNL fabrication

To date, two LBNL large format CCD runs have been started. One is
complete and the other is mostly so. Devices as large as 2k x 4k with 15
μm pixels have been built and tested with good results. On the same
wafers there are modestly large devices with 10.5 μm and 12 μm pixel
sizes that are relevant for SNAP. Testing of these has only begun. There
are also a variety of readout structures on these devices -- various
sizes of source follower FETs and layout. Noise measurements and other
electrical tests are leading to a selection among the options.

In early 2001, additional fabrication of CCDs will start. While these
will not be of the SNAP format, large devices will cover the area of the
wafer that could be populated with SNAP devices. From this, we will
obtain yield information to evaluate LBNL as a backup foundry for CCDs.
There will be other devices on the periphery for additional testing of
small pixel sizes and readout structures that are relevant to SNAP. All
devices will be used as controls for monitoring the commercially
produced ones.

LBNL fabricated 4" wafer containg an 2k x 4k, 15 μm CCD.

The other two large devices have 10.5 μm and 12 μm pixels.

![](media/image1.png){width="3.995833333333333in"
height="3.1493055555555554in"}

Commercially produced 4" wafer containing LBNL 2k x 2k, 15 μm CCDs.

![](media/image2.jpeg){width="4.0in" height="3.423611111111111in"}

### Commercial fabrication

The design for the first LBNL large format CCDs has been fabricated at a
commercial foundry. The 2k x 2k devices are functional and many of the
smaller format devices have been tested electrically and optically and a
few have been radiation damaged. The results are encouraging.

The commercial vendor has switched from 4" wafers to 6" ones. To monitor
the critical steps of the new process, wafers comprised of an array of 3
mm x 3 mm PIN diodes has been fabricated. These should be complete in
December 2000 and we will then map the areal quality of the wafers. Some
will also be measured for dark current after radiation exposure.

In January 2001 we will submit a design containing our best current
guess for the physical format of a SNAP CCD. At the moment, we think
that nine CCDs can be packed onto a production wafer. These first wafers
will not contain SNAP format CCDs exclusively, but the SNAP ones will be
of the production format and contain samples with 10.5 μm and 12 μm
pixels. This run of wafers will have two lots. The first lot will not go
through the wafer thinning process so that we can receive a lot as soon
as possible to perform electrical and radiation tolerance measurements.
The second lot will be thinned to 300 μm so that optical performance can
be measured. The first lot should be available 16 weeks after design
submission, a schedule quoted by the vendor.

We hope to be able to submit two additional prototyping runs during the
period of the R&D phase. The second run will incorporate additional
guard ring structures if our radiation damage tests on in-hand
prototypes show them to be effective. Both runs will include the crucial
wafer-thinning step.

## Build test facility

To support the testing of CCDs we have purchased or constructed three
dewars and have purchased two UCSD controllers interfaced to two SUN
workstations. One dewar and controller have been in service for well
over a year and the local electronics has been continually evolving to
reduce system noise and to provide clocking flexibility to readout the
CCDs in their various modes. The newest generation of this electronics
is being outfitted to all three dewars.

The software in the controllers and in the workstations is continually
evolving as new measurement procedures are established, become routine,
and need to be automated. For example, an IDL control panel has been
developed to easily measure CTE, dark current, x-ray spectra, and noise.
The controller DSP software has been embellished to allow setting
voltages in volts rather than digital units. Further enhancements needed
are support for trap measurement via pocket pumping and for additional
CTE measurement methods. Other needs will arise over the next 18 months
as we elaborate out test procedures, especially as more optical testing
is introduced.

## Test CCDs

For well over a year we have building up our test abilities. Until very
recently these have concentrated on non-optical measurements. Over the
next year we will be adding more optical performance test capabilities.

At the end of the R&D phase we will have developed documented procedures
for qualifying CCDs. Besides insuring quality control during
construction, this will determine how complex a production test facility
we will have to build.

### Non-optic measurements

The first things we measure on a new CCD are its dark current and read
noise using dark exposures. For parts packaged for front illumination an
^55^Fe source is used. If we can see the Mn Kα and Kβ peaks we are
pretty sure we have a functioning device. The Kα line is then used to
measure parallel and serial CTEs.

It would be interesting to measure the dark current and CTE as a
function of temperature. This has proven difficult because of
uncertainty of our temperature and its stability. A program to improve
the temperature regulation is being implemented now.

As part of a general improvement to our on-cryostat electronics to
reduce system noise, we are implementing a scheme to control the linear
rise and fall times of the clocks. These will be used to optimize gain
and noise as we start increasing the readout rate to 100 kHz required by
SNAP.

### Optical measurements

We are in the early stages being able to project light onto CCDs. We
have successfully imaged flat fields, test patterns, and pin holes. With
the pinholes we have been able to study linearity and well depth for
different pixel sizes and to study erase strategies for persistent
images from over exposures.

Improvements over the next year will permit a measurement of CTE as a
function of pixel charge, locate trap sites, and measure MTF and QE.
These require a combination of software enhancements and hardware
purchases.

Another important program for the next year is to understand diffusion
for backside illuminated devices. For our thick devices, diffusion is a
function of the thickness, wavelength, and depletion voltage. This can
be measured with pinholes of varying size. We note that cosmic rays can
also provide an interesting measurement of diffusion.

### Radiation damage testing

Degradation of CTE and creation of blemishes due to radiation in space
are a critical concern for CCDs. While our n-type, high resistivity,
p-channel devices should be inherently more hardy than devices used
before, we must demonstrate this. At LBNL we have access to the 88"
Cyclotron where w are doing radiation dosing approximately bi-monthly.
Our first test was ambitious. We exposed a cold, powered device up to
6x10^9^ protons/cm^2^ at 13 MeV and it survived with some observed
shifts in the operating point of the source follower FET. This is well
in excess of the expected SNAP lifetime exposure.

Our more recent studies have been done with unpowered devices at room
temperature. We have so far tested four devices during two runs,
incrementally upping the integrated dose in each. A third exposure of
these devices will be done at the end of January. Our procedure is to
measure the source follower I-V and sub-threshold curves pre and post
radiation. The devices are then tested cold pre and post radiation for
dark current, CTE, read noise, and blemishes. Results today are very
encouraging. After the completion of the third exposure we will see if
thermal annealing provides any damage recovery.

Slated instrumentation improvements to improve our radiation studies are
lower system noise to better detect subtle changes and the introduction
of a pocket-pumping test to map out trap sites. Radiation testing will
be on going. We want to move towards performing exposures at lower, more
realistic dose rates on powered, cold devices. Besides the 88"
Cyclotron, we also have access to a ^60^Co source at LBNL if we
determine that pure ionization radiation dosing can produce additional
information.

## Build assembly facility

Before a CCD can be tested it needs to be packaged so that thermal and
electrical contact can be made. To date, we have been doing packaging in
a conventional lab environment. This has been adequate for the
electrical of the last year. As optical measurements become more
important we need to control dust. Also, to measure the yield of CCD
production we need to implement strict, repeatable ESD protection
procedures. We have constructed a Class 10000 clean room for assembling
the CCDs onto their mounts. Supporting equipment installed are a
refrigerator for epoxy storage, a vacuum oven, a laminar flow bench, and
a wire-bonder.

## CD1 planning

A major deliverable at the end of R&D is a cost and schedule for
producing fully tested CCDs. From the prototyping runs we will know the
foundry production costs and turn-around times and our testing program
will measure the yield of usable devices. From these we can establish a
fabrication cost and schedule.

The yield of devices will also determine how large a production test
facility we will have to construct. Our experience with the R&D test
facility will establish the equipment and labor costs required for a
production facility.

## Planning for long lead procurements

It is likely that at the time of CD1 we would seek approval to move
ahead with the procurement of production CCDs as fast as possible,
subject to the state of the prototype development. There are three
reasons for this. One, ASIC fabrication runs have an associated risk of
failure where months of delay can be incurred while the problem is
diagnosed and parts are re-fabricated. Two, production yields can vary
and additional time can be required for additional production runs.
Three, a chosen semiconductor technology may not be long lived and may
no longer be available if there is a large gap between development and
production, *e.g.*, our present foundry has changed from 4" to 6" wafer
size during our brief relationship with them.

## R&D deliverables

The table below highlights deliverables generated during the R&D effort.

  -------------------------------------------- --------------------------
  **Deliverable**                              **Completion Date**

  Development CCDs                             

     LBNL                                      Jul-2001

     Commercial 2                              May-2001

     Commercial 3                              Nov-2001

     Commercial 4                              Jun-2002

  Requirements for production test facility    2-Aug-2002
     and test procedures                       

  Fabrication & test cost and schedule         2-Oct-2002
  -------------------------------------------- --------------------------

## Risk assessment

Preliminary indications are that both LBNL CCDs and commercially
produced versions function well: read noise is low, CTEs are good, dark
current is low, and radiation tolerance is acceptable. The statistics
are low at this time but the number of tested devices will increase
greatly over the next twelve months. The risk areas for the construction
phase are 1) can 6" wafers be thinned to 300 μm or less with good yield,
2) will the yield from commercial vendor be acceptable, and 3) will the
commercial vendor be interested in production at the end of the
development phase. One and two effect the cost and time of production
and testing. There is no indication that three will be a problem. To
cover all three risk areas we are exploring using the LBNL 4"
fabrication line as a backup. The first run of 2001 will answer wafer
yield questions including thinning and we will be assessing upgrade
costs to make this a small production facility.

## Manpower

The table below shows the manpower estimates that have been derived from
a resource load schedule.

+----------------------+--------------------+------------+------------+
| **Personnel**        | ##### Category     | #### FTE   |            |
+----------------------+--------------------+------------+------------+
|                      |                    | **FY01**   | **FY02**   |
+----------------------+--------------------+------------+------------+
| S. Holland           | Engineer           | 1.00       | 1.00       |
+----------------------+--------------------+------------+------------+
| N. Palaio            | Engineer           | 1.00       | 1.00       |
+----------------------+--------------------+------------+------------+
| G. Wang              | Engineer           | 1.00       | 1.00       |
+----------------------+--------------------+------------+------------+
| A. Karcher           | Engineer           | 1.00       | 1.00       |
+----------------------+--------------------+------------+------------+
| W. Kolbe             | Engineer           | 0.90       | 0.90       |
+----------------------+--------------------+------------+------------+
| B. Turko             | Engineer           | 0.25       | 0.25       |
+----------------------+--------------------+------------+------------+
| J. Lee               | Technician         | 1.00       | 1.00       |
+----------------------+--------------------+------------+------------+
| R. Kuiper            | Machinist          | 0.05       | 0.05       |
+----------------------+--------------------+------------+------------+
| M. Uslenghi          | Scientist          | 1.00       | 1.00       |
+----------------------+--------------------+------------+------------+
| A. Secroun           | Scientist          | 1.00       | 1.00       |
+----------------------+--------------------+------------+------------+
| B. Frye              | Scientist          | 1.00       | 1.00       |
+----------------------+--------------------+------------+------------+

A brief description of the personnel follows:

-   Steve Holland is an LBNL engineer and is the inventor of the high
    resistivity, n-type CCD detectors. He heads the LBNL Micro Systems
    Lab where the in-house devices have been fabricated.

-   Nick Palaio is an LBNL semiconductor process engineer at the Micro
    Systems Lab.

-   Guobin Wang is an LBNL semiconductor engineer at the Micro Systems
    Lab.

-   Armin Karcher is an electrical engineer with experience in digital
    board level design and has been responsible for establishing the
    LBNL CCD test facility.

-   Bill Kolbe is an LBNL engineer with a broad experience in developing
    scientific instruments many incorporating optics systems.

-   Boyan Turko is an LBNL engineer with a long history in the
    application of CCDs and their low noise readout.

-   Joong Lee is an LBNL technician in the CCD lab with responsibility
    for electronics support and for developing the SUN-based readout
    software.

-   Richard Kuiper is a machinist adjacent to the CCD lab and does
    occasional fabrication.

-   Michela Uslenghi is a UC Berkeley postdoc with prior experience in
    the use of CCDs with image intensifiers.

-   Aurelia Secroun is a UC Berkeley postdoc who has prior experience in
    CCD testing and has most recently been developing the requirements
    for the SNAP star tracker.

-   Brenda Frye is an LBNL postdoc who has been working with supernova
    cosmology project.

## Budget summary 

The table below contains the budget summary in k\$ excluding scientist
salaries.

  ----------- ----------- ---------- ---------- --------- ---------- --------
  **WBS**                 **FY01**                        **FY02**   

              EDIA        Material   Total      EDIA      Material   Total

  A.1.12.3    452         276        728        475       97         571
  ----------- ----------- ---------- ---------- --------- ---------- --------

## Schedule summary

A schedule summary is shown below which tracks the narrative above. The
fully expanded schedule is provided elsewhere.

![](media/image3.wmf){width="6.497916666666667in"
height="4.225694444444445in"}