**Cost Comparison**

Below is a cost comparison of the DSP-based and FPGA-based options, and
a comparison with the U.S. baseline cost estimate. A number of
assumptions are made to make this comparison

-   The L1 trigger rate is 100 KHz

-   The S-link is assumed to operate at 40 Mwps

-   A Region-of-Interest trigger is assumed

-   The Pixel cost does not apply to the B-layer

-   TOT pixel readout is assumed

-   Only component costs are shown. Raw-board cost, board loading and
    board debugging have not been included. These costs were included in
    the production baseline ROD estimate and were taken at that time to
    be \$952(FY97) per board.

-   The preprototype baseline cost was \$84K(FY97) for fabrication of 16
    cards + 2 \"prototype\" cards. This cost included the bare-board,
    board loading etc. Thus to make a comparison with the estimates
    presented at the review, I have calculated a component cost per
    board as follows: \$84K/16= \$5250 - \$952 = \$4298(FY97).

-   The production baseline component estimate of \$4059 - \$952 =
    \$3107(FY97) was inflated by 6% to FY99 and is \$3293(FY99).

-   The preprototype baseline component estimate of \$4298(FY97) was
    inflated by 6% to \$4556.

-   No attempt was made to scale either the FPGA-based or DSP-based
    preprototype estimates to production quantities.

+-----------------------+------------+---------------+--------+-------+
|                       | SCT Links  | PIXEL LINKS   | Sct    | PIXEL |
|                       |            |               |        |       |
|                       | per rod    | PER ROD       | COST   | COST  |
+-----------------------+------------+---------------+--------+-------+
| Preprototype baseline | 32         | 32            | 4556   | 4556  |
+-----------------------+------------+---------------+--------+-------+
| ROD production        | 32         | 32            | 3293   | 3293  |
| baseline              |            |               |        |       |
+-----------------------+------------+---------------+--------+-------+
| FPGA-based            | 96         | 36            | 4392   | 3309  |
| preprototype          |            |               |        |       |
+-----------------------+------------+---------------+--------+-------+
| DSP-based             | 96         | ?             | ?      | ?     |
| preprototype          |            |               |        |       |
+-----------------------+------------+---------------+--------+-------+

**Schedule Comparison**

The baseline milestone for the completion of fabrication of the first
preprototype ROD was 30-Mar-99. A comparison with the milestones
presented at the review is given below. A five month delay is projected
in the case of the FPGA-based design and a ?? month delay in the case of
the DSP-based design.

  ----------------------- -----------------------------------------------
                          First preprototype complete

  Baseline schedule       30-Mar-99

  FPGA-based              1-Sep-99

  DSP-based               ?
  ----------------------- -----------------------------------------------

**Manpower**

A summary of the physicist, electrical engineer and student manpower
available through the expected debug-period of the preprototype ROD is
given below.

  ------------------------ ---------- ------------------------- ----------
  UW                       FTE        UCI                       FTE

  Dao(EE)                  0.10       Dailing(EE)               

  Fasching(Phys)           1.0        Fahland(Phys)             

  Hayes(Phys)              1.0        Lankford(Phys)            

  Jared(EE)                0.25       Pier(EE)                  

  Marks(EE)                1.0        Schernau(Phys)            

  Nagel(EE)                1.0        Students                  

  Students                 0.5                                  
  ------------------------ ---------- ------------------------- ----------