Annual Technical Status Report

For

February 2003 -- January 2004

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Monolithically Interconnected Silicon-Film^TM^

Module Technology

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## Prepared by

AstroPower, Inc.

461 Wyoming Road

Newark, DE 19716-2000

USA

NREL Technical Monitor: B. von Roedern

Prepared under Subcontract No. RAT-3-30630-29

January 2004

# EXECUTIVE SUMMARY

# 

AstroPower is developing a thin-silicon on ceramic photovoltaic product.
Work has focused on understanding the efficiency potential of silicon
layers formed by atmospheric chemical vapor deposition and
recrystallized by zone melting recrystallization. The thermal properties
of the ceramic continue to be refined to more closely match silicon. Key
results for this period include:

Ceramic Substrate Development:

-   Decreased the amount of solvent in the slurry by 5%.

Solar Cell Device Results:

-   Completed a 30-watt module comprised of CVD epi on p+ single
    crystal.

Silicon Recrystallization:

-   New large area zone melt recrystallization (ZMR) system installed.

Solar Cell and Sub-Module Fabrication:

-   Designed new monolithically interconnected solar cell (MISC) grid
    pattern to reduce both I^2^R losses and aperture area.

-   SIMS and thermography characterization tools used on new MISC
    design.

# CERAMIC SUBSTRATE DEVELOPMENT

Experiments were performed with the standard formulation in an attempt
to reduce the cracking that occurs occasionally as the cast tape dries.
The amount of binder in the slurry was increased from 3.5 % to 6.5 % in
one percent increments. This did not reduce any of the cracking and at
6.5 % the green density of the ceramic was reduced considerably.
Previous experiments to look at the effects of reducing the amount of
binder in the slurry only caused the cracking to increase upon drying.
The amount of solvent in the slurry was also adjusted and it was found
that 5 % less solvent in the slurry reduced the cracking enough to
improve the yield of dried green ceramics by \~ 15 %.

Work was performed to match the CTE of our ceramic with the CTE of
silicon by using ZrW~2~O~8~ material as a CTE modifier in our ceramic.
ZrW~2~O~8~ exhibits negative thermal expansion (NTE) but this phase is
apparently only thermodynamically stable between 1105 C and 1231 C. This
phase can be obtained at room temperature by rapidly cooling from 1200
C, and remains kinetically stable on heating to about 600 C. Our ceramic
firing process takes the ceramics to 1500 C, however, it is a very slow
cooling process and would not allow the NTE phase to be locked in. The
ZMR process, however, would take the substrate to 1200 C and allow for
rapid cooling from this temperature. We tried this heat treatment step
previously using the small area ZMR system but the bottom set of lamps
only brought the substrate temperature to about 850 C, and the top lamp
only brought the 2mm wide region below it to 1200 C as it scanned the
surface. Our new large area ZMR system is capable of heating a sample to
1250 C using only the bottom bank of lights, and allows for rapid
cooling, making it an effective RTP system. Utilizing the large area ZMR
system we heat-treated our standard ceramic formulation containing 3%
and 6% ZrW~2~O~8~ as an additive to adjust CTE. The substrates were
heated to 1200 C and held for intervals of 10, 20, and 30 minutes before
the lamps were turned off, allowing the substrates to rapidly cool to
room temperature. CTE measurements were done using our dilatometer, and
it was found that for times up to 30 minutes at 1200 C there was not a
reduction in CTE but rather an increase, indicating that the ZrW~2~O~8~
had decomposed into its components ZrO~2~ and WO~3~. The CTE curves for
additions of 3 % and 6 % heated to 1200 C for 30 minutes are pictured in
Figure 1. The 10 and 20-minute curves for each of the percentages were
not included, as they closely mimicked one another.

![](media/image1.wmf){width="5.979166666666667in"
height="4.020833333333333in"}

Figure 1. CTE curves for 3% and 6% ZrW~2~O~8~ additions to ceramic after
heat treatment

## 

## 

## **CVD Development**

Efforts with respect to the CVD for the first half of the year were
primarily focused on 100-cm2 device processing development. This
included depositing 20 to 25m thick, 1 -cm, epitaxial layers on low
resistivity p+ single crystal and p-type Silicon-Film wafers. The single
crystal wafers had a sand blasted and NaOH etched surface texture. The
Silicon-Film samples were etched with a chemical polish (CP), which
helped planarize the surface, prior to epitaxy.

The epitaxial growths on the Silicon-Film samples first had an in-situ
p+ (0.02 ohm-cm) layer deposited to reduce any contribution from the
p-type bulk followed by the standard active layer. The epitaxial growth
rates for these samples averaged 4.2 m / min.

The following structure was used for the Silicon-Film devices:

-   in-situ HCl etch (0.5 m) to remove any native oxide

-   22 m in-situ p+ (0.02 -cm) epitaxial BSF

-   22 m 1 -cm epitaxial active layer

The latter part of the year involved a restructuring of the company,
which included a change in personnel and a learning curve in both the
operation and maintenance of the CVD system. A high scrubber pressure
during a polycrystalline silicon on ceramic run, led us to completely
dismantle and clean the scrubber system only to find that a faulty
manual valve was creating too much back pressure in the system. After
fixing the valve and doing a couple of polycrystalline Si seed layer
depositions on ceramic, we then developed a low pressure problem with
the scrubber system. This time the problem was tracked to a solenoid
valve that was stuck open causing the recirculation pump to suck air
into the system. A few runs later another problem developed. This time
it was with the RF power supply. While powering up the RF heating system
an arcing was heard coming from the power supply. Although it has not
been determined what is causing the arcing, two of seventeen ceramic
resistors were found cracked in the power supply. New resistors were
installed, and CVD development has resumed.

# Grain Growth

The new large area ZMR was completed. The large area ZMR system is
capable of recrystallizing samples as large as 6 x 6 square at speeds
from 1 mm to 1 cm /min. and has the capability to heat the sample to
1200 C using only the bottom lamps. Being able to heat the sample to
this temperature with only the bottom lamps results in less power
required to obtain a melt using the top lamp, and the ability to
recrystallize at faster speeds. Being able to recrystallize at faster
speeds will allow us to study the effect of grain growth and crystal
orientation as a function of growth speed on the ceramic substrate. The
new ZMR system, pictured in Figure 2, was built in part by CVD Equipment
Corporation of Ronkonkoma New York, and part in-house. CVD Equipment
Corporation fabricated the square quartz tube system with automated
load/unload, and the bottom heater configuration consisting of nine
infrared lamps in a gold plated reflector housing. The top lamp
configuration and scan drive mechanism were fabricated in-house. This
consists of a single infrared lamp in a reflective housing that is
suspended from a linear slide and driven with a ball screw and DC motor.
The top lamp housing is quickly adjustable in .002 increments to
accommodate varying sample thickness and the scan speed is variable from
1 mm to 1 cm/min.

After the new large area ZMR system was turned on and brought up to
temperature, it became apparent that there was insufficient heat
shielding. The motor and drive mechanism for the top lamp, and the lead
wires for the bottom lamps were not shielded from the bottom IR lamps
causing them to become too hot. A heat shield was fabricated from
specular aluminum sheet and is connected to one side of the top lamp to
protect the drive motor and one end of the drive mechanism. On the other
side of the top lamp we needed some type of folding or collapsible heat
shield that would compact as the top lamp neared the bulkhead at the end
of its travel. For this we fabricated something similar to a bellows
type way-cover out of aluminized fiberglass cloth. The aluminum coating
on the fiberglass reflects 95 % of the IR light providing an excellent
heat shield. We used the same material to fabricate heat shields over
the lead wires for the bottom lamps.

![](media/image2.jpeg){width="5.45in" height="4.075in"}

Figure 2. New AstroPower large are recrystallization system.

The first experiments in the new ZMR system were the heat treatment
experiments done on the ZrW~2~O~8~ containing ceramics. There appeared
to be no problems, with the bottom lamps heating the system to 1200 C
for as long as 30 minutes. The first recrystallizations done in the new
large area ZMR system were an experiment to look at the silicon growth
morphology as a function of scan speed. After adjusting the top scan IR
lamp to provide a narrow focused beam, the melt uniformity was adjusted
side to side at a speed of 0.3 cm/min. With the ZMR speed of 0.3 cm/min.
providing long extended grains, we began increasing the ZMR speed of the
top lamp while the bottom lamps held the samples at \~ 1200 C. For each
sample, melt zones were obtained at the 0.3 cm/min. speed before the
speed was increased. The speeds investigated and the resulting
morphology are listed in Table 1. Figure 3 displays the three different
morphologies observed as a function of the different growth speeds.

+------------------------------------+---------------------------------+
| **Growth Speed (cm/min.)**         | ### Resulting Morphology        |
+------------------------------------+---------------------------------+
| 0.3                                | ### Long extended grains        |
+------------------------------------+---------------------------------+
| 0.5                                | ### Long extended grains        |
+------------------------------------+---------------------------------+
| 0.7                                | ### Dendritic grains            |
+------------------------------------+---------------------------------+
| 1                                  | ### Small grains                |
+------------------------------------+---------------------------------+

Table 1. Growth speeds and resulting morphology

![](media/image3.jpeg){width="2.8in"
height="1.9305555555555556in"}![](media/image4.jpeg){width="3.0in"
height="1.9409722222222223in"}

Figure 3. (a) Small grained growth (b) Long extended grain growth

![](media/image5.jpeg){width="2.8in" height="1.9513888888888888in"}

\(c\) Dendritic grain growth

Figure 3. Displays the three different morphologies observed as a
function of the different growth speeds.

The dendritic growth is generally observed in our thin Si films when the
heat is extracted too rapidly from the recrystallizing film. The small-
grained growth occurs with even faster heat extraction, indicating that
if we want to be able to grow at these speeds we will need to put more
heat into the sample. In October of 2002 we had XRD performed on some of
our thin-film silicon on ceramic that had been grown at 0.3 cm/min. to
determine the crystallographic orientation. The XRD indicated that our
dominant orientation was \<111\> with the \<220\> peak also apparent. It
has been proposed that by varying the scanning speed and base
temperature during the ZMR process, that a preferred \<100\> orientation
can be achieved. XRD will be performed on these samples grown at faster
speeds, and experiments will continue to obtain large extended grain
growth at faster scan speeds.

# Device Fabrication Development

A device process was developed for silicon deposited on both 100 cm^2^
Silicon-Film wafers and low resistivity single crystal CZ wafers. The
two primary variables for the optimization of a production viable
process on these devices are the post diffusion anneal (PDA) and the
contact firing. The PDA is required because the samples are diffused
utilizing a phosphorous-based production spray and a continuous belt
diffusion. In order to optimize the emitter and reduce any inactive
phosphorous at the surface the post diffusion annealing step is
performed. Initially, both the CVD on Silicon-Film and the CVD on single
crystal samples were fabricated into devices using the appropriate
production PDA and screen-printed contact process for those respective
materials. Device results were poor due to low voltages and fill factors
with fill factors being reduced by both series and slight shunt
resistance. It was clear from these results that both the PDA and the
contact process required further optimization to maximize performance.
In order to isolate the problems associated with the PDA from those
associated with the contact firing, a photo-mask and evaporated contact
process was used for device fabrication. The evaporated contact process
greatly reduced the series resistance increasing the fill factor by an
average of 15-20 %. For the CVD on single crystal material the open
circuit voltage was increased by an average of 30 mV with a 40 C
increase in PDA temperature. The CVD on Silicon-Film material did not
fair as well and displayed no improvement with the variation of the PDA
temperature. Both materials responded to PECVD hydrogenation with an
average of 13-15 % increase in efficiency. This increase could possibly
be due to the passivation of surface defects or further annealing of the
emitter that is not being completed in PDA.

Forty of the epitaxially grown CVD silicon on p+ single crystal
substrate samples were current matched and then tabbed. The average
device results for the forty tabbed cells are listed in Table 2.

  -------------- -------------- -------------- -------------- --------------
  \# of cells    avg. Voc (mV)  avg. Isc (A)   avg. FF (%)    avg. Pmax (W)

  40             563            2.6            67             0.98
  -------------- -------------- -------------- -------------- --------------

Table 2. Device results for tabbed epitaxial CVD silicon on p+ single
crystal substrate with evaporated contacts.

A module was then fabricated with these forty cells. The tabbing had to
be done manually, as our production tabbing and stringing processes are
not tooled to handle evaporated contacts. The remainder of the module
fabrication step, however, was performed in our module production line.
The module was tested here at AstroPower and the IV curve is pictured in
Figure 4, with test results listed in Table 3.

![](media/image6.wmf){width="5.364583333333333in"
height="3.0104166666666665in"}

Figure 4. IV curve for 40 (100 cm^2^) cell module

  ----------- ----------- ----------- ----------- ------------- ------------
  Voc (V)     Isc (A)     FF (%)      Pmax (W)    Module        Aperture
                                                  efficiency    efficiency
                                                  (%)           (%)

  22.52       2.39        69.74       37.57       7.6           9.1
  ----------- ----------- ----------- ----------- ------------- ------------

### 

### Table 3. Device results for 40 cell module

Previously, device processing utilized both our Research & Development
and Production facilities to perform diffusions. Since it was determined
that tube diffusion causes a back junction and lower current on our
ceramic devices, spray diffusion was chosen as the replacement. This was
performed inline with our Silicon Film^TM^ production furnace. Problems
arose due to scheduling and different spray formulations. Repeatability
and cleanliness became difficult to control. In order to maintain
uniformity among our samples, experiments were conducted to bring spray
diffusion online at our Solar Park (R&D) facility.

With spray diffusion, an oxide needs to be present in order to ensure
uniform coverage of the sample. This is accomplished in production by
growing a thin oxide prior to the belt diffusion process. The lack of
appropriate equipment to form this oxide required the development of a
new spray formulation for the phosphorous dopant that eliminated the
need for the oxide. Isopropyl alcohol (IPA) was added to the mixture to
allow surface tension to hold the uniformity of the spray. When viewed
under the microscope, large droplets were noticed along with areas
without spray coverage. The spray gun was replaced with one which
produced a finer mist. This reduced the size of the droplets as well as
the amount of spray used. We can now routinely achieve sheet
resistivities of 40-50 /square on polycrystalline control wafers using
the spray belt diffusion process.

A new contact scheme was designed for the monolithically interconnected
sub-module structure. The new design, pictured in Figure 5, has the
cross-over interconnects in the middle of the cells as opposed to the
ends, as in the previous design. With this new design the *I ^2^ R*
losses are minimized and the non-aperture area is reduced. The original
sub-module design was primarily developed as a proof of concept to show
that we could successfully electrically insulate the dice cuts and then
reconnect the segments in series with minimal losses. The interconnects
were placed at the ends of the segments on this structure so that we
could use a dielectric epoxy as cross-over insulation as opposed to the
expensive photo-patterned polyimide. The epoxy wasn't used in a center
cross-over structure for fear of shading the emitter with slop from the
application process. This is no longer a problem as we now can deposit
the epoxy in a very small-defined area with our direct write ink
dispenser. The further reduction of losses and reduction of non-aperture
area with the new design should increase sub-module efficiency by as
much as 25 %.

![](media/image7.wmf)

Figure 5. Schematic of monolithically interconnected solar cell design.

Mesa devices fabricated on the silicon on ceramic material have had good
current densities (17-18 mA/cm^2^) with diffusion lengths from 15-21 m,
however, voltages have varied from the mid 300 mV to 500 mV range within
a small area (9-16 cm^2^). These results have changed our focus from
device processing to characterization.

A MISC device (#254) was fabricated using the new design. The electrical
data without AR is listed in Table 4.

  ---------------------- ------------------------ -----------------------
  V~oc~ (mV)             J~sc~ (mA/cm^2^)         FF (%)

  422                    18                       54
  ---------------------- ------------------------ -----------------------

Table 4. Electrical results for new MISC design (#254).

This device was studied using SIMS, I-V measurements under sun
simulator, I-V measurements using Sinton tester, quantum efficiency
measurements, and contactless light lock-in-thermography.

Figure 6 shows results of SIMS measurements of the sample #254, which
has three layers: active (20 m), BSF (12 m), and seed (50 m). Only a
part (about 20 m) of the seed layer is shown in Fig.1. Regarding the
profile of Boron, one should mention two important facts: (i) relatively
low concentration near the surface (2x10^16^cm^-3^), and (ii) gradient
of doping from the interface towards the surface. To understand the role
of this doping gradient, we performed PC1D modeling of the solar cell
parameters. In particular, we compared a homogenously doped
(2x10^16^cm^-3^) active layer and active layer with the doping profile
from Fig. 6. However, no marked difference regarding Isc and Voc values
was observed in these structures.

![](media/image8.wmf)Figure 6. SIMS profiles of B, Fe, Al and Cr in a
three-layer Si structure grown on a ceramic substrate (measured at NREL)
\[2\].

To perform shunt-analysis in the solar cell array, a new method --
contactless light lock-in-thermography (Figs.7, 8) - developed in the
University of Konstanz, Germany was used for the first time. Contrary to
the known contact lock-in-thermography method \[1\], which uses a
current flow generated by voltage applied to the solar cell contacts,
the new method allows shunt-analysis without any contacts. The voltage
(V~oc~) in the contactless solar cell (or in the open-circuited cell
with contacts) is generated by a pulsed LED light. If no leakage exists
in the cell or it is homogenous, no heat distribution peculiarities can
be determined. However, any leaky (shunt) spots cause laterally
inhomogeneous distribution of the photogenerated current (in the
open-circuited cell it is equal to the dark current), and - in terms of
heat -- hot spots appear on the surface. The application of pulsed
illumination allows the use of lock-in methods and reveals a very small
heat increase over a background level.

![](media/image9.wmf)

Figure 7. Schematic of contactless light lock-in thermography setup
\[3\].

![](media/image10.png){width="2.875in" height="3.125in"}

Using the contactless light lock-in-thermography we studied one of the
fabricated PV arrays: #254. Fig. 9 shows a picture of a light lock-in
thermogram of this array. In this picture one can easily distinguish
shunts, which are mostly located near the contact grid lines. As it is
clear from the name of the method, the contactless light
lock-in-thermography does not require contacts to reveal shunts. Thus,
this method allows studying the shunt formation at different stages of
the solar cell processing (after diffusion, etching, formation of
contacts). This more detailed study of shunt formation is planned for
the nearest future.

![](media/image11.jpeg){width="6.4319444444444445in"
height="3.963888888888889in"}

Figure 9**.** Light lock-in thermogram of the array #254 \[3\].

References

\[1\] O.Breitenstein, M.Langenkamp, J.P. Rakotiaina, and J.Zettner " The
imaging of shunts in solar cells by infrared lock-in thermography", in.
Proc. of 17^th^ European Photovoltaic Solar Energy Conference, Munich,
Germany, 2001, pp. 1499-1502.

\[2\] Data courtesy of Bob Reedy, NREL..

\[3\] Image courtesy of the University of Konstanz, Germany.