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**SVX II Silicon Strip Detector Upgrade Project**

**TEST FIBER INTERFACE BOARD**

**\--PRELIMINARY\--**

November 13, 2023

S. Zimmermann, J. Andresen, J. Chramowicz, H. Gonzalez,

K. Treptow, T.Zmuda

Document \# ESE-SVX-950817

1\. GENERAL INFORMATION

1.1 System Introduction

1.2 Description of Component & How it Fits into the System

1.3 List Of Component Requirements

2\. THEORY OF OPERATION AND OPERATING MODES

2.1 Basic Features & Operation

2.2 Configuration of The TPC and SVX-II Chips

2.3 High Level Command Emulation

2.4 Data FIFO AB and C

2.5 G-Link Boards

2.6 Test Port Card Analog to Digital Converters

2.7 Calibration Inject

2.8 Number of Clocks for the SVX II Analog to Digital Converter

3\. EMBEDDED & DIAGNOSTIC/DEVELOPMENT SOFTWARE

4\. INTERFACE SPECIFICATIONS

4.1 VMEbus Interface

4.1.1 Addressing Modes

4.1.2 Data Cycles Types

4.1.3 VME Register Descriptions

4.2 STAR/SRC Interface

4.2.1 J3 Backplane Control Connector

4.2.2 Front Panel Control Connector

4.2.3 Command Protocol

4.3 Test Port Card Interface

4.4 G-Link Interface

4.5 Front Panel

5\. RESET, POWER UP RESET & INITIALIZATIONS,

6\. DIAGNOSIS

6.1 Diagnosis of the TFIB and TPC

6.1.1 Reset

6.1.2 Cables and Drivers/Receivers between TFIB and TPC

6.1.3 Configuration of the SVX-II Chips or FPGA

6.1.4 HDI Cables and Partial Test of SVX-II Chips

6.2 Diagnosis of the Command Lines between STAR/SRC and TFIB

6.3 Diagnosis of the G-Links

6.4 Status Latch

7\. ELECTRICAL & MECHANICAL SPECIFICATIONS

7.1 Connectors and Dip Switches

7.2 Packaging & Physical Size

7.3 PC Board Construction

7.4 Power Requirements

7.5 Cooling Requirements

8\. SAFETY FEATURES & QUALITY ASSURANCE PROCEDURES

8.1 Module Fusing & Transient Suppression

8.2 Other Safety & Quality Assurance Subsections

9\. APPENDICES

9.1 List Of Component Documentation

9.2 Schematics

9.3 PAL, FPGA Equations

9.4 Timing Diagrams

9.5 Parts List

9.6 Additional Appendices

# GENERAL INFORMATION

## System Introduction

This document describes the "TEST FIBER INTERFACE BOARD", hereafter
referred to as the TFIB. The TFIB is a 9Ux400 VME card which interfaces
to a customized J3 backplane and the J1 VMEbus backplane. It is one of
the modules of a test stand designed to control and readout the SVX-II
chips \[ref. 1\]. Figure 1 illustrates the basic components of the test
stand which are the SVX Test Acquisition and Readout (STAR) board \[ref.
2\], the TFIB, the Test Port Card (TPC) board \[ref. 3\], and the
MVME162/7 motherboard. The TFIB board can also be interface with the
Silicon Readout Controller (SRC) \[ref. 4\] board through the J3
backplane, allowing further testing.

## Description of Component & How it Fits into the System

The TFIB will be used to fully test the SVX-II chips and silicon
detectors. This testing will be used in the development of the next
generation of the CDF SVX detector. The control of the SVX-II chips is
divided into two boards which are the TFIB and the TPC. The TFIB
executes commands from three different sources:

-   Commands delivered by the STAR board or by the SRC board through the
    J3 backplane or front panel.

-   Commands previously stored by the VME motherboard inside the
    Configuration/Command FIFO.

-   Commands executed via selectable bits of the TFIB's Control
    Register.

When the TFIB executes commands from its Configuration/Command FIFO or
Control register, the TFIB works independently of the STAR/SRC. These
commands are executed synchronously with the TPC. The TFIB interprets
these commands and delivers microcommands to the TPC. The word
"microcommands" refers specifically to the sequence of bits that the
TFIB-CT sends to the Test Port Card controller (TPC-CT). The TPC
generates the logic levels to control the internal features of the
SVX-II chips. One TPC can control up to three chains of SVX-II chips
which are mounted on a hybrid. These hybrids are connected to the TPC
through the High Density Interconnect (HDI) cable.

The following is the flow of commands and clocks from the STAR/SRC to
the SVX-II chips:

-   The STAR or the SRC sends a 53 MHz clock and commands to the TFIB
    through the J3 backplane or front panel.

-   The TFIB interprets the commands from the STAR/SRC and sends the
    SVX-II clock, the serial clock, and microcommands to the TPC using
    differential PECL levels.

-   The TPC controller interprets the microcommands and delivers the
    proper CMOS logical level sequences to the SVX-II chips through the
    HDI.

The clock sequences for the SVX-II chips are generated directly by the
TFIB. These clocks are fanned out by the TPC to the three HDIs.

The data from the SVX-II chips travels through the following path:

-   SVX-II chips transmit the data to the TPC, through the HDI, using
    CMOS levels.

-   The TPC converts these signals to differential PECL levels and
    transmits the data to the TFIB through three 8 bit parallel wire
    links.

-   The TFIB board accepts data from three of these HDI links.

-   The STAR board accepts data from three of these HDI links.

The STAR/SRC board has a large eight-bit buffer to hold the data from
the SVX-II chips. The TFIB has three 2K x 8 buffers which corresponds to
one buffer for the data from each HDI.

The following sections give detailed descriptions of the TFIB.

## List Of Component Requirements

The major components of the TFIB design are as follows:

-   The TFIB is a 9 U x 400 mm VME card.

-   The TFIB is connected to the J1 and J3 backplanes of the VME crate.
    Connections to J2 are not implemented.

-   The J1 backplane follows the VMEbus specification (ANSI/IEEE
    STD1014) \[ref. 5\].

-   The J3 backplane is a custom made backplane \[ref. 6\]. The STAR
    board sends commands and clocks to the TFIB through this backplane.
    Pins on the J3 connector provide -5.2 V for the ECL logic on the
    TFIB.

-   The STAR supplies one command every 132 ns.

-   The TFIB controls one TPC. The TFIB is capable of reading from all
    three HDIs connected to the TPC. The readout data rate is 26.5
    MBytes/sec in each HDI.

-   The digital electrical interface between TFIB and TPC is
    differential PECL using AT&T 41 Series chips \[ref. 7\].

-   Two G-Link daughter boards can be connected to the TFIB. The G-Link
    daughter boards are used to send data that has been read by the TFIB
    to the SAR board \[ref. 8\].

-   The TFIB supplies the TPC with the Calibration, Ramp-Reference and
    Ramp-Pedestal analog voltages.

-   Cooling for the TFIB will be supplied by fans mounted on the VME
    crate.

-   The TFIB requires +5.0 V and -5.2 V power supplies.

# THEORY OF OPERATION AND OPERATING MODES

## Basic Features & Operation

Figure 2 is a block diagram of the TFIB. The main features of the TFIB
are the following:

-   The execution of commands sent by the STAR/SRC or from the
    Configuration/Command FIFO.

-   Saves the sequence of commands into a Silo FIFO.

-   Synchronizes and shapes the appropriate clock for the SVX-II chips.

-   Translates these commands into microcommands to the TPC.

-   Receives and stores into the Data FIFOs the parallel data from the
    TPC.

-   Appends HDI identification to the data from the TPC.

-   Allows diagnostic testing of the SVX-II chips and TPC.

-   Delivers the Calibration, Ramp-Pedestal and Ramp-Reference bit
    stream to the DACs on the TPC.

-   Controls the configuration of the TPC controller which is a FPGA.

-   Reads back the configuration of the TPC controller.

-   Control the configuration of the SVX-II chips.

-   Read back the configuration of the SVX-II chips.

-   For future testing, allows the installation of boards with G-Links
    and laser diodes

All units of the TFIB operate synchronously with a 53 MHz clock. This 53
MHz clock is supplied by the STAR/SRC through the J3 backplane or a
connector on the front panel. The TFIB also has the capability to
operate independently of the STAR/SRC as the TFIB has its own 53 MHz
clock generator. The source of the clock for the TFIB is selected by one
bit of the Control Word and DIP Switch S1.

The functions of the TFIB are controlled by the TFIB controller
(TFIB-CT). The TFIB-CT has several VME registers. One of the functions
of these VME registers is to configure the TFIB-CT to execute commands.
In this document, the word "commands" refers specifically to commands
that the following units pass to the TFIB-CT:

-   The STAR/SRC through the J3 backplane or front panel.

-   The list of commands previously downloaded into the
    Configuration/Command FIFO.

-   The VME interface through the Control Register.

Depending on which unit supplied the command, the TFIB-CT has three
modes of operation which are named Real Mode, Emulation Mode, and
Immediate Mode. When the TFIB-CT executes commands received from the
STAR/SRC, it is working in the Real Mode. When the TFIB-CT executes the
list of commands from the Configuration/Command FIFO, it is in Emulation
Mode. When the TFIB-CT executes commands from the Control Register, it
is in Immediate Mode.

The main function of the Real Mode and Emulation Mode are for the data
acquisition of the SVX-II chips. However, there are commands for
calibration of the SVX-II chips, for the resetting of the TFIB, TPC, and
SVX-II chips, for the regaining of lock of the G-Links, and for
diagnostic testing. These commands are listed in Section 4.2.3 of this
document. The Emulation Mode is implemented to allow the TFIB-CT to test
all commands that the STAR/SRC can request independently of these
STAR/SRC modules. This Emulation Mode is a powerful tool for diagnostic
testing as well as for the development of the TFIB. The VME interface
writes to the Configuration/Command FIFO the list of commands to be
executed when in the Emulation Mode. The VME interface then uses the
Immediate Command code 1 (Execute Emulation Mode) of the Control
Register to trigger the Emulation Mode.

The Immediate Mode is used for configuration of the SVX-II chips and the
FPGA of the TPC. This mode is also used for diagnostic testing.

The VME motherboard can monitor the Executing Real/Emulate Command and
Executing Immediate Command bits to check when the FIB is executing
commands. When executing commands, the VME motherboard should access
solely the Status and Control registers of the TFIB. For example,
consider that the TFIB is executing real commands. To access other
registers inside the TFIB, the VME motherboards first has to disable
real commands (set to "one" bit 5 of the Control Low Register). Then, it
has to monitor if the TFIB already finished the execution of the present
real command. Finally, it can access the registers of the TFIB.

When the TFIB-CT receives a command, it executes the appropriate
operation. If the command is associated with the TPC, the TFIB-CT sends
the necessary serial microcommands (through the line SR-CMD) to the TPC.
The TFIB receives commands, interprets these commands, and when
necessary sends microcommands to the TPC. The bits of the SR-CMD are
validated by the Serial Clock (SR-CLK). After the microcommand is
delivered to the TPC-CT, the TFIB and the TPC work synchronously. The
TFIB-CT sends SR-CLK to the TPC-CT to advance the state machine of the
TPC-CT. The TFIB-CT delivers these clocks with the appropriate timing
required by the SVX-II chips and TPC-CT.

In Real Mode, the STAR/SRC delivers commands (CMD \[4:0\]), SYNC pulse,
advance pipeline (AD-PIPE), and the 53 MHz master clock (MCLK) through
the J3 backplane or front panel. A set of 2_inputs/1_output
multiplexers, controlled by a DIP switch S1, is used to select the
source of these signals between the J3 backplane or front panel. Section
4 of this document describes the timing of this interface. When the TFIB
is in this mode, the source of clock is the J3 backplane or front panel.
When the TFIB-CT receives the commands, TFIB-CT executes the requested
actions.

The SVX-II chip clock has different shapes and frequencies \[ref. 1\].
The maximum and minimum delay of the SVX-II chip acquisition clock has
to be controlled within strict boundaries in order to guarantee that all
SVX-II chips controlled by different TFIBs and TPCs will be acquiring
data synchronously. When the TFIB-CT is in Real Mode with commands being
supplied by the J3 backplane and the SVX-II chips are in acquisition
mode, the SVX-II Clock Shaper formats the SVX-II chip acquisition clock
using the internal advance pipeline signal (INT-AD-PIPE) and the J-SYNC
pulse delivered by the J3 backplane. When the same is happening, but the
commands being supplied by the front panel, the TFIB uses the INT-SYNC
pulse to generate the acquisition clock. The INT-SYNC pulse is
synchronous with the master clock (the D flip-flop synchronizes it). For
all other operations, the clock is supplied directly by the TFIB-CT, by
the SVX_GEN_CLK line. The signal SVX_CLK_SEL, supplied by the TFIB
controller, informs the SVX-II Clock Shaper when to use the SYNC pulse
of the J3 backplane. AT&T differential PECL drivers are used to send the
SVX-II Clock, Serial Clock, and microcommands to the TPC.

One of the commands executed in Real and Emulation modes is the
Calibration Inject. This command forces the SVX-II chip to inject charge
into its own pre-amplifiers. The TFIB-CT uses a delay line, programmable
by the VMEbus, to time this command in relation to the acquisition
clock. So, when the TFIB-CT recognizes this command, it sends the proper
microcommands to the TPC-CT, then, it times the Serial Clocks to advance
the state machine of the TPC-CT using this delay line. With this
feature, one can control the timing relation between the acquisition
clock and Calibration Inject operation.

The Silo FIFO is a 2K x 9 FIFO which stores the code of all commands
delivered through the J3 backplane or front panel. The VME motherboard
can access this FIFO and read out the sequence of these commands. When
the FIFO gets full, the TFIB-CT removes the old commands from the FIFO
in order to be sure that the most recent 2K commands are saved. The
store can be disabled by a bit in the Control Register or by the
execution of the Latch Status command.

The bottom portion of the TFIB block diagram has a set of components to
receive the data read out from the TPC. The TPC can read out data from a
total of three High Density Interconnects (HDI). The data is transmitted
to the TFIB using the same AT&T PECL protocol. The AT&T receivers
translate this data to TTL electrical levels. The main components of
this section is the set of three Data FIFOs (A, B and C). These Data
FIFOs are used to synchronize the data from different HDIs and for
diagnostic testing. The different modes of operation of these Data FIFOs
are set by the Control Register located inside the TFIB-CT. The TFIB-CT
communicates with the FIFO controller logic (DFIFO-CT) which then
generates the proper clocking for the various components of this data
readout section of the logic.

The HDI IDs are a set of latches accessible through the VME interface.
The VME motherboard downloads the HDI identification number into this
latches. The HDI ID is appended to the top of the SVX-II data.

The TFIB reads out data from the SVX-II chips and transmits this data to
the SAR through the G-Links. Further details on the format of this data
are in the Data FIFO AB and C section of this document. In this Real
mode of operation, the FIFOs are used to synchronize data from different
HDIs. Before the TFIB-CT actually starts the readout of the data, it
requests to the DFIFO-CT to store the HDI ID into the FIFOs. Then, the
TFIB-CT sends the readout clock for the SVX-II chips and informs the
DFIFO-CT to enable the data write operation. The SVX-II clock (A-CLK,
B-CLK or C-CLK clock signals in Figure 2) arrives in parallel with the
data through the AT&T receivers. Figure 3 shows the relation between
this data and clock. New data is available at each transition of the
SVX-II clock which operates at 26.5 MHz. The delay between the
transition of the clock and valid data on the output of the SVX-II chip
has not been determined, therefore there are delay lines to set the
proper relationship between data and clocks.

The DFIFO-CT logic delays the clock in order to synchronize the clock
with valid data. Then, it shapes the clock to a duty cycle of
approximately 50% (Latch Clock in Figure 3). This The Latch Clock stores
the data into the input latches. After another delay, the data is
transferred to the Data FIFOs. As soon as the two FIFOs connected to one
G-Link have three or more words, the DFIFO-CT reads the data out of the
FIFOs and sends the information through the G-Links.

The HDI Enable register allows the VME motherboard to enable the input
circuitry associated with the HDI that are properly connected and
operational. The TFIB-CT synchronizes itself with the SVX-II chips, by
means of special data patterns End Of Readout (EOR). The EOR informs to
rest of the data acquisition system that all data from that HDI was read
out. When the DFIFO-CT detects this pattern, it informs the TFIB-CT. The
TFIB-CT sends at least four more SVX-II readout clocks (STAR
requirement) and then suspends the SVX-II readout clock to conclude the
readout operation. Of course, the DFIFO-CT should not look for EOR in
HDI that are not operational.

As previously mentioned, this section of the TFIB has other operating
modes. The G-Links may be disabled resulting in all SVX-II data staying
inside the Data FIFOs. The VME motherboard can then transfer this data
to its own memory through the use of the VME interface. Another mode of
operation allows the VME motherboard to actually write different
patterns into the Data FIFOs. The VME motherboard can read back the Data
FIFOs, or the DFIFO-CT can transmit the pattern in the Data FIFOs
through the G-Links.

For configuration of the SVX-II chips and the TPC-CT, the TFIB-CT uses
the Configuration/Command FIFO and specific microcommands. When the VME
motherboard requests the download of the configuration of the SVX-II
chips, the TPC-CT sends microcommands to the TPC to set the SVX-II chips
into configuration mode. The TPC-CT then reads the configuration bytes
from the Configuration/Command FIFO, serializes the configuration bytes,
and sends them to the TPC, using the Serial Microcommand line. A similar
operation occurs when the TFIB-CT configures the TPC-CT.

The Configuration/Command FIFO is not connected directly to the VME
interface. The data flows through the TFIB-CT because the TFIB-CT also
has to write to this FIFO when it is uploading the configurations of the
SVX-II chips or the TPC-CT. When the TFIB-CT is uploading the
configuration, the bit stream arrives as one bit of the data path
connected to the TPC in parallel with the clock. This is similar to
Figure 3 except that it is one data bit instead of DATA\[7:0\]. The bit
is latched but not stored inside the Data FIFOs. The DFIFO-CT intercepts
this data stream and forwards the bits to the TFIB-CT. The TFIB-CT
assembles a byte and stores it inside the Configuration/Command FIFO.
The VME motherboard can then check the consistency of the information.

The VME motherboard also has to program serial digital to analog
converters (DAC) on the TPC. They set analog voltages used for
calibration, ramp-pedestal and ramp-reference. The TFIB has several VME
registers that are used for this task. When the motherboard writes to
these registers, a specific controller serializes the data, and sends it
to the TPC. There, it is used to program the DAC. Soon after dowloanding
a DAC, the DAC Controller reads back the data stored inside the DAC
Readback Data register.

## Configuration of The TPC and SVX-II Chips

The TFIB allows the VME motherboard to download and upload the
configuration of the SVX-II chips connected to one TPC and the FPGA[^1]
mounted on the TPC. These operations are performed through the following
VME registers:

-   Configuration/Command FIFO Register.

-   HDI address Register.

-   Number of chips/HDI Register.

-   Control Register.

-   Status Register.

The VME motherboard sees the download and upload of the configuration of
the SVX as one operation. The TFIB actually performs these
download/upload sequence automatically. The VME motherboard writes the
configuration bits to the Configuration/Command FIFO. Then, the VME
motherboard programs the HDI Address Register and the number of SVX-II
chips connected to the HDI into the Number of Chips/HDI Register. Next,
it requests the immediate command Download/Upload Configuration of
SVX-II chips of the Control Register which triggers the sequence. The
CFIFO controller reads the Configuration/Command FIFO and sends the
appropriate clocks, microcommands, and serial data string to the TPC.
The TPC controller programs the SVX-II chips. Then, the TFIB controller
sends the appropriate clocks and microcommands to read back the
configuration of the SVX chips. The CFIFO controller reads the data
string and stores it into the Configuration/Command FIFO. The VME
motherboard may poll the Executing Immediate Command bit of the Status
Register to recognize when the operation is completed. Finally, the
motherboard can check if the uploaded data is correct.

To download the FPGA of the TPC, the VME motherboard writes the
configuration to the same Configuration/Command FIFO. Then, the VME
motherboard request the immediate command Download Configuration of the
FPGA in the Control Register which triggers the download. The CFIFO
controller reads the FIFO and sends the appropriate clocks and data
string to the FPGA. The VME motherboard may poll the Executing Immediate
Command bit of the Status Register to recognize when the operation is
completed.

To upload the configuration of the FPGA, the VME motherboard uses the
same Configuration/Command FIFO as before. The VME motherboard request
the immediate command Upload Configuration of the FPGA in the Control
Register which triggers the upload. The TFIB controller sends the
appropriate clocks and microcommands. The CFIFO controller reads the
data string and stores the data string into the Configuration/Command
FIFO. The VME motherboard may poll the Executing Immediate Command bit
of the Status Register to recognize when the operation is completed. The
VME motherboard reads the Configuration/Command FIFO to check the
configuration.

We have also implemented the immediate command Reset Configuration of
the FPGA, which allows the VME motherboard to clear the configuration of
the FPGA if the FPGA is not correctly downloaded or if the configuration
is corrupted. Then, the motherboard can re-configure the part. It is
good practice to reset the configuration of the FPGA before downloading
its configuration. Finally, before downloading or uploading any
configuration one should reset the CFIFO, to guarantee that it is empty.
To perform this operation, use the Reset Configuration/Command FIFO bit
of the Configuration/Command FIFO Control/Status register.

The motherboard has to store the configuration bits of the SVX-II chips
into the Command/Configuration FIFO as indicated in Table 1 (C~0~ is
configuration bit 0, etc.).

+-----------------------------------------------------------------------+
| **Data Lines**                                                        |
|                                                                       |
| **D~7~ - - - - - - D~0~**                                             |
+-----------------------------------------------------------------------+
| C~7~ - - - - - - C~0~                                                 |
+-----------------------------------------------------------------------+
| C~13~ - - - - - - C~8~                                                |
+-----------------------------------------------------------------------+
| :                                                                     |
|                                                                       |
| :                                                                     |
|                                                                       |
| :                                                                     |
+-----------------------------------------------------------------------+
| X X C181 \-- C~176~                                                   |
+-----------------------------------------------------------------------+
| C~7~ - - - - - - C~0~                                                 |
+-----------------------------------------------------------------------+
| etc.                                                                  |
+-----------------------------------------------------------------------+

Table 1. Configuration data format SVX-II chips.

Note that the number of bits to download is not a multiple of eight.
Therefore, the last byte have two bits with "don\'t care" information
(X[^2]). Normally, when configuring the SVX-II chips, it is necessary to
download several chips which are connected to the same HDI. Table 1
shows the bits for the first chip, followed by the bits of the second
chip, etc. The configuration bits of the next SVX-II chip start at bit 0
of the next byte. When uploading the configuration, the bits are saved
in the same format.

The configuration bit stream for the FPGA are available in a Motorola S3
format file. The user has to remove the control characters of this
format before storing then into the Configuration/Command FIFO. Three
ZERO bytes (0x0[^3]) have to be append in the end of the configuration.
The comparison of the readback bit stream of the configuration of the
FPGA is not straight forward, because the data does not have the same
format that was downloaded. See the Xilinx manual \[ref. 12\] for more
details or the software drivers developed for this task (see Ref. 12).

## High Level Command Emulation

The TFIB can emulate the high-level commands that it receives from the
STAR/SRC. The VME motherboard stores the commands, one or several
commands, into the Configuration/Command FIFO. The motherboard starts
the emulation by asserting the immediate command Execute Emulation Mode
in the Control Register. The TFIB controller will perform the operations
in the same way it operates when it receives commands from the STAR/SRC.
The VME motherboard may poll the Executing Immediate Command bit of the
Status Register to recognize when all emulated commands were executed.
Note that the bit Executing Real/Emulate Command of the Status Register
will also be asserted.

One of the commands that the TFIB can emulate is the readout of the
SVX-II chips. The Disable G-Links bit in the Control Register disables
the G-Links and forces the data into the Data FIFOs. Normally, the Data
FIFOs are used to synchronize different data paths from the TPC. The VME
motherboard can read this data from the Data FIFOs and check data
consistency. This allows the VME motherboard to read the data from the
SVX chips without the STAR board.

## Data FIFO AB and C

There are a set of three 2K x 8 FIFOs with each FIFO associated with one
HDI. The Data FIFOs are shown in Figure 2. These FIFOs receive data from
the VMEbus or the AT&T receivers and are read by the VMEbus.

The Data FIFOs have two main functions:

-   The primarily function is the synchronization of the data coming
    from different HDIs. The data comes from the TPC in parallel with a
    clock and is stored inside the FIFOs. When all FIFOs have three or
    more words[^4], the data is transmitted through the G-Links.

-   Other functions are associated with the following diagnostic
    operations:

a\) the VME motherboard can download a known data pattern into these
FIFOs and use the G-Links to ship the data to the SAR.

b\) the G-Links may be disabled with the data that comes from the TPC
being read by the VME motherboard instead of being transmitted to the
SAR.

The data from the TPC has the format shown in Table 3 (a). End Of
Readout (EOR) is differentiated from CHIP ID and Channel Number by the
two most significant bits (see Table 2). Further details are provided
within the SVX-II and TPC specifications.

  ------------------------------- ---------------------------------------
  **Control Byte**                **Bit Assignment**

  Chip ID                         10dddddd[^5]

  Channel \#                      0ddddddd

  EOR                             11dddddd
  ------------------------------- ---------------------------------------

Table 2. Control Byte and Bit Assignment

The TFIB board appends the HDI identification number to the beginning of
the data coming from the TPC. This is shown in Table 3 (b).

\(a\) (b)

  ---------------------------- -------------- ----------------------------
  CHIP ID                                     HDI MSB ID

  STATUS                                      HDI LSB ID

  CH \#                                       CHIP ID

  DATA                                        STATUS

  CH \#                                       CH \#

  :                                           DATA

  CHIP ID                                     CH \#

  STATUS                                      :

  CH \#                                       CHIP ID

  :                                           STATUS

  EOR                                         CH \#

                                              :

                                              EOR
  ---------------------------- -------------- ----------------------------

Table 3. Data format (a) from Test Port Card, (b) with HDI ID appended

## G-Link Boards

The present test stand does not require the G-Links. However, in order
to provide a way to further enhance and test the concept of the final
data acquisition system, the TFIB has an interface that allows
connection to G-Link and Finisar transmitters. These G-Link and Finisar
transmitters are assembled on daughter boards which are plugged into the
top of the TFIB \[ref. 8\]. Two of these daughter boards can be
connected to the TFIB. Figure 4 is a diagram of this daughter card.

The implementation of this high speed data link as a self-contained
board makes for greater flexibility of the overall data acquisition
system in view of future upgrades. The daughter card concept permits
convenient independent testing of the high speed communication system.
Maintenance is simplified due to the boards' interchangeability. The
approximate dimensions of this daughter board is 4.5\" x 2\". The SMA
connector allows for the bypassing of the Finisar Laser Diode. For more
information about this interface, refer to the G-Link/Finisar
Transmitter and Receiver Boards specifications \[ref. 9 and 10\].

## Test Port Card Analog to Digital Converters

The TPC has a total of 18 12 bits serial Digital to Analog Converters
(DAC) that control the various reference voltages of the three HDIs. The
TFIB has the DAC Controller which remotely controls the DACs on the TPC.

The VME motherboard writes the Select Code into the DAC Select Register
and the 12 bit value into the DAC Data Register. As soon as the DAC
Controller recognizes that the VME motherboard finished the write to the
DAC Data Register, it initiates the transfer to the TPC. It assembles a
serial stream compose by part of the select code and the data and
transmit to the TPC, in addition with several control signals required.
After the data is properly transferred to the select DAC, the controller
serially uploads the data and stores into the DAC Readback Data
Register. The VME motherboard has to wait for 8 μs before the readback
data is available. Presently, there is no circuit inside the TFIB to
indicate when the readback is done and therefore the VME motherboard has
to use its own resources to count this time.

## Calibration Inject

The Calibration Inject command forces the SVX-II chip to inject charge
into its own pre-amplifiers. The TFIB-CT uses a delay line, programmable
by the VMEbus, to time this command in relation to the acquisition
clock. Figure 5 shows the relationship among the several signals
associated with the calibration inject and the SVX-II data sampling.
Note that, presently, the input of the delay line is timed by the second
raising edge of the master clock (MCLK) after the SYNC pulse.

## Number of Clocks for the SVX II Analog to Digital Converter

The SVX-II chips have an analog-to-digital Gray Code counter, which
counts until it reaches the Counter Module value programmed inside the
configuration parameter bits \[174:167\] of the SVX-II chip. The analog
to digital conversion is completed when the Gray counter reaches the
Counter Module value, and the TFIB can proceed with the readout.
Presently, the TFIB does not have a way to program the number of
digitization clocks to deliver to the Test Port Card. It always delivers
enough clocks to convert the maximum possible value programmed in the
Counter Module register of the SVX-II chip.

# EMBEDDED & DIAGNOSTIC/DEVELOPMENT SOFTWARE

The control and diagnosis of the TFIB and TPC are done through a
MVME162/7 VME motherboard. The TFIB is a slave of this motherboard. This
VME motherboard controls and executes the diagnostic features of the
TFIB. The software is being currently designed. The document "TFIB
Diagnostic Software" describes this software \[ref. 11\].

# INTERFACE SPECIFICATIONS

The TFIB board has the following interfaces, which we will now describe:

-   With the TPC.

-   With the STAR/SRC through the specially designed J3 backplane.

-   With VMEbus through the J1 backplane.

-   With G-Link transmitters to connect with the SAR board during future
    testing.

## VMEbus Interface

The TFIB is a VMEbus slave which implements A24:D16 addressing. Block
transfers are not implemented. Presently, the TFIB does not generate
VMEbus errors neither VMEbus interrupts. The VME interface has the
following characteristics:

-   The TFIB board is always a VMEbus slave. The TFIB board has no VME
    master capability.

-   The VME interface is implemented through the J1 connector.

-   Only a 24 bit addressing scheme is allowed.

-   The VME interface only executes single data transfers.

-   The VME interface allows 16 or 8 bit data transfers.

-   The VME interface does not generate interruptions.

-   The VME interface generates VMEbus errors.

### Addressing Modes

The TFIB is addressed using a 24 bit address mode and the VME Address
Modifiers either 0x29 or 0x39. The base address has a fixed pattern,
encoded inside a programmable logical device (PAL U86 on the
schematics), and a variable one, which depends if the board is connected
to the J3 backplane. We will call Addressing Mode 1 when the board is
connected to the J3 backplane, and Addressing Mode 2 when it is not.

The fixed part of the address encoded inside the PAL is compared with
address lines A\[23:16\] of the VME interface. Presently it is
programmed for pattern 0x10 (we may change if necessary).

If the board is connected to the J3 backplane (Addressing Mode 1), the
address lines A\[15:12\] are compared with the geographic address
supplied by the backplane. Table 4 shows the relationship between
A\[15:12\] and GA\[3:0\]. When the higher order 12 bits of the VME
address, A\[23:12\], compare with the eight PAL bits and with the four
bits GA\[3:0\], the lower address lines A\[11:0\] select one register
inside the TFIB. The TFIB recognizes that it is being addressed by the
VME motherboard and performs the requested action.

  ----------------------------------- -----------------------------------
  **GEOGRAPHIC ADDRESS**              **ADDRESS LINE**

  GA3 (msb)                           A15

  GA2                                 A14

  GA1                                 A13

  GA0                                 A12
  ----------------------------------- -----------------------------------

Table 4. Geographic Address And Address Line Relationships

If the board is *NOT* connected to the J3 backplane (Addressing Mode 2),
the address lines A\[15:12\] are compared with the setting of DIP switch
S2 (see Section 7.1 for position and assignment of this DIP switches).
Table 40 shows the relationship between A\[15:12\] and the position of
the DIPs. Bits are set to zero by having the switch in the on position.
Bits are set to one by having the switch in the off position. When the
higher order 12 bits of the VME address, A\[23:12\], compare with the
eight PAL bits and A\[15:12\] with the four DIP switch positions, the
lower address lines A\[11:0\] select one register inside the TFIB. The
TFIB recognizes that it is being addressed by the VME motherboard and
performs the requested action.

### Data Cycles Types

The TFIB only implements 8 and 16 bit single data transfers. The TFIB
does not use the signal lines on the J2 connector and does not have
block transfer capability. The following contains a description of each
TFIB register.

### VME Register Descriptions

Table 5 shows the VME registers and associated information.

  --------------------------- ---------- --------------- --------------------
  **REGISTER**                **TYPE**   **OPERATION**   **ADDRESS**

  Status                      byte[^6]   read only       Base Address + 0x00

  Status Latch                byte       read only       Base Address + 0x02

  Control Low[^7]             byte       read/write      Base Address + 0x04

  Control High                byte       read/write      Base Address + 0x06

  Spare                                                  

  HDI Address                 byte       read/write      Base Address + 0x0A

  Conf/Cmd FIFO               byte       read/write      Base Address + 0x0C
  Control/Status                                         

  Number of Chips/HDI         byte       read/write      Base Address + 0x0E

  Conf/Cmd FIFO               9 bits     read/write      Base Address + 0x10

  G-Link Control/Status       byte       write/read      Base Address + 0x12

  Data FIFOs Control/Status   byte       write/read      Base Address + 0x14

  HDI_AB Identification LSB   word       read/write      Base Address + 0x16

  HDI_AB Identification MSB   word       read/write      Base Address + 0x18

  HDI_C Identification LSB    byte       read/write      Base Address + 0x1A

  HDI_C Identification MSB    byte       read/write      Base Address + 0x1C

  HDI_AB Contents             word       read only       Base Address + 0x1E

  HDI_C Contents              byte       read only       Base Address + 0x20

  HDI Enabled                 byte       read/write      Base Address + 0x22

  Data FIFO AB                word       read/write      Base Address + 0x24

  Data FIFO C                 byte       read/write      Base Address + 0x26

  Silo FIFO                   9 bits     read only       Base Address + 0x28

  Silo FIFO Control/Status    byte       read/write      Base Address + 0x2A

  SVX-II Pipeline Reset Time  byte       write only      Base Address + 0x2C

  Calibration Inject Delay    byte       write only      Base Address + 0x2E
  Line                                                   

  Spare                                                  Base Address + 0x30

  VME Control/Status          byte       read/write      Base Address + 0x32
  (N.I.)[^8]                                             

  DAC Data                    word       read/write      Base Address + 0x34

  DAC Select                  byte       write/write     Base Address + 0x36

  DAC Readback Data           word       read only       Base Address + 0x38
  --------------------------- ---------- --------------- --------------------

Table 5. VME Registers

#### Status Register

Table 6 provides the Status Register bit assignment.

  ------------------- ---------------------------------------------------
  **BIT NUMBER**      **MEANING**

  7                   not used[^9]

  6                   Real/Emulate State Machine \[3\]

  5                   Real/Emulate State Machine \[2\]

  4                   Real/Emulate State Machine \[1\]

  3                   Real/Emulate State Machine \[0\]

  2                   Executing Real/Emulate Command

  1                   Executing Immediate Command

  0                   Real command source: J3 =\> 0, Front Panel =\> 1
  ------------------- ---------------------------------------------------

Table 6. Status Register

**Real/Emulate State Machine \[3:0\]:** Indicates the state of the state
machine which controls the execution of real/emulate commands. Table 7
describes the state assignment. Note that read pipeline/digitize/readout
is controlled by another state machine, not accessible through the
Status register.

  ------------------------- ---------------------------------------------
  **STATE NUMBER**          **MEANING**

  10                        G-Link send fill frames

  9                         Port Card controller reset

  8                         TFIB reset

  7                         SVX chip reset

  6                         Start preamplifier reset

  5                         Enter in data sampling mode phase 1

  4                         Enter in data sampling mode phase 0

  3                         Stop preamplifier reset

  2                         Calibration inject phase 1

  1                         Calibration inject phase 0

  0                         Idle
  ------------------------- ---------------------------------------------

Table 7. State assignment for the Real/Emulate State Machine

**Executing Real/Emulate Command:** when set to ONE, the TFIB-CT is
executing a Real command.

**Executing Immediate Command:** when set to ONE, the TFIB-CT is
execution an Immediate Command.

**Real command source:** This bit allows the readout of the position of
the first switch of DIP switch S1 which selects the source of Real
commands (see Section 7.1). When this bit is ZERO, the TFIB receives
Real commands through the J3 backplane, when it is ONE, it receives Real
commands through the front panel.

#### Status Latch

The Status latch is a byte wide latch which is used for diagnostic
purposes. When the TFIB controller executes the Latch Status command
(see Section 4.2.3), the Status Latch saves the contents of the Status
Register. The VME motherboard can read this register. The Status latch
is not resetable and have the same bit assignment of the Status Register
(see Table 6, Status Register).

#### Control Low Register 

Table 8 gives the bit assignment for Control Low register.

  ------------------ ----------------------------------------------------
  **BIT NUMBER**     **MEANING**

  7                  TFIB reset

  6                  53 MHz clock source: 0 =\> external, 1 =\> internal

  5                  Disable Real Commands

  4                  Execute immediate command

  3                  Immediate command \[3\]

  2                  Immediate command \[2\]

  1                  Immediate command \[1\]

  0                  Immediate command \[0\]
  ------------------ ----------------------------------------------------

Table 8. Control Low Register

**TFIB reset:** When this bit is set to one, it resets the TFIB. It is a
volatile bit, nad has no meaning when readout out by VME motherboard.

**53 MHz clock source:** This bit selects the source of the 53 MHz clock
for the TFIB. In order to change the 53 MHz source and guarantee that
the TFIB will work properly, the VME motherboard has to execute the
following sequence:

a)  The TFIB should not be executing any Immediate command.

b)  Disable Real commands.

c)  Check if all Real commands are done (bit Executing Real/Emulate
    Commands of the Status Register has to be zero).

d)  Change the clock source

DIP Switch S1 selects the source of external clock: the front panel or
the J3 backplane (see Section 7.1 for position and assignment of this
DIP switch).

**Disable Real Commands:** When set to ONE, this bit disables the
external commands and, therefore, the TFIB ignores all commands from the
STAR/SRC. It may happen that, when the Real commands are disabled, the
TFIB is still executing a Real command whose execution started prior the
disabling. Therefore, the VME motherboard should check the Executing
Real command bit of the Status Register to know when the TFIB is idle.

**Execute immediate command:** When this bit is set to one, the TFIB
executes the immediate command. It is a volatile bit, and has no meaning
when readout by VME motherboard. To execute Immediate commands, the Real
commands have to be disabled and not in execution.

**Immediate command \[0:3\]:** The Immediate commands are encoded into
bits 0 to 3 of the Control Register. Table 9 shows the Immediate command
codes ICMD\[0:3\]. Codes 9 to 0xF are not presently used.

  -------------------- --------------------------------------------------
  **ICMD\[0:3\]**      **MEANING**

  8                    Reset SVX-II chips

  7                    Erase configuration of the FPGA

  6                    Reset Port Card controller

  5                    Download/upload configuration of the SVX-II chips

  4                    Upload configuration of the FPGA

  3                    Download configuration of the FPGA

  2                    G-Link transmit Fill Frames

  1                    Execute Emulation mode

  0                    No operation
  -------------------- --------------------------------------------------

Table 9. Immediate Command Codes

The TFIB-CT uses the Executing Immediate Command of the Status register
to inform the VME motherboard when the operation is completed.

#### Control High Register 

Table 10 gives the bit assignment for Control High register.

  --------------------------- -------------------------------------------
  **BIT NUMBER**              **MEANING**

  7                           not used

  6                           not used

  5                           not used

  4                           not used

  3                           not used

  2                           not used

  1                           not used

  0                           Silo FIFO store disable
  --------------------------- -------------------------------------------

Table 10. Control High Register

**Silo FIFO store disable:** When set to one, the store of Real commands
inside the Silo FIFO is disabled. The Silo FIFO also can be
automatically disable (and this bit is automatically set to ONE) when
the TFIB executes the Real command Latch Status.

#### High Density Interconnect Address Register

Table 11 shows the HDI Address Register bit assignments.

  ---------------- ---------------- -------------------------------------
  **Bit 1**        **Bit 0**        **HDI selected**

  0                0                all

  0                1                A

  1                0                B

  1                1                C
  ---------------- ---------------- -------------------------------------

Table 11. HDI Address Register

This register is used to select the proper hybrid which is connected to
one HDI. There can be three HDIs connected to one TPC. Certain
operations are associated with specific HDIs as in the case of the
specific HDI used to configure the SVX-II chips. This register is only
used in immediate mode. Bits \[2:7\] are not used.

#### Configuration/Command FIFO Control/Status Register

Table 12 shows the bit assignment of the Configuration/Command FIFO
Control/Status Register.

  --------------------- -------------------------------------------------
  **BIT NUMBER**        **MEANING**

  7                     not used

  6                     not used

  5                     not used

  4                     not used

  3                     not used

  2                     Configuration/command FIFO Flag 2

  1                     Configuration/command FIFO Flag 1

  0                     Reset Configuration/command FIFO
  --------------------- -------------------------------------------------

Table 12. Conf./Com. FIFO Control/Status

**Configuration/Command FIFO Flag 1 and 2:** See Table 13. Note that
this flags may change during a VME read, if the Configuration/Command
FIFO is in use.

  -------------- -------------- ------------------------------------------
  **FLAG 1**     **FLAG 2**     **STATE**

  0              0              Empty

  1              0              Almost empty: 1 to 16 bytes

  1              1              Intermediate range: 17 to 2031 bytes

  0              1              Almost full or full: 2032 to 2048 bytes
  -------------- -------------- ------------------------------------------

Table 13. FIFO Flag True Table

**Reset Configuration/Command FIFO:** When set to one, the
Configuration/command FIFO is reseted. In order to guarantee the reset,
the TFIB can not be executing commands associated with the
Configuration/command FIFO, i.e., executing emulating commands or
configuring the SVX-II chips or FPGA. It is a volatile bit and is not
readable.

#### Number of SVX-II Chips Connected to HDI Register

The number of SVX-II chips per HDI is programmed in this register. This
information is used to download/upload the configuration of the SVX-II
chips. Bits No.Chips/HDI\[0:4\] is a binary code, programmed from 0 to
31 chips. Zero means one chip, while 31 means 32 chips. Therefore, this
register should be loaded with the number of chips minus one. Note that
this register should be programmed before any download/upload operation
can be executed. Table 14 shows the bit assignment.

  --------------------- -------------------------------------------------
  **BIT NUMBER**        **MEANING**

  7                     not used

  6                     not used

  5                     not used

  4                     No.Chips/HDI \[4\] MSB

  3                     No.Chips/HDI \[3\]

  2                     No.Chips/HDI \[2\]

  1                     No.Chips/HDI \[1\]

  0                     No.Chips/HDI \[0\]
  --------------------- -------------------------------------------------

Table 14. Number of Chips/HDI Register

#### Configuration/Command FIFO

The Configuration/Command FIFO is a 2K x 9 FIFO which is used for
configuration and the emulation of commands. Table 15 shows the bit
assignment of this FIFO when it is used for emulation commands.

  -------------------------------- --------------------------------------
  **BIT NUMBER**                   **MEANING**

  8                                spare 2

  7                                spare 1

  6                                BXING[^10]

  5                                AD_PIPE

  4                                CMD\[4\]

  3                                CMD\[3\]

  2                                CMD\[2\]

  1                                CMD\[1\]

  0                                CMD\[0\]
  -------------------------------- --------------------------------------

Table 15. Conf./Com. FIFO assignment for Emulation commands

Section 2.2 provides further information about the format of the data
when this FIFO is used for configuration of the TPC controller (a FPGA)
or the SVX-II chips.

Due to the simplicity of the VME interface being used, the following
procedure is recommended to read the FIFOs:

a\) Check if the FIFO is empty by reading the Status/Control Register.

b\) If the FIFO is empty, the readout is done.

c\) If the FIFO is not empty, read one more byte.

d\) Go to step (a).

#### G-Link Control/Status Register

The G-Link transmitter supplies status information. This information is
shown in Table 16 and is readable through the G-Link Status Register.

  --------------------- -------------------------------------------------
  **BIT NUMBER**        **MEANING**

  7                     not used

  6                     not used

  5                     not used

  4                     G-Links transmit DFIFOs DONE

  3                     G-Links transmit DFIFOs

  2                     Disable G-Links

  1                     G-Link_1, Locked

  0                     G-Link_0, Locked
  --------------------- -------------------------------------------------

Table 16. G-Link Status Register

**G-Link_0 and \_1 Locked:** This is a read only bit. It indicates the
lock status of the transmitter's PLL. A ONE indicates lock. This signal
has to be debounced by the VME motherboard through several reads.

**Disable G-Links:** This is a read/write bit. When set to one, disable
the G-Links, forcing the SVX-II data to stay into the Data FIFOs.

**G-Links Transmit DFIFOs:** When set to one, the DFIFO-CT transmit the
contents of the DFIFOs through the G-links. This is a volatile bit, and
is not readable.

**G-Links Transmit DFIFOs DONE:** This bit is set to ONE when the
transmission of the content of the DFIFOs by the G-links is done. It is
a read only bit, it does not change when the VME motherboard writes to
this register.

#### Data FIFOs Control/Status Register

This register allows the VME motherboard to read the status and reset
the three Data FIFOs. Table 17 shows the bit assignment of this
register.

  --------------------- -------------------------------------------------
  **BIT NUMBER**        **MEANING**

  7                     not used

  6                     Data FIFO_C Flag 2

  5                     Data FIFO_C Flag 1

  4                     Data FIFO_B Flag 2

  3                     Data FIFO_B Flag 1

  2                     Data FIFO_A Flag 2

  1                     Data FIFO_A Flag 1

  0                     Reset Data FIFOs
  --------------------- -------------------------------------------------

Table 17. Data FIFOs Status Register

**Reset Silo FIFO:** When set to one, the Data FIFOs are reseted. In
order to guarantee the reset, the Data FIFOs should be idle. It is a
volatile bit and is not readable.

**Silo FIFO Flag 1 and 2:** See Table 13 for the meaning of flags 1 and
2 associated with the FIFOs. Note that this flags may change during a
VME read, if the Data FIFOs are in use.

#### HDI_AB Identification LSB Register

The value of this 16 bit register is appended to the beginning of the
data read out from the TPC. They are the least significant bytes (LSB)
of the HDI identification number for the A and B HDI and are
programmable by the VME motherboard. The bit assignment is shown in
Table 18.

  ----------------------------------- -----------------------------------
  **HDI Ident.**                      **Data Lines**

  B                                   D\[15:8\]

  A                                   D\[7:0\]
  ----------------------------------- -----------------------------------

Table 18. HDI_AB Identification LSB Register

#### HDI_AB Identification MSB Register

The value of this 16 bit register is appended to the beginning of the
data read out from the TPC. They are the most significant bytes (MSB) of
the HDI identification number for the A and B HDI and are programmable
by the VME motherboard. The bit assignment is shown in Table 19.

  ----------------------------------- -----------------------------------
  **HDI Ident.**                      **Data Lines**

  B                                   D\[15:8\]

  A                                   D\[7:0\]
  ----------------------------------- -----------------------------------

Table 19. HDI_AB Identification MSB Register

#### HDI_C Identification LSB Register

The value of this 8 bit register is appended to the beginning of the
data read out from the TPC. They are the least significant byte (LSB) of
the HDI identification number for the C HDI and are programmable by the
VME motherboard. The bit assignment is shown in Table 20.

  ----------------------------------- -----------------------------------
  **HDI Ident.**                      **Data Lines**

  C                                   D\[7:0\]
  ----------------------------------- -----------------------------------

Table 20. HDI_C Identification LSB Register

#### HDI_C Identification MSB Register

The value of this 8 bit register is appended to the beginning of the
data read out from the TPC. They are the least significant byte (MSB) of
the HDI identification number for the C HDI and are programmable by the
VME motherboard. The bit assignment is shown in Table 21.

  ----------------------------------- -----------------------------------
  **HDI Ident.**                      **Data Lines**

  C                                   D\[7:0\]
  ----------------------------------- -----------------------------------

Table 21. HDI_C Identification MSB Register

#### HDI_AB Contents Register

When the VME motherboard reads this register, the TFIB sets on the VME
data bus the actual bit pattern of HDIs A and B. Table 22 shows the bit
assignment of this register.

  ----------------------------------- -----------------------------------
  **HDI Contents**                    **Data Lines**

  B                                   D\[15:8\]

  A                                   D\[7:0\]
  ----------------------------------- -----------------------------------

Table 22. HDI_AB Content Register

#### HDI_C Contents Register

When the VME motherboard reads this register, the TFIB sets on the VME
data bus the actual bit pattern of HDI C. Table 23 shows the bit
assignment of this register.

  ----------------------------------- -----------------------------------
  **HDI**                             **Data Lines**

  C                                   D\[7:0\]
  ----------------------------------- -----------------------------------

Table 23. HDI_C Content Register

#### HDI Enable Register

The TFIB can be connected up to three HDIs. This register allows the VME
motherboard to enable the input circuitry associated with the HDI that
are connected by setting the appropriate bit to ONE. Also, note that in
case of failure of one HDI, this register can also be used to disable
that specific part of the circuit. Table 24 shows the bit assignment of
this register.

  --------------------- -------------------------------------------------
  **BIT NUMBER**        **MEANING**

  7                     not used

  6                     not used

  5                     not used

  4                     not used

  3                     not used

  2                     Enable HDI C

  1                     Enable HDI B

  0                     Enable HDI A
  --------------------- -------------------------------------------------

Table 24. HDI Enable Register

#### Data FIFO_AB

These are two 2K x 8 FIFOs with each FIFO associated with HDI A and HDI
B. Their primary use is the synchronization of the data coming from
different HDIs. These two FIFOs are connected to the Data FIFO_AB
Register as a 16 bit word. Table 25 provides further details on these
two FIFOs.

  ----------------------------------- -----------------------------------
  **HDI Ident.**                      **Data Lines**

  B                                   D\[15:8\]

  A                                   D\[7:0\]
  ----------------------------------- -----------------------------------

Table 25. Data FIFO AB

The G-Links can be disabled with the Disable G-Link bit of the Control
Register. In this case, all data from the TPC are stored inside these
data FIFOs. The format of the data is the same as the data readout from
the SVX-II chips but with HDI identification appended to the beginning
of the data as shown in Table 2.

Due to the simplicity of the VME interface being used, the following
procedure is recommended to read the FIFOs:

a\) Check if the FIFO is empty by reading the Data FIFO Status/Control
Register.

b\) If the FIFO is empty, the readout is done.

c\) If the FIFO is not empty, read one more word.

d\) Go to step (a).

#### Data FIFO_C

This is a 2K x 8 FIFO associated to HDI C. Its primary use is the
synchronization of the data coming from different HDIs. This third FIFO
is connected to Data FIFO C Register as a 8 bit byte. Table 26 provides
further details on this FIFO.

  ----------------------------------- -----------------------------------
  **HDI Ident.**                      **Data Lines**

  C                                   D(0:7)
  ----------------------------------- -----------------------------------

Table 26. Data FIFO C

Due to the simplicity of the VME interface being used, the following
procedure is recommended to read the FIFOs:

a\) Check if the FIFO is empty by reading the Status/Control Register.

b\) If the FIFO is empty, the readout is done.

c\) If the FIFO is not empty, read one more byte.

d\) Go to step (a).

#### Silo FIFO

The Command Silo FIFO is a 9 bits wide 2K FIFO used for diagnostic
purposes. The bit assignment of this FIFO is the same as the
Configuration/Command FIFO when it is used to emulate commands (see
Table 15).

All REAL MODE commands executed by the TFIB are stored in this FIFO.
When it gets full, the older commands are removed from the FIFO. The VME
motherboard can read this register for diagnostic purposes. The Silo
FIFO is not resetable by the TFIB Reset command or the TFIB Reset bit in
the Control register. When the TFIB executes the Latch Status command,
it disable any further stores inside the Silo FIFO. The VME motherboard
has to reset the Silo FIFO Store Disable bit in the Control register in
order to enable again the store.

Due to the simplicity of the VME interface being used, the following
procedure is recommended to read the FIFOs:

a\) Check if the FIFO is empty by reading the Status/Control Register.

b\) If the FIFO is empty, the readout is done.

c\) If the FIFO is not empty, read one more byte.

d\) Go to step (a).

#### Silo FIFO Control/Status Register

Table 27 shows the bit assignment of this register.

  --------------------- -------------------------------------------------
  **BIT NUMBER**        **MEANING**

  7                     not used

  6                     not used

  5                     not used

  4                     not used

  3                     not used

  2                     Silo FIFO Flag 2

  1                     Silo FIFO Flag 1

  0                     Reset Silo FIFO
  --------------------- -------------------------------------------------

Table 27. Silo FIFO Control/Status

**Reset Silo FIFO:** When set to one, the Silo FIFO is reseted. In order
to guarantee the reset, the Silo FIFO has to be disabled. It is a
volatile bit and is not readable.

**Silo FIFO Flag 1 and 2:** See Table 13.

#### SVX-II Pipeline Reset Time Register

This register programs the pipeline reset pulse width of the acquisition
clock of the SVX-II chip. When it is set to ZERO, the reset pulse width
is 19 ns, when it is set to 15, the reset pulse width is 34 ns. This
register\'s bits are shown in Table 28.

  --------------------- -------------------------------------------------
  **BIT NUMBER**        **MEANING**

  7                     not used

  6                     not used

  5                     not used

  4                     not used

  3                     Pipeline reset time \[3\] MSB

  2                     Pipeline reset time \[2\]

  1                     Pipeline reset time \[1\]

  0                     Pipeline reset time \[0\]
  --------------------- -------------------------------------------------

Table 28. SVX-II Preamp Speed Register

#### Calibration Inject Delay Line Register

This register allows the VME motherboard to define the time relationship
between the SVX-II acquisition clock and the calibration inject pulse.

Figure 5 shows the relationship between clock, SYNC pulse, SVX-II
Acquisition clock and the trigger of the delay line TFIB controller
triggers this delay line. When the delay expires, the TFIB controller
sends a calibration inject pulse to the Port Card Controller. The delay
is programmed from 5 ns to 315 ns, with increments of 5 ns. Table 29
shows the bit assignment of this register.

  --------------------- -------------------------------------------------
  **BIT NUMBER**        **MEANING**

  7                     not used

  6                     not used

  5                     Calibration Inject Delay \[5\]

  4                     Calibration Inject Delay \[4\]

  3                     Calibration Inject Delay \[3\]

  2                     Calibration Inject Delay \[2\]

  1                     Calibration Inject Delay \[1\]

  0                     Calibration Inject Delay \[0\]
  --------------------- -------------------------------------------------

Table 29 Calibration Delay Line

#### VME Control/Status Register (Not Implemented)

This register indicates which unit generated the VME bus error. Table 30
shows its bit assignment.

  ---------------------- ------------------------------------------------
  **BIT NUMBER**         **MEANING**

  7                      not used

  6                      not used

  5                      not used

  4                      DACs controller bus error

  3                      Conf/Cmd FIFO controller bus error

  2                      Data FIFO controller bus error

  1                      TFIB controller bus error

  0                      Reset bus errors status
  ---------------------- ------------------------------------------------

Table 30. VME Status/Control Register

**Reset bus error status:** When set to ONE, the bus error bits of this
register are reseted. This is a volatile bit, and is not readable.

#### DAC Data Register

This register is used to specify the data to be downloaded to the DAC
selected by the DAC Select register. The TPC uses 12 bit DACs and they
correspond to VME data bits 11 to 0. The programming of a selected DAC
is initiated as soon as the VME write operation to the DAC Data register
is completed.

#### DAC Select Register 

The DAC Select register is used to specify the DAC that will be
programmed by the logic on the TFIB. The DAC assignment is shown on
Table 31.

  ----------------------------------- -----------------------------------
  **DAC Select CODE**                 **Data Selected**

  0x00                                HDI-A Calibration φ

  0x01                                HDI-A Calibration z

  0x02                                HDI-A Ramp Ref. φ

  0x03                                HDI-A Ramp Ref. z

  0x04                                HDI-A Ramp Ped. φ

  0x05                                HDI-A Ramp Ped. z

  0x08                                HDI-B Calibration φ

  0x09                                HDI-B Calibration z

  0x0a                                HDI-B Ramp Ref. φ

  0x0b                                HDI-B Ramp Ref. z

  0x0c                                HDI-B Ramp Ped. φ

  0x0d                                HDI-B Ramp Ped. z

  0x10                                HDI-C Calibration φ

  0x11                                HDI-C Calibration z

  0x12                                HDI-C Ramp Ref. φ

  0x13                                HDI-C Ramp Ref. z

  0x14                                HDI-C Ramp Ped. φ

  0x15                                HDI-C Ramp Ped. z
  ----------------------------------- -----------------------------------

Table 31. DAC Select Code

#### DAC Readback Data Register.

This register is used to store the DAC data transmitted by the TPC
everytime that a DAC is downloaded. Under proper operation, the contents
of this register must match the data stored on the DAC Data Register.
Note that the transmission of data from the TFIB to the TPC and from the
TPC to the TFIB are serial and enough time (more than 8 μs) should be
allowed for the Readback register to have to correct data.

## STAR/SRC Interface

The STAR/SRC communication is done through the J3 backplane of the VME
crate or a connector on the front panel of the TFIB. The J3 backplane
was designed by Fermilab's D0 and has more lines available than the TFIB
requires.

The next sections describe the electrical and logical protocol of this
interface.

### J3 Backplane Control Connector

The following is a short description of the J3 backplane STAR/SRC
interface signals that the TFIB will use. For further details, refer to
specific documentation \[ref. 4\].

• Fan out the 53 MHz differential ECL clock signal named MCLK.

• Fan out a 18.9 ns wide, 132 ns period, \"SYNC\" pulse in differential
ECL.

• Command(4:0) named CMD\[4:0\] which are bussed TTL level signals.

• Advance-Pipeline named AD-PIPE and Beam Crossing named BXING (no
presently used) which are TTL level signals.

• Provide for geographic addressing of the TFIB Modules. These lines are
connected to ground and require pull-up resistors.

• Provide +5.0 Vdc, -5.2 Vdc, and Ground.

• Provide a \"MAC 2\" fiber optic backplane connector for future use.

Table 32 shows the pin assignment of the J3 VME backplane connector.
Table 33 gives the correspondence between Geographic Address and VME
slot number.

  ----------------- ----------------- ----------------- -----------------
  **PIN NUMBER**    **ROW A**         **ROW B**         **ROW C**

  1                 GND               GND               J-MCLK

  2                 GND               GND               J-MCLK\*

  3                 GND               GND               J-SYNC

  4                 GND               -5.2V             J-SYNC\*

  5                 GND               NC[^11]           -5.2V

  6                 GND               NC                -5.2V

  7                 +5V               NC                -5.2V

  8                 +5V               J-AD-PIPE         -5.2V

  9                 +5V               J-BXING           -5.2V

  10                +5V               NC                -5.2V

  11                +5V               NC                J-CMD0

  12                +5V               NC                J-CMD1

  13                GA3               NC                J-CMD2

  14                GA2               NC                J-CMD3

  15                GA1               NC                J-CMD4

  16                GA0               NC                NC
  ----------------- ----------------- ----------------- -----------------

Table 32. J3 backplane pin assignment

  ----------------------------------- -----------------------------------
  **SLOT NUMBER**                     **GA\[0:3\]**

  6                                   0

  7                                   1

  :                                   :

  20                                  0xE

  21                                  0xF
  ----------------------------------- -----------------------------------

Table 33. Geographic address and VME slot number

### Front Panel Control Connector

The front panel Control connector uses a 20 pin 100 mils spacing
connector. The electrical protocol is differential positive ECL provided
by AT&T receivers. It is differentially terminated by 100 ohm resistors.
Table 34 shows the pin assignment. The TFIB employs a jumper (J13) to
open the ground, in case is necessary to avoid ground loops.

  ------------------------------------------- ---------------------------
  **Pin number**                              **signal**

  1                                           F-CMD0\*

  2                                           F-CMD0

  3                                           F-CMD1\*

  4                                           F-CMD1

  5                                           F-CMD2\*

  6                                           F-CMD2

  7                                           F-CMD3\*

  8                                           F-CMD3

  9                                           F-CMD4\*

  10                                          F-CMD4

  11                                          F-AD-PIPE\*

  12                                          F-AD-PIPE

  13                                          F-BXING[^12]\*

  14                                          F-BXING

  15                                          F-SYNC\*

  16                                          F-SYNC

  17                                          F-MCLK\*

  18                                          F-MCLK

  19                                          GND

  20                                          GND
  ------------------------------------------- ---------------------------

Table 34. Front Panel Command Connector Assignment

### Command Protocol

The commands that the STAR/SRC sends to the TFIB controller are
associated with the modes of operation of the SVX-II chip and the data
acquisition. These commands are sent in parallel with the SYNC line. A
zero-to-one transition in the SYNC line validates the commands. Table 35
lists the code assignment of these commands.

  --------------------- -------------------------------------------------
  **CODE**              **MEANING**

  0x15                  G-Links send Fill Frames

  0x14                  Reset TPC Controller

  0x13                  Reset TFIB

  0x12                  Reset SVX-II chip

  0x11                  Latch status

  9                     Calibration inject

  8                     Stop data sampling clocks

  5                     Read-pipeline/Digitize/Readout

  4                     Preamplifier start reset

  3                     Enter in data sampling mode

  2                     Preamplifier stop reset

  0                     No operation
  --------------------- -------------------------------------------------

Table 35. Real and Emulation Mode Code Assignment

Commands 0x12, 0x13, and 0x14 set the SVX-II chip, the TFIB, and the TPC
into known states. Command 0x12 does not re-configure the SVX-II chips
but sets the SVX-II chips to a known state (specifically, to the data
sampling mode, but no SVX-II acquisition clock is delivered). Command
0x15 forces the G-Link transmitter to send fill frames to allow the
G-Link receiver on the SAR to regain lock. Command 0x11 is used for
diagnostic purposes (see Section 4.1.3.2). The commands that are not
listed have the same behavior as No Operation but may be used in future
upgrades and should be considered RESERVED.

The STAR/SRC forwards these commands and signals every 132 ns.
CMD\[4:0\] and AD-PIPE are validated by the SYNC pulse and change half
way between SYNC pulses as is shown in Figure 6.

The TFIB-CT can *NOT* execute more than one command at a time as the
TFIB-CT does not have pipeline capability. After the STAR/SRC sends a
command, the STAR/SRC has to wait until the end of the execution of this
command, which can take several multiples of 132 ns. However, this rule
has exceptions that we will now describe:

a)  the Latch Status and Stop Data Sampling Clocks command can be sent
    when another command is in execution.

b)  the execution of Preamplifier Start Reset and Preamplifier Stop
    Reset commands takes more than 132 ns (see Table 36), and is
    normally issue during data sampling mode. However, during data
    sampling, after the STAR/SRC issued one of these commands, a trigger
    may arrive. In this case, the STAR/SRC does not need to wait until
    the completition of the Preamplifier Start or Stop Reset. The
    STAR/SRC can issue the Read-Pipeline/Digitize/Readout command right
    after the Preamplifier Start or Stop Reset commands.

The number of SYNC pulses to execute different SVX-II operations,
including the one used to validate the command, are listed in Table 36.
The operation Read-pipeline/digitize /readout is not listed because the
TPC supplies the EOR control byte to inform when the operation is
completed.

  ----------------------------------- -----------------------------------
  **OPERATION**                       **NUMBER OF SYNC PULSES**

  Reset TPC Controller                10

  Reset TFIB                          300 ms[^13]

  Reset SVX-II chip                   6

  Latch status                        1

  Calibration inject (minimum)        6

  Calibration inject (maximum)        8

  Stop data sampling clocks           1

  Preamplifier start reset            4

  Enter in data sampling mode         7

  Preamplifier stop reset             2
  ----------------------------------- -----------------------------------

Table 36. Number of SYNC pulse to execute different SVX-II operations

## Test Port Card Interface

The TPC receives microcommands from the TFIB through the Serial-Clock
(SR-CLK) and Serial Microommand (SR-CMD) lines. These microcommands when
executed perform specific operations on the SVX-II chips.

Sequencer microcommands are executed by sending the microcommand and
then a specific number of clocks to cycle the sequencer through its
states. The state of the SVXII control lines is determined by the
sequencer state and the timing between states is determined by the time
between clocks. The TPC will not except another microcommand until the
previous command is completed.

The electrical communication is accomplished by several sets of
differential Positive ECL (PECL) lines which are driven by AT&T chips.
There are several spare AT&T transmitters connected between the TFIB and
TPC. These lines are implemented for future use and are not currently
used. Data is received from the TPC from eight data lines in parallel
with the SVX-II clock. Further information about the TPC interface is
contained in the Test Port Card documentation \[ref. 3\].

## G-Link Interface

The electrical interface between the G-Link and the TFIB is described in
G-Link/Finisar Transmitter and Receiver Boards specification \[ref. 9
and 10\]. The data being read out from two hybrids are combined into one
G-Link transfer as is shown in the example of Table 37.

  ----------------------------------- -----------------------------------
  **HDI \# x**                        **HDI \# y**

  HDI MSB ID                          HDI MSB ID

  HDI LSB ID                          HDI LSB ID

  CHIP ID                             CHIP ID

  STATUS                              STATUS

  CH \#                               CH \#

  DATA                                DATA

  CH \#                               CH \#

  :                                   :

  CHIP ID                             CH \#

  STATUS                              DATA

  CH \#                               CH \#

  :                                   DATA

  CH \#                               EOR

  DATA                                XXX

  EOR                                 XXX
  ----------------------------------- -----------------------------------

Table 37. G-Link or Data FIFO data format

The data of two HDIs are transferred at a rate of 53 MHz per word with a
word being 16 bits. The data transmitted has appended a HDI
identification word, the MSB ID, and LSB ID. These two bytes correspond
to two bytes used to identify the source of the data packet. EOR is
flagged independently on each HDI data packet by asserting bits 6 and 7
of the data byte (see Table 2). The Data FIFO AB and C Section provides
further explanation on this topic. The EOR is inserted by the TPC
controller as soon as it recognizes that the last SVX-II chip of the HDI
is done transmitting its data. The readout data from one HDI can finish
before the other, and then we have unknown data (X's on the Table) being
asserted in that HDI. The HDI data packet is formed by an even number of
bytes.

The outputs of the Finisar LEDs are connected to MAC-II connectors
through short fiber optic links which are assembled as part of the J3
Backplane. This is shown in Figure 8.

## Front Panel

Figure 7 shows the front panel of the TFIB.

# RESET, POWER UP RESET & INITIALIZATIONS,

The TFIB is reseted as the result of four different actions:

-   Power up

-   Press the reset button on the front panel

-   The execution of the Real/Emulate command Reset TFIB

-   The VME motherboard asserts the TFIB Reset bit of the Control
    Register.

All registers and FIFOs are reseted as a result of these actions, with
three exceptions: the Status and Status Latch registers, as well as the
Silo FIFO. These units are associated with diagnostic features of the
TFIB, which we keep the information intact for future examination.
Therefore, if for some reason the TFIB is not operating properly, the
user can execute some of these resets, and then examine the registers.
Of course, on power up, the content of the Silo FIFO is unknown, and the
VME motherboard has to specifically reset it to guarantee that it is
empty.

Below, we describe some procedures to assist the setup of the TFIB:

1.  If the TFIB is not connect to an external Master Clock (MCLK)
    through the J3 backplane or front panel, it will not operate until
    the internal MCLK is enabled. For this, the user has to set to ONE
    the 53 MHz Clock Source bit of the Control Register. Note that after
    reset this bit is logical level ZERO.

2.  To execute Immediate Commands, the Real Commands have to be
    disabled. Therefore, bit Disable Real Commands of the Control
    Register has to be set to ONE. After reset, this bit is logical
    level ZERO, and the Real commands are enabled.

3.  The Silo FIFO is enabled after reset.

4.  The FIFOs should be reset before they are used. This guaranties that
    they are empty. However, there is no need to do this when the TFIB
    reads out data from the SVX chips. The Data FIFOs are automatically
    reset by the DFIFO Controller before it stores the data into the
    Data FIFOs.

5.  The VME motherboard should employ a timeout, when it is reading out
    data from the SVX chips. The TFIB has no internal timeout to detect
    the absence of End Of Readout (EOR), and it will continue sending
    readout clocks until the VME motherboard aborts the operation.

# DIAGNOSIS

Diagnostic features are an important part of this system. There are
several methods to test and check the proper behavior of the TFIB. As an
example, the TFIB can operate in Emulation Mode independent of the
STAR/SRC. Also, the TFIB can read back the configuration of the SVX-II
chips. The use of the test stand will point out new procedures to
diagnose the TFIB and associated electronics.

The calibration mode is a powerful diagnostic method of the test stand.
The calibration mode produces a known set of data which can be used to
test the various inputs of the SVX-II chips as well as the overall test
stand at maximum frequency. It is necessary to provide means to
separately test the various facilities of the test stand. The following
is a description of these tests.

## Diagnosis of the TFIB and TPC

The focus of the proposed diagnostic method is to test the various units
associated with the TFIB and TPC. These associated units are the
following:

-   The TPC controller.

-   The SVX-II chips.

-   The cables.

-   The AT&T drivers and receivers.

-   The HDI cables.

The following is a description of these tests.

### Reset

The TFIB, TPC, and SVX-II chips can be set into a known state through
Reset. After Reset, the state of the data/control lines of the SVX-II
chips is known. Specifically on the case of the reset of the SVX-II
chips, a VME read of the HDI_AB and HDI_C Contents registers allows the
VME motherboard to read the current contents of the HDI.

### Cables and Drivers/Receivers between TFIB and TPC 

(NOT CURRENTLY IMPLEMENTED) The Byte Pattern Register is used to test
the cables and the drivers/receivers.

### Configuration of the SVX-II Chips or FPGA

The configuration of the SVX-II chips can be read back to determine if
the appropriate bits in the configuration of the SVX-II has been set.
When read back, these bits should be equal to the value that was
downloaded. The same with the FPGA used for the TPC controller. However,
the verification of the configuration of the FPGA is more involving (see
ref. 12).

### HDI Cables and Partial Test of SVX-II Chips

There are two ways of testing the HDI cables and partially test the
SVX-II chips. One method is to perform a readout of the SVX-II chips
without actually performing a digitization. The other method is to
perform a full read pipeline/digitize/readout with the configuration
READOUT ALL CHANNEL bit of the SVX-II chips asserted.

#### Readout Without Digitization 

(NOT CURRENTLY IMPLEMENTED) To perform this test, the READOUT ALL
CHANNELS configuration must be unasserted, which means that the SVX-II
chip must be in the sparsifier mode. The SVX-II chip ID is programmed
during configuration. This test allows the readout of SVX-II chip ID and
the status of all of the SVX-II chips in a HDI that do not contain data.
The SVX-II chip ID can be configured to fully test the HDI lines. Table
38 shows the format of the data.

*NOTE: RAY YAREMA DID NOT TEST THIS MODE OF OPERATION. HE BELIEVES IT
WILL WORK AS PRESENTED.*

+-----------------------------------------------------------------------+
| **HDI**                                                               |
+-----------------------------------------------------------------------+
| MSB ID                                                                |
+-----------------------------------------------------------------------+
| LSB ID                                                                |
+-----------------------------------------------------------------------+
| CHIP ID                                                               |
+-----------------------------------------------------------------------+
| STATUS                                                                |
+-----------------------------------------------------------------------+
| CHIP ID                                                               |
+-----------------------------------------------------------------------+
| STATUS                                                                |
+-----------------------------------------------------------------------+
| :                                                                     |
|                                                                       |
| :                                                                     |
+-----------------------------------------------------------------------+
| CHIP ID                                                               |
+-----------------------------------------------------------------------+
| STATUS                                                                |
+-----------------------------------------------------------------------+
| EOR                                                                   |
+-----------------------------------------------------------------------+

Table 38. Data FIFO format for readout without digitize

#### Readout with Digitization

To perform this test, the READOUT ALL CHANNELS configuration of the
SVX-II chips must be asserted. The TFIB executes the
read-pipeline/digitize/readout command. Meaningful information is not
connected to the input of the SVX-II chips. The data will be invalid,
but the Chip ID and the Channel Number are known. The full readout will
set the Channel Number from ZERO to 127. This will test all of the HDI
lines as well as the Priority In/Priority Out scheme of readout. This
mode can also be used to test part of the configuration of the SVX-II
chips such as the Chip ID.

## Diagnosis of the Command Lines between STAR/SRC and TFIB

The STAR/SRC sends commands and clock pulses to the TFIB. In order to
test this connection, the motherboard can read the Command Silo FIFO.
This FIFO saves all REAL MODE commands.

## Diagnosis of the G-Links

For further testing of the TFIB, two G-Links can be installed. The
G-Links are assembled in a daughter board which is plugged into the top
of the TFIB. The VME motherboard writes a data pattern to the Data FIFOs
and set the G-Links Transmit DFIFOs bit of the G-Link Control/Status
register. The TFIB transmits, through the G-Links, the data stored
inside the Data FIFO. The G-Links Transmit DFIFOs DONE bit of the G-Link
Control/Status register indicates when the operation is completed.

The G-Link Status register and the immediate command G-Link Send Fill
Frame of the Control Register are facilities available to help diagnose
the G-Links as well as regain synchronization with the receiver.

## Status Latch

When the TFIB-CT executes the Latch Status command, it saves the Status
register into the Status Latch register. The VME motherboard can later
check the contend of the Status Latch register. The Status Latch is a
non-resetable register.

# ELECTRICAL & MECHANICAL SPECIFICATIONS

## Connectors and Dip Switches

Figure 8 shows the location of limo connectors and DIP switches.

Both the SVX-CLK and 53 MHz-CLK limos are single-ended ECL output
designed to connect to a 50 ohms coaxial cable, terminated to ground by
a 50 ohms load. The SVX-CLK limo shows the clocks sent to the SVX chips,
while the 53 MHz-CLK is the master clock of the board. The 53 MHz-CLK
has three sources: front panel commands connector, the J3 backplane
command connector or the internal 53 MHz clock generator (for selection
of this clock, see DIP switch S1 and Control Low Register).

DIP switch S1 is used to select the external source of the 53 MHz clock
(Master Clock) for the TFIB. This DIP switch is enabled when the 53 MHz
Clock Source bit of the Control register is set to ZERO. Table 39 show
the DIP switch S1 assignment.

  ---------------------- ------------------------------------------------
  **DIP SWITCH NUMBER**  **FUNCTION**

  4                      Not used

  3                      Not used

  2                      Not used

  1                      External Clock select: Open =\> Front panel,
                         Close =\> J3 backplane.
  ---------------------- ------------------------------------------------

Table 39. DIP Switch S1 Assignment

DIP switch S2 is used to set the base address to the TFIB (see Section
4.1.1). Table 40 shows the assignment of DIP switch S2. Bits are set to
zero by having the switch in the on position. Bits are set to one by
having the switch in the off position.

  ----------------------------------- -----------------------------------
  **DIP SWITCH OPEN = 1, CLOSE = 0**  **ADDRESS LINE**

  8                                   not used

  7                                   not used

  6                                   not used

  5                                   not used

  4                                   A15

  3                                   A14

  2                                   A13

  1                                   A12
  ----------------------------------- -----------------------------------

Table 40. DIP Switch S2 Assignment

## Packaging & Physical Size

The TFIB is a 9Ux400 card.

## PC Board Construction

## Power Requirements

The TFIB requires +5.0V and -5.2V power supplies.

## Cooling Requirements

Cooling for the TFIB will be supplied by fans mounted on the VME crate.

# SAFETY FEATURES & QUALITY ASSURANCE PROCEDURES

## Module Fusing & Transient Suppression

The TFIB card is protected with fuses and transorbs.

## Other Safety & Quality Assurance Subsections

#  APPENDICES

## List Of Component Documentation

## Schematics

## PAL, FPGA Equations

## Timing Diagrams

## Parts List

## Additional Appendices 

**REFERENCES**

\[1\] R. Yarema *et. al.*, \"A Beginners Guide to the SVX-II\", Fermilab
document.

\[2\] J. Oliver, \"SVX Test Acquisition and Readout Board\".

\[3\] H. Gonzalez, K. Treptow, S. Zimmermann, J. Andresen \"Test Port
Card\", Fermilab document, May 20, 1994.

\[4\] C. Gay and J. Oliver, \"Silicon Readout Controller\".

\[5\] VMEbus Specifications, ANSI/IEEE STD1014

\[6\] M. Baert, \"D0 Silicon Acquisition and Readout Electronics: Custom
J3 Backplane Specifications\".

\[7\] AT&T, \"The 41 Series High-Performance Line Drivers, Receivers and
Transceivers\".

\[8\] "Low Cost Gigabit Rate Transmit/Receive", Hewlett Packard,
November 1993.

\[9\] C. Bonacorso, \"G-Link/Finisar Transmitter and Receiver Boards\",
Fermilab document, SVX-II Silicon Strip Detector Upgrade Project.

\[10\] "Finisar Low Cost Gigabit Optics + G-Link Chips", Finisar Corp.

\[11\] D. Walsh and S. Zimmermann, \"TFIB Diagnostic Software\",
Fermilab document.

\[12\] "The Programmable Logic Data Book," Xilinx Corp., 1994.

[^1]: The FPGA becomes the TPC Controller after it is programmed.

[^2]: X = Don\'t care

[^3]: 0x means hexadecimal.

[^4]: The two HDI ID bytes and the first byte (Chip ID) of the first
    SVX-II chip.

[^5]: d is data bit.

[^6]: The term \"byte\" is 8 bits. The term "9 bits" is a 9 bits. The
    term \"word\" is 16 bits.

[^7]: Both Control Low and High are reference as Control Registers.

[^8]: N.I. = Not Implemented

[^9]: Bits that are marked as \"not used\" have no meaning, and they are
    readable or writable as ZERO or ONE. When the VME motherboard reads
    these bits, it should mask them off.

[^10]: The signal BXING is not presently used by the TFIB logic.

[^11]: NC = Not Connected

[^12]: Not presently used.

[^13]: This parameter does not use "number of SYNC pulses". This time is
    given by the reset circuitry of the TFIB, formed by a MAX707
    manufactured Maxim. It maximum reset pulse is 280 ms.