![](media/image1.png){width="0.7916666666666666in"
height="0.8958333333333334in"}

> Fermilab/AD/TEV
>
> Beams-doc-1512-v3

Dec. 27, 2004

Tevatron BPM Upgrade Test Stand Setup

Dehong Zhang

Fermilab, Computing Division, CEPA

# Abstract

This document contains a description of the test stand setup for the
Tevatron Beam Position Monitor (BPM) Upgrade. Functionalities of the
various hardware pieces are briefly outlined, necessary procedures for
setting up the system are listed and precautions highlighted.

# Overview

The BPM system determines how to digitize the electric signals from the
pick-ups and how to present the data to the users according to events
received from the Tevatron TCLK system and according to messages
received from the Accelerator Controls Network (AcNet). It uses the 53.1
MHz Tevatron RF clock as its time base and the BSYNC signals to derive
the triggers.

For standalone software and/or hardware testing, the RF clock, TCLK and
BSYNC signals may be omitted all together, or generated from a modified
"Clocks Box", and the front-end processor can boot from anywhere. For
integrated tests, these signals must be obtained from the "Accelerator
Controls Fiber Optic Repeater", while the front-end processor must be
connected to AcNet via a dedicated switch. Please refer to the following
picture for the relevant hardware pieces.

![](media/image2.png){width="6.016666666666667in"
height="6.727777777777778in"}

# Fiber Optic Repeater

This device provides fanouts for the Tevatron TCLK and BSYNC signals.
Two optic fibers were run from the MAC room to FCC, one carrying the
TCLK signal, the other the BSYNC signal. The TCLK signal actually
originates in the MAC room, while the BSYNC signals, including the 53.1
MHz low level RF signal and the turn marker (0xaa), are generated in
service building MI60 and sent to the MAC room.

On the back of this device, there are in total 5 TCLK output spigots, 4
BSYNC spigots and 2 53.1 MHz RF spigots (opposite phases) as can be seen
in the following picture. In the service buildings, these signals should
be obtained from the standard "Clocks Box"es.

![](media/image3.png){width="6.0159722222222225in"
height="3.265277777777778in"}

Since this device only does fanouts, it can be powered up or down at any
time. For more information, please contact Greg Vogel of the Accelerator
Controls Department at Ext. 4942.

# Clocks Box

In the service buildings, the standard "Clocks Box"es provide the same
fanouts as the "Fiber Optic Repeater"s do. By pressing the corresponding
"Select" button, a group of spigots can be set to fanout a certain
signal, and one LED will turn on to indicate the signal chosen, see the
picture below.

![](media/image4.png){width="6.009722222222222in"
height="0.8652777777777778in"}

For standalone setups which do not need to interact with the real
Tevatron environment, Craig Mcclure of the Accelerator Controls
Department, Ext. 3580, had made a modified version to generate the 53.1
MHz RF signal (actually 52.8 MHz), a few TCLK events and a few BSYNC
events without external inputs. This box was used before we extended all
Tevatron signals to FCC and has been in the rack ever since.

# 

# Network Switch

If AcNet access is needed, the front-end processor will have to be
connected to AcNet and boot from node "fecode-bd" of the Accelerator
Division. To allow this connectivity, two optic fibers were run from the
Computer Room of the Accelerator Division to FCC, and a dedicated
network switch installed.

![](media/image5.png){width="6.011805555555555in"
height="0.7013888888888888in"}

Before connecting a processor to the switch, please:

1.  apply for a fixed IP address for the Accelerator Division Networks
    at:

> http://www-bdnew.fnal.gov/Netwebrequests/net-connection.asp

2.  contact Tim Zingelman of the Accelerator Controls Department to
    activate a particular port for that particular processor (MAC
    address);

3.  contact Denise Finstrom of the Accelerator Controls Department to
    add the node name and user "vxworks_boot" pair to some ".rhosts"
    file so that the processor can access the boot area on "fecode-bd";

4.  contact Brian Hendricks of the Accelerator Controls Department to
    obtain an AcNet Trunk ID;

5.  contact Dinker Charak of the Computing Division, CEPA/OAA for a
    proper version of the VxWorks kernel. Up to now we have been using
    VxWorks 5.5. Please load the processor's bootrom and program its
    flash by following the instructions listed on (load from fndaut on
    the 253 subnet):

> http://cepa.fnal.gov/oaa/internal/vxworks/docs/burningbootroms.shtml
>
> Be sure to answer the questions like the following:
>
> Node Control Memory Address =xxxxxxxx? 01F9E000
>
> \...
>
> Server IP Address =0.0.0.0? 131.225.253.22
>
> \...
>
> File Name =? vxboot/mv2400/v5_5a/tbpm-boot.bin
>
> \...

The boot parameters should read like the following:

boot device : dc

unit number : 0

processor number : 0

host name : fecode-bd

file name : vxworks_boot/kernel/test/mv2400/v5_5/vxWorks-acdfgP

inet on ethernet (e) : 131.225.126.234:ffffff00

host inet (h) : 131.225.121.145

gateway inet (g) : 131.225.126.200

user (u) : vxworks_boot

flags (f) : 0x0

target name (tn) : fccts1_0x0BD4

startup script (s) : vxworks_boot/fe/tbpm/tbpmstartup-dev

where "fccts1" is the node name, "0x0BD4" the AcNet Trunk ID.

Due to the critical nature of the AcNet, please by all means observe the
following:

1.  **NEVER** power up, or plug the optic fiber back to, the switch
    without permission from the Main Control Room, Ext. 3721.

> This is because these actions will make the switch to broadcast to the
> AcNet to announce its joining. This broadcast will cause other
> switches to update their route tables and possibly delay some
> time-critic accelerator controls activities, and consequently cause a
> beam loss.
>
> In contrast, to power down, or to unplug the optic fiber, is not as
> disruptive.

2.  Only connect the allowed hardware to the designated port. A port
    will be immediately shut off if an unknown hardware is connected to
    it, even if that particular piece of hardware is allowed for one of
    the other ports.

> If a mistake is made and a port disabled, please contact Tim
> Zingelman, Ext. 3245, to re-activate.

An UPS power supply was recently installed for this network switch to
minimize possible disruptions to its stable operation.

# Beam Simulator

For testing timing relations and system behavior, various beam simulator
modules exist in the Accelerator Division. Both uncoalesced and
coalesced beam structures can be generated with a beam generator,
amplified with a fixed gain of 10 and then manipulated with an analog
multiplier to tune the overall gain or modulate the output with another
signal, refer to the following picture.

![](media/image6.png){width="6.011111111111111in"
height="3.1319444444444446in"}

The beam generator can generate a sequence of pulses spaced as
uncoalesced buckets or coalesced bunches. It uses the 53.1 MHz Tevatron
RF clock as its time base, uses the turn marker in the BSYNC signal to
trigger the generation sequence, and has 4 dials in the front for
setting the time delay between the turn marker and the pulse sequence.
It has a processor on-board with a name "tevbpmtesttrig" and IP address
"131.225.126.242", and can be controlled from Nova. The connectors for
the Ethernet, the 53.1 MHz RF clock and the BSYNC signal inputs are in
the back of the module.

Two control commands exist on Nova in "/export/home/cytan/sp". One is
for enabling or disabling individual buckets or bunches like the
folloing:

sp --a tevbpmtesttrig \[-B\|\--Bunch \<enable bunch 1\<=bunch\<=36\>\]

\[-b\|\--bucket \<enable bucket 1 \<= bucket \<= 1113 \>\]

\[-D\|\--Disable \<disable bunch 1 \<= bunch \<=36\>\]

\[-d\|\--disable \<disable bucket 1 \<=bucket \<=1113\>\]

\[-r\|\--reset \<disable all buckets/bunches\>\]

\[-h\|\--help\]

if -b, -B, -d, -D or -r not set, the current bunch/bucket settings will
be displayed.

The other is to enable the 36 coalesced bunches all at once:

do36 --a tevbpmtesttrig

The analog multiplier is used to control the intensity of the simulated
beam. Its gain varies linearly with the input to the corresponding
control spigot. The gain will be 1 when a 10 V DC is fed to the control
input. Transverse beam motion inside the beam pipe can be simulated by
feeding input "A" of a summer module with a DC, input "B" a low
frequency sine wave, and connecting its outputs "A+B" and "A-B" to the
analog amplier's two control inputs.

For more information about beam simulations, please contact Jim Steimel
of the Tevatron Department, Ext. 4826.

# The BPM Crate

The production Dawn VME64X crates have been used in the test area. A
test crate should at least have the following installed (see picture on
the next page):

1.  one Motorola MVME2400 PPC processor board, with a PMC UCD daughter
    board;

2.  one Timing Generator Fanout (TGF) board;

3.  one Echotek ECDR-GC814-FV-A board.

Other boards like the corresponding Filter board for the Echotek board,
and VMetro board etc. can be included when needed.

The PPC processor board needs 2 inputs: connection to the network switch
to gain access to AcNet and to node "Nova/fecode-bd", and TCLK signal
for the PMC UCD daughter board. An optional console terminal can be
connected through the console port. The typical boot parameters are
listed in the "Network Switch" section above.

The TGF board needs 3 inputs, all in the front: the 53.1 MHz Tevatron RF
clock, the TCLK signal and the BSYNC signal. In the front, it has 8
"Clock Out"s, 8 "Sync Out"s to feed the Echotek boards, and 4 diagnostic
signals -- "TRG0" for start event, "TRG1" for turn marker (0xaa), "TRG2"
for 53.1 MHz pulses continuous or train-of-7 phase locked with the turn
marker, and "DAC" which is not yet defined. The 53.1 MHz continuous or
train-of-7 diagnostic pulses are also outputted to the VME back plane
for the filter boards.

The availabilities of the input signals are shown on the front panel
with LEDs. For basic system tests which do not involve interactions with
TCLK, the TCLK signal can be omitted. For standalone testing, all the 3
inputs can be omitted. In this case the TGF will

![](media/image7.png){width="6.017361111111111in" height="9.14375in"}

use its internal crystal and PLL to generate the desired 74.3466 MHz,
and reverse derive the 53.1 MHz RF clock. The only limitation is that it
will not be able to generate the trained 53.1 MHz diagnostic pulses
because there is no turn marker to trigger the sequence.

Each Echotek board needs a clock input, a sync input and 8 analog
inputs, and has 2 LEDs to show its state. The red "OF" LED will turn on
immediately after power on, and turn off when the FPGA firmware has been
properly loaded. The green "CA" LED will remain off until proper clock
signal is available and the internal PLL has successfully locked to it.

Each Echotek board has a dip switch to set the highest 4-bit of its A16
base address (bits 12 -- 15 in 0x?000). The switch is located on the
back of the board, below the Tundra Universe II chip and the 64 MHz
crystal and near the top end of the bottom VME connector (see picture
below). The left-most handle is for bit 12, the right-most handle is for
bit 15. The up position, or "ON", means "1", while the down position
means "0". Within a crate, boards should be set from 0x8000 through
0xf000 (maximum 8 boards) from left to right in order for the front-end
software to properly map the channels.

![](media/image8.png){width="6.00625in" height="2.970138888888889in"}

In tests where we do not need to time relate the signals, we can omit
the sync input and use a software trigger.

# General Note

Please insert/remove boards carefully, be sure to properly seat the
boards, and tighten the screws whenever possible. \-- Improperly seated
boards do cause a wide variety of strange behaviors.