Radiation effects in hafnium oxide as MOS gate dielectric caused by
e-beam lithography

Hiu Yung Wong

> *Department of Electrical Engineering and Computer Sciences,
> University of California, Berkeley, 94720*

The radiation effects in hafnium oxide as MOS capacitor gate dielectric
by e-beam lithography was studied and compared with that in silicon
dioxide. Two different standard e-beam lithography processes utilizing
different resists, with exposure dose of 100μC/cm^2^ for AZPN114 and
exposure dose of 1000μC/cm^2^ for HSQ, were used together with optical
i-line lithography as reference. It is found that high dose e-beam
exposure increases the fixed charge of 38Ǻ hafnium oxide by
7.3×10^11^cm^-2^ and the dielectric quality is also significantly
degraded in terms of Time-Zero-to-Dielectric Breakdown (TZDB). Silicon
dioxide seems to be less affected by the irradiation of e-beam.

**I. INTRODUCTION**

According to the International Technology Roadmap for Semiconductors
(ITRS), transistor gate length will continue to shrink and reaches
sub-25nm by 2010 in order to achieve faster switching speed and higher
device density per unit silicon area.[^1] E-beam lithography is a
possible candidate for patterning such small feature sizes other than
Extreme Ultra Violet (EUV) lithography. At the same time, gate oxide
thickness is also decreasing in order to increase the gate capacitance
and thus the control of the gate over the channel and thickness of less
than 1nm will be required if silicon dioxide continues to be used.Error:
Reference source not found However, the gate leakage current will
increase substantially due to direct tunneling at sub-1nm dielectric.
High-k dielectric (HfO~2~) is being sought to replaced silicon dioxide
because its higher permittivity allows its physical thickness to be
larger while still attaining the same capacitance. With larger physical
thickness, the gate tunneling current is thus suppressed.

Compared with conventional optical lithography with use relatively low
energy photons, energetic electron beam as large as 100keV is used to
pattern the resist in e-beam lithography. Since most of the electrons
will penetrate more than several micrometers of depth without
significant loss of energy,[^2] it would then be of much concern if
e-beam lithography is used for patterning the gate of MOS transistors,
in which the gate dielectric quality and reliability is very important,
on which the lifetime and performance of the transistors depend.
Moreover, usually high-k dielectric involves atoms of higher atomic
number (e.g. Hf with Z=72). Therefore, they possess larger scattering
cross-section and it is expected that more e-beam energy will be
dissipated on the high-k dielectric compared with SiO~2~. To the best of
our knowledge, only radiation effects on MOS devices with SiO~2~ have
been studied.[^3] Therefore it is necessary to investigate the possible
radiation effects of e-beam on high-k dielectrics.

In this study, the radiation effect of e-beam lithography on HfO~2~ was
studied by choosing two different doses, 100μC/cm^2^ (for exposing
AZPN114) and 1000μC/cm^2^ (for exposing HSQ) to pattern MOS capacitors.
Gate dielectric quality was assessed by studying the capacitance-voltage
(CV) curves, leakage current, and Time-Zero-to-Dielectric-Breakdown
(TZDB) of the capacitors. Optical lithography was used as reference.
Effect of low dose e-beam exposure on SiO~2~ was also studied.

**II. EXPERIMENT**

Arrays of 60×60μm^2^ n-type MOS capacitors were formed throughout a
3×5cm^2^~­~ area on 4-inch p-type silicon wafers (Figure 1). Firstly, the
gate dielectric is formed and is either 3.8nm HfO~2~ (physical
sputtering of Hf followed by Rapid Thermal Oxide (RTO) at 700^o^C for
30sec) or 3.4nm thermal SiO~2~. In-situ phosphorus doped amorphous
silicon (a-Si) was then deposited using Low Pressure Chemical Vapor
Deposition (LPCVD) and the dopants are activated by either Excimer Laser
Annealing (ELA) or Thermal Annealing (TA). I-line resist, AZPN114 and
HSQ are then applied to different wafers and exposed using g-line
lithography, low dose (100μC/cm^2^) and high dose (1000μC/cm^2^) e-beam
lithography (100keV) respectively. Table 1 shows the experimental
splits.

After lithography, pattern was transferred to gate electrode using
ICP/RIE etching. Piranha (H­~2~O~2~/ H~2~SO~4~) was used to remove the
organic resists afterwards while buffered HF (40:1BHF for 35 sec) was
used to remove HSQ. Following Forming Gas Annealing (FGA) at 400^o^C for
30 mins., CV curves, leakage currents and TZDB were measured.

![](media/image1.png){width="3.123611111111111in"
height="3.115972222222222in"}

+---------------+--------+-----------+-----------+--------+----------+
|               | E2     | E3        | E4        | EO1    | EO2      |
+---------------+--------+-----------+-----------+--------+----------+
| Resist        | i-line | 200nm     | 200nm     | i-line | 200nm    |
|               |        |           |           |        |          |
|               |        | AZPN      | HSQ       |        | AZPN     |
+---------------+--------+-----------+-----------+--------+----------+
| Dielectric    | HfO~2~ | HfO~2~    | HfO~2~    | SiO~2~ | SiO~2~   |
+---------------+--------+-----------+-----------+--------+----------+
| Dopant        | ELA    | ELA       | ELA       | TA     | TA       |
|               |        |           |           |        |          |
| Activation    |        |           |           |        |          |
+---------------+--------+-----------+-----------+--------+----------+
| a-Si          | 70     | 70        | 70        | 150    | 150      |
| thickness     |        |           |           |        |          |
| (nm)          |        |           |           |        |          |
+---------------+--------+-----------+-----------+--------+----------+

Table 1: Experimental Splits

**III. EXPERIMENTAL RESULTS**

**A. HfO~2~ dielectric**

Fig. 2 shows the C-V curves of the n-type MOS capacitors patterned by
different lithography methods. It is clear that the CV curves of those
formed by optical (E2) lithography are the same as those by using low
dose e-beam lithography (E3). However, those formed by high dose e-beam
lithography show a parallel shift to the negative direction by 0.1eV. By
using the equation relating the flat band voltage (V~FB~), difference in
the work function of the gate and the substrate (Φ~MS~), the fixed
charge per unit area (Q~f~) and the capacitance (C~OX~)[^4],

$V_{\text{FB}} = \Phi_{\text{MS}} - \frac{Q_{f}}{C_{\text{ox}}}\text{.}\text{.}\text{.}\text{.}\text{.}\text{.}(1)$we
can deduce that there are effectively additionally 7.3×10^11^cm^-2^ of
positive fixed charged induced by due to high-dose e-beam lithography or
the gate work function is reduced by 0.1eV.

![](media/image2.wmf){width="3.2604166666666665in"
height="2.303472222222222in"}

Figure 3 shows the TZDB distribution of the capacitors patterned using
different lithography methods. Obviously, the quality of those patterned
with high dose electron beam is degraded, as the TZDB voltage is about 2
volts lower than those by low dose e-beam lithography. Compared with
optical lithography, low dose e-beam lithography narrowed the
distribution towards the low quality side.

Figure 4 shows the leakage current distribution of capacitors patterned
using different lithography method. Generally, they show similar
distribution and the leakage current does not increase when e-beam
lithography is used.

**B. SiO~2~ dielectric**

Figure 5 shows the leakage current distribution of n-type MOS capacitors
with SiO~2~ dielectric patterned by optical lithography and low dose
e-beam lithography. Again, there is no significant difference between
these two cases.

Figure 6 shows the TZDB distribution of the capacitors patterned by
optical and low dose e-beam lithography. The dielectric quality is
reduced when e-beam lithography is used with the distribution becomes
narrower and concentrates towards the lower quality side.

**IV. DISSCUSSION**

The origin of the additional fixed charged induced by the irradiation of
e-beam lithography is unknown. It has been reported that through
positive ion implantation into the gate dielectric, the fixed charge in
the silicon dioxide can increase.[^5] However, if the bonds between the
hafnium and oxygen atoms are broken due to the high-energy electron
beam, it could not be concluded easily that there will be additional
positive charge. And intuitively, as the devices had not gone through
long time operations, it is expected the overall induced charge to be
neutral or negative (due to accumulation of electrons) and only under
temperature bias stress would the CV curves shifted.Error: Reference
source not found

Another possible explanation to the CV curves shifting is that the
energetic electrons have broken the bonds between Si and Hf (Hf-Si
bonds) at the gate dielectric and gate electrode interface. Poly-Si/
HfO~2~ MOS capacitors is known to have the problem of fermi-level
pinning due to the formation of interfacial layer containing Hf-Si
bonds. As a result, the effective work function of the n+ silicon gate
is increased from --0.86eV to about --0.7eV when undoped p-type
substrate is used. According to equation (1), the shift of the CV curve
can also be explained as the increase of the Φ~MS~ resulted from Hf-Si
bonds breaking.[^6]

The TZDB data shows that when patterned with e-beam lithography, the
breakdown voltage decreases in both case of HfO~2~ and SiO~2~. This is
possibly due to the weakening of the defect bonds inside the gate
dielectric during ebeam exposure. As a result the on-set of the
breakdown is earlier. It can also be concluded that for lose dose
exposure, the weakening of the defect bonds is comparable to or smaller
than the weakest intrinsic defects. Therefore, the distribution of TZDB
is narrowed towards the low quality side. While for the high dose
e-beam, the damage is much large than the intrinsic defects and the
whole distribution shifted. Comparing Figure 3 and Figure 6, it is found
that the effect of the low dose ebeam on the SiO~2~ is less than that on
HfO~2~. This may due to the lower scattering cross section of Si and
thus less energy dissipation on the dielectric
layer.![](media/image8.wmf){width="3.0368055555555555in"
height="1.2652777777777777in"}

The leakage current distribution in both SiO~2~ and HfO~2~ cases show no
dependence on the lithography method. This means that the damage of the
electron beam on the high-k dielectric is not high enough to enhance the
mechanism for gate tunneling. Since both the SiO~2~ and HfO~2~
dielectric are thicker than 3nm, the mainly tunneling mechanisms are
Fowler-Nordheim Tunneling and trap assistant tunneling.[^7] Therefore,
the damage of the ebeam on the gate dielectric is not large enough (even
for high dose) to generate substantial traps to increase the leakage
current in both dielectrics.

It may be argued that the degradation of the high dose e-beam case is
due to the etching of HfO~2~ on due to BHF around the gate capacitor
edge. However, it has been reported that HfO~2~ is difficult to be
removed by HF after being annealed at 700^o^C for 30 sec.[^8] Since our
film was formed by RTO at the same condition, it is reasonable to assume
that in-situ annealing was achieved. Moreover, since large capacitors
are used in the experiment, the effect of BHF is assumed to be
negligible.

**V. CONCLUSIONS**

The radiation effect in HfO~2~ and SiO~2~ gate dielectrics has been
studied using high-dose and low-dose e-beam lithography compared with
optical lithography. It is found that the gate quality of high dose case
is severely degraded. Although low dose case also shows degradation, the
dielectric quality is still comparable with optical lithography. SiO~2~
dielectric seems to be less affected by e-beam radiation due to their
smaller cross-section.

[^1]: ITRS 2003

[^2]: Ludwig Reimer, "Scanning Electron Microscopy", Spinger-Verlag
    (1985)

[^3]: M. Peckerar et al., "Radiation Effects in MOS Devices caused by
    x-ray and e-beam lithography", JVST, 16 (6), 1658, 1979.

[^4]: S.M. Sze, "Physics of Semiconductor Devices," WILEY, 1981.

[^5]: H. Y. Wong et al., "Reduced Poly-Si Gate Depletion Effect By
    Pulsed Excimer Laser Annealing," to be appeared in ECS 04.

[^6]: H. Takeuchi, et al., "Process Optimization and Integration of HfO2
    and Hf-Silicates," D7.6 MRS Spring 04.

[^7]: D. K. Schroher, "Semiconductor Material and Device
    Characterization," 2^nd^. Ed.,Wiley 1998.

[^8]: K. L. Saenger et. al, "A Selective Etching Process for Chemically
    Inert High-k Metal Oxides," MRS Symp. Proc. Vol. 745, N3.9.1, 2003.