**1. [Scope and Purpose]{.underline}**

This document addresses the configuration variables which have been
found to affect Ball Grid Array (BGA) interconnect reliability.
Preferred configurations which control these variables and enhance the
BGA's interconnect reliability are discussed. Examples of these
configuration variables are provided in Appendix A. Commercially
available analysis tools are discussed which can be used to assess the
reliability of a BGA interconnect based on its configuration variables.

This document is limited to a discussion of BGA's and does not
investigate Column Grid Array packages. It is also limited to
interconnections between BGA's and polymeric printed circuit boards
(PCBs).

**2. [BGA Reliability]{.underline}**

BGA solder joint reliability is normally characterized by thermal cycle
life. CTE mismatch between the part and the PCB as well as mechanical
stress due mechanical bending or board warp are the leading
environmental contributors to failure. Typical lifetimes for BGA joints
are between 100 thermal cycles and \~6000 thermal cycles for temperature
excursions between -55°C and 100°C. Life expectancy will be shorter for
greater temperature swings.

A large number of variables related to the physical design of a BGA
package, the layout pattern on the PCB and the application of solder to
the PCB prior to solder reflow will affect the thermal cycle life of the
final BGA joints. These variables are discussed in the following
sections.

**3. [Package Material: Plastic vs Ceramic]{.underline}**

Reliability studies have shown that Plastic BGAs (PBGA) have longer
lived solder joints that those of Ceramic Ball Grid Array (CBGA) joints.
The reasons include better Coefficient of Thermal Expansion (CTE) match
and coplanarity is less of an issue. Thermal cycling ranges beyond
20^o^C to 85^o^C will further reduce CBGA joints. PBGAs should be
selected if the application allows it.

Ceramic packages, largely manufactured for the high reliability market
or where thermal management necessitates a high conductivity package
material, have not been manufactured often as Ball Grid Arrays. Instead,
column interconnects are being offered to increase pin count for ceramic
packages. Column Grid Array reliability is not treated herein.

**3.1. [Coefficient of Thermal Expansion Matching]{.underline}**

For a PBGA, the selection of the PCB laminate system is not critical
since both FR-4 and polyimide have a CTE closely matched to
Bismaleimide-Triazine (BT), which is usually the internal package
substrate material. Ceramic BGA's have a CTE mismatch with all typical
PCB laminates. For applications where large thermal excursions are
expected an FR-4 with high glass transition temperature should be used.
Typical thermal coefficients of expansion are shown in Table 1 for the
various materials involved.

+------------------+-------------------------+------------------------+
| #### T           |                         |                        |
| able 1 Typical C |                         |                        |
| oefficients of T |                         |                        |
| hermal Expansion |                         |                        |
+------------------+-------------------------+------------------------+
| **Material**     | **CTE (x-y              | **CTE (z axis)         |
|                  | axis)ppm/^o^C**         | ppm/^o^C**             |
+------------------+-------------------------+------------------------+
| Tin-lead solder  | 24                      | 24                     |
+------------------+-------------------------+------------------------+
| Copper           | 16-18                   | 16-18                  |
+------------------+-------------------------+------------------------+
| FR-4             | 16-18                   | 60-85                  |
+------------------+-------------------------+------------------------+
| Polyimide        | 15-18                   | 65                     |
+------------------+-------------------------+------------------------+
| BT               | 15                      | 50                     |
+------------------+-------------------------+------------------------+
| Epoxy Overmold   | 15                      | 15                     |
+------------------+-------------------------+------------------------+
| Silicon          | \~2.6                   | \~2.6                  |
+------------------+-------------------------+------------------------+
| Alumina oxide    | 3-6                     | 3-6                    |
+------------------+-------------------------+------------------------+

**4. [Package Size vs Die Size]{.underline}**

The BT package substrate in a PBGA package is organic giving it a CTE
closer to that of the laminate polymeric PCB than that of the die
itself. Therefore, the larger the die the more pronounced the effect of
the CTE will be and the less reliable the interconnect. A very large die
and a large package will be more sensitive to board warp and mechanical
effects associated with uneven thermal conditions (such as during
reflow), shock and vibration.

**5. [Ball Size to BGA Pad Size]{.underline}**

BGA's with larger solder balls tend to have higher reliability than
smaller balls. The larger solder balls provide greater standoff and more
mechanical compliance. The greater solder mass of the larger balls
provides better thermal conductivity. Extremely small balls are used to
increase interconnect density which introduce a greater opportunity for
electrical shorting between contacts and more sensitivity to thermal
design issues.

**6. [Die to Substrate Connection]{.underline}**

The three common methods of electrically connecting the die to the
package are wire bond, flip chip, and tape automated bonding. Of these
three, wire bonded devices are more reliable because the
interconnections have stress relief. Wire bonded devices should be
selected if available.

**7. [Moisture Sensitivity]{.underline}**

PBGA's have not been shown to be any more sensitive to moisture than
their leaded, plastic counterparts. All protections and practices
associated with plastic encapsulated microcircuits (PEMs) for space
hardware also apply to PBGA packages. Parts with moisture sensitivity
levels 1 and 2 per J-STD-033A are recommended.

**8. [Substrate and PCB Pad Configurations]{.underline}**

On both PCB's and the package's substrate, there are two primary pad
configurations for BGA solder ball attach: Solder Mask Defined (SMD) and
Non-Solder Mask Defined (NSMD). SMD pads allow the solder mask to touch
the pad. NSMD pads limit the solder mask to outside of the pad area,
(Figure 1). With SMD pads, a smaller ball to pad interface is achieved
resulting in a less robust connection. Also, it has been shown that the
sharp edges of the solder mask in SMD pads can initiate solder joint
cracking at the ball to pad interface. When available, devices with NSMD
substrate pads should be chosen. PCB layout should always use NSMD pad
design for BGAs. The manufacturer's recommended pad size should be used.

Figure 1, SMD vs. NSMD

9\. **[PCB Design Considerations]{.underline}**

BGA package interconnect reliability is highly dependant on the unit as
integrated with the PCB and the overall mechanical and thermal design at
the box level. Pad design, part arrangements across the entire board,
via design and trace management are all factors. The following
paragraphs discuss these factors.

**9.1 [Via Design]{.underline}**

Where PCB space is available, the preferred via is an open interstitial
via with an aspect ratio of 4:1 or less. The drilled hole size should be
0.020" or larger when possible. The solder mask (SM) opening should
provided 0.0015" clearance around the pad. A minimum of 0.010" of SM
between a BGA pad and its via is necessary. In all cases, vias must be
sufficiently isolated from BGA solder pads to prevent solder joint
starving. This can be accomplished by applying solder mask over bare
copper to cover the via. It is preferable to first fill the via with a
suitable via filler material before applying solder mask for isolation.
If the pitch of the BGA chosen will not allow these aspect ratio and SM
recommendations to be met, then filled vias should be used. The fill
material should be a thermally matched conductive material with or
without overplating.

**9.2 [Part Placement]{.underline}**

To facilitate removal and replacement, adequate free space is required
around the BGA package. A clearance of 0.125" minimum should be allowed
for this. Careful consideration must be given to the placement of heavy
or large thermal mass parts to avoid uneven solder joint reflow or
excessive board displacement near the BGA connection during shock and
vibration events.

**9.3 [Routing and Separation]{.underline}**

The very dense contact spacing of the BGA package allows significant
board size reduction. It is recommended that relatively large traces and
spacing be maintained away from the part to enhance PCB production cost
and yield. Traces should be a minimum of 0.004" wide provided this is
adequate for the anticipated current. Traces should be separated by a
minimum of 0.004" provided this is adequate dielectric separation for
the application.

**9.4. [Stencil Design/Type]{.underline}**

The main considerations for the stencil design should be solder paste
volume, aperture shape, aperture size and printing quality. Stencils are
generally electroformed nickel or stainless steel which is laser cut or
precision etched. Precision etching can be used for component pitches
down to 0.635mm (0.025") and laser cut for component pitches below this.
The stencils are generally in the 0.004" to 0.008" thickness range. A
1.5^o^ -- 2.5^o^ draft angle of a trapezoidal aperture offers the best
paste release characteristics and deposits that are resistant to slump.
Nickel electroforming offers a harder finish than stainless steel and
naturally smooth walls to enhance paste release.

**9.5 [Underfill]{.underline}**

Non-reworkable underfill with an epoxy material may be necessary to
improve solder joint life. Reworkable underfill is available but test
data indicates that it may actually decrease solder joint life so its
use is not recommended. For applications where outgassing and offgassing
are a consideration, the underfill should be a type that can pass the
total mass loss and condensable volatile materials tests prescribed in
ASTM E-595 and the criteria established by SP-R-0022A.

**9.6. [Coplanarity]{.underline}**

Generally, the coplanarity of the BGA is very small since there are no
leads to bend and the plane of the solder bumps is flat. The warp of the
printed circuit board will generally dictate the coplanarity of the BGA
assembly. It is recommended that the allowable warp of a PCB for BGA use
be held to less than 1%; 1% warp could be greater than 0.010 inch under
a 35 mm square BGA. An allowable PCB warp of 0.5% max is recommended.

**10. [Quality Control and Inspection Techniques]{.underline}**

Even though the BGA package and board layout may be theoretically
optimized for reliability by design, the process of manufacturing and
assembly can have just as much impact on the longevity of the BGA
connection. The paragraphs below describe practices which can be used to
reduce manufacturing/assembly related problems.

**[10.1 Solder Wetting Verification]{.underline}**

BGA solder balls (tin-lead composition) when in contact with the pads on
the PCB will self-align during solder reflow. However, the ability to
visually inspect is limited and non-destructive means will not reveal
minute defects in the solder connection. Therefore, bare PCB wetting
verification tests are recommended for each lot of PCB's to ensure that
the PCB surface finish does not inhibit reflow. It is suggested that an
extra coupon be required with each board or panel for this verification
test.

**10.2. [Verification Runs]{.underline}**

For mission critical applications, a minimum of three soldering
verification runs is recommended for new designs. Verification hardware
must be the same parts layout configuration as production hardware;
however, equivalent dummy devices may be used in lieu of parts with live
die. Daisy chained parts, when available, should be used to enable
electrical verification of completed joints which can not be visually
inspected. Hardware from verification runs should be subjected to visual
and oblique angle x-ray inspections and destructive physical analysis.

**10.3 [Part Moisture Control]{.underline}**

Prior to population of flight printed circuit assemblies with PBGA's or
other plastic IC's, it must be verified that controls for moisture have
been followed in accordance with IPC/JEDEC J-STD-033A. Bake-out of
PBGA's at 125^o^C for 4 hours is recommended followed by dry storage
until use. The time between removal from storage and reflow is dependent
upon the parts sensitivity factor per J-STD-033A and must be strictly
followed. PCB's should be baked at 120^o^C for 3.5 hours.

**10.4 [Underfill Application ]{.underline}**

When used, underfill material should be applied following the
manufacturer's recommendations in such a way as to minimize voids.
Printed circuit assemblies must be cleaned of flux residues and other
contaminants and baked (see 10.3 above) prior to underfill application.

5.  **[X-ray and Visual Inspection]{.underline}**

There are numerous limitations that prevent x-ray and visual inspection
from being sufficiently thorough inspection methods. A combination of
inspections should be used. Fiber optic instrumented CCD camera-based
inspection systems are available and can enable visual inspection of the
inner connections hidden from the outside. Visual inspection of BGA
solder joints may be performed using distal focus endoscopic techniques
or equivalent. X-ray imaging can reveal bridged contacts and voids in
the solder balls. X-ray inspection should be performed using an oblique
angle real-time system with at least micron focus capabilities. Oblique
angle transmission can assist in determining the proximity of voids to
critical interfaces (solder ball to part and PCB).

**11.** **[Reliability Analysis]{.underline}**

Unlike leaded surface mount devices, which have inherent stress relief
from lead compliance and where reliability doesn't vary significantly
from device-to-device, many characteristics of the BGA influence the
overall reliability. These factors, discussed above, are also summarized
in Table 2. Analysis of test data is ongoing to further quantify these
sensitivity factors as the primary characteristics that influence
overall BGA solder joint reliability. These sensitivity factors are
included in reliability modeling software created by Auburn University's
Center for Advanced Vehicle Electronics (CAVE). The CALCE center at the
University of Maryland also has the capability to model BGA interconnect
reliability however the sensitivity factors considered in the CALCE
product have not been studied for this report. At the time of this
writing, the CAVE statistical modeling tool is available online to CAVE
members. The finite element modeling tool and math model are not
available online but are available to CAVE members by contacting CAVE
directly at cave@eng.auburn.edu.

+----------------+-----------------+------------------+---------------+
| #### Ta        |                 |                  |               |
| ble 2 - Factor |                 |                  |               |
| s that Affect  |                 |                  |               |
| BGA Solder Joi |                 |                  |               |
| nt Reliability |                 |                  |               |
+----------------+-----------------+------------------+---------------+
| **Feature**    | **Lower         | **Moderate       | **Higher      |
|                | Reliability**   | Reliability**    | Reliability** |
+----------------+-----------------+------------------+---------------+
| Part Type      | CBGA            | CCGA             | PBGA          |
+----------------+-----------------+------------------+---------------+
| Die size to    | Largest         |                  | Smallest      |
| part ratio     |                 |                  |               |
+----------------+-----------------+------------------+---------------+
| Ball to pad    | Smaller         |                  | Larger        |
| ratio          |                 |                  |               |
+----------------+-----------------+------------------+---------------+
| Pad type       | SMD             |                  | NSMD          |
+----------------+-----------------+------------------+---------------+
| Via type       | In-pad unfilled | In-pad filled    | Interstitial  |
|                |                 |                  | open          |
+----------------+-----------------+------------------+---------------+
| Via size, min. | \< 0.020" (\>   |                  | ≥ 0.020" (≤   |
| (aspect ratio) | 4:1)            |                  | 4:1)          |
+----------------+-----------------+------------------+---------------+
| Ball size      | Smaller         |                  | Larger        |
+----------------+-----------------+------------------+---------------+
| Stencil        | \< 0.006"       |                  | ≥ 0.006"      |
| thickness      |                 |                  |               |
+----------------+-----------------+------------------+---------------+
| Underfill      | Reworkable UF   | No UF            | N             |
|                |                 |                  | on-reworkable |
|                |                 |                  | UF            |
+----------------+-----------------+------------------+---------------+

**[Introduction]{.underline}**

Since BGA reliability varies significantly with package and assembly
architectures, understanding the architecture and inherent reliability
is critical to safe implementation of BGA's in space. This checklist is
designed to collect the data needed to adequately analyze the BGA part
selection, board design and installation process for suitability for use
in space flight hardware. The analysis may be done using existing
expertise (no specific method is detailed herein) or can be done by
purchasing the analysis from qualified organizations such as the CAVE
center at Auburn University or the CALCE center at the University of
Maryland. The checklist is based upon reference 1 in the list below and
reliability test data collected by NASA and the CAVE center. Additional
discussion of the architectural features of BGA's that influence
reliability can be found in the following
[http://nepp.nasa.gov](http://nepp.nasa.gov/) resources:

1\. [Placeholder for Pradeep Lall's Guidelines document]{.underline}

2\. Ball Grid Array Assembly Reliability, R. Ghaffarian, January 17,
2004,
http://nepp.nasa.gov/DocUploads/82697EAD-43DA-41D8-8494322006165BF7/NEPP-webex-present1-17-04A.pdf

3\. Technology Readiness Overview: Ball Grid Array and Chip Scale
Packaging, R. Ghaffarian, January 23, 2003,
http://nepp.nasa.gov/DocUploads/4D47B29A-4824-4DDD-8A21A4DE4ADADF89/Technology%20Readiness%20Overview%20BGA%20and%20CSP.pdf

4\. Ball Grid Array Reliability Assessment for Aerospace Applications,
R. Ghaffarian, Microelectronics Reliability Journal, Volume 39, August
10, 1998,
http://nepp.nasa.gov/DocUploads/CD467677-8023-44E3-A795CBCF2DECFF05/RG-MicroRel-1-99.pdf

5\. Shock and Thermal Cycling Synergism Effects on Reliability of CBGA
Assemblies, R. Ghaffarian, January 19, 2000,
http://nepp.nasa.gov/index_nasa.cfm/619/9A4F59B1-2CC9-46E8-ABED865E68B712AB/

6\. FEA Stress Analysis for the Comparison of BGA and CGA, Mark Fan,
September 17, 2001,
<http://nepp.nasa.gov/index_nasa.cfm/619/36E5103D-EEAC-4E98-80A2FDAB9AAC3EBF/>

## [Parts Selection]{.underline} 

## Internal Design

a.  What die configuration is used?

> Single die
>
> Multiple die (planar orientation)
>
> Multiple die (stacked orientation)
>
> Other:      
>
> *Rationale: The configuration of die in the package affects radiation
> susceptibility, mechanical properties, and thermal mass.*

b.  What is the internal interconnect method employed?

> Wire bond
>
> Gold
>
> Aluminum
>
> Other:      
>
> Flip chip
>
> TAB
>
> Other:      
>
> *Rationale: The internal connection method is often a determining
> factor in consideration of the absolute amount of thermal energy that
> can be applied to a package during reflow / rework, the amount of
> mechanical shock the components can sustain, the potential failure
> modes, and the reliability of the part to board interconnections.*

c.  What alloy are internal bump terminations (FCP, stack array, etc.)?

> Sn05Pb95
>
> Sn03Pb97
>
> Ni/Au
>
> Other:      
>
> Not Applicable (wire bond only)
>
> *Rationale: The composition of the internal bump terminations is often
> a determining factor in consideration of the absolute amount of
> thermal energy that can be applied to a package during reflow /
> rework.*

d.  What is the die orientation in the package?

> Cavity Up
>
> Cavity Down
>
> *Rationale: The die orientation in the package provides insight about
> thermal impedance and how to prepare the sample for radiation
> testing.*

e.  What is the die attach method used?

> Elastomeric
>
> Silver-Filled Epoxy
>
> Solder
>
> Other:      
>
> *Rationale: The die attach method has an effect on the overall
> reliability of the die / substrate interconnect, and is often a
> determining factor in consideration of the absolute amount of thermal
> energy that can be applied to a package during reflow / rework.*

f.  What is the die size (length, width, thickness)?

> Length:       mm (      in.)
>
> Width:       mm (      in.)
>
> Thickness:       mm (      in.)
>
> *Rationale: This information describes the die's physical attributes.*

g.  What is the die size to package body ratio?

> N/A -- Multiple die (see "m")
>
> Ratio:      
>
> *Rationale: The die to package ratio influences the thermal
> coefficient of expansion. The basic assumption is that the die is
> placed in the approximate center of the package cavity. Packages with
> multiple die respond differently. The reliability generally decreases
> with an increase of the die to package ratio. Packages with smaller
> die are preferred for applications with excessive thermal cycle
> exposure.*

h.  What is the die size to array ratio?

> N/A -- Multiple die (see "m")
>
> Ratio:      
>
> *Rationale: The die to array ratio influences the thermal coefficient
> of expansion. The basic assumption is that the die is placed in the
> approximate center of the array pattern. Packages with multiple die
> respond differently.*

i.  What are the size and type of the pads on the substrate?

>      
>
> *Rationale: The size of the pads in relation to ball size affects the
> overall reliability of the solder connection on the package side. Pad
> type influences the mechanical strength of the part-side solder joint
> due to differing solder joint geometries with pad type.*

j.  What is the substrate material and thickness?

>      
>
> *Rationale: The substrate material type and thickness affect how the
> device responds to thermal changes.*
>
> How many layers in the substrate?
>
> Layer count:      
>
> Unknown
>
> *Rationale: The number of layers in the substrate affects the
> stiffness of the package and strength of the copper in the vias.*

k.  What type is the substrate (i.e., rigid, flexible)?

> Rigid
>
> Flexible
>
> Other:      
>
> *Rationale: Flexible substrates are more prone to fatigue damage from
> thermal excursions.*

## External Design

a.  What is the package material?

> Ceramic
>
> Glass-Sealed Ceramic
>
> Metal-Sealed Ceramic
>
> Plastic
>
> Other:      
>
> *Rationale: The package material has a direct effect on thermal
> expansion, thermal dissipation, and radiation susceptibility.*

b.  If plastic, what is the moisture sensitivity level of the device
    (per J-STD-033) and how has the device been stored?

```{=html}
<!-- -->
```
(1) Moisture Sensitivity Level and Maximum Exposure Time @ ≤ +30°C / 60%
    RH

> 1 -- Unlimited (≤ +30°C / 85% RH)
>
> 2 -- 1 year
>
> 2a -- 4 weeks
>
> 3 -- 168 hours
>
> 4 -- 72 hours
>
> 5 -- 48 hours
>
> 5a -- 24 hours
>
> 6 -- Time specified on Label (TOL)

(2) Storage

> MBB -- Vendor
>
> MBB -- Repack
>
> Nitrogen-blanket Cabinet
>
> Other:      
>
> None
>
> *Rationale: Moisture sensitive components must be stored in Moisture
> Barrier Bag (MBB) or a controlled environment, such as a drying oven
> or nitrogen-blanket cabinet to prevent moisture-induced damage.*
>
> c\. If plastic, what is the filler content of the mold compound?
>
> Low
>
> High
>
> *Rationale: The filler content has an effect on the thermal
> reliability of a BGA package.*

d.  What type of termination array pattern does the device employ?

> Full Array Populated
>
> Even Row / Even Column
>
> Odd Row / Odd Column
>
> Staggered Pattern
>
> Peripheral Array / Zone Depopulated
>
> *Rationale: Question is describing the termination architecture /
> pattern, and assists in understanding how the die / chip size
> interacts with the CTE of the package.*

e.  Provide the following information concerning the part:

```{=html}
<!-- -->
```
1.  Length:       mm / (      in.)

2.  Width:       mm / (      in.)

3.  Thickness including ball/column (prior to reflow):       mm / (     
    in.)

4.  Number of I/O:      

5.  Pitch:      mm / (      in.)

6.  Ball/column diameter (prior to reflow):       mm / (      in.)

7.  Ball/column height (prior to reflow):       mm / (      in.)

8.  Package side pad surface finish:      

> *Rationale: Defines the package attributes.*

f.  What is the ball?

> In50Pb50
>
> Ni/Au
>
> Sn03Pb97
>
> Sn05Pb95
>
> Sn10Pb90
>
> Sn63Pb36Ag02
>
> Sn63Pb37
>
> Other:      
>
> *Rationale: The ball / column alloy is a factor in selecting the
> reflow temperature and reflow alloy.*

g.  Does the device employ thermal balls?

> \--Yes \--No
>
> *Rationale: Devices with thermal balls may require special processing
> during reflow, and require thermal vias and planes under the device.*

## [Reliability Assessment]{.underline}

1.  Has the exact device been thermally cycled in a daisy chained
    configuration?

> Yes
>
> No
>
> Explain:      

2.  Can device reliability be established by similarity to a device that
    has been tested?

> Yes
>
> No
>
> Explain:      

3.  If test data is not available publicly, then a copy of the report or
    the results should be provided, including the following data:

```{=html}
<!-- -->
```
1.  Thermal cycle profile/cycles to first failure

2.  Sample size

3.  Distribution of failure (e.g., Weibull, log normal)

4.  If test data was not used, then what method was used to predict
    reliability of the solder joints?

>      

5.  What is the CTE and modulus of each material used in the part and
    are these manufacturer provided or were they determined
    experimentally?

>      

6.  If determined experimentally, what method was used (e.g., DMA, TMA)

>      

## [PCB and Design Characteristics]{.underline}

1.  What is the mission / service environment?

> \--EVA
>
> \--Ground Support
>
> \--IVA
>
> \--Payloads
>
> *Rationale: This question defines the environment and mission.*

2.  What is the expected thermal range and cycles for the useful life of
    the assembly?

> Number of flights required: -1; -10; -100; -Other:      
>
> Estimated thermal cycles per Flight:      
>
> Flight Thermal Environment: -      °C to +     °C (-     °F to
> +     °F)
>
> Board Level Thermal Environment: -      °C to +     °C (-     °F to
> +     °F)
>
> Maximum thermal swing (Δ°T max):       °C (      °F)
>
> *Rationale: The mission life and thermal environment drive many of the
> printed circuit board (PCB) design decisions. The objective is to base
> design decisions on realistic mission and thermal profiles, rather
> than a default flight environment.*

3.  What is the board design type?

> Type 1 -- Single-sided Board
>
> Type 2 -- Double Sided Board
>
> Type 3 -- Multilayer board without blind or buried vias
>
> Type 4 -- Multilayer board with blind and/or buried vias
>
> Type 5 -- Multilayer, metal-core board without blind or buried vias
>
> Type 6 -- Multilayer, metal-core board with blind and/or buried vias
>
> Type X -- Multilayer with embedded passives (with/without metal-core,
> with/without blind and/or buried vias)
>
> Type Y -- Multilayer with embedded actives (with/without metal-core,
> with/without blind and/or buried vias)
>
> *Rationale: This question defines the printed circuit board
> architecture.*

4.  What is the board construction?

> Rigid
>
> Flexible
>
> Folded-Flexible
>
> Rigid-Flexible
>
> *Rationale: The type of laminate may define component mounting
> processes and workmanship requirements.*

5.  What is the board producability level?

> A -- Simple Through-Hole Technology (THT) only
>
> B -- Simple Surface Mount Technology (SMT) only
>
> C -- Simple Mixed Technology (SMT / THT)
>
> X -- Complex Mixed Technology (SMT / THT / FPT / BGA)
>
> Y -- Moderately Complex Mixed Technology (SMT / THT / FPT / BGA / µBGA
> / UFPT / CSP)
>
> Z -- Extremely Complex Mixed Technology (SMT / THT / FPT / BGA / µBGA
> / UFPT / CSP / TAB / FCP / CIB / COB / Embedded Active / Embedded
> Passive)
>
> *Rationale: This question defines the technology requirements driving
> the printed circuit board design.*

6.  What is the printed circuit board laminate and glass transition
    temperature (Tg)?

> BT-Epoxy /      
>
> Duroid /      
>
> FR4 /      
>
> FR5 /      
>
> Kapton /      
>
> Quartz /      
>
> Teflon /      
>
> Other:      
>
> *Rationale: The choice of laminate is defined by the mission's
> environmental requirements, and forces design trade-offs.*

7.  What is the board solderability finish?

> Electroplated Gold (Hard)
>
> Electroplated Nickel
>
> ENIG -- Electroless Nickel, Immersion Gold
>
> HASL -- Hot Air Solder Leveling
>
> I-Ag -- Immersion Silver
>
> I-Ni - Immersion Nickel
>
> I-Sn -- Immersion Tin
>
> OSP -- Organic Solderability Preservative
>
> SMOBC - Solder Mask Over Bare Copper
>
> Wire Bondable Gold (Soft)
>
> *Rationale: The finish processes used to preserve printed circuit
> board solderability may have an effect on solder assembly processes,
> overall reliability, and requirement for additional environmental
> protection (conformal coating).*

8.  What is the expected layer count, internal, and external copper
    weight?

> Number of layers:       Internal weight:       oz. External weight:
>       oz.
>
> *Rationale: Defines printed circuit board construction.*

9.  What is the minimum trace width and spacing?

> Trace width:       mm (      in.) Trace spacing:       mm (      in.)
>
> *Rationale: Trace width and spacing influence produce-ability and
> workmanship issues.*

10. What is the printed circuit board finished thickness?

>       mm /       in.
>
> *Rationale: Finished thickness influences aspects such as thermal
> expansion coefficient, thermal profile, thermal loading, BGA solder
> joint reliability, handling, drying, etc.*

11. What are the number of ground / power planes and the density of
    traces under the BGA?

> Power:      ; Ground:      ; Isolation:      ; Trace Density:      %
> (relative to full metallization)
>
> *Rationale: The density of metallization under the BGA influences the
> thermal load required during assembly / rework, thermal dissipation
> during operation, localized coefficient of expansion, and possible EMI
> abatement practices.*

12. How much clearance is there around the BGA(s)?

>       mm /       in.
>
> *Rationale: Design for Manufacturability (DfM) / Design for
> Inspectability (DfI) concern. Sufficient clearance must be provided in
> the design to allow for inspection, assembly / rework tooling, and to
> provide a thermal radiation buffer between adjacent components.*

13. What are the BGA pad sizes, types, and ratio to the ball diameter?

>      
>
> *Rationale: Pad to ball diameter ratio will define the amount of
> solder paste required, the expected ball-to-pad fillet profile**, and
> the ball-to-pad alignment tolerance / overhang risk.*

14. Are BGA pads solder-mask defined (SMD)?

> \--Yes \--No
>
> *Rationale: Solder Mask Defined (SMD) pads can affect ball-to-pad
> reliability and the ball-to-pad alignment tolerance / overhang risk.*

15. What type of vias are used and what is the worst case aspect ratio
    (per device/PCB)?

    a.  Average aspect ratio:      :1

    b.  Worst case aspect ratio:      :1

    c.  Are thermal vias used?

> \--Yes \--No

d.  Are vias in the pads?

> \--Yes \--No

e.  Are vias filled, tented, or plated over?

> \--Yes \--No
>
> If YES, specify material / process:
>
> If filled:      
>
> If tented:      
>
> If plated over:      
>
> Have materials been tested for outgassing? \--Yes \--No
>
> *Rationale: These questions address the design and use of vias which
> have a direct affect on overall assembly reliability.*

16. Who will be performing micro-section analysis on the printed circuit
    board coupons?

> PCB vendor
>
> Independent certified third party lab
>
> NASA Center Lab
>
> ARC (Ames Research Center)
>
> DFRC (Dryden Flight Research Center)
>
> GRC (Glenn Research Center)
>
> GSFC (Goddard Space Flight Center)
>
> JPL (Jet Propulsion Laboratory)
>
> JSC (Johnson Space Center)
>
> KSC (Kennedy Space Center)
>
> LaRC (Langley Research Center)
>
> MSFC (Marshall Space Flight Center)
>
> SSC (Stennis Space Center)

*Rationale: Coupons shall be included in the printed circuit board build
panel and shall comply with IPC-6012 \[4.0\], Tables 4-1 through 4-4.
Coupon analysis shall comply with IPC Class 3A requirements. All tested
and untested coupons shall be delivered as part of the procurement.*

17. What is the maximum expected CTE mismatch between the PCB and BGA?

>      ppm/°C

18. What is the CTE mediation method employed?

> Compliant layer
>
> Column grid
>
> TAB
>
> Underfill
>
> Other:      

19. What thermal management method is used for the BGA(s)?

> Convection
>
> Forced Convection (Heat sink w/ Fan)
>
> Heat Pump (Recirculating Liquid)
>
> Metal-core PCB
>
> Thermoelectric Module (TEM)
>
> Top-mounted Conduction (Heatsink / Coldplate)
>
> *Rationale: How is the component's thermal load going to be managed?
> Use of thermal management processes requires infrastructure planning.*

20. Will underfill (UF) material be used?

> \--Yes \--No
>
> If YES, specify material / application process:      
>
> Have materials been tested for outgassing? \--Yes \--No
>
> *Rationale: Prudent use of underfill has been demonstrated to
> significantly improve the MTBF of solder ball terminations, by a
> factor of 5X to 10X for fully populated plastic area array packages.
> Lack of repair capability must be agreed upon by customer.*

## [Manufacturing / Quality]{.underline}

1.  What are the previous experiences with comparable designs with this
    produce-ability rating?

>      
>
> *Rationale: This question is to allow the vendor to document previous
> experience with designs of comparable complexity.*

2.  Will any process samples of the printed circuit assembly (PCA) be
    subjected to DPA prior to approving the assembly process?

> \--Yes \--No
>
> Explain:      
>
> *Rationale: Destructive physical analysis (DPA) of special / unusual
> terminations may be required to verify effectiveness and reliability.*

3.  How is BGA package warping controlled during reflow?

>      
>
> *Rationale: Warpage of the BGA package during reflow is a known
> reliability concern.*

4.  What process / verification method is used for ensuring that UF is
    free of voids or micro-cracks?

>      

5.  Will C-SAM be employed?

> \--Yes \--No
>
> Explain:      

6.  Are wetting verification runs required for each bare board?

> \--Yes \--No
>
> Explain:      

7.  What method will be used to apply solder paste?

> Dispensing Process
>
> Automated
>
> Manual
>
> Stencil Process
>
> Laser
>
> Electroformed
>
> Chemical Etch
>
> Screen
>
> Other:      
>
> *Rationale: Describes the process used to apply solder paste to the
> printed circuit board (PCB).*

8.  What size mesh solder solids are to be used for this application?

> Mesh size:      
>
> Previous experience:      

9.  What type of inspection system is used?

> X-ray:       Define type of x-ray including resolution:
>
> Visual:      
>
> Comments:      
>
> *Rationale: Defines the type of inspection that will be used. Each
> type has benefits and limitations.*

10. Are the ball / column terminations 100% inspected for voids/wetting?

> \--Yes \--No
>
> Explain:      
>
> *Rationale: Defines the level of inspection.*

11. What criteria are used for determining acceptable level of voiding?

> Explain:      

12. Are the boards cleaned and baked before UF is applied?

> \--Yes \--No

## Explain: