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| ![](media/image1.emf){width="0.9770833333333333in"                    |
| height="0.8333333333333334in"} **Fermilab**                           |
|                                                                       |
| **Particle Physics Division/CDF Upgrade Project**                     |
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**DRAFT**

**Specification for**

**Trigger Sum Cable Receiver Module**

**(TSCR)**

T. M. Shaw

11/7/95

revised

T. M. Shaw, J. Perveiler

6/16/97

1/8/99

1.0 Introduction

A module, the Trigger Sum Cable Receiver (TSCR), will be used to receive
\"trigger sums\" from cables. This board will be of a purely diagnostic
purpose - it will be used to test cable, transceiver and connector
integrity. In normal operation, trigger sums will be driven by the ADMEM
boards and received by the DRAW boards produced by the University of
Chicago.

2.0 Features

A block diagram of the board is shown in Figure 1. The board features a
group of eight FIFO blocks which can be read or written over VMEbus. The
board can be put into a special mode which causes the input of the FIFOs
to be driven by the cables.

**Receivers** - Trigger sum cable receivers will be LVDS.

**Eight Channels** - The board will provide the ability to receive 8
channels worth of Trigger Sums.

**Shield Ground** - The cable shield will be optionally grounded to the
board through a jumper.

**Clock Source** - The onboard clock comes from the backplane of the CDF
Custom Crate.

**8K deep FIFOs** - These FIFOs are read/writeable over VMEbus and can
also receive data from front panel cables.

When the FIFOs are to be filled with cable data and the Control Register
bit "B0 MODE" is set, they will begin filling only when a Beam_zero
signal occurs following a Halt-Recover-Run sequence. If "B0 MODE" bit is
not set, the FIFOs will begin filling immediately. In either mode, the
FIFOs will be written to until they are full.

Independent clocks, each with their own delay, will drive the input
logic of the FIFOs. This feature allows for differing lengths on the
trigger sum cables.

3.0 Cable/Connector Pinout of Trigger Sum Cables

Pin Signal Pin Signal

1 A(0) 2 A\*(0)

3 A(1) 4 A\*(1)

5 A(2) 6 A\*(2)

7 A(3) 8 A\*(3)

9 A(4) 10 A\*(4)

11 A(5) 12 A\*(5)

13 A(6) 14 A\*(6)

15 A(7) 16 A\*(7)

17 A(8) 18 A\*(8)

19 A(9) 20 A\*(9)

4.0 VME Slave Interface

The TSCR will implement a modified version of a VMEbus slave interface.
Only 32 bit aligned data transfers will be supported; these may be
either single word transfers or block transfers. Only extended (32-bit)
addressing modes will be supported. All boards will be assigned a unique
geographical address through use of backplane pins on the CDF Custom J2
backplane. TSCR modules will respond to the following address modifier
codes: 09, and 0B.

![](media/image2.emf)

Figure 1 Block Diagram of TSCR

**Memory Map**

YY00 0000 Diagnostic Register (32 bit Read/Write)

YY00 0004 Control (32 bit Read/Write)

**[Bit]{.underline}** **[Function]{.underline}**

0 FIFO 0 Reset\* (toggle bit low, then return to high state to reset)

1 FIFO 1 Reset\*

1 FIFO 2 Reset\*

3 FIFO 3 Reset\*

4 FIFO 4 Reset\*

5 FIFO 5 Reset\*

6 FIFO 6 Reset\*

7 FIFO 7 Reset\*

8-28 Undefined

29 B0 Mode

30 Software Reset (currently unused by module)

31 Enable VMEbus Path to FIFOs

YY00 0008 Status Register (32 bit Read)

**[Bit]{.underline}** **[Function]{.underline}**

0 FIFO 0 HF\*

1 FIFO 0 EF\*

2 FIFO 0 PAFE\*

3 Undefined

4 FIFO 1 HF\*

5 FIFO 1 EF\*

6 FIFO 1 PAFE\*

7 Undefined

8 FIFO 2 HF\*

9 FIFO 2 EF\*

10 FIFO 2 PAFE\*

11 Undefined

12 FIFO 3 HF\*

13 FIFO 3 EF\*

14 FIFO 3 PAFE\*

15 Undefined

16 FIFO 4 HF\*

17 FIFO 4 EF\*

18 FIFO 4 PAFE\*

19 Undefined

20 FIFO 5 HF\*

21 FIFO 5 EF\*

22 FIFO 5 PAFE\*

23 Undefined

24 FIFO 6 HF\*

25 FIFO 6 EF\*

26 FIFO 6 PAFE\*

27 Undefined

28 FIFO 7 HF\*

29 FIFO 7 EF\*

30 FIFO 7 PAFE\*

31 Undefined

YY00 000C MC Phase delay Register (32 bit Read/Write)

**[Bit]{.underline}** **[Function]{.underline}**

0 Delay(0) Channel 0

1 Delay(1) Channel 0

2 Delay(2) Channel 0

3 Undefined

4 Delay(0) Channel 1

5 Delay(1) Channel 1

6 Delay(2) Channel 1

7 Undefined

8 Delay(0) Channel 2

9 Delay(1) Channel 2

10 Delay(2) Channel 2

11 Undefined

12 Delay(0) Channel 3

13 Delay(1) Channel 3

14 Delay(2) Channel 3

15 Undefined

16 Delay(0) Channel 4

17 Delay(1) Channel 4

18 Delay(2) Channel 4

19 Undefined

20 Delay(0) Channel 5

21 Delay(1) Channel 5

22 Delay(2) Channel 5

23 Undefined

24 Delay(0) Channel 6

25 Delay(1) Channel 6

26 Delay(2) Channel 6

27 Undefined

28 Delay(0) Channel 7

29 Delay(1) Channel 7

30 Delay(2) Channel 7

31 Undefined

YY10 0020 - YY10 009C ID PROM (upper 8 bits)

YY20 0000 - YY20 7FFF FIFO 0 (Bits 31:16) Bits (25:16) represent Trigger
Bits (9:0)

YY21 0000 - YY21 7FFF FIFO 1

YY22 0000 - YY22 7FFF FIFO 2

YY23 0000 - YY23 7FFF FIFO 3

YY24 0000 - YY24 7FFF FIFO 4

YY25 0000 - YY25 7FFF FIFO 5

YY26 0000 - YY26 7FFF FIFO 6

YY27 0000 - YY27 7FFF FIFO 7

**YY** is the VME geographical address of the TSCR.