**Barrier Coatings and Stability of Thin Film Solar Cells**

**1st Quarterly Report - Phase II:**

**September 1, 2003 \-- November 30, 2003**

**NREL Subcontract: 44575A**

**Subcontractor: Pacific Northwest National Laboratory**

**Principal Investigator: Larry C. Olsen**

**1. OBJECTIVES/APPROACH**

The key objectives of this program are to develop low cost barrier
coatings for CdTe and CIS solar cells and to develop an improved
understanding of mechanisms affecting the stability of CdTe solar cells.
The scope of this work entails investigation of multilayer, barrier
coatings for solar cells and studies of stability issues for CdTe solar
cells. The work is structured into three main tasks: (1) Barrier layer
coatings for CdTe and CIS solar cells; (2) Modeling of mechanisms
influencing CdTe stability; (3) Experimental studies of CdTe cells
supporting Tasks 1 and 2.

**2. PROGRESS FOR THIS REPORTING PERIOD**

**2.1 Accelerated Testing of SSI Circuits**

Data were obtained for a 10 cm x 10 cm SSI circuit that had a slightly
thinner coating than previously used. The process developed for
depositing barrier coatings for Shell Solar CIGSS devices consists of
first applying a relatively thick polymer layer to provide a planarizing
surface onto which to deposit the first oxide layer. Formation of the
thick polymer + oxide layer (subsequently referred to as the base dyad)
is followed by deposition of several dyads, each dyad consisting of a
polymer layer plus oxide. Previously reported accelerated lifetest data
were obtained for circuits coated with four dyads on top of the base
dyad (subsequently referred to as a five dyad coating). Figure 1
describes the barrier coating applied to Circuit \# S4079-22-8. This
circuit has been subjected to accelerated testing at 60ºC/90% RH for
1826 hours without significant degradation of performance. Efficiency
versus time for this circuit is shown in Figure 2.

![](media/image1.png){width="5.4375in" height="2.5833333333333335in"}

**Figure 1. Illustration of a barrier coating formed by adding three
dyads to the base dyad.**

![](media/image2.wmf){width="5.09375in" height="3.5625in"}

**Figure 2. Efficiency versus time for SSI Circuit in an environment of
60ºC and 90% RH.**

Circuit characteristics are shown in Table 1. Although it is satisfying
that very good performance is achieved with a four dyad coating, it is
particularly significant that the PNNL barrier coating enables the SSI
circuit to undergo 1826 hours of accelerated testing with minimal
reduction in circuit performance. If we consider the change in circuit
performance relative to performance prior to coating deposition, after
1826 hours at 60/90 the efficiency only decreased from 10.3 % to

10.0 %. Note that the value of J~sc~ and FF actually increased while Voc
decreased slightly.

**2.2 Studies With SSI Mini-Modules**

Current studies of SSI circuits are being carried out with Shell\'s new
mini-modules shown in Figure 3. Shell\'s 10 cm x 10 cm circuits that
were provided for barrier coating studies have one cm wide deletion
regions along each edge of the glass substrate. It is clear from results
of accelerated tests and from PNNL work with coatings for OLEDs that the
width of one cm provides a very good \'edge seal.\' The situation with
the min-modules is quite different. There is a 2 mm deletion region
around the mini-module shown in Figure 3. As noted, the cells along two
sides are inactive. As indicated, we can delete material from two of the
edges to establish an improved \'edge seal,\' but the two edges with
contacts can not be deleted completely. Evaluation of barrier coating
properties

**Table 1 \-- Circuit Characteristics For S4079-22-8 ^\*^**

  ------------- ---------------- -------- ---------------- ------------ -----------------
  **V~oc~**     **J~sc~**        **FF**   **Efficiency**   **Time**     **Measurement**

  **(Volts)**   **(mA/cm^2^)**   **( %    **( % )**        **( Hrs@     **Date**
                                 )**                       60/90)**     

                                                                        

  5.75          31.91            56.1     10.3             before       9/26/2003
                                                           cleaning     

  5.74          31.87            56.5     10.3             cleaned      9/3/2003

  5.68          31.96            58.3     10.6             coated       9/3/2003

  5.64          31.86            58.4     10.5             50h          9/5/2003

  5.57          31.86            58.3     10.3             111h         9/8/2003

  5.6           32.01            58.7     10.5             166h         9/10/2003

  5.61          32.21            58.4     10.6             266h         9/14/2003

  5.61          31.88            58.8     10.5             360h         9/18/2003

  5.61          32.3             58.4     10.6             460h         9/23/2003

  5.59          32.06            59.1     10.6             530h         9/26/2003

  5.59          31.86            58.8     10.5             595h         9/29/2003

  5.59          31.56            59.5     10.5             660h         10/2/2003

  5.58          31.73            59.2     10.5             775h         10/6/2003

  5.59          31.37            58.6     10.3             851h         10/9/2003

  5.56          31.15            57.8     10               1002h        10/15/2003

  5.52          31.1             56.2     9.65             1125h        10/20/2003

  5.38          32.32            55.4     9.64             1160h        10/22/2003

  5.56          30.99            58.5     10.1             1210h        10/24/2003

  5.57          30.91            58.8     10.1             1282h        10/28/2003

  5.56          31.01            57.1     10.1             1353h        10/31/2003

  5.58          31.25            58.3     10.2             1425h        11/3/2003

  5.57          31.56            57.4     10.1             1502h        11/7/2003

  5.53          31.1             57.7     9.93             1574h        11/10/2003

  5.54          31.48            56.8     9.91             1664h        11/14/2003

  5.55          32.04            56.3     10               1826h        11/21/2003
  ------------- ---------------- -------- ---------------- ------------ -----------------

\* J~sc~ refers total Circuit short circuit current divided by
individual cell area of 5.71 cm^2^.

based on results for mini-modules may be more difficult but studies will
be conducted because of their availability. SSI will probably continue
to provide 10 cm x 10 cm circuits as well. It should be noted that PNNL
is developing approaches to edge seals for applications to OLEDs.

**2.3 Effects Of Damp Heat On Bare SSI Circuits**

As reported previously, one SSI circuit was subjected to 60/90
accelerated testing that did not have a barrier coating \-- that is, a
bare circuit. Values of I-V properties were plotted versus time in the
last quarterly report. All parameters were affected significantly with
J~sc~ being affected the most. One significant effect of the stress

![](media/image3.png){width="4.749305555555556in"
height="3.3361111111111112in"}

**Figure 3**. The SSI 6 cm x 6 cm mini-module.

conditions is that the effective series resistance of the circuit
increases. However, since V~oc~ decreases significantly over the first
few hundred hours, it would appear that current-loss mechanisms
associated with the junction are also affected. The effect of the
accelerated tests on current loss mechanisms is discussed in this
report.

We have concentrated on analysis of dark data in this report.
Measurement of Circuit properties consists of measuring the total
current supplied to (or produced by) a circuit versus voltage across the
circuit terminals. Each circuit consists of ten cells connected in
series, each one approximately 8 cm x 0.7 cm. We have assumed that the
ten cells are identical, and characterized by individual device
parameters I~o~, A and R~s~. We ignore shunt resistance as a parameter
(which means that such effects are incorporated in I~o~ and A) and
assume that the series resistance associated with the external contacts
is negligible. Thus the assumed model is described by Figure 4. We
consider ranges of data where a single current mechanism is dominant.

We have determined the J and V for an individual cell from

J = I / (5.71) and V = V~circuit~ / 10 (1)

where 5.71 cm^2^ is the individual cell area, and 10 is the number of
cells in series.

![](media/image4.png){width="4.0in" height="2.4479166666666665in"}

**Figure 4.** Assumed equivalent circuit for 10 cm x 10 cm circuit.

Assuming that there is a dominant current loss mechanism, we write

J = J~o~ \[ exp(V~jct~/AkT\] (2)

where V~jct~ = V - R~s~ I = V - (5.71) R~s~ J (3)

The value of series resistance is determined by considering a plot of J
vs V~jct~ for a range of values for R~s\ ,~ and selecting the value that
leads to a straight line for J vs V~jct~ on a semilog plot. Figures 5A
and 5B summarize results for J-V analyses for Circuit S4079-22-3. Figure
5A gives the measured values for J vs V where J is the total current ( I
) divided by 5.71 cm^2^, and V is V~circuit~/10. At beginning-of-life
(BOL), the I-V data exhibit typical characteristics for a good quality
SSI CIGSS cell or circuit, that is, two current mechanisms are evident
with the transition occurring in the range of 0.35 to 0.4 .

Volts. After 1000 hours in a 60/90 environment, the bare circuit is
characterized by much larger current losses.

Figure 5B shows \'adjusted\' J-V characteristics. Series resistance
values were determined that provides a straight line on the semilog plot
for the large voltage mechanism at BOL conditions, and for most of the
voltage range for the 1000 hour case. Rs values of 1.8 ohms and 3.6 ohms
were determined as appropriate for the BOL and 1000 hour cases. These
values correspond to estimated values for one cm^2^ of junction. One of
the key results of this analysis is that the degradation is not simply
explained by a degradation of the series resistance associated with each
cell. In fact, the effective Jo accounts for a significant part of the
degradation, or in other words, it would appear that current loss
mechanisms due to recombination in the junction region account for a
significant part of the degradation. The straight line portion of the
adjusted curves are fit by parameters given in Table 2. It is
interesting that the A-value is essentially the same for the degraded
J-V curve and the upper mechanism at BOL. However, the J~o~-value

**(A)**

![](media/image5.wmf){width="4.542361111111111in"
height="3.4229166666666666in"}

**(B)**

![](media/image6.wmf){width="4.501388888888889in"
height="3.407638888888889in"}

**Figure 5.** (A) Measured dark J-V characteristics for bare circuit at
beginning of life (BOL) and after 1000 hours in environment of 60ºC and
90% relative humidity.

increased from 1.5x10-8 A/cm^2^ to 5x10-6 A/cm^2^ as a result of the
stress. It is tempting to interpret these results as follows: the stress
increases the density of recombination centers associated with the
A-value for 1.8 to 1.88 by a factor on the order of 400.

Clearly, we have tried to extract a lot of information from these I-V
characteristics. I think we can make two general conclusions: (1) the
average series resistance per cell increases as a result of the stress,
and is probably due to effects of moisture on ZnO; (2) the stress also
affects the junction region such that recombination centers leading to
current losses are increased. It is also tempting to postulate that the
effect of the moisture on this cell was to increase the density of
recombination centers in the depletion region that contribute to the
dominant current loss mechanism. In particular, since the A-factor is
essentially the same at BOL and after 1826 hours of stress, it appears
that the dominant recombination center at BOL is greatly increased as a
result of the stress.

**Table 2 \-- I-V Parameters For The SSI Bare Cell, S4079-22-3**

At BOL R~s~ = 1.8 ohms A = 1.80 J0 = 1.5E-8 A/cm^2^

After 1000 hrs R~s~ = 3.6 ohms A = 1.88 J0 = 5E-6 A/cm^2^

at 60/90

**2.4** **Module Reliability Meeting**

Dr. Olsen attended the Module team meeting in Albuquerque, September 18
and 19, 2003. Results for the first three quarters of this project were
presented. Discussions were held with several solar cells industries,
and plans made for future interactions. The meeting was very beneficial
for defining problems faced by manufacturers, and will be of tremendous
help in determining the direction of future work.