AFE8 Board Qualification Criteria

> Fred Borcherding / Jerry Blazey

D0 Electronics Group

> This note defines the criteria to be met by a single pair of left- and
> right-handed AFE8 prototype boards. Production of the AFE8s requires
> satisfaction of these criteria.

# General Requirements. 

AFE8 boards must: supply bias voltage to the VLPC chips, monitor and
regulate the cassette temperature, supply discriminated signals to the
trigger and readout, and supply analog hit information for calibration.
The specifications in this document are given in fC delivered to the
AFE8 board from the VLPC. With a VLPC gain of about 40K and a nominal
bias voltage setting, 7fC roughly translates to one PE.

## Bias Voltage. 

The bias settings must have a resolution and stability of \< 50mV.

## Temperature Control. 

Temperatures stable to \<100 mK after calibration.

The following specifications must be performed (1) on the LAB3 test
cryostat, (2) with operating cryogenics and bias controls, (3) with an
operating matching board (both a LHB and RHB must be present), and (4)
with a single set of threshold voltages for all channels of a single
SIFT.

## Discriminated Signals. 

On a single AFE8, data will be collected from each MCM with a patterned
light mask such that one channel out of four is exposed. The exposed
channels will be illuminated with an average of 1.5 PE. Thresholds shall
be set such that the discriminator rate for the unexposed channels on a
single MCM averages 0.5%. The variance of the 128 thresholds will be
calculated and used to simulate the expected efficiency of the track
trigger. This efficiency must be acceptable for the boards to be
approved.

With these fixed thresholds and after five days uninterrupted running
the firing rates must not increase by more than a factor of two.

The performance must not degrade with the addition of a 20MHz
background.

The transmission to the DFE must have an error rate of less then 0.1%.
That is discriminator output must be transmitted on the proper output
link, line, and time slice with errors less than 0.1%. It must do this
with 53MHz link speed.

The discriminated data must be sampled, stored, and transferred to the
sequencer for L3 readout with less than a 0.1% error rate per full data
set. The information transferred must imitate the SVX chip readout such
that the sequencer correctly receives and transmits this to the VRB. The
information must include address and data. The transfer of the complete
set of bits of data plus address information must be less than 8us.

## Fiber Analog Information. 

The AFE8 must be able to add channel amplitude information through the
SVX chip to the sequencer readout. This can be requested dynamically
though a command from the online control system. The data must be of
sufficient quality such that fitting routines can separate the first and
second photoelectron peaks for greater than 50% of the channels for each
MCM. This must be done for low and high gain cassettes

The system must be able to transfer the data without readout errors less
than 0.1%. No information or should be lost, bits dropped, or signal
variations introduced in the transfer. Readout completion must occur
before completion of the SMT readout.

.

## Mechanical Criteria.

Mechanical specifications must be met with a fully populated and
operating LHB and a fully populated and operating RHB. Before and after
reaching thermal equilibrium both boards mounted together must (1)
properly mate with a cassette including both the back plane connectors
and the high-density connectors along the bottom edge and (2) the two
boards must also be mounted without contact. In addition (3) two
adjacent boards each belonging to two different but adjacent cassettes
must be mounted without contact.

**Specification Checklist**

  ------------------------------------------------- ---------------------
  **Requirement**                                   **Date Complete**

                                                    

  **Bias Voltage**                                  

  50 mV resolution                                  14-Mar-01

  50 mV stability                                   

                                                    

  **Temperature Control**                           

  100 mK stability                                  

                                                    

  **Discriminated Signals**                         

  Variance of 128 signals                           

  Trigger Simulation Complete                       

  DFE Transmission Error Free                       14-Mar-01

  SEQ Transmission Error Free, \< 8 us              

  20 MHz Pulser Test \*                             

  Five day stability \*                             

                                                    

  **Analog Information**                            

  SEQ Transmission Error Free, \< 8 us              

  Fit 50% channels, high gain                       

  Fit 50% channels, low gain \*                     

                                                    

  **Mechanical**                                    

  Properly Seated                                   

  No contact intracryostat                          

  No contact intercryostat                          

                                                    

  \* Not required                                   
  ------------------------------------------------- ---------------------