**July 9, 1999**

**Silicon Subsystem Report**

**June 1999**

**Subsystem Manager's Summary (M. Gilchriese)**

[Cost and Schedule Summary Status]{.underline}

Milestones corresponding to the baseline schedule are marked with a \*.
Additional milestones are included, and will be included, as needed to
monitor progress

1.1.1 Pixel System

Costs are within allocated limits but funding for the mechanics
activities, particularly manpower, is becoming very tight. There have
been 1-2 month delays in the completion of fabrication of prototype
parts for the first full-disk prototype and for the first panels of the
prototype frame. In both cases, this is the result of manufacturing
errors on the part of the vendors involved and is expected to be
corrected at no cost to the project. The design of the 2^nd^ prototype
sensors is complete after small modifications were made following pixel
meetings early in June. Fabrication should begin shortly. Test beam
results from May continue to validate the baseline design choice for the
sensors. Preparation are underway for a Final Design Review of the
sensors. The submission of the first rad-hard prototype chip, FE-D, has
been further delayed until the end of July. The additional delay results
in part from the need to redesign a critical part of the circuitry that
was found by simulation to be inadequate after irradiation. And in part
from the completion of careful measurements of the proposed front-end at
LBNL that indicate inadequate time dispersion across the pixel array.
The cause of this dispersion is not fully understood and cannot, at the
moment, be reproduced in simulation. The designer of this block at
Marseille is attempting to understand the problem. This is not a fatal
problem at this prototype stage and so we will not wait for a full
understanding of this problem before submitting FE-D. The agreements
needed to allow European collaborators access to the Honeywell SoI
process were resubmitted by Honeywell to the State Department in
mid-June, after making extensive changes requested by DoD. Honeywell
estimates that it will take 12-20 weeks for approval. This is a major
problem for the design of FE-H and a fallback plan is under development
for discussion in early July, but the only possibilities are either a
very substantial delay or the assumption of nearly full responsibility
in the next some months by the U.S. team that has access to the design
rules. Work is proceeding at Ohio State State on a prototype rad-hard
version of the optical driver/receiver chips. These will be included in
the FE-D submission, as will a version of the MCC chip and some rad-hard
LVDS drives so that irradiation tests can be done with current
single-chip PC support boards. The fabrication of the next flex hybrid
prototypes(1.x) has been delayed by 4-6 weeks by the U.S. vendor. They
have started two lots but have had to scrap both because of processing
problems, neither claimed to be fundamental. Fabrication at CERN has
been delayed by the lack of material on order from the US. As a result,
it is very unlikely that flex modules with these new hybrids will be
ready in time for the July test beam run. In addition, the printed
circuit cards used to hold bare modules(those without flex hybrids that
serve as reference for performance measurements) that have been made in
Italy have substantial yield problems and the U.S. has been asked to
find an alternative vendor(and pay for the boards). A practice wafer
thinning test was completed unsuccessfully with a California vendor that
had previously thinned wafers successfully. Alternative vendors have
been found and additional practice wafers are under fabrication in
Berlin for this purpose. The first serious design work on module
assembly tooling started in June under the direction of a new engineer
recently liberated from BaBar. Finally, discussions are continuing with
our Canadian colleagues regarding coordination of module assembly and
other work in North America.

1.1.2 Silicon Strip System

A BCP was submitted and approved to accelerate the fabrication of ABCD
and ABC, and to provide additional test engineering and equipment for
these chips. Processing of the revised ABCD wafers was completed by
Temic but their measurements of process monitors indicated that at least
four items were out of specification. Although these particular items
are not expected to impact the performance significantly of the ABCD, it
is clearly not desirable to qualify a vendor based on out-of-spec
wafers. Thus the SCT group has entered into a negotiation with Temic to
(a) have them reprocess the ABCD wafers ASAP but (b) get one or two of
the out of spec wafers to test in any case to get an early look and not
wait for the reprocessing. As this report is being written, two ABCD
wafers have just been delivered to CERN for testing and negotiations
with Temic will occur in mid-July after a quick look at these wafers.
The ABC fabrication is still on track for delivery in early August. The
source of the design error in the Read-Out-Controller in the new ABC is
known(see the detailed text) and it is hoped that the corrected version
(present in the ABCD) can be already integrated into a new layout and
verified before the ABC returns from the vendor to get a head start.
Doing this depends critically on the availability of IC manpower at RAL,
which is uncertain. Tests of CAFE-P continue to be good and a two-chip
module connecting CAFE-Ps to detectors along with older digital
chips(CDPs from the SSC era) is under fabrication. The design of the
high speed (100 MHz) test system for ABC(and ABCD) is well advanced and
some parts are on order. Beryllia hybrids for the CAFE/ABC are on order
with two vendors and we have agreed to fabricate additional hybrids (on
a cheaper substrate) for radiation tests only with a third vendor with
whom there is substantial experience. Work is underway to fabricate the
few modules needed to test the ICs when they arrive. Renovations to
provide two clean rooms for production module assembly are now in full
gear and on schedule to be completed by September.

1.1.3 ReadOut Driver System

A meeting was help at CERN on June 2 to review the state of the SCT off
detector electronics. Representatives of all the ROD interfaces were
present (timing interface module, ROD crate processor, back of the crate
card (optical interface), and ROD software. Status presentations on each
of the areas were presented. The exchange was of importance for many
details were flushed out. It is clear that the interface definitions
need updating. Completing the interface definitions is essential to the
ROD development. There will be a follow up meeting in July to complete
the interface definitions. This will be an ongoing effort.

Progress has been made on the Architecture and simulation code. See the
details below:

Latency

We agreed to several small changes in the latency. John Lane has and is
making a list of the latencies. John should distribute this list for our
review and corrections if any. It was agreed that all free latency be
placed in Alex's latency contingency list and that we apply for any
latency that we need in the future. It is clear that this will be an
area of ongoing discussion as design details may change the predictions
of latency. The current status is that Alex Grillo has about 5.5 clock
ticks (out of 132) of latency in contingency.

Read Out Driver (ROD)

The ROD design and schedule was presented. The schedule was agreed to
for the ROB interface cards. They will also adopt a similar schedule.
This is important because these interface cards are needed to test the
complete functionality of the ROD. The ROD discussion was centered
around the following items.

ROD Item 1: The buffer in the ROD continues to fill when back

pressure is exerted by the S-link.

ROD Item 2: The number of links in the ROD is not determined. There is a
conviction on the part of the off detector SCT groups that that ROD
should have the same safety factor as the front end chips (2%
occupancy).

ROD Item 3: What embedded processor functionality is in the ROD? It was
generally agreed that the ROD should contain primitives that allow the
higher intelligence in the system to command the ROB to perform
operation such as calibration, configuration and data taking.

ROD Item 4: What is a reasonable schedule? There was general agreement
that the proposed schedule was reasonable. This schedule produced
debugged cards in the Feb. 2000 time frame. Then six months are needed
to evaluate the functionality of the prototype ROD by the SCT community.
The number of cards produced will be determined before Feb. 2000 as the
schedule and needs for evaluation and module testing is better
understood.

ROD Crate Controller (RCC)

The RCC functionality was presented. The RCC discussion was centered

around the following items.

RCC Item 1: There was general agreement that pixel software will be
similar to the SCT software and that it should be investigated if a
common effort can be arranged.

RCC Item 2: What are the stages of SCT off detector software
development? There was general agreement that the software would proceed
in three stages.

The first stage is the development of a stand alone version of the SCT
off detector electronics software that relies on a crate processor or
National Instruments VME Interface. This system (ROD test stand) is
intended to provide the functionality to test and debug the ROD and RCC
and in a later phase test the BOC and TIM. Initial test will best be
done in the US. The UK personnel will contribute software for the
initial tests. Test systems will be set up in the UK and US. The UK
testing will help considerably in the debugging of the ROD

The second stage is to develop the software for external user and model
tests of the ROD. The user feed back is essential to the development of
the off detector electronics production models.

The third stage is to develop the SCT off detector electronics software

to run under the ATLAS DAQ. This software development is at least a

year in the future. The RCC group will provide the software.

J.Hill was proposed and agreed as responsible for RCC software and
overall software architecture issues.

Back Of Crate (BOC) (Optical interface to the front end modules)

The BOC functionality was presented. The BOC discussion was centered

around the following items.

BOC Item 1: The current chips being fabricated (if they work as

expected) for the BOC card should be the final ones. Only production

runs will follow with little to no chip development. This is important
to help

meet that schedule constraints.

BOC Item 2: VCSELs available today are in groups of 4 and require a

circuit such as a current mirror. VCSELs in groups of 12 that do not

need the current mirror will be available in the future, but no

confirmed time scale is known.

BOC Item 3: Timing jitters of the clock to the BOC need clarification.

Roy Wastie will find and distribute the information. This issue is, how
is the clock distributed from the TIM to the BOC card?

Timing Interface Module (TIM)

The TIM functionality was presented. The TIM discussion was centered

around the following items.

TIM Item 1: The TIM schedule is for the one TIM to be available by
February of 2000. Three PC cards will be in reserve. There is a need for
4 cards identified at this time.

TIM Item 2: The TIM will be a 9U VME card. This is needed to connect

to the clock signals on the P3 back plane.

TIM Item 3: The pins connections from the TIM to the VME back plane are
not completely identified at this time. This needs to be completed so
that the design of the card will not suffer from this lack of
definition.

General Technical Items:

The interface documents need to be updated.

The description of each card in the SCT Off Detector Electronics needs
updating. The crate configuration and rack space needs to be understood
so that there are no surprises in the future.

DC power available from the crate needs understanding.

More communication with the ROB, trigger and DAQ needs to take place.

Latency is currently 128 clock ticks with 2.5 contingency, compared to a

pipeline of 132 with 4 contingency required by Alex.

Richard Jared was proposed and agreed to be overall SCT off detector
electronic project leader. Andy Parker agreed to help where possible,
especially with attendance at European meetings.

Architecture of the ROD is nearing completion. The ROD will have FPGAs
in the data path augmented by DSPs to perform monitoring and
calibration. The SCT off detector meeting in July will be used to obtain
the required user perspectives in the architecture. There is not
expected to be major changes that result from the meeting.

Simulation of the SCT ROD have been completed. The simulation show that
96 links with a triple gather can meet the requirements. A 72 link rod
will also meet the requirements with added safety. The selection is
expected to be made at the July meeting (subject to concurrence of the
SCT community. Pixel ROD simulation is in progress. This study is to
determine the number of links that will fix the bandwidth. It is planned
that the pixel ROD will be a partially loaded card that meets the need
of the pixel bandwidth.

Test beam support is continuing at a low level

# Detailed Reports

1.1.1 Pixel System

1.1.1.1 Mechanics (E. Anderssen, D. Bintinger, M. Gilchriese)

  ---------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}     [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*ID Eng. Review at CERN     20-Oct-98                20-Oct-98                                        Done

  Select prototype ring        1-Nov-98                 1-Feb-99                                         Done
  concept                                                                                                

  Select materials for frame   15-Mar-99                7-Apr-99                                         Done
  proto.                                                                                                 

  Complete fab 1^st^ prototype 1-Apr-99                 30-Jun-99                31-Jul-99               Delay
  ring                                                                                                   

  Complete frame Phase I       1-Jul-99                 1-Jul-99                 31-Jul-99               Delay

  Complete fab 1^st^ prototype 1-Jul-99                 1-Jul-99                 31-Aug-99               Delay
  disk                                                                                                   

  \*Select sector baseline     1-Sep-99                 1-Sep-99                 1-Sep-99                OK
  concept                                                                                                

  \*Module attachment CDR      1-Sep-99                 1-Sep-99                 1-Sep-99                OK

  \*Compl test of 5-disk       1-Sep-99                 1-Sep-99                 1-Sep-99                OK
  prototypes                                                                                             

  Complete frame Phase II      1-Oct-99                 1-Oct-99                 1-Oct-99                OK

  Complete frame Phase III     1-Feb-00                 1-Feb-00                 1-Feb-00                OK
  ---------------------------- ------------------------ ------------------------ ----------------------- ----------------------

LBNL

1.1.1.1.1 Design

Design studies for the overall pixel support frame continue by Hytec,
Inc. FEA models of support frame panels have been updated to be compared
to measurements. New disk layout studies commenced to investigate disk
sectors for disks with 66 and 54 modules versus 72 and 60 modules The
new disk layout will be compatible with the revised pixel barrel layout
accepted at the June pixel meeting. A draft of an evaporative cooling
test program was circulated for discussion.

1.1.1.1.2 Development and Prototypes

ESLI, San Diego, has stated that it will deliver the planned 14
prototype sectors by 15 July. Twelve of these sectors and the prototype
disk support ring will be used to fabricate the first prototype pixel
disk. The C-Channel layups of the prototype support ring, which make up
the ring facings close-outs, have dimensional errors. The C-Channels
will probably be remade which will lead to a delay in the ring delivery.
It is estimated that the ring bonded assembly will be completed by 31
July.

Aluminum tube sector 4 was tested for cooling performance with C6F14
fluid as coolant. The sector meets our thermal requirements up to a
power of 48 Watts with a coolant flow of 20 cc/s and an inlet
temperature of -20 degrees C.

Facing material prototypes previously tested for tensile modulus have
been irradiated to 25 MRads at the LLNL Co60 source. Moduli of the
facing materials after irradiation were measured as the same as before
irradiation. Moduli and tensile strength of the materials were as
expected.

One prototype panel for the pixel overall support frame was fabricated.
This panel used a graphite-fiber hexcel core from YLA celluar. One edge
of the hexcel core has a rough edge and hence a lesser bond strength is
expected for that side. This problem will be cured with new hexcel core
that will be purchased at no cost to the project. The first panel and a
second panel fabricated with the present hexcel have allowed the
development of the bonding process. Aluminum block inserts have been
bonded into the panels. These inserts are connection points between
sections of the overall frame. The need to order new hexcel introduces a
delay in completing Phase I of the prototype frame program.

1.1.1.1.3 Disk Production

No activity.

1.1.1.2 Pixel Sensors (S. Seidel)

  --------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}    [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*Start market survey       2-Nov-98                 1-Dec-98                                         Done

  \*2^nd^ prototype PDR       1-Dec-98                 1-Dec-98                                         Done

  \*Complete market survey    5-Mar-99                 12-Feb-99                                        Done

  \*2^nd^ prototype FDR       29-Mar-99                22-Feb-99                                        Done

  \*Compl. Test 1^st^         13-Apr-99                13-Apr-99                                        Done
  prototypes                                                                                            

  \*Compl. 2^nd^ prototype    27-Apr-99                1-May-99                                         Done
  design                                                                                                

  \*Compl. Fab of 2^nd^       21-Sep-99                21-Sep-99                21-Sep-99               OK
  prototypes                                                                                            
  --------------------------- ------------------------ ------------------------ ----------------------- ----------------------

1.1.1.2.1 Design

No activity.

1.1.1.2.2 Development and Prototypes

The non-disclosure agreement (NDA) between 6 ATLAS institutes and 3
sensor vendors was finalized. An additional NDA between ATLAS and BTev
is being finalized to permit BTev to use the ATLAS prototype sensor
design. Initial organizational work for the PRR was begun.

1.1.1.2.3 Production

New Mexico was able to obtain non-ATLAS support for 2 student
technicians; with M. Hoeferkamp, these students completed the assembly
of the cleanroom that is required for production sensor probing.

1.1.1.2 Pixel Electronics (K. Einsweiler, R. Kass)

  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}   [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  Compl. Design HSOI test    16-Apr-98                1-Nov-98                                         Done
  die                                                                                                  

  Compl. Fab HSOI test die   26-Aug-98                31-Mar-99                                        Done

  Compl. Design DMILL test   15-Dec-98                15-Dec-98                                        Done
  device                                                                                               

  Submit 2^nd^ Honeywell SoI 15-Jan-99                                                                 Not known
  test die                                                                                             

  1^st^ design review of     25-Jan-99                23-Feb-99                                        Done
  DMILL proto                                                                                          

  \*FDR DMILL 1^st^          25-Jan-99                15-Jun-99                21-Jul-99               Delay
  prototype                                                                                            

  \*Compl. Design DMILL      26-Feb-99                30-Jun-99                31-Jul-99               Delay
  1^st^ proto.                                                                                         

  1^st^ design review of     1-Jun-99                 1-Oct-99                 1-Oct-99                Delay
  Honey. Proto                                                                                         

  Compl. Eval. HSOI test die 1-Jul-99                 1-Aug-99                 1-Aug-99                Delay

  \*FDR Honeywell SoI 1^st^  5-Mar-99                 15-Nov-99                15-Nov-99               Delay
  prototype                                                                                            

  \*Compl. Design Honey. SoI 2-Apr-99                 1-Dec-99                 1-Dec-99                Delay
  proto.                                                                                               

  \*Compl. Fab of DMILL      23-Jul-99                15-Oct-99                15-Oct-99               Delay
  1^st^ proto.                                                                                         

  \*Compl. Fab of Honey. SoI 25-Aug-99                1-Mar-00                 1-Mar-00                Delay
  1^st^ proto                                                                                          

  \*Compl eval. DMILL        9-Dec-99                 1-Jun-00                 1-Jun-00                Delay
  prototype                                                                                            

  \*Compl eval HSOI          15-Feb-00                1-Jun-00                 1-Jun-00                Delay
  prototype                                                                                            

  \*Review design approach   19-Jan-00                15-Jun-00                15-Jun-00               Delay

  \*Select rad-hard vendor   29-Jan-00                15-Jul-00                15-Jul-00               Delay
  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------

1.1.1.3.1 Design

LBNL

Our highest priority remains the DMILL front-end chip submission (FE-D).
The schematic for the entire chip is now essentially frozen, and the
last few blocks in the chip are in the final layout stages. However,
difficulties described below have introduced about another month delay
in submission.

The layout work for the blocks of the digital readout portion of the
chip is now completed, including all buffer sizing. We have been running
top-level Verilog simulations including back-annotated timing
performance for the fast-fast, typical, and irradiated-slow-slow device
models. We have also been running SPICE (ELDO) simulations of the entire
basic digital readout (one column pair, all EOC buffers, and all of the
digital circuitry in the bottom of the chip). So far, no additional
problems have been discovered in these simulations. This work will
continue throughout much of July. The remaining critical issue in the
digital readout is the sense amplifier design. This is a new block in
the FE-D design, added to speed up the transfer of data from the pixels
to the EOC buffers. The original design proved to be less robust in
simulation than we had expected. In particular, it was rather tricky to
get it to work at 20 MHz after irradiation. This arose because the
DC-coupled design did not have a threshold that automatically tracked
the varying DC baseline at its input (which varies as a function of
radiation dose), requiring "fiddling" to get it to perform. We now have
a new design that seems to be much more robust, as well as providing
nice low swing signals in the column (only about 200-300mV). We are
still completing the simulations on this new design before doing the
layout work. However, it appears fairly certain that the new sense
amplifier design will fit in the allowed space and meet our power budget
(there are 198 of these amplifiers in the complete pixel array).

The Bonn group has completed the floorplan of the full pixel array,
including the integration of all the remaining analog blocks into the
overall layout. The interconnection of all blocks is essentially
complete. The remaining block is a new charge injection circuit, which
has been designed and simulated, but not yet laid out. Verilog
simulations, in particular of the control part of the chip (command,
global, and pixel select registers) have been carried out to check that
everything functions correctly.

Finally, over the last few months we have performed a comprehensive set
of measurements at LBL of the performance of the front-end design
(preamp and discriminator) that we plan to use in FE-D. We have found a
rather disturbing problem in the design, which was sufficiently large
that it has been overlooked by the other groups working on this chip.
There is a very large transit time through the last stage of the
discriminator, which depends strongly on the bias current in the
discriminator. This can cause additional delays of up to 100ns.
Furthermore, since the transit time depends strongly on the bias
current, any source of dispersion in this bias current becomes a source
of global timing dispersion in the pixel array. This has led to effects
as large as 30ns peak-peak in the present pixel array chip. Initially
this problem was blamed on suspected problems in the digital readout,
but its origin has been definitively identified to lie in the back-end
of the discriminator. Additional measurements and simulations are
proceeding at CPPM (the designer of the front-end). Some obvious power
distribution issues have been addressed, which should reduce the timing
dispersion significantly, but it could still be easily 5ns (the FE-B
chip built by LBL has a 1ns timing dispersion for large charges). This
additional dispersion must be subtracted from the already quite
aggressive 20 ns timewalk budget we are seeking to achieve for the
individual pixel front-ends. It significantly increases the risk that we
will have to read out two crossings worth of data to achieve high
efficiencies, or lose all of the smaller charges which arrive too late
for a single-crossing readout. CPPM will work on this problem for
several more weeks, at which point we will almost certainly have to
proceed with the submission in any case.

We completed a 2-day "internal review" meeting in Bonn on June 9-10 with
all of the chip designers. We reviewed the design and simulation results
for the complete chip. This was extremely useful to get a coherent
picture of all of the different components of the present chip, and to
assess exactly what work remained to be done. We agreed on the list of
issues to attack next, and have now set a date for our next (and final)
internal review, to be once again in Bonn, from July 21-23. We believe
that with fairly high confidence we can submit the chip shortly after
this last review.

The complete reticle for this TEMIC DMILL engineering run has also been
worked out. It will include two pixel array chips (FE-D). It will also
include an MCC prototype from Genova containing many improvements
towards a final version, but not yet representing a complete chip. There
are also prototypes of opto-link chips (two versions of a receiver chip
and one version of a driver chip). The opto-electronics designs are
based on those of the SCT, but have been transferred from a commercial
rad-soft bipolar process by Siegen and Ohio State University. A special
process monitor bar is being developed by LBL to allow reliable
extraction of SPICE models from the FE-D wafers so that we can
cross-check our design performance against expectations. Finally, a
rad-hard LVDS buffer is included which will allow us to make a complete
rad-hard version of the single-chip support card that we use for testing
single chips in the lab and testbeam. With this buffer, we have the
capability to operate a single pixel chip (or electronics/sensor
assembly) while it is being irradiated to LHC fluences.

Ohio State

During the month of June we continued to make progress towards producing
a radiation- hard version of the DORIC4 chip. A meeting on the DORIC
chip was held in Siegen mid June. The participants at the meeting
included Chuck Rush (OSU), Harris Kagan (OSU), Joachim Hausmann
(Siegen), Martin Holder (Siegen) and Michal Ziolkowski (Siegen). At the
meeting many issues concerning the DORIC chip were discussed. The
circuits were simulated and discussed in detail. As a result of the
simulations and discussions the performance of the preamp was improved
for smallest input signals (60μA/20μA), a set of probing points to be
implemented in the circuit was chosen, and it was realized that there is
a serious layout bug in the current version of the bias circuit for LVDS
cells (this will be fixed in Bonn). Finally, the following was agreed:

a\) submit a single version of the DORIC chip; the one which based on
current mirrors.

b\) complete the simulations (included post-radiation) and make the
results available to leaders in the pixel electronic group.

c\) create the gds files for DORIC and VDC.

d\) run an independent simulation at OSU, based on complete netlists
generated in Siegen.

We are still discussing ITAR agreement compliance and security with OSU
officials. A meeting was held earlier in the week with the OSU officials
to discuss certain details of OSU\'s interpretation of security.
Hopefully, all remaining issues will be resolved soon.

The installation of CADENCE on our workstation(s) is proceeding and
progress has been made in simulating some simple circuits.

1.1.1.3.2 Development and Prototypes

LBNL

We have spent quite a bit of time the last few weeks improving our
measurements on the FE-C chips we have received from Bonn. We have a
very complete set of timing measurements on 2 different chips that
clearly characterize the timing dispersion problem discussed above. This
problem was missed in part because we have concentrated on timewalk
measurements that always involve timing differences, where absolute time
dispersion between channels cancels out.

We have also carried out further studies on the new baseline SSGb
detector design, and verified that the cross-talk performance is
slightly better than the old SSG design (wider implants), and the noise
performance is also slightly better. Recent testbeam measurements also
verified that the charge collection losses in this new design were very
small and localized. Hence, this design looks like it passes all of our
requirements for the final sensor design for ATLAS. Nevertheless, we
will soon receive several additional single chip assemblies with which
we will complete our characterization of all of the designs included in
the sensor 1b prototype run. One of these designs has lower capacitance,
and hence better noise performance, than the SSGb, but could still
suffer from charge collection problems. There is also a "floating pixel"
design that could be of interest to improve resolutions in the B-layer
during initial operation. These single-chip devices will be fully
characterized in the July H8 testbeam.

The Honeywell SOI multi-project submission which we made in Nov. 98 has
returned to LBL and undergone preliminary evaluation. We are working to
set up a test program on the CERN IC tester to continue the testing in
Geneva, where the chip designer is now resident. This is proceeding
well, and first test results form this system have been produced.
However, we have not been able to fully characterize the design in the
way we would like prior to performing irradiation testing. We have
therefore delayed our plans to irradiate several die in the 88"
cyclotron at LBL until after the end of the several month shut-off which
begins in July.

1.1.1.3.3 Production

No activity.

1.1.1.3 Pixel Hybrids (R. Boyd, S. Timm)

  ---------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}     [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \* Compl. Assembly of 1^st^  14-Jan-99                10-Nov-98                                        Done
  proto.                                                                                                 

  \* 1^st^ prototype design    18-Feb-99                18-Feb-99                                        Done
  review                                                                                                 

  \* Compl. Tests of 1.0       15-Apr-99                15-Mar-99                                        Done
  protos.                                                                                                

  \* Select hybrid type        15-Apr-99                1- Mar-99                                        Done

  Compl. Design of 1.x         1 - Apr- 99              21-Apr-99                                        Done
  proto^.^                                                                                               

  Fabrication of 1.x compl                              1-Aug-99                 1-Aug-99                OK

  Singulate 1.x proto compl                             15-Aug-99                15-Aug-99               OK

  Assembly of 1.x proto compl                           1-Sep-99                 1-Sep-99                OK

  Prototype 1.x tests complete                          15-Oct-99                15-Oct-99               OK

  Module assy with 1.x compl                            15-Sep-99                15-Sep-99               OK

  Design of proto 2.0 begins                            1-Sep-99                 13-Jul-99               OK
  ---------------------------- ------------------------ ------------------------ ----------------------- ----------------------

1.1.1.4.1 Design

Oklahoma

Delivery of Flex Hybrids from R&D circuits has beem delayed due to
maufacturing mistakes. Processing of a third batch was begun the last
week of June, with delivery expected the first week of July. It is not
clear that they will arrive in time for a module to be built for testing
in the July test beam at CERN. Several sample circuits are expected in
early July from the last failed fabrication attempt. One frame of top
metal only circuits have beem received from CERN for wire bond testing,
which is under way. Preliminary design work for prototype version 2.0
will begin in July, ahead of schedule..

1.1.1.4.2 Development

Spice models of the power lines of the v1.x Flex Hybrids have been
constructed using Maxwell Spicelink. These are simple models which are
being used to try to understand decoupling needs for future designs.

Radiation tests of Flex Hybrids, SMT components and assembly materials
were carried out earlier this year with assistance from LBNL. All
samples were irradiated using a ^60^Co source at LLNL to 25MRad. To
summarize, the Flex Hybrid was not damaged by radiation, although the
color of the Kapton darkened. The average values of irradiated SMT
components were within 1 sigma of the unirradiated values. Only one
adhesive showed an udesirable change in properties, and this one is not
being considered for use because of other problems with it.

A more detailed summary follows.

[Strip and Resistance Test]{.underline}

-Purpose and Method: Strips of conductive adhesive 75mm long were bonded
to glass slides in the manner used in Flex Hybrid application. Half of
each sample was irradiated, the other half remained in storage until
testing. For tests, tape was applied rigorously to strip of material,
removed, and examined for possible residue indicating loss of test
material from the glass slide. Resistance was measured across the full
75mm length (values quoted are in Ohms).

-52C thermaphase:

-null result; identical performance between rad and non-rad samples.

-H20E (old):

-one rad, one non-rad

-null result; identical performance between rad and non-rad samples.

-resistance: rad=1.8, non-rad=3.0

-EG105 (old):

-one rad, one non-rad

-slight possible loss on rad sample

-resistance: rad=0.4, non-rad=0.4

-E2101 (old):

-three rad, three non-rad

-null result; identical performance between rad and non-rad samples.

-resistance: rad=0.3, non-rad=0.4

-note: qualitatively, this epoxy is significantly more robust/less
brittle than the other samples.

-Conclusions: 52C thermaphase showed no change due to irradiation.
Little difference is noted between the three types of epoxy, with the
possible exception of the single component EG105.

Shear Test, Loctite

-Purpose and Method: 200 ohm 0402 surface mount resistors were bonded to
glass slides using Loctite SMT adhesive. Force was applied essentially
perpendicular to the bond using a load cell. Only maximum values of
force were recorded (values quoted are in lbs.).

-non-rad (3 samples):

-5.22, 3.83, 3.56 =\>4.20 +/- 0.89

-rad (6 samples):

-4.10, 3.23, 2.60, 3.72, 4.53,4.33 =\>3.75 +/- 0.72

-rad on kapton tape:

-null result; Kapton tears at much lower force than required to break

loctite bond.

-Conclusions: Sample sizes are much too small to confirm or deny the

suitability of Loctite adhesive. We can with some confidence show that
the

Loctite bond is significantly stronger than the Flex material, and as
such, does meet minimum strength requirements.

Thermaphase Overlap, 52C

-Purpose and Method: Two glass slides were bonded together using 52C
Thermaphase with an approximate area of overlap of 25 mm^2^. Force was
applied via a load cell perpendicular to the slides at a distance of
roughly 35 mm from the center of the bonded area. Only maximum values of
force were recorded (values quoted are in lbs.).

-rad (3 samples):

-1.50, 1.50, 1.35 =\> 1.45 +/- 0.09

-non-rad (2 samples)

-1.39, 1.04 =\>1.20 +/- 0.26

-further tests:

-rephased one each of rad and non-rad samples =\>rad = 1.41, non-rad =
1.50

(glass broke before thermaphase bond)

-rephased second rad sample and cooled to -10C =\> rad= 1.35

-qualitative inspection of rephase characteristics show no change in rad

sample

-Conclusions: Again, sample sizes are too small. Results do indicate,
however, that no significant degredation occurs in 52C Thermaphase due
to irradiation.

SMT Component Electrical Response

-Purpose and Method: Several units of each type of component were
mounted to glass slides using Loctite adhesive and E2101 epoxy. Half of
the entire sample was irradiated, the other half remained in storage
until testing. Each component\'s response as a function of frequency was
recorded to ensure no primary radiation damage.

-Conclusions: No significant change in irradiated components. Values are
well within the manufacturer\'s specified errors.

Miscellaneous

-double sided Kapton tape:

-no qualitative damage observed

-bare flex on 52C Thermaphase:

-flex and Thermaphase disassociated cleanly from glass slide. I could
not repeat this effect, which suggests that the observed phenomena could
be due in part to the irradiation process. Further tests are required to
explain this result.

Albany

The Windows NT computer and PLL were received this month. Thus, the
PixelDAQ system is setup and the VME instrumentation is being checked.
All power supplies required for module tests have been ordered. Tests of
a single chip module, to be supplied by OU or LBNL, will begin in July.
A probe card for testing a pair of FE pads at one time on a v2.x Flex
Hybrid have been ordered and delivery is expected in early July.

1.1.1.4.3 Production

No activity.

1.1.1.5 Pixel Modules (R. Boyd, K. Einsweiler, K. K. Gan, M. Gilchriese)

  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}   [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*Compl. 1^st^ proto.      29-Oct-98                1-Mar-99                                         Done
  Design                                                                                               

  \*1^st^ proto. Design      18-Feb-99                18-Feb-99                                        Done
  review                                                                                               

  \*Compl. Tests of 1^st^    18-Mar-99                17-Sep-99                17-Sep-99               Delay
  protos.                                                                                              

  \*Select module type                                18-Mar-99                22-Feb-99               Done

  \*2^nd^ proto. Design      17-Sep-99                10-Sep-99                10-Sep-99               OK
  review                                                                                               
  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------

1^st^ prototypes will continue to be tested during the May and July test
beam cycles.

1.1.1.5.1 Design/Engineering

LBNL

Work continued at a slow pace on understanding thinning of IC wafers. A
dummy wafer from IZM in Berlin was ground by GDSI in Sunnyvale with poor
results. Although GDSI has previously ground successfully one-half of a
6\" FE-B wafer to 150 microns and some dumy 4\" wafers with indium
bumps, they broke the new dummy wafer during the grinding process. In
addition, removal of the tape holding the wafer(UV release tape)
apparently also caused many bumps to be removed. The cause for this is
not understood. Pictures of the results have been transferred to IZM and
discussions with GDSI are continuing.

As a result of this failure, we have investigate alternative sources for
wafer thinning. The 150 micron specification is very aggressive but we
have tentatively identified two other companies(Okamoto and Tru-Si
Technologies) that appear to have superior experience(Okamota) or
capabilities(Tru-Si) for very thin wafers. Tru-Si uses a new type of
technology rather than mechanical grinding to thin wafers and is aiming
at the very thin \"smart card\" market down to 50 microns thickness.
However, they are a start-up company and not yet in full production
mode. Okamoto is a well established company that uses conventional
grinding but has considerable experience grinding solder and gold
bump(but not indium bump) wafers and they are appropriately cautious
about committing to 150 micron thickness. Additional dummy wafers will
be fabricated at IZM for delivery in early July to try each company. It
is by no means clear that the 150 micron specification can be met in a
production mode for an affordable cost and considerable additional
effort will be needed to validate the thinning process.

Design work for tooling for module assembly began this month under the
direction of F. Goozen. The few modules assembled so far have been done
\"by hand\" but production-quality tooling will obviously be required
for the assembly of hundreds of modules.

1.1.1.5.2 Development and Prototypes

LBNL

We are preparing for the July testbeam by re-fabricating the complex
module support card, originally produced by Genova. In the May testbeam,
we were very distressed to find that our one almost perfect "bare"
module (one in which the interconnects are done on a PC board instead of
a Flex Hybrid) no longer worked because of an internal board short that
developed in the clock distribution net. This PC board is a 10-layer
card with a very large number of micro-vias which are used to route all
of the signals near the wire-bond pads, and it has not proven possible
to repair the card. So far, we have found only one well-qualified vendor
interested in producing this card, and they want over 1K\$ per card, so
further searching for vendors continues. It is becoming increasingly
likely that we will not be able to produce a new module of this type in
time for the July testbeam. These bare modules are intended to serve as
an "electrical reference", with in particular much better power supply
distribution and decoupling than is possible in the Flex Hybrid
prototypes.

Additional delays in both the Flex 1.x fabrication, and in the new Flex
Support card fabrication are making it more likely that we will not have
any of these new modules ready in time for the July testbeam either.
This will be quite unfortunate, because we observed problems with
communications between the FE chips and the MCC in the one Flex 1.0
module which was tested in May in the testbeam. It is not clear whether
these problems are related to noise pickup, which then provokes a
problem with the present MCC-FE protocols, or whether there is something
more fundamental wrong. No lab tests have so far shown any evidence for
similar problems, and we were relying on returning to the testbeam in
July to learn more about this problem. The symptoms of the problem are
that the MCC stops responding with data when triggers are sent to it,
until it is reset. Such behavior would not be acceptable in ATLAS, as it
would produce significant deadtime.

An additional task which we are pursuing at the moment is the tooling to
allow probing of complete modules as they return from the bump-bonding
vendor. This consists of a complex vacuum support fixture to locate the
module and secure it by vacuum holes behind each of the sixteen FE die
in the module, as well as a special "deep access" probe card to test the
operation of individual FE chips, and a special very-low-profile HV bias
connection. The probe card, which has a very limited clearance, must be
able to pass over the HV bias connection during scanning. We believe
this will prove feasible, and this would give us the ability to carry
out complete threshold scans, and even photon source runs to check bump
yield, on a bare module assembly prior to attaching the Flex and
ancillary electronics. We will try out this procedure for the first time
when we begin to make focussed ion beam modifications to a module
assembly to fix the FE-B readout problem that prevents us from reading
out the last 8 columns on each pixel chip.

Ohio State

Work is continuing on the packaging of VCSELs. We now have a procedure
for depositing Au/Cr traces on macor after several attempts. A test run
of 26 wire bondings has 100% success rate. The pull strength on 3 test
bonds are high, 10, 11, and 12 grams. This is well above the minimum of
6 grams considered acceptable. The 3-dimensional mask for depositing the
traces has been redesigned. The previous version has machined slits on a
bend brass sheet. This has the disadvantage of a round corner at the
bend and the fine metal traces are weak and prompt to breakage. In the
new mask, we use two metal sheets with fine teeth mounted at right angle
to form slits. The teeth are significantly stronger than the slits from
the previous prototype. We have successfully deposited traces using the
new mask.

We prototyped two VCSEL mounting jigs. The first prototyped has the
VCSEL placed face down in a pocket and the orientation of the chip is
observed via a small hole (125 μm) under the chip. Unfortunately, the
drilling of a 3-mm long hole is not practical. The next prototype is a
three-piece design with the VCSEL placed face up: a base piece for
housing the base of the optical package, a 50 μm stainless steel sheet
with three pockets for the VCSEL and PIN, and a top piece to push the
sheet against the base piece. The prototype is also not satisfactory
because it is not possible to mount the thin sheet flat to the level of
25 μm. We are working on a third prototype in which the jig is made out
of one piece of aluminum with a small area machined down to 50 μm to
replace the stainless steel sheet. If this is successful, we can then
mount the VCSELs and measure the coupled optical power.

1.1.1.5.3 Production

No activity.

1.1.2 Silicon Strips

1.1.2.1 IC Electronics (A.A. Grillo)

  --------------------------- ------------------------- ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}    [Baseline]{.underline}    [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*Send out market survey    1-Sep-98                  17-Aug-98                17-Aug-98               Done

  \*FDR for 2nd CAFÉ-M        15-Sep-98                 11-Sep-98                11-Sep-98               Done

  \*Procurement in place for  9-Oct-98                  13-Nov-98                13-Nov-98               Done
  2nd proto                                                                                              

  \*FDR for 2nd ABC           23-Oct-98                 26-Jan-99                26-Jan-99               Done

  \*Closing date for market   26-Oct-98                 25-Sep-98                25-Sep-98               Done
  survey                                                                                                 

  \*Submit 2nd CAFÉ-M         30-Oct-98                 26-Jan-99                26-Jan-99               Done

  \*Issue call for tender     9-Nov-98                  9-Nov-98                 9-Nov-98                Done

  \*Submit 2nd ABC            16-Nov-98                 1-May-99                 1-May-99                Done

  \*FDR for 2nd ABCD          11-Dec-98                 15-Dec-99                15-Dec-99               Done

  \*Closing date for tender   21-Dec-98                 22-Jan-99                22-Jan-99               Done

  \*Submit 2nd ABCD           27-Jan-99                 8-Apr-99                 8-Apr-99                Done

  \*CERN finance comm.        15-Mar-99                 15-Mar-99                15-Mar-99               Done
  Approval                                                                                               

  \*Frame contract in place   15-Apr-99                 30-Jul-99                30-Sep-99               Delay

  \*Compl. Fab of 2nd CAFÉ-M  19-Apr-99                 8-Apr-99                 8-Apr-99                Done

  \*Compl. Fab of 2nd ABC     19-Apr-99                 3-Aug-99                 3-Aug-99                Delay

  \*Test systems complete     26-Apr-99                 31-Jul-99                31-Jul-99               Delay

  \*1st ICs avail. For 2nd    18-May-99                 30-Aug-99                30-Aug-99               Delay
  proto hybrid                                                                                           

  \*Compl. Fab of 2nd ABCD    30-Jun-99                 26-Jun-99                15-Jul-99               OK

  Compl. metallization 1^st^  \-\-\-\-\-\-\-\-\-\-\--   15-Jul-99                7-Aug-99                OK
  ABCD                                                                                                   
  --------------------------- ------------------------- ------------------------ ----------------------- ----------------------

1.1.2.1.1 Design/Engineering

LBNL & UCSC

Some progress was made in understanding the bug in the new ABC design
which was discovered just after it was submitted for fabrication. It
appears the source of the problem is a last minute fix to the original
ABC design just before it was submitted for fabrication. The RAL
engineer in charge then made a change to the ROC (Read Out Controller)
sub-circuit to fix a bug rather than deferring the problem to the ROC
designer at Geneva. This "fix" did fix one problem but created the
present one. Unfortunately, the testing of the "FIBed" ABCs did not
uncover the problem since it only shows up when multiple triggers are
received in short succession. In the mean time, the ROC designer did a
proper fix for the ABCD which did not introduce the new problem. We have
confirmed that this bug was present in the originally fab'd ABC. As a
fix, the ROC sequencer design from the new ABCD has been substituted
into the new ABC design and the bug does not appear under the same set
of test vectors which showed the error. Obviously, more simulation work
is needed. We plan to complete the insertion of this ROC sequencer into
ABC layout and re-run the full set of simulations which were previously
run on the chip plus more simulations using random data patterns. The
goal is to complete this work now and not wait for the new fabrication
to be completed and tested. This will give us confidence that we
understand the cause of the error and that we have a fix in place should
the CAFÉ/ABC solution be chosen.

1.1.2.1.2 Development and Prototypes

LBNL & UCSC

The status of the ABC lot at Honeywell is still on track for delivery
the first week of August.

The ABCD wafers completed fabrication at Temic but their PCM tests
(electrical tests of process control monitor devices) showed that all
wafers were outside of the process spec limits on one or more of four
parameters. We do not believe that these parameters will cause a problem
with the IC performance but it is particularly troubling to be
qualifying a process and a design with even some parameters out of spec.
At the same time, having new wafers fabricated will delay our project by
another 8-12 weeks. At month end, our plan is to discuss the issue with
Temic as soon as possible and come to some resolution. One possibility
is to have Temic process new wafers but for us to keep one or two of the
existing wafers so that we can at least start our evaluation with the
out of spec parts.

Testing of the CAFÉ-P has continued with more radiation tests. We are
preparing one two-chip module with CDPs and 12 cm detector to evaluate
the performance of the CAFÉ-P when connected to a detector load.
Depending upon those results which we hope to obtain in early July and
the schedule of the ABC delivery, we may add more CAFÉ-P/CDP pairs to
this module to gain experience with a more complete module.

1.1.2.1.3 Production

A successful meeting was held with Temic on 7-Jun to discuss details of
the Frame Contract. However, it is clear that more negotiations are
needed and the similar negotiations with Honeywell will not now start
until July. Given this and our better understanding of the approval
process still awaiting the contract at CERN, the contracts will not be
in place this summer. CERN Purchasing has been informed of the
importance of having the contracts in place by September if we are to
keep to our schedule of making a decision on technologies (i.e. vendors)
in December. Without the Frame Contract in place we will not have
definite price numbers available to make our choice.

1.1.2.2 Silicon Strip Hybrids (C. Haber)

  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}   [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  Complete design of 1st     17-Nov-97                17-Nov-97                                        Done
  prototype                                                                                            

  Complete fab of 1st        2-Feb-98                 23-Mar-98                                        Done
  prototype                                                                                            

  Preliminary design review  3-Aug-98                 15-Sep-99                7-Dec-99                Delay

  \*Compl. 2nd proto subs.   29-Oct-98                15-Jun-99                15-Jun-99               Done
  design                                                                                               

  \*Compl. 2nd proto cable   29-Oct-98                15-Jun-99                1-Sep-99                Delay
  design                                                                                               

  \*Compl. 2nd proto fanout  29-Oct-98                15-Jun-99                1-Sep-99                Delay
  design                                                                                               

  \*Compl fab of 2nd proto   11-Mar-99                1-Aug-99                 15-Aug-99               Delay
  substrate                                                                                            

  \*Compl fab of 2nd proto   11-Mar-99                1-Aug-99                 1-Oct-99                Delay
  cable                                                                                                

  \*Compl fab of 2nd proto   11-Mar-99                1-Aug-99                 1-Nov-99                Delay
  fanout                                                                                               

  \*Compl procure of 2nd     11-Mar-99                1-Jul-99                 1-Jul-99                Delay
  proto comps                                                                                          

  \*Compl. 2nd proto         17-May-99                15-Aug-99                1-Sep-99                Delay
  assembly                                                                                             

  \*1st 2nd proto hybrids    14-Jun-99                15-Aug-99                1-Sep-99                Delay
  available                                                                                            
  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------

LBNL

1.1.2.2.1 Design

A process for reviewing the three hybrid options for ATLAS(ceramic,
kapton and pyrolitic grpahite substrates) has been established. There
will be an initial review in September 1999 with a final review and
decision planned for early December 1999. The later has been designated
by us as the preliminary design review.

The new hybrid layout for the Cafe-P and ABC chips was completed this
month, checked and sent to the vendor for fabrication.

We can and will use the existing cable design for this new hybrid. We
will make a modified cable design as the module work progresses through
the next few months. We are therefore delaying this cable milestone.

We can and will use the existing fanouts for this hybrid particularly in
the initial testing and ASIC evaluations. We will pursue a new fanout
design as part of the module testing program on a somewhat longer time
scale. Note the milestone change above.

1.1.2.2.2 Development and prototype fab

The laser machined substrates, documentation, and the design files were
sent to the two fabrication vendors. Work commenced there on producing
this set of new prototypes.

1.1.2.2.3 Production

No activity.

1.1.2.3 Modules for Silicon Strips(C. Haber)

  ------------------------------ ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}       [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*Preliminary design review    3-Aug-98                 1-Apr-99                 T BD                    Delay

  Complete fabrication of 1st    15-Aug-98                15-Aug-98                                        Done
  dummy modules                                                                                            

  Prototype tooling complete     1-Apr-99                 1-Aug-99                 1-Aug-99                Delay

  \*Compl. Design of proto       14-Jun-99                15-Nov-99                15-Nov-99               Delay
  assy/test                                                                                                

  \*Compl. Fab of tooling for    14-Jun-99                15-Nov-99                15-Nov-99               Delay
  proto                                                                                                    
  ------------------------------ ------------------------ ------------------------ ----------------------- ----------------------

LBNL

1.1.2.3.1 Design of Assembly and Test

New drawings of the assembly fixtures were received from RAL and these
are being reviewed. Design continues on a folding fixture for the
hybrids.

1.1.2.3.2 Development and prototypes

The new calibration plate was submitted for fabrication last month and
received this month.

An attempt was made to machine some of the PG for the test of thermal
performance last month but it was unsuccessful. We pursued some
alternate approaches based upon suggestions received from Europe and
were able to finally get a good result.

The process of training a new technician on the assembly system
continues. This individual is expected to be the lead technician on the
module assembly during the construction phase.

As part of the program to test the new Cafe-P chips, we began assembly
on a single sided test module this month. This effort also provides a
training opportunity for our technician.

1.1.2.3.3 Production

No activity.

1.1.3 ReadOut Drivers(R. Jared, A. Lankford)

  ----------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}      [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*Select PreROD               30-Oct-98                26-Mar-99                                        Done
  implementation                                                                                          

  \*Requirements review         30-Nov-98                18-Nov-98                                        Done

  \*Compl. System design        28-Dec-98                TBD                      15-Jul-99               Rev

  Compl. SCT ROD simulation     N/A                      N/A                      7-Jul-99                Rev

  Compl. Pixel ROD simulation   N/A                      N/A                      1-Aug-99                Rev

  Compl. DSP eval. Setup        N/A                      N/A                      15-Aug-99               Rev

  \*System design review        11-Jan-99                TBD                      20-Aug-99               Rev

  Compl. Decoder VHDL code      N/A                      N/A                      1-Oct-99                Rev

  Compl. gather VHDL code       N/A                      N/A                      1-Oct-99                Rev

  \*Compl. PreROD layout        15-Feb-99                TBD                      1-Oct-99                Rev

  \*Compl. PreROD procure       1-Mar-99                 TBD                      1-Oct-99                Rev

  \*Compl. PreROD PCB fab       16-Mar-99                TBD                      15-Oct-99               Rev

  Compl. Mux VHDL code          N/A                      N/A                      1-Nov-99                Rev

  Compl. Controller VHDL code   N/A                      N/A                      1-Nov-99                Rev

  \*Compl. PreRod Design        29-Jan-99                TBD                      1-Nov-99                Rev

  \*Compl. PreROD 1^st^         30-Mar-99                TBD                      1-Nov-99                Rev
  assembly                                                                                                

  Compl DSP C code              N/A                      N/A                      1-Dec-99                Rev

  Compl. Initial test stand SW  N/A                      N/A                      1-Dec-99                Rev

  \*Compl. protoROD debug/test  9-Jul-99                 TBD                      1-Feb-00                Rev

  PreROds prod. Fab complete    N/A/                     N/A                      1-Jul-00                Rev
  ----------------------------- ------------------------ ------------------------ ----------------------- ----------------------

The milestones above have been updated to agree with the new schedule
reported in last month's report. It should be noted that the
preprototype ROD is now the prototype ROD. This change should allow for
the completion of the project on schedule. Baseline dates shown are for
the preprototype ROD. They have not been changed to reflect the US ATLAS
ROD prototype schedule. \"Rev\" indicates revised milestones that are
now the new baseline schedule as of this month.

1.1.3.1.1 Strip Test Beam Support (A. Lankford)

UC Irvine

Hardware and software support for laboratory and beam tests of SCT
electronics and modules is ongoing. Activity in May and June consisted
of providing technical support to users of systems already in the field.

1.1.3.1.2 Pixel Test Beam Support (R. Jared)

> Minor support effort was supplied in May.

1.1.3.2.1 ROD Requirements (R. Jared)

Contacts have been made with the user community to define and justify
the following requirements:

1.  Monitoring of the ROD data flow status (buffer occupancy, S-Link
    status, front-end status, etc) as recommended in the recent ROD
    review. John Hill that heads the ROD crate processor effort will
    assist in this effort

2.  Dynamic throttling of individual links during data taking. This
    would be based on the measured number of events in the front-end
    modules.

3.  Issue configuration commands during the periodic reset.

4.  The number and speed of pixel lengths into a ROD. This question is
    governed by what capabilities can be designed into the module
    control chip.

These issues were discussed at the pixel and SCT weeks in Europe.
Initial consciences was reached on many of the requirement issues. It is
expected that July meeting in the UK will provide the concurrence to
start the change procedure of the requirements.

1.1.3.2.2 ROD Essential Model (R. Jared)

The essential model defines the essential functionality of the ROD and
defines the interfaces of the ROD to other functional units. It is
complete, except for refinements that are ongoing during the development
of the implementation model. No refinements of the essential model were
made during June

1.1.3.2.3 ROD Implementation Model (R. Jared)

The architectural definition of the ROD has progressed to the point were
the interfaces between FPGAs is the focus of the effort. As these
interfaces are clarified, coding will commence. This should be within
two weeks. The simulation of the SCT ROD have been essential to this
progress.

1.1.3.3.7 Preprototype ROD (R. Jared)

Complete simulation of the SCT ROD data path have been performed. These
simulation show that 96 or 72 links will satisfy the bandwidth for an
occupancy the is 2- 3 times the TDR occupancy. Initial selection of the
number of links per rod will be confirmed at the July workshop in
England. Architectural studies are nearing completion. The derandomizing
buffer sizes are now understood. This has allowed us to change from the
ORCA FPGA to the Xilinx FPGA and eliminate the external FIFO memories.
This will result in lower cost for the ROD event data path. Simulation
of the Xilincs and ORCA have shown that the existing decoder and
gatherer modules will run faster in the Xilinx. Logic utilization is
also lower in the Xilinx.