LG 03/03/2008

Pixel LVDS Data Path Testing Procedure

We are testing the LVDS data path for the readout of the IPHC developed
Phase-1 and Ultimate digital output sensors for use in the STAR Pixel
Detector. To accomplish this we have constructed a set of PCBs that mock
the components expected to be used in the final system. A system diagram
is shown in Fig 1. We intend to produce a system that is a mockup of the
complete data path for a single ladder starting and returning from the
Virtex-5 development board.

![](media/image1.wmf){width="5.999305555555556in" height="4.53125in"}

There are four basic components.

1.  Mock Ladder -- We have constructed a mock ladder. Since Phase-1
    sensors are not available, we have used a LVDS 1:4 fan-out chip
    SN65LVDS104 to take the place of the Phase-1 sensor. The mock ladder
    contains ten SN65LVDS104s on 2 cm spacing, and six FIN1108 8-port
    LVDS repeater chips as buffers at the end of the ladder. The mock
    ladder receives 3 input LVDS signals that are multi-dropped in
    groups of 4, 3 and 3. Correspondingly, there are 40 outputs that are
    buffered at the ends of the mock ladder and carried to the Mass
    termination board. The mock ladder is constructed of standard FR4
    with copper traces and has a finish thickness of 0.032" for 4
    layers.

2.  Mass termination board -- The mass termination board (MTB) is a
    close model of what we expect to have for a single ladder in the
    final system. Latch-up protected power is generated on the MTB and
    delivered to the mock ladder via 24 ga wire. In the interest of
    testing multiple possible signal paths, the MTB used In these tests
    has two possible data paths. One is straight through from input to
    output connectors. The other is buffered with the same FIN1108 parts
    used on the mock ladder.

3.  Virtex-5 interface -- The Virtex-5 interface board (V5IB) attaches
    to the Xilinx Virtex-5 development board with a 1200 contact points.
    The data signals into and out of the Xilinx V-5 are buffered on the
    V5IB with FIN1108s. There are test points to look at all
    differential signals.

The Virtex-5 development board generates 3 streams of pseudo random data
that are fed through the data path chain and returned to the V5IB. Each
stream of data is compared to what was sent and any errors are counted.
The results are then displayed on LEDs on the V5 development board and
can be read out over the SIU interface. We are interested in looking at
bit error rate, eye patterns at the end of the chain, temperature
response of the system and the response to data clock speed and cable
lengths.

I propose the following testing procedure;

1.  Assemble system and set up to run at operating speed.

2.  Use software to set the latch delay.

3.  Run for 20 minutes

4.  Use software to set the latch delay again.

5.  Look for bit errors, if none proceed.

6.  Use a heat gun to heat the ladder to 60-70 degrees C. Verify the
    temperature with the IR thermometer. Use the heat gun to hold the
    temperature for 2 minutes. If no bit errors are observed, proceed to
    next steps.

7.  Make eye pattern measurement of returning data measured in one place
    between the LVDS repeater and the V5 input pin triggered on the
    rising edge of the correct data output measured at the V5 output.
    Save and label the scope picture.

8.  Run the system for 12 hours overnight and check for bit errors. Note
    the number of bit errors observed.

We will have 8 possible hardware configurations and 4 speeds (120, 160,
200, 240 MHz) of interest. The configurations are listed below.

Configuration 1 -- 1 meter fine twisted pair wire mock ladder =\> MTB.
MTB set for buffered data path. 6 meters 3M 3644 cable from MTB =\>
V5IB.

Configuration 2 -- 1 meter fine twisted pair wire mock ladder =\> MTB.
MTB set for non-buffered data path. 6 meters 3M 3644 cable from MTB =\>
V5IB.

Configuration 3 -- 1 meter fine twisted pair wire mock ladder =\> MTB.
MTB set for buffered data path. 6 meters CAT-5 shielded cable from MTB
=\> V5IB.

Configuration 4 -- 1 meter fine twisted pair wire mock ladder =\> MTB.
MTB set for non-buffered data path. 6 meters CAT-5 shielded cable from
MTB =\> V5IB.

Configuration 5 -- 2.3 meters fine twisted pair wire mock ladder =\>
MTB. MTB set for buffered data path. 6 meters 3M 3644 cable from MTB =\>
V5IB.

Configuration 6 -- 2.3 meters fine twisted pair wire mock ladder =\>
MTB. MTB set for non-buffered data path. 6 meters 3M 3644 cable from MTB
=\> V5IB.

Configuration 7 -- 2.3 meters fine twisted pair wire mock ladder =\>
MTB. MTB set for buffered data path. 6 meters CAT-5 shielded cable from
MTB =\> V5IB.

Configuration 8 -- 2.3 meters fine twisted pair wire mock ladder =\>
MTB. MTB set for non-buffered data path. 6 meters CAT-5 shielded cable
from MTB =\> V5IB.

Not all configurations and speeds are of interest for testing. In the
interest of producing the most relevant data first I propose the
following testing plan.

1.  Test Configuration 1 with all speeds.

2.  Test Configuration 5 with all speeds

3.  Test Configuration 2 with 160, 200, 240 MHz.

4.  Test Configuration 6 with 160, 200, 240 MHz.

5.  Test Configuration 3, 4, 7, 8 with 200 MHz only