> Beam Loss Monitor Upgrade Users' Guide

Al Baumbaugh\
Craig Drennan\
Brian Fellenz\
Kelly Knickerbocker\
Jonathan Lewis\
Stephen Pordes\
Randy Thurman-Keup\
Mike Utes\
Jin-yuan Wu

November 14, 2023

BEAMS-DOC-1410-V8

*Abstract*

The new BLM readout system is designed to perform several tasks: to
provide a flexible and reliable abort system to protect Tevatron
magnets; to provide loss monitor data during normal operations of the
Tevatron, Main Injector and Booster; and to provide detailed diagnostic
loss histories when an abort happens. Beam losses are detected using the
same ion chambers that have been used with the legacy system.

# System Overview

The basic principle of operation of the new BLM system is to integrate
for a short period of time, typically 21 μs, and digitize to 16 bits.
There are two integrators per channel, running in a "Ping-Pong" mode,
alternating between charge integration and digitization, so that no loss
is missed. While one channel is integrating, the other is digitized, its
integrator is reset, and the data are processed. The reset and
processing time set a lower limit of 15 μs. The digital data are used to
construct several numbers that are compared against thresholds to
generate abort signals. These constructed data are sliding sums, which
are a measure of the integrated loss over a variety of time scales from
a single reading to a period of up to 64k cycles. The abort signal is
made in firmware by looking at these sums and thresholds as well as the
number of channels requesting an abort.

The new BLM system uses a standard 6Ux160mm VME format crate. Besides
the VME crate computer in Slot 1 that communicates data to the main
control system, the BLM system includes five types of custom cards:

-   Digitizer Cards (DC)

-   Timing Card (TC)

-   Control Card (CC)

-   High Voltage card (HV)

-   Abort Card (AC)

A custom J2 backplane is used for local system communication. A Control
Bus using the user-defined pins on the J2 VME connector handles all of
the critical BLM controls. This bus has 13 address lines and 8 data
lines. The CC is the only master on this bus, and the other cards are
slaves. Also on the J2 connector is an Abort Bus where the AC is the
master and the digitizer cards are the slaves (see Figure 1).

![](media/image1.wmf)

Figure

1: Block diagram of a BLM crate.

The sliding sum time scales and corresponding buffers and abort channels
are referred to either by the sum (or abort number) or intended time
scale. These are as follows:

  ------------ --------------------- ----------------- -------------------
  **Number**   **Name**              **Typical\        **Circular Buffer\
                                     Time Scale**      Depth**

  0            Immediate             20 μs             64k

  1            Fast                  1 ms              16k

  2            Slow                  50 ms             4k

  3            Very Slow             1 s               4k
  ------------ --------------------- ----------------- -------------------

In this document, we include a summary description of each of the
components followed by a description of the bus and communications
protocol and detailed descriptions of the functions performed by each
module including address maps.

## Digitizer Card

The Digitizer Card (DC) integrates and digitizes the current from four
loss monitor chambers each beam revolution. To avoid dead time between
measurements, signals for each input are switched between the two
channels of a TI/Burr-Brown ACF2101 integrator chip (see \[2\] for tests
of the integrator chip). Results are digitized from the two channels on
alternate cycles and fed to on-board FPGA devices.

The digitizer has 16 bit resolution with scaling such that one digitizer
count represents 15.26 fC of charge in the integrator. The sensitivity
of the BLM ion chamber is approximately 70 nC of charge per Rad.

The logic maintains three running sums per channel with programmable
durations of up to 65,536 base clocks (1.4 seconds for the Tevatron) and
compares the current measurement and the running sums to abort
thresholds (4 thresholds in all). Each threshold can be set
independently for each channel. There can be up to 15 digitizer cards in
a crate. We envision sliding sums with periods of approximately 1 ms, 50
ms and 1s for normal operation.

The block diagram in Figure 2 illustrates the signal processing for each
channel. Note that the Sum registers will be read and the Threshold
Registers written over the BLM Control Bus. The SRAM memory which stores
the integrator output values can be read over the VME bus (J1) by the
crate computer.

![](media/image2.png){width="5.59375in" height="7.126388888888889in"}

Figure

2: Block diagram of the signal processing for one of the four channels
on the Digitizer Card.

## Timing Card

The Timing Card (TC) receives accelerator system-wide timing information
from three sources, the Tevatron Clock (TCLK), the Beam Sync Clock
(BSCLK) and Machine State Data (MDAT).

The TC decodes BSCLK to generate the BLM system master clock which it
distributes on the BLM Control Bus. For the Tevatron this will be
generated from the AA marker with a \~21 μs period. For the Main
Injector it will be half the AA marker frequency for a period of \~22
μs. The master clock signal is known as *Make_Meas* ("Make
Measurement").

The TC maintains a 64k circular buffer of timing information for each
cycle including a 32-bit Unix time (seconds since 1970) and a 24-bit
microsecond counter which is reset at one second intervals; this buffer
is in parallel with the circular buffer of loss measurements in the
Digitizers. The master clock defines the integration interval of the
Digitizers and sets the threshold-comparison timing and abort-logic
comparison timing. The TC also generates signals at appropriate
intervals to cause the Digitizers to latch the current values of the
sliding sums and the Control Card to read these sums with the latched
timing information.

The TC decodes TCLK and puts TCLKs requested by the CC into a queue that
is readable by the CC through the Control Bus. In addition, other events
from TCLK are used to signal the BLM system to collect and store
synchronous ring-wide data samples for beam studies.

The MDAT signal is decoded to determine the machine state. State changes
are made available to the CC through another Control Bus accessible
queue that the Control Card reads to determine the appropriate abort
thresholds and logic to load when the machine state changes.

## Control Card

To ensure that data communications and other tasks running on the VME
crate computer do not impact the reliability of the BLM abort logic, the
Control Card (CC) provides an independent dedicated processor that
manages the setting of abort thresholds and other parameters used in the
abort logic. The Control Card CPU is a Zilog eZ80\--a 24-bit address,
8-bit data, 45 MHz microcontroller.

The CC communicates with the other system cards over the dedicated
custom J2 backplane keeping local communications separate from VME data
transfers. The CC also maintains circular buffers that store the
histories of the three running sums for each digitizer channel with time
stamps provided by the TC. The histories will be at least 4096 time bins
deep and are stored in a dual port memory[^1], allowing the crate
computer to read them at any time. In addition, the most recent entry
can be saved to one of three different buffers in response to a Flash,
Profile, or Display TCLK event. The CC also stores abort thresholds for
each of the sums for each channel for up to 256 machine states. When a
change in accelerator state is detected, the CC updates the thresholds
in the Digitizer Cards as well as the abort masks and multiplicity
requirements in the Abort Card.

## Abort Card

The four abort signals from each channel on each Digitizer Card are read
by the Abort Card every integration interval. The aborts of a particular
type are counted and compared to a programmable multiplicity requirement
for that abort type. It is possible to mask channels off in the AC so
they do not participate in the count. If the multiplicity for that
integration interval equals or exceeds the threshold, a beam abort
signal is generated. This logic is illustrated in Figure 3. To
accommodate the different operating conditions, the abort masks and
multiplicity thresholds in the Abort Card can change depending on the
Machine State. We have also included a serial link on the Abort Card to
allow a single point to receive information from all the BLM crates
around the ring to be able to implement a ring-wide abort condition.

![](media/image3.png){width="4.670138888888889in"
height="5.372222222222222in"}

Figure

3: Abort Card multiplicity logic.

## Turn-by-Turn Buffers

In addition to the diagnostic buffers maintained by the Controller Card,
which are circular buffers that are periodically overwritten, the BLM
system has two linear buffers in the Digitizers and Timing Card that are
triggered and are not automatically overwritten. These buffers are
Turn-By-Turn (TBT) and are each 8k deep. The TBT Buffers are designed to
match the capability of the new BPM system and allow the simultaneous
sampling of beam position in the BPM and beam losses in the BLM.

The injection TBT buffer (ITBT) is designed to match the BPM injection
TBT buffer and is triggered by *ITBT_Trig* at injection. The studies TBT
buffer is designed to match the BPM TBT buffer used for beam studies and
is triggered by *STBT_Trig*. Both of these triggers are generated on the
TC by clock events on TCLK or BSCLK. When either of these TBT buffers is
triggered, the DCs and TC will set a bit in a status register indicating
the TBT operations are in progress and that the TBT memory is not
accessible from VME. Once the TBT operation completes, or if an abort
happens, the DCs and TC will reset the status bit, and VME will have
access to the TBT memory. TBT operations require the DCs and TC to not
only write the large 64k circular buffer each sample period, but to also
write the data into the TBT buffer each sample period.

Once it has been triggered, the TBT buffer will fill to its limit of 8k
and stop. It will not be overwritten until the next relevant clock event
happens. If another trigger happens prior to the completion of the
current TBT operation, the TBT pointer will be reset to 0, and 8k of new
TBT data will be written into the TBT buffer.

If a *STBT_Trig* happens during an ITBT operation, the ITBT operation is
ended and the STBT pointer is set to 0 and a STBT operation is started.
Thus only a single TBT operation is allowed at any given time. If this
happens the host should be able to fully reconstruct the ITBT data using
the ITBT and STBT buffers and their time stamps.

## Chassis

The Chassis is an integrated 6Ux160mm VME crate, power supply and fan
fabricated by Weiner. In addition to the J1 backplane that is being
fabricated by Weiner, each crate includes a custom J2 backplane that
handles the BLM control bus with all lines bussed on the A and C rows
for slots 4-21. Slots 1-3 will have no backplane connections on rows A
and C. Row B includes the standard extensions for A32D32 VME operation.
The power supply blocks the rear of the backplane, so transition modules
cannot be used in a BLM crate. The Wiener fan tray also includes an
Ethernet -- TCP/IP interface which enables slow control and monitoring
via web browser, and provides a serial link to the crate processor via
telnet. See \[3\], \[4\], and \[5\] for various performance studies of
the custom backplane.

## BLM Crate Normal Operations Sequence

Once the CC loads the settings into the TC, DCs and AC, the system is
ready to run. The BLM operations are initiated by a clock event such as
"Prepare for Beam" which will cause the CC to tell the TC to issue a
Digitizer Card Reset (*DC_Reset*) on the control bus. The *DC_Reset*
causes the DCs to zero all sliding sums and causes the DCs, TC, and AC
to reset all circular buffer pointers. This assures that all buffers are
synchronized and ready to take data.

The primary clock for the BLM system, *Make_Meas*, is derived from the
AA marker on the beam sync clock (typically 21 μs). *Make_Meas* is
transmitted on the BLM control bus to all BLM cards. Optionally the
*Make_Meas* signal can be created by dividing the AA marker or by
dividing down an internal clock. The shortest allowable period for this
signal is 15 microseconds due to the reset time needed by the
integrators.

On the digitizer cards, the *Make_Meas* signal defines the sample
period, causing the ACF2101 integrators to switch between channels for
each input and triggering the ADCs to digitize the charge for the
channel not being integrated. After that, the sliding sums are updated
and all abort comparisons are made. At this time the new ADC readings
are written to a 64k deep circular buffer which is used for diagnostic
purposes as well as the source of the sliding sums. The new ADC data may
also be written to one of two turn-by-turn (TBT) dedicated studies
buffers. The abort states are latched on the next *Make_Meas*. Thus the
DC has the full sample period to do its conversions, make the sliding
sums and do the abort compare with thresholds. The timing card stores
real-time clock data on each cycle in a 64k deep circular buffer that is
synchronized with those of the digitizers.

On the AC, the *Make_Meas* signal causes the abort summing state machine
to cycle through each BLM channel by putting the channel address
ACS(5:0) on the abort bus and to read back from each channel the state
of each of its abort requests ABORT(3:0). For each abort type, each
channel has an abort mask bit which determines if that channel is
allowed to request an abort of that type. A count is made for each of
the four abort types of allowed AND requesting channels (i.e. those
above threshold). If the number of channels requesting an abort for any
of the four abort types equals or exceeds the abort multiplicity setting
for that abort type, an abort request is transmitted from the card on a
50Ω TTL line driver.

The *Make_Meas* signal, therefore, causes the data to be taken and the
abort logic to be updated every cycle. While a sliding sum might be the
sum over 500 samples (10 ms) its abort threshold is compared every 21
µs.

During each 21μs cycle, the DCs make and update the three sliding sums
of samples. These sliding sums are compared every cycle to their abort
limits. However, for diagnostic purposes, these sums are stored
periodically in circular buffers on the Control Card. This process is
controlled by the TC, which periodically generates 3 latch signals, one
for each sliding sum. The latch signals cause the DCs to latch the
appropriate sum and the TC to latch the time stamp and to interrupt the
CC so that it knows the data is latched and ready to be read and stored
in the appropriate circular buffer. The individual ADC readings are 16
bits; however, the sliding sums are 32 bit numbers. Therefore, the
dynamic range of, for example, the 1 second sliding sum is almost 32
bits. These sliding sums are the total integrated loss over the sum
interval, not just samples of losses spaced in time.

At any given time, the BLM has a variety of stored loss histories with
different time resolutions: the 64k deep raw measurement buffer provides
1.4 seconds of loss data with 21 µs resolution; the 16k Fast circular
buffer provides 16 seconds of integrated loss data with 1 ms resolution,
the 4k Slow circular buffer provides 200 seconds of integrated loss data
with 50 ms resolution; and the 4k Very Slow buffer provides 4096
seconds, over an hour, of integrated loss data with 1 second resolution.
As one can see, in the event of an abort, there is a very detailed
history of losses prior to the abort, which may be examined to aid in
diagnosing the problem.

## Card Addresses

The system communicates with the outside world via ACNET through a
standard VME host CPU. This VME host sets the parameters in the BLM
system trough a block of shared memory in the Control Card. An overview
of the BLM addressing scheme is given in Table 1. In this document,
unless otherwise specified, all VME and control-bus addresses are
specified in hexadecimal. VME addressing is based on 8-bit bytes, but
the BLM system uses 16-bit data. Therefore, the lowest address bit (A0)
is always assumed to be 0 for VME.

Table

1: Overview of BLM addressing scheme. Detailed switch/jumper settings
are available in \[1\].

  ----------------------------------------------------------------------------------------------
  **Board Type and   **Switch   **VME      **VME Address range**              **Control Bus
  \#**               or Jumper  Address                                       Address Range**
                     Setting    Type**                                        
                     (hex)**                                                  
  ------------------ ---------- ---------- ---------------------------------- ------------------
  Control Card       09         A32        09000000 -- 09FFFFFE               Master

  Timing Card        0B         A32        0B000000 -- 0B0FFFFE               1000 -- 10FF

  Timing Card Bridge            A32        0B100000 -- 0B101FFE               Master

  Abort Card         0A         A32        0A000000 -- 0A3FFFFE               1100 -- 11FF

  A0 Abort Card      0C         A32        0C000000 -- 0C3FFFFE               N/A

  HV Card            08         A32        08000000 -- 08000FFE               N/A

  Digitizer #0       0          A24        000000 --0FFFFE                    0000 -- 00FF

  Digitizer #1       1          A24        100000 --1FFFFE                    0100 -- 01FF

  Digitizer #2       2          A24        200000 --2FFFFE                    0200 -- 02FF

  \- - - - - - -     \- - - - - \- - - - - \- - - - - - - - - - - - - - - - - \- - - - - - - - -

  Digitizer #D       D          A24        D00000 --DFFFFE                    0D00 -- 0DFF

  Digitizer #E       E          A24        E00000 --EFFFFE                    0E00 -- 0EFF

  Digitizer          N/A        N/A        N/A                                1300 -- 13FF
  Broadcast                                                                   
  ----------------------------------------------------------------------------------------------

The BLM system has essentially 3 busses, a VME bus, the BLM Control bus
on the A row of J2, and the Abort Bus on the C row of J2. All operations
on the Abort bus are done from the AC via its state machine. All
operations on the Control bus are done from the CC via eZ80 software. In
systems without a CC, VME can access the control bus only via a bridge
on the TC. Normally VME places data into the shared memory on the CC,
and the CC puts that data into the hardware. The pin assignments of the
J2 backplane are shown in Table 2. (Note that slots 1-3 on J2 are
standard VME A32D32 with straight-through pins on rows A and C.) All
hardware parameters are sent by the CC over the dedicated BLM control
bus. This control bus has 13 address lines (CA12:0) and 8 data lines
(CD7:0). The digitizers use A24D16 addressing on VME while all other
boards use A32D16. All BLM data are integers where the lower byte
corresponds to the less significant bits.

There can be up to 15 digitizers per crate. Four switches on the
digitizers set the high four bits of the VME address (A23:20). They also
set the high four bits of the control bus address and the abort channel
select (*Abort_CS*). Each card has 256 bytes of address space (CA(7:0))
which makes up its memory register space. The Control Cards maintains a
setup table for each of a possible 256 machine states, and will load
this data into the hardware in response to an MDAT state change. These
settings affect only the Digitizer Cards and the Abort concentrator
card. The settings for the Timing card do not change with machine state,
and should only be changed during beam off periods. An important feature
of the BLM system is that all abort operations are handled by state
machines, once setup by the CC, these operations proceed without
intervention from either VME or eZ80. The only things that the CPUs do
is setup the parameters.

In order to smoothly update the settings in the DCs and AC, these cards
must double buffer all registers. This double buffering is accomplished
in two ways. The AC transfers data to the actual usage register via a
backplane signal, *Update_Settings,* which will occur after all settings
have been written and will be generated on the TC, synchronously with
*Make_Meas*, in response to a command from the CC. When the DC is in
original memory map mode, it functions just like the AC. When the DC is
in native memory map mode, it utilizes a paging system for storing
thresholds and as such doesn't use the *Update_Settings* line (with a
few exceptions). The double buffering is accomplished by the CC writing
to a different page than is currently used and then switching the DC to
the new page. See Section 2.2 for details about the memory models in the
DC.

## Backplane Signal Functions

The operation of the digitizer card is controlled by signals on the
control bus. These signals are:

-   *Reset* \[C21\]: This signal is the BLM Crate reset signal driven by
    the Controller Card (CC). It resets the state machine on the DC and
    TC. This pin is driven by eZ80 I/O pin PB1.

-   *Reset_DC* \[C20\] "Reset Digitizer Card.": This signal clears the
    sliding sums and resets the DC raw measurement data (RMD) pointer
    and TC time-stamp pointer to FFFF. This signal typically is used to
    initialize the DC and TC and get ready for data taking.

-   *Make_Meas* \[C22\] "Make Measurement": This signal causes the DC to
    switch integrator channels, latches the previous abort states,
    digitizes the reading, resets the integrator, calculates the sliding
    sums, and makes the abort comparisons. This signal is generated on
    the TC and typically runs continuously at about once every 20
    microseconds. The sliding sums are made by adding the current
    reading to the sum and subtracting the oldest reading from the sum.
    The 3 sliding sums have 3 oldest data pointers, which point to the
    data in the RMD that is to be subtracted. There is also new data
    pointer, which sets the location in the RMD where the newest reading
    is stored. When *Make_Meas* is generated, the TC also stores the
    real time in the 64k deep time-stamp buffer. *Make_Meas* triggers
    the AC to query the abort states of the digitizers and to store the
    results in the 64k deep abort buffer.

-   *Fast_Latch* \[C15\]: This signal is produced on the TC to tell the
    DC state machine to latch the current Fast_Sum into a register so
    the controller can read it. The TC latches the time stamp as well.
    Each of these latch signals also sets a bit in a register and causes
    the TC to assert the IRQ2 line so that the CC knows to fetch data
    into its larger circular buffers.

-   *Slow_Latch* \[C16\]: This signal is produced on the TC to tell the
    DC state machine to latch the current Slow_Sum into a register so
    the controller can read it. The TC latches the time stamp as well.

-   *VSlow_Latch* \[C17\]: This signal is produced on the TC to tell the
    DC state machine to latch the current Very_Slow_Sum into a register
    so the controller can read it. The TC latches the time stamp as
    well.

-   *Abort_CS(0:5)* \[C10:14,27\] "Abort Channel select": These signals
    come from the Abort Controller (AC) and are used to poll all the
    channels to request abort demand conditions. The DC state machine
    compares Abort_CS(2:5) with the address switch values to determine
    if the requested channel is on the board. Abort_CS(0:1) signify
    channels 0-3 on the board. When selected, each channel's four abort
    lines are driven onto the bus's Abort(0:3) lines. A channel
    requesting an abort drives the corresponding line low.

-   *Abort(0:3)* \[C5:8\] "Abort lines 0,1,2,3": These are the abort
    requests driven by the DC to the AC in order for the AC to determine
    how many channels are requesting an abort for each of the four abort
    types.

-   *Abort_Sync* \[C28\] This signal is produced on the TC to trigger
    the ring-wide serial abort link. The special abort card at A0
    listens for this trigger which is generated every 2 ms and initiates
    the next data collection sequence on the link.

-   *CA(0:12)* \[A1:12\] "Control Bus Address": These are used to
    address control and data within the state machine. These are driven
    by the CC.

-   *CD(0:7)* \[A19:26\] "Control Bus Data": These are the data lines
    used to read and write data to and from the state machine.

-   *MREQ\** \[A15\] "Memory Request": This active-low signal indicates
    to the DC, AC, and TC that the CC is sending a valid address on the
    control bus for them to parse. The eZ80 on the CC uses the same
    address space for control bus operations as well as memory
    operations. Thus addresses are valid on the bus only if *MREQ\** is
    low.

-   *MemRD\** \[A16\] "Memory Read": Indicates that the current Control
    Bus cycle is a read from the bus by the CC. This is active low and
    should go down at the same time as *MREQ\**.

-   *WE\** \[A17\] "Memory Write Enable": This is the write strobe for
    data. Data should be latched on the rising edge of WE\*. WE\* is
    pulled low by the eZ80 on the CC (or by the control-bus bridge on
    the TC).

-   *Update_Settings* \[C29\]: The abort thresholds, masks and
    multiplicities are double buffered on the DC and AC with current
    values and set values. After the CC is notified by the TC of an MDAT
    event, it updates the set values. When all values have been written,
    it sets *Update Settings* to notify the DC and AC to move the set
    values to be the current values which are then used in abort
    decisions.

-   *ITBT_Trig* \[C2\] "Injection Turn-by-Turn Trigger": Causes the raw
    data to be written into the 8k ITBT buffer. Once the buffer is full
    or the system stops, this data is readable via VME. The trigger is
    caused by the TC receiving a programmable TCLK event.

-   *STBT_Trig* \[C3\] "Studies Turn-by-Turn Trigger": Causes the next
    8k raw measurement data to be written into the STBT Buffer. Once the
    buffer is full or the system stops, this data is readable via VME.
    Note: If a STBT trigger happens while an ITBT is in progress, the
    ITBT is terminated and the STBT operation is initiated. If either of
    these is in operation a bit is set in a status register and VME is
    not allowed to read the TBT data. The TC sends *STBT_Trig* after
    receiving a programmable BSCLK event.

-   *ChOK* \[C1\] "Channel OK": Sent by the digitizer to the abort card
    with the abort data to indicate that the channel is working
    properly. If *ChOK* is low, the AC ignores the data and interrupts
    the CC.

-   *AIP* \[C19\] "Abort in Progress": In normal operation *AIP* is sent
    by the TC with a programmable delay after receiving the
    Abort-in-progress TCLK event (\$47). *AIP* on the control bus stops
    all circular buffers and allows the 64k-deep raw data buffers on the
    DCs and TC to be read. *AIP* is latched until reset by external
    control. *AIP* can also be set by-hand in the TC.

-   *IRQ0* \[A28\] "Interrupt Request 0": Timing Card notification to
    Control Card that a TCLK event has been loaded into the TCLK FIFO.

-   *IRQ1* \[A29\] "Interrupt Request 1": Timing Card notification to
    Control Card that an MDAT state change has occurred and the new
    state is ready to be read.

-   *IRQ2* \[A30\] "Interrupt Request 2": Timing Card notification to
    Control Card that one or more of the Fast, Slow, or Very Slow
    latches has fired and the data is ready to read and placed in the
    circular snapshot buffers on the CC

-   *IRQ3* \[A31\] "Interrupt Request 3": Abort Card notification to
    Control Card that the AC needs servicing, either it has channel NOT
    OK bits, or is requesting ABORT.

-   *CPU_Detect* \[C23\]: Pulled low by CC when plugged into the crate.
    This disables the control-bus bridge on the TC.

-   *Error* \[A32\]: Set if any of the cards senses an internal error.
    This allows the CC to set a VME interrupt to notify the front-end
    CPU to send an alarm. This pin is routed to pin 89 on the eZ80 chip
    (*a.k.a.* General Purpose I/O pin PB2).

-   *Osc* \[C31\] Oscillator: 10 MHz from timing card internal
    oscillator

-   *BusReq* \[C25\] and *BusAck* \[C26\]: For future expansion if
    needed. These allow for a second master such as a DMA controller to
    request control of the bus from the eZ80 by pulling the BusReq low,
    the eZ80 responds by placing all of its control and address lines
    into a high impedance state and pulling the BusAck low to signal
    that the requesting device can now use the bus.

Table

2: J2 backplane connector pinout.

  -------------------------------------------------------------------------------------------------------
  **Pin**   **Row A**                             **Row B**      **Row C**                     
  --------- -------------- ----------- ---------- -------------- ----------------- ----------- ----------
            **Function**   **Write**   **Read**   **Function**   **Function**      **Write**   **Read**

  1         CA0            C           DTA        +5V            ChOK              D           A

  2         CA1            C           DTA        Gnd            ITBT_Trig         T           D

  3         CA2            C           DTA        Reserved 1     STBT_Trig         T           D

  4         CA3            C           DTA        VME-A24        Abort4 (spare)                 

  5         CA4            C           DTA        VME-A25        Abort0            D           A

  6         CA5            C           DTA        VME-A26        Abort1            D           A

  7         CA6            C           DTA        VME-A27        Abort2            D           A

  8         CA7            C           DTA        VME-A28        Abort3            D           A

  9         CA8            C           DTA        VME-A29        Gnd                            

  10        CA9            C           DTA        VME-A30        Abort_CS0         A           D

  11        CA10           C           DTA        VME-A31        Abort_CS1         A           D

  12        CA11           C           DTA        Gnd            Abort_CS2         A           D

  13        CA12           C           DTA        +5V            Abort_CS3         A           D

  14        Gnd                                   VME-D16        Abort_CS4         A           D

  15        MREQ\*         C           DTA        VME-D17        Fast_Latch        T           D

  16        MEMRD\*        C           DTA        VME-D18        Slow_Latch        T           D

  17        WR\*           C           DTA        VME-D19        V SIow_Latch      T           D

  18        Gnd                                   VME-D20        Gnd                            

  19        CD0            CDTA        CDTA       VME-D21        AIP               T           DA

  20        CD1            CDTA        CDTA       VME-D22        Reset DC          T           DTA

  21        CD2            CDTA        CDTA       VME-D23        Reset             C           DTA

  22        CD3            CDTA        CDTA       Gnd            Make_Meas         T           DA

  23        CD4            CDTA        CDTA       VME-D24        CPU_Detect        C           T

  24        CD5            CDTA        CDTA       VME-D25        Gnd                            

  25        CD6            CDTA        CDTA       VME-D26        BusReq                        C

  26        CD7            CDTA        CDTA       VME-D27        BusAck            C            

  27        Gnd                                   VME-D28        Abort_CS5         A           D

  28        IRQ0           T           C          VME-D29        Abort_Sync        T            A

  29        IRQ1           T           C          VME-D30        Update_Settings   T           DA

  30        IRQ2           T           C          VME-D31        Gnd                            

  31        IRQ3           A           C          Gnd            Osc                            

  32        Error          DTA         C          +5V            Spare2                         
  -------------------------------------------------------------------------------------------------------

## Standard Board ID Block

The BLM system uses a fairly standard scheme for identifying modules.
Each module has an ID block containing board type, firmware versions,
and possibly authors (see Tables 3 and 4). These ID blocks allow the
crate to be mapped out to verify that the correct cards have been
installed in each crate. The ID check also forms a simple test for the
basic functioning of each module. In addition, each module has a serial
number encoded in a DS2401 serial device (see Tables 5 and 6).

Table

3: ID block structure.

  --------------- --------------- ---------------------------------------
  **Address**     **Size**        **Function**

  0000-0003       4 numbers       Board ID Number (ASCII)

  0004-002F       44 characters   Board ID Text String (ASCII)

  0030-009F       112 characters  Firmware version numbers, authors, etc
  --------------- --------------- ---------------------------------------

Table

4: ID block locations for each board. Note that the DC has 2 locations
since the 2 FPGAs are programmed independently and each ID block
contains the firmware version for that FPGA. The CC has a separate ID
block for the eZ80 software which is 48 bytes long.

  ------------------------- ------------------- --------------------------
  **Board**                 **Address**         **Board ID Number**

  Control Card\             NN700000\           0001
  FPGA\                     NN810000            
  eZ80                                          

  Timing Card               NN000000            0002

  Abort Card                NN000000            0003

  Digitizer Card\           N00000\             0004
  Integ FPGA\               N02100              
  Sums FPGA                                     

  HV Card                   NN000000            0005
  ------------------------- ------------------- --------------------------

Table

5: Word format for the serial number from the DS2401. The family code is
always 01 hex.

  -------- -------- -------- -------- -------- -------- -------- --------
  **Word            **Word            **Word            **Word   
  0**               1**               2**               3**      

  XX       XX       XX       XX       XX       XX       XX       01

  8-bit    48-bit                                                Family
  CRC      ID                                                    Code
           number                                                

           Board                                                 
           serial                                                
           number =                                              
           ( ID                                                  
           *mod*                                                 
           1000 )                                                
  -------- -------- -------- -------- -------- -------- -------- --------

Table

6: Location of Silicon IDs.

  --------------------------------------- -------------------------------
  **Board**                               **Address**

  Control Card                            NN7000F8

  Timing Card                             NN000200

  Abort Card                              NN000200

  Digitizer Card                          N00200

  HV Card                                 NN000200
  --------------------------------------- -------------------------------

## Temperature Sensors

The TC, AC, CC, and DCs are each equipped with a digital temperature
sensor. The CC, AC, and TC all use a National Semiconductor LM74 as the
temperature sensing device. The LM74 has 12-bit plus sign temperature
resolution (0.0625°C per LSB) while operating over a temperature range
of -55°C to +150°C. Temperature data is represented by a 13-bit, two's
complement word with an LSB (Least Significant Bit) equal to 0.0625°C.
The DC uses an Analog Devices TMP03 as the temperature sensing device.
The output of the TMP03 is encoded in the duty cycle of an output pulse
which is measured by the FPGA firmware with a LSB of 0.0625°C. The
temperature words for the TC, AC, and DCs are periodically copied by the
CC over the control bus and made available in the VME memory of the CC.
To convert to °C, one must multiply the signed value in Table 7 by
0.0625 (1/16 °C).

Table

7: Bit layout of temperature words. The words are all available on the
CC.

  ------------ ------------- ---------- -------- -------- -------- -------- -------- ------- ------- ------- ------- ------- ------- ------- ------- ------- -------
  **Device**   **Address**   **Bits**                                                                                                                        

                             **15**     **14**   **13**   **12**   **11**   **10**   **9**   **8**   **7**   **6**   **5**   **4**   **3**   **2**   **1**   **0**

  TC           NN800060      Signed                                                                                                          1       1       1
                             Value                                                                                                                           

  AC           NN800062                                                                                                                                      

  CC           NN7000F2                                                                                                                                      

  DC           NN800064...   Signed                                                                                                                          
                             Value                                                                                                                           
  ------------ ------------- ---------- -------- -------- -------- -------- -------- ------- ------- ------- ------- ------- ------- ------- ------- ------- -------

# Digitizer Card

The digitizer card is the primary data collector in the system. It
includes the following features:

-   4 loss-monitor channels, 4 dual integrators, 4 16-bit ADCs

-   4 16-bit DACs for analog (MADC) outputs

-   Control Bus Interface for setting parameters

-   512 Kbytes of RAM for storing Raw Measurement Data (RMD)

-   128 Kbytes of RAM for storing 2 banks of 8k TBT data

-   A VME interface used primarily for reading raw measurement data when
    the system is stopped and for reading TBT data when TBT is not in
    operation.

-   A 4-bit switch-selectable card number that sets the base address for
    the Control Bus, Abort Bus and VME. For digitizer cards on the
    Control Bus, CA12=0 and CA8:11=Switch for card select.

-   A state machine that runs the digitizer section and makes the 3
    sliding sums for each channel. It also maintains the RMD RAM
    circular buffer.

-   An Abort channel select and 4 abort line drivers, these 4 lines are
    for:

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-   Immediate Loss Abort threshold (few microseconds)

-   Fast Loss Abort Threshold (few milliseconds)

-   Slow Loss Abort Threshold (few 10s of milliseconds)

-   Very Slow Loss Abort Threshold (few seconds)

The reading of the raw measurement data (RMD) is allowed only when the
state machine is stopped, and this data is only available via the VME
interface. This is the only data available to VME on this card. The VME
Address lines 20:23 are compared with the 4-bit address switch to
determine if the card is being addressed. VME Address lines 1:2 are
channel select, VME address 0 is byte select (only used if reading in
byte mode) and VME address lines 3:18 are the 64k RMD pointer. Note that
the RMD is a 64k deep circular buffer used to store raw data; the time
stamps for this data are stored on the TC. In order to see raw
measurement data while running, there are two turn-by-turn buffers that
are described below in Section 1.5. VME is also able to read the card ID
Block and the board status at 30000.

The control bus address map of the digitizer is described in Tables 8
and 9. These are the offsets from the control bus base address for data
communication with the Control Card.

The response of the digitizer has been calibrated in prototypes. The
least count in the low integration range corresponds to a charge of
\~0.02pC or a loss of 0.3µRad. In the high range, the least count
corresponds to a factor of 5 more charge.

## Address Maps

BLM digitizer cards respond to A24D16 and may take nearly all of the
A24D16 address space (16 MB) since there may be up to 15 digitizer
cards. Each card uses the addresses N00000-NFFFFE where N is card number
0-E. The base address is set by switches on the board which determine
bits 20-23 \[1\]. The data are stored as follows as offset from the base
address.

  --------------- -------------------------------------------------------
  **Address**     **Description**

  00000-00FFE     Standard ID block (Sec. 1.10)

  01000           FPGA Reconfiguration Signal: COM_REG

  0100A           FPGA Reconfiguration Signal: DIAG1

  10000-1FFFE     64kB of Injection TBT Data (8k Turns, Increments)

  20000-2FFFE     64kB of Studies TBT Data (8k Turns, Increments)

  30000           Status Register

  80000-FFFFE     Raw Measurement Circular Buffers (64k turns)
  --------------- -------------------------------------------------------

The turn-by-turn linear buffers and raw circular buffers are addressed
as follows:

-   A2:A1 = Channel 0/1/2/3

-   A18:A3 = Index

The index for the raw buffer is set to 0000 on a reset and increments on
each *Make_Meas*. It resets when it reaches FFFF. The current location
is indicated by the RMD pointer which is located in a control bus
register.

The following table shows the bit definitions for the status register at
30000.

  --------- -------- -------- -------- -------- -------- ------- ------- --------- ------- ------- ------- ------- ------- ------- -------
  **Bit**                                                                                                                          

  **15**    **14**   **13**   **12**   **11**   **10**   **9**   **8**   **7**     **6**   **5**   **4**   **3**   **2**   **1**   **0**

                                                                         Running                                           TBT     AIP
  --------- -------- -------- -------- -------- -------- ------- ------- --------- ------- ------- ------- ------- ------- ------- -------

## Control Bus Address Maps

The digitizer card can be accessed from the control bus (CB) with 8 data
bits and 13 address lines. The upper bits of the address lines are used
to distinguish the modules in the crate. Each digitizer card is normally
given 256 bytes to be accessed by the control card.

The information accessible via CB is stored in the digitizer card using
block memories and registers implemented in the lower (sums03) FPGA.
There are 4 types information accessible via the CB: thresholds,
operation settings, sums and control registers. The thresholds and
operation settings are supported with a paging scheme. The data being
accessed by the CB and the data being used for module operation can be
different. The paging scheme allows users to avoid changing thresholds
and operation settings while they are being used. The pages being used
and being accessed are changed by writing corresponding control
registers. The sums are latched as if they are double buffered. However,
the sums are actually implemented using a rotating paging scheme. The
users are allowed to take further advantage of this sum implementation
in the sense that data from the previous 6 time periods are still
accessible via other pages.

The particular addresses of the contents can be assigned in two
different mappings: the original mapping and native mapping. The
registers are internally arranged in the digitizer cards using native
mapping. The registers can be remapped via an address translation ROM to
the original mapping so that the original test software can still be
used. In the native mapping, registers that are normally read at the
same time are grouped together to allow users to write faster and
simpler software. The switching between the mappings is purely a
software operation; simply set or reset bit 7 of the FF register (at
address 0xFF). The power on default is the original mapping for backward
compatibility with the Visual Basic test software.

The digitizer card also supports both individual and broadcast accesses.
Each digitizer card in the crate can be accessed individually at the
assigned card address. All the cards in the crate can be written
simultaneously at the broadcast address. The broadcast ability allows
the cards to change operation state (such as threshold page to be used)
together.

### Native Mapping

The native mapping of the digitizer card is shown in Table 8. The
digitizer presents the native register mapping when bit 7 of the FF
register is set (=1xxxxxxx_b).

Table

8: Native memory map of the DC.

  ------------- ---------- ------------------------ ------------------- -------------
  **Address**   **Access   **Register**             **Mode**            **Channel**
                Type**                                                  

  00            R/W        Abort Thresholds         Immediate           0

  04                                                                    1

  08                                                                    2

  0C                                                                    3

  10                                                Fast                0

  14                                                                    1

  18                                                                    2

  1C                                                                    3

  20                                                Slow                0

  24                                                                    1

  28                                                                    2

  2C                                                                    3

  30                                                Very Slow /         0
                                                    Integrated          

  34                                                                    1

  38                                                                    2

  3C                                                                    3

  40            R/W        Sum Lengths              Immediate           N/A

  42                                                Fast                N/A

  44                                                Slow                N/A

  46                                                Very Slow           N/A

  48            R/W        Constants                                    0

  4A                                                                    1

  4C                                                                    2

  4E                                                                    3

  50            R/W        Integration Squelch                          0
                           Level                                        

  52                                                                    1

  54                                                                    2

  56                                                                    3

  58            R/W        Pedestal_LO                                  0

  5A                                                                    1

  5C                                                                    2

  5E                                                                    3

  60            R/W        Pedestal_HI                                  0

  62                                                                    1

  64                                                                    2

  66                                                                    3

  68            R/W        Mode Select                                  0

  6A                                                                    1

  6C                                                                    2

  6E                                                                    3

  70            R/W        DAC Out                                      0

  72                                                                    1

  74                                                                    2

  76                                                                    3

  78            R/W        Test DAC                                     N/A

  7A            R/W        MaxDY (=0x80)                                N/A

  7C            R/W        CIC Length (=124-128)                        N/A

  7E            R/W        Ped Length (=750-752)                        N/A

  80            R          Sums                     De-rippled          0

  84                                                                    1

  88                                                                    2

  8C                                                                    3

  90            R                                   Fast                0

  94                                                                    1

  98                                                                    2

  9C                                                                    3

  A0            R                                   Slow                0

  A4                                                                    1

  A8                                                                    2

  AC                                                                    3

  B0            R                                   Very Slow           0

  B4                                                                    1

  B8                                                                    2

  BC                                                                    3

  C0            R          Integration / CIC_WF                         0

  C8                                                                    1

  D0                                                                    2

  D8                                                                    3

  E0            R/W        THR U page                                   N/A

  E1            R/W        THR C page                                   N/A

  E2            R/W        Constant U page                              N/A

  E3            R/W        Constant C page                              N/A

  E4            R/W        Sum U page                                   N/A

  E5            R/W        Sum F page                                   N/A

  E6            R/W        Sum S page                                   N/A

  E7            R/W        Sum V page                                   N/A

  E8            N/A        Unused                                       N/A

  F6            R          Circular Buffer PT                           N/A

  F8            R/W        FPGA Ctrl Reg.                               N/A

  FA            N/A        Unused                                       N/A

  FC            R          Temperature                                  N/A

  FE            N/A        Unused                                       N/A

  FF            R/W        FF reg                                       N/A
  ------------- ---------- ------------------------ ------------------- -------------

The thresholds from addresses 0x00 to 0x3F are 32-bit numbers each
occupying 4 bytes and stored in Little Endian format, *i.e.* the LSB of
the threshold occupies the lowest address. There are 64 pages of
thresholds. The pages being used and being accessed via CB are
represented by the lower 6 bits of the "THR U page" (at 0xE0) and the
"THR C page" (at 0xE1) registers, respectively.

The addresses from 0x40 to 0x7F contain the settings for the module
operation. There are 8 pages for this class of information. The pages
being used and being accessed via CB are represented by the lower 3 bits
of the "Constant U page" (at 0xE2) and the "Constant C page" (at 0xE3)
registers, respectively.

The addresses from 0x80 to 0xDF are assigned for sums. The fast, slow
and very slow sliding sums are 32-bit integers occupying 4 bytes each in
Little Endian format. The immediate measurements are implemented as
sliding sums with a sum length = 1. On power on, the sum length (at 0x40
and 0x41) for immediate is automatically preset to 1, i.e., (0x40) =
0x01 and (0x41) = 0x00. The users need not set the immediate sum length
for regular operation. The immediate sums are stored internally but not
output. Instead, the de-rippled sums are output at addresses 0x80 to
0x8F, 4 bytes for each channel. The de-rippled sums are for display only
and are not used to compare with thresholds. The integrations are 64-bit
integers and are readout from 0xC0 to 0xDF in normal operation. Two
other numbers useful for debugging, the baseline waveform, WF, and the
CIC sums can be readout form the integration locations if bit 4 of the
FF register is set to 1. The CIC sum is a sliding sum of a sliding sum.
It filters out higher frequency noise better than sliding sum. The
baseline waveform is stored in internal memory and used in de-ripple
process. It is a sample of the noise present when there are no losses.

There are 8 pages for the sums. The pages being used and being accessed
via CB are specified by the lower 3 bits of the "Sum U page" (at 0xE4),
the "Sum F page" (at 0xE5), the "Sum S page" (at 0xE6) and the "Sum V
page" (at 0xE7) registers, respectively. All the page registers are
reset on power up and can be read and written by the Controller Card.
When the latch sum signals for fast, slow and/or very slow become
active, the sum F, S and/or V pages are updated to the current value of
the Sum U page and then the Sum U page increases by 1. So the
corresponding pages for different sum types point to the last latched
values unless more than 8 latch commands have been issued before the
sums are readout. Bit 7 of the sum F, S and V page registers are used to
prevent the registers from being updated by the latch sum signals. The
user may set the bit 7 of the page registers before reading the sums so
that the contents are not corrupted by the new latch sum signals.

The contents of de-rippled sums and the integrations are pointed by the
Sum F page and the Sum V page registers, respectively.

### Original Mapping

The original mapping is shown in Table 9. The digitizer presents the
original mapping when bit 7 of the FF register is reset (=0xxxxxxx_b).
The original mapping is also the power on default condition since the
original test software doesn't know about the two mappings.

Table

9: Original memory map of the DC. This mode is used during bridge
program use.

  ------------- ---------- --------------------- --------------------- -------------
  **Address**   **Access   **Register**          **Mode**              **Channel**
                Type**                                                 

  00            R/W        Abort Thresholds      Fast                  0

  04                                             Slow                  0

  08                                             Very Slow /           0
                                                 Integrated            

  0C                                             Immediate             0

  10            R          Sums                  Fast                  0

  14                                             Slow                  0

  18                                             Very Slow             0

  1C            R/W        Mode Select                                 0

  1E            R/W        DAC Out                                     0

  20            R          Sum                   De-rippled            0

  22            R/W        Pedestal_HI                                 0

  24            R/W        Constant                                    0

  26            R/W        Pedestal_LO                                 0

  28            R          Integration / CIC_WF                        0

  30            R/W        Threshold             Fast                  1

  34                                             Slow                  1

  38                                             Very Slow /           1
                                                 Integrated            

  3C                                             Immediate             1

  40            R          Sums                  Fast                  1

  44                                             Slow                  1

  48                                             Very Slow             1

  4C            R/W        Mode Select                                 1

  4E            R/W        DAC Out                                     1

  50            R          Sum                   De-rippled            1

  52            R/W        Pedestal_HI                                 1

  54            R/W        Constant                                    1

  56            R/W        Pedestal_LO                                 1

  58            R          Integration / CIC_WF                        1

  60            R/W        Threshold             Fast                  2

  64                                             Slow                  2

  68                                             Very Slow /           2
                                                 Integrated            

  6C                                             Immediate             2

  70            R          Sums                  Fast                  2

  74                                             Slow                  2

  78                                             Very Slow             2

  7C            R/W        Mode Select                                 2

  7E            R/W        DAC Out                                     2

  80            R          Sum                   De-rippled            2

  82            R/W        Pedestal_HI                                 2

  84            R/W        Constant                                    2

  86            R/W        Pedestal_LO                                 2

  88            R          Integration / CIC_WF                        2

  90            R/W        Threshold             Fast                  3

  94                                             Slow                  3

  98                                             Very Slow /           3
                                                 Integrated            

  9C                                             Immediate             3

  A0            R          Sums                  Fast                  3

  A4                                             Slow                  3

  A8                                             Very Slow             3

  AC            R/W        Mode Select                                 3

  AE            R/W        DAC Out                                     3

  B0            R          Sum                   De-rippled            3

  B2            R/W        Pedestal_HI                                 3

  B4            R/W        Constant                                    3

  B6            R/W        Pedestal_LO                                 3

  B8            R          Integration / CIC_WF                        3

  C0            R          Sums                  Immediate             0

  C4                                                                   1

  C8                                                                   2

  CC                                                                   3

  D0            R/W        Integration Squelch                         0
                           Level                                       

  D2                                                                   1

  D4                                                                   2

  D6                                                                   3

  DA            R/W        MaxDY (=62)                                 N/A

  DC            R/W        CIC Length (=124-128)                       N/A

  E0            R/W        THR U page                                  N/A

  E1            R/W        THR C page                                  N/A

  E2            R/W        Constant U page                             N/A

  E3            R/W        Constant C page                             N/A

  E4            R/W        Sum U page                                  N/A

  E5            R/W        Sum F page                                  N/A

  E6            R/W        Sum S page                                  N/A

  E7            R/W        Sum V page                                  N/A

  EA            R/W        Ped Length (=750-752)                       N/A

  EC            R/W        Sum Length            Immediate             N/A

  F0                                             Fast                  N/A

  F2                                             Slow                  N/A

  F4                                             Very Slow             N/A

  F6            R          Circular Buffer PT                          N/A

  F8            R/W        FPGA Ctrl Reg.                              N/A

  FA            R/W        Test DAC                                    N/A

  FC            R          Temperature                                 N/A

  FE            N/A        Unused                                      N/A

  FF            R/W        FF reg                                      N/A
  ------------- ---------- --------------------- --------------------- -------------

### Broadcast Access

The CB address space has 13 bits. The digitizer card individual access
address is 0x0NXX, where N = 0 to E is the board switch setting and XX =
00 to FF is the byte address.

The digitizer card broadcast access uses the address space outside the
above. The address is 0x13XX which is unused by any card. In the
broadcast access address space, all digitizer cards are selected as
being individually accessed.

-   Writing to a location in 0x13XX causes the addressed byte in all
    cards being written with the same value.

-   Reading in the 0x13XX space is not recommended since the bus
    conflict may be resulted in. Reading-after-writing is allowed since
    the anticipated values from all cards are identical but may not be
    very useful.

The broadcast access is essentially used to change the operating
condition of all cards simultaneously. For example, one may change the
threshold page being used when a machine state change is needed.

## Control Bus Registers

### FF Register

The FF register is always at address 0xFF in both native and original
mapping.

  ---------- -------- -------- -------- -------- -------- -------- --------
  **Bits**                                                         

  **7**      **6**    **5**    **4**    **3**    **2**    **1**    **0**

  Mapping    Ch OK             Out\              Do Sums  Clear    
                               De-Bug                     Sums     
  ---------- -------- -------- -------- -------- -------- -------- --------

-   Bits 1 and 2 are used to initialize sum operations without a timing
    card. Turning bit 1 high and then low causes the digitizer card to
    initialize the summing operation. Turning bit 2 high and then low
    causes the digitizer card to accumulate sliding sums and
    integrations.

> The summing operation via toggling the FF register bits 1 and 2 is
> usually for debugging purposes and the input data are always the
> constants stored in addresses 0x48 to 0x4F. The bit 0 in the FPGA
> Control Register should be set in order to use constant as the summing
> and integration input.

-   Bit 4 specifies that the baseline waveform and the CIC sums should
    be made available in the space normally used for integrated values.

-   Bit 6 Enable/Disable the *ChOK* line on the Abort Bus backplane. The
    channel OK line is not currently connected to anything meaningful,
    so this bit should be 0.

-   Bit 7 of the FF register is used to control the mapping for the
    Control Bus. In this document, native mapping is used when referring
    to Digitizer Card Control Bus addresses, which requires bit 7 being
    set. To use the original mapping, bit 7 is cleared.

### FPGA Control Register

The FPGA Control Register is a 16-bit register at address 0xF8 and 0xF9
in both native and original mapping.

  ---------- -------- -------- -------- -------- -------- ------- ------- ------------ ------- ------- ------- ------- ------- ------- ------------
  **Bits**                                                                                                                             

  **15**     **14**   **13**   **12**   **11**   **10**   **9**   **8**   **7**        **6**   **5**   **4**   **3**   **2**   **1**   **0**

  NSKIP16                                                                 Decimation                                                   Use constant
                                                                          Offset                                                       
  ---------- -------- -------- -------- -------- -------- ------- ------- ------------ ------- ------- ------- ------- ------- ------- ------------

-   Bit 0 set means constants loaded at 0x48 to 0x4F (in native mapping)
    are used as input values for computing sliding sums and
    integrations. In normal operation using the real ADC input, bit 0 is
    clear.

-   Bits 1 to 7 specify an offset to the default decimation constant
    used in the noise filter. The default value of the decimation
    constant is 22336. Bit 7 specifies the sign of the offset
    (1=negative), and bits 1..6 specify a value which gets multiplied by
    32 to form the actual offset. So the final decimation constant is
    22336 + sign(bit\[7\]) \* bit\[6..1\] \* 32. See reference \[6\] for
    details about the noise filter.

-   Bits 8 to 15 represent a number NSKIP16 that is loaded by the user.
    The digitizer card ignores the first 16\*NSKIP16 measurements before
    starting summing and integration processes.

### Mode Select Registers

The Mode Select Registers are 16-bit words at 0x68 to 0x6F (in native
mapping). Each channel is controlled by its own Mode Select Register.
The bits of the registers are assigned as shown in the following table:

  ---------- -------- -------- -------- -------- -------- ------- --------- --------- ---------- ------- ------- ------------- ------- ---------- --------
  **Bits**                                                                                                                                        

  **15**     **14**   **13**   **12**   **11**   **10**   **9**   **8**     **7**     **6**      **5**   **4**   **3**         **2**   **1**      **0**

                                                                  Squelch   /INP_ON   MADC                       Use           Test    Enable     Enable
                                                                                      Function                   Integration   Mode On Long Time  High
                                                                                      Select                     Mode                  Constant   Range
                                                                                      \[2:0\]                                                     
  ---------- -------- -------- -------- -------- -------- ------- --------- --------- ---------- ------- ------- ------------- ------- ---------- --------

-   Bit 0 specifies whether to use low or high range which causes the
    integration capacitor for the integrator chips to be set to either
    100 pF or 500 pF; a difference of a factor of 5 in the least count
    and range for the data.

-   Bit 1 enables the long time constant for the integration circuit.
    The normal series resistance of the input to the integrator is about
    2 kΩ. When this control bit is set, an additional 15 kΩ resistor is
    included in series, increasing the effective time constant of the
    integrator.

-   Bit 2 enables test mode, whereby the on-board DAC is used to send a
    fixed current to the input of the integrator. The value of the DAC
    is set from the Test DAC register.

-   When bit 3 is turned on, the 32-bit very slow abort thresholds will
    be compared with bits 16 to 48 of the integration values. When this
    bit is clear, the integrations will still be accumulated, but they
    are not compared with the thresholds.

-   Bits 4 to 6 indicate what should be put on the analog outputs of
    the DC. The analog output for each channel can provide up to 8
    different signals derived from the raw data. These are specified in
    the firmware. The output choices are:

  ------------ ----------------------------------------------------------
  **3-bit      **Description**
  Value**      

  0            Value from MADC Manual Setting

  1            Raw measurement value

  2            Integrated current value (if enabled)

  3-7          Unused
  ------------ ----------------------------------------------------------

-   Bit 7 opens or closes the integrator input switch. A value of zero
    closes the input switch (normal operation), and a value of 1 opens
    it.

-   Bit 8 "Squelch" turns on the squelch operation for integration mode.
    Inputs lower than the sum of the pedestal plus squelch level are
    considered noise and are not accumulated into the integration. (See
    Section 2.11 for a description of the squelch level)

## Remote FPGA Programming

The two FPGA devices, Integ03 and Sums03 on the digitizer card are each
configured from an EEPROM device AT17LV002A at power up. The contents of
the EEPROM can be both read and rewritten from VME. Once the EEPROM is
successfully rewritten, the FPGA will be configured with new firmware at
the next power up.

Write access to the EEPROM signals is via a command register COM_REG at
N01000 and the read access is from a diagnostic register DIAG1 at
N0100A. Tables 10 and 11 list the relevant bits of the reprogramming
registers. The remaining bits are used for other purposes and should be
set to 0 when writing to COM_REG.

Table

10: Bit definitions for the COM_REG reprogramming register showing which
EEPROM pins are connected to which bits.

  ------------ ---------- --------- --------- -------- --------- -------- -------- ----------
  **COM_REG                                                                        
  (N01000)**                                                                       

  **Bit 15**   **14**     **13**    **12**    **11**   **10**    **9**    **8**    **7-0**

  Unused       DATA0_V1   DCLK_V1   SER_EN1   Unused   DATA0_V   DCLK_V   SER_EN   Reserved

               To Sums03                               To                          
               FPGA                                    Integ03                     
                                                       FPGA                        
  ------------ ---------- --------- --------- -------- --------- -------- -------- ----------

Table

11: Bit definitions for the DIAG1 reprogramming register.

  --------------------- -------------- -------------- --------------------
  **DIAG1 (N0100A)**                                  

  **Bit 15-6**          **5**          **4**          **3-0**

  Reserved              DATA0_in1      DATA0_in       Reserved

                        From Sums03    From Integ03   
                        FPGA           FPGA           
  --------------------- -------------- -------------- --------------------

The signals to the EEPROM pins are set by writing to the COM_REG
register. To set a signal high or low, write 1 or 0 to the given bit in
the COM_REG. A signal stays at the level after being written until next
time an opposite level is written. The level of DATA can be read from
DIAG1 register bit 4 and 5 as shown above.

Not that there is an inverter each for the SER_EN and SER_EN1 signals.
They are active high from program view while the inverted versions of
them presented at the device pins are active low. After power-up, these
register bits are 0, which disables access to the EEPROM devices. To
read or write an EEPROM, set SER_EN (or SER_EN1) to 1. The polarities of
the DATA0 and the DCLK signals are non-inverted.

Check the card for the following to ensure correct reconfiguration:

-   Jumpers J53, J54 and J66 must be installed for Integ03 FPGA
    reconfiguration.

-   Jumpers J51, J52 and J64 must be installed for Sums03 FPGA
    reconfiguration.

## Noise Filtering

Because of the EMF pickup encountered in the tunnels, the fast sums in
particular can display a rather large noise of up to 200 mR/s. To combat
this from a display perspective, an additional sum type was created that
consists of a sliding sum of a sliding sum where the sum length is
picked to be approximately 360 Hz. The double sliding sum, *a.k.a.*
Cascaded Integration Comb filter (CIC), provides better rejection of the
360 Hz multiples when the sampling frequency is not exactly aligned with
360 Hz. In particular, during acceleration, the sampling frequency,
which is the turn frequency, is changing by small amounts. In addition,
instead of just an average pedestal subtraction, the actual shape of the
noise (taken when there are no losses) is subtracted from the CIC sum.
This last step removes 60 Hz and multiples. This filtering process is
described in detail in \[6\].

## Integration Operation

The digitizer card computes sliding sums and integrations triggered by
the *Make_Meas* signal. In typical operation, the signal is generated by
the TC about every 21 μs. The integrations are 64-bit long integers
readable from the control bus at 8 bytes each.

The integration process begins after the sums are reset. The first set
of measurement points can be ignored and the number of points to be
ignored is defined by users. Then the pedestals of the 4 channels are
accumulated. The pedestals are stored once the accumulation is done. In
the integration mode, very slow sliding sum for each channel is used as
input data to the squelch checking and the integration accumulation.

After the pedestals become available, the very slow sliding sums are
used to compare with the pedestals plus the squelch levels to see if
valid data is present or not. If the very slow sum of a channel is
higher than the pedestal plus the squelch level, the pedestal is
subtracted from the very slow sum and the result is added to the
integration. A sufficiently large initial value is given to the
integrations which prevents the integrations from drifting negative when
the pedestals fluctuate too high.

In integration mode, bits 16-48 of the 64-bit integration value are
compared with the 32-bit very slow thresholds every 21 μs. The details
are described below.

## Sum Lengths

The lengths of the sliding sums are 16-bit integers. In addition to the
fast, slow and very slow sliding sums, the immediate measurement for
each channel is also implemented as a sliding sum with length = 1. All
these sums are implemented identically and their lengths can be
arbitrarily defined by the users.

The pedestal sum length at 0x7E is defined similarly. The length is used
to calculate the pedestals at the beginning of the run. In integration
mode, there must be a fixed ratio of 16 between the very slow sum
length, which is the input to the integration, and the pedestal sum
length. Typically, the very slow sum length is chosen to be about 47 and
the pedestal length to be about 752. Note that the users are allowed to
choose very slow sum length freely. For example, the very slow sum
length can be 55 and the pedestal sum length 880.

## Pedestals

All digitizer measurements are positive integers. In order to avoid bias
from negative noise signals, a fixed current is added to the input of
each integrator circuit. This presents a pedestal for each measurement.
As discussed in Section 2.4, a pedestal is subtracted in making the
integrated sum. However, for the raw measurement data or sliding sum
data, pedestals must be subtracted external to the digitizer. In order
to minimize the load on the control card, these subtractions are done by
the front-end CPU. Pedestals are taken at the beginning of a measurement
cycle, after *Reset_DC* is asserted. As mentioned earlier, the first
16\*NSKIP16 measurements are ignored before the pedestals are
calculated. The calculated pedestals are placed into the RAM block
interfacing with the control bus and can be read by the CC. The
pedestals can be changed by the users also, if necessary. But to avoid
being overwritten, they should only be changed after the accumulation of
the pedestals at the beginning of each run.

Abort thresholds for each channel are stored in the ACNet database and
correspond to actual losses. The front-end corrects the thresholds for
the pedestals before loading them to the Control Card. While care was
taken to minimize analog noise, some residual 60Hz and 720Hz noise
remains. Therefore, the length of the averaging period used to determine
the pedestal should be an integral multiple of 1/60 second. For the
Tevatron, this is 795 cycles; while for the main injector, it is 748
cycles at 8 GeV with *Make_Meas* running at half the AA marker
frequency.

Because the on-board pedestal must be an integer, it is possible to see
a slow drift in the integrated measurement with no losses. In the low
(high) range this is 14 mRad/s (70 mRad/s).

## Thresholds

Pre-loaded sets of thresholds are organized as pages and there are 64
pages total in a digitizer card. The users are allowed to select a
particular page to be used at any time. A clean way to change pages is
via a control bus broadcast.

## Saturation Protection

In order to be sensitive to extremely large losses, the Digitizer
protects the integrator from becoming saturated. During the integration
phase of the cycle, the output voltage is checked by a comparator. If it
reaches approximately 95% of full scale for the ADC, the input current
is shut off, and the remaining charge is stored on the cable. Thus for
large losses, the leading edge time is preserved; however, the raw
measurement will be near full scale until all charge from the loss has
been collected. Those measurements will be included as normal in the
sliding sums. In this way, by summing over measurements, it is possible
to record the full energy deposition.

## Calculations

This section presents the exact mathematical prescriptions for the
various quantities calculated by the DC. It also provides conversions
from physical values to digitizer values.

Table

12: Table of BLM quantities. Highlighted quantities are calculations
done by the DC. Other quantities are calculated by the front end or
other entitiy.

  ------------------------------------------------------------------------------------
  **Quantity**     **Registers**   **Description**
  ---------------- --------------- ---------------------------------------------------
  *N~S~*           F9              ( number of *Make_Meas* to skip before summing ) /
                                   16

  *L~PED~*         7E-7F           Pedestal sum length (must be 16 \* *L~VS~* for
                                   integration mode to work)

  *T*              \-\--           Type of sum (F=Fast, S=Slow, VS=Very Slow)

  *L~T~*           40-47           Sum length for type T

  *L~C~*           7C-7D           CIC length (used in the derippled sum)

  *X~i~*           \-\--           Raw data measurement (this quantity is only
                                   available in the original mapping)

  *S~i~^T^*        90-BF           Sliding sum

  *S~i~^D^*        80-8F           Derippled sum

  *S~j~^C^*        C0-DF*^†^*      CIC sliding sum which forms part of the derippled
                                   sum

  *P*              58-67           Pedestal

  *W~j-j0~*        C0-DF*^†^*      Baseline waveform for subtraction in derippled
                                   output

  *q*              \-\--           Squelch level in units of \# of sigma above noise
                                   RMS

  *σ*              \-\--           Raw data measurement RMS

  *Q*              50-57           Squelch level in units of 16 \* the very slow sum

  *Y~i~*           C0-DF           Integrated value on Digitizer Card (64 bits)

  *Z~i~*           \-\--           Integrated value in Control Card circular buffer

  *A~i~^T^*        \-\--           Average pedestal subtracted measurement using the
                                   specified sum in units of mR/s

  *A~i~^C^*        \-\--           Pedestal subtracted, derippled measurement in units
                                   of mR/s

  *I~i~*           \-\--           Real integrated value in units of mR

  *P~I~*           \-\--           Integration pedestal (only really needed if input
                                   switches are opened)

  *I~Thresh~*      30-3F           Abort threshold for integrations in ADC counts

  *A^T^~Thresh~*   00-2F           Abort threshold for sum type *T* in ADC counts

  *I~Lim~*         \-\--           Abort threshold for integrations in mR

  *A^T^~Lim~*      \-\--           Abort threshold for sum type *T* in mR/s
  ------------------------------------------------------------------------------------

*^†^ These registers normally contain the integrated values. The
baseline waveform and the CIC sum is available if bit 4 of the FF
register is set.*

The pedestal starts after a delay of (16\**N~S~*) *Make_Meas* cycles to
give the analog portion of the board time to settle

$$P = \sum_{i = \text{16}N_{S}}^{(\text{16}N_{S} + L_{\text{PED}} - 1)}X_{i}$$

The derippled baseline waveform is collected from data when there are no
losses

$$W_{j - j_{0}} = \sum_{k = (j - j_{0}) - L_{C} + 1}^{j - j_{0}}\left( \sum_{i = k - L_{C} + 1}^{k}X_{i} \right)$$

The sliding sum is the sum of the previous *L~T~* raw data measurements

$$S_{j}^{T} = \sum_{i = j - L_{T} + 1}^{j}X_{i}$$

The DeRippled sum, *S~j~^D^,* is a sum of sums

$$S_{j}^{C} = \sum_{k = j - L_{C} + 1}^{j}\left( \sum_{i = k - L_{C} + 1}^{k}X_{i} \right)$$

minus the baseline waveform plus the average pedestal

$$S_{j}^{D} = S_{j}^{C} - W_{j - j_{0}} + \overline{W}$$

The squelch level that must be downloaded to the digitizer is \~16 times
the very slow sum noise level times the number of sigma desired (it is
16\*17 rather than 16\*16 because of the contribution of the pedestal)

$$Q = q\sigma\sqrt{\text{16} \times \text{17} \times L_{\text{VS}}}$$

To determine the squelch level σ from a fast time plot of the fast sum,
look at the plot and determine the level, *R*, where you'd like to place
the squelch. Then use the following formula.

$$q\sigma = \frac{R\sqrt{L_{F}}}{\text{14}\text{.}2}$$

The integral starts accumulating after the delay and the pedestal
measurement and has the slow sum added every *Make_Meas* cycle. The
integral also has an offset of 128 Meg added to it to prevent negative
numbers on the digitizer. The *U( )* function is the unit step function
( *U(x) =* 0 if *x\<* 0 and = 1 if *x\>*0 )

$$Y_{k} = 2^{\text{27}} + \sum_{j = (\text{16}N_{S} + L_{\text{PED}})}^{k}{(\text{16}S_{j}^{\text{VS}} - P) \times U(}\text{16}S_{j}^{\text{VS}} - P - Q)$$

The integration value is stored in the digitizer as a 64-bit number. The
control card reads out bits 16-47 and puts that in the very slow sum
buffer.

$$Z_{k} = \frac{Y_{k}}{2^{\text{16}}}$$

In the front end, the sums must be turned into averages and have
pedestals subtracted and conversion factors applied. For the Fast, Slow,
and Very Slow,

$$A_{i}^{T} = \left\lbrack \frac{S_{i}^{T}}{L_{T}} - \frac{P}{L_{\text{PED}}} \right\rbrack \times \text{14}\text{.}2\ \text{mR/s}$$

whereas for the DeRippled,

$$A_{i}^{C} = \left\lbrack \frac{S_{i}^{C}}{L_{C}L_{C}} - \frac{P}{L_{\text{PED}}} \right\rbrack \times \text{14}\text{.}2\ \text{mR/s}$$

To obtain a true integrated value, the very slow sum buffer value must
have the 16 bit shift undone along with the factor of 16 and the over
counting by *L~VS~*. Then the value can be converted to mR. The
pedestal, *P~I~*, is either 2^27^/2^16^, or a measured value. A measured
value is needed if the input switch is opened during pedestals.

$$I_{i} = \frac{(Z_{i} - P_{I}) \times 2^{\text{16}}}{\text{16}L_{\text{VS}}} \times 0\text{.}\text{000313}\ \text{mR}$$

The abort thresholds are simply the inverse of the *A^T^* and *I*.

$$I_{\text{Thresh}} = \frac{I_{\text{Lim}} \times \text{16}L_{\text{VS}}}{2^{\text{16}} \times 0\text{.}\text{000313}\ \text{mR}} + P_{I}$$

$$A_{\text{Thresh}}^{T} = \left\lbrack \frac{A_{\text{Lim}}^{T}}{\text{14}\text{.}2\ \text{mR/s}} + \frac{P}{L_{\text{PED}}} \right\rbrack \times L_{T}$$

### Bit Alignment

As can be see above, divisions are not actually taken when the variables
are to be interpreted as averages such as pedestals and very slow
sliding sums. The values are scaled according the corresponding sum
lengths.

In the FPGA implementation the variables are aligned based on the
following picture:

![](media/image4.wmf){width="5.990972222222222in"
height="1.6104166666666666in"}

The pedestals and sliding sums are accumulated aligned with the raw
measurement data. The squelch level is added to the pedestal with bit 0
aligned. Therefore, it is possible set squelch level with fractional
part.

When the very slow sliding sums are operated with pedestals and squelch
levels, the sliding sums are shifted up for 4 bits equivalent to
multiplying by 16.

The integration is aligned with the pedestals. Therefore, dividing the
integration value by *L~PED~* scales it back to the raw measurement data
unit.

The thresholds are aligned to the bit 16 to 47 of the integration.

# Timing Card

The timing card (TC) is the primary controller for data collection in
the BLM system. It includes the following features:

-   Control Bus Interface for setting parameters

-   TCLK decoder\
    Used to receive encoded TCLK events. One of several actions can be
    taken upon receipt of a selected TCLK. TCLK events which are written
    to the FIFO cause IRQ0 to be asserted. A 1 MHz clock is derived from
    this clock. In locations without a TCLK, an optional 10 MHz
    oscillator is provided. The list of chosen TCLK events is downloaded
    through the control bus and stored in RAM.

-   BSCLK decoder\
    Used to receive the encoded Beam-Sync Clock events such as \$AA or
    TBT trigger events. As with the TCLK decoder, this one also features
    several actions that can be taken for each BSCLK event. The main use
    for this decoder is in receiving the AA marker which normally feeds
    the *Make_Meas* signal logic.

-   MDAT decoder\
    Used to receive machine state information from the MDAT system.
    Different machine states require different abort thresholds.
    Receiving an MDAT event causes IRQ1 to be asserted. The MDAT frames
    of interest are set in the firmware and are \$12 for the Tevatron
    and \$56 for the Main Injector. An MDAT event is defined as a change
    in the value of the relevant frame. Only the lowest 7 bits of the
    frame are considered. The upper bit is set to 1 if the frame was a
    MI frame and 0 if it was a TEV frame.

-   Real-time clock\
    The 32-bit Unix time in seconds is incremented by the TCLK 1 Hz
    event (\$8F). A 24-bit microseconds counter increments from each 1
    Hz event. These time values are used to mark the digitizer raw and
    sum data.

-   512 Kbytes of RAM for storing 64k of Raw Measurement Data Time
    Stamps. These are stored as 8 bits of state, 32 bits Unix time in
    seconds, and 24 bits of microseconds.

-   128 Kbytes of RAM for storing 2 sets of 8k worth of TBT time stamps.

-   A VME interface used for reading the Raw Data Time Stamps when the
    system is stopped and for reading TBT Time Stamps when TBT is not in
    operation.

-   *Make_Meas* backplane output\
    *Make_Meas* can be generated from either of two sources:

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-   The1 MHz clock with an 8-bit divisor

-   The AA marker from BSCLK or the AA marker / 2 for MI.

    The *Make_Meas* signal also latches the 64-bit time-stamp data and
    writes it into the time stamp RAM array and increments the RAM
    Pointer. The *Reset_DC* signal resets this pointer.

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```
-   Divisors of the *Make_Meas* signal used to make the *Fast_Latch,
    Slow_Latch*, and *Very_Slow_Latch* signals. The divisors are 16 bit
    numbers. These latch signals set a bit in a register and cause IRQ2
    to be asserted so that the CC knows to read the latched data from
    the digitizers. These three latch signals also latch the current
    time stamp into three registers so that the time stamp can also be
    read.

-   Writeable registers to force the creation of *Reset_DC, AIP, Clear
    AIP* etc

-   Front Panel lemo inputs which also make *Reset_DC, AIP,* and *Clear
    AIP*

-   Abort-in-Progress (*AIP*) signal\
    *AIP* being asserted causes the state machine to stop making all
    control pulses: *Make_Meas*, *xxxx_Latch*, etc., effectively
    freezing all buffers in the system. AIP is a latched signal cleared
    by *Clear_AIP* and by *Reset*.

-   ITBT Trigger\
    This line is driven onto the backplane in response to a TCLK
    Injection clock event, it causes the 8k Injection TBT buffer to be
    filled on the digitizer cards as well as the injection TBT time
    stamps to be filled on the TC.

-   STBT Trigger\
    This line is driven onto the backplane in response to a BSCLK
    Studies clock event, it causes the 8k Studies TBT buffer to be
    filled on the digitizer cards as well as the Studies TBT time stamps
    to be filled on the TC.

The control bus registers for the Timing Card are described in Table 13.
The Timing Card is controlled by signals on the control bus and by TCLK,
BSCLK, and MDAT events.

The reading of the Raw Measurement Time Stamp circular buffer is allowed
only when the state machine is stopped*, i.e. AIP* is true. The TBT time
stamp buffers can be read whenever a turn study is not in progress. The
VME address map is described in Section 3.1 below.

The TC also includes a VME to Control Bus Bridge to allow for setting up
the DC and TC hardware in situations where a CC module is not present.
VME Address line 20 set to 1 indicates that the Bridge is being
accessed. VME Address lines 1:13 are copied to Control Bus address lines
0:12 and control bus data lines 0:7 are connected to VME data lines 0:7.
The bridge must also use appropriate VME signals to create the following
Control Bus signals: *MEMRD\*, MREQ\*,* and *WE\*.* The TC will pull Bus
line *CPU_Detect* high. If this line is sensed low, the bridge will be
disabled since there is a CC present.

To set the seconds counter, one writes the time setting to the
appropriate registers and then sets the register to update the time
setting on the next \$8F TCLK event. The TC resets that register when
the time has been updated. When using a host CPU to set the time on the
Control Card, there is a similar feature whereby one sets the time to
use in the update and sets a register that the CC polls periodically to
see if there is an updated setting to pass to the TC.

## Address Maps

BLM Timing Cards respond to A32D16 and occupy 2Mb. Each card uses the
addresses NN000000-NN1FFFFE where NN is the base address. The base
address is set by switches on the board which determine bits 24-31. The
data are stored as follows as offset from the base address.

  --------------- -------------------------------------------------------
  **Address**     **Description**

  000000-000FFE   Standard ID Block (see Sec. 1.10)

  00A000          JTAG programming register

  00A002          JTAG enable register

  010000-01FFFE   64KB of TBT Data (8k Turns) Injection, linear buffer

  020000-02FFFE   64KB of TBT Data (8k Turns) Studies, linear buffer

  030000          Status Register

  080000-0FFFFE   512KB of TBT Data (64k Turns), Circular buffer

  100000-103FFE   VME to Control Bus Bridge
  --------------- -------------------------------------------------------

The following table shows the bit definitions for the status register at
30000.

  --------- -------- -------- -------- -------- -------- ------- ------- --------- ------- ------- ------- ------- ------- ------- -------
  **Bit**                                                                                                                          

  **15**    **14**   **13**   **12**   **11**   **10**   **9**   **8**   **7**     **6**   **5**   **4**   **3**   **2**   **1**   **0**

  1         1        0        0        1        0        1       1       Running                                           TBT     AIP
  --------- -------- -------- -------- -------- -------- ------- ------- --------- ------- ------- ------- ------- ------- ------- -------

The time stamp buffers are addressed as follows

-   A2:A1 = Time Stamp Words (0-3)

-   A18:A3 = Turns number

The structure of the time stamp data is:

  ---------- ------------------------------ ------------------------------
  **Word**   **Most Significant Byte**      **Least Significant Byte**

  0          Abort State                    Microseconds, byte 2

  1          Microseconds, byte 1           Microseconds, byte 0

  2          Unix Time, byte 3              Unix Time, byte 2

  3          Unix Time, byte 1              Unix Time, byte 0
  ---------- ------------------------------ ------------------------------

For the 64k turns of raw measurement time stamps, the index increments
from 0000 to FFFF and then wraps. This data can be read only when the
system is stopped (*i.e. AIP* is asserted). The timestamps for
turn-by-turn data may not be read during a turn study.

When using the control bus bridge VME A13:1 map to CA12:0 and A19:14 are
ignored. The 8-bit Control Bus data is on VME D7:0.

Table

13: Timing Card Control Bus registers.

+-------------------------------------+----------+--------+------+----+
| **Function**                        | **       | **Add  | *    | ** |
|                                     | Access** | ress** | *Byt | Bi |
|                                     |          |        | es** | ts |
|                                     |          | **(    |      | ** |
|                                     |          | Hex)** |      |    |
+-------------------------------------+----------+--------+------+----+
| **Setup**                           |          |        |      |    |
+-------------------------------------+----------+--------+------+----+
| CSR                                 | R/W      | 00     | 2    | 16 |
+-------------------------------------+----------+--------+------+----+
| Abort State                         | R/W      | 02     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| TBT Status (bit 4)                  | R        | 03     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| Seconds Time Clock setting          | W        | 04     | 4    | 32 |
+-------------------------------------+----------+--------+------+----+
| Set Clock on next (\$8F)            | W        | 08     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| Update Settings on next Make_Meas   | W        | 09     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| **Control**                         |          |        |      |    |
+-------------------------------------+----------+--------+------+----+
| Make_Meas Divisor                   | R/W      | 10     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| Fast Sum Length                     | R/W      | 12     | 2    | 16 |
+-------------------------------------+----------+--------+------+----+
| Slow Sum Length                     | R/W      | 14     | 2    | 16 |
+-------------------------------------+----------+--------+------+----+
| Very Slow Sum Length                | R/W      | 16     | 2    | 16 |
+-------------------------------------+----------+--------+------+----+
| Raw Data Time Stamp Pointer         | R        | 20     | 2    | 16 |
+-------------------------------------+----------+--------+------+----+
| TCLK Event FIFO                     | R/W      | 30     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| TCLK Event FIFO Status              | R/W      | 31     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| BSCLK Event FIFO                    | R/W      | 32     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| BSCLK Event FIFO Status             | R/W      | 33     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| MDAT Event FIFO                     | R        | 34     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| MDAT Event FIFO Status              | R/W      | 35     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| TCLK RAM Pointer                    | R/W      | 36     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| TCLK RAM Data                       | R/W      | 37     | 1    | 4  |
+-------------------------------------+----------+--------+------+----+
| BSCLK RAM Pointer                   | R/W      | 38     | 1    | 8  |
+-------------------------------------+----------+--------+------+----+
| BSCLK RAM Data                      | R/W      | 39     | 1    | 3  |
+-------------------------------------+----------+--------+------+----+
| **Clocks/Timing**                   |          |        |      |    |
+-------------------------------------+----------+--------+------+----+
| Fast Latch Time Stamp               | R        | 40     | 8    | 64 |
+-------------------------------------+----------+--------+------+----+
| Slow Latch Time Stamp               | R        | 48     | 8    | 64 |
+-------------------------------------+----------+--------+------+----+
| Very Slow Latch Time Stamp          | R        | 50     | 8    | 64 |
+-------------------------------------+----------+--------+------+----+
| **General**                         |          |        |      |    |
+-------------------------------------+----------+--------+------+----+
| Force Clear                         | W        | F0     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| Force Start (Reset DC)              | W        | Fl     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| Force Stop                          | W        | F2     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| Force ClkReset (\$8F)               | W        | F3     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| Force AIP                           | W        | F4     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| Force Sum Latches                   | W        | F5     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| Force ITBT Trigger                  | W        | F6     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| Force STBT Trigger                  | W        | F7     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| IRQ2 Status Reg Fast                | R/W=Clr  | F8     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| IRQ2 Status Reg Slow                | R/W=Clr  | F9     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| IRQ2 Status Reg Very Slow           | R/W=Clr  | FA     | 1    | 0  |
+-------------------------------------+----------+--------+------+----+
| **Diagnostics**                     |          |        |      |    |
+-------------------------------------+----------+--------+------+----+
| Board Temperature                   | R        | FE     | 2    | 16 |
+-------------------------------------+----------+--------+------+----+

## Control Bus Registers

### CSR

  ---------- -------- -------- -------- -------- ----------- -------- --------
  **Bits**                                                            

  **7**      **6**    **5**    **4**    **3**    **2**       **1**    **0**

                                                 Make_Meas            
                                                 source               
  ---------- -------- -------- -------- -------- ----------- -------- --------

-   Bits 0...2 specify the source of *Make_Meas*.

  ---------- ------------------------------------------------------------
  0          Use MI AA marker 2

  3          Use 1 MHz internal oscillator

  4          Use TEV AA marker
  ---------- ------------------------------------------------------------

### Make_Meas Divisor

This specifies the divisor to use if the 1 MHz internal oscillator is
selected in the CSR register.

### Event FIFO Status

  --------- --------------------- --------------------- ---------------------
  **Bit**   **TCLK**              **BSCLK**             **MDAT**

  0         FIFO Empty            FIFO Empty            FIFO Empty

  1         FIFO Full             FIFO Full             FIFO Full

  2                                                     

  3                                                     

  4                                                     MDAT decode error

  5                                                     

  6                                                     

  7                                                     
  --------- --------------------- --------------------- ---------------------

### Timestamps

  ----------- -----------------------------------------------------------
  **Byte**    **Description**

  0           Microseconds Low Byte

  1           Microseconds Middle Byte

  2           Microseconds High Byte

  3           State

  4           Seconds Low Byte

  5           Seconds Middle Byte

  6           Seconds More Middle Byte

  7           Seconds High Byte
  ----------- -----------------------------------------------------------

## Remote FPGA Programming

The FPGAs are normally programmed by connecting a cable called a
"ByteBlaster" between the parallel port of a computer and the JTAG
connector on the front panel of the card, and downloading the proper
programming file using Altera's Quartus program into the card's
configuration device. The configuration device holds the FPGA
programming bitstream in non-volatile memory, and programs the FPGAs
whenever the board is powered-up. An alternative method of loading the
configuration device exists using four bits of a VME register to emulate
the four bits of the JTAG lines. Table 14 shows the bit assignments.

Table

14: VME register NN00A000 for loading the configuration device.

  ---------------- ------------------------------------------------------
  **Bit**          **JTAG Function**

  0                TCK

  1                TMS

  6                TDI

  7                TDO
  ---------------- ------------------------------------------------------

This programming register is at NN00A000. As a precaution, in order for
this programming operation to occur, a special code must be written to
register NN00A002. Currently the only requirement in this special code
is that a 1 be written to bit 0. The idea is obviously to ensure that no
random or erroneous VME operations corrupt the FPGA configurations. The
software routines for carrying out the remote programming are part of
the front end code collection.

## Clock Decoders

### Introduction

The timing cards contain decoders for TCLK, BSCLK, and MDAT. Both TCLK
and BSCLK are programmable with respect to which clock events are acted
upon. It is the responsibility of the Control Card to load the TC with
the proper list of clock events to use. The MDAT decoder is hardwired in
firmware to listen to two MDAT frames, one for the TEV and one for the
MI.

### Tevatron Clock (TCLK) Decoder

The following is a list of Control Bus Addresses and functions involved
in setting up the TCLK Clock Event Decoder RAM. The RAM is 256 x 4 bits
where each 4 bit value is associated with clock event (entries 0-255)
and each bit specifies an action to be taken when that particular clock
event happens.

Table

15: Table of TCLK decoder associated registers.

+------+-----------------+--------------------+----------------------+
| **CB | **Description** | **Read**           | **Write**            |
| A    |                 |                    |                      |
| ddre |                 |                    |                      |
| ss** |                 |                    |                      |
+------+-----------------+--------------------+----------------------+
| nn30 | Event FIFO\     | Gets the next      | Clears the FIFO.     |
|      | 32 events deep\ | properly decoded   |                      |
|      | (each entry is  | TCLK event.        |                      |
|      | 8 bits)         |                    |                      |
+------+-----------------+--------------------+----------------------+
| nn31 | Event FIFO      | Gets the FIFO      | Disables decoding    |
|      | Status          | status.            | and enables writing  |
|      |                 |                    | to decoder RAM.      |
|      |                 | Disables writing   |                      |
|      |                 | to decoder RAM and |                      |
|      |                 | enables normal     |                      |
|      |                 | event decoding     |                      |
+------+-----------------+--------------------+----------------------+
| nn36 | Decoder RAM     | Gets the current   | Specifies the RAM    |
|      | Address Pointer | address pointer.   | address pointer.     |
|      |                 | The RAM is 256 x 4 |                      |
|      |                 | bits.              |                      |
+------+-----------------+--------------------+----------------------+
| nn37 | Decoder RAM     | Gets the 4 bits of | Writes the lower 4   |
|      | Data            | data at the        | bits to the current  |
|      |                 | current Address    | address pointer      |
|      |                 | Pointer location.  | location.            |
+------+-----------------+--------------------+----------------------+

The 4 bits of the RAM data are defined as follows:

  --------- ----------------------------------------------------------------
  **Bit**   **Description**

  0         A one in this bit location causes a 1Hz interrupt to occur.
            (Only used by the 8F Clock Event.)

  1         A one in this bit location causes an Injection TBT Trigger to
            occur.

  2         A one in this bit location causes a hardware Abort in Progress
            (AIP) to be generated.

  3         A one in this bit location causes the decoded TCLK event to be
            written into the FIFO.
  --------- ----------------------------------------------------------------

#### Loading the TCLK Clock Event Decoder RAM

The procedure to load the clock event decoder RAM for the TCLK decoder
is as follows:

1.  Execute a Control Bus write to the TCLK FIFO status address (nn31).
    This enables the Decoder RAM Address Pointer and allows data to be
    written into the RAM. It also disables normal TCLK Event Decoding.

2.  Write the value of the address you want to change within the Clock
    Event Decoder RAM to the Decoder RAM Address Pointer (nn36).

3.  Write the value of the data you want within the RAM to the Decoder
    RAM Data (nn37).

4.  Repeat steps 2 and 3 until the Decoder RAM is filled.

5.  Execute a Control Bus read from the FIFO status address (nn31). This
    will disable writing to the Decoder RAM, and enable normal TCLK
    Event Decoding.

#### Example setup for a couple of TCLK Clock Events

This example sets up the Tevatron Prepare for Beam Clock Event (\$71)
and the Tevatron 1Hz Clock Event (\$8F).

1.  Write any value to the TCLK event FIFO status address (nn31).

```{=html}
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```
6.  Write \$71 to the TCLK Event Decoder RAM Address Pointer (nn36).

7.  Write \$08 to the TCLK Clock Event Decoder RAM Data (nn37). This
    will cause the \$71 clock event to be loaded into the Event FIFO
    when decoded.

8.  Write \$8F to the TCLK Event Decoder RAM Address Pointer (nn36).

9.  Write \$01 to the TCLK Clock Event Decoder RAM Data (nn37). This
    will cause a hardware 1 Hz interrupt when the \$8F clock event is
    decoded.

10. Read from the TCLK Event FIFO status address (nn31).

### Beam Sync Clock (BSCLK) Decoder

The following is a list of Control Bus Addresses and functions involved
in setting up the BSCLK Clock Event Decoder RAM. The RAM is 256 x 3 bits
where each 3 bit value is associated with a clock event (entries 0-255)
and each bit specifies an action to be taken when that particular clock
event happens.

Table

16: Table of BSCLK decoder registers.

+------+-----------------+--------------------+----------------------+
| **CB | **Description** | **Read**           | **Write**            |
| A    |                 |                    |                      |
| ddre |                 |                    |                      |
| ss** |                 |                    |                      |
+------+-----------------+--------------------+----------------------+
| nn32 | Event FIFO\     | Gets the next      | Clears the FIFO.     |
|      | 32 events deep\ | properly decoded   |                      |
|      | (each entry is  | BSCLK event.       |                      |
|      | 8 bits)         |                    |                      |
+------+-----------------+--------------------+----------------------+
| nn33 | Event FIFO      | Gets the FIFO      | Disables decoding    |
|      | Status          | status.            | and enables writing  |
|      |                 |                    | to decoder RAM.      |
|      |                 | Disables writing   |                      |
|      |                 | to decoder RAM and |                      |
|      |                 | enables normal     |                      |
|      |                 | event decoding     |                      |
+------+-----------------+--------------------+----------------------+
| nn38 | Decoder RAM     | Gets the current   | Specifies the RAM    |
|      | Address Pointer | address pointer.   | address pointer.     |
|      |                 | The RAM is 256 x 3 |                      |
|      |                 | bits.              |                      |
+------+-----------------+--------------------+----------------------+
| nn39 | Decoder RAM     | Gets the 3 bits of | Writes the lower 3   |
|      | Data            | data at the        | bits to the current  |
|      |                 | current Address    | address pointer      |
|      |                 | Pointer location.  | location.            |
+------+-----------------+--------------------+----------------------+

The 3 bits of RAM data are defined as follows:

  --------- ----------------------------------------------------------------
  **Bit**   **Description**

  0         A one in this bit location causes an internal AA event to occur.
            (Used by the \$AA Clock Event.) An AA event feeds into the
            *Make_Meas* generating logic.

  1         A one in this bit location causes a Studies TBT Trigger to
            occur.

  2         A one in this bit location causes the decoded BSCLK event to be
            written into the FIFO.
  --------- ----------------------------------------------------------------

#### Loading the BSCLK Clock Event Decoder RAM

The procedure to load the clock event decoder RAM for the BSCLK decoder
is as follows:

1.  Execute a Control Bus write to the BSCLK event FIFO status address
    (nn33). This enables the BSCLK Event Decoder RAM address pointer and
    allows data to be written into the BSCLK Event Decoder RAM. It also
    disables normal BSCLK Event Decoding.

```{=html}
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11. Write the value of the address you want to change within the Clock
    Event Decoder RAM to the BSCLK Event Decoder RAM Address Pointer
    (nn38).

12. Write the value of the data you want within the RAM to the BSCLK
    Clock Event Decoder RAM Data (nn39).

13. Repeat steps 2 and 3 until the BSCLK Clock Event Decoder RAM is
    filled.

14. Execute a Control Bus read from the BSCLK Event FIFO status address
    (nn33). This will disable writing to the BSCLK Event Decoder RAM,
    and enable normal BSCLK Event Decoding.

#### Example setup for a couple of BSCLK Clock Events

This example sets up the Tevatron Data Acquisition Event (\$DA) and the
Tevatron Beam Rotation Marker (\$AA).

1.  Write any value to the BSCLK event FIFO status address (nn33).

```{=html}
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```
15. Write \$XX to the BSCLK Event Decoder RAM Address Pointer (nn38).

16. Write \$04 to the BSCLK Clock Event Decoder RAM Data (nn39).

17. Write \$AA to the BSCLK Event Decoder RAM Address Pointer (nn38).

18. Write \$01 to the BSCLK Clock Event Decoder RAM Data (nn39).

19. Read from the BSCLK Event FIFO status address (nn33).

### MDAT Decoder

The MDAT decoder decodes the MDAT stream listening for frames \$12 and
\$56. Frame \$12(\$56) is the TEV(MI) state frame and contains the
16-bit machine state for the Tevatron(MI). Currently, only states 1-63
are supported by the BLM system, so the MDAT decoder copies bits 0...6
of the state value into the MDAT queue and puts a 0(1) in bit 7 if the
machine is TEV(MI).

Table

17: MDAT queue registers.

  ----------- ------------------ --------------------- -----------------------
  **CB        **Description**    **Read**              **Write**
  Address**                                            

  nn34        Event FIFO\        Gets the next         Clears the FIFO.
              32 events deep\    properly decoded MDAT 
              (each entry is 8   frame.                
              bits)                                    

  nn35        Event FIFO Status  Gets the FIFO status. N/A
  ----------- ------------------ --------------------- -----------------------

# High Voltage Card

The High Voltage card is a double-wide 6U VME module that can carry one
to four high voltage modules that are independently controlled through
the VME bus. It has an 8-bit switch selectable card number which sets
the card address corresponding to VME address (A31:A24). A Quad 12-bit
DAC provides the program voltage for each of the high voltage modules
for voltage output control. The combination multiplexer and 16-bit ADC
reads the high voltage monitors for each module.

The card incorporates an FPGA (Altera Cyclone) to interface with the VME
bus and provide local timing and control. The FPGA receives all the VME
bus control, address, and data lines for reading/writing of data on the
card. The FPGA can be programmed from the front panel through the Active
Serial Program connector. The card has a serial number and ID memory to
identify individual cards (see Section 1.10).

The program voltage circuitry consists of a 12-bit four-channel DAC
device and an op-amp gain circuit. The DAC is controlled from the VME
bus through an FPGA to select and send data to the selected channel. The
DAC has an output range of 0 to 10V which feeds the control input of the
HV module and results in a HV output of 0 to 2250V. So a setting value
of 0  FFF corresponds to an output of 0  2250V.

To read all the high voltage monitors, the card uses a 16-to-1
multiplexer and 16-bit bipolar input digitizer. The circuit operates in
a circular mode, such that the digitizer is continually digitizing all
the monitor signals from each channel and storing the data into
registers. The registers then can be read at anytime through the VME
bus. The ADC has an input range of ±10V with an output of 0 to FFFF (0V
input 8000 output). The timing and control is done through the FPGA.
Voltage readings are scaled such that 1V ADC input corresponds to 1kV
and current readings are scaled such that 1V ADC input corresponds to
100μA.

## Address Maps

BLM HV cards respond to A32D16 and occupy \<1 kb. The base address of
the board is set by a dip switch which corresponds to A31:A24. The
address offsets for the registers on the board are given in Table 18.
The only data that can be written are the HV settings and the HV enable
words. Note that only the lowest 12 bits are significant in the HV
setting.

Table

18: VME address map of HV board.

  ------------ ------------ ----------- ---------- --------------------------------------
  **Offset**   **Access**   **Size**               **Description**

                            **Bytes**   **Bits**   

  000000       R            160         \-\--      Board ID

  000200       R            8           \-\--      Serial Number

  **Channel                                        
  1**                                              

  000250       R/W          2           12         Channel 1 HV Setting

  000252       R            2           16         Channel 1 Output Current

  000254       R            2           16         Channel 1 Output Voltage

  000256       R            2           16         Channel 1 Return Voltage

  **Channel                                        
  2**                                              

  000260       R/W          2           12         Channel 2 HV Setting

  000262       R            2           16         Channel 2 Output Current

  000264       R            2           16         Channel 2 Output Voltage

  000266       R            2           16         Channel 2 Return Voltage

  **Channel                                        
  3**                                              

  000270       R/W          2           12         Channel 3 HV Setting

  000272       R            2           16         Channel 3 Output Current

  000274       R            2           16         Channel 3 Output Voltage

  000276       R            2           16         Channel 3 Return Voltage

  **Channel                                        
  4**                                              

  000280       R/W          2           12         Channel 4 HV Setting

  000282       R            2           16         Channel 4 Output Current

  000284       R            2           16         Channel 4 Output Voltage

  000286       R            2           16         Channel 4 Return Voltage

  **Other                                          
  stuff**                                          

  000290       R/W          1           1          0/1 disables/enables channel 1 supply

  000292       R/W          1           1          0/1 disables/enables channel 2 supply

  000294       R/W          1           1          0/1 disables/enables channel 3 supply

  000296       R/W          1           1          0/1 disables/enables channel 4 supply
  ------------ ------------ ----------- ---------- --------------------------------------

## Positive High Voltage Module

The High Voltage module is a self-contain module with two SHV
connectors, one for high voltage output, the other for a high voltage
return. A third connector is used as an I/O for input power, program
voltage and high voltage monitoring. High voltage is produced by a dc to
high voltage converter that is controlled by a programmed voltage input.
The high voltage output is regulated and has low ripple output. The
module also has three high voltage monitors for voltage output, voltage
input return and current output monitoring. Shown below are the
specifications for the module.

-   DC to HV Converter: 0 to 3000V @ 500µA max. Emco model: G30

-   Voltage Output: 0 to +2.25kV

-   Maximum current output: 500µA

-   Output Ripple: \< 200mVp-p (full load) freq. @ 150KHz

-   Output Regulation: \< .1% @ full load

-   Program input voltage: 0 to +10V

-   Voltage & current inputs: +12V @ 220mA, -12V @ 5mA (full load)

-   Monitor outputs:

```{=html}
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-   HV current monitor: +1V/100uA

-   HV output monitor: +1V/1000V

-   HV return monitor: +1V/1000V

```{=html}
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```
-   Status monitor (on/off): ON = +3.3V, OFF = 0V

-   HV input and output connectors: SHV, Kings No. 1704-1

-   I/O connector: AMP 534237-8

-   Module size: L 5" x W 2" x H 1.125"

# **Abort Card**

The Abort Card (AC) is the primary controller for abort collection and
reporting. The BLM abort status will be sent to the existing abort
chassis in each service building. In addition, each card will be part of
a serial link which sends Tevatron abort information from house to house
to a dedicated collection board located at A0. A diagram of the abort
cards data flow is given in Figure 4. Functions and features of the
abort card are as follows:

-   Reads the Abort information from each Digitizer Card once per
    measurement cycle.

-   Applies channel mask and multiplicity requirements before requesting
    an abort.

-   Stores the abort information in a VME-readable circular buffer for
    65536 turns.

-   Periodically sends this abort information to the next house, forming
    a serial data stream of abort information. Each successive house
    appends its data to the data stream.

-   VME registers exist for reading the circular buffer, testing the
    memory, sending diagnostic signals, reading board ID information.

-   Control Bus for setting the mask and multiplicity values, and for
    reading the Channel OK bits that were latched while reading abort
    information from the DCs.

-   Abort bus for reading the abort bits from the Digitizer Cards.

-   Masks and Multiplicity numbers are double-buffered..

-   Front Panel Lemo outputs: Immediate Abort, Fast Abort, Slow Abort,
    Very Slow Abort.

-   Front Panel BNCs: Abort Out, Serial Link In, and Serial Link Out..

-   VME Test of Serial Link

-   VME interrupt capability to be specified.

-   Front panel displays and LEDs show the board status.

-   Remote FPGA programming capability using the VME bus

The Abort Card is master of the Abort Bus, which is used to gather abort
data for the crate. Upon receiving a *Make_Meas* signal, the Abort Card
sends addresses out on the AbortCS\[5..0\] and for each address sent it
receives one channel's worth of abort data on the Abort\[3..0\] lines.
These four bits correspond to the four "abort types" Immediate abort,
Fast Abort, Slow Abort, Very Slow Abort. If a bit is a "0" then the
channel has a digitized value greater than its threshold value (preset
in the Digitizer Card via the Control Bus). AbortCS\[5..3\] represent
the DC board address, and AbortCS\[1..0\] represent the four individual
channels per board. Upon receiving all the abort information, the Abort
Card counts the number of channel hits per abort type and compares the
value to a preset multiplicity value. If any value is greater than the
multiplicity threshold the AC sends an abort request to the Abort System
via a BNC connector on the front panel. Each of the four abort types
behaves independently in this manner, and four Lemo connectors exist on
the front panel in case individual pulse information is desired. The
abort outputs are active-low. Thus the TTL high output corresponds to a
beam permit.

Each digitizer channel in the crate can also be "masked" to prevent its
inclusion in an abort request. There are four masks per channel
corresponding to the four abort types.

-   Abort 0 Immediate Abort

-   Abort 1 Fast Abort

-   Abort 2 Slow Abort

-   Abort 3 Very Slow Abort.

A mask setting of "1" allows that channel to cause an abort.

The abort bus also includes a Channel OK line. This indicates that the
digitizer state machine is functioning properly. In case of an error,
the abort card keeps a mask of problem channels and can interrupt the
control card to generate an error associated with the problem. If a CHOK
is false, the channel is not used in the abort multiplicity calculation.

The register map for control bus data is given in Table 23.

![](media/image5.png){width="6.486111111111111in"
height="3.223611111111111in"}

Figure

4: Overview of Abort Card functions.

## Address Maps

BLM Abort Cards respond to A32D16 and occupy 4Mb. The address offset and
data for the Abort Card are as follows:

  ------------------------- ---------------------------------------------
  **Address**               **Description**

  000000-000FFE             8kB of Settings, ID etc.

  00A000                    JTAG FPGA programming register

  00A002                    JTAG enable register

  020000                    Interrupt Register

  030000                    Abort Status Register

  040000                    Memory Pointer LSBs

  040002                    Memory Pointer MSBs

  050000                    Memory Test Register

  050010                    Abort Control Register

  060000                    Serial Diagnostic Register

  060010                    Serial Link Test Register

  070000                    Position in Serial data stream (reserved)

  200000-3FFFFE             Abort History Circular Buffer (64k turns)
  ------------------------- ---------------------------------------------

The bits of the various settings and status registers are decoded
according to Table 19.

Table

19: Definition of bits for VME Registers.

+---+--------+---------------+--------------+--------------+-----------+
| * | **Int  | **Abort       | **Memory     | **Serial     | **Abort   |
| * | errupt | Status        | Test         | Link Test    | Control   |
| B | Regi   | Register**    | Register**   | Register**   | R         |
| i | ster** |               |              |              | egister** |
| t |        |               |              |              |           |
| * | (res   |               |              |              |           |
| * | erved) |               |              |              |           |
+---+--------+---------------+--------------+--------------+-----------+
| 0 | R/W    | AIP           | Memory Test  | Error Count  | Reset for |
|   |        |               | Mode (allows | Bit0         | VME and   |
|   |        |               | VME write    |              | CB        |
|   |        |               | cycles to    |              | Registers |
|   |        |               | Circular     |              |           |
|   |        |               | Buffer)      |              |           |
+---+--------+---------------+--------------+--------------+-----------+
| 1 | R/W    | Circular      | Zero         | Error Cnt    | Zero      |
|   |        | Buffer        |              | Bit1         |           |
|   |        | "Wrapped" bit |              |              |           |
+---+--------+---------------+--------------+--------------+-----------+
| 2 | R/W    | Immed. Abort  | Zero         | Error Cnt    | Zero      |
|   |        |               |              | Bit2         |           |
+---+--------+---------------+--------------+--------------+-----------+
| 3 | R/W    | Fast Abort    | Zero         | Error Cnt    | Zero      |
|   |        |               |              | Bit3         |           |
+---+--------+---------------+--------------+--------------+-----------+
| 4 | R/W    | Slow Abort    | Zero         | Error Cnt    | Serial    |
|   |        |               |              | Bit4         | Link      |
|   |        |               |              |              | Reset     |
+---+--------+---------------+--------------+--------------+-----------+
| 5 | R/W    | V. Slow Abort | Zero         | Error Cnt    | Zero      |
|   |        |               |              | Bit5         |           |
+---+--------+---------------+--------------+--------------+-----------+
| 6 | R/W    | Zero          | Zero         | Error Cnt    | Zero      |
|   |        |               |              | Bit6         |           |
+---+--------+---------------+--------------+--------------+-----------+
| 7 | R/W    | Running       | Zero         | Error Cnt    | Zero      |
|   |        |               |              | Bit7         |           |
+---+--------+---------------+--------------+--------------+-----------+
| 8 | N/A    | Reset Abort   | R            | Error Cnt    | N/A       |
|   |        | Status        |              | Bit8         |           |
+---+--------+---------------+--------------+--------------+-----------+
| 9 | N/A    | N/A           | N/A          | Error Cnt    | N/A       |
|   |        |               |              | Bit9         |           |
+---+--------+---------------+--------------+--------------+-----------+
| 1 | N/A    | N/A           | N/A          | Error Cnt    | N/A       |
| 0 |        |               |              | Bit10        |           |
+---+--------+---------------+--------------+--------------+-----------+
| 1 | N/A    | N/A           | N/A          | Error Cnt    | N/A       |
| 1 |        |               |              | Bit11        |           |
+---+--------+---------------+--------------+--------------+-----------+
| 1 | N/A    | N/A           | N/A          | Error Cnt    | N/A       |
| 2 |        |               |              | Bit12        |           |
+---+--------+---------------+--------------+--------------+-----------+
| 1 | N/A    | N/A           | N/A          | Error Cnt    | N/A       |
| 2 |        |               |              | Bit13        |           |
+---+--------+---------------+--------------+--------------+-----------+
| 1 | N/A    | N/A           | N/A          | Reset Err    | N/A       |
| 4 |        |               |              | Count        |           |
+---+--------+---------------+--------------+--------------+-----------+
| 1 | N/A    | N/A           | N/A          | Link Test    | N/A       |
| 5 |        |               |              | Mode         |           |
+---+--------+---------------+--------------+--------------+-----------+

The Abort History is a circular buffer parallel to those in the
Digitizer and Timing cards. Each data record frame is 32 bytes, and
corresponds to one turn. The first 28 bytes contain the unmasked abort
status for 56 of the 64 possible DC channels in a crate. A 16-bit status
word for four channels is structured as in Table 20.

Table

20: Definition of bits for each 16-bit word in the circular buffer.

  ------------------ --------------------- -------------------------------
  **Bit**            **Channel**           **Status**

  0                  0                     Immediate

  1                  0                     Fast

  2                  0                     Slow

  3                  0                     Very Slow

  4                  1                     Immediate

  5                  1                     Fast

  6                  1                     Slow

  7                  1                     Very Slow

  8                  2                     Immediate

  9                  2                     Fast

  10                 2                     Slow

  11                 2                     Very Slow

  12                 3                     Immediate

  13                 3                     Fast

  14                 3                     Slow

  15                 3                     Very Slow
  ------------------ --------------------- -------------------------------

The Abort History data record has the following structure; channels are
numbered commensurate with backplane lines AbortCS\[5..0\].

Table

21: VME address offset corresponding to DC channels.

  ------------------ ----------------------------------------------------
  **Offset**         **Function**

  0                  Status, Channels 0-3

  2                  Status, Channels 4-7

  4                  Status, Channels 8-11

  .......            ...................

  1A                 Status, Channels 52-55

  1C                 Summary word 1

  1E                 Summary word 2
  ------------------ ----------------------------------------------------

The two summary words of Table 21 contain the multiplicities of the
aborts after the mask and the abort bits that are output to the
beam-permit system:

Table

22: Last two words in each circular buffer frame (one frame per turn).

  ---------- ----------- -------------------------------------------------
  **Word**   **Bits**    **Function**

  1          0:3         Abort bits (VS, S, F, I)

  1          4:9         Fast Abort Multiplicity

  1          10:15       Immediate Abort Multiplicity

  2          0:3         4-bit counter incrementing on MM

  2          4:9         Very Slow Abort Multiplicity

  2          10:15       Slow Abort Multiplicity
  ---------- ----------- -------------------------------------------------

The Abort Status Register looks at the status the four abort bits as
seen on the front panel, except they are latched in this status register
to record if any bits had gone high and subsequently cleared. This was
intended as a tool for the Operators to keep track of aborts around the
ring. The reset Abort Status bit resets only the four abort bit
readbacks in this register.  Actually any write to this register will
perform the reset.   These bits do not affect the front panel outputs. 
The bits are also cleared by Sysreset, front panel reset, and bit D0 of
the Abort Control Register. Also in this register is "running" which is
the inverse of AIP, and the Circular buffer "wrapped" bit.  The Wrapped
bit is cleared by a front-panel reset or the backplane signal Reset DC.

Table

23: Control Bus register map for Abort Card.

  ---------------------------------- ----- ---------- ------------- ----------- ----------
  **Function**                             **Type**   **Address**   **Bytes**   **Bits**

  **Masks**                                                                     

  Abort Mask                               R/W        00            1           6

  Abort Channel Count                      R/W        01            1           6

  Abort Enable                       R/W              0A            1           1

  Immediate Abort Mask                     R/W        10            8           64

  Fast Abort Masks                         R/W        18            8           64

  Slow Abort Masks                         R/W        20            8           64

  Very Slow Abort Masks                    R/W        28            8           64

  **Multiplicities**                                                            

  Immediate Multiplicity                   R/W        40            1           6

  Fast Multiplicity                        R/W        41            1           6

  Slow Multiplicity                        R/W        42            1           6

  Very Slow Multiplicity                   R/W        43            1           6

  **General**                                                                   

  Force Abort H                            R/W        45            1           6

  Force Abort L                            R/W        A4            1           6

  Force Abort Permit                       R/W        A5            1           6

  **Diagnostic**                                                                

  ADC Reading Temperature                  R          4E            2           16

  Channel OK                               R          50            8           64

  Memory Pointer (Bits 11..04)             R          02            1           8

  Memory Pointer (Bits 19..12)             R          03            1           8

  Interrupt Register                       R          A6            1           7

  Abort Status Register                    R          A7            1           5

  Abort Snapshot Register                  R/W        60            32          256

  Abort OR Register                        R          80            32          256

  Snapshot Pointer (Bits 11..04)           R          04            1           8

  Snapshot Pointer (Bits 19..12)           R          05            1           8
  ---------------------------------- ----- ---------- ------------- ----------- ----------

Table

24: Control Bus register bits.

  --------- ------------------------- ------------------ ----------- -----------
  **Bit**   **Interrupt Register**    **Abort Enable**   **Abort     **Abort
                                                         Mask**      Status**

  0         Assert IRQ3 when an abort Abort Enable       Immediate   Immediate
            occurs before                                            
            multiplicity is applied                                  

  1         Assert IRQ3 when an abort Zero               Fast        Fast
            occurs                                                   

  2         Assert IRQ3 when any      Zero               Slow        Slow
            Channel "not OK"                                         

  3         Zero                      Zero               Very Slow   Very Slow

  4         Raw Abort Interrupt       Two consecutive                
                                      aborts                         

  5         Abort Interrupt           Reset channel OK   All         Logical OR
                                      list                           

  6         Ch not OK Interrupt       Reset Abort OR                 
                                      Register                       

  7         Clear IRQ3                Zero                           
  --------- ------------------------- ------------------ ----------- -----------

The Abort Snapshot register captures the last frame of the Abort History
circular buffer just prior to an abort. It will keep this frame until
anything is written to Control Bus register 60.

The Abort OR register keeps a running tab of which abort bits went over
threshold since the last reset. This reset is bit D6 of the Abort Enable
register or power-up or Reset CB. The Abort OR register does not
register the "sum words" that exist in the circular buffer.

## Remote FPGA Programming

The FPGAs are normally programmed by connecting a cable called a
"ByteBlaster" between the parallel port of a computer and the JTAG
connector on the front panel of the card, and downloading the proper
programming file using Altera's Quartus program into the card's
configuration device. The configuration device holds the FPGA
programming bitstream in non-volatile memory, and programs the FPGAs
whenever the board is powered-up. An alternative method of loading the
configuration device exists using four bits of a VME register to emulate
the four bits of the JTAG lines. Table 25 shows the bit assignments.

Table

25: VME register NN00A000 for loading the configuration device.

  ---------------- ------------------------------------------------------
  **Bit**          **JTAG Function**

  0                TCK

  1                TMS

  6                TDI

  7                TDO
  ---------------- ------------------------------------------------------

This programming register is at NN00A000. As a precaution, in order for
this programming operation to occur, a special code must be written to
register NN00A002. Currently the only requirement in this special code
is that a 1 be written to bit 0. The idea is obviously to ensure that no
random or erroneous VME operations corrupt the FPGA configurations. The
software routines for carrying out the remote programming are part of
the front end code collection.

## Reset Functions

A breakdown of the reset functions of the board follows:

-   **Front Panel Reset Button**: VME State Machine, VME Interrupt
    Register, Control Bus sequencing, CB Interrupt Register, Abort
    Outputs, Abort enable bit, Snapshot register, wrapped bit, circular
    buffer pointer, all Serial state machines and FIFOs, Serial error
    detector, remote programming special code.

-   **VME SysReset**: VME State Machine, VME Interrupt Register, Control
    Bus sequencing, CB Interrupt Register, Abort Outputs, Abort enable
    bit, Snapshot register, all Serial state machines and FIFOs, Serial
    error detector, remote programming special code.

-   **Abort Control Register Bit D0**: VME Interrupt Register,
    AbortStatusRegister, MemTest Register, JTAG programming registers,
    Control Bus sequencing, CB Interrupt Register, Abort Outputs, remote
    programming special code.

-   **Abort Control Register Bit D4:** All Serial state machines and
    FIFOs, Serial error detectors.

-   **Reset DC** (backplane): Wrapped bit, circular buffer pointer,
    Snapshot register.

-   **Reset CB** (backplane): Abort enable bit, Snapshot register.

# Abort Card at A0

A special Abort Card at A0 is used for initiating the Serial link data
stream and processing all the houses' data from the serial link once
they make it completely around the ring. All three FPGAs on this abort
card need special firmware. Although the data is serialized for
transmission on the buried coax between houses, the Serial Link FPGA on
each Abort Card treats the data a byte at a time.

Upon receipt of the signal "Abort Sync" from the Timing Card, A sixteen
byte "preamble" is sent out of the A0 card to the first house, A1. This
house checks for the correct preamble and puts its 32 bytes of data
immediately at the end of the preamble and sends out the data to A2.
Each subsequent house tacks its 32 bytes of data immediately onto the
end of the data from the upstream house until the whole ring's worth of
data arrives back at the A0 Abort Card. The A0 card largely ignores the
four sum bytes from each house, separates out the bits based on abort
type, adds up the bits and compares these four sums to serial-link
multiplicity values also based on abort type. If any are over threshold,
and also "enabled", an abort signal goes out the front panel. The
*Abort_Sync* occurs every 2 msec.

## Address Maps

The following table contains the VME registers for the A0 Abort Card.
There is no Control Bus access.

  ------------------------- ---------------------------------------------
  **Address**               **Description**

  060000                    Serial Link Data Buffer FIFO

  060020                    Upstream House Link Errors

  070000                    Link Errors

  A00000,A00002             Multiplicity Registers

  A00004                    Abort Enable Register
  ------------------------- ---------------------------------------------

## Abort Multiplicity Registers

There are four abort multiplicity settings, one for each abort type.

  ------------- ---------------------------- ------------------------------
  **Address**   **Bits**                     

                **15...8**                   **7...0**

  A00000        Fast multiplicity            Immediate multiplicity

  A00002        Very Slow multiplicity       Slow multiplicity
  ------------- ---------------------------- ------------------------------

## Abort Enable Register

The Abort Enable register (NNA00004) allows individual inclusion of each
abort type from around the ring to be included in the ringwide abort
signal.

  --------- -------------------------------------------------------------
  **Bit**   **Abort Enable**

  0         Immediate abort enable

  1         Fast abort enable

  2         Slow abort enable

  3         Very Slow abort enable

  4         Zero

  5         Zero

  6         Preamble Error Read and Reset Error

  7         Abort Read and Reset Abort
  --------- -------------------------------------------------------------

## A0 Serial Link Data Buffer

The A0 Serial Link Data Buffer (NN060000) is a FIFO memory that stores
the complete data set that makes it to A0 prior to the latest abort. The
data is comprised of all 32 bytes of circular buffer data from each
house, including sum words, for a total of 880 bytes (16 byte preamble +
27 houses x 32 bytes). Data order is the preamble from the A0 Abort
Card, A1 data, A2 data, and so on. To obtain this data, read NN060000 a
minimum of 880 times. As long as *Abort_Sync*s are occurring, this
buffer will accumulate data, writing over the previous ring's worth of
data with each *Abort_Sync*. When an abort occurs the buffer will
continue filling until it receives all the data from the last house in
the chain. Further writing is then prohibited. The buffer is re-armed
when bit 7 of the Abort Enable register is written high.

## A0 Serial Link Error Handling

The Serial Link Receiver on each Abort Card checks for valid 8B/10B data
arriving at the input. If an invalid code is detected an error bit is
generated. This error bit is placed on bit D3 of the last of the four
sum bytes in the serial data (it does not affect the counter in the
circular buffer described above). This bit is the exception; the rest of
the bits in the four sum bytes from each card are ignored by the A0
Abort Card.

If this bit is set from any of the ACs in the ring, it is assumed that
the data for the present sample prior to this point is wrong and the
serial link multiplicity counters are reset, preventing an abort. Error
free transmission after this point in the turn may still abort if there
are enough bits set. Upon receiving the next Abort Sync pulse from the
TC, the algorithm starts anew. A register at NN070000 is available for
reading the number of errors detected around the ring. A fourteen bit
number counts the errors between resets to the register. The number
resides in bits D13-D0, and the reset is bit D14. To date, no errors
have been detected on the link.

A similar register which monitors only the errors from the upstream
house resides at 14060020. It is also has a fourteen bit counter and is
reset by bit D14.

# Control Card

The Control Card (CC) is the primary controller for the Tevatron BLM
system. It includes the following features:

-   eZ80 microprocessor running the main control program

-   1 MB flash memory for storing code

-   2 MB RAM for running the control program

-   Control Bus Interface Master for setting parameters and reading back
    sliding sums, etc.

-   8 Megabyte Block of shared memory with the VME bus. This is used for
    getting setup parameters and for storing the circular buffers and
    other frame memories.

-   Two RS-232 ports for diagnostics and standalone operation

-   [A TCP/IP 10/100 baseT port for standalone operation (not
    implemented)]{.mark}

The Control Card functions by running a control program \[7\] on the
eZ80 that

-   initializes the other cards,

-   responds to TCLK events

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```
-   prepare for beam and end of beam events which start and stop the DAQ

-   Flash, profile and display frame events

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```
-   reads the sums from the digitizers,

-   responds to MDAT state changes by changing abort thresholds and
    masks,

-   responds to requests from the front end crate controller

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```
-   changes to abort thresholds and masks

-   changes to other settings

The program is stored in the 1 MB flash memory and can be reprogrammed
remotely. At boot time, the program is copied to the 2 MB RAM where it
then runs. The program is kept in the Controls Department's CVS
repository on **nova.fnal.gov** under project **blmez80**.

## Address Maps

The control card address space is a 24-bit address space, enough to
address 16MB of memory. The eZ80 is allowed to access the entire space
while the VMEbus is allowed to access a subset of it. The memory space
of the control card is shown in the following table.

  ------------------------------------------------------------------------------
  **eZ80          **VMEbus      **Contents**                          **Size**
  address**       address**                                           
  --------------- ------------- ------------------------------------- ----------
  000000-0FFFFF                 Flash                                 1MB

  200000-3FFFFF                 eZ80 Program RAM                      2MB

  400000-401FFF                 Control Bus                           8KB

  500000-507FFF                 Internet Chip W3100A (not             32KB
                                implemented)                          

  610000          NN610000      FPGA reconfiguration signal: DCLK     

  620000          NN620000      FPGA reconfiguration signal: DATA     

  630000          NN630000      FPGA reconfiguration signal: SER_ENn  

  700000-7000EF   NN700000-     ID block, utility RAM                 240B

  7000F2-\        NN7000F2-     Temperature                           2B
  7000F3                                                              

  7000F8-7000FF   NN7000F8-     Silicon ID: family code, ID, check    8B
                                sum                                   

  700100-7001EF   NN700100-     Utility RAM                           240B

  800000-FFFFFF   NN800000-     Shared RAM                            8MB
  ------------------------------------------------------------------------------

The VMEbus uses A32D16 mode. The higher 8 bits of the address, "NN", are
set by a DIP switch on the control card \[1\]. Note that the byte
alignment is reversed from VMEbus standard. The byte written to the even
address by the eZ80 is the lower byte in the 16-bit VMEbus data. The
VMEbus can only access memory space from NN610000 to NNFFFFFE. The
control card firmware does not guard on invalid accesses. Attempts of
accessing memory addresses not listed in the table will have effects not
documented here. Users are advised to access only the listed space. The
lower addresses are only accessible by the eZ80.

### The 8MB Shared Memory Space

On the control card, 8MB of RAM are designed to be accessible from both
VME and eZ80 sides. The access is time shared using sequential circuits.
In practical program writing, the users are allowed to access the memory
"simultaneously" from both VME and eZ80 sides. However, it is a common
practice to use a handshaking protocol so that a block of data is
readout by one process only after the other process has finished writing
valid data into the block. The shared memory begins at NN800000.
Addresses described below are added to this address. Table 26 lists the
main blocks of memory in the 8MB of shared memory on the Control Card.
For the details of every address, see \[7\].

Table

26: Map of the shared memory on the Control Card. This table enumerates
blocks of addresses and not individual address details. For that
information see \[7\].

  -------------------------------------------------------------------------------
  **Address**   **Size**   **Description**
  ------------- ---------- ------------------------------------------------------
  000000        2          eZ80 Program Status Word

  000002        30         Various front end triggers and settings

  000020        32         Indices and pointers to the various data storage
                           buffers

  000050        34         Temperatures

  000080        8          Channel Not OK List from Abort Card

  000100        512        Various settings (not all addresses are used)

  000300        256        32-bit pedestals stored in standard data record

  000400        120        16-bit squelch values

  000500        74         Abort Snapshot Info

  000600        256        32-bit Integration pedestals

  010000        48         Program name, version, and build date

  010030        \~64K      Debug information

  020000        128K       Buffer for new flash memory contents

  080000        128K       256 Flash Frames

  0A0000        128K       256 Profile Frames

  0C0000        512        Display Frame

  0E0000        256        MDAT state to Abort state map

  0E0100        512        TEV F Sector - MI TCLK Info

  0F0000        64K        TEV F Sector Info

  100000        256 K      Abort Settings for Abort States 0-255. Each state is
                           1K of data. The front end writes new settings to this
                           block.

  140000        256 K      Copy of settings that are in use. The eZ80 program
                           copies the data from the previous block to this block.
                           These are the settings that are copied to the AC and
                           DCs.

  180000        512 K      DeRippled Sum Buffer 2K frames deep

  200000        4 Meg      Fast Sum Buffer 16K frames deep

  600000        1 Meg      Slow Sum Buffer 4K frames deep

  700000        1 Meg      Very Slow Sum Buffer 4K frames deep
  -------------------------------------------------------------------------------

### The ID Block and Utility RAM

The address ranges NN700000-NN7000EF and NN700100-NN7001EF is
implemented with a small memory block. (In fact, it is the same memory
block that supports the temperature and silicon ID) This memory contains
the ID block.

Users are allowed to read and write into this small memory block;
therefore it is also called utility RAM. However, care must be taken
while writing from eZ80 side. The utility RAM is organized as 16-bit
words that are can be read or written in a single operation from VME.
From eZ80, the even and odd bytes can be readout separately. However,
while writing from the eZ80, either to the even or odd byte, both bytes
in the 16-bit word are written with the same number. For example, if a
byte XY is written into 700000 or 700001 the 16-bit word becomes XYXY.

The utility RAM can be used as handshaking information exchange
resource. It is important that a data item being exchanged is written in
a single operation. The inconvenience while writing from eZ80 side
described above was primarily for simplicity of the implementation.
However, it also prevents the users from mistakenly sending 2-byte
information that needs two operations from eZ80 to VME for handshaking.

## Remote Programming

### FPGA

The FPGA on the control card is configured from an EEPROM device
AT17LV002A at each power up. The contents of the EEPROM can be read and
rewritten from both eZ80 and VME sides. Once the EEPROM is successfully
rewritten, the FPGA will be configured with new firmware at next power
up.

There are three signals used to control reading and writing information
into the EEPROM:

-   The DCLK signal at NN610000

-   The DATA signal at NN620000

-   The SER_ENn signal at NN630000

These signals are single bit registers. To set a signal high or low,
write 1 or 0 to the given address from the eZ80. From VME, write FFFF to
set the signal high and 0 to set it low. A signal stays at the level
after being written until it is overwritten with the opposite level. The
level of DATA can be read. Bit 0 of the byte at 620000 or word at
NN620000 represents the level of signal DATA.

Check the card for the following to ensure correct reconfiguration:

-   BP112 must be present.

-   Jumper J5, J6 and J7 must be installed.

### eZ80

The eZ80 program must be running to reprogram it remotely since VME does
not have access to the Flash memory. The general approach is to write
the new code to a section of dual-port memory and then trigger the eZ80
program to copy it to flash memory. See \[7\] for details about
reprogramming the eZ80.

## Data Structures

BLM data is reported in two different ways: Snapshots and Profiles. A
profile is taken in response to a TCLK event. Profile data are the most
recent data from the specified sum (Fast or Slow) from each BLM channel.
The "Flash" and "Display" frames are the same as a Profile, but are
taken in response to a different TCLK event. It is possible to store up
to 256 Flash frames and 256 Profile frames in the CC for later readout
and analysis. There is only one Display Frame. The current frame indexes
are stored in registers. The Snapshot buffers contain the history of
losses for all channels for data from each of the sliding sums. These
data are stored in the circular buffers of the Control Card and can be
read by the front-end CPU from the CC's dual-port memory and then
reported to ACNET. Snapshot data is stored in circular buffers in the
same format as the Profile data. In addition to the sliding sum data,
Profile/Flash/Display frames include the integrated loss since the last
reset for the Main Injector and the very slow sum for the Tevatron. Thus
these data records are 512 bytes long, while the Snapshot (circular
buffer) records are only 256 bytes long. Table 27 enumerates the
contents of a 256 byte data frame.

Table

27: Contents of a 256 byte data frame. Profile/Flash/Display frames
contain 2 of these frames. The Timestamps are stored in Little-Endian
format.

  ------------- ------------ -----------------------------------------------
  **Byte        **Length**   **Description**
  Offset**                   

  00            1            Machine state (0-255)

  01            1            Measurement Divisor

  02            2            Sum Divisor

  04            1            Instantaneous Abort Status from AC

  05            1            Channel Count

  06            1            Data flag to indicate normal (0), last of cycle
                             (1), new cycle (2), or waiting for stable data
                             (3) frame

  07            1            Unused

  08            4            Time stamp: Microseconds since last TCLK 1 Hz
                             Event

  0C            4            Time stamp: seconds since T0 (*i.e.* 1 January
                             1970)

  10 + n\*4     240          Sliding Sum data for channel *n*
  ------------- ------------ -----------------------------------------------

## Abort Settings

The abort settings for the system are downloaded into the CC memory by
the front end. In addition to the thresholds and the masks, there is
also an array which maps MDAT state to abort state. The thresholds,
masks, and the map are all entered by the user through a console
application. There is currently support for states 1...63. This When a
new MDAT state appears, the map is used to determine which abort state
to switch to and the CC

# Revision History

  --------- ----------- ------- ------------------------------------------
  1.00.0    10/14/04    AB      First Posting in Doc DB.

  1.00.1    10/19/04    AB      Improved Figures for JDL.

  1.00.2    10/26/04    AB      Modified address map to have maximum of 60
                                Channels.

  1.00.3    11/2/04     AB      Modified Address map card IDs etc. and
                                updated J2 Connector pin list to include
                                standard VME in B row.

  1.00.4    11/2/04     AB      Fixed errors in Modified Address map for
                                Card Ids etc.

  1.00.5    4/14/05     JL      Major formatting overhaul. Clean up
                                address maps. Add introduction.

  1.00.6    6/6/05      JL      Modified CC map to include integral
                                measurements. Added info on HV and Abort
                                Cards. Minor cleanups.

  1.01.0    6/10/05     JL      CC map fixed. Ready for prime time. (FLW)

  1.01.1    7/25/05     JL      Cleanups. Update AC description

  2.00.0    4/5/07      RMTK    Semi-major overhaul to reflect all the
                                changes that occurred during production
                                and integration.
  --------- ----------- ------- ------------------------------------------

# References

1.  **BEAMS-DOC-2360**, "VME Base Address Switch Settings for the BLM
    System".

2.  **BEAMS-DOC-1126**, "Tests of BLM Integrator".

3.  **BEAMS-DOC-1736**, "BLM VME J2 Backplane Crosstalk Evaluation".

4.  **BEAMS-DOC-1994**, "BLM VME J2 Backplane Impedance".

5.  **BEAMS-DOC-2000**, "BLM System Control Bus Testing".

6.  "Digitizer Card Operating Guides".
    <http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/DCopGuide.doc>.

7.  **BEAMS-DOC-2433**, "BLM Upgrade Control Card Program Design".

[^1]: The dual porting is implemented in the on-board FPGA as a
    time-sliced sharing between VME and the eZ80.