D0 Note 3988

May 2002

# **Phase-5 Tests and Studies of the** 

# **Run IIa Analog Front End Board**

Pushpa Bhat, Alan Bross, Kirsten Goldmann,

Rick Jesik, Yi Jiang, Mike Matulik,

Hugh Montgomery and Andriy Zatserklyaniy

# **Abstract**

Each of the 198 Analog Front End Boards that instrument the Central
Fiber Tracker and the Pre-shower Detectors were thoroughly tested in the
Phase-5 test stand and certified prior to commissioning in the Run IIa
D0 detector. We describe those tests and discuss the online and offline
analysis of the data taken on the test stand. We present a variety of
results on the SVX gains, discriminator turn on and gains and pedestal
behavior. We also discuss the board certification issues for
commissioning and show distributions that provide a global perspective
of the system.

## 

## 

## **Contents**

1.  Introduction

2.  Phase-5 Test Goals

3.  Phase-5 Test Stand and Data Acquisition

4.  Phase-5 Tests

5.  Test Stand Data and Analysis

    1.  VREF Scan

    2.  Online Tests

    3.  Pedestals

    4.  SVX Response and SVX Gain

    5.  Discriminator Threshold Scans

        1.  Discriminator Turn-On and SIFT Gains

        2.  Turn-On Width

    6.  Zero Suppression Threshold Studies

        1.  Pedestals from Phase-5 Tests

        2.  Pedestals from Platform Tests

6.  Board Certification Issues

    1.  Definition of a Bad Channel

    2.  Criteria for Grading AFE Boards

7.  Summary

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1.  **Introduction**

The Analog Front End (AFE) Boards instrument three Scintillation Fiber
detectors, the Central Fiber Tracker (CFT), the Central Pre-Shower (CPS)
and the Forward Pre-Shower (FPS), in the D0 detector. They receive
charge signals from the fibers via the Visible Light Photon Counters
(VLPCs) and provide (1) digital output for trigger and (2) analog
signals with charge amplitude information. The AFE board also provides
VLPC bias and temperature control functionalities.

There are three color-coded versions of the AFE board, which differ from
each other in input gain and VLPC control circuitry. The details are as
follows:

-   CFT boards -- green -- 136 needed (76 for axial layers/trigger)

-   CPS/CFT boards -- blue -- 30 needed (10 for axial layers/trigger)

-   FPS boards -- red -- 32 needed (all needed for trigger)

Between the three versions of the AFE boards, they instrument 77,000
channels in the CFT, 7,680 channels in the CPS and 14,000 channels in
the FPS.

The AFE boards also have a handedness. There are Left-handed (LH) and
Right-handed (RH) boards because of the way the boards are installed in
a VLPC cassette. Each AFE board has eight Multi-Chip-Modules (MCMs) and
a total of 64 channels each of analog and digital outputs. Each MCM has
1 Silicon Vertex (SVX-IIe) charger sensitive ADC (64 banded channels out
of a total of 128) and 4 SIFT (Scintillating Fiber Trigger)
discriminator chips (64 total channels- 2 SIFTs with 14 channels and 2
with 18 channels). A photograph of an RH AFE board is shown in Fig.1,
with important components labeled. For detailed design specification see
Ref. 1. Other notable sub-systems apart from the eight MCMs are:

-   1553 Control & Communication systems

-   A "virtual SVX" (VSVX) system to buffer discriminator data for
    readout with SVX data

-   A high-speed data multiplexing system which routes all discriminator
    data from the SIFT chips via LVDS links to Digital Front End (DFE)
    boards.

-   Analog monitoring for the VLPC temperature and bias (bias & cryo
    control)

-   DAC system to develop all control voltages for SIFTs

-   A clock generation system to generate all timing clock pulses for
    the SIFTs

All major logic functions are provided using Complex Programmable Logic
Devices (CPLDs). Embedded software in the on-board microprocessor is
used to respond to commands from the external world that appear on the
1553 bus.

![](media/image1.jpeg){width="5.665354330708661in"
height="5.004330708661417in"}

**Fig.1:** A photograph of a Right-handed AFE Board

2.  **Phase-5 Test Goals**

The phase-5 test of the AFE involves an attempt to verify all functional
aspects of every AFE board and to evaluate it for installation in the
detector on the platform. The primary goals of the phase-5 testing are:

1.  Re-testing the basic functionalities of the devices (communication
    interfaces, microcontroller, SVX and SIFTs),

2.  Studying the response of all 512 channels of the AFE to injection of
    charge,

3.  To test the ability of the AFE to operate the bias voltage and
    cryogenic temperature control systems, and

4.  The verification of the transfer of discriminator information to the
    level-1 trigger system.

If the test results are satisfactory (see description in Sec. 6), the
board is ready for installation. If not, repairs are made and the board
is re-tested and re-evaluated.

3.  **Phase-5 Test Stand and Data Acquisition**

To accomplish two of the primary goals of Phase V testing, an Analog
Front End Test Module (AFETM) was designed and built. An AFETM is
connected to the AFE by means of 8 VLPC 64 channel flexible cables
(V64), just as the AFE would be connected to the Visible Light Photon
Counters (VLPC) when installed in the Cryostat located under the D0
detector. Circuitry located on the AFETM is capable of injecting
variable and programmable amounts of charge into the conductors located
on the V64 cables and then onto the AFE. Also located on the AFETM is
circuitry used to emulate the response of the cryogenic temperature
monitoring resistors that are located under the VLPCs and circuitry that
can verify the operation of both the cryogenic temperature and bias
voltage control circuits on the AFE.

These aspects of the Phase V testing of the AFE are incorporated into
Visual Basic (VB) code (running under Excel) that controls the hardware
used to generate the test stimuli and read the AFE and AFETM for the
results. The test hardware (except for the AFETM) resides in a VME crate
located in the rack that holds the AFE backplane structure. The
computer, which runs the VB code, communicates with the VME crate via a
Bit3 card and cable system. Within the VME crate is the 1553 Controller
that sends instructions to and reads some test results back from the AFE
and the AFETM. Also within the VME crate is the Stand Alone Sequencer
(SASEQ) that is used to read Level 3 data from the AFE. To test the
response of channels on the AFE, the VB code sends 1553 commands to the
VME crate through the Bit3 system. The 1553 controller interprets the
commands and sends (or receives as necessary) appropriately coded 1553
compliant communication to either the AFE or the AFETM, to; set various
Digital to Analog Converters (DACs), configure patterns of channels to
inject charge to, set or clear various digital signal levels, etc. The
VB code then instructs the SASEQ (again using the Bit3 system) to
initiate a data transfer cycle, then reads the resulting AFE digitized
charge information and discriminator output information back from the
SASEQ. Typically, many events are taken for a given set up. For each
channel on the AFE, the mean of the digitized charge value and the
occupancy of the discriminated output is computed and compared to
limits. If the AFE is capable of performing the base level operations
and the channel response falls within limits, more extensive
characterization tests are run and analyzed off-line.

To accomplish the third goal of Phase V testing, a module used to verify
the design of the Digital Front End (DFE) module is used to read and
verify the Level 1 Trigger information from the AFE. The Data Pump
module can accept a stream of Low Voltage Differential Signal (LVDS)
from the AFE and make it available to the personnel computer running the
test. The AFE forms LVDS data streams from the discriminator output data
from the MCMs and would send the data to the DFE in normal running mode.
Code installed in some of the Complex Programmable Logic Devices (CPLD)
on the AFE can generate known patterns of diagnostic discriminator data
to the LVDS drivers when instructed to do so.

The LVDS portion of the Phase 5 test is run using different VB code. The
same path to the VME crate is utilized, but as noted above, the data
comes from the Data Pump module instead of the SASEQ. The data format is
sufficiently different and the LVDS test code was written late enough
that no effort was made to integrate both tests into a common package.

4.  **Phase-5 Tests**

> The tests conducted on the AFE boards during phase-5 fall into three
> categories:

1.  Retesting some of the basic functionalities of the AFE board even
    though they were looked at in earlier phases of testing:

-   The AFE can respond to the 1553 communication system

-   The microcontroller is working

-   The chain of SVX chips are functional and respond to commands

-   The discriminators are functional

2.  Testing the response of all 512 channels of the AFE to charge
    injection:

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1.  Establish the operating voltage V~ref~ (V~ref~ scan)

2.  SVX response for different amounts of charge injected ⇒ SVX gain

3.  Discriminator threshold scans with different amounts of charge
    injected

4.  SIFT gain ⇒ Discriminator turn-on curve

5.  Pulse channels in different patterns and readout

6.  Pedestals (means and sigmas) for all channels

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3.  Testing the ability of the AFE to operate the bias voltage and
    cryogenic temperature control.

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5.  **Test Stand Data and Analysis**

Channel level testing of the AFE Module at the Phase V test Stand is
carried out in two sections, the VREF sweep and the On-line analysis,
followed by a section that generates data for off-line analysis. The
goal of the VREF sweep section is to determine the correct voltage to
apply to each SIFT as an operating parameter. The On-line test and
analysis procedure injects charge into AFE analog input channels in an
attempt to determine to what extent all channels are responding but not
to the detail attempted in the off-line testing.

The AFE Test Module (AFE TM) is designed to allow the injection of a
variable amount of charge into the analog input channels of the AFE. The
same flexible printed circuits used to connect the AFE to the Visible
Light Photon Counters in the Fiber Tracker Cryostat are used to connect
the AFE to the AFE TM in the test stand. The design of the AFE TM allows
the injection of charge into as few as 8 non-adjacent (but common to a
single Multi-Chip Module (MCM)) channels at a time.

The AFE test stand code operates in a series of steps. The code
processes each step by first reading an array of stored test parameter
values, writing these values to appropriate registers and
Digital-to-Analog Converters (DACs) on both the AFE and the AFE TM to
set up a given step in the test. The system is then triggered and data
(both discriminator and digitized) is read out from the AFE for a number
of events for each step. The data read from the AFE is stored by channel
into three arrays after discriminator occupancy, SVX mean and SVX
standard deviation calculations are computed. The VREF scan operates
under this arrangement changing the VREF DAC values in steps. The other
On-line tests as well as those associated with the generation of data
for the Off-line test use the constant values for the VREF DACs as
determined from the VREF scan, but vary other parameters depending on
what is to be tested.

1.  **V~ref~ Scan**

The VREF input to the SIFT is used to match the quiescent SIFT output
capacitor voltage to the SVX input offset voltage. Differences in these
voltages are seen as charge by the SVX and can be either positive or
negative depending on the sign of the difference. Note that this charge
is due to the operation of the SIFT chip and not due to charge injected
into a SIFT input channel. For very small values of the VREF input
voltage, the difference between the SIFT and SVX is large and negative
(the capacitor output voltage is less than the SVX channel input
voltage). The effective negative charge transferred to the SVX is
sufficient to saturate the SVX. At the maximum voltage of the VREF
input, the difference is large and positive. The effective positive
charge transferred to the SVX is also sufficient to saturate the SVX.
The mean value of all saturated bonded SVX channels is a constant value,
dependent on the initialization values downloaded to the SVX chip. As
the voltage of the VREF input is increased, the SVX channels start to
come out of saturation and respond to the small negative charge with
mean values of less than the saturated value. As the VREF input voltage
continues to increase, the effective negative charge applied to the SVX
input decreases and the mean value of the SVX channels falls to zero. At
some VREF input voltage, the SIFT output capacitor voltage and the SVX
input voltages are equal. Increasing the VREF voltage past this point
results in the effective transfer of positive charge into the SVX. At
some greater VREF voltage, the amount of positive charge injected into
the SVX results in the channel mean to start to rise from zero. The mean
values of the SVX channels increase linearly with increasing VREF input
voltage (stored as a DAC value by the code) until the SVX approaches
saturation and the mean drops to the constant saturation value.

In the VREF sweep, the DACs that drive the VREF input to each of the 32
SIFT chips located inside the MCMs located on the AFE, are swept in 1
count steps through a portion of their range such that the lower and
upper saturation ranges of the SVX channels can be observed. For each
step of the VREF sweep, the AFE is triggered 20 times and the mean value
for each of the 512 channels on the AFE is calculated and stored in an
array. After all 58 steps that comprise the VREF sweep are completed,
the Visual Basic code that runs the AFE testing computes best VREF value
for each SIFT. Component variations do not allow the establishment of a
single global value for this voltage.

Each channel responds slightly differently to the VREF sweep. With one
VREF input to each SIFT, and a single SIFT controlling 18 channels, the
code attempts to determine the best VREF DAC value for each SIFT. This
is accomplished first on an individual channel basis, then by grouping
the results by SIFT and selecting the average value calculated from all
channels associated with a given SIFT. If channel responses are widely
divergent, the code may determine that a VREF value is not calculable
and generate an error. The method the code uses to determine the VREF
DAC value is to look for the VREF DAC value at which the SVX channel
mean first exceeds the saturation value by a fixed amount. In practice,
this offset (10 counts used in our tests) would be chosen in an attempt
to equalize the bonded channels at a common pedestal value and to allow
the differentiation of bonded from unbonded or unused channels. Once the
VREF DAC value for each SIFT had been determined, it is stored in an
array for future reference.

![](media/image2.png){width="5.024305555555555in"
height="5.115277777777778in"}

**Fig.3: V~ref~ Scan:** Plots of mean SVX response for each SVX channel
in each SIFT (one plot/SIFT) of an MCM for AFE Board 560480, as a
function of the applied reference voltage.

2.  **Other Online Tests**

In the On-line analysis procedure, the test stand code instructs the AFE
TM to inject charge into all 512 channels on the AFE in 8 steps,
applying the same charge to the same 8 channels in each of the 8 MCMs on
each step. For each of these steps, the test stand code stores
discriminator and SVX data for 500 events.

With the VREF DAC values as determined in the VREF sweep loaded into the
parameter array, the amplitude of the digitized signal found for
channels into which charge has been injected is expected to be
relatively constant across all SIFT channels. The amount of charge
injected into each channel (implemented in the parameter array as the
value written to a DAC on the AFE TM) was empirically selected to result
in something less than full-scale response from the SVX for the
initialization values downloaded to the SVX. The mean value obtained for
each of the 1024 SVX channels on the AFE is compared to limits to gauge
the response of the channel. Since not all channels are subjected to
charge injection on each of the 8 steps, the test stand code considers
channels to be of one of four types for each step. There are 56 channels
on each SVX that are not connected to any input, these are considered to
be Unbonded channels. There are 8 channels on each MCM that are fully
instrumented but not connected to an analog input channel on the AFE,
these are Unused channels. The remaining 512 SVX channels are fully
instrumented on the MCMs and connected to analog input channels on the
AFE. Only 64 are capable of receiving charge from the AFE TM at a time
for a given step, these are considered Pulsed channels. The channels not
receiving charge for a given step are Unpulsed channels. For each step
in the On-line test section, all SVX channels are subjected to different
limits depending on what kind of channels they are. Channels with mean
values outside the established limits are flagged as failed.

At the same time that channels are subjected to injected charge for
determination of their mean SVX values, the discriminator function of
each of the channels is also being tested. There are 512 discriminated
outputs from the MCMs on the AFE. They are divided into pulsed and
unpulsed categories for each step depending on which ones are receiving
the charge from the AFE TM. For the evaluation of the discriminator
channels on the AFE, the test stand code computes the fraction of the
number of times a discriminator channel was found to be ON (charge found
to be in excess of threshold) by the number of events in a given step.
Correctly responding discriminator channels should have occupancy of no
less than 1 when they are being pulsed and no more than 0 when they
aren't. Circuitry on the AFE exists to apply an effective threshold
voltage to the SIFT chips for use in the charge discrimination
operation. These threshold voltages can be changed by writing to DACs
located on the AFE. The values to be written to the threshold DACs are
stored in the parameter array for each test step. The particular values
to be written to the threshold DACs (setting the charge threshold level
for discriminator operation) were chosen empirically based on the amount
of charge injected for the SVX channel testing.

3.  **Pedestals**

The pedestals were read out multiple times (\~100-300) and the pedestal
mean and sigma for each channel is stored in the data files for offline
analysis. The pedestal means and sigmas for a typical board are shown in
Fig.4. The distributions of the same are shown in Fig.5. The pedestal
sigma was required to be within 7 ADC counts (or 1 p.e.) in the LG mode
for the channel to be tagged as a good channel. We have performed some
zero suppression studies using the pedestal data both from phase-5 test
data and some data taken on the platform. These are discussed in section
5.6.

![](media/image3.png){width="5.5in" height="6.501388888888889in"}

**Fig.4:** Pedestal means and sigmas for each of the 512 channels for
AFE board 560480 (Date: ) Note: Later modifications to the AFE board
yield much smaller variations in pedestals. See Fig X.XX.

![](media/image4.png){width="5.5in" height="6.501388888888889in"}

**Fig.5:** Distributions of pedestal means and sigmas for AFE board
560480.

4.  **SVX Response and SVX Gain Studies**

During the tests, pre-determined amounts of charges (Q=20, 30, 40, 50
QDAC units, 1QDAC unit ≈ 4.5 fC) are injected into each of the SVX
channels and the response read out. This was done both in the "Low Gain"
(LG) and "High Gain" (HG) modes. For each channel, then, we perform a
linear fit (using MINUIT in PAW) to the SVX response as a function of
the input charge to determine the SVX gain for that channel. Fig.6 (a)
and (b) show such a linear fit for one of the channels in low gain and
high gain modes, respectively. The gains and offsets from the fits for
all used channels are shown in Figs.7,9. The distributions of gains and
offsets are shown in Figs.8,10. The average SVX gain for the AFE board
560575 in low-gain mode is 4.766 ADC counts/QDAC unit and in high gain
mode is 9.95. (One photoelectron, 1 p.e., corresponds to about 7 counts
in the LG mode and about 15 counts in the HG mode). The ratio of SVX
gain in HG mode to LG mode is \~ 2.1 for the board 560575. The
distribution of gain for all installed boards are discussed later.

![](media/image5.png){width="2.975in"
height="3.861111111111111in"}![](media/image6.png){width="2.9833333333333334in"
height="3.861111111111111in"}

a.  **(b)**

**Fig.6:** SVX response in ADC units as a function of injected charge
(in QDAC units) for channel number 1014 in Low Gain mode (Top) and High
Gain mode (Bottom).

![](media/image7.png){width="5.5in" height="6.501388888888889in"}

**Fig.7:** Results of linear fits to SVX response vs. charge for all 512
used channels in Low Gain mode. (Top) Fitted SVX Gain, (Bottom) Fitted
offset.

![](media/image8.png){width="5.5in" height="6.622222222222222in"}

**Fig.8:** Distributions of Fitted SVX gains and offsets displayed in
Fig.7.

![](media/image9.png){width="5.5in" height="6.55625in"}

**Fig.9:** Same as Fig.7. in High Gain mode.

![](media/image10.png){width="5.5in" height="6.501388888888889in"}

**Fig.10:** Distributions of fitted SVX gains and offsets in High Gain
mode.

Any channel that has its SVX gain less than 75% of the nominal (average
gain for the board) is tagged as a bad channel.

5.  **Discriminator Threshold Scans**

The test stand data also includes threshold voltage scans with different
set amounts of charges injected (Q=0, 20, 35, 50). For each amount of
charge injected (and in case of no charge injection), the threshold
voltage is varied and the digital output from the specific channels are
read out. The output averaged over X events are plotted as the occupancy
as a function of threshold voltage. These provide turn-on curves for
each channel and are shown in Figs.11 and 12 (1 plot/SIFT) for an MCM
for the cases Q=0 and Q=50 DAC units. (The turn-on value for each
channel is taken to be the threshold voltage corresponding to 50%
occupancy at a given charge.) We determine the turn-on width for each
channel as the voltage difference between those corresponding to 10%
occupancy and 90% occupancy.

![](media/image11.png){width="5.5in" height="5.973611111111111in"}

**Fig.11:** Plots of average occupancy as a function of threshold
voltage for each channel in a SIFT for MCM=3 and AFE Board 560480 in the
absence of charge injection. Most of the channels have overlapping
discriminator turn-on.

![](media/image12.png){width="5.5in" height="5.753472222222222in"}

**Fig.12:** Same as Fig.10, but in the presence of injected charge Q=50
DAC units

1.  **Discriminator Turn-On and SIFT Gains**

The mid-point (50% average occupancy) of the turn-on curve for each
injected charge Q is taken as the threshold voltage value (V~th~). A
linear fit is performed to this V~th~ as a function of Q to obtain the
SIFT gain; the V~th~ values for the three Q values which are shown in
Fig.13 for an AFE board. The discriminator/SIFT gains and offsets for
all the channels are shown in insert from 560480.ps. The average SIFT
gain for this board is --4.34. The distributions for gain and offsets
are shown in Fig.14.

![](media/image13.png){width="5.372222222222222in"
height="6.413194444444445in"}

**Fig.13:** The threshold voltages (calculated as V~th~ at 50% average
occupancy) for each channel at Q = 20, 35 and 50 QDAC units for AFE
board 560480.

**Fig.14:** (a) SIFT gains and offsets for all channels using data from
Fig.13

Again, as in the case of SVX gain, any channel that has gain less than
75% in magnitude of the average SIFT gain for the board is tagged as a
bad channel.

2.  **Turn-On Width**

For each channel, using the threshold voltage scan data (see Figs.11 and
12), we determine the discriminator turn-on width as the difference in
V~th~ for average occupancies of 10% and 90%. They are typically 3-6 DAC
counts.

6.  **Zero Suppression Threshold Studies**

    1.  **Pedestals from Phase-5 Tests**

We studied the zero suppression threshold issues for 50 AFE-boards as
part of the Phase-5 analysis. The initial goal of this test was to find
zero suppression thresholds for every SIFT/MCM allowing for certain
occupancy and to determine the number of bad channels a board has for a
chosen threshold. The number of bad channels would then be included in
the total number of bad channels reported for the board, to be used to
classify the board. Eventually, however, there were problems in
determining and setting of appropriate V~ref~ voltages for different
SIFT chips and also the idea that the behavior of the pedestals on the
platform could be quite different than in Phase-5. So, we decided that
it is not useful to include the bad channels from the phase-5 zero
suppression study in the total bad channel count for board
certification. We, however, describe the study with phase-5 data here.

1.  **Finding the Threshold**

For each SIFT, the SVXmean (mean pedestal) values are used to define a
rough zero suppression threshold. Since there are 4 SIFTs in each MCM
and 8 MCMs on an AFE board each board gets 32 different thresholds.

In Fig.15 the SVXmean values for MCM number 1 for board 560606 are
shown.

![](media/image14.png){width="3.9993055555555554in"
height="3.997916666666667in"} **Fig.15:** SVXmean values for MCM1,
AFE-board 560606

In the first iteration of the study a zero suppression threshold for
each MCM was considered but because of the wide spread in SVXmean values
the number of bad channels was too high. Therefore, subsequently, a
threshold for each SIFT was considered. Fig.16 shows the data for MCM 1
for each of the four SIFTs separately.

![](media/image15.png){width="6.924305555555556in"
height="6.738888888888889in"} **Fig.16:** SVXmean values for each SIFT
of MCM1, AFE-board 560606

2.  **Strategy**

To find a proper threshold the following strategy is used. First one
determines the maximum pedestal mean for each SIFT, i.e. one looks for
the last filled bin. To have a sensitivity for two photoelectrons, 14
ADC counts (because the tests were done in LG mode) are subtracted from
this maximum and channels which have SVXmean entries below that are
identified and labeled as bad channels. If there are any bad channels
found, a new zero suppression threshold was applied. To this purpose the
last filled bin below the first threshold is taken as a new threshold
(that is the channel with mean below the highest). Then 14 ADC counts
are subtracted again and bad channels below this value are looked for.
If there are any we look for a third threshold and if necessary for a
fourth threshold as well. The search for bad channels is applied for all
thresholds in the same way as described above.

As an illustration of this procedure Fig.17 shows the SVXmean
distribution for SIFT 1 of MCM2 and board 560568. The last filled bin
and consequently the maximum pedestal has the SVXmean of 35.86. After
subtraction of 14 ADC counts 5 bad channels are found for the given
threshold (left of the arrow). If we apply the zero suppression
threshold at the second maximum there are no bad channels left because
of the big gap between the last but one and the last filled bin.

![](media/image16.png){width="4.267361111111111in"
height="4.152777777777778in"}

**Fig.17:** SVXmean distribution for SIFT1 of MCM2 of board 560568

For boards that have a big number of bad channels the SVXmean values are
clustered in some regions resulting in a lot of gaps dispersed over the
whole SVXmean distribution.

3.  **Results**

36 boards out of 50 had pedestal widths below 14 counts for all SIFTs so
they had 0 bad channels with zero occupancy above the threshold. 14
boards out of 50 had bad channels by applying the threshold below the
maximum pedestal. By applying the threshold below the second maximum
only 10 boards with bad channels are left. It is possible to reduce this
number to 7 boards if the threshold is set below the third maximum.
Table 1 shows it is not possible to reduce this number again by applying
a new threshold. Table 1 summarizes the number of bad channels for these
14 boards.

![](media/image17.wmf)

**Table.1:** Number of bad channels as a function of number of channels
above threshold.

![](media/image18.png){width="5.996527777777778in"
height="5.836111111111111in"} **Fig.18:** Number of channels above
threshold.

2.  **Pedestals from Platform Tests**

We also analyzed pedestal data recorded for 10 AFE boards on the
platform. These 10 boards have board-numbers:

560464, 560453, 560519, 560498, 560525, 560558, 560561, 560542, 560562,

560489

The distribution of pedestals (calculated in p.e. units and mean
subtracted) for channels in each SVX of the board 560464 are displayed
in Fig.19. In Fig.20(top), the pedestals of all channels from all 10
boards are shown. Fig.20(bottom) shows the distribution of the RMS of
the pedestal reading for each channel in all 10 boards. Since the
platform data was taken in the High Gain mode, we assume 1 photoelectron
(p.e.) = 15 ADC counts.

We then calculate probability for pedestal above a given cut. The
probabilities for each SVX of one board are shown in Fig.21 and for all
10 boards are shown in Fig.22. If we request 3% occupancy, for example,
the cut will be over 2 Pe. In Fig.23 we use mean of each SVX as the zero
point to calculate the probability of the pedestals over given cut of
all 10 boards and the cut will be 1.2 Pe for 3% occupancy. In Fig.24, we
use mean of each SIFT as the zero point to calculate the probability of
the hits over given cut of all 10 boards and the cut will be 1.0 Pe for
3% occupancy.

So, the best sensitivity to signal can be achieved by setting the zero
suppression threshold separately for each SIFT (as anticipated). In
principle the V~ref~ on these boards are set to bring pedestal means of
all the 4 SIFTs within a small range.

6.  **Board Certification Issues**

    1.  **Definition of a Bad Channel**

A channel is defined as bad using the following criteria:

1\. **SVX and SIFT gain:** A channel is flagged as bad if its SVX or
SIFT gain is \< 75% of the nominal gain SVX or SIFT gain, respectively.
Nominal gain is taken as average gain for the board.

2\. **SVX pedestal sigmas:** A channel is flagged as bad if its SVX
pedestal sigma is \> 1 pe (7 ADC counts).

3\. **Discriminator turn-on:** A channel is flagged as bad if the
turn-on defined as the width in DAC counts for 0 to 90% occupancy is
greater than 2 pe (14 DAC counts assuming SVX and SIFT gain are about
equal)

4\. **SVX zero suppression:** A SIFT is flagged as bad if the pedestal
mean distribution for the 14 or 18 channels in the SIFT has a full width
greater than 2 pe (14 ADC counts). The bad channels are those channels
whose pedestal mean is more than 14 ADC counts below the maximum
pedestal mean.

Even though, we performed some simple and crude studies of zero
suppression as explained in section 5.6, we did not use the fourth
criterion (the zero suppression criteria) for grading and selecting
boards for commissioning. More careful and sophisticated studies of
pedestals, their variations and occupancies are needed,
post-installation, to establish appropriate zero-suppression thresholds
and to tag bad channels.

2.  **Criteria for Grading AFE Boards**

For commissioning the AFE boards, they were graded based on the number
of bad channels that were found in the offline analysis of the phase-5
data and a few other loose parsing criteria. The boards were rejected if
the V~ref~ scans shoed a spread wider than 1p.e. for channels belonging
to a SIFT.

The classifications were then performed as follows:

Class Criteria

A N~bad~ \<8 channels, Pass LVDS, Bias tests

B N~bad~ \<20 channels, Not A.

C N~bad~ \<64 channels

7.  **Summary**

In summary, we would like to show the results of the offline analysis of
the data from recent test data. Figs. 25 through 35 show various results
and typical distribution of pedestals, SVX and SIFT gains, offsets,
turn0on widths, etc. The results for a CFT/CPS board which instruments
CFT channels with outer 4 MCMs and CPS channels with inner 4 MCMs.

To get a global perspective of all the AFE boards, we show plots of
interesting quantities for all boards using latest test data for each
board. First of all, we show the distributions of bad channels for all
boards in Fig.36. The installed boards have bad channels\<20 and mainly
fall into the category of A or B class boards. Quite a bit of repair
work was done to replace/repair SIFTs and/or MCMs to reduce the number
of bad channels.

The pedestal mean and pedestal sigma distributions are shown in Fig.37.
The distributions of all SVX gains and SIFT gains are shown in Figs.38
and 39

![](media/image19.png){width="5.621527777777778in"
height="4.156944444444444in"}

**Fig.19:** Pedestal distributions in p.e. units (mean-subtracted) for
channels in each MCM for board 560464.

![](media/image20.png){width="5.500694444444444in"
height="3.876388888888889in"}

**Fig.20: (Top)** Pedestals of all channels for 10 boards listed in
section 5.6.2.

**(Bottom)** RMS of pedestals for all channels for the 10 boards.

![](media/image21.png){width="5.753472222222222in"
height="4.020833333333333in"}

![](media/image22.png){width="5.566666666666666in"
height="4.029166666666667in"}

**Fig.21:** Probability for pedestals above a given threshold for each
SVX in a board. Separate curves are shown for each SIFT.

![](media/image23.png){width="5.6875in" height="4.156944444444444in"}

**Fig.22:** Probability for pedestals above cut containing all boards.

![](media/image24.png){width="5.809027777777778in"
height="4.088888888888889in"}

**Fig.23:** Probability as in Fig.22 but calculated after subtracting
each SVX mean.

![](media/image25.png){width="5.809027777777778in"
height="4.250694444444444in"}

**Fig.24:** Same as Fig.23 but calculated after subtracting SIFT mean.

![](media/image26.png){width="5.993055555555555in"
height="6.622222222222222in"}

**Fig.25:** Results from fits to SVX gain for a CFT/CPS board. The inner
four MCMs are used for CPS and have gains smaller by approximately a
factor of 2.

![](media/image27.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.26:** Threshold voltage values (at 50% occupancy) for CFT channels
at Q = 20, 35, 50 QDAC units (Ignore inner MCMs)

![](media/image28.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.27:** Same as Fig.26 for CPS channels (ignore outer MCMs)

![](media/image29.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.28:** SIFT gains and offsets obtained from linear fits to data
from Figs.26 and 27 for CFT and CPS channels respectively.

![](media/image30.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.29:** Distribution of SVX fit gains and offsets.

![](media/image31.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.30:** Distributions of SIFT fit gains and offsets.

![](media/image32.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.31:** Pedestal means and sigmas for all channels for board 560650.

![](media/image33.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.32:** Distributions of pedestals and pedestal errors for board
560650.

![](media/image34.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.33:** Discriminator turn-on width in DAC units for all active
channels in AFE560650.

![](media/image35.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.34:** Distributions of turn-on widths shown in Fig.33.

![](media/image36.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.35:** Ratio of SVX gain to SIFT gain for all channels displayed as
a function of channel number.

![](media/image37.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.36:** Distribution of Number of bad channels for all AFE boards.

![](media/image38.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.37:** Distribution of pedestals for all AFE boards.

![](media/image39.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.38:** (TOP) Distribution of the SVX gain for all AFE boards.
(BOTTOM) Plots show the SVX gain distributions for the CPS/FPS and the
CFT boards.

![](media/image40.png){width="5.993055555555555in"
height="7.7555555555555555in"}

**Fig.39:** (TOP) Distribution of the SIFT gain for all AFE boards.
(BOTTOM) Plots show the SIFT gain distributions for the CPS/FPS and the
CFT boards.