# SUBCONTRACT TITLE: *ADVANCED PROCESSING OF CdTe- AND CuIn~X~Ga~1-x~Se~2~- BASED SOLAR CELLS*

# 

# SUBCONTRACT NO: NDJ-2-30630-18

# REPORT FOR: Phase II/Quarter 2

# 

# SUBMITTED TO: Ken Zweibel

#  National Renewable Energy Laboratory

# PRINCIPAL INVESTIGATORS: C. S. Ferekides and D. L. Morel

# University of South Florida

# Department of Electrical Engineering

# 4202 East Fowler Avenue

# Tampa, FL 33620

# 

# 

This is the progress report for the 2^nd^ quarter of Phase II for the
months of April through July 2003. The project covers two thin film
technologies: CdTe and CIGS. The focus areas include: (a) CdTe --
stability, novel back/front contacts, and the development of
manufacturing friendly processes; (b) CIGS -- development of two-step
non-co-evaporation technology.

A. CdTe

Stability

*Cu Effects*

As described previously the stability work is now focused on correlating
the amount of Cu in the back contact with device stability. Devices with
varying amounts of copper in the back contact and heat treated at
various temperatures have been prepared. Approximately 40 cells were
selected for light soaking and they have been mounted in the vacuum
oven. At this time only devices with certain performance characteristics
have been included: V~OC~ 730-830 mV and FF 0.60 to 0.74. The automated
apparatus for data collection (dark and light J-V) has also been
completed and it will be used for the first time for this set of
devices. The most recently updated data cover the first 130 hours of
light soaking[^1]. The V~OC~ and FF for several devices are shown in
Fig.1 (top - 10 Å of Cu/heat treated at 240°C; middle - 10 Å of Cu/heat
treated at 200°C; bottom - 5 Å of Cu/heat treated at 170°C). For each
set of processing conditions four cells are being light soaked: 2 held
at open-circuit (OC) and 2 @ short-circuit (SC). All performance data
are taken at operating temperatures which are typically 35-45ºC above
RT.

For the devices shown in Fig. 1, the V~OC~ remains essentially unchanged
after 130 hours of light soaking, *regardless of the processing
conditions or bias*. Only the device with 10 Å Cu and heat treated at
the highest temperature (of 240ºC) appears to show a slight decrease in
V~OC~, but the trend will have to be verified over the next few hundred
hours; this may suggest that the doping and back contact barrier two
factors that can influence V~OC~ are not changing. The FF of *all cells*
shown has already decreased significantly during the first 130 hours. In
general, it remains at higher levels for the devices heat treated at the
highest temperature (240ºC).

![](media/image1.wmf){width="5.995833333333334in"
height="8.605555555555556in"}

Another commonly observed behavior in CdTe devices is an initial
increase in performance. Evidence for that is present in some of the
cells shown in Fig. 1, where the FF exhibits an initial increase (with
the V~OC~ remaining constant). However, the increase is not present in
all devices, and the degree to which the FF increases varies. The
eventual decrease in the FF does not exhibit a consistent trend with
regards to bias; in one case (top) the FF of devices held at OC appears
to decrease faster while in the other (middle) the SC conditions seem to
lead to faster degradation in the FF. The OC conditions were found in
the past (by us and other groups) to lead to greater degradation, and it
is not clear right now whether the sample for which the SC conditions
lead to faster degradation is one of a kind. A significant amount of
data is currently being summarized and a more detailed report on a
larger number of processing conditions will be provided in the future.

![](media/image2.wmf){width="5.996456692913386in"
height="2.9909448818897637in"}As a result of bringing on line the
automated data collection system, it is now possible to perform a large
number of measurements. During the initial stages of this light soaking
experiments light J-V data were measured every 30 minutes. An
interesting feature of the device performance variation is displayed in
Fig 2 below, where the V~OC~ and FF for one of the devices of Fig. 1
(middle) are shown over a period of 20 hours (i.e. for 5 light cycles).
The arrows in Fig. 2 mark the start (solid) and end (dashed) of a light
cycle (ON). The V~OC~ decreasing trend during the ON cycle is consistent
with the cell operating temperature rising; cell temperatures have
reached 70ºC in some instances. The FF behavior however cannot be
explained by the rise in the operating temperature. The FF appears to
increase initially and subsequently (roughly at the mid point of the ON
cycle) begins to decrease. During the latter ON cycles (i.e. closer to
30 hours) the FF increases but appears to level off rather than decrease
during the second half of the cycle. Transient effects have been
reported and observed before, but their impact on device stability is
not well understood yet. We plan to continue to monitor these changes
but at this time the plan is to maintain the ON and OFF times at 4
hours. In future experiments it may be possible to study the effect of
the duration of the ON cycle in order to study the extent to which the
transients observed are reversible and whether long term stability can
benefit.

Vapor Chloride Treatment

As described in a previous report a larger vapor CdCl~2~ annealing
furnace has been brought on line in order to process several substrates
at a time and improve our overall understanding of this process. The
configuration currently used is shown in Fig. 3 below. The major change
over the small area annealing furnace is the extension of the substrate
zone to accommodate four 3 x 3 cm^2^ substrates.

![](media/image3.wmf){width="6.5in" height="2.4881889763779528in"}

![](media/image4.wmf){width="3.660236220472441in"
height="3.2291338582677165in"}Device results obtained in the new furnace
remain slightly below the performance levels achieved previously, and
performance is not uniform. At this time one of the issues appears to be
a temperature gradient along the sample zone that leads to a "gradient"
in performance. One example is shown in Fig. 4 where the V~OC~ and FF of
cells from two substrates heat-treated in CdCl~2~ vapors for three
minutes at a substrate temperature of 420ºC are shown (the temperature
is measured at the center of the sample zone). The cell position axis
indicates the location of the cells in the sample zone with #1 being the
device closer to the CdCl~2~ source and #8 being the device farthest
from the CdCl~2~ source. The sample zone has been profiled twice for
different source/sample temperature combinations and the measurements
have yielded a large gradient from the front to the back of the sample
that to a great extent follows the performance gradient shown. The close
proximity of the source and substrate zones and the large variation in
their temperatures appear to hinder our efforts to minimize this
temperature gradient, but changes are in the way in order to improve
this apparent shortcoming in the annealing furnace.

Large Area Deposition System

During the last few months work on films/devices prepared using the
large area deposition (LAD) system has focused on identifying the
cause(s) for the observed performance variation (cells prepared using
this process yielded V~OC~'s in excess of 820 mV and FF of over 70%).
One of the obvious problems was the presence of pinholes which in some
cases were visible to the naked eye. Figure 5 below shows SEM images
from several CdTe films prepared in the LAD system. The top images are
from films prepared using a gas mixture of He and O~2~ exhibiting grains
of about 1 μm (on average). These are similar to CdTe films deposited
with the baseline small area process. The two bottom images are from
specific regions in films where device performance exhibited significant
scattering. These show in one case a crater with a diameter of approx.
5-7 μm (left), and in the other several (CdTe) particles embedded in the
CdTe film, believed to have been ejected from the source during the
deposition process. These two images demonstrate what is believed to be
the major source for the variation in device performance; current
efforts are focused on ways to sinter the CdTe powder in order to
address this issue. It is believed that once these large defects are
eliminated that performance will be very uniform over the entire 10 x 10
cm^2^ deposition area.

![](media/image5.png){width="3.309055118110236in"
height="2.586220472440945in"}![](media/image6.png){width="3.309055118110236in"
height="2.5866141732283463in"}![](media/image7.png){width="3.309055118110236in"
height="2.586220472440945in"}![](media/image8.png){width="3.309055118110236in"
height="2.5866141732283463in"}

An example of the cell to cell variation (from the same run) is shown in
Fig. 6 below. The dark current increases (shunting) by nearly three
orders of magnitude in some extreme cases. Shunting is also present in
the light J-V data shown in the same figure.

![](media/image9.wmf){width="6.5in" height="3.2181102362204723in"}

TCO's/Buffer Layers

We continue to investigate devices with Zn-Sn-O-based buffer layers. The
main objective is to determine the effect of the metal ratio i.e. Zn/Sn,
on the device performance; a Zn/Sn ratio of 2 could produce the
stoichiometric Zn~2~SnO~4~ phase depending on post-deposition heat
treatment conditions. Zn-Sn-O films are being deposited by co-sputtering
allowing for easy control/variation of the film stoichiometry; the films
are used either as-deposited or after a high temperature heat treatment.
Promising device results presented in the last quarterly report were for
TCO/buffer structures based on Cd~2~SnO~4~ and Zn~2~SnO~4~ (Zn/Sn ratio
of 2). Currently, SnO~2~:F/Zn-Sn-O structures are being utilized and the
ratios being study are for Zn-rich films i.e. Zn/Sn\>2 (typically
between 2 and 3). Device results for Zn-rich buffer layers are in
general "average" with no obvious advantages in performance (V~OC~'s and
FF's have reached the 800-820 mV and high 60's ranges respectively). A
common device limitation is high leakage currents (shunting); it is
possible that the observed high leakage is due to the excess Zn
diffusing into CdS and the main junction. Work on these buffer films
continues with the main focus continuing to be on the effect of the
Zn/Sn ratio.

B. CIGS

One of the challenges that we continue to face with our 2-step
processing approach is controlling defects. As discussed on several
occasions, a particular issue is the effective incorporation of Ga. We
can get Ga into the space charge layer, and we can get it to bond to
open the band gap. However, in doing so we seem to always increase the
defect level. While we have made progress in reducing defect levels, we
still have not reduced them sufficiently to achieve the level of desired
performance. If we knew what the controlling defects are, this may lead
to process modifications that could control them. Unfortunately, there
is no direct way to determine exactly what the defects are at such low
levels. Instead we must use indirect techniques that rely upon various
types of input. We can measure the effect of defects on electronic
properties with techniques such as photocapacitance\[1\]. This also
helps us understand the relationship between the defects that we sense
and film composition as well as the relationship between composition and
device performance. These insights have lead to improvements in
processing and in performance, but more needs to be done.

![](media/image10.wmf){width="4.0582677165354335in"
height="3.341732283464567in"}To aid our experimental efforts we rely as
well upon guidance provided by simulation. In our earlier efforts much
of our device modeling was based upon assumed dominance by deep
levels\[2\]. This resulted in good agreement with experimental results
and to some extent helped point the way to new wrinkles in processing.
However, as we all know, models that fit a set of data are rarely
unique, and in this case we did not know what the deep level was that we
were using as the basis for modeling. Materials modeling by the NREL
Theory Group is assisting these efforts by providing insights to likely
defects in CIGS\[3\]. In Quarterly Report 5 of year 3 in the predecessor
to this project we presented modeling results based upon use of the
primary defect levels identified by the NREL Theory Group\[3\]. The
defects with the lowest formation energies are the V~Cu~ and the M~Cu~ +
2V~Cu~ defect pair. The V~Cu~ is acceptor-like, and the defect pair is
donor-like. Both are shallow, and thus compensation effects are
operative. ( A full discussion of this can be found in the earlier
report). What we want to pick up on here is the result that indicated a
difference in dark IV curves when one or the other of these defects is
dominant. In figure 1 we show an extended version of that result. The
lines are simulations for varying levels of compensation. The lowest
lying line is the ideal case of no defects. The device band gap is 0.95
eV, so with an expected Jsc of 40 mA/cm^2^ extrapolation of the dark IV
would result in an expected Voc of 600 mV. The solid line is the dark IV
that results from fitting the power curve of one of our top-end devices.
To fit the data for these devices requires about 40% compensation. The
top-most line is for full compensation, and the one below it is for 80%
compensation. As can be seen, as the level of compensation increases,
the dark IV shifts upward and thus lowers Voc. However, at the highest
compensation levels there is bending over at high voltages which reduces
the expected loss. Based upon these observations we feel that the dark
IV may be a telltale that indicates the level of compensation, and thus
indirectly suggests the operative defects.

![](media/image11.wmf){width="4.2334645669291335in"
height="3.033464566929134in"}Since the results in figure 1 only involve
shallow levels, there is a suggestion that deep levels may not be
operative as originally thought. To sort this out we are starting to
look more carefully at dark IV data. The data points( ) in figure 1 are
experimental data from a device with Voc of about 425 mV. The data is
from Isc --Voc plots. This eliminates contributions from series
resistance allowing a more direct look at junction properties. As can be
seen, the data falls near the curve for complete depletion, but seems to
bend over a bit more at high voltage. If the behavior is explainable
only by the shallow states used for the simulations in figure 1, then it
would be between 80% and 100% compensated. In figure 2 we show the
simulation of the junction region for 40% and 80% compensation. As can
be seen, the space charge width increases from about 200 nm to 450 nm
over this range of compensation. At full compensation, the device would
be completely depleted which would result in more unusual behavior.
However, 80% compensation with a space charge width of 400 -- 500 nm is
not unrealistic. 200 -- 500 nm is typically what we observe. This model
would result in a direct correlation between Voc and capacitance. That
is, as compensation increases, the space charge width increases
resulting in decreasing capacitance and correspondingly decreasing Voc.
We have observed such behavior previously in our photocapacitance
studies\[1\], but based on the then current model were attributing it to
deep states. These new observations suggest that shallow states may be
playing a role as well because of their compensation effects.

It now becomes important to distinguish between contributions from deep
and shallow states if we are to fully understand what is going on. The
near fit of the data to the shallow state simulations is suggestive, but
just a start. The bend over in the data seems to favor additional
mechanisms. In particular, deep states can produce such behavior\[2\]. A
comparison of diode factor behavior for deep and shallow states is shown
in figure 3 from our earlier simulation efforts. As can be seen, shallow
levels(at Ec -- 0.27 eV) produce low diode factors and thus steep IV
curves like those in figure 1. However, mid-gap levels produce diode
factors which become large in certain voltage ranges and thus can
produce the kind of bend over (small slopes) seen in figure 1. A more
direct comparison can be made by observing the experimental diode factor
in figure 4. This is from the data in figure 1. The behavior is seen to
be much more like the mid-gap simulation in figure 3 than the shallow
state simulation and thus favors contributions from deep states.

Although there appears to be support for deep state contributions in the
experimental data, determining what these states might be is not
straightforward. What one would look for is a defect near mid-gap with
low formation energy. There is no obvious answer here based upon the
defect properties from the NREL theory group. To sort this out will take
a considerable amount of data and analysis and some measure of luck.
Before getting that specific, however, we need to first address the
relative contributions from deep levels versus compensation from shallow
levels. An update will be provided in future reports.

![](media/image12.wmf){width="3.689763779527559in"
height="3.1381889763779527in"}

![](media/image13.wmf){width="3.791732283464567in"
height="2.617322834645669in"}References

1.  M. Shankaradas, Y. Ying, H. Sankaranarayanan, P. Panse, C. S.
    Ferekides and D. L. Morel, "Photocapacitance Analysis of Defect
    Mechanisms in Cu(In,Ga)Se Solar Cells", Proceedings of the 28^th^
    IEEE PVSC, Anchorage, 09/2000.

2.  P. Panse, H. Sankaranarayanan, R. Narayanaswamy, M. Shankaradas, Y.
    Ying, C. S. Ferekides and D. L. Morel, "Evaluation and Modeling of
    Junction Parameters in Cu(In,Ga)Se Solar Cells", Proceedings of the
    28^th^ IEEE PVSC, Anchorage, 09/2000.

3.  Su-Huai Wei, S. B. Zhang, and Alex Zunger, *Appl. Phys. Lett*.,
    **72**(4), 3199 (1998).

[^1]: ^†^ The lamps used for light soaking have failed on two occasions
    and the system had to be vented and repaired at approx. 80 and 130
    hours. Also due to lamp failure, the intensity for approx. 25 hours
    was 25% below the 1 sun level.