[^1]

*Abstract*---A DC balanced coding scheme designed for transmitting
relatively small amount of messages along with clock in a single signal
channel is described in this paper. The primary feature of this scheme
is that all the leading edges of all the pulses are at evenly
distributed times, while the message bits are encoded into the widths of
the pulses. Therefore the pulse train can drive sequential logics
directly just as an ordinary clock signal. Unlike most coding schemes,
the C5 scheme needs no channel initiation such as preamble, frame
synchronization pattern, etc.

*Index Terms*---Trigger System, DAQ, digitizer, DC balanced, data coding

# INTRODUCTION

[IN]{.smallcaps} high-energy physics experiment detectors, it has become
a trend to place the digitization devices close to the signal sources
and to send digitized data via serial link to the data acquisition (DAQ)
modules. The digitization devices usually need a clock signal derived by
the data acquisition modules from a common timing reference. In addition
to the clock, the DAQ system sometime sends various commands such as
register loading, synchronization, trigger acceptance, etc. to the
digitization devices.

![](media/image1.wmf){width="1.0506944444444444in"
height="1.1513888888888888in"}

In this paper, we describe the "Clock-Command Combined Carrier Coding"
(C5) scheme that is DC balanced and is designed to transmit command
messages with clock together in a single channel (usually a pair of
differential signals).

The primary feature of the C5 scheme is that the clock and message
recovery is extremely simple. In the C5 scheme all the leading edges of
all the pulses are at evenly distributed times, while the message bits
are encoded into the widths of the pulses. Therefore practically there
is no "recovery" needed for the clock. The pulse train can drive
sequential logics directly just as an ordinary clock signal.

In the C5 scheme, the channel initiation processes such as preamble,
training pattern, frame synchronization pattern etc. are not needed.
This simplifies the design of both the sender and the receiver.

# The Coding Scheme

## The Pulse

When there is no message sending, the pulse is a plain 50% duty cycle
clock. To carry message bits, pulse widths become wider or narrower
while all the leading edges of the pulses remain the same clock times.

Consider each clock period to be 4 unit intervals (UIs) long. A narrow
pulse has 1 UI high and 3 UIs low with 25% duty cycle; a wide pulse has
3 UIs high and 1 UI low with 75% duty cycle and a normal 50% one has 2
UIs in both high and low times. It is also possible to define 8-UI clock
periods. The duty cycles of the wide and narrow pulses are 62.5% and
37.5% respectively in the 8-UI case.

We use (-1), (0) and (+1) to denote three possible widths of each pulse,
i.e. narrow, normal and wide, respectively.

## The Pulse Train

Consider a pulse train with 5 pulses. Given that there are 3 possible
widths for each pulse, the total number of possible combinations is 3^5^
= 243. Out of these combinations, 51 of them are DC balanced.

We further require that the first pulse is non-zero one, i.e. either
wide (+1) or narrow (-1). This requirement ensures simple frame
detection. After long time with no message transition, the first
non-zero pulse represents the start of a message frame. This requirement
reduced the number of combinations down to 32.

Up to this point, one may transmit 5-bit frame in 5 clock cycles. We
denote this coding scheme as "5B/5C". However, it is preferable to
transmit message frames that fit byte boundaries. In order to transmit
4-bit frames using 5 clock cycles (4B/5C), we further select fewer
combinations.

Since the first pulse is either wide or narrow one, a disparity is
created. We require that the next non-zero pulse to cancel this
disparity. The number of combinations that meet this requirement now
becomes 24.

We assign 16 of them as "data codes" to transmit 4-bit frames. The other
8 are called "control codes", which have same maximum disparity and
therefore are also suitable to transmit information. However, the coding
scheme is so simple that there is practically no control protocol needed
in the operation.

![](media/image2.wmf){width="3.4493055555555556in"
height="2.2416666666666667in"}

![](media/image3.wmf){width="3.4472222222222224in"
height="2.2423611111111112in"}

The "data codes" and the "control codes" are shown in Fig. 2 and 3.

An indispensable pulse train is the plain 50% duty cycle clock. The
receiver is required to return initial condition after receiving 5 or
more 50% duty cycle clock pulses.

We use D0 to D15 to denote the 16 data codes, and C3, C5, C6, C7, C11,
C13, C14 and C15 to denote the command codes. The plain 50% duty cycle
clock is denoted as Q0. The vertical axes in Fig. 2 and 3 represent the
code numbers.

## Coding Rules:

Both encoding and decoding functions are very simple. A localized coding
scheme is chosen so that the widths of pulses 0-3 represent bits 3-0,
respectively. The coding rules can be described as the following:

1.  After 5 or more 50% duty cycle clock pulses, the first wide (+1) or
    narrow (-1) pulse, pulse 0, is the start of a 4-bit frame. The bit 3
    is determined by the width of pulse 0: wide = 1, narrow = 0.

2.  The bits 2-0 are determined by the width of the pulses 1-3: wide or
    narrow =1, normal = 0.

3.  The second non-zero pulse of both data and control codes cancels the
    disparity of the pulse 0. The third non-zero pulse, if any, has same
    disparity as the pulse 0 for data codes. For example, if pulse 0 is
    wide, the third non-zero pulse is also wide. The third non-zero
    pulse for control codes has different disparity as the pulse 0. The
    fourth non-zero pulse, always cancels the disparity of the third
    non-zero pulse.

4.  The pulse 4 is ignored in the decoding functions. In the encoding
    function, the width of pulse 4 is chosen to achieve DC balance.

5.  After pulse 4, if the pulse 5 is non-zero, either wide or narrow, it
    is the start of next 4-bit frame.

In the decoding functions, if the control codes are not used, the rule 3
above can be ignored.

## Subsets of the Codes

In Table I, all 16 data and 8 control codes are listed. Some subsets of
these codes should be discussed here.

There are 8 data codes and 2 control codes that are contained in pulse
trains with 4 pulses. This subset can be used to transmit 3-bit frames
in 4 clock cycles and is denoted 3B/4C. The frames duration of 4 clock
cycles is convenient for both encoding and decoding implementation when
there are less than 10 combinations needed to be transmitted every 4
clock cycles.

The 2B/3C codes transmit 2 bits information in 3 clock cycles. The
DC-balance is guaranteed after 3 clock cycles.

The smallest possible disturb to the pulse train from the plain clock
comes from 1B/2C codes. The disparity happens briefly when the pulse 0
becomes wide or narrow. It is canceled immediately in the next cycle.

In real applications when 4B/5C codes are used, one may reserve the
1B/2C or 2B/3C subsets for clock-jitter-critical conditions, while the
other codes can be used in non-critical ones. In the high-energy physics
digitizer case, use 1B/2C or 2B/3C codes for trigger and synchronization
check during data taking, for example, the other codes can be used for
register setting, configuration etc. before or after data taking.

# FPGA Implementations

## The encoder

A possible FPGA implementation of the C5 encoder is shown in Fig. 4.

![](media/image4.wmf){width="3.2666666666666666in"
height="1.5909722222222222in"}

The encoder operates at a clock 4 times as the bit rate. The (mod 20)
counter provides 5 bits counting from 0 to 19 and rotates back. The
lower 2 bits (UIb\[1..0\]) represent the phases or unit interval within
an output clock cycle. The first UI is always 1 and the last always 0 so
that a pulse with fix leading edge timing is output every 4 clock
cycles. The two bits in the middle, Y1 and Y2 can be both high (for wide
pulse), both low (for narrow pulse) or Y1=1, Y2=0 (for normal pulse).
They are determined by the function generator depending on the input
code (CD, B3-B0) and the pulse count (UIb\[4..2\]). The input "CD"
signifies a command or data code to be output and the inputs "B\[3..0\]"
specify the code number. As the counter output UIb\[4..0\] increments
from 0 to 19, 5 pulses with predefined widths are sent out.

The function generator can be visualized as a 256x2 bits ROM lookup
table. Use Altera Cyclone FPGA family as an example, the C5 encoder
shown in Fig. 4 takes only 1/8 of the M4K block for function generator
plus 6 logic elements. The unused memory bits and address lines can
still be used by other functions such as I/O buffers, or build a pair of
encoders using same M4K block for both function generators.

In our actual implementation of the encoder, logic elements instead of
the M4K block are used for the function generator. Since the bit map of
the function generator are highly localized, it is possible to decompose
the map into a set of 16x1 sub maps that can be built with FPGA logic
elements.

There are several options for plain clock generation. The plain clock
can be assigned to an invalid control code such as "C0", (or all 8
invalid control codes). When unused address lines are available in the
memory block, an additional control line can be used to produce plain
clock pulses. It is also possible to use a logic element to intersect
the output stream for plain clock generation.

## The decoder

A possible decoder diagram is shown in Fig. 5.

![](media/image5.wmf){width="3.1625in" height="1.9694444444444446in"}

The input pulse train CC to the decoder can drive sequential logic and
even phase-lock-loop (PLL) circuit directly. A recovered x4 clock is
generated as system clock for other functions in the chip and used to
provide delays for decoding functions. The decoder shown in Fig. 5 is
able to decode 16 data codes and uses only 22 logic elements.

The decoder extracts pulse width information by sampling two delayed
versions of the pulse train. The two samples are pipelined down in two
shift registers. The value of a bit is derived from the width of a pulse
directly using a simple AND (or NAND) operation.

The decoder is self-framed when a transmission starts. Initially, the
decoder receives more than 5 plain clock pulses. The (mod 5) counter is
held in reset state. When the first wide or narrow pulse appears as the
first pulse of the 5-pulse train, the counter begins to count. When the
counter reaches 4, the pulse train is correctly aligned in the shift
register and the data is stored in the parallel holding register as a
data valid signal "C5Valid" is generated.

The counter rotates to 0 to allow next data frame being received
immediately. Arbitrary numbers of data frames can be transferred back to
back. The availability of a data frame is signified by the "C5Valid"
signal. After the last data frame in a transmission, plain clocks are
sent. The decoder is held in the reset state again, ready for the next
transmission.

The C5 scheme also contains some intrinsic redundancy that can be used
as error detection. For example, the pulse train seen at the receiver
end must be DC balanced in the 5-pulse frame. It takes only a few logic
elements to implement the error detection feature.

## Test result

The encoder and the decoder described above are compiled and tested in
an Altera Cyclone (EP1C6Q240C6) FPGA device. Continuous sequences of 80
plain clock pulses followed by 16 connected C5 pulse trains are sent
from the encoder to the decoder through low cost twist pair wires. A
typical oscilloscope screen shot is shown in Fig. 6.

![](media/image6.png){width="2.688888888888889in"
height="2.061111111111111in"}

The traces in channel 1 are C5 pulse trains that the first pulse is
either wide or narrow. The pulse trains are used to drive both
sequential logics and a phase-lock-loop (PLL) circuit in the FPGA. The
recovered x4 clock from the PLL is divided by 2 using a 1 bit counter
and both polarities of the counter outputs are shown in Channel 3 and 4.
The data in the pulse train are extracted and the data valid signal is
fed into channel 2. The data valid pulse seen on screen comes from the
previous 5-pulse train outside the left edge of the screen. We trigger
on the data valid pulse generated by the 5-pulse train in the screen.
Due to the pipeline latency and cable delays, the data valid pulse we
triggered on is outside the right edge of the screen.

The operating frequency or bit rate of 26MHz is arbitrarily chosen but
it is within the range of normal clock/message transmission for most
high energy physics front end/digitizer applications.

Data errors are detected at the receiving end and no errors are seen in
continuous operation of several days, which corresponds to a data error
rate less than 10^-13^. At the relatively low frequency, the data error
rate should be very low as expected. There is no jitter observed in the
recovered clock beyond the accuracy of our instruments.

# Conclusion

Whenever a clock is to be transmitted, the C5 scheme is a convenient
method of carrying message along with the clock. It is a handy
replacement of configuration infrastructure.

The C5 scheme is not designed as a high efficiency data transmission
protocol. If we define the channel bandwidth efficiency as (number of
bits per frame)/(number of UIs per frame), for C5 scheme, it is 20%
comparing with 80% for 4B/5B or 8B/10B coding. However, the clock and
data encoding and decoding for C5 scheme are significantly simpler than
the high efficiency coding schemes.

The C5 pulse trains are directly correlated with the clock cycles. Clock
cycles are marked by the commands transmitted with no ambiguity. It is a
very useful feature for the synchronization checking and triggering.
Since the commands are transmitted in the same cable as clock, the
timing skew problem is completely eliminated.

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3.  H. Poor, *An Introduction to Signal Detection and Estimation*. New
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[^1]: ^^Manuscript received June 2, 2005. This work was supported in
    part Operated by Universities Research Association Inc. under
    Contract No. DE-AC02-76CH03000 with the United States Department of
    Energy.

    Jinyuan Wu and Zonghan Shi are with Fermi National Accelerator
    Laboratory, Batavia, IL 60510 USA (phone: 630-840-8911; fax:
    630-840-2950; e-mail: jywu168@ fnal.gov).