**Pierre Auger Project Electronics**

**Front End (FE) Board**

**Kwame Bowie**

September 1, 2000

##### Revised: 4/17/2001

1.  **Introduction**

The Front End (FE) board is the data acquisition board for the Surface
Detector Electronics system.

The Surface Detector Electronics system consists of a CPU board (CPU), a
Slow Controls board (SC), a Time Tagging board (TG), an Ethernet board
(ETH), a GPS receiver (GPS), and the Front End (FE) board. The FE board
is directly linked via the Local Bus to the all the subsections except
the Slow Controls board, which is accessible via the CPU. The block
diagram Fig. 1 shows the basic layout.

Figure 1: Surface Detector Electronics Interconnections

2.  **Operation**

The FE board is the data-acquisition board, the data storage board, and
the trigger generation board for the Surface Detector. The main
functions of the board are listed below:

-   FE Board must take 6 channels of analog data from photo multiplier
    tubes and convert it to digital data.

-   FE Board must store this digital data in memory deep enough to hold
    25.6 μs of data (6.4 μs pre-trigger and 19.2 μs post-trigger).

-   FE Board must transmit this data to the CPU based upon trigger
    conditions.

The following are the specifics of the board operation based upon the
Surface Detector and Front End board specification.

1)  The analog to digital data conversion (ADC) is to be done at a
    sampling rate of 40MHz and with a precision of 10 bits per channel.

2)  There will be six (6) channels of analog inputs from the photo
    multiplier tubes (PMTs). The three (3) high gain channels will
    contribute to the analog trigger, while all six channels will
    contribute to the digital trigger. All six channels will be stored
    as data within the FIFO memories.

3)  There will be a total of three (3) types of triggers: analog,
    digital, and external

4)  The memory will be double buffered so that an event may be accepted
    while data is being read out.

5)  The FE board must be air-cooled with no fan.

6)  The board must operate at temperatures between --20C and +60C.

To ensure that a prototype will be available for initial insertion, two
(2) versions of the FE board will be produced: Version1.0 and Version
2.0.

### 2.1 Version 1.0

The first version, Version 1.0, of the FE board will include only the
motherboard and the analog daughter card. However, the Version 1.0 will
support the use of a digital daughter card by providing a connector and
signal paths for the digital daughter card. The digital daughter card is
to be developed in parallel at a different location. The digital
daughter card will produce a digital trigger signal, which will be OR'ed
with the other two triggers (Analog and External) to control data flow
into the FIFOs.

To improve development time of Version 1.0, the FE board has been split
into three (3) separate boards: the FE motherboard, the Analog Daughter
Card, and the Digital Daughter Card. By separating the FE Board design
into distinct parts, several engineers may work on various portions of
the board in parallel. By making these distinct parts separate boards, a
delay on one board will have minimal effect on the others

.

### 2.2 Version 2.0

Version 2.0 of the Front End board will have the same physical
dimensions and stacking- connector positioning, but will eliminate the
FIFOs and the PLD. In place of the FIFOs and PLD will be an ASIC socket
for an ASIC designed to integrate all of the digital logic into a single
chip. As a result, the digital daughter card connector along with all
digital logic will be gone from Version 2.0. Also, the ASIC will handle
a more advanced triggering scheme which will be all digital so no analog
trigger will be present.

This document is to be used as a user's manual for the FE board and will
discuss only sections common to the FEv1 and FEv2 boards.

3.  **Input signals**

Input signals to the FE board originate from two (2) PMTs in groups of 3
analog signals. The two PMTs are set up so that their output gain is
different by a factor of 32. To simplify nomenclature we simply call the
two PMTs high gain and low gain. The PMT signals are appear at the FE
board as six single-ended, negative edged signals on 50 Ohm cables from
the PMT bases. The cables are terminated with high frequency SMA
sockets. The high gain channels have an input voltage range of 0 to
--0.3V and the low gain signals have a voltage span from 0 to --1.5V.

-   6 single-ended signals

-   50 Ohm cable impedance from bases

-   High gain range (0 to --0.3V)

-   Low gain range (0 to --1.5V)

The FE board has the ability to handle the 6 input signals in either
purely single ended form or in a pseudo-differential form via jumper
selection. The pseudo-differential method provides the ideal solution in
low-noise environments as it eliminates possible ground offsets between
the FE board and the PMT bases. To connect with the coax cable, we have
selected standard, right-angle, PCB-mount, SMA connectors from Amphenol
(part \# : ).

5.  **Shaping/Amplification/Filtering**

> **5.1 Overvoltage protection**

Before any filtering, shaping, or amplification is done, the amplifiers
must be protected from over-voltage conditions. This actually serves 2
purposes: first, it prevents large voltage spikes from exceeding the
maximum op-amp voltage ratings. Reliability will certainly be a major
concern in this project as the stations are predicted to be serviceable
only at very long intervals. Replacing op-amps after any large event or
noise spike is not an option. The second reason for including surge
protection on the analog input signals is to lower the power consumption
within the analog portion of the FE board. To achieve the over-voltage
protection goal, we use series-connected dual pin diodes. For the high
gain channels we only use 2 per channel since we can clamp after one
diode drop since the signal is limited to 300mV. However, for the low
gain channels, the signal range is much larger (1.5 V) so we need at
least 3 diode drops in the signal direction before we clamp the signal.
So for the low gain channels, each channel receives 3 pin dual diodes.
The pin diodes that were selected for this application are part #: .

**5.2 Amplification**

The very next step after surge protecting the inputs is to amplify the
inputs. The amplification enables the analog inputs to match the ADC
input range. We have selected the AD9203 ADC, and are using a 0 to 1V
input span, so the inputs must be amplified accordingly. I use the term
amplification as a generalization of the operations performed on the
inputs. The operations are actually polarity inversions, amplifications,
and/or attenuations. All three of these terms may be generalized and
considered amplifications by a gain factor, A. The sign and absolute
value of this gain factor determines whether the amplification is a
polarity inversion, an amplification, or an attenuation. In our case,
all high gain channels have a gain factor -10/3 and all low gain
channels have a gain factor of -2/3. Thus the high gain channel is
actually inverted the amplified, whereas the low gain channel is
inverted then attenuated. The part selected for the amplifier section
was the AD8011 current feedback op-amp because it provides excellent
gain vs. bandwidth characteristic and is also a very low power device.

**5.3 Filtering**

After the amplification stage, the inputs are filtered. This filter is a
simple, 2-pole, anti-aliasing filter. The signals that we intend to
recover span a wide range of frequencies and have spectral components
that also span many frequency ranges. The desired signals range from DC
to the maximum resolvable by the ADC. As a result, under-sampling
techniques must be rejected, and an anti-aliasing filter provides good
rejection of unwanted noise signals above the Nyquist frequency. The
sampling frequency of the ADC is 40 MHz so a simple 2-pole active filter
with cutoff frequency at 20 MHz works very well.

6.  **Analog to Digital Conversion**

The signal lines are single-ended analog waveforms which represent the
filtered, shaped, and amplified PMT outputs. These six signals are the
inputs for the analog-to-digital converters (ADCs). The ADC's ground
connections are isolated from each other and only return to their own
ground plane in order to prevent digital ground currents returning to
the analog input.

> **Figure 2: Analog-to-Digital Converter Supply Isolation**

The sampling device that was selected was the Analog Devices AD9203
flash ADC chip. This chip was selected due to its very low power
consumption with the high conversion rate and decent precision. The
AD9203 utilizes both edges of the SYSCLK signal. The ADC inputs are
clocked into the flash converter's sample and hold amplifiers on every
trailing edge of the SYSCLK signal. The digital outputs are latched onto
the data bus at each rising SYSCLK edge. To enable such a high sampling
rate at decent precision and low power, the AD9203 incorporates a
pipelined flash architecture. The intrinsic delay of each input sample
is 7 rising SYSCLK edges.

7.  **Digital Interface**

Due to the large difference between the FEv1.0 and FEv2.x boards, only a
very brief synopsis will be given of the digital interface will be
covered here. To fully understand the digital interface for each board,
the Appendices (FEv1.0 and FEv2.x) must be referenced.

All FE boards must interface with the PowerPC (PPC) 403GCX local station
CPU in order to transfer the accumulated data. The transfers occur once
a data buffer is filled and ready to transmit the ADC data. The PPC is
signaled that the FE is ready when the FE asserts EVTCLK. The PPC
processor then determines when it would like to conduct a data transfer.
To ease the load on the processor, the DMA fly-by-burst memory transfer
mode was selected. By deciding to use the DMA transfer mode, the ALU and
registers of the CPU can still execute instructions uninterrupted. The
fly-by-burst mode, is the fastest and simplest of all of the DMA
transfer modes, which is very important as the CPU data bus is locked
out at this time. The actual transfer uses 1 wait state for the memory
to enable adequate time for the FE boards to access the necessary data.
As a result, the data is put onto the bus at a 20MHz rate. Each buffer
consists of 2 FIFOs therefore reading both of these 1024 word buffers
will take roughly 102 us. However, after several CPU write cycles, the
CPU intervenes to allow the DRAM to refresh and row switch so the full
data transfer time ends up being a little bit longer than that.
Specifics of the DMA fly-by-burst protocol can be obtained from the
PPC403 User's Manual.