###### **Reliability Assessment of Embedded Passives for** 

***Spaceborne Electronics***

##### NASA RTOP 100774 2.B.03.2

TASK MANAGER: David Gerke, JPL

Report FY02

Preliminary Electrical Characterization

Date Submitted:

January 15, 2002

Authors:

Emily Wesseling (818)354-0619

Linda Del Castillo (818) 393-0418

David Gerke (818) 393-6372

# Embedded Passives - Preliminary Electrical Characterization

## **Introduction**

One of the greatest tasks of packaging is connecting large passive
devices, for example surface mount capacitors, with the active circuit
elements, which are often all together as one or a few IC's. With
embedded passives, fabricated on silicon or other substrates using thin
film technology, the portion of the circuit containing these
traditionally discrete elements can be created all together, in batch,
and eliminate the tedious picking, placing, and soldering process and
these vulnerable joint. They also promise great savings in circuit
volume, as well as potentially decreased parasitics and increased
robustness. These devices are intrinsically low height, but circuit
footprint could be drastically reduced by stacking passives within a
substrate and by putting active die over them. In principle the process
for making thin film passives can simply be repeated to stack devices.
However, these steps must be demonstrated, and the interactions between
nearby devices must be understood. While bump-bonding to attach die to
properly metallized surfaces is commonplace, the impact of the thermal
conditions for die attach procedures on the underlying materials must be
assessed. Under the Center for Integrated Space Microsystems' System on
a Chip program Integral Wave Technologies, Inc. (IWT) fabricated eight
"PASM Phase I" wafers to investigate these issues. The test vehicle
includes stacked capacitors and resistors and metallization for the
attachment of standard "daisy-chain" die. The data from these will lay
the foundation for design rules for embedded capacitors and resistors.
The Laboratory for Electronic Assembly and Packaging (LEAP) at Auburn
University will conduct studies in die attachment, particularly the role
of underfills, in addition to the tests by the advanced packaging group
at JPL. Later in the year this NEPP task will subject these test
structures to environmental stress.

### PASM Phase I 

The PASM Phase I chips contain capacitors made with two different kinds
of dielectric, Ta~2~O~5~ (TaO) and benzocyclobutene (BCB), and CrSi
resistors. The layout encompasses the various possible overlaps of these
devices and a flipped daisy-chain chip. The capacitors are two 5 mm by 5
mm parallel plates of copper separated by either TaO or BCB. All the TaO
capacitors were designed to be 25 nF, the BCB capacitors 150 pF. The
straight resistors were to be 1.1 cm long and 10 mils wide, with a value
of 4.5 k. The layers are separated by BCB, and the entire wafer is
coated with BCB with openings for the probe pads.

> Figure 1: Sketched layout of the PASM I chip. "T" indicates TaO
> capacitor, "B" BCB capacitor, and "R" resistor.

Table 1: Measured Passive Component and Location of Component

+-----------------------------------+-----------------------------------+
| ### Device                        | ### Location                      |
+-----------------------------------+-----------------------------------+
| T1                                | Layer 1 nothing above or below    |
+-----------------------------------+-----------------------------------+
| T2                                | Layer 1 under R5                  |
+-----------------------------------+-----------------------------------+
| T3                                | Layer 1 partially under T6        |
+-----------------------------------+-----------------------------------+
| T4                                | Layer1 partially under B4 and     |
|                                   | flip chip                         |
+-----------------------------------+-----------------------------------+
| T5                                | Layer 1 mostly under flip chip    |
+-----------------------------------+-----------------------------------+
| T6                                | Layer 2 over T3, R2, and B2       |
+-----------------------------------+-----------------------------------+
| B1                                | Layer 1 partially under B4        |
+-----------------------------------+-----------------------------------+
| B2                                | Layer 1 partially under T6 and    |
|                                   | flip chip                         |
+-----------------------------------+-----------------------------------+
| B3                                | Layer 1 mostly under flip chip    |
+-----------------------------------+-----------------------------------+
| B4                                | Layer 2 over B1, R2, and T4       |
+-----------------------------------+-----------------------------------+
| R1                                | Layer 1 nothing above or below    |
+-----------------------------------+-----------------------------------+
| R2                                | Layer 1 under T6 and B4           |
+-----------------------------------+-----------------------------------+
| R3                                | Layer 1 mostly under flip chip    |
+-----------------------------------+-----------------------------------+
| R4                                | ##                                |
|                                   | ## Layer 1 mostly under flip chip |
+-----------------------------------+-----------------------------------+
| #### R5: meander resistor         | Layer 2 over T2                   |
+-----------------------------------+-----------------------------------+

![](media/image2.wmf){width="3.8229166666666665in"
height="3.8125in"}Figure 2 Layout of the thirteen chips on the wafer.

Table 2: Wafer Conditions

+-------------+--------------------------------------------------------+
| ### Wafer   | ### Comment                                            |
+-------------+--------------------------------------------------------+
| A           | Poor yield. Singulated and daisy chain die attached to |
|             | 2 chips at JPL                                         |
+-------------+--------------------------------------------------------+
| B           | Poor yield. Sent to Auburn University.                 |
+-------------+--------------------------------------------------------+
| C1, C2, C3, | Good yield.                                            |
| C4, C5, C7  |                                                        |
+-------------+--------------------------------------------------------+

The first two wafers, completed in September 2001, primed the
fabrication line but yielded very poorly. All of the Layer 1 resistors
were open. The six delivered in October had a greater than 95% yield, if
yield is defined as those devices which are neither open nor short.

All the capacitors were measured at JPL with a Hewlett Packard 4284A LCR
meter at 100 kHZ, using 1 V~RMS~ exciting voltage and no bias voltage.
The results agreed well those from ITW, obtained from a Stanford
Research Systems 715 LCR meter. The resistors were measured at DC with a
Fluke 77 digital multimeter.

> ![](media/image3.wmf){width="5.99375in"
> height="3.248611111111111in"}**Figure 3:** Distribution of resistance
> for the R1-R4, the four straight resistors on Layer 1, and R5, the
> meander resistor on Layer 2.

Figure 3 shows the DC values of the resistors. The resistances of four
straight devices range from about three to more than ten times greater
than the target, 4.5 k. As the lithography looks approximately correct,
the value of the sheet resistance must be higher than expected. Since R5
is about twice as long but (visually) the same width as R1-R4, the sheet
resistance of that layer of SiCr must be even greater because its
resistance is consistently on the order of 100 k, not 9 k.

The capacitances at 100 kHz for the capacitors are plotted as a function
of radial position in Figure 4. We were concerned that these values
would depend on radial position due to processing variations, but they
do not appear to. Figure 4 does show that the TaO capacitors
consistently fall below the 25 nF target. The capacitors on Layer 2, B4
and T6, appear to have lower capacitances than those on Layer 1. The low
values for B3 were noted at ITW, and they were looking for design
variation to explain it. The capacitance of B2 on Chip 11 was greater
than 300 pF on wafers C1, C2, C3, and C4. Overall the variation among
the capacitors is reasonably low. 439 of the 468 TaO capacitors fall
between 21.8 and 23.4 nF (C/C~AVE~ = 1.6 / 22.5 = 0.071 .) The BCB
capacitors have an average value of 151 pF, very close to the 150 pF
target. They show a wider spread but are still fairly uniform on each
wafer and especially on the same wafer and under the same environment,
for example the partially covered B1 and B2. In this plot the high
values are all from Layer 1 on C7.

![](media/image4.wmf){width="5.998611111111111in" height="3.5in"}

![](media/image5.wmf){width="5.997222222222222in" height="3.5in"}

**Figure 4:** Capacitance versus distance from the center of the wafer
for all the capacitors in the "C" lot, except for extreme outliers and
failures. Top chart (TaO) includes 439 of 468 devices, and the bottom
includes 276 of 312 BCB capacitors. Devices were modeled as a capacitor
and resistor in series.

Several capacitors on C5 have been evaluated as a function of the
magnitude of applied alternating and direct voltages using a Hewlett
Packard 4284A. For each measurement the voltage was applied for a few
seconds and the impedance recorded. Then the voltage was changed and the
procedure repeated. The BCB capacitors are generally more robust than
the TaO ones. Twenty out of twenty BCB capacitors survived a bias
voltage of 40 V with 10 mV~RMS~. Of twenty-two TaO capacitors, eight did
not fail under the maximum available voltage, 40V~DC~, at least the
first time they were measured. One of these failed at 12.5 V~DC~ on a
subsequent measurement. The distribution of failures on the first set of
measurements is presented in Figure 5. No change in either the
capacitance or the resistance was detected for any of the capacitors
until failure. Neither the BCB nor the TaO capacitors' impedances showed
a definite dependence on the applied alternating voltage over the range
available, from 0.01 mV~RMS~ to 1.2 or 10 V~RMS~.

![](media/image6.wmf){width="5.99375in" height="3.248611111111111in"}

Figure 5: Number of failing TaO capacitors vs. applied DC voltage with
10 mV~RMS~

### Conclusion

The PASM Phase I C lot wafers yielded well, better than 95%. They
demonstrate the feasibility of fabricating CrSi resistors, BCB
capacitors, and TaO capacitors on the same substrate, both neighboring
each other on one layer and overlying each other. We have completed
initial measurements of their primary values and will proceed to
characterize their parasitics. These form the baseline against which we
can assess the effects of future die-attach and environmental stress
experiments.