## Response to US ATLAS Pixel Review

\*\*\*DRAFT\*\*\*

November 28, 2000

### WBS 1.1.1.1 Mechanics

Since the review, there have been a number of developments in the pixel
mechanics.

*A revised radial envelope for the pixel system(including the support
tube) was fixed by mid-November. This radial envelope is smaller than
that presented at the review. However, the pixel support tube no longer
must act as a thermal barrier for the forward SCT(a separate structure
will now do this), somewhat simplifying the design of the support tube.
But the design of the space frame and rail system becomes more
challenging(less space) than that presented at the review.*

*The US ATLAS management requested that we include the design and
fabrication of the pixel support tube in the US baseline scope or find
an alternative outside the US. The ATLAS management has formally
requested us to accept this responsibility, no other alternative being
available to maintain the schedule(see minutes of the Inner Detector
Steering Group Meeting of November 16).*

We have therefore accepted this responsibility and done our best to
update our preliminary cost estimate.

The estimated cost of this element was modified based on design work
done in the first two weeks of November, after a final definition of
envelopes and the creation of preliminary requirements document.

The \"thermal barrier\" has been renamed \"support tube\" to more
clearly identify its function.

WBS 1.1.1.1.1.2.4 Support Tube(Design). Design costs have been moved
into baseline scope.

WBS 1.1.1.1.2.4 Support Tube(Prototype). Costs for prototype have been
moved into baseline scope.

WBS 1.1.1.1.3.5 and 1.1.1.1.3.6(added element). Fabrication costs have
been updated.

*Some elements of the schedule we presented for the mechanics were felt
by the pixel Project Leader to be too aggressive. In particular, the
Production Readiness Review of the local supports(barrel staves and disk
sectors) was felt to be too early for the staves, a non-US
responsibility. Although the disk sectors could easily be ready for PRR
on the schedule shown at the review, the barrel staves and other barrel
elements being designed in Europe may not be ready for review on the
schedule shown. We have therefore modified the US schedule by adding up
to about four months in some milestones(reviews). Practically, the US
and European design efforts should be reviewed at the same time.*

*It may be possible to streamline the support structure design to reduce
cost.*

We have scrubbed the WBS elements 1.1.1.1.1.2.2(Disk Support Rings and
Mounts) and 1.1.1.1.1.2.3(Support Frame). The cost of 1.1.1.1.1.2.2 has
not been reduced. The reduction in radial envelope(beyond that presented
at the review) may require a partial redesign of the support ring to
meet space requirements, and the only practical means to assess the
viability of such a design is by analysis by Hytec. This may require
more analysis than originally planned.

The cost of 1.1.1.1.1.2.3 ascribed to Hytec has been reduced from about
369K to 325K. The test program of the support frame prototype attached
to a prototype support cone and endplate has been shifted to LBL. These
tests are assumed to be carried out by LBL mechanical
technicians(supported by base program. We assume the use of tooling
already made by Hytec and the TV holography system now being
commissioned at LBL.

In reviewing the estimate for this item, we identified tasks that had
not been included. In particular, the modifications(precision holes)
that must be put into the support frame. We have determined that this
work should be done at LBL and have made an estimate of the tooling
required based on preliminary design sketches. We have included these
costs, assuming one prototype round for the existing support frame and
one for production.

We understand the reviewers concerns that these design costs may appear
high after some years of development. But we note that

-   some months have been added to the schedule at the request of the
    pixel Project Leader.

-   a substantial design revision has occurred(going to an
    insertable-layout) with very tight clearances

-   the design of disk ring mounting has not yet been tested

-   the design of the frame has not been completed and significant
    uncertainties remain in some areas(services supports, interface to
    barrel shells being designed in Europe, overall mounting
    scheme\....)

-   all design effort on the pixel mounting scheme within the SCT
    remains to be done, and this is critical for the stability of the
    system

-   the frame will be a \"build to print\" bid overseen by Hytec
    throughout the bid and construction. All fabrication drawings must
    be completely redone as a result of the recent layout change and the
    final dimensions of the frame are still uncertain. All tooling
    drawings created for the prototype must be redone.

-   the disk ring fabrication will be done in a similar manner(although
    the fabrication may be sole-sourced)

In short, it is the strong opinion of the subsystem leader that
considerable engineering effort must be devoted to these critical items,
and that LBL engineering cannot be substituted, given the very
significant other mechanical commitments in the project. We will, of
course, make every effort to minimize the overall expenditure for
design, consistent with meeting requirements and schedule.

*Review installation issues again early next year.*

Installation issues will be part of the conceptual design review of the
support frame and related elements. In addition, the overall ATLAS
installation scenario is being revised and a new baseline installation
plan and schedule should appear by Spring 2001.

*WBS items 1.1.1.1.1.2.7 and 1.1.1.3.8 need clarification.*

We have reorganized the WBS as follows

WBS 1.1.1.1.1.2.7 has been renamed to be Final Assembly and no longer
includes design effort for installation at CERN - only assembly at LBL
or surface assembly at CERN.

A new WBS element 1.1.1.1.1.2.10 Installation now includes design effort
related to installation(insertion of the pixel system) at CERN. This
design effort is now in Management Contingency with a release date of
9/2002.

The design effort in WBS 1.1.1.1.1.2.6(Disk Assembly) and
1.1.1.1.1.2.7(Final Assembly) now maps into the sum of the Production
elements 1.1.1.1.3.7 and 1.1.1.1.3.8.

The Production element 1.1.1.1.3.10(Installation) is now all Management
Contingency with a release date of 9/2002.

The design effort in Integration(WBS 1.1.1.1.9) has been increased at
the request of the ID subsystem leader but the increased effort is all
in Management Contingency with a release date of 9/2002.

*There may be opportunities to reduce cost by examining tolerances*

We agree but this will naturally following during the design and early
fabrication process. We note that a requirements document exists so far
only for the local supports(disk sectors and barrel staves) but will be
created for reviews of the support structures. This will provide an
opportunity to systematically review all tolerances and reduce
fabrication costs if appropriate.

### WBS 1.1.1.2 Sensors

No recommendations were made by the reviewers.

### WBS 1.1.1.3 Electronics

*This plan (development of 0.25μ CMOS FE chip) is supported by the
committee to reduce risk. However, it results in a large design effort
for the transfer of the design, which needs to be supported in regards
to schedule, cost and manpower. In particular, the presented schedule
has serious resource conflicts in FY01 when major design and test tasks
will be pursued on large chips in two technologies in parallel.*

We agree with this concern, and we intend to give the 0.25μ development
higher priority when there is a resource conflict with work required for
the original DMILL effort. We also intend to make the critical go/no-go
decision on the use of DMILL as soon as it seems practical to do so, in
order to focus all effort on one solution.

*SEU performance needs to be predicted using cross section estimates,
and then measured for each design.*

We agree that SEU effects are a significant concern for microelectronics
located very close to the IP. We are pursuing a significant design,
prototype, and measurement program to address this concern. In our first
0.25μ test chip, we will already include several different FF designs,
with different levels of SEU tolerance. One will be a standard cell
design, one will involve three-fold majority logic to resolve bit flips,
and one will use a special SEU-tolerant FF design developed by CERN and
RD-49. We expect to compare the measured upset rates for structures in
our test chip with the estimated SEU cross-sections and thresholds
predicted by RD-49. This work will initially concentrate on the 55MeV
protons available at LBL, and then be extended to the CERN PS (24GeV
protons) and ultimately to PSI where the 300MeV pions are an excellent
model for an LHC underlying event.

In our 0.25μ design, we will use a very robust technique such as
redundant storage (perhaps three-fold majority logic) for our critical
configuration information. The exact choice on what approach to use will
depend on our measurements of relative sensitivities, but we believe
that a redundant scheme is the only way to achieve the desired
reliability (integrity) of the stored information. For less critical
information, whose disruption would affect only a single channel in a
50K channel module, we presently plan to use the SEU-tolerant FF design,
which offers reduced sensitivity but no redundancy.

In addition, we are specifically examining the effects of upset events
(small amount of charge deposited in a specific FET) on the performance
of our critical digital logic blocks using simulations, and depositing
spurious hits directly in the Verilog simulations. We are attempting to
ensure that all state machines and logic blocks will suffer only minor
transient effects after an upset, rather than longer term disruption of
the chip operation.

*Radiation degradation results for the TSMC process are similar, but
must be verified by ATLAS.*

We intend to perform initial irradiations of TSMC test chips in early
2001, in order to verify the impact of irradiation on our designs.
However, at this time we do not intend to carry out a complete
qualification of the radiation hardness of the TSMC process (as has been
carried out by RD-49 and others over the last few years for the IBM
process), as this is a very significant program. Rather, we see TSMC
primarily as a rapid prototyping process with properties very similar to
those of our primary vendor (IBM). Should problems arise with our
primary vendor, we would already have a functional design in TSMC, whose
performance under irradiation was roughly characterized, and we would
then undertake to fully qualify the TSMC version of the design for ATLAS
pixels. This appears to be the best compromise with our existing
resources.

*A more detailed plan on how many submissions of test chips is
needed\....The committee feels that the schedule, which contains no
float, is overly optimistic.*

We have worked out a more detailed plan for all activities required to
reach production quality 0.25μ pixel electronics. We have prepared a
revised summary schedule and milestone list based on this detailed work
plan. Our planning now includes two TSMC test chips(via MOSIS) prior to
the submission of the first IBM engineering run in July 2001.

The first test chip, referred to as a digital test chip even though it
also contains some analog blocks, will contain many individual circuit
blocks that will be used in the pixel chips. It would be submitted in
the Jan 8 2001 MOSIS run, to provide early feedback on our evolving
design. We intend to include the current reference and current-mode DACs
used for bias control, the revised LVDS I/O blocks, several shift
registers based on different FF designs for SEU studies, the present
SRAM storage cell used in the pixel, and several synthesized digital
blocks from the bottom of the pixel chip (timestamp generator for
example). The intention of this first test chip is to check our
understanding of the design rules and basic SPICE parameters, and then
to evaluate in detail the analog performance of some actual design
blocks. Finally, it will be irradiated and serve to check our
understanding of the process and some basic design blocks under
irradiation.

The second test chip is similar to ones we have built for previous
submissions to DMILL and HP. It would be an analog test chip, including
a small array of the preamp/discriminator design to be used in the final
pixel array, as well as the complete analog support for these circuit
blocks (current reference, current DACs, bias generation, calibration
circuitry). Our schedule would have first versions of all of these
blocks available in time to submit a test chip to the Mar 5 2001 TSMC
MOSIS run. With the expected 10-week delivery time from MOSIS, there
would still be adequate time to characterize the performance of this
chip before submitting the engineering run.

Finally, we have delayed the submission date for the FE-I1 engineering
run in order to provide adequate verification time for the final design.
We have also shifted the planned second engineering run date to allow
for final test beam characterization of complete FE-I1 modules in the
2002 testbeam. The original schedule had very little float before the
2001 testbeam window would be missed, and would very likely have forced
us to compromise on our verification of the FE-I1 submission in order to
get devices in time for 2001 testbeam. We prefer a schedule where the
testbeam verification comes at the end of the FE-I1 evaluation period,
in order to be able to test fully irradiated modules and to benefit from
the accumulated understanding of the chips which we would have by this
time.

*The consensus of the committee is that the contingency (36%) of the
electronics cost estimate is insufficient.*

We believe the contingency for the fabrication costs of the front-end
electronics and testing of same is adequate. However, we agree that the
contingency associated with the design labor is not large enough,
primarily resulting from uncertainties in base program support.
Therefore we have raised the contingency on the design effort from 25%
to 54%.

*The group has to increase the confidence level by tests whether the
0.25μ (process) will meet the requirements in the high-radiation
B-(Layer) location.*

We would like to first emphasize that in terms of total dose, there is
not a large difference between the B-layer and the outer layers. The
outer layers should withstand a total dose of about 50Mrad (including
several safety factors), over their design lifetime of ten years. The
B-layer was never anticipated to survive ten years, but was expected to
be replaced regularly as technology improved, and to have the same total
dose lifetime as the outer layers. In addition, the performance of the
B-layer, in terms of spatial precision and efficiency, has a large
impact on ATLAS physics capabilities, and hence it is expected that
there will be very strong interest in replacing this layer before its
lifetime has been reached. A second issue is whether our initial
electronics design can cope fully with the high occupancies and rates at
the small radius of the B-layer. As we noted at the review, the fallback
position is to use exactly the same electronics for the B-layer as for
the outer layers in case (a) the radiation resistance is found
inadequate or (b) insufficient design time is available to modify the
outer layer design to meet the more demanding requirements for the
B-layer. The initial (lower luminosity) operation of the B-layer should
be adequate with electronics designed for the outer layers. The ability
to replace the B-Layer during a [short]{.underline} access scenario is
built into our design. Thus an upgrade would be the most natural path in
case there are difficulties with the B-layer-specific design.

*A thorough test of system functionality in beam tests should be
planned.*

We have performed typically three beam tests at the CERN SPS per year on
pixel prototypes since 1997, and plan to continue doing so into the
future. In particular, we will be testing complete irradiated modules in
the 1.5T magnetic field of the SPS H8 beam at the latest by June 2002.
This work is carried out using the same VME-based readout electronics
that we use in our labs, and allows us to carefully cross-correlate
testbeam and lab results. The SPS provides special 25ns bunched-beam
running periods as well. We have already used the first such run to
verify that the performance we have measured in non-bunched beam tests
is really identical to that measured with the real beam time structure.
Finally, the next major step in the testbeam, originally scheduled to
occur in 2001, but now delayed by the problems with DMILL chips,
involves readout of multiple modules using the real off-detector
electronics (what in ATLAS are called RODs), and the opto-link
prototypes. This complete system test would occur in 2002 in our current
planning.

*No specification on the power supply rejection ratio of the FE- and
opto-chips has been presented*

We find this difficult to specify. We have tried to make our designs as
insensitive to power supply noise as possible, and we are planning to
evaluate a differential front-end design for our 0.25μ prototypes to see
how much this could help. We have measured the power supply rejection
versus frequency for our front-end chips by modulating the power supply
voltages with a small AC component, and characterizing the noise and
threshold (extracted from error-function fits to individual electronics
channels) as a function of amplitude and frequency of the injected
noise. We have then optimized our decoupling network on the module Flex
Hybrid to provide optimal power supply noise rejection in the frequency
range of maximum noise sensitivity. We are working on SPICE level
simulations of the power distribution (long power cables, and components
at intermediate patch panels), including the Flex Hybrid, to try to
further optimize their performance. We have recently constructed
electrical prototypes of our power cables, and plan to test single
modules with these prototypes and to measure the noise sensitivity of
the entire system of pixel module and power cable (however, this is
still using our old rad-soft electronics, so it is only the beginning).

*More work in regards to transient protection and fusing of low voltages
is required to establish a power distribution system.*

We agree completely with this recommendation and note that the
fabrication of multiple prototype, full-length, low-voltage cables is
underway with the intention of testing modules with prototype power
supplies in the next few months. This will provide a natural test bed
for transient protection studies. For the original DMILL electronics, we
had selected a ceramic surface mount varistor part for transient
protection. This appeared to work well in the lab, and sample parts were
irradiated in the SPS in May 2000 and were shown to work well after
irradiation. However, this technology does not have a steep enough I/V
curve to protect devices running at 2.0V (our planned 0.25μ operating
voltage) as opposed to the 3.5V-4.0V operating voltage planned for our
DMILL chips. We have located a new type of transient protection, using
an optimized punch-through diode, which looks ideal for protecting 0.25μ
chips. The particular design used for this diode looks promising in
terms of radiation hardness, and so we have ordered a large number of
these devices for evaluation and irradiation. Once they pass basic lab
characterization tests, we plan to use the prototype power cables and
prototype power supplies to study the types of transient waveforms that
can be induced in our power distribution system, and how well they are
suppressed by these devices. We expect that this series of measurements
will have largely validated our power distribution design within the
next 6 months.

*Radiation qualification of the custom ICs is a major task and the
manpower and milestones must be carefully planned.*

We completely agree on the scale of this effort. The present activity in
this area is largely carried by our European collaborators. During this
year, the following irradiations have been performed: (1) total dose and
SEU studies of opto-link components at PSI, in collaboration with ATLAS
SCT; (2) irradiation of single DMILL transistors, and complete Analog
Test chips in April at the PS, (3) irradiation of opto-link electronics
in May at the PS, (4) irradiation of MCC chips in Oct at the PS,
including real-time evaluation of functionality and SEU rates. These
tests were all performed on devices contained on our FE-D1 wafers. The
FE-D chips themselves were not irradiated in these periods because there
were too many yield problems with the existing devices to warrant such
effort. We intend to perform similar irradiations on most of the die
from the FE-D2 run. We also have inserted appropriate milestones into
our overall schedule for this work for the FE-I1 wafers. We are
establishing an irradiation effort based at LBL as well, using 55MeV
protons, in order to allow irradiation studies to continue during the
5-6 months per year that the CERN PS is not operating for irradiation
work. The detailed studies of the MCC under irradiation have already
been performed with their complete lab test system, with additional
boards added to support irradiation studies in situ. Similarly, for the
FE chips, we have already designed a rad-hard support card to interface
single chips or modules to our existing test system, and allow full in
situ characterization to be performed during irradiation, in the same
way that we do this work in our labs. We intend to perform these
irradiations using 55MeV protons (LBL), 24 GeV protons (CERN SPS), and
^60^Co gammas. In addition, we will try to perform realistic SEU studies
at PSI using their 300MeV pion beams.

*In general, the schedule needs to include more detailed task
descriptions to be able to develop a complete schedule and work plan*

We have developed a preliminary detailed schedule for all of the
electronics activity over the next 18 months, including the FE-I1
submission, its characterization, and the submission of the revised
FE-I2. We have inserted additional milestones into the overall pixel
project schedule for the test chips associated with the FE-I1 design
effort, and for the evaluation of the FE-I1 wafers. The detailed
schedule for the FE-I1 design includes schedules for the individual
circuit blocks, both at the schematic and layout level, as well as
top-level simulations at the schematic and post-layout levels. The
revised review and submission dates in the summary schedule reflect this
more detailed planning. An ATLAS Design Review has also been included
prior to submission of FE-I1. The submission date for FE-I has been
delayed by approximately 6 weeks to provide additional verification time
in the design flow.

*Management needs to be more project oriented\...\....*

As we noted in the review, we have included funding for systems/project
engineering. Peter Denes, who has considerable experience in electronics
management and who is now a senior member of the LBNL Engineering
Division (as of November 1), has just started working with the ATLAS
team in the area of IC and overall system design. In addition, the pixel
Project Leader is exploring the possibilities of enhancing the senior
engineering presence in Europe.

*The approach to IC design verification should become more
rigorous\.....*

Our overall approach to design verification includes the following:

-   specifications for each chip

-   the design is judged to be successful when simulations indicate that
    the specifications are met

-   a complete top-level(full-chip) simulation will be performed at the
    \"schematic\" level and a design review held

-   a complete top-level post-layout simulation will be performed and
    similarly reviewed

Each time we submit a new version of the pixel chips (we have now made
five versions in three different processes), we improve our verification
methodology. The present plan for FE-I1 includes the following steps:
(1) simulate and verify all individual blocks using SPICE and Verilog
with the vendor corner models; (2) simulate and verify at higher levels
using Verilog, including annotation for interconnection parasitics; (3)
simulation of large SPICE netlists, including all layout parasitics, for
large critical blocks like the column-pair; (4) many Verilog simulations
at the top level, using random data patterns to look for potential
design problems. In addition, we have worked with a newer verification
tool (TimeMill) which allows simulation of very large circuit blocks
with SPICE-like accuracy. If time and manpower permit, we will try to
use this tool during the final verification steps to insure there are no
timing errors at the highest level of the chip integration.

In our first DMILL submission (FE-D1), the global verification using
Verilog did not include proper back-annotation of parasitics. In
addition, the post-layout SPICE simulations of critical blocks were not
completed prior to chip submission. The result was a chip which worked
correctly, but had several internal buffering problems occuring at the
top level in the chip integration. These errors were not fatal, but were
not caught prior to submission because of the incomplete verification
methodology used. We believe that the revised methodology proposed here
does provide an adequate safety net to catch any significant errors in
the design.

*It would be prudent for the collaboration to develop fallback plans in
case additional IC iterations are needed, or if planned levels of base
manpower do not materialize.*

The only realistic fallback plan is the one that we presented at the
review: installation of the pixel system in 2006. We have increased the
contingency on the design effort in the US to respond to this
recommendation. In addition, every effort is being made to utilize
design resources outside the US, and some modest additional manpower in
Europe has been identified since the review and is being integrated into
the effort.

*The overall coordination of the electronics effort needs to be
strengthened*

We believe this can be accomplished to some extent by adding
systems/project engineering at LBNL, as we proposed at the review and
have described above. However, we note that the electronics coordination
within the global collaboration has been a rotating position, and that
the US does not, and cannot, have final authority in all areas of the
pixel electronics system.

Double counting error of 75K(too much) fixed in 1.1.1.3.2.4.1

A WBS element for the costs of TSMC test chips done via MOSIS has been
added(1.1.1.3.2.3.1).

### WBS 1.1.1.4 Flex and Optical Hybrids

Flex Hybrids

No changes made regarding flex hybrids.

Optical Hybrids

A milestone in June 2001 has been added to decided between the use of
the OSU and Taiwan optical packages.

*The committee indicated some concerns about reliability, the effects of
low temperature operation and irradiation.*

The reliability of the opto-packages has been studied using accelerated
aging tests AFTER irradiation. The PIN diode has passed the irradiation
and accelerated aging test up to to the pixel dosage. The VCSEL has been
tested to the SCT dosage and tests up to the pixel dosage are planned.
The cap of the opto-pack is fabricated uses ULTEM, which according to
CERN\'s Compilation of Radiation Damage Test Data (CERN 98-01), is
rad-hard to 10 Grad. We irradiated the cap with Co^60^ up to 50 Mrad and
no degradation was observed. We plan to do accelerated aging test after
irradiation of the completed packages. We also plan to do temperature
cycling between -20 and +20 C on the packages.

*The committee also had concern about \"single-point\" failure resulting
in no read out of multiple modules.*

We agree, of course, with this concern and understand that the design of
the optical hybrids must be as fail-safe as possible. This includes both
the optical and electrical components, and power distribution to these
components. We expect through the extensive prototype program(three
rounds included) to be able to arrive at a very robust system. We also
note that the design concept for the optical hybrids allows them to be
replaced(unplugged and new ones inserted), albeit with some considerable
time for access.

### WBS 1.1.1.5 Module Assembly/Test

*Wire bonding is a critical step and we recommend that it either be
concentrated at LBL or other sites be extensively qualified and
monitored. LBL should explore the purchase of an additional wirebonder.*

We concur with these concerns but believe it premature to include now in
the baseline cost estimate another wire bonder at LBNL. We intend to
move forward with qualifying university sites(and LBL). We note that UC
Santa Cruz is planned to share wire bonding for the SCT and some
capacity there may also be available for pixel construction.

We have added a WBS element during the prototype phase for production of
dummy wafers. It appears the cost of doing this in the US is the lowest,
and 8\" capability appears to exist. This adds about 20K to the cost
estimate.

Based on our experience with wire bonding to flex hybrids, we have added
the cost of a plasma cleaner. In addition, have added the cost of a more
sophisticated wire bond pull tester, since this will be needed routinely
during production for QA. This adds about 20K to the cost estimate.

We have also internally scrubbed this estimate.

Errors have been corrected in 1.1.1.5.1.3.2.

WBS 1.1.1.5.2.4.1 One of two additional tooling iterations has been
eliminated.

WBS 1.1.1.5.2.4.3 Electrical technician time has been reduced with
better estimate. Most of this work will be done by physicists.

WBS 1.1.1.5.2.5.1 Errors corrected

### WBS 1.1.1.6 Beam/System Test Support

Made level of effort(hence contingency set to zero) and total effort
cost reduced from 143K to 105K.