![](media/image1.png){width="0.7916666666666666in"
height="0.8958333333333334in"}

> Fermilab/AD/TEV
>
> Beams-doc-1499-V5

January 24, 2005

Tevatron Beam Position Monitor (BPM) Upgrade

Timing Generator Fanout Module, Filter Card and Integrated Crate Test
Plan

**Luciano Piccoli, Bill Haynes, Ken Treptow, Jim Steimel,**

**Vince Pavlicek,** **Dehong Zhang,** **Tim Kasza**

# Introduction

This document specifies the test plan for the standalone quality control
(QC) tests performed by the CD prep group for the Timing Generator
Fanout (TFG) modules and Filter Cards (FC) as well as the integration
tests performed on the fully assembled and cabled crates before they are
taken to the Tevatron service buildings. It is often logical to modify
the original qualification criteria. However, justifications of such
changes and modified test results should be included in this document.

# Timing Fanout Generator Stand-alone QC Test plan 

**Introduction**

The Timing Generator Fanout is a Double Width VME card. Its main
function is to provide a precision phase locked clock and Sync (or Gate)
pulse to each of the Echotek digitizers of the Tevatron Beam Position
Monitor (BPM) system. The TGF also provides a high resolution time stamp
and can generate VME interrupts based on 16 different TCLK events. The
Clock fan-out section of the TGF requires only power from VME to operate
and can be tested independently of the operation of the FPGA controlled
timing section. After the usual verification that power/ground plane
shorts do not exist, proceed as follows:

**Equipment and setup needed for the stand alone quality control test:**
![](media/image2.jpeg){width="0.7888888888888889in"
height="5.538194444444445in"}

1.  VME64X crate.

2.  Motorola MVME2400 processor board.

3.  VME Console Terminal.

4.  Frequency Counter, Spectrum Analyzer or Oscilloscope.

5.  Various cables.

**Test procedure**

**Step 1: Clock Fanout**

Note: Reference Beams-doc-1065 for a detail explanation of the TGF
module's Inputs and Outputs.

a.  After assembly and incoming inspection, prepare the TGF for testing.

```{=html}
<!-- -->
```
i.  Remove R29 & R31 to disconnect FPGA clock output from fan-out
    circuits.

ii. Remove solder short from JP10 and JP3.

iii. Add solder short to JP11 and JP4.

iv. Add solder short across JP7 to enable Conner Winfield Clock
    generator.

```{=html}
<!-- -->
```
b.  

c.  Insert the module into an un-powered VME Crate. Turn on the crate
    power and the front panel 5.0v & 3.3v LEDs should turn on.

d.  The firmware in the TGF must always be the latest version. If this
    test is the initial test or the firmware needs to be updated, new
    FPGA firmware must be downloaded to the TGF via the Front JTAG port
    using the Quartus programmer software. The firmware file name is
    'BPM_TOP.pof' and takes about 5 minutes to download.

e.  

f.  Connect an RFCLK (53.104 MHz clock, \> 60 mv) source to the RFCLK
    input and note that the LED labeled RFCLK turns on. The LED lights
    when the internal PLL is locked to the RFCLK and producing an output
    clock which is the RF clock multiplied by a 7/5 ratio. The PLL
    locking range is +/- 100ppm (approx. +/- 5KHz) of the center
    frequency of 53.10468MHz. Nominally the RFCLK is 53.10468MHz and the
    output clock is 74.34655MHz

Connect an RFCLK (53 MHz clock) source to the RFCLK input and note that
the LED labeled RFCLK turns on. The LED lights when the internal PLL is
locked to the RFCLK and producing an output clock which is the RF clock
multiplied by a 7/5 ratio. Nominally the RFCLK is 53.10468MHz and the
output clock is 74.34655MHz.

g.  

h.  Connect a frequency counter, spectrum analyzer or oscilloscope to
    the CLK0 output connector. In general an oscilloscope is adequate to
    test the clock fan-out circuit for functionality but a frequency
    counter or spectrum analyzer should used occasionally to measure
    that the locked output frequency is precisely 74.34655MHz (unless
    there is beam being accelerated in the Tevatron). If a spectrum
    analyzer is being used, any side band noise within a 50 MHz band
    should be attenuated by least 50dbm.

i.  Compare the remaining CLK1 - CLK7 to CLK0 to confirm that all
    outputs are the same frequency and amplitude (\> 700mv). The signals
    are transformer coupled (1:1) PECL levels.

**Step 2: FPGA Controlled Section**

The FPGA section consists of the VME interface, the BSync and TClk
Decoders, and the logic to control Sync pulses the Echotek digitizers
and interrupts to the VME CPU.

a.  

b.  

c.  

d.  Set the pc board eight position dip switch to all "on" except for
    switch position 2 being set to "off". This gives a VME base address
    of 0x2000. The sub rack map document (Beams #1498) shows how to set
    the address on this module.

e.  

f.  Run the TGF diagnostic software "runTimingTest" from the VxWorks
    prompt on the crate controller console terminal for the remaining
    tests.

g.  

h.  Select Register Test, menu item "0" of the "TGF diagnostic
    software". This test will verify that all the TGF registers are
    readable and writeable from VME. Confirm that the front panel VME
    SELECT LED flashes during the above test.

i.  

j.  Connect BSync to its front panel input and confirm that the front
    panel BSYNC LED turns on. The LED turns on when valid BSYNC events
    are being decoded and therefore requires RFCLK must also be
    connected.

k.  

l.  Connect TClk to its front panel input and confirm that the front
    panel TCLK LED turns on. The LED turns on when valid TCLK events are
    being decoded and therefore requires RFCLK must also be connected.

m.  

n.  Before the following tests can be run the user must have already
    confirmed that events are occurring on the BSync and TClk cables.
    This can be done by running the "TGF diagnostic software" menu item
    "e". The software will display the decoded events that have occurred
    on the BSync and TClk cables. Note, the displayed events are
    accumulated over a period of time and may require several seconds or
    minutes to display them all. To clear the accumulated events run
    menu item "l".

o.  

p.  Select the BSync Test menu item \# 1 of TGF diagnostic software.
    This checks the BSync event interrupts to the VME CPU with all the
    events required in the full BPM System.

q.  

r.  Select the menu item \# 2 of the "TGF diagnostic software". This
    checks TClk event interrupts to the VME CPU based on the decoding of
    specific TClk events and requires TClk to be connected to the TGF
    card. This test will try several combinations of TClk events
    interrupts and report success or failure.

s.  

t.  Select the menu item \# 3 of the "TGF diagnostic software". This
    checks the interaction of VME interrupt levels with simultaneous
    BSync and TClk events.

u.  

v.  Select the Wait TClk menu item \# 4. User inputs a particular TClk
    event (decimal) to be decoded and a specific TGF register, one of
    sixteen, to use. This event should be selected from the list of
    events known to be occurring. If the TClk event is not decoded in 30
    seconds an error is reported otherwise a successful detection is
    reported. This test can be used by module experts to diagnose
    specific interrupt problems in detail.

w.  

x.  Select the Sync Test menu item \# 5 of TGF diagnostic software. This
    test uses the BSync revolution marker (0xAA) for generating the
    trigger and Sync output pulses. Connect the front panel TRIG1 output
    to an oscilloscope trigger input and verify that each of the Sync
    (0-7) outputs generate one pulse per trigger. The output pulse of
    Sync0 will be generated first, followed by output Sync1, then Sync2,
    thru to Sync7. Each of the pulses should be evenly spaced through
    one revolution of the beam (\~21us).

y.  

z.  Run the "TGF diagnostic software" Time Stamp test, menu item #6.
    This test will measure the time interval from a BSync Clear event to
    the first Turn Marker after a Start event. This time interval is
    counted by an internal 106 MHz counter and should be the same for
    each TGF card (+-1 count).

a.  

b.  Run the "TGF diagnostic software" Filter Card test, menu item #7.
    This test will setup a Filter card inserted the VME subrack to
    connected a diagnostic signal (a modulated 53MHz pulse train) to all
    of the filter card output connectors. Connect TRIG1 of the TGF to
    the trigger input of an oscilloscope and observe the diagnostic
    signal of the Filter card output. The diagnostic signal can also be
    viewed on the TRIG2 connector of the TGF as a TTL pulse train

Run the "TGF diagnostic software" Filter Card test, menu item xx This
test will permit individual relays within the Filter card to be set or
cleared via the VME backplane. Writing a "01" to channel 0 should be an
adequate enough test to show that the TGF can communicate with the
Filter Card. This command will enable the diagnostic signal (a This
concludes the incoming production tests and qualifies the card for
system level tests.

> Note: To write to a particular TGF register outside the diagnostic
> software: run setTSGRegister offset, value at the VxWorks prompt. The
> offset and value are in standard hex format, for example 0x102,
> 0x0203.
>
> To read to a particular TGF register outside the diagnostic software:
> run getTSGRegister offset. The offset is in standard hex format, for
> example 0x102.

# Filter Card Stand-alone QC Test plan 

**Introduction**

The Filter Card is a single width VME64X card. The Filter Card obtains
5V, 12V, -12V power, SYSCLK, and interfaces to the Timing Generator
Fan-out (TGF) via reserved bussed pins from the VME crate. The Filter
Cards main function is to filter and attenuate the signal from the TeV
BPM sensors going to the Echotek digitizers. It also allows via relays
for a diagnostic signal to be sent to the Echotek, the BPM sensor, or
both. The TGF card controls this through its VME interface.

**Equipment and setup needed for the stand alone quality control test:**

> 1\. VME64X crate.
>
> 2\. Motorola MVME2400 processor board.
>
> 3\. Two Echotek ECDR-GC814-FV-A modules.
>
> 4\. Timing Generator Fan-out card.
>
> 5\. VME Console Terminal.

6.  Agilent 4395A Network Analyzer and 87511A S-Parameter Test Set.

7.  Various cables.

It requires two external inputs: Ethernet access to the 253 subnet of
FCC for the PPC processor and the 53.1 MHz Tevatron RF clock for the
TGF.

Here the TGF serves 3 purposes:

1.  Interface to the filter board to control the relays;

2.  Generate the 53.1 MHz diagnostic signal on the VME back plane;

3.  Generate the 74.3466 MHz clock signal for the Echotek boards.

One of the Echotek boards serves as the down-stream digitizer, while the
other as fake pick-ups up-stream to monitor the signals sent back to the
BPM pick-ups.

The PPC processor boots from "fndaut", and can save test results to
"/usr/devel/area2/vxworks/filter_board_test" on "fndaut". The loadable
modules, Echotek setup files and the startup script can be found in:
"/usr/products/devel/vxworks/tbpm_filter_board_test" on "fndaut".

Here is a picture of the setup, except for the VME console terminal.

![](media/image3.png){width="4.749305555555556in"
height="4.749305555555556in"}

**Test procedure:**

**Step 1: Visual Inspection and Initialization**

a.  

b.  Visually inspect the card for damage, solder shorts, or missing
    components.

c.  

d.  Verify with an ohmmeter that there are no power to ground shorts.

e.  

f.  Insert the card into an un-powered VME64X crate. Turn on the crate
    power and the 5V, 12V, and --12V LEDs should turn on.

g.  Download the FPGA firmware (bpmfc_control.pof) via the JTAG port
    using the Altera programmer software and an Altera ByteBlaster cable
    or equivalent.

**Step 2: Diagnostic Signal Test**

**Description of the tests**

Currently, we foresee to perform 3 tests on each production filter
board. First we set the TGF to generate the 53.1 MHz diagnostic signal,
then:

1.  Set the TGF to switch all the 8 relays on the filter board to "ADC",
    or

2.  Set the TGF to switch all the 8 relays on the filter board to "BPM",
    or

3.  Set the TGF to switch all the 8 relays on the filter board to "ADC
    and BPM"

Next we software trigger the Echotek boards to digitize and analyze the
signals they receive, then read out the Echotek boards to check the 53.1
MHz components against some predetermined range (minimum -- maximum)
criteria.

The software for these tests is actually a merge and adoption of the
multi-board test for the Echotek driver and the PREP filter test for
quality control of the production Echotek boards. The core part is the
setup file for the Echotek boards.

We took "DDC_board_test.ch" from the PREP filter test, modified the
following parameters:

a.  

b.  Clock rate from "80 MHz" to "74.3466 MHz";

c.  

d.  NCO frequency from "3 MHz" for an over-sampled 3 MHz input to
    "21.2418857 MHz" for an under-sampled 53.1047 MHz input;

e.  

f.  RCVR_DATA_SKIP from "0" to "18" to skip the transient effect;

g.  OUTPUT_WORD_SIZE from "6B" to "2B" to force one RCVR_DATA_SKIP to
    correspond to one BURST_COUNT.

With this setup, the Echotek boards would digitize the 53.1 MHz
diagnostic signals at 74.3466 MHz, down-convert their images at
21.2418857 MHz to DC, decimate and filter out frequency components
beyond +/- 0.26 MHz. The total decimation is 16. The overall frequency
response is shown in the following plot:

![](media/image4.png){width="5.834027777777778in"
height="4.375694444444444in"}

For each test, we take 64 samples from each channel and find the minimum
and maximum. The current cut-off range criteria are as follows:

  ------------------- -------- -------- -------- -------- -------- --------
  ECDR Channel        ADC               BPM               ADC &    
                                                          BPM      

                      min      max      min      max      min      max

  Proton ADC          1200     1600     0        50       700      1000

  Pbar ADC            4000     5000     0        50       2300     3000

  BPM Pick-up         0        50       14000    18000    9500     13000
  ------------------- -------- -------- -------- -------- -------- --------

The 2 Echotek boards are set to A16 addresses of "0xc000" \-- the one on
the left, the "ADC", and "0xd000" -- the one on the right, the fake
BPMs, while the filter board is set to index "0".

**Step** **3: Testing procedure**

a.  

b.  Set the filter board to index "0", insert into the crate, make sure
    it has seated properly;

c.  

d.  Connect the 8 output cables straight across horizontally to the
    corresponding input connectors on the Echotek board on the left --
    the ADC board;

e.  

f.  Connect the 8 input cables slightly slanted to the corresponding
    input connectors on the Echotek board on the right -- the fake BPM
    pick-ups;

g.  Power on the crate, watch for the boot process, in the end there
    will be 3 times rather loud "pop" sound, while the PPC prints to the
    console screen like the following:

Filter Board Test -\>RunTests

0x1da441c0 (tShell):

0x1da441c0 (tShell): Diagnostic 53.1 MHz ==\> ADC

0x1da441c0 (tShell): Channel 1: 35 34 35 \-- BAD !!!

0x1da441c0 (tShell): Channel 2: 35 34 35 \-- BAD !!!

0x1da441c0 (tShell): Channel 3: 34 33 34 \-- BAD !!!

0x1da441c0 (tShell): Channel 4: 32 32 33 \-- BAD !!!

0x1da441c0 (tShell): Channel 5: 31 30 31 \-- BAD !!!

0x1da441c0 (tShell): Channel 6: 34 34 35 \-- BAD !!!

0x1da441c0 (tShell): Channel 7: 33 32 34 \-- BAD !!!

0x1da441c0 (tShell): Channel 8: 36 35 36 \-- BAD !!!

0x1da441c0 (tShell): Channel 9: 20 19 22

0x1da441c0 (tShell): Channel 10: 22 21 24

0x1da441c0 (tShell): Channel 11: 28 27 29

0x1da441c0 (tShell): Channel 12: 26 25 27

0x1da441c0 (tShell): Channel 13: 14 13 15

0x1da441c0 (tShell): Channel 14: 14 13 15

0x1da441c0 (tShell): Channel 15: 19 18 20

0x1da441c0 (tShell): Channel 16: 19 18 21

0x1da441c0 (tShell):

0x1da441c0 (tShell): Diagnostic 53.1 MHz ==\> BPM

0x1da441c0 (tShell): Channel 1: 34 33 35

0x1da441c0 (tShell): Channel 2: 35 34 35

0x1da441c0 (tShell): Channel 3: 34 32 34

0x1da441c0 (tShell): Channel 4: 32 30 33

0x1da441c0 (tShell): Channel 5: 30 29 32

0x1da441c0 (tShell): Channel 6: 34 34 35

0x1da441c0 (tShell): Channel 7: 33 32 34

0x1da441c0 (tShell): Channel 8: 36 36 37

0x1da441c0 (tShell): Channel 9: 20 18 23 \-- BAD !!!

0x1da441c0 (tShell): Channel 10: 21 20 23 \-- BAD !!!

0x1da441c0 (tShell): Channel 11: 28 27 29 \-- BAD !!!

0x1da441c0 (tShell): Channel 12: 26 25 27 \-- BAD !!!

0x1da441c0 (tShell): Channel 13: 14 13 15 \-- BAD !!!

0x1da441c0 (tShell): Channel 14: 14 12 15 \-- BAD !!!

0x1da441c0 (tShell): Channel 15: 19 18 21 \-- BAD !!!

0x1da441c0 (tShell): Channel 16: 19 17 22 \-- BAD !!!

0x1da441c0 (tShell):

0x1da441c0 (tShell): Diagnostic 53.1 MHz ==\> ADC and BPM

0x1da441c0 (tShell): Channel 1: 34 34 35 \-- BAD !!!

0x1da441c0 (tShell): Channel 2: 35 34 35 \-- BAD !!!

0x1da441c0 (tShell): Channel 3: 34 33 35 \-- BAD !!!

0x1da441c0 (tShell): Channel 4: 32 32 34 \-- BAD !!!

0x1da441c0 (tShell): Channel 5: 31 30 32 \-- BAD !!!

0x1da441c0 (tShell): Channel 6: 34 34 35 \-- BAD !!!

0x1da441c0 (tShell): Channel 7: 32 32 34 \-- BAD !!!

0x1da441c0 (tShell): Channel 8: 36 35 37 \-- BAD !!!

0x1da441c0 (tShell): Channel 9: 20 18 22 \-- BAD !!!

0x1da441c0 (tShell): Channel 10: 22 20 23 \-- BAD !!!

0x1da441c0 (tShell): Channel 11: 28 27 30 \-- BAD !!!

0x1da441c0 (tShell): Channel 12: 26 25 27 \-- BAD !!!

0x1da441c0 (tShell): Channel 13: 15 14 15 \-- BAD !!!

0x1da441c0 (tShell): Channel 14: 14 13 16 \-- BAD !!!

0x1da441c0 (tShell): Channel 15: 20 19 21 \-- BAD !!!

0x1da441c0 (tShell): Channel 16: 19 17 20 \-- BAD !!!

0x1da441c0 (tShell):

0x1da441c0 (tShell): This board FAILed the tests !!!

> Where the last printout should declare the board to have passed or
> failed the tests. If the board fails, please check the cable
> connections, and re-run the tests by typing "RunTests" on the console
> keyboard;

e.  Type 'save "Serial No"' on the console keyboard to save the test
    result in "/usr/products/devel/vxworks/tbpm_filter_board_test" on
    "fndaut". The file will have a name like 'Board\_"Serial No".txt',
    and read like the following (from a different test than the above):

FRI DEC 03 14:44:55 2004

\-\-\-\-\-\-\-\-- FAIL \-\-\-\-\-\-\-\--

======================================================

Diagnostic 53.1 MHz ==\> ADC

Check criteria:

Proton ADC 1200 \-- 1600

Pbar ADC 4000 \-- 5000

Pick-up 0 \-- 50

Proton & Pbar Pick-up

\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\--
\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\--

mean min max mean min max

Channel 1: 1424 1423 1426 27 25 29

Channel 2: 1393 1392 1394 26 25 28

Channel 3: 4287 4286 4288 30 29 31

Channel 4: 4119 4117 4120 29 27 29

Channel 5: 1330 1329 1332 16 14 18

Channel 6: 1363 1362 1364 19 18 21

Channel 7: 4503 4502 4505 24 23 26

Channel 8: 4535 4533 4536 22 20 24

======================================================

Diagnostic 53.1 MHz ==\> BPM

Check criteria:

Proton ADC 0 \-- 50

Pbar ADC 0 \-- 50

Pick-up 14000 \-- 18000

Proton & Pbar Pick-up

\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\--
\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\--

mean min max mean min max

Channel 1: 17 16 18 16239 16218 16257

Channel 2: 17 16 18 15972 15952 15991

Channel 3: 16 15 17 15650 15633 15666

Channel 4: 19 18 19 15021 15006 15036

Channel 5: 15 14 16 15057 15045 15073

Channel 6: 14 12 15 15652 15640 15672

Channel 7: 10 8 11 16091 16077 16112

Channel 8: 9 8 10 16308 16292 16331

======================================================

Diagnostic 53.1 MHz ==\> ADC and BPM

Check criteria:

Proton ADC 700 \-- 1000

Pbar ADC 2300 \-- 3000

Pick-up 9500 \-- 13000

Proton & Pbar Pick-up

\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\--
\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\--

mean min max mean min max

Channel 1: 859 858 861 11174 11159 11188

Channel 2: 830 829 831 11048 11033 11062

Channel 3: 2562 2560 2563 10859 10842 10872

Channel 4: 2457 2456 2459 10397 10383 10407

Channel 5: 794 793 795 10403 10392 10415

Channel 6: 813 811 814 10824 10814 10836

Channel 7: 2680 2679 2682 11150 11140 11164

Channel 8: 2707 2705 2708 11309 11299 11323

Step 4: **Through Response (S21) Test**

a.  

b.  Using the Agilent 4395A with the S-parameter test set, measure the
    magnitude and phase difference between channel pairs. Calibrate to
    one channel and measure and record the difference of the second.

c.  Repair out of spec channels.

# VME Crate Integration Test

Once the VME crate is stuffed with individual boards, loaded with
appropriate firmware, following test procedures are performed. The
objective of this test procedure is to fully qualify the crate before
taking it to the assigned service buildings.

**Equipment and setup needed for the stand alone quality control test:**

**Test procedure:**

**Step 1: Check ...**

***Goal:***

Goal of the testing ...

***Equipment and HW/SW setup needed for the stand alone quality control
test***

***Pass/fail Criteria:***

***Performer:***

**Step 2: Check ...**

(Repeat steps as necessary)

# 

***Test result documentation (spreadsheets, screen captures etc. and
their on-line locations)***

# Change Log 

  ------------- ------------ ------------------------------------------------
  **Version**   **Issue      **Description of Change**
                Date**       

  1.0                        Original

                             

                             
  ------------- ------------ ------------------------------------------------

# Concurrence

Following persons reviewed and concurred with the content of this
document.

Steve Wolbers, Project Manager (date)

Bob Webber, Deputy Project Manager (date)

\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_

Jim Steimel, Technical Coordinator (date)

Vince Pavlicek, Subsystem Manager (date)

\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_

Margaret Votava, Subsystem Manager (date)

\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_

Rob Kutschke, Subsystem Manager (date)