![](media/image1.wmf){width="5.607638888888889in" height="0.85in"}

**D-Zero Detector Central Fiber Tracker (CFT) Axial Project**

**Readout Electronics**

**Central Tracker Trigger (CTT) Mixer System**

**Diagnostic Procedures**

Date: April 1^st^, 2002

Revision Date: March 18^th^, 2003

**N. George Wilcer, S. Marco Rapisarda, M. Tomoto**

**Document \# ESE-D0-020401**

**Table of contents**

1\. Introduction [5](#introduction)

2\. Subrack Controller [6](#subrack-controller)

Figure 2.1, Subrack controller simplified block diagram.
[6](#__RefHeading___Toc35762473)

2.1 Use of board Controller 1553 Interface
[7](#use-of-board-controller-1553-interface)

2.1.1 Read Subrack Controller Status Word
[7](#read-subrack-controller-status-word)

Table 2.1, Read Subrack Controller status word.
[7](#__RefHeading___Toc35762476)

Figure 2.2, Subrack Controller (DFEC) Status Word.
[7](#__RefHeading___Toc35762477)

2.1.2 Read from Subrack Controller Memory
[7](#read-from-subrack-controller-memory)

Table 2.2, Read from Subrack Controller memory.
[7](#__RefHeading___Toc35762479)

2.1.3 Write to Subrack Controller Memory
[8](#write-to-subrack-controller-memory)

Table 2.3, Write to Subrack Controller memory.
[8](#__RefHeading___Toc35762481)

2.1.4 Writing and executing a sequence of Subrack Controller Commands
[8](#writing-and-executing-a-sequence-of-subrack-controller-commands)

Table 2.4, Write and executing a sequence of Subrack Controller
commands. [8](#__RefHeading___Toc35762483)

3\. Diagnostic Procedure [9](#diagnostic-procedure)

3.1 Use of slow monitoring serial bus
[9](#use-of-slow-monitoring-serial-bus)

Table 3.1, Slow Monitoring information read back procedure.
[9](#__RefHeading___Toc35762486)

Figure 3.1, Mixer Board Slow Monitoring information
[9](#__RefHeading___Toc35762487)

Table 3.2, Example of Board Status Block read back.
[10](#__RefHeading___Toc35762488)

Figure 3.2, Slow Monitoring Diagnostic Procedure flow
[11](#__RefHeading___Toc35762489)

4\. Procedures [12](#procedures)

4.1 Board procedures [12](#board-procedures)

4.1.1 Read a board-controller register
[12](#read-a-board-controller-register)

Table 4.1, Read a Board Controller register
[12](#__RefHeading___Toc35762493)

4.1.2 Write to a board-controller register
[12](#write-to-a-board-controller-register)

Table 4.2, Write to a Board Controller register
[12](#__RefHeading___Toc35762495)

Figure 4.1, broadcast control for writes operations
[13](#__RefHeading___Toc35762496)

4.1.3 Board devices access structure
[13](#board-devices-access-structure)

Figure 4.2, Board device access structure
[13](#__RefHeading___Toc35762498)

4.1.4 Read device registers [14](#read-device-registers)

Figure 4.3, Read from device registers [15](#__RefHeading___Toc35762500)

4.1.5 Write to device registers [16](#write-to-device-registers)

Figure 4.4, Write to device registers [18](#__RefHeading___Toc35762502)

4.1.6 Board reset [19](#board-reset)

Table 4.5, Mixer board reset command sequence
[19](#__RefHeading___Toc35762504)

Figure 4.5, Mixer board reset [19](#__RefHeading___Toc35762505)

4.1.7 Reset Board Controller History Information
[19](#reset-board-controller-history-information)

Figure 4.6, Reset board controller history information
[19](#__RefHeading___Toc35762507)

4.1.8 Read Mixer Board configuration status and device\'s firmware ID
[20](#read-mixer-board-configuration-status-and-devices-firmware-id)

Figure 4.7, Read configuration status and device\'s firmware ID
[20](#__RefHeading___Toc35762509)

4.1.9 Erase Mixer Board Configuration
[20](#erase-mixer-board-configuration)

Figure 4.8, Erase mixer board configuration
[20](#__RefHeading___Toc35762511)

4.1.10 Configure mixer board [21](#configure-mixer-board)

Figure 4.9, configure mixer board [21](#__RefHeading___Toc35762513)

Table 4.6, Configuration Files denomination.
[21](#__RefHeading___Toc35762514)

Table 4.7, Mixer# and Subrack slot#. [22](#__RefHeading___Toc35762515)

4.1.11 Read board controller firmware revision date and board serial
number
[22](#read-board-controller-firmware-revision-date-and-board-serial-number)

Figure 4.10, Read board controller firmware revision date and board
serial number [22](#__RefHeading___Toc35762517)

4.1.12 Read/Write test [23](#readwrite-test)

Figure 4.11, Read/write test [23](#__RefHeading___Toc35762519)

4.1.13 Reset Board History Information
[23](#reset-board-history-information)

Figure 4.12, Reset Board History Information
[23](#__RefHeading___Toc35762521)

4.1.14 Taking a snapshot of Mixer Board status
[24](#taking-a-snapshot-of-mixer-board-status)

Figure 4.13, Mixer Board status snapshot
[24](#__RefHeading___Toc35762523)

4.2 Input Links procedures [25](#input-links-procedures)

4.2.1 Read input links error status [25](#read-input-links-error-status)

Figure 4.14, Read input links error status
[25](#__RefHeading___Toc35762526)

4.2.2 Read input links status [26](#read-input-links-status)

Figure 4.15, read input links status [26](#__RefHeading___Toc35762528)

4.2.3 Reset Mixer Board input links status history
[27](#reset-mixer-board-input-links-status-history)

Figure 4.16, Reset input links status history
[27](#__RefHeading___Toc35762530)

4.2.4 Input Links Control [28](#input-links-control)

Figure 4.17, Input Links control procedure.
[28](#__RefHeading___Toc35762532)

Figure 4.18, Input Links Control register
[28](#__RefHeading___Toc35762533)

4.2.5 Input Links Control bits masking
[29](#input-links-control-bits-masking)

Figure 4.19, Input Link Control Bits Mask Register
[29](#__RefHeading___Toc35762535)

Figure 4.20, Command bits generation, timing and denomination.
[29](#__RefHeading___Toc35762536)

Table 4.8, Example of command sequence to mask control bits on the input
links. [30](#__RefHeading___Toc35762537)

Figure 4.21, input links control bits masking
[31](#__RefHeading___Toc35762538)

4.2.6 Monitoring mode 7 masking [32](#monitoring-mode-7-masking)

Figure 4.22, monitoring mode 7 masking [32](#__RefHeading___Toc35762540)

4.2.7 Input Links Control bits status
[33](#input-links-control-bits-status)

Figure 4.23, read input links control bits status
[33](#__RefHeading___Toc35762542)

4.2.8 Embedded Command Bits Status [34](#embedded-command-bits-status)

Figure 4.24, Read Embedded Command Bits status.
[34](#__RefHeading___Toc35762544)

4.3 Backplane Devices Procedures [35](#backplane-devices-procedures)

4.3.1 Reset Backplane Devices History
[35](#reset-backplane-devices-history)

Figure 4.25, reset backplane devices history.
[35](#__RefHeading___Toc35762547)

4.3.2 Readback Mixer Board clock/SYNC status
[36](#readback-mixer-board-clocksync-status)

Figure 4.26, Read Clock/SYNC Status and History.
[36](#__RefHeading___Toc35762549)

4.3.3 Reset Mixer Board clock/SYNC status history
[36](#reset-mixer-board-clocksync-status-history)

4.4 Output links devices procedures
[37](#output-links-devices-procedures)

4.4.1 Output link FIFO read [37](#output-link-fifo-read)

Figure 4.27, Read content of an output link FIFO.
[37](#__RefHeading___Toc35762553)

4.4.2 Output link FIFO Write [38](#output-link-fifo-write)

Figure 4.28, Write content of an output link FIFO.
[38](#__RefHeading___Toc35762555)

4.4.3 Output Link FIFO reset [38](#output-link-fifo-reset)

4.4.4 Output link FIFO Configuration
[39](#output-link-fifo-configuration)

Figure 4.29, Output link FIFO configuration.
[39](#__RefHeading___Toc35762558)

4.4.5 Triggering of Output Links FIFO
[40](#triggering-of-output-links-fifo)

Figure 4.30, Triggering of Output Link FIFO.
[40](#__RefHeading___Toc35762560)

4.4.6 Use of Output Links FIFOs [40](#use-of-output-links-fifos)

Figure 4.31, Use of Output Links FIFOs.
[40](#__RefHeading___Toc35762562)

4.4.7 Reset Output Links History Information
[41](#reset-output-links-history-information)

Figure 4.32, Reset output links history information
[41](#__RefHeading___Toc35762564)

4.4.8 Output links Control Bits Masking
[42](#output-links-control-bits-masking)

Table 4.9, Example of command sequence to mask control bits on the
output links. [42](#__RefHeading___Toc35762566)

Figure 4.33, Output links control bits masking.
[43](#__RefHeading___Toc35762567)

4.4.9 Output Links Control [44](#output-links-control)

Figure 4.34, Output links control [44](#__RefHeading___Toc35762569)

4.5 System procedures [45](#system-procedures)

4.5.1 Mixer System reset [45](#mixer-system-reset)

Figure 4.35, Mixer System reset [45](#__RefHeading___Toc35762572)

4.5.2 Mixer System Extended Reset [46](#mixer-system-extended-reset)

Figure 4.36, Mixer System extended reset
[46](#__RefHeading___Toc35762574)

4.5.3 Mixer System power-up initialization
[47](#mixer-system-power-up-initialization)

Figure 4.37, Mixer System Power-up initialization
[47](#__RefHeading___Toc35762576)

4.5.4 Mixer System configuration erasing
[47](#mixer-system-configuration-erasing)

Figure 4.38, Mixer System configuration erasing.
[47](#__RefHeading___Toc35762578)

4.5.5 Broadcast configuration of the mixer system
[48](#broadcast-configuration-of-the-mixer-system)

Figure 4.39, broadcast configuration of the mixer system
[48](#__RefHeading___Toc35762580)

5\. Use of the LEDs Monitoring Mode
[49](#use-of-the-leds-monitoring-mode)

Figure 5.1, Front panel LEDs and LEDs monitoring mode
[49](#__RefHeading___Toc35762582)

Figure 5.2, Mode of Operation register [49](#__RefHeading___Toc35762583)

Figure 5.3, Monitoring Mode Register [50](#__RefHeading___Toc35762584)

Figure 5.4, Monitoring Status Registers
[50](#__RefHeading___Toc35762585)

Figure 5.5, Monitoring Status History Registers
[50](#__RefHeading___Toc35762586)

Table 5.1, Monitoring Mode change [51](#__RefHeading___Toc35762587)

Figure 5.6, Monitoring Mode change [51](#__RefHeading___Toc35762588)

Figure 5.7, Enable/Disable LEDs to show monitoring mode
[51](#__RefHeading___Toc35762589)

Figure 5.8, Read monitoring status and status history
[52](#__RefHeading___Toc35762590)

6\. Problem reporting [53](#problem-reporting)

6.1 Report a problem to mixer system support
[53](#report-a-problem-to-mixer-system-support)

6.2 Report a problem to AFE system support
[53](#report-a-problem-to-afe-system-support)

7\. References [54](#references)

# Introduction

This document describes the use of the diagnostic features and provides
the recommended procedures to operate the mixer system.

More information on the D0 CTT Mixer System is provided in a separate
document \[Ref.4d\].

# Subrack Controller

Details provided in separate document \[Ref. 4d\].

![](media/image2.wmf){width="6.0in" height="5.40625in"}

[]{#__RefHeading___Toc35762473 .anchor}Figure 2.1, Subrack controller
simplified block diagram.

## Use of board Controller 1553 Interface

### Read Subrack Controller Status Word

Table 2.1 provides the command sequence to read the Subrack Controller
(DFEC) status word. The status word contains the information on the
current status of the subrack controller (BUSY, HALT, IDLE) and the type
of error in the case an error occurred in executing the last command.

  ------------- ------------ -------- ----------------------------------------
  Command to    1553 Remote  Number   Notes
  1553 Remote   Terminal     of words 
  Terminal      subaddress            

  Read          18 (0x12)    1        Readback Subrack Controller Status Word.
  ------------- ------------ -------- ----------------------------------------

[]{#__RefHeading___Toc35762476 .anchor}Table 2.1, Read Subrack
Controller status word.

![](media/image3.wmf){width="4.96875in" height="1.75in"}

[]{#__RefHeading___Toc35762477 .anchor}Figure 2.2, Subrack Controller
(DFEC) Status Word.

### Read from Subrack Controller Memory

  ------------- ------------ -------- ----------------------------------------
  Command to    1553 Remote  Number   Notes
  1553 Remote   Terminal     of words 
  Terminal      subaddress            

  Write         16 (0x10)    1        Write the memory address in the subrack
                                      controller address pointer register.

  Read          17 (0x11)    n        Read the subrack controller data
                                      register. The content of the address
                                      pointer register is automatically
                                      incremented each time the data register
                                      is accessed.
  ------------- ------------ -------- ----------------------------------------

[]{#__RefHeading___Toc35762479 .anchor}Table 2.2, Read from Subrack
Controller memory.

### Write to Subrack Controller Memory

  ------------- ------------ -------- ----------------------------------------
  Command to    1553 Remote  Number   Notes
  1553 Remote   Terminal     of words 
  Terminal      subaddress            

  Write         16 (0x10)    1        Write the memory address in the subrack
                                      controller address pointer register.

  Write         17 (0x11)    n        Write to the subrack controller data
                                      register. The content of the address
                                      pointer register is automatically
                                      incremented each time the data register
                                      is accessed.
  ------------- ------------ -------- ----------------------------------------

[]{#__RefHeading___Toc35762481 .anchor}Table 2.3, Write to Subrack
Controller memory.

### Writing and executing a sequence of Subrack Controller Commands 

+------+-------+-----+-----------+-----------------------------------+
| Com  | 1553  | Num | Data      | Notes                             |
| mand | R     | ber |           |                                   |
| to   | emote | of  |           |                                   |
| 1553 | Ter   | wo  |           |                                   |
| Re   | minal | rds |           |                                   |
| mote | subad |     |           |                                   |
| Term | dress |     |           |                                   |
| inal |       |     |           |                                   |
+------+-------+-----+-----------+-----------------------------------+
| W    | 16    | 1   | 0x0080    | Write the address of the top      |
| rite | (     |     |           | location of the command buffer in |
|      | 0x10) |     |           | the address pointer register.     |
+------+-------+-----+-----------+-----------------------------------+
| W    | 17    | n   | \<command | Write to the subrack controller   |
| rite | (     |     | 1\>       | data register. The data will be   |
|      | 0x11) |     |           | written in the command buffer     |
|      |       |     | \<...\>   | starting from location 0x0080.    |
|      |       |     |           |                                   |
|      |       |     | \<command |                                   |
|      |       |     | m\>       |                                   |
+------+-------+-----+-----------+-----------------------------------+
| W    | 17    | 1   | 0xA1      | Write to the subrack controller   |
| rite | (     |     |           | data register.\                   |
|      | 0x11) |     |           | 0xA1 is the "End of List" command |
|      |       |     |           | and must always be placed at the  |
|      |       |     |           | end of a command sequence to stop |
|      |       |     |           | the subrack controller from       |
|      |       |     |           | fetching and executing commands.  |
+------+-------+-----+-----------+-----------------------------------+
| W    | 16    | 1   | 0x0080    | Optional step (command sequence   |
| rite | (     |     |           | verification)\                    |
|      | 0x10) |     |           | Write the address of the top      |
|      |       |     |           | location of the command buffer in |
|      |       |     |           | the address pointer register.     |
+------+-------+-----+-----------+-----------------------------------+
| Read | 17    | n   | ...       | Optional step (command sequence   |
|      | (     |     |           | verification)\                    |
|      | 0x11) |     |           | Verify that the read back         |
|      |       |     |           | sequence matches the sequence of  |
|      |       |     |           | commands \<command 1\> ...        |
|      |       |     |           | \<command m\>.                    |
+------+-------+-----+-----------+-----------------------------------+
| W    | 18    | 1   | 0x00      | Write to subaddress 18 (0x12) to  |
| rite | (     |     |           | have the Subrack Controller to    |
|      | 0x12) |     |           | execute the command sequence      |
|      |       |     |           | stored in the command buffer.     |
+------+-------+-----+-----------+-----------------------------------+
| Read | 18    | 1   | \<status  | Read back Subrack Controller      |
|      | (     |     | word\>    | status word.\                     |
|      | 0x12) |     |           | Verify the Subrack Controller     |
|      |       |     |           | status is IDLE or BUSY.\          |
|      |       |     |           | Continue read back until the      |
|      |       |     |           | state is IDLE to confirm the      |
|      |       |     |           | execution of the entire sequence  |
|      |       |     |           | of commands without errors.       |
+------+-------+-----+-----------+-----------------------------------+

[]{#__RefHeading___Toc35762483 .anchor}Table 2.4, Write and executing a
sequence of Subrack Controller commands.

# Diagnostic Procedure

## Use of slow monitoring serial bus

Detailed information on the mixer system subrack controller is provided
in \[Ref.1f\].

The mixer board status information is continuously collected from the
mixer boards by the Mixer System subrack controller over a custom serial
bus. The information is stored in the subrack controller memory space
and is made accessible through the MIL-STD-1553 Remote Terminal
interface. The mixer board status information read back from each mixer
board is shown in Figure 3.3.

Table 3.5 provides the command sequence to read back the slow monitoring
board status information from the Mixer System subrack controller
memory.

Figure 3.3 shows the information provided in the Mixer Board slow
monitoring word, detailed description of the word is provided in a
separate document \[Ref.4d\].

  ------------- ------------ ---------- -----------------------------------
  Command to    1553 Remote  Number of  Notes
  1553 Remote   Terminal     words      
  Terminal      subaddress              

  Write 0x0080  16 (0x16)    1          Point the address pointer to the
                                        top of the Board Status Block
                                        memory space (0x0080-0x00F9)

  Read          17 (0x11)    20         Read back Board Status Block
                                        Memory. The first word provide the
                                        status information of the mixer
                                        board in slot# 2, the 20^th^ word
                                        of the mixer board in slot# 21.
  ------------- ------------ ---------- -----------------------------------

[]{#__RefHeading___Toc35762486 .anchor}Table 3.5, Slow Monitoring
information read back procedure.

![](media/image4.wmf){width="5.958333333333333in" height="2.0in"}

[]{#__RefHeading___Toc35762487 .anchor}Figure 3.3, Mixer Board Slow
Monitoring information

  -------------- --------- ------------------------------------- -------------------------------
  Subrack        Mixer     Read back data                        Notes
  Controller     Subrack                                         
  Memory Address Slot#                                           
  (Board Status                                                  
  Block)                                                         

  0x0080         2         0x**D**22C\                           The board type is 0xD (mixer
                           b**1101**\_0010_0010_1100             board).

  0x0081         3         0xD**2**2C\                           The board is fully configured
                           b1101_00**1**0_0010_1100              (all 16 devices).

  0x0082         4         0xD2**2**C\                           All the bit in the LED Status
                           b1101_0010_00**1**0_1100              Register are high (the logic
                                                                 AND is '1')

  0x0083         5         0xD22**C\                             The board is in LED monitoring
                           **b1101_0010_0010\_**1100**           mode 12 (0xC, default at power
                                                                 up).

  0x0084         6         0x**F**FFF\                           The board type is not correct
                           b**1111**\_1111_1111_1111             (should always be 0xD =\> the
                                                                 board is not responding
                                                                 correctly or is missing.

  0x0085         7         0xD**E**2C\                           The board has a Global
                           b1101_1**1**10_0010_1100              Clock/SYNC error =\> the board
                                                                 is not using the correct source
                                                                 for the global Clock/SYNC or
                                                                 the SYNC used doesn't respect
                                                                 the correct protocol.

  0x0086         8         0xD**F**2C\                           Beside having a Global
                           b1101_1111_0010_1100                  Clock/SYNC error as the board
                                                                 in slot #7 this board has also
                                                                 an input link error =\> at
                                                                 least one of the 16 input links
                                                                 has a clock/sync error.

  0x0087         9         0xD**E60**\                           The board has a Global
                           b1101\_**1110**\_0**11**0\_**0000**   Clock/SYNC error, is in LED
                                                                 monitoring mode 0 (input links
                                                                 clock and DLL status), the bits
                                                                 in the LED Status registers are
                                                                 all high but there is a change
                                                                 in LED status reported in the
                                                                 LED Error Status History
                                                                 registers. No input link error
                                                                 is reported.

  0x0088         10        0xD**9**CC\                           The board is not fully
                           b1101_100**1**\_1100_1100             configured (READY bit is low).

  ...            ...       ...                                   ...

  0x0093         21        0xD\                                  
                           b1101_0000_0000_0000                  
  -------------- --------- ------------------------------------- -------------------------------

[]{#__RefHeading___Toc35762488 .anchor}Table 3.6, Example of Board
Status Block read back.

Figure 3.4 shows the suggested diagnostic procedure flow. The flow is
based on the information collected from the slow monitoring system; this
data is used to define two levels of error (critical and severe) and one
level of warning (alert). The flow diagram reports for each error and
alert an ordered list containing, in order of precedence, the possible
procedures to be used to investigate the problem. The procedures marked
with an (+) are specified in this document.

A critical error is defined as one that affects the system in disrupting
both the data flow and the system diagnostic. A severe error is one that
just disrupts the data flow and makes the data unreliable. Alerts are
used to warn about the board being accessed, being operated in a mode
which can impair the data flow and when errors are reported form the
input links diagnostic.

![](media/image5.wmf){width="7.591666666666667in" height="7.9375in"}

[]{#__RefHeading___Toc35762489 .anchor}Figure 3.4, Slow Monitoring
Diagnostic Procedure flow

# Procedures

## Board procedures

### Read a board-controller register

+----------------+-----------------------------------------------------+
| Subrack        | Notes                                               |
| Controller     |                                                     |
| command (0x)   |                                                     |
+----------------+-----------------------------------------------------+
| \<             | Read the content of the board controller register   |
| 22\>\<00\>\<of | having address \<offset\> on the mixer board in     |
| fset\>\<slot\> | slot \<slot\>.                                      |
|                |                                                     |
|                | \<22\>: subrack controller command \"read byte from |
|                | backplane\".                                        |
|                |                                                     |
|                | \<00\>: unused byte.                                |
|                |                                                     |
|                | \<offset\>: board register address, from 0x00 to    |
|                | 0x1F.                                               |
|                |                                                     |
|                | \<slot\>: mixer subrack slot number, from 0x02 to   |
|                | 0x15.                                               |
|                |                                                     |
|                | The read data byte will be available in the subrack |
|                | controller General Purpose Memory at location       |
|                | 0x00FA.                                             |
+----------------+-----------------------------------------------------+

[]{#__RefHeading___Toc35762493 .anchor}Table 4.7, Read a Board
Controller register

### Write to a board-controller register

+----------------+-----------------------------------------------------+
| Subrack        | Notes                                               |
| Controller     |                                                     |
| command (0x)   |                                                     |
+----------------+-----------------------------------------------------+
| \<12           | Write the byte \<data\> to the board controller     |
| \>\<data\>\<of | register having address \<offset\> on the mixer     |
| fset\>\<slot\> | board in slot \<slot\>.                             |
|                |                                                     |
|                | \<12\>: subrack controller command \"write byte to  |
|                | backplane\".                                        |
|                |                                                     |
|                | \<data\>: data byte to be written.                  |
|                |                                                     |
|                | \<offset\>: board register address, normal          |
|                | addressing range from 0x00 to 0x1F.                 |
|                |                                                     |
|                | The most significative three bit of the \<offset\>  |
|                | byte are using for broadcasting control (see Figure |
|                | 4.5).                                               |
|                |                                                     |
|                | \<slot\>: mixer subrack slot number, from 0x02 to   |
|                | 0x15.                                               |
+----------------+-----------------------------------------------------+

[]{#__RefHeading___Toc35762495 .anchor}Table 4.8, Write to a Board
Controller register

The write operation can also be targeted to a particular set of mixer
boards using the broadcasting control (see Figure 4.5).

![](media/image6.wmf){width="4.364583333333333in"
height="1.4895833333333333in"}

[]{#__RefHeading___Toc35762496 .anchor}Figure 4.5, broadcast control for
writes operations

### Board devices access structure

![](media/image7.wmf){width="4.760416666666667in" height="4.21875in"}

[]{#__RefHeading___Toc35762498 .anchor}Figure 4.6, Board device access
structure

### Read device registers

+---+-------------------+---------------------------------------------+
| S | Subrack           | Notes                                       |
| t | Controller\       |                                             |
| e | command (0x)      |                                             |
| p |                   |                                             |
| # |                   |                                             |
+---+-------------------+---------------------------------------------+
| 1 | \<22\>\<0         | Read the content of the Mode of Operation   |
|   | 0\>\<04\>\<slot\> | register.                                   |
|   |                   |                                             |
|   |                   | \<22\>: subrack controller command \"read   |
|   |                   | byte from backplane\".                      |
|   |                   |                                             |
|   |                   | \<00\>: unused byte.                        |
|   |                   |                                             |
|   |                   | \<04\>: \<offset\> byte, Mode of Operation  |
|   |                   | register address.                           |
|   |                   |                                             |
|   |                   | \<slot\>: mixer subrack slot number, from   |
|   |                   | 0x02 to 0x15.                               |
|   |                   |                                             |
|   |                   | The read data byte \<MOreg_data\> will be   |
|   |                   | available in the subrack controller General |
|   |                   | Purpose Memory at location 0x00FA.          |
+---+-------------------+---------------------------------------------+
| 2 | \<12\>\<data_     | Enable Device Access Registers (default is  |
|   | a\>\<04\>\<slot\> | disabled) in the Mode of Operation          |
|   |                   | register.                                   |
|   |                   |                                             |
|   |                   | \<12\>: subrack controller command \"write  |
|   |                   | byte to backplane\".                        |
|   |                   |                                             |
|   |                   | \<data_a\>: \<MOreg_data\> OR \<04\>.\      |
|   |                   | Is the logic OR of the byte obtained from   |
|   |                   | the previous operation (\<MOreg_data\>) and |
|   |                   | the mask used to enable the Device Access   |
|   |                   | Registers (\<04\>).                         |
|   |                   |                                             |
|   |                   | \<04\>: \<offset\> byte, Mode of Operation  |
|   |                   | register address. The most significative    |
|   |                   | three bit of the \<offset\> byte can be     |
|   |                   | used for broadcasting control (see Figure   |
|   |                   | 4.5).                                       |
|   |                   |                                             |
|   |                   | \<slot\>: mixer subrack slot number, from   |
|   |                   | 0x02 to 0x15.                               |
+---+-------------------+---------------------------------------------+
| 3 | \<12\>\<0x0,devic | Point the Device Status/Control Register to |
|   | e\>\<01\>\<slot\> | a specific device. No masking is required.  |
|   |                   |                                             |
|   |                   | \<12\>: subrack controller command \"write  |
|   |                   | byte to backplane\".                        |
|   |                   |                                             |
|   |                   | \<0x0,device\>: 0x0 followed by 4 bit       |
|   |                   | device address, from 0x00 to 0x0F.          |
|   |                   |                                             |
|   |                   | \<01\>: \<offset\> byte, Device             |
|   |                   | Status/Control register address. The most   |
|   |                   | significative three bit of the \<offset\>   |
|   |                   | byte can be used for broadcasting control   |
|   |                   | (see Figure 4.5).                           |
|   |                   |                                             |
|   |                   | \<slot\>: mixer subrack slot number, from   |
|   |                   | 0x02 to 0x15.                               |
+---+-------------------+---------------------------------------------+
| 4 | \<12\>\<registe   | Point the Device Access Address Register to |
|   | r\>\<07\>\<slot\> | a specific register inside the device. No   |
|   |                   | masking is required.                        |
|   |                   |                                             |
|   |                   | \<12\>: subrack controller command \"write  |
|   |                   | byte to backplane\".                        |
|   |                   |                                             |
|   |                   | \<register\>: Device's internal register    |
|   |                   | address.                                    |
|   |                   |                                             |
|   |                   | \<07\>: \<offset\> byte, Device Access      |
|   |                   | Address register address. The most          |
|   |                   | significative three bit of the \<offset\>   |
|   |                   | byte can be used for broadcasting control   |
|   |                   | (see Figure 4.5).                           |
|   |                   |                                             |
|   |                   | \<slot\>: mixer subrack slot number, from   |
|   |                   | 0x02 to 0x15.                               |
+---+-------------------+---------------------------------------------+
| 5 | \<22\>\<0         | Read the content of the Device Access Data  |
|   | 0\>\<08\>\<slot\> | register.                                   |
|   |                   |                                             |
|   |                   | \<22\>: subrack controller command \"read   |
|   |                   | byte from backplane\".                      |
|   |                   |                                             |
|   |                   | \<00\>: unused byte.                        |
|   |                   |                                             |
|   |                   | \<08\>: \<offset\> byte, Device Access Data |
|   |                   | address.\                                   |
|   |                   | If broadcasting control was used in the     |
|   |                   | preceding writing operations this step      |
|   |                   | should be repeated for each of the boards   |
|   |                   | belonging the subset of boards accessed by  |
|   |                   | the broadcasting.                           |
|   |                   |                                             |
|   |                   | \<slot\>: mixer subrack slot number, from   |
|   |                   | 0x02 to 0x15.                               |
|   |                   |                                             |
|   |                   | The read data byte \<devreg_data\> will be  |
|   |                   | available in the subrack controller General |
|   |                   | Purpose Memory at location 0x00FA.          |
+---+-------------------+---------------------------------------------+
| 7 | \<12\>\<data_     | Disable Device Access Registers in the Mode |
|   | c\>\<04\>\<slot\> | of Operation register.                      |
|   |                   |                                             |
|   |                   | \<12\>: subrack controller command \"write  |
|   |                   | byte to backplane\".                        |
|   |                   |                                             |
|   |                   | \<data_c\>: \<MOreg_data\> AND              |
|   |                   | \<bxxxxx0xx\>.\                             |
|   |                   | Is the masking of the byte obtained from    |
|   |                   | step#1 (\<MOreg_data\>) and the mask used   |
|   |                   | to disable the Device Access registers      |
|   |                   | (\<bxxxxx0xx\>).                            |
|   |                   |                                             |
|   |                   | \<04\>: \<offset\> byte, Mode of Operation  |
|   |                   | register address. The most significative    |
|   |                   | three bit of the \<offset\> byte can be     |
|   |                   | used for broadcasting control (see Figure   |
|   |                   | 4.5).                                       |
|   |                   |                                             |
|   |                   | \<slot\>: mixer subrack slot number, from   |
|   |                   | 0x02 to 0x15.                               |
+---+-------------------+---------------------------------------------+

Table 4.9, Read from device registers

![](media/image8.wmf){width="4.822916666666667in"
height="4.114583333333333in"}

[]{#__RefHeading___Toc35762500 .anchor}Figure 4.7, Read from device
registers

### Write to device registers

The write operation follows all the steps of the read operation. The
difference is that the result of the read is OR-ed with the desired mask
and then used in one more step to write back the desired content to the
device register.

+---+------------------+----------------------------------------------+
| S | Subrack          | Notes                                        |
| t | Controller       |                                              |
| e | command (0x)     |                                              |
| p |                  |                                              |
| # |                  |                                              |
+===+==================+==============================================+
| 1 | \<22\>\<00       | Read the content of the Mode of Operation    |
|   | \>\<04\>\<slot\> | register.                                    |
|   |                  |                                              |
|   |                  | \<22\>: subrack controller command \"read    |
|   |                  | byte from backplane\".                       |
|   |                  |                                              |
|   |                  | \<00\>: unused byte.                         |
|   |                  |                                              |
|   |                  | \<04\>: \<offset\> byte, Mode of Operation   |
|   |                  | register address.                            |
|   |                  |                                              |
|   |                  | \<slot\>: mixer subrack slot number, from    |
|   |                  | 0x02 to 0x15.                                |
|   |                  |                                              |
|   |                  | The read data byte \<rdbk_dataA\> will be    |
|   |                  | available in the subrack controller General  |
|   |                  | Purpose Memory at location 0x00FA.           |
+---+------------------+----------------------------------------------+
| 2 | \<12\>\<data_a   | Enable Device Access Registers (default is   |
|   | \>\<04\>\<slot\> | disabled) in the Mode of Operation register. |
|   |                  |                                              |
|   |                  | \<12\>: subrack controller command \"write   |
|   |                  | byte to backplane\".                         |
|   |                  |                                              |
|   |                  | \<data_a\>: \<rdbk_dataA\> OR \<04\>.\       |
|   |                  | Is the logic OR of the byte obtained from    |
|   |                  | the previous step (\<rdbk_dataA\>) and the   |
|   |                  | mask used to enable the Device Access        |
|   |                  | registers (\<04\>).                          |
|   |                  |                                              |
|   |                  | \<04\>: \<offset\> byte, Mode of Operation   |
|   |                  | register address. The most significative     |
|   |                  | three bit of the \<offset\> byte can be used |
|   |                  | for broadcasting control (see Figure 4.5).   |
|   |                  |                                              |
|   |                  | \<slot\>: mixer subrack slot number, from    |
|   |                  | 0x02 to 0x15.                                |
+---+------------------+----------------------------------------------+
| 3 | \<               | Point the Device Status/Control Register to  |
|   | 12\>\<0x0,device | a specific device. No masking is required.   |
|   | \>\<01\>\<slot\> |                                              |
|   |                  | \<12\>: subrack controller command \"write   |
|   |                  | byte to backplane\".                         |
|   |                  |                                              |
|   |                  | \<0x0,device\>: 0x0 followed by 4 bit device |
|   |                  | address, from 0x00 to 0x0F.                  |
|   |                  |                                              |
|   |                  | \<01\>: \<offset\> byte, Device              |
|   |                  | Status/Control register address. The most    |
|   |                  | significative three bit of the \<offset\>    |
|   |                  | byte can be used for broadcasting control    |
|   |                  | (see Figure 4.5).                            |
|   |                  |                                              |
|   |                  | \<slot\>: mixer subrack slot number, from    |
|   |                  | 0x02 to 0x15.                                |
+---+------------------+----------------------------------------------+
| 4 | \<12\>\<register | Point the Device Access Address Register to  |
|   | \>\<07\>\<slot\> | a specific register inside the device. No    |
|   |                  | masking is required.                         |
|   |                  |                                              |
|   |                  | \<12\>: subrack controller command \"write   |
|   |                  | byte to backplane\".                         |
|   |                  |                                              |
|   |                  | \<register\>: Device's internal register     |
|   |                  | address.                                     |
|   |                  |                                              |
|   |                  | \<07\>: \<offset\> byte, Device Access       |
|   |                  | Address register address. The most           |
|   |                  | significative three bit of the \<offset\>    |
|   |                  | byte can be used for broadcasting control    |
|   |                  | (see Figure 4.5).                            |
|   |                  |                                              |
|   |                  | \<slot\>: mixer subrack slot number, from    |
|   |                  | 0x02 to 0x15.                                |
+---+------------------+----------------------------------------------+
| 5 | \<22\>\<00       | Read the content of the Device Access Data   |
|   | \>\<08\>\<slot\> | register.                                    |
|   |                  |                                              |
|   |                  | \<22\>: subrack controller command \"read    |
|   |                  | byte from backplane\".                       |
|   |                  |                                              |
|   |                  | \<00\>: unused byte.                         |
|   |                  |                                              |
|   |                  | \<08\>: \<offset\> byte, Device Access Data  |
|   |                  | address.\                                    |
|   |                  | If broadcasting control was used in the      |
|   |                  | preceding writing operations this step       |
|   |                  | should be repeated for each of the boards    |
|   |                  | belonging the subset of boards accessed by   |
|   |                  | the broadcasting.                            |
|   |                  |                                              |
|   |                  | \<slot\>: mixer subrack slot number, from    |
|   |                  | 0x02 to 0x15.                                |
|   |                  |                                              |
|   |                  | The read data byte \< devreg_data \> will be |
|   |                  | available in the subrack controller General  |
|   |                  | Purpose Memory at location 0x00FA.           |
+---+------------------+----------------------------------------------+
| 6 | \<12\>\<data_b   | Write to the Device Access Data register.    |
|   | \>\<08\>\<slot\> |                                              |
|   |                  | \<12\>: subrack controller command \"write   |
|   |                  | byte to backplane\".                         |
|   |                  |                                              |
|   |                  | \<data_b\>: \<devreg_data_new\>.\            |
|   |                  | devreg_data_new is the byte obtained from    |
|   |                  | the previous operation (\<devreg_data\>)     |
|   |                  | after having applied the desired changes.    |
|   |                  |                                              |
|   |                  | \<08\>: \<offset\> byte, Device Access Data  |
|   |                  | register address. The most significative     |
|   |                  | three bit of the \<offset\> byte can be used |
|   |                  | for broadcasting control (see Figure 4.5).   |
|   |                  |                                              |
|   |                  | \<slot\>: mixer subrack slot number, from    |
|   |                  | 0x02 to 0x15.                                |
+---+------------------+----------------------------------------------+
| 7 | \<12\>\<data_c   | Disable Device Access Registers in the Mode  |
|   | \>\<04\>\<slot\> | of Operation register.                       |
|   |                  |                                              |
|   |                  | \<12\>: subrack controller command \"write   |
|   |                  | byte to backplane\".                         |
|   |                  |                                              |
|   |                  | \<data_c\>: \<rdbk_dataA\> AND               |
|   |                  | \<bxxxxx0xx\>.\                              |
|   |                  | Is the masking of the byte obtained from     |
|   |                  | step#1 (\<rdbk_dataA\>) and the mask used to |
|   |                  | disable the Device Access registers          |
|   |                  | (\<bxxxxx0xx\>).                             |
|   |                  |                                              |
|   |                  | \<04\>: \<offset\> byte, Mode of Operation   |
|   |                  | register address. The most significative     |
|   |                  | three bit of the \<offset\> byte can be used |
|   |                  | for broadcasting control (see Figure 4.5).   |
|   |                  |                                              |
|   |                  | \<slot\>: mixer subrack slot number, from    |
|   |                  | 0x02 to 0x15.                                |
+---+------------------+----------------------------------------------+

Table 4.10, Write to device registers

![](media/image9.wmf){width="4.752083333333333in"
height="4.752083333333333in"}

[]{#__RefHeading___Toc35762502 .anchor}Figure 4.8, Write to device
registers

### Board reset

This procedure will reset to the default value/state all the registers
and state machines on the mixer board. Due to the fact that some state
machines may take several clock cycles to go to normal operation not all
the history information after a board reset is reliable. After a reset
it is suggested to reset history information (procedure described in
paragraph 4.1.13). When a master board is reset the operation should be
followed by the reset of all the slave boards in the same supersector.
Paragraph 4.5 describe the procedure to reset the mixer system.

+---+-------------------------+----------------------------------------+
| S | Subrack Controller      | Notes                                  |
| t | command (0x)            |                                        |
| e |                         |                                        |
| p |                         |                                        |
| # |                         |                                        |
+---+-------------------------+----------------------------------------+
| 1 | \<1                     | \<12\>: subrack controller command     |
|   | 2\>\<02\>\<00\>\<slot\> | \"write byte to backplane\".           |
|   |                         |                                        |
|   |                         | \<02\>: \<data\> byte, set high the    |
|   |                         | reset bit in the board status/control  |
|   |                         | register.                              |
|   |                         |                                        |
|   |                         | \<00\>: \<offset\> byte, board         |
|   |                         | status/control register address. The   |
|   |                         | most significative three bit of the    |
|   |                         | \<offset\> byte can be used for        |
|   |                         | broadcasting control (see Figure 4.5). |
|   |                         |                                        |
|   |                         | \<slot\>: mixer subrack slot number,   |
|   |                         | from 0x02 to 0x15.                     |
+---+-------------------------+----------------------------------------+
| 2 | \<1                     | \<12\>: subrack controller command     |
|   | 2\>\<00\>\<00\>\<slot\> | \"write byte to backplane\".           |
|   |                         |                                        |
|   |                         | \<00\>: \<data\> byte, set low the     |
|   |                         | reset bit in the board status/control  |
|   |                         | register.                              |
|   |                         |                                        |
|   |                         | \<00\>: \<offset\> byte, board         |
|   |                         | status/control register address. The   |
|   |                         | most significative three bit of the    |
|   |                         | \<offset\> byte can be used for        |
|   |                         | broadcasting control (see Figure 4.5). |
|   |                         |                                        |
|   |                         | \<slot\>: mixer subrack slot number,   |
|   |                         | from 0x02 to 0x15.                     |
+---+-------------------------+----------------------------------------+

[]{#__RefHeading___Toc35762504 .anchor}Table 4.11, Mixer board reset
command sequence

![](media/image10.wmf){width="4.302083333333333in"
height="1.2604166666666667in"}

[]{#__RefHeading___Toc35762505 .anchor}Figure 4.9, Mixer board reset

### Reset Board Controller History Information

This procedure will reset the history information on the board
controller FPGA.

![](media/image11.wmf){width="2.90625in" height="0.59375in"}

[]{#__RefHeading___Toc35762507 .anchor}Figure 4.10, Reset board
controller history information

### Read Mixer Board configuration status and device\'s firmware ID

![](media/image12.wmf){width="4.822916666666667in" height="2.03125in"}

[]{#__RefHeading___Toc35762509 .anchor}Figure 4.11, Read configuration
status and device\'s firmware ID

### Erase Mixer Board Configuration

![](media/image13.wmf){width="5.0in" height="3.40625in"}

[]{#__RefHeading___Toc35762511 .anchor}Figure 4.12, Erase mixer board
configuration

### Configure mixer board

![](media/image14.wmf){width="5.958333333333333in" height="2.84375in"}

[]{#__RefHeading___Toc35762513 .anchor}Figure 4.13, configure mixer
board

Step 1 is described in paragraph 2.1.1. Step 4 is described in paragraph
4.1.8.

  -------- --------- ------------------- ------------- ------------- ------------- -------------
  Device   Device    Schematic device#,  Mixer#1 files Mixer#2 files Mixer#3 files Mixer#4 files
  \#       Type      device name                                                   

  0        Spartan   U2, DFE1 YP         0200_PC.bin   0300_PC.bin   0400_PC.bin   0500_PC.bin
           XL        (Outlink 5).                                                  

  1        Spartan   U1, DFE1 RB         0201_PC.bin   0301_PC.bin   0401_PC.bin   0501_PC.bin
           XL        (Outlink 6).                                                  

  2        Spartan   U10, DFE1 OG        0202_PC.bin   0302_PC.bin   0402_PC.bin   0502_PC.bin
           XL        (Outlink 4).                                                  

  3        Spartan   U11, DFE0 RB        0203_PC.bin   0303_PC.bin   0403_PC.bin   0503_PC.bin
           XL        (Outlink 3).                                                  

  4        Spartan   U19, DFE0 OG        0204_PC.bin   0304_PC.bin   0404_PC.bin   0504_PC.bin
           XL        (Outlink 1).                                                  

  5        Spartan   U18, DFE0 YP        0205_PC.bin   0305_PC.bin   0405_PC.bin   0505_PC.bin
           XL        (Outlink 2).                                                  

  6        Virtex    U31, LINK_IN 13-15. 0206_PC.bin   0306_PC.bin   0406_PC.bin   0506_PC.bin

  7        Virtex    U45, LINK_IN 4-6.   0207_PC.bin   0307_PC.bin   0407_PC.bin   0507_PC.bin

  8        Virtex    U46, LINK_IN 1-3.   0208_PC.bin   0308_PC.bin   0408_PC.bin   0508_PC.bin

  9        Virtex    U32, LINK_IN 10-12. 0209_PC.bin   0309_PC.bin   0409_PC.bin   0509_PC.bin

  10       Virtex    U47, LINK_IN 0.     020A_PC.bin   030A_PC.bin   040A_PC.bin   050A_PC.bin

  11       Virtex    U48, Backplane Left 020B_PC.bin   030B_PC.bin   040B_PC.bin   050B_PC.bin
                     Driver.                                                       

  12       Virtex    U33, LINK_IN 7-9.   020C_PC.bin   030C_PC.bin   040C_PC.bin   050C_PC.bin

  13       Virtex    U12, Backplane DFE0 020D_PC.bin   030D_PC.bin   040D_PC.bin   050D_PC.bin
                     receiver.                                                     

  14       Virtex    U5, Backplane DFE1  020E_PC.bin   030E_PC.bin   040E_PC.bin   050E_PC.bin
                     receiver.                                                     

  15       Virtex    U6, Backplane Right 020F_PC.bin   030F_PC.bin   040F_PC.bin   050F_PC.bin
                     Driver.                                                       
  -------- --------- ------------------- ------------- ------------- ------------- -------------

[]{#__RefHeading___Toc35762514 .anchor}Table 4.12, Configuration Files
denomination.

  ----------------------- -----------------------------------------------
  Mixer#                  Subrack slots

  1                       **02**, 06, 10, 14, 18

  2                       **03**, 07, 11, 15, 19

  3                       **04**, 08, 12, 16, 20

  4                       **05**, 09, 13, 17, 21
  ----------------------- -----------------------------------------------

[]{#__RefHeading___Toc35762515 .anchor}Table 4.13, Mixer# and Subrack
slot#.

###  Read board controller firmware revision date and board serial number

![](media/image15.wmf){width="4.364583333333333in"
height="2.7916666666666665in"}

[]{#__RefHeading___Toc35762517 .anchor}Figure 4.14, Read board
controller firmware revision date and board serial number

### Read/Write test

![](media/image16.wmf){width="4.833333333333333in" height="4.25in"}

[]{#__RefHeading___Toc35762519 .anchor}Figure 4.15, Read/write test

### Reset Board History Information

![](media/image17.wmf){width="2.9270833333333335in"
height="2.6666666666666665in"}The reset of the history information on a
mixer board follow few steps to operate on the several devices on the
board. The procedure can be generalized to the mixer system or to a
subset of it using broadcasting of the commands.

[]{#__RefHeading___Toc35762521 .anchor}Figure 4.16, Reset Board History
Information

Step 1 is described in paragraph 4.1.7. Step 2 is described in paragraph
4.2.3.

Step 3 is described in paragraph 4.4.7. Step 4 is described in paragraph
4.3.1.

### Taking a snapshot of Mixer Board status

Taking a snapshot of mixer board status consists in reading all the
board controller registers and all of the device registers. This can be
done using the procedures described previously in Paragraphs 4.1.1 (for
step 1 in Figure 4.17) and 4.1.4 .

![](media/image18.wmf){width="4.802083333333333in"
height="6.885416666666667in"}

[]{#__RefHeading___Toc35762523 .anchor}Figure 4.17, Mixer Board status
snapshot

The read of the output links FIFOs is not included in the procedure. One
exception is the procedure to read the content of the Device
Status/Control register and the Device Firmware ID register. The content
of these registers reflect the status/information of the device pointed
by the four less significative (device select) bits of the Device
Status/Control register.

It is suggested to erase all the history information after each snapshot
(step 9 in Figure 4.17, the procedure is specified in paragraph 4.1.13).
At the next snapshot this will provide useful insides on what happened
on the board (i.e. loss of input links
clock/frame-marker/frame-synchronization, etc.).

##  Input Links procedures

### Read input links error status

![](media/image19.wmf){width="4.447916666666667in" height="4.46875in"}

[]{#__RefHeading___Toc35762526 .anchor}Figure 4.18, Read input links
error status

### Read input links status

![](media/image20.wmf){width="6.875in" height="8.302083333333334in"}

[]{#__RefHeading___Toc35762528 .anchor}Figure 4.19, read input links
status

### Reset Mixer Board input links status history

Steps 4, 5, 6 are used to reset the control bits history information
stored in the Control Bits Status registers.

![](media/image21.wmf){width="6.875in" height="4.020833333333333in"}

[]{#__RefHeading___Toc35762530 .anchor}Figure 4.20, Reset input links
status history

### Input Links Control

![](media/image22.wmf){width="5.90625in" height="4.791666666666667in"}

[]{#__RefHeading___Toc35762532 .anchor}Figure 4.21, Input Links control
procedure.

![](media/image23.wmf){width="3.8645833333333335in"
height="2.5104166666666665in"}

[]{#__RefHeading___Toc35762533 .anchor}Figure 4.22, Input Links Control
register

### Input Links Control bits masking 

![](media/image24.wmf){width="2.5520833333333335in"
height="1.7916666666666667in"}

[]{#__RefHeading___Toc35762535
.anchor}![](media/image25.wmf){width="6.864583333333333in"
height="6.25in"}Figure 4.23, Input Link Control Bits Mask Register

[]{#__RefHeading___Toc35762536 .anchor}Figure 4.24, Command bits
generation, timing and denomination.

+----------------+-----------------------------------------------------+
| command (0x)   | Notes                                               |
+----------------+-----------------------------------------------------+
| \<12\>\<17     | Write 0x17 to the Mode of Operation Register of     |
| \>\<84\>\<02\> | [all]{.underline} mixer boards in the subrack       |
|                | (subrack broadcast) to enable Device Access         |
|                | Registers.                                          |
+----------------+-----------------------------------------------------+
| \<12\>\<0A     | Write byte 0x0A to the Device/Status Control        |
| \>\<81\>\<02\> | register in [all]{.underline} mixer boards (subrack |
|                | broadcast). Sets the device select pointer to       |
|                | device 0x0A.                                        |
+----------------+-----------------------------------------------------+
| \<12           | Write byte \<reg_addr\> to the Device Access        |
| \>\<reg_addr\> | Address register (address \<07\>) of the mixer      |
| \<07\>\<slot\> | board in slot \<slot\>. This set the Device Access  |
|                | Address register to point inside device 0x0A to the |
|                | register having address \<regaddr\>.\               |
|                | \<regaddr\> depends on the input link on which the  |
|                | control bits mask is to be modified:                |
|                |                                                     |
|                | \<40\>: Link#0 Control Bits Masking register\       |
|                | \<41\>: Link#1 Control Bits Masking register\       |
|                | \<42\>: Link#2 Control Bits Masking register\       |
|                | \<43\>: Link#3 Control Bits Masking register\       |
|                | \<44\>: Link#4 Control Bits Masking register\       |
|                | \<45\>: Link#5 Control Bits Masking register\       |
|                | \<46\>: Link#6 Control Bits Masking register\       |
|                | \<47\>: Link#7 Control Bits Masking register\       |
|                | \<48\>: Link#8 Control Bits Masking register\       |
|                | \<49\>: Link#9 Control Bits Masking register\       |
|                | \<4A\>: Link#10 Control Bits Masking register\      |
|                | \<4B\>: Link#11 Control Bits Masking register\      |
|                | \<4C\>: Link#12 Control Bits Masking register\      |
|                | \<4D\>: Link#13 Control Bits Masking register\      |
|                | \<4E\>: Link#14 Control Bits Masking register\      |
|                | \<4F\>: Link#15 Control Bits Masking register       |
|                |                                                     |
|                | \<07\>: \<offset\> byte: board Device Access        |
|                | Address register address. The most significative    |
|                | three bits of the \<offset\> byte can be used for   |
|                | broadcasting control (see Figure 4.5).              |
|                |                                                     |
|                | \<slot\>: mixer subrack slot number, from 0x02 to   |
|                | 0x15.                                               |
+----------------+-----------------------------------------------------+
| \<1            | Write \<cb_mask\> to the Device Access Data         |
| 2\>\<cb_mask\> | register of the mixer board in slot \<slot\>. The   |
| \<08\>\<slot\> | byte \<cb_mask\> will be written to the register    |
|                | pointed by \<reg_addr\> in the device 0x0A. This    |
|                | will mask the control bits on input link specified  |
|                | by \<reg_addr\>.                                    |
|                |                                                     |
|                | \<cb_mask\> is the control bit mask and should be   |
|                | chosen depending on the control bits to be asked    |
|                | (see Figure 4.23 and Figure 4.24).\                 |
|                | \<00\>: masking disabled (equivalent to no          |
|                | masking)\                                           |
|                | \<FF\>: masking enabled, no bit is masked\          |
|                | \<01\>: all control bits are masked\                |
|                | \<DF\>: only control bit at time slot 5 (L1 Accept) |
|                | is masked.                                          |
|                |                                                     |
|                | \<08\>: \<offset\> byte: board Device Access Data   |
|                | register address. The most significative three bits |
|                | of the \<offset\> byte can be used for broadcasting |
|                | control (see Figure 4.5).                           |
|                |                                                     |
|                | \<slot\>: mixer subrack slot number, from 0x02 to   |
|                | 0x15.                                               |
+----------------+-----------------------------------------------------+
|                | Repeat the last two commands as needed to mask the  |
|                | control bits on all the desired links.              |
+----------------+-----------------------------------------------------+
| \<12\>\<13     | Write 0x13 to the Mode of Operation Register of     |
| \>\<84\>\<02\> | [all]{.underline} mixer boards in the subrack       |
|                | (subrack broadcast) to disable Device Access        |
|                | Registers.                                          |
+----------------+-----------------------------------------------------+
| \<A1\>\<00\>   | End of list command. Stop the subrack controller    |
|                | execution of the commands in the command buffer.    |
+----------------+-----------------------------------------------------+

[]{#__RefHeading___Toc35762537 .anchor}Table 4.14, Example of command
sequence to mask control bits on the input links.

![](media/image26.wmf){width="4.024305555555555in"
height="4.815972222222222in"}

[]{#__RefHeading___Toc35762538 .anchor}Figure 4.25, input links control
bits masking

### Monitoring mode 7 masking

![](media/image27.wmf){width="5.759722222222222in"
height="4.808333333333334in"}

[]{#__RefHeading___Toc35762540 .anchor}Figure 4.26, monitoring mode 7
masking

### Input Links Control bits status

![](media/image28.wmf){width="6.875in" height="3.65625in"}

[]{#__RefHeading___Toc35762542 .anchor}Figure 4.27, read input links
control bits status

### Embedded Command Bits Status

This procedure will allow to verify the status of the Embedded Command
Bits (see Figure 4.24).

![](media/image29.wmf){width="5.552083333333333in" height="5.46875in"}

[]{#__RefHeading___Toc35762544 .anchor}Figure 4.28, Read Embedded
Command Bits status.

## Backplane Devices Procedures

### Reset Backplane Devices History

![](media/image30.wmf){width="5.831944444444445in"
height="4.127777777777778in"}

[]{#__RefHeading___Toc35762547 .anchor}Figure 4.29, reset backplane
devices history.

### Readback Mixer Board clock/SYNC status

![](media/image31.wmf){width="5.322916666666667in" height="5.53125in"}

[]{#__RefHeading___Toc35762549 .anchor}Figure 4.30, Read Clock/SYNC
Status and History.

### Reset Mixer Board clock/SYNC status history

The procedure to reset the clock and SYNC history on the mixer board is
the same specified to reset history information on backplane devices
(paragraph 4.3.1) applied to the Backplane right driver device (board
controller).

## Output links devices procedures

### Output link FIFO read

![](media/image32.wmf){width="4.697916666666667in"
height="5.510416666666667in"}

[]{#__RefHeading___Toc35762553 .anchor}Figure 4.31, Read content of an
output link FIFO.

### Output link FIFO Write

![](media/image33.wmf){width="4.75in" height="6.291666666666667in"}

[]{#__RefHeading___Toc35762555 .anchor}Figure 4.32, Write content of an
output link FIFO.

Step 8 is specified in paragraph 4.4.1.

### Output Link FIFO reset

Consist in the same procedure described in paragraph 4.4.2 for the
output link FIFO write using \<location_data\> = 0x00.

### Output link FIFO Configuration

![](media/image34.wmf){width="5.415972222222222in"
height="5.511805555555555in"}

[]{#__RefHeading___Toc35762558 .anchor}Figure 4.33, Output link FIFO
configuration.

### Triggering of Output Links FIFO 

![](media/image35.wmf){width="2.8645833333333335in"
height="1.3333333333333333in"}

[]{#__RefHeading___Toc35762560 .anchor}Figure 4.34, Triggering of Output
Link FIFO.

### Use of Output Links FIFOs

![](media/image36.wmf){width="4.166666666666667in"
height="3.3645833333333335in"}

[]{#__RefHeading___Toc35762562 .anchor}Figure 4.35, Use of Output Links
FIFOs.

Step 1 is specified in paragraph 4.4.4. Step 2 and 3 are specified in
paragraphs 4.4.2 and 4.4.3.

Step 4 is specified in paragraph 4.4.5. Step 5 is specified in paragraph
4.4.1.

### Reset Output Links History Information

![](media/image37.wmf){width="5.336111111111111in"
height="4.111805555555556in"}

[]{#__RefHeading___Toc35762564 .anchor}Figure 4.36, Reset output links
history information

### Output links Control Bits Masking

+-----------------+----------------------------------------------------+
| command (0x)    | Notes                                              |
+-----------------+----------------------------------------------------+
| \<12\>\<1       | Write 0x17 to the Mode of Operation Register of    |
| 7\>\<84\>\<02\> | [all]{.underline} mixer boards in the subrack      |
|                 | (subrack broadcast) to enable Device Access        |
|                 | Registers.                                         |
+-----------------+----------------------------------------------------+
| \<              | Write byte \<0x0, device\> to the Device/Status    |
| 12\>\<0x0,devic | Control register in [all]{.underline} mixer boards |
| e\>\<81\>\<02\> | (subrack broadcast). Sets the device select        |
|                 | pointer to a particular device. There are 4 output |
|                 | links carrying control bits:                       |
|                 |                                                    |
|                 | Output link 02 (orange) is on device 0x4 (DFE0     |
|                 | Green Orange FPGA)                                 |
|                 |                                                    |
|                 | Output link 05 (blue) is on device 0x3 (DFE0 Blue  |
|                 | red FPGA)                                          |
|                 |                                                    |
|                 | Output link 12 (orange) is on device 0x2 (DFE1     |
|                 | Green Orange FPGA)                                 |
|                 |                                                    |
|                 | Output link 15 (blue) is on device 0x1 (DFE1 Blue  |
|                 | red FPGA)                                          |
+-----------------+----------------------------------------------------+
| \<              | Write byte \<reg_addr\> to the Device Access       |
| 12\>\<reg_addr\ | Address register (address \<07\>) of the mixer     |
| >\<07\>\<slot\> | board in slot \<slot\>. This set the Device Access |
|                 | Address register to point inside the chosen device |
|                 | to the register having address \<regaddr\>.\       |
|                 | \<regaddr\> depends on the ounput link on which    |
|                 | the control bits mask is to be modified:           |
|                 |                                                    |
|                 | \<B2\>: Link#02 Embedded Command Bits Mask         |
|                 | register\                                          |
|                 | \<A2\>: Link#05 Embedded Command Bits Mask         |
|                 | register\                                          |
|                 | \<A2\>: Link#12 Embedded Command Bits Mask         |
|                 | register\                                          |
|                 | \<B2\>: Link#15 Embedded Command Bits Mask         |
|                 | register                                           |
|                 |                                                    |
|                 | \<07\>: \<offset\> byte: board Device Access       |
|                 | Address register address. The most significative   |
|                 | three bits of the \<offset\> byte can be used for  |
|                 | broadcasting control (see Figure 4.5).             |
|                 |                                                    |
|                 | \<slot\>: mixer subrack slot number, from 0x02 to  |
|                 | 0x15.                                              |
+-----------------+----------------------------------------------------+
| \               | Write \<cb_mask\> to the Device Access Data        |
| <12\>\<cb_mask\ | register of the mixer board in slot \<slot\>. The  |
| >\<08\>\<slot\> | byte \<cb_mask\> will be written to the register   |
|                 | pointed by \<reg_addr\> in the device \<device\>.  |
|                 | This will mask the control bits on output link     |
|                 | specified by \<reg_addr\>.                         |
|                 |                                                    |
|                 | \<cb_mask\> is the control bit mask and should be  |
|                 | chosen depending on the control bits to be asked   |
|                 | (see Figure 4.23 and Figure 4.24).\                |
|                 | \<00\>: masking disabled (equivalent to no         |
|                 | masking)\                                          |
|                 | \<FF\>: masking enabled, no bit is masked\         |
|                 | \<01\>: all control bits are masked\               |
|                 | \<DF\>: only control bit at time slot 5 (L1        |
|                 | Accept) is masked.                                 |
|                 |                                                    |
|                 | \<08\>: \<offset\> byte: board Device Access Data  |
|                 | register address. The most significative three     |
|                 | bits of the \<offset\> byte can be used for        |
|                 | broadcasting control (see Figure 4.5).             |
|                 |                                                    |
|                 | \<slot\>: mixer subrack slot number, from 0x02 to  |
|                 | 0x15.                                              |
+-----------------+----------------------------------------------------+
|                 | Repeat the last three commands as needed to mask   |
|                 | the control bits on all the desired links.         |
+-----------------+----------------------------------------------------+
| \<12\>\<1       | Write 0x13 to the Mode of Operation Register of    |
| 3\>\<84\>\<02\> | [all]{.underline} mixer boards in the subrack      |
|                 | (subrack broadcast) to disable Device Access       |
|                 | Registers.                                         |
+-----------------+----------------------------------------------------+
| \<A1\>\<00\>    | End of list command. Stop the subrack controller   |
|                 | execution of the commands in the command buffer.   |
+-----------------+----------------------------------------------------+

[]{#__RefHeading___Toc35762566 .anchor}Table 4.15, Example of command
sequence to mask control bits on the output links.

![](media/image38.wmf){width="6.083333333333333in"
height="4.822916666666667in"}

[]{#__RefHeading___Toc35762567 .anchor}Figure 4.37, Output links control
bits masking.

### Output Links Control

![](media/image39.wmf){width="5.34375in" height="4.791666666666667in"}

[]{#__RefHeading___Toc35762569 .anchor}Figure 4.38, Output links control

To be noted that the output links LVDS transmitters clock can be
disabled for all the output links at once using the Board Controller's
Mode of Operation register.

## System procedures

### Mixer System reset

![](media/image40.wmf){width="6.322916666666667in"
height="2.6979166666666665in"}

[]{#__RefHeading___Toc35762572 .anchor}Figure 4.39, Mixer System reset

### Mixer System Extended Reset

![](media/image41.wmf){width="3.15625in" height="4.802083333333333in"}

[]{#__RefHeading___Toc35762574 .anchor}Figure 4.40, Mixer System
extended reset

Steps 1 and 2 specified in paragraph 4.1.6. Steps 2 and 4 specified in
paragraph 4.1.13.

Steps 5 and 6 consist in the sequance of steps from 5 to 7 of the
procedure specified in 4.2.1.

Step 7 is specified in Figure 5.49.

### Mixer System power-up initialization

![](media/image42.wmf){width="6.041666666666667in"
height="1.3229166666666667in"}

[]{#__RefHeading___Toc35762576 .anchor}Figure 4.41, Mixer System
Power-up initialization

Step 1 is automatically performed by the subrack controller using the
command sequances stored in the "autoexec.000" and "autoexec.001" files.

Step 2 is specified in paragraph 4.5.2.

### Mixer System configuration erasing

![](media/image43.wmf){width="5.0in" height="3.40625in"}

[]{#__RefHeading___Toc35762578 .anchor}Figure 4.42, Mixer System
configuration erasing.

### Broadcast configuration of the mixer system

The procedure is illustrated in Figure 4.43 and follows the same steps
used to automatically configure the mixer system at power-up. The
command sequence used at power-up is stored in two "autoexec" command
files on the subrack controller Compact Flash memory card. Steps 2 and 3
are not used for automatic power-up configuration but are needed when
issuing commands remotely. The firmware ID byte can assume any value and
at the moment no convention has been established for the mixer system.
Step 6 is described in procedure XYZ and is used to verify that the
successful configuration of the mixer system.

![](media/image44.wmf){width="5.458333333333333in"
height="4.260416666666667in"}

[]{#__RefHeading___Toc35762580 .anchor}Figure 4.43, broadcast
configuration of the mixer system

# Use of the LEDs Monitoring Mode

![](media/image45.wmf){width="6.864583333333333in"
height="4.739583333333333in"}

[]{#__RefHeading___Toc35762582 .anchor}Figure 5.44, Front panel LEDs and
LEDs monitoring mode

![](media/image46.wmf){width="3.9583333333333335in" height="1.625in"}

[]{#__RefHeading___Toc35762583 .anchor}Figure 5.45, Mode of Operation
register

![](media/image47.wmf){width="4.583333333333333in"
height="2.7604166666666665in"}

[]{#__RefHeading___Toc35762584 .anchor}Figure 5.46, Monitoring Mode
Register

![](media/image48.wmf){width="2.90625in" height="1.5in"}

[]{#__RefHeading___Toc35762585 .anchor}Figure 5.47, Monitoring Status
Registers

![](media/image50.wmf){width="3.1979166666666665in"
height="1.4895833333333333in"}

[]{#__RefHeading___Toc35762586 .anchor}Figure 5.48, Monitoring Status
History Registers

+---+------------------+----------------------------------------------+
| 1 | \<22\>\<00       | Read the content of the Monitoring Mode      |
|   | \>\<0B\>\<slot\> | register.                                    |
|   |                  |                                              |
|   |                  | \<22\>: subrack controller command \"read    |
|   |                  | byte from backplane\".                       |
|   |                  |                                              |
|   |                  | \<00\>: unused byte.                         |
|   |                  |                                              |
|   |                  | \<0B\>: \<offset\> byte, Device Access Data  |
|   |                  | address.                                     |
|   |                  |                                              |
|   |                  | \<slot\>: mixer subrack slot number, from    |
|   |                  | 0x02 to 0x15.                                |
|   |                  |                                              |
|   |                  | The read data byte \<MMreg_data \> will be   |
|   |                  | available in the subrack controller General  |
|   |                  | Purpose Memory at location 0x00FA.           |
+===+==================+==============================================+
| 2 | \<12\>\<data_a   | Write to the Monitoring Mode register.       |
|   | \>\<0B\>\<slot\> |                                              |
|   |                  | \<12\>: subrack controller command \"write   |
|   |                  | byte to backplane\".                         |
|   |                  |                                              |
|   |                  | \<data_a\>: (\<MMreg_data\> AND              |
|   |                  | \<bxxxx0000\>) OR \< MMreg_mask \>.\         |
|   |                  | Is the logic AND of the byte obtained from   |
|   |                  | the previous operation (\<MMreg_data\>) and  |
|   |                  | \<bxxxx0000\> to reset the four least        |
|   |                  | significative bits to "0". The result is     |
|   |                  | then ORed with the desired mode:\            |
|   |                  | \<MMreg_mask\> = \<b0000, mode\>.            |
|   |                  |                                              |
|   |                  | In \<bxxxx0000\> the "bxxxx" are four        |
|   |                  | non-care bits meaning that the AND operation |
|   |                  | is not performed on them and "mode" are four |
|   |                  | bits representing the desired monitoring     |
|   |                  | mode. The four bxxxx bits can be replaced by |
|   |                  | a different set of bits to enable/disable    |
|   |                  | some of the monitoring features such as      |
|   |                  | "Enable LED latch Mode", select the "LED     |
|   |                  | Monitoring set (green/red)", turn the LEDs   |
|   |                  | ON/OFF in monitoring mode #15, see Figure    |
|   |                  | 5.46.                                        |
|   |                  |                                              |
|   |                  | \<0B\>: \<offset\> byte, Monitoring Mode     |
|   |                  | register address. The most significative     |
|   |                  | three bit of the \<offset\> byte can be used |
|   |                  | for broadcasting control (see Figure 4.5).   |
|   |                  |                                              |
|   |                  | \<slot\>: mixer subrack slot number, from    |
|   |                  | 0x02 to 0x15.                                |
+---+------------------+----------------------------------------------+

[]{#__RefHeading___Toc35762587 .anchor}Table 5.16, Monitoring Mode
change

![](media/image52.wmf){width="5.625in" height="1.25in"}

[]{#__RefHeading___Toc35762588 .anchor}Figure 5.49, Monitoring Mode
change

![](media/image53.wmf){width="5.052083333333333in" height="1.25in"}

[]{#__RefHeading___Toc35762589 .anchor}Figure 5.50, Enable/Disable LEDs
to show monitoring mode

![](media/image54.wmf){width="4.5in" height="4.21875in"}

[]{#__RefHeading___Toc35762590 .anchor}Figure 5.51, Read monitoring
status and status history

# Problem reporting

## Report a problem to mixer system support

*Stefano M. Rapisarda*

> E-mail: <rapisard@fnal.gov>
>
> Phone: (630) 840-6559.

*Neal G. Wilcer*

E-mail: <wilcer@fnal.gov>

Phone: (630) 840-2749.

Computing and Engineering for Physics Application Department

Electronics Systems Engineering Section

Names and emails available on the ESE Section web page:

http://www-ese.fnal.gov/

## Report a problem to AFE system support

*George Ginther*

> E-mail: <ginther@fnal.gov>
>
> Phone: (630) 840-6337.

*Fred Borcherding*

> E-mail: <fredb@fnal.gov>
>
> Phone: (630) 840-3164.

*John T. Anderson*

> E-mail: <janderson@fnal.gov>
>
> Phone: (630) 840-8885.

# References

> **\[1\]** Jamieson T. Olsen,

a.  \"Digital Front End Mother Board register map\", Engineering Note
    2000-01-28a.

b.  \"DFE and Mixer Board Registers \", Engineering Note 2000-01-28a.

c.  \"DFE backplane address/data bus protocol\", Engineering Note
    2000-03-28a.

d.  \"DFE slow monitoring custom serial bus specification\",\
    Engineering Note 2000-01-31a.

e.  Digital Front End Controller (DFEc) Board:\
    <http://d0server1.fnal.gov/users/jamieson/www/projects/dfec/index.html>

f.  "DFE Crate Controller (DFEC) Command Structure and 1553 Interface
    Specification",\
    Engineering Note 2001-04-16a.

> Information available on the internet:
> <http://d0server1.fnal.gov/users/jamieson/www/index.html>
>
> **\[2\]** Robert D. Angstad, technical documentation.\
> Information available on the internet:\
> <http://d0server1.fnal.gov/users/angstadt/www/datapump/datapump.htm>
>
> **\[3\]** John T. Anderson,

a)  "D-Zero Central Fiber Tracker 8-MCM Analog Front End Board,\
    Design Specification", January 7, 2000.

> Information available on Internet:\
> <http://d0server1.fnal.gov/users/janderson/Public_Eng_Notes/default.html>.
>
> **\[4\]** Mixer System documentation

a)  Neal Wilcer, John Anderson, Stefano Rapisarda "Central Tracker
    Trigger (CTT) Mixer System Backplane Description & Power
    Distribution Specification", July 4, 2000. Document#: ESE-D0-000704.

b)  Makoto Tomoto, \"Note on cable mapping from AFE to Mixer\", October
    26, 2001.

c)  Central Tracker Trigger (CTT) Mixer System Test Procedures.

d)  Central Tracker Trigger (CTT) Mixer System.

> The mentioned documents and several others are available on Internet:\
> <http://www-ese.fnal.gov/D0_CTT_Mixer/>