![](media/image1.emf){width="5.722222222222222in"
height="0.9444444444444444in"}

**SVX II Silicon Strip Detector Upgrade Project**

**Readout Electronics**

**a GSTM Loop-Back Daughter Card**

**for GSTM self testing**

**\--PRELIMINARY\--**

Date: April, 1996

James Franzen

Fermilab

Document \# ESE-SVX-960422

##  Table of Contents {#table-of-contents .appendix}

**1. GENERAL INFORMATION**

1.1 System Introduction 1

1.2 Description 2

1.3 Design 4

2\. DIAGNOSTIC/DEVELOPMENT SOFTWARE

3\. ELECTRICAL & MECHANICAL SPECIFICATIONS

3.1 Packaging

3.2 PC Board Construction

3.3 Power Requirements

3.4 Cooling Requirements

##  {#section .appendix}

# GENERAL INFORMATION 

This document describes and specifies a "General System Test Module"
(GSTM) daughter card that allows for self testing a GSTM. The daughter
card will perform a loop-back function by interconnecting a GSTM
transmitting port (T-Port) to a receiving port (R-Port) on the same
GSTM. Using a minimum of circuitry and complexity, this **GSTM Loop-Back
Daughter Card** will establish the baseline functionality of a
GSTM-based test stand.

By linking a GSTM transmitting and receiving port together with a
solitary GSTM Loop-Back daughter card, the GSTM module can be tested and
diagnosed in a minimal test stand environment. The test stand could be
as physically compact as a single 9U VME crate.

##  System Introduction

The GSTM was designed to be a generic system test module that provides
two FIFO-sourced transmit ports (T-Ports) and two receive ports
(R-Ports) feeding into FIFOs for later readback. The GSTM provides
control, status, and mode signals for user-defined manipulation of
custom daughter cards.

The GSTM Loop-Back Daughter Card specified in this document will enable
the GSTM to be self tested before employing other daughter cards for
sub-system testing.

The GSTM Loop-Back Daughter Card will take the data stream from a GSTM
under-test's T-Port and directly connect that stream to the same GSTM's
R-Port. The bi-directional data streams will be interconnected as well,
with tri-state buffering employed to protect the GSTM's circuitry from
signal driver collisions.

The GSTM Loop-Back Daughter Card will also test control, mode and ID
lines, as well as generate patterns upon status lines implemented on
GSTM ports to verify their operability as well.

## Description

Physically, the GSTM Loop-Back Daughter Card will mount over both a GSTM
transmitting and receiving port connector simultaneously. The Loop-Back
Daughter Card will also connect to both GSTM mezzanine power connectors
associated with the transmit and receive ports under test. The daughter
card will draw power from one of the enveloped GSTM port mezzanine power
connectors.

The GSTM Loop-Back Daughter Card tests a singular pair of GSTM "T" and
"R" ports simultaneously. To test the alternate GSTM T-Port and R-Port
pair, the GSTM Loop-Back daughter card must be repositioned on the GSTM
mother board.

For any given GSTM transmit and receive port pair under-test, the
functions performed by the GSTM Loop-Back Daughter Card are listed
below:

-   . Test the GSTM transmit and receive FIFOs for data integrity.

```{=html}
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```
-   Test the functionality of the bi-directional data paths incorporated
    into the GSTM T-port and R-port, as well as the FIFOs associated
    with them..

-   Test the control, mode, ID and status bits implemented on the GSTM.

Figure 1 shows the interconnection between the GSTM T-port and R-port.

Figure 1: GSTM and daughter card Overview

![](media/image2.emf){width="3.4159722222222224in"
height="1.8159722222222223in"}

A VME CPU running VxWorks will be used to both control the GSTM and
supply data test patterns. Data test patterns will be written to the
GSTM transmit port FIFOs and read back from the GSTM receive port FIFOs.
The VME CPU will perform all error checking tasks.

Figure 2: Test System Overview

![](media/image3.emf){width="4.022916666666666in"
height="2.129166666666667in"}

The design of the GSTM Loop-Back Daughter Card is such as to employ
whatever general-purpose GSTM programmable logic set for internal GSTM
control and operation is supplied as standard.

## Design

A unidirectional data path from the 26 T-Port (**DAT-T**) unidirectional
T-FIFO to the R-port (**DAT-R**) R-FIFO is implemented by a one-to-one
copper interconnection. No signal buffering, re-transmitting or latching
is implemented.

Both the T-Port's and R-Port's nine bits of bi-directional FIFO data
(called **DATA-IO** on both ports) are interconnected with a transparent
bi-directional tri-state buffer. Direction control is determined by the
state of the P-Cntrl \<2\> bits from each port. Using both the T-Port
and R-Port P-Cntrl \<2\> bits enables the Loop-Back card logic to
protect against accidental on-board signal driver collisions.

*(Programmer's note: The upper four bits of the GSTM Mode Register
should be set to insure that all four port's DATA-IO lines are in
receive mode. The Loop-Back Daughter Card will power up in a receive
mode from both ports it envelops as well. Care must be exercised in the
sequence used to enable signal drivers to prevent GSTM-daughter signal
collisions when test software is constructed.)*

It is worth pointing out that there are no VME registers implemented on
the GSTM by which a daughter card can be interrogated. Even the status
lines provided for daughter card responses are not directly mapped
through GSTM internal control logic to a VME register.

Therefore to simplify the daughter card design, the test software, and
to prevent any specialized logic requirements in the GSTM 'standard'
FPGA set, a non-standard use of the GSTM-provided daughter card ID bits
has been implemented. This approach provides a VME-readable register for
interrogating the GSTM Loop-Back daughter card. Sanctioning for such a
non-standard usage of the ID bits is derived from the solitary purpose
of the Loop-Back card to verify the operation of the GSTM itself.

The GSTM daughter card ID bits are directly readable from VME. To the
benefit of the design, the GSTM Loop-Back daughter card envelops two
ports simultaneously (an R-Port and a T-Port). Since testing the ID bits
associated with both enveloped ports is required, the GSTM Loop-Back
daughter card is by default connected to 12 VME-readable bits (six ID
bits for each port). The GSTM Loop-Back card employs the 12 ID bits as
an inherent VME general purpose read-back readable register. The
Loop-Back Daughter Card used the ID bits for several purposes, by
multiplexing information depending on the state of the GSTM CR-Cbits and
/Master-Reset.

Upon the assertion of a GSTM /Master-Reset signal, the GSTM Loop-Back
Daughter Card generates it\'s unique ID number of "1" upon both ID bit
fields (one corresponding to each port) to which it is connected. The
Loop-Back Daughter Card will continue to assert it's ID until which time
as any GSTM CR-Cbit is asserted. At any time the Loop-Back Daughter Card
can be made to re-assert it's ID by issuing another /Master-Reset from
the GSTM.

  ----------- ------------------- --------- --------------------------------------
  **GSTM Test                               
  Register                                  
  (read only)                               
  at Base                                   
  Address +                                 
  0x00, GSTM                                
  Loop-Back                                 
  across T1                                 
  and R1                                    
  ports**                                   

  BIT         MEANING             EXAMPLE   NOTES

  26-31       T1-Port Daughter    0x01      Loop-Back Card gives ID number after
              Card ID                       /Master-Reset

  20-25       R1-Port Daughter    0x01      Loop-Back Card gives ID number after
              Card ID                       /Master-Reset

  14-9        T2-Port Daughter    ...       undefined (no card/unknown daughter
              Card ID                       card attached)

  8-13        R2-Port Daughter    ...       undefined (no card/unknown daughter
              Card ID                       card attached)

  0-7         fixed to be 0x05    0x05      always 0x05
  ----------- ------------------- --------- --------------------------------------

Upon generation of a global GSTM CR-Cbit0 signal, the low-order six
T-FIFO bits are multiplexed onto the ID bits. This provides the ability
to generate test patterns within the lowest order six bits of the T-FIFO
that can be used to verify operation of each ID bit, thus fully testing
the GSTM's ability to see all the ID bits of both ports toggle. The same
low-order T-FIFO data is supplied to both port's ID bit fields. A
multiplexer failure would indicate a problem with the CR-Cbit0 signal at
the erring port connector.

  -------------- ------------------- --------- --------------------------------------
  **GSTM Test                                  
  Register (read                               
  only) at Base                                
  Address +                                    
  0x00, GSTM                                   
  Loop-Back                                    
  across T1 and                                
  R1 ports**                                   

  **Global                                     
  CR-Cbit0                                     
  asserted, last                               
  T-FIFO data                                  
  strobed by                                   
  SYS-CLK was                                  
  0x0000001A**                                 

  BIT            MEANING             EXAMPLE   NOTES

  26-31          T1-Port Daughter    0x1A      Loop-Back Card returns last clocked
                 Card ID                       T-FIFO data

  20-25          R1-Port Daughter    0x1A      Loop-Back Card returns last clocked
                 Card ID                       T-FIFO data

  14-9           T2-Port Daughter    ...       undefined (no card/unknown daughter
                 Card ID                       card attached)

  8-13           R2-Port Daughter    ...       undefined (no card/unknown daughter
                 Card ID                       card attached)

  0-7            fixed to be 0x05    0x05      always 0x05
  -------------- ------------------- --------- --------------------------------------

Upon generation of a global GSTM CR-Cbit1 signal, the ID bits will be
multiplexed in such a way as to monitor the status of the P-Control
bits, the port-unique /CR-Control bits, and the MR-Mode bits. Thus, test
software can command the GSTM to generate these signals and the ID bits
can be used to verify their operability at each port connector. The
control bits monitored through any given port ID bit field are the
control bits for that port. A multiplexer failure would indicate a
problem with the CR-Cbit1 signal at the erring port connector.

  -------------- ------------------- --------- --------------------------------------
  **GSTM Test                                  
  Register (read                               
  only) at Base                                
  Address +                                    
  0x00, GSTM                                   
  Loop-Back                                    
  across T1 and                                
  R1 ports**                                   

  **Global                                     
  CR-Cbit1                                     
  asserted, last                               
  T-FIFO data                                  
  strobed by                                   
  SYS-CLK was                                  
  0x00000017**                                 

  BIT            MEANING             EXAMPLE   NOTES

  26-31          T1-Port Daughter    0x17      T-PORT P-Cntrl\<2:0\> =5, /CR-Cntrl =
                 Card ID                       1, MR-Mode = 1

  20-25          R1-Port Daughter    0x17      R-PORT P-Cntrl\<2:0\> =5, /CR-Cntrl =
                 Card ID                       1, MR-Mode = 1

  14-9           T2-Port Daughter    ...       undefined (no card/unknown daughter
                 Card ID                       card attached)

  8-13           R2-Port Daughter    ...       undefined (no card/unknown daughter
                 Card ID                       card attached)

  0-7            fixed to be 0x05    0x05      always 0x05
  -------------- ------------------- --------- --------------------------------------

Upon generation of both the global GSTM CR-Cbit0 and CR-Cbit1 signals,
the low-order five T-FIFO bits are multiplexed across the port-specific
status return bits as shown:

  ---------------- ------------ ------------ ------------ ------------ ------------
  **Relationship                                                       
  of T-FIFO bits                                                       
  to status                                                            
  lines:**                                                             

                   T-FIFO bit 4 T-FIFO bit 3 T-FIFO bit 2 T-FIFO bit 1 T-FIFO bit 0

  R-PORT           P-Status2    P-Status1    P-Status0    SR-Status1   SR-Status0

  T-PORT           P-Status2    P-Status1    P-Status0    SR-Status1   SR-Status0
  ---------------- ------------ ------------ ------------ ------------ ------------

This provides the ability to generate test patterns within the lowest
order six bits of the T-FIFO that can be used to verify operation of
each status bit, thus fully testing the GSTM's ability to see all the
status bits of both ports toggle.

Upon the assertion of a GSTM /Master-Reset, a bit pattern of all zeroes
will be placed on the port-specific status return bits. This feature
assures that no 'error' status is returned upon power-up, and that
diagnostic software can return to an idle status condition after testing
the status bits.

A light emitting diode will indicate the presence of fused and filtered
+5 volt power for active components used on the Loop-Back daughter card.
Four more light emitting diodes will indicate the presence of raw +5 and
-5 voltages at each of the power connectors.

# DIAGNOSTIC/DEVELOPMENT SOFTWARE

The following diagnostic descriptions often refer to GSTM Motherboard
logic that will be tested. For reference, have a copy of the GSTM
Motherboard Specification document number ESE-SVX-960126 on hand.
References made here to GSTM hardware can be seen in the GSTM
Motherboard Specification, Figure 2: "Functional Blocks for the GSTM
Motherboard".

A test program will be needed which generally adheres to the content and
sequence detailed here.

-   Issue a /Master-Reset and check for an ID value of 0x01 in both
    T-Port and R-Port fields of the GSTM Test Register. This test
    verifies the receipt of /Master-Reset at each port.

```{=html}
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-   Test that all six ID bits of both ports are functional. Generate a
    global GSTM CR-Cbit0 signal after putting bit-toggle test patterns
    in the T-FIFO. The low-order six bits of T-FIFO data should appear
    on the ID bits. A multiplexer failure might indicate a problem with
    the CR-Cbit0 signal at the erring port connector.

-   Write test pattern data into the T-Port FIFO until full. Clock the
    T-Port T11 (or T21) FIFO data into the R-Port R11 (or R21) FIFO.
    Read the R-Port FIFO and compare for errors.

-   Repeat FIFO tests while controlling the T-Port's and R-Port's nine
    bits of bi-directional data (called **DATA-IO** on both ports) as
    well as the GSTM Mode Register's direction control bits. Perform
    this to test both the bi-directional capabilities of the GSTM
    buffers and the data integrity of the FIFOs. This FIFO test should
    be performed twice, once in each direction (T-Port to R-Port and
    vice versa). The P-Cntrl \<2\> bits from both ports define direction
    control for the GSTM Loop-Back Daughter Card.

*(Programmer's note: The upper four bits of the GSTM Mode Register
should be set to insure that no signal driver collisions occur between
the Loop-Back Daughter Card and the GSTM. The Loop-Back Daughter Card
provides internal self protection against on-board signal collision
should both ports drive their DATA-IO lines. It is possible though to
create a situation where the Loop-Back Daughter Card could drive against
a GSTM port that is also driving. Care must be exercised in the sequence
used to enable signal drivers to prevent GSTM-to-daughter signal
collisions when test software is constructed.)*

-   Using the T-Port's and R-Port's P-Cntrl \<2\> bits to control data
    flow direction, write test pattern data into the T12 (or T22) FIFO-1
    and read the data out through the R12 (or R22) FIFO-2. Perform the
    same test using the T12 (or T22) FIFO-2 and the R12 (or (R22) FIFO-1

-   Test the functionality of the P-Control bits, the /CR-Control bits
    and the MR-Mode bits for both ports under test. Generate a global
    GSTM CR-Cbit1 signal and the ID bits will be multiplexed in such a
    way as to monitor the status of the bits. Test software must command
    the GSTM to generate these signals and use the ID bits to verify
    their operability at each port connector. The control bits monitored
    through any given port ID bit field are the control bits for that
    port. A multiplexer failure might indicate a problem with the
    CR-Cbit1 signal at the erring port connector.

```{=html}
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```
-   Test the functionality of daughter card status return bits
    P-Status\<2:0\> and SR-Status\<1:0\> for both ports under test.
    Generate both the global GSTM CR-Cbit0 and CR-Cbit1 signals after
    loading test pattern data in the T-FIFO. The low-order five T-FIFO
    bits will be echoed across the port-specific status return bits.

*(Programmer's note: Remember that the Loop-Back card tests are always
being implemented on both Transmit and Receive ports, hence the
diagnostic software [must]{.underline} verify bit operations on both the
T-Port and the R-Port for a complete test.)*

# ELECTRICAL & MECHANICAL SPECIFICATIONS

## Packaging

The GSTM Loop-Back card is a 4.0" x 6.0" card.

Figure: Physical outline of the GSTM Loop-Back card.

![](media/image4.emf){width="4.923611111111111in"
height="1.617361111111111in"}

## PC Board Construction

The board is made of FR4 fiberglass with a thickness of .063".

## Power Requirements

Power calculations are:

2 \-- PA7140 PEEL arrays @ 150mA ea. = 300mA

1 \-- AMD 29861 bi-directional buffer = 150mA

5 \-- LEDs @ app. 20mA ea. = 100mA

Power consumption is estimated to be less than 3.0 watts.

## Cooling Requirements

Minimally, a conventional VME air-cooling fan tray is recommended for
any VME installation. Otherwise, no supplemental cooling is required for
the GSTM Loop-Back Daughter Card.

## A1 Component Documentation {#a1-component-documentation .appendix}

## Introductory level data sheets for the ICT PA7140 and the AMD 29861 follow this page.  {#introductory-level-data-sheets-for-the-ict-pa7140-and-the-amd-29861-follow-this-page. .appendix}

## A2 Schematics {#a2-schematics .appendix}

## A one-page schematic follows this page.  {#a-one-page-schematic-follows-this-page. .appendix}

## A3 FPGA Equations {#a3-fpga-equations .appendix}

## There are two programmable logic arrays used on the GSTM Loop-Back Daughter Card. Both are ICT PA7140 PEEL arrays. The equations for both PEELs are identical. A multi-page listing of the equation will follow this page.  {#there-are-two-programmable-logic-arrays-used-on-the-gstm-loop-back-daughter-card.-both-are-ict-pa7140-peel-arrays.-the-equations-for-both-peels-are-identical.-a-multi-page-listing-of-the-equation-will-follow-this-page. .appendix}

## A4 Parts List {#a4-parts-list .appendix}