# Double-Silicon Stave Thermal Solutions-Comments

Two separate models were constructed. The distinguishing features
between the two were the shape of the cooling tube and the contact of
the tube with the stave composite face. One tube was flattened and the
other circular. The flattened tube provides a 2mm wide contact, whereas
the circular tube was provided with a secondary composite part to
overcome the resulting line contact.

In each case the separation between the stave sandwich facings was
4.6mm; therefore, the hydraulic diameter for each cooling tube is
different. This leads to a difference in calculated convective film
coefficients for the two tube geometries, as well as coolant pressure
drop. In each case the coolant mass flow rate is the same, based on 192W
per stave. Figure 1 is shaded image of the parasolids model used in the
coolant analysis. To reduce computational time a portion of the stave
was modeled.

![](media/image1.wmf)

Figure 1: Parasolids model of stave with double-sided silicon wafers,
12.4cm long, with 4 hybrids per wafer and 6 chips per hybrid. Dissipated
power to the coolant U-Tube is 192W. The stave length (exclusive of end
caps) is 1064mm long. The width is 71.5mm (including the side strips)

The parasolids model of Figure 1 was sliced on either side of a full
length silicon wafer, upper and lower. The partial model is 21.9cm long
providing a thermal assessment of the 12.4cm wafer with four hybrids,
and a significant portion of a second one. One will find that the 1mm
separation on either side of a 12.4cm wafer defines a distinct thermal
pattern. This pattern arises from end of wafer having a row of chips
near the edge and at the opposite edge the chips are set-back. This
pattern is clearly seen in Figure 1 (arrow pointing to 1mm separation).
The break and relative sizes of the silicon wafers represented in the
thermal model is depicted in Figure 2.

![](media/image2.wmf)

Figure 2: View of silicon wafers from the thermal model. Two full length
wafers are present, with partial wafers at each end.

Figure 3 illustrates the geometry used in solving for the temperature
gradient. Each chip is assumed to dissipate 0.5W; in this case a total
of 42W.

![](media/image3.wmf)

Figure 3: View of reduced parasolids model, used in the CFDesign code.

Not evident is that the 6 electric chips mount onto a dielectric hybrid,
\~0.23mm thick. Through the thickness thermal conductivity of this
material is estimated to be 5W/mK. This dielectric hybrid is in turn
mounted onto a 0.38mm BeO substrate that has a thermal conductivity of
240W/mK. For modeling purposes, we combined the two materials into a
0.38mm thick single layer of 8W/mK thermal conductivity.

The balance of the parameters used in the thermal model is listed in
Table 1.

Table 1: Material Thermal Properties

  ----------------------------- ------------------ ----------------------
  Material                      K- (W/mK)          Thickness (mm)

  Silicon Wafer                 148                0.28

  Silver-Adhesive               1.55               0.0508

  Dielectric/BeO Hybrid         8                  0.38

  Cable Bus                     0.12               0.125

  Composite Facing                                 0.75

  Stave axis                    384                

  Transverse                    97                 

  Through thickness             1.44               

  Coolant tube (Al)             204                0.3048

  CGL Adhesive                  1                  0.0762
  ----------------------------- ------------------ ----------------------

Figure 4 is a steady state solution for the thermal gradients in the
stave with silicon modules mounted on both sides. As indicated earlier
the 1mm separation between silicon modules causes a repeating thermal
pattern to occur. Since the module has chopped off ends, the region most
representative of the thermal gradients is shifted slightly relative to
that indicated in Figure 4.

The peak chip temperature is nominally -11.97ºC. To the left of this
peak, the exposed silicon module surface temperature is -16.7ºC.
Progressing to the right of the peak chip, the module surfaces are
-15.2ºC, -15.3ºC, and -15.4ºC. The module surface temperature in front
of the last row of chips (RHS) is -16.1ºC.

Localized modules temperatures are predicted as low as -17.3ºC just
front of the chips where the 1mm separation between wafers exists. This
region is directly over the cooling tubes.

Some heat spreading occurs along the stave axis from the high
conductivity composite facings. This is the effect that gives rise to
the slight variation in silicon module surface temperatures.

![](media/image4.wmf)

Figure 4: Thermal solution for stave with flattened coolant tube.
Aluminum cooling tube with a convective film coefficient 2342W/m^2^K,
coolant at -25ºC.

A round cooling tube will be needed to contain a high pressure CO~2~
coolant. In anticipation that circular tube to a flat surface will lead
to an unacceptable thermal resistance, a composite material is used to
increase contact. The material proposed is highly conductive graphitic
foam with a specific gravity 0.45g/cm^3^. The foam is bonded and
feathered in to the cooling tube before bonding the cooling tube to the
composite facing. This concept is shown in Figure 5.

![](media/image5.wmf)

Figure 5: Modification to the parasolids file for round cooling tube. A
high conductivity composite is added to each side of the cooling tube to
overcome the line contact between the cooling tube and the composite
facing.

The thermal solution for the round coolant tube produced lower
temperatures than the flattened tube because of the increased thermal
contact provided by the graphitic foam. The predicted peak chip
temperature is -12.6ºC, and exposed silicon module surface temperature
ranges from a low of -17.5ºC to a high of -16.1ºC. The module surface
near the 1mm split has a slightly lower temperature than before (-17.5ºC
versus -16.7ºC for the flatten tube).

![](media/image6.wmf)

Figure 6: Thermal solution using circular tube (4.6mm OD, 12mil wall)
with graphitic foam bonded to tube to enhance thermal contact
coefficient. Foam material has thermal conductivity of 125W/mK in plane
(along tube axis) and 50W/mK normal. Convective film coefficient is
3000W/m^2^K.

A thermal image was created using CFDesign program software, which
allows solid parts to be removed for viewing interface temperatures.
Figure 7 is a view of the silicon module surface temperature with the
chips and hybrids removed. The silicon module surface directly beneath
the hybrid region is warmer than the exposed surface by approximately
2.9ºC, diminishing to 2.2ºC at the last row of chips. The highest
differential occurs for the array of chips near the 1mm split between
silicon modules.

![](media/image7.wmf)

Figure 7: Thermal image *with the chip and hybrid components removed*
for the circular tube model (4.6mm OD, 12mil wall) of Figure 6*.* Foam
material has thermal conductivity of 125W/mK in plane (along tube axis)
and 50W/mK normal. Convective film coefficient is 3000W/m^2^K.

# Closing Comments

The results are considered to be reasonable approximation to what can be
expected. However, it would be prudent to spend time to improve the
prediction for the convective film coefficients for the two tube
geometries.

If the design advances in the direction of the round tube, it may be
wise to add a 5mil strain relief layer (graphite) between the tube and
graphitic foam. This transition layer would contribute to a more
reliable thermal joint between dissimilar materials. If this concept is
considered acceptable the added thermal resistance should be factored
into the model.

The dielectric cable, coupled with the increased heat flux (more chips)
is contributing to warmer silicon surface temperatures. One option worth
evaluating is adding a transverse heat spreader inside the composite
sandwich directly beneath chip array. This heat spreader would be
designed to conduct heat from the two middle chips to the two axial
coolant tubes.

# Updated Solution

Question may arise to what effect the cable thermal conductivity has on
silicon module and chip peak temperatures. The previous solutions used
an in-plane and through the thickness of 0.12W/mK. This value was
revised to 1W/mK and the solution for round coolant tube re-run. This
result is shown in Figure 8. Notice the peak chip temperature has
dropped by 4ºC and module peak surface temperature is now nominally
minus17.4ºC.

![](media/image8.wmf)

Figure 8: Thermal solution using circular tube (4.6mm OD, 12mil wall)
with graphitic foam bonded to tube to enhance thermal contact
coefficient, same conditions as Figure 6 and Figure 7. Right inset has
the hybrids and chips removed to see the module surface temperature.
Surface temperatures in the model middle are used as indicative of peak
temperatures, away from edge effects.