# SUBCONTRACT TITLE: *ADVANCED PROCESSING OF CdTe- AND CuIn~X~Ga~1-x~Se~2~- BASED SOLAR CELLS*

# 

# SUBCONTRACT NO: NDJ-2-30630-18

# REPORT FOR: Phase II/Quarter 3

# 

# SUBMITTED TO: Ken Zweibel

#  National Renewable Energy Laboratory

# PRINCIPAL INVESTIGATORS: C. S. Ferekides and D. L. Morel

# University of South Florida

# Department of Electrical Engineering

# 4202 East Fowler Avenue

# Tampa, FL 33620

# 

# 

This is the progress report for the 3^rd^ quarter of Phase II for the
months of August through October 2003. The project covers two thin film
technologies: CdTe and CIGS. The focus areas include: (a) CdTe --
stability, novel back/front contacts, and the development of
manufacturing friendly processes; (b) CIGS -- development of two-step
non-co-evaporation technology.

A. CdTe

In this report we provide a summary of results obtained in three areas:
(a) dry back contact processing, (b) front contact/buffer studies, (c)
large area CdTe thin films on moving substrates, and (d) Cu-effects.

\(a\) Dry Back Contact Processing

A common processing step prior to the application/formation of a back
contact to CdTe solar cells is a surface treatment to remove oxides and
leave a Te-rich region. USF's baseline process includes a light etch in
a Br~2~/methanol solution (0.1% vol). This has been found to be as
effective and to a great extent more reproducible than the
Nitric/Phosphoric etch. In this report we describe device results
obtained for CdTe cells processed using a dry etch step -- rf sputter
etching -- instead of the above mentioned wet treatments. Following the
CdCl~2~ heat treatment, the cells were exposed to Ar, or N~2~ in an rf
sputter etcher; in some cases a small amount of O~2~ was also added to
determine the process' tolerance to O~2~. The effect of rf power and
etch time on V~OC~ and FF are shown in Fig. 1. In this case the
sputtering gas was N~2~. With the exception of one data point, the V~OC~
is essentially independent of power and etch time (in the range of
820-840 mV). Only the device etched using the highest power (of 100 W)
and the longest etch time (10 min) exhibited a low V~OC~ (below 800 mV).
This is attributed to possible surface damage which, as it will be
further discussed, is also the reason for the behavior of the FF as a
function of power and time. The FF exhibits a greater sensitivity on the
power and etch time. It increases with decreasing power, and for each
power setting it decreases with increasing etch time. The observed
behavior can be explained by defining two operating regions for this
process: (a) "cleaning" and (b) "damaging"; in all cases the sputter
etch process results in removing surface oxides (therefore enabling the
formation of an effective back contact), but at high power settings
and/or long etch times it appears that the plasma in addition to
removing oxides, is also damaging the CdTe surface resulting in a
defective region (heavily compensated with reduced effective carrier
concentration) which leads to the formation of a barrier at the back
contact.

![](media/image1.wmf){width="3.341732283464567in"
height="3.333464566929134in"}

![](media/image2.wmf){width="3.341732283464567in"
height="3.325196850393701in"}Figure 2 shows the dynamic resistance (i.e.
dV/dJ in Ω-cm^2^) for several devices. The device etched for 20 minutes
@ 75W rf power, exhibits the characteristic "bump" in its dV/dJ data
indicating the presence of a back barrier. At the other extreme, the
device etched for 10 min @ 50W, exhibits no signs of a back barrier and
its dV/dJ data is approaching the lowest series resistance value
(1.2-1.3 Ω-cm^2^) in this group of cells. The characteristics of the
other two devices are also affected by what appears to be an increased
"series resistance" around V~OC~ limiting the FF (the light J-V for the
cells of Fig. 2 are included in the appendix).

![](media/image3.wmf){width="3.132677165354331in"
height="3.2244094488188977in"}

The ambient pressure also influenced cell performance as indicated in
table 1 (the data shown are for N~2~). The behavior is similar to what
was described in Fig. 1 above, where the V~OC~ remains essentially
unaffected but the FF appears to reach a maximum in the range of 250-300
mTorr. The light J-V characteristics for the last three devices in table
1 are shown in Fig. 3. In this case the decrease in the FF is not due to
the formation of a barrier at the back contact; rather the J-V data
suggest that collection losses may be responsible for the lower FF.

\(b\) Front Contact/Buffer Studies -- Zn~2~SnO~4~

Work on front contacts is based on co-sputtered thin films based on Cd,
Sn, Zn, and In. Of the ternaries being investigated Cd~2~SnO~4~ is being
deposited by co-sputtering from CdO and SnO~2~ targets, Zn~2~SnO~4~ from
ZnO and SnO~2~ and Cd~2~InO~4~ ZnIn~2~O~4~ from metallic targets in a
Ar-O~2~ ambient. Binaries such as SnO~2~, and In~2~O~3~ are deposited by
both reactive sputtering from the metals as well as rf sputtering from
ceramic targets.

In this report we focus on the most successful to-date buffer (resistive
layer) for CdTe cells as demonstrate by the CdTe group at NREL: zinc
stannate (Zn~2~SnO~4~ or ZTO). Since co-deposition allows for variations
in the stoichiometric composition of these films, one of the objectives
is to investigate the effect of the Zn/Sn ratio on solar cell
performance. While most of the work is focused for Zn/Sn ratio around
2.0 (1.9-2.1) devices have also been fabricated at ratios of 1.5 and 2.5
in an effort to improve our understanding of these materials and
processes and the interactions between the contact/window materials. The
stoichiometric ratio is established by controlling the deposition rates
of the two metals (or oxides). The ultimate objective is to advance
device performance and determine the robustness of the overall process.
A series of calibration experiments are also underway where ZTO films
are being characterized using XRD in order to determine the material
phases that form under various deposition conditions and heat
treatments. Figure 4 shows the XRD data for ZTO/SnO~2~:F bi-layers. The
SnO~2~ is deposited by CVD and the ZTO film is deposited using
co-sputtering as indicated above. The Zn/Sn ratio for the films in Fig.
4 is 2.0 and the layers were heat treated at three different
temperatures (550, 575, and 600°C); at this time it was decided to
deposit ZTO on the baseline conductive oxide (CVD SnO~2~), since this
bi-layer structure will be used to fabricate solar cells. A reference
pattern for SnO~2~ is also included in the figure. The major peaks at
approximate 2θ values of 26.56, 51.68, and 54.67° are associated with
SnO~2~ (as seen in the SnO~2~ reference pattern). Annealing the
SnO~2~/ZTO bi-layers at 550°C does not appear to lead to crystallization
of the ZTO films; however at 575 and 600°C, several ZTO related peaks
appear indicating the formation of Zn~2~SnO~4~. The region between 32
and 46° is also shown in Fig. 4 with the ZTO peaks marked. No ZnO
related peaks were detected. At this time it would not be possible to
verify from these particular set of bi-layers if the ZTO films contain a
SnO~2~ phase.

![](media/image4.wmf){width="5.996456692913386in"
height="2.9456692913385827in"}

Figure 5 shows the J-V and SR characteristics for four devices
fabricated on SnO~2~:F/ZTO (legend values correspond to the ZTO
annealing temperatures). In this case the ZTO films were deposited with
a Zn/Sn ratio of 2.5. The only processing variation is the ZTO annealing
temperature (prior to the deposition of CdS): the ZTO films were used
(a) as-deposited (amorphous), and (b) heat-treated at 550, 575, and
600°C in inert ambient; the CdCl~2~ heat treatment was carried out at
400°C. Figure 5 displays the dark J-V and SR for CdTe cells fabricated
on ZTO/SnO~2~:F substrates; the CdCl~2~ heat treatment was carried out
at 400°C. It is clear that the dark J-V "degrade" (i.e. dark currents
increase) as the annealing temperature of ZTO decreases, with the device
fabricated on as-deposited (AD) ZTO exhibiting the highest dark current.
The QE data suggests that the CdS for the AD-ZTO device has been
entirely "consumed" during the fabrication process, while for the cells
fabricated on heat treated ZTO it appears that the CdS thickness (i.e.
blue QE) is the same. However, the red response for the 600°C device is
improved indicating improvement in collection for that device.

![](media/image5.wmf){width="5.997244094488189in"
height="2.9480314960629923in"}

Figure 6 displays similar data as that on Fig. 5, the only difference
being the CdCl~2~ annealing temperature - in this case a higher
temperature of 420°C was used. The overall trends shown in the two
figures are similar: in both cases the dark currents increase with
decreasing annealing temperature of the ZTO with the AD-ZTO devices
exhibiting the highest dark currents. However the higher CdCl~2~
annealing temperature seems to lead to higher dark currents for the 550
and 575 heat treated ZTO devices, with no apparent differences observed
for the 600C device. The SR also follows similar trends (as those
observed in Fig. 5), with the higher CdCl~2~ annealing temperature
having essentially no effect on the 600°C HT ZTO device; the red
response (collection) of the other three cells appears to improve
(compared to the devices annealed at 400°C).

Figure 7 shows the V~OC~ and FF for the above described devices, where
the overall improvement in performance for higher ZTO annealing
temperatures is evident. The devices CdCl~2~ treated at 420°C exhibited
in nearly all cases minor improvements in performance. It should also be
noted that both the V~OC~ and FF are below state-of-the-art values and
they were at best 780-790 mV and 65-66% respectively.

![](media/image6.wmf){width="5.998425196850394in"
height="2.9653543307086614in"}

Based on the results described above the following conclusions can be
tentatively made for CdTe cells fabricate on Zn-rich ZTO films
(Zn/Sn=2.5):

-   Device performance improves with higher annealing ZTO temperatures
    suggesting that the ZTO films must be crystallized prior to
    fabricating the CdS/CdTe junction.

-   Devices fabricated on amorphous (as-deposited) ZTO films exhibited
    improved blue SR (essentially no significant amount of CdS appears
    to remain in the device) suggesting that "consumption" of the CdS
    during the fabrication process results through interdiffusion with
    both the CdTe and ZTO, and can be possibly controlled (to a certain
    extent) by controlling the amount of amorphous ZTO (i.e. through the
    annealing temperature).

-   Higher CdCl~2~ temperatures appear to improve collection in some
    cases, however overall performance enhancements are in general
    small, with the most significant changes taking place for devices
    with ZTO heat treated at low temperatures (or as-deposited);
    therefore, the main benefit from annealing the ZTO at high
    temperatures seems to be a larger process window with regards to the
    CdCl~2~ annealing temperature. It should be noted that the
    performance of baseline devices (i.e. bi-layer SnO~2~/CdS/CdTe) when
    CdCl~2~ heat treated at temperatures above 400°C degrades
    significantly.

> Reactively Sputtered SnO~2~
>
> Reactively sputtered SnO~2~ is also being evaluated as a buffer layer.
> Reactive sputtering was considered as an alternative process that can
> have manufacturing advantages over CVD for large area deposition. The
> conductive oxide used for these devices was CVD SnO~2~:F. One of the
> parameters studied was the thickness of the sputtered SnO~2~ buffer.
> The results indicated that even at thicknesses of only 125 Å can be
> sufficient to improve solar cell performance (compared to a cell w/o a
> buffer). The results for a series of devices where the thickness of
> the reactively sputtered SnO~2~ buffer layer was varied from 125 to
> 1000 Å are listed in table 2. These represent the best devices
> fabricated to-date for each SnO~2~ thickness; series (R~S~) and shunt
> (R~SH~) resistances were estimated from the slope (dV/dJ) of the light
> J-V at reverse and forward bias respectively. As already mentioned
> above, even a SnO~2~ layer with an approximate thickness of 125 Å
> leads to state-of-the-art performance characteristics. Although the
> best performer appears to be the device with 1000 Å thick SnO~2~, the
> differences among these cells are well within the typical run to run
> variability (and should not be considered as significant).
>
> In addition to reactively sputtered SnO~2~ we have also evaluated
> *In~2~O~3~* in ITO/In~2~O~3~ bi-layers. Indium oxide was also found to
> be an effective buffer layer; details on this work will be included in
> a future report.

![](media/image7.wmf){width="6.0in"
height="3.0in"}![](media/image8.wmf){width="6.0in" height="3.0in"}

\(c\) Large Area CdTe Thin Films on Moving Substrates

In a previous report we identified as a key problem associated with the
large area deposition system (10 x 10 cm^2^) variations in device
performance associated with high dark currents (i.e. shunting) which
were believed to be due to localized defects (primarily "pinholes" in
CdTe). In order to address this issue a series of experiments were
performed to better understand effect of process parameters (primarily
substrate motion) on device performance. Figure 8 describes with simple
schematics the four process variations studied; heater C is for
pre-heating/annealing of the CdS, heater B is for substrate heating
during the deposition, and heater A is the source heater; the four
variations utilized were:

\(a\) *stationary process*, where the substrate is maintained above the
source for the duration of the entire process (including heating up);
this process is essentially identical to the small area CSS utilized at
USF;

\(b\) a *semi-stationary* process where the source and substrate are
first heated up and once the deposition temperatures are reached, the
substrate is quickly transferred over the source (few seconds),
maintained over the source until the deposition is complete (1-3
minutes), and finally transferred beyond the deposition zone where it is
allowed to cool down;

\(c\) a *moving substrate* process similar to (b), however in this case,
after reaching the desired source and substrate temperatures, the
substrate is set in continuous motion; the deposition takes place as the
substrate moves through the deposition zone;

\(d\) the last variation is essentially identical to process (c),
however, in this case once the substrate moves beyond the deposition
zone, the motion is reversed and the substrate passes for a second time
through the deposition zone.

![](media/image9.wmf){width="5.996456692913386in"
height="2.041732283464567in"}

Process (d) proved to be ineffective as it appeared to produce bi-layers
of CdTe; in several instances the "top" CdTe (i.e. the material
deposited during the second pass through the deposition zone) peeled off
leaving behind approximately a CdTe film of 1-2 μm in thickness.

A comparison of device results, and in particular cell performance
variations over the 10 x 10 cm^2^ deposition area, indicated that
uniformity improved from (c) to (b) to (a); it should be noted that our
objective under this task is to optimize performance for process (c).
The observed behavior is believed to be related to the microstructure of
the CdTe and in particular the initial stages of the nucleation process.
Considering the typical source/substrate temperatures of 660/600°C, in
process (a) where the substrate is kept at all times above the source
including the heating up period, the CdTe deposition is expected to
begin at temperatures below the ultimate 660/600°C combination; although
no experiments have been carried out to determine the exact temperatures
where the growth begins, it is estimated that approximately 10% of the
deposition takes place during the heating up period. Nucleation at lower
temperatures leads to a higher nucleation density (compared to the
moving substrate processes) smaller grains (initially) and in general
denser films. This assertion is currently based on the observed device
performance and the fact that cell to cell variations are essentially
eliminated for devices fabricated using the *stationary* process (Fig. 8
(a)); however, additional studies of the CdTe nucleation and
microstructure must be carried out to better quantify the effect of
substrate motion on the structural properties of CdTe and cell
performance.

As indicated in previous reports, the use of O~2~ during the CdTe
deposition process leads to denser films, but also lower deposition
rates; the deposition rate as a function of the O~2~ pressure in our
large area deposition chamber is shown in Fig. 9. One of the reasons for
the lower deposition rates in O~2~ ambient is the fact that the surface
of the CdTe source material oxidizes. Figure 10 shows the effect of O~2~
pressure on the FF of a series of solar cells. In this case the CdTe
thickness varied as these experiments were part of a series of
depositions carried out to calibrate the CdTe deposition rate as a
function of O~2~ pressure. Nevertheless the FF increases with decreasing
thickness (improved shunting), offering one more indication of the
improvement in the density of the CdTe films with O~2~ pressure.

![](media/image10.wmf){width="3.025196850393701in"
height="3.0082677165354332in"}![](media/image11.wmf){width="2.9917322834645668in"
height="3.0082677165354332in"}

**(d) Cu-effects**

Copper and its use in the fabrication of CdTe solar cells --
specifically its use for effective back contact formation -- have been
receiving considerable attention in recent years. One of the tasks under
the back contact studies being carried out at USF is to develop
"Cu-free" processes/options. Material options considered in the past
include Sb~2~Te~3~ and Ni~2~P. Although Ni~2~P produced reasonable solar
cell performance Sb~2~Te~2~ did not. In this report we present efforts
focused on improving our understanding of the role of Cu, and develop
conditions/processes to utilize this element in a way that it will not
affect the reliability of the devices. Our approach focuses on
introducing Cu into the devices during an early fabrication step, in
this case Cu is introduced in CdS, and eliminating it from the back
contact process; most CdTe research groups introduce Cu during the back
contact formation process after the CdTe deposition. USF baseline
devices are fabricated with Cu-containing graphite paste, or sputtered
Cu~2~Te as the back contact. The results presented here are empirical
and experiments have focused on optimizing device performance.

The cell fabrication sequence utilized for results presented in this
section is based on "baseline" processes described in previous reports;
the key differences are: (a) following the CdS deposition by close
spaced sublimation, the films are exposed to Cu. The Cu is either
deposited on the CSS-CdS using sputtering, or by dipping the samples in
a CuCl solution. (b) No Cu is used in the back contact process; the
contact materials utilized to-date are graphite paste and
sputter-deposited Sb~2~Te~3~ followed by Mo.

Table 3 lists device results for cells fabricated with plain graphite;
prior to the CdTe deposition the CSS-CdS films were dipped in a CuCl
solution for the times indicated in the table (treatment time).

Table 3. Solar cell characteristics for cells with CdS treated in a CuCl
solution.

![](media/image12.wmf){width="6.375196850393701in"
height="3.2338582677165353in"}

The light J-V and QE data for the "Cu-treated-CdS" cells are shown in
Fig. 11. It should be noted that thickness variations in CdS (as
indicated by the blue QE) are not intentional, but rather represent run
to run variations, which can be significant for CSS-deposited films.
With the exception of the device treated for 5 minutes all other cells
have a "sufficiently" thick CdS. Notwithstanding the thickness
variations, the above data suggest that the treatment time (which is
assumed to be directly related to the amount of Cu incorporated into
CdS) has an effect on the performance of the devices. Treatments for
10-15 minutes appear to be most effective. The device treated for 20
minutes exhibits shunting and poor collection as indicated in its QE
performance; this QE behavior has been verified in devices where the
amount of Cu added to the CdS was relatively high. The devices treated
for 10 and 15 minutes (same CdS thickness) exhibit similar performance,
however, the 15-min cell also seems to be collection limited as
indicated by the light J-V in the 0-0.5 volts range.

Although, the consistency and reproducibility of these results requires
further verification, it appears that no barrier forms at the back
contact as indicated by the light J-V for these cells (the entire light
J-V of Fig. 11 are included in the appendix). This suggests that Cu
could potentially be eliminated from the back contact processing steps,
and that the formation of Cu~2~Te at the back surface may not be
necessary for the formation of a barrier free back contact.

A second set of cells processed under the same conditions as the cells
of table 3 but contacted with Sb~2~Te~3~ was also fabricated and the
V~OC~ and FF for these are listed in table 4. Compared to what we have
previously accomplished with Sb~2~Te~3~-based back contacts (with no Cu
used during any fabrication step), device performance in this case has
improved dramatically; a treatment time of 10 min appears to be optimum
as was the case for graphite discussed above. However, the light J-V of
the Sb~2~Te~3~-contacted cells of table 3 clearly suggests that a
barrier has formed at the back contact as shown in Fig. 12. The forward
current consistently increases with the treatment time, suggesting that
the amount of Cu added to the CdS is affecting the doping levels in
CdTe. This approach has produced interesting results and it will be
further pursued as a tool to better understand Cu-issues as well as
determine whether long term cell stability can be improved by
eliminating Cu from the back contact process.

Table 4. Solar cell characteristics for cells with CdS treated in a CuCl
solution and contacted with Sb~2~Te~3~.

  ------------------- ---------------- ----------------- -----------------
  Treatment Time      Cell \#          V~OC~ \[mV\]      FF \[%\]
  \[min\]                                                

  5 min               8-6-2..a         760               62.3

                      ..b              760               64.0

                      ..c              750               61.6

                      ..d              750               57.5

  10 min              8-7-1A..a        730               60.6

                      ..b              770               71.1

                      ..c              780               69.1

                      ..d              780               67.0

  15 min              8-6-1..a         750               53.8

                      ..b              740               61.2

                      ..c              720               64.7

                      ..d              660               51.7

  20min               8-7-1B..a        750               49.9

                      ..b              780               55.0

                      ..c              780               54.4

                      ..d              650               41.8
  ------------------- ---------------- ----------------- -----------------

![](media/image13.wmf){width="2.9917322834645668in" height="3.0in"}

**B. CIGS**

In our ongoing effort to improve understanding of the role of defects in
CIGS performance we have focused mostly on known defects associated with
CIGS itself. Primary guidance in these efforts is provided by defect
property calculations provided by the NREL theory group\[1\]. In our
last Quarterly Report we extended the range of these efforts to include
contributions from the substrate. What we specifically targeted was Na
as supplied by the glass substrate. We limited the amount of Na entering
the Mo and CIGS layers by depositing varying thicknesses of Si~3~N~4~ on
the sodalime glass substrate prior to deposition of the Mo. For
reference we provide a summary of those results as follows:

-   Reducing the Na level produces lower Jsc's and Voc's

-   Devices fabricated under single chamber conditions were more
    sensitive to these effects than those produced in our in-line dual
    chamber.

-   We briefly speculated on a mechanism whereby Na catalyzes the
    oxidation of In in the vicinity of V~Se.~ This mechanism is thought
    to favor Cu- poor films.

The third point above is consistent with the second in that conditions
in our single chamber deposition offer more opportunities for oxidation.
Interwoven in the discussion is a possible interplay between Cu and Na.
However, the first result is the one we want to pick up on. It clearly
calls for raising the Na level in our devices, and that is a direction
we have begun exploring.

While it is convenient to add Na by depositing, for example, Na~2~ Se,
we chose instead to attempt modulating the Na level by varying the Mo
thickness. A particular side issue that we hope to gain insights to is
that every time we switch to a new batch of glass we can expect
fluctuations in performance. This, of course, signals the fact that the
substrate is influencing device performance. Clearly it would be
advantageous to understand the underlying mechanisms and be able to
control them. Ideally this would be accomplished by adjusting the Mo
deposition conditions, so we wished to learn to what extent this could
be done.

Our Mo deposition procedure is not unlike that commonly reported in the
literature. It is deposited by RF magnetron sputtering using a 3 inch
diameter Mo target. The important aspects of the deposition are that the
film is a two layer film deposited at two different pressures. Our
typical total film thickness is about 1 μm. About half of the layer is
deposited at a high pressure of about 5 mTorr and the second half is
deposited at about 1.5 mTorr. It is commonly known that the high
pressure layer results in good adhesion, though has higher resistivity.
The second layer is thought to be denser and have lower resistivity. The
film is deposited at room temperature following preheating of the glass
substrate. The preheating is done just above 100 º C primarily to dry
the glass surface. However, this step as well as the entire glass
cleaning procedure influences the surface Na level of the glass.

The devices for this study were deposited in our single chamber system
using our baseline run conditions. Jsc values were determined by
integration of QE response using Si and Ge references calibrated by
NREL. The effect of Mo thickness on Jsc is shown in figure 1. There is a
clear increase of 1 -- 2 mA/cm^2^ when the Mo thickness is reduced below
the 1 µm range. We are postulating that this is at least in part due to
an increase in the Na level. We have preliminary EDS data supporting
that the Na increases with reduced Mo thickness, but the data is not yet
conclusive. The increase in Jsc at low Mo thickness is observed to be
due to an overall upward shift in the QE spectrum. We have modeled such
behavior previously in terms of changes in defect levels in the top
layer of the device. It is not surprising that Na may find its way
there, but this result would then suggest that that region is the most
sensitive to Na.

![](media/image14.wmf){width="3.5in"
height="2.8618110236220473in"}![](media/image15.wmf){width="3.499212598425197in"
height="2.457086614173228in"}

The effect of Mo thickness on Voc is shown in figure 2. As can be seen,
there is little effect down to 6000 Å, then Voc plummets. Again
interpreting this result in terms of Na it suggests a range of
insensitivity for Voc down to 6000 Ǻ at which point something
significant kicks in. The two data points below 6000 Ǻ offer further
insights. At a total Mo thickness of 6000 Ǻ 3000 Ǻ is deposited first at
high pressure, and the remaining 3000 Ǻ at low pressure. In reducing the
thickness further, if the thickness of the upper low pressure layer is
reduced below 3000 Ǻ, loss of adhesion sets in. The data point at 5000 Ǻ
has composition 3000 Ǻ/2000 Ǻ for the high/low pressure layers. The low
Voc of 360 mV is thus the result of a change in stress at the Mo
interface. The data point at 4000 Ǻ has composition 1000 Ǻ/3000 Ǻ and is
seen to have a higher Voc. The effect on Voc then is not just that
associated with Na, but also includes changes in interfacial stress. Jsc
seems to be less affected by stress related issues. Nevertheless, these
results again show Voc and Jsc going in opposite directions with Mo
thickness as the varying parameter. We have observed such behavior
previously that was associated with metal ratios and defect formation,
particularly in the top region of the CIGS. We have focused a lot of
effort on understanding and controlling the mechanisms that affect Voc
and Jsc, and in particular have sought out means of controlling these
parameters independent of each other to optimize performance. The
details of our process recipe are a result of optimizing these
tradeoffs. These new results with Na and stress as additional factors,
provide new opportunities for further optimization.

Based upon the above results it is now clear that Mo deposition
conditions are a more critical factor than we realized. This is
particularly relevant considering the nature of the Mo sputtering
process. Starting with a new Mo target the sputtering environment
![](media/image16.wmf){width="3.677165354330709in"
height="2.333464566929134in"}![](media/image17.wmf){width="3.6251968503937007in"
height="2.4811023622047244in"}![](media/image16.wmf){width="3.677165354330709in"
height="2.333464566929134in"}![](media/image18.wmf){width="3.3751968503937007in"
height="3.322047244094488in"}measured Na content so far also suggest a
role for Na. Further effort will be required to sort this out and
understand what each is contributing.

In figure 5 we show the effect of deposition rate on spectral response
for the devices from figure 3 deposited at low(1.3 Ǻ/s) and high(3.2
Ǻ/s) deposition rates. As can be seen, there is an overall upward shift
in the QE spectrum at high rates. We have simulated such behavior in the
past and have found it to be explainable in terms of interface defects.
This might be attributed to Na catalyzed defect formation in the
interface region. It is not clear how to understand the role of stress
in this regard.

Yet another contributing operational parameter for Mo deposition is the
target voltage. As a new target breaks in the voltage required to
maintain a desired deposition rate is constantly changing. Our typical
standard deposition rate is about 2 Ǻ/s. To reach this level with a new
target results in target voltages in excess of 600 volts. The effect
this has on Voc is shown in figure 6. The deposition rate for this range
of discharge voltages is 2 -- 3 Ǻ/s which is good for Jsc as per figure
3, however, this range is clearly not acceptable for Voc. The data
points between 600 and 700 volts are from a new target that is not yet
broken in. The data point at 400 volts is for a target that has been
broken in. The lower discharge voltage results in higher Voc. In this
case the deposition rate is in the same 2 -- 3 Ǻ/s range, so Jsc's will
also be high. At a practical level this indicates that it is important
to break a new Mo target in before depositing films. However, this can
take a lot of time and waste a lot of Mo, so it is important to
understand the underlying mechanisms so that run conditions can be
adjusted with a new target to cut down on this waste of time and
material.

![](media/image19.wmf){width="3.25in" height="2.3570866141732285in"}

In consideration of previous efforts to modify the back contact the
strong dependence on Voc on the sputtering target voltage is surprising.
In our simulations we showed that the back contact energy can have an
effect on Voc. We tried numerous experiments to alter the back contact
energy and were successful only in sending it in the wrong direction.
The above results, however, may be thought of in these terms. A high
target discharge voltage during Mo deposition results in an unfavorable
back contact energy. More effort will be required to determine the
nature of the Voc dependence and to understand the film growth
mechanisms that cause it.

![](media/image20.wmf){width="3.5in" height="2.95748031496063in"}One
additional piece of data that is useful in sorting out the role of Na is
provided in figure 7. This is the Voc and FF profile for the 5 x 5 array
of devices that we deposit on the 2" x 2" substrate. During CIGS
deposition the Cu source is at the top, In at the bottom, Ga to the
left, and Se to the right. For our purposes here we note that the
devices at the top have more Cu than those at the bottom. For this
sample the Mo thickness was 6000 Ǻ, evenly split between high and low
pressure deposition. This reduced Mo thickness is expected to let more
Na through to the CIGS layers. The Na catalyzed In oxidation mechanism
is reported to be more active in a Cu-deficient region\[2,3\], and the
possible replacement of Cu by Na would also be expected to be more
active in a Cu-deficient region as well. Thus we might expect to see a
top to bottom dependence in the above array. The absence of such a
dependence suggests that Na might not be the dominant parameter under
these conditions. To first order stress would not seem to be dependent
on the metal ratios in the CIGS, so its influence would not be expected
to result in gradients. At this point it seems that stress has the upper
hand in terms of understanding the Mo deposition data. More to follow.

**References**

1.  Su-Huai Wei, S. B. Zhang, and Alex Zunger, *Appl. Phys. Lett*.,
    **72**(4), 3199 (1998).

2.  L. Kronik, D. Cahen, and H. Schock, *Advanced Materials,*
    Communications, September 10, 1997.

3.  D. Cahen and R. Noufi, *Appl. Phys. Lett.,* 1989, **54**, 558.

APPENDIX

![](media/image21.wmf){width="3.341732283464567in"
height="3.325196850393701in"}![](media/image22.wmf){width="3.2992125984251968in"
height="3.3165354330708663in"}