**HIGH THROUGHPUT PROCESSING of CdTe/CdS SOLAR CELLS**

Brian E. McCandless, Wayne A. Buchanan and Robert W. Birkmire

Institute of Energy Conversion, University of Delaware, Newark, DE 19716
USA

**ABSTRACT**

Methods for achieving high throughput and materials yield in processing
\>13% efficient CdTe thin film solar cells are demonstrated, with
emphasis on semiconductor deposition and post-deposition processing.
Chemical surface deposition was used to deposit uniform 100 cm^2^ area
CdS films 50 nm thick at 0.2 nm/sec, with \>80% utilization of solvated
Cd species. Vapor transport at 20 Torr was used to deposit dense CdTe
films, 1-7 μm thick, onto CdS-coated substrates with \>50% utilization
in an unbaffled system. Uniform films have been deposited with
translation at up to 12 cm/min and static equivalent growth rate \>80
μm/min. Vapor CdCl~2~ post-deposition treatments yielded solar cells
with AM1.5 conversion efficiency \>13% for 6 m thick CdTe and \>8% for 1
m thick CdTe.

**Introduction**

Achieving low-cost photovoltaics for terrestrial power generation using
thin film technologies requires translating laboratory-scale cell
developments to the production-scale, with high throughput and good
materials yield. For polycrystalline thin film CdTe/CdS solar cells, the
upper limits of throughput and materials utilization for semiconductor
deposition and processing need to be evaluated with respect to film
properties and cell performance. The upper limits of film deposition
rate and post deposition processing have not been systematically or
quantitatively evaluated with respect to their effects on film
properties and device performance. Such an evaluation can facilitate
refinement and simplification of existing technologies as well as
development of suitable equipment for thin film semiconductor
processing. The present work addresses semiconductor deposition and
post-deposition processing. Chemical surface deposition (CSD) of CdS was
selected for the very high utilization of Cd species, and vapor
transport (VT) deposition of CdTe were selected to unify the advantages
of high deposition temperature for cell performance and growth rate for
throughput. Vapor CdCl~2~ post-deposition processing was used for the
flexibility and control it offers with respect to temperature, time and
CdCl~2~ concentration.

**CdS Deposition**

High efficiency CdTe/CdS devices require uniform, ultra-thin,
pinhole-free CdS films to serve as the heterojunction window layer. CSD
offers several advantages over chemical bath deposition, by allowing the
heated substrate to selectively provide the heat for reaction at the
substrate surface, thereby enhancing heterogeneous nucleation on the
substrate and reducing homogeneous nucleation in the bath, which
increases the utilization of solvated Cd species \[[^1]\]. In practice,
CSD can be accomplished by flow-on, spray, or other methods \[[^2]\].
CSD CdS films were deposited on 10 cm x 10 cm Ga~2~O~3~/SnO~2~-coated
glass (L.O.F. TEC15) from a solution containing 1.5 mM CdSO~4~, 0.15 M
CS(NH~2~)~2~, and 1.8 M NH~4~OH. A 4 min. deposition carried out at
55-60ºC produces 40-50 nm thick films (rate = 0.2 nm/sec). Cd species
utilization is \>80%. Glancing incidence x-ray diffraction (GIXRD)
analysis of as-deposited films indicates increasing crystallinity with
deposition temperature, with wurtzite structure and microcrystalline
order \~ 20 nm for 60ºC deposition (Figure 1). Heat treatment of the
films in argon ambient at 550ºC for 5 minutes (HTA) or CdCl~2~:O~2~:Ar
vapor at 430ºC for 5-10 minutes induces primary recrystallization,
producing sharp reflections of the wurtzite phase. HTA preserves (001)
film orientation while vapor CdCl~2~ treatment induces randomization and
secondary recrystallization (Figure 2). Vapor CdCl~2~ treatment is used
for cell processing, sharpens the optical transmission edge and
increases transparency (Figure 3).

![](media/image1.png){width="3.248611111111111in" height="1.75625in"}

Figure 1. GIXRD pattern of CSD CdS as deposited (As Dep), after anneal
at 550ºC for 5 min (HTA) and after vapor CdCl~2~ treatment at 430C for
10 min (CdCl~2~). CdS peaks at 2 = 20º, 26.5º,28.2º, 44º, 52º and 53º;
remaining peaks due to ITO.

![](media/image2.png){width="1.6069444444444445in"
height="1.6208333333333333in"}![](media/image3.png){width="1.5638888888888889in"
height="1.6208333333333333in"}

Figure 2. Atomic force micrographs of CSD CdS film: as-deposited at 65C
(left) and after vapor CdCl~2~ HT at 430C (right).

![](media/image4.png){width="3.079861111111111in"
height="1.9805555555555556in"}

Figure 3. Normalized optical transmission, T/(1-R), of window layer used
in VT cells.

**Vapor Transport CdTe Deposition**

The VT deposition system previously described \[[^3],[^4]\] was used to
deposit CdTe films down onto moving 10 cm x 10 cm TEC-15 plates coated
with CSD CdS films. In VT deposition, He or N~2~ carrier gas is
saturated with Cd and Te~2~ vapor and then de-saturated at the cooler
substrate. The substrate rests on a graphite susceptor which translates
at an adjustable rate over an array of quartz halogen lamps. Baseline
deposition conditions were established to provide a benchmark for
analyzing processing variations. For routine batch operation, the system
pressure is maintained at 100 Torr while the CdTe source manifold is
heated, then is reduced to 20 Torr as substrate translation at 3 cm/min
begins for deposition, and is finally increased after deposition to
\>100 Torr to suppress re-evaporation from the substrate. Baseline
deposition is carried out at a He carrier gas flow rate of 20 sccm and
source temperature of 800ºC, with a 3 mm wide exit slit located 1.5 cm
above the substrate, producing a CdTe delivery rate of 5 x 10^-6^ mol/s
and a uniform deposition zone 1-1.5 cm wide. CdTe crystals with 6N
purity from Alfa/Aesar were used for all depositions. The growth rate
was found to be invariant with substrate temperature over the range
studied, from 500ºC to 570ºC. The static equivalent growth rates and
utilization of transported CdTe vapor obtained for different source
temperatures and carrier gas flow rates are listed in Table 1. High
deposition rates, up to nearly 100 m/min, were achieved, and utilization
remained constant \~50% except at the highest deposition rate. Scaling
this process up is achievable by increasing the deposition zone area, by
matching the source slit length to the substrate width and increasing
the exit slit width.

Table 1. Static equivalent growth rate and utilization of VT CdTe.

+---------------+----------------+----------------+-------------------+
| T source (C)  | Flow (sccm)    | Rate           | Utilization       |
|               |                |                |                   |
|               |                | (m/min)        | (%)               |
+---------------+----------------+----------------+-------------------+
| 780           | 20             | 6              | 50                |
+---------------+----------------+----------------+-------------------+
| 800           | 20             | 8              | 56                |
+---------------+----------------+----------------+-------------------+
| 820           | 20             | 12             | 53                |
+---------------+----------------+----------------+-------------------+
| 840           | 20             | 18             | 52                |
+---------------+----------------+----------------+-------------------+
| 780           | 20             | 6              | 50                |
+---------------+----------------+----------------+-------------------+
| 780           | 40             | 8              | 49                |
+---------------+----------------+----------------+-------------------+
| 840           | 20             | 18             | 52                |
+---------------+----------------+----------------+-------------------+
| 840           | 40             | 35             | 47                |
+---------------+----------------+----------------+-------------------+
| 860           | 40             | 81             | 7                 |
+---------------+----------------+----------------+-------------------+

The effect of deposition conditions on CdTe film morphology and grain
size is illustrated in the following series of 20 m x 20 m AFM images.
As reported previously \[Error: Reference source not found\], O~2~
partial pressure, \<0.1 Torr, improves lateral grain packing and nearly
eliminates pinholes. All samples were deposited in He ambient containing
\~50 mTorr O~2~ partial pressure. Figure 4 shows increasing grain size
with increasing substrate temperature for 5 micron thick films. Figure 5
shows increasing grain size with increasing film thickness for 550ºC
substrate temperature. Figure 6 shows decreasing grain size with
increasing deposition rate. The appreciable differences measured have a
direct bearing on the effects of post-deposition processing, since
diffusion in grain boundaries significantly enhances overall CdS-CdTe
diffusion during CdCl~2~ treatment \[[^5]\]. In this series, the image
in Figure 6-left corresponds to the baseline deposition.

![](media/image5.png){width="1.5145833333333334in"
height="1.5916666666666666in"}![](media/image6.png){width="1.6493055555555556in"
height="1.6208333333333333in"}

Figure 4. AFM images of 5 m thick CdTe films deposited by vapor
transport on moving substrates in He+O~2~ at 500C (left) and 570C
(right).

![](media/image7.jpeg){width="1.6319444444444444in"
height="1.6076388888888888in"}![](media/image8.jpeg){width="1.525in"
height="1.54375in"}

Figure 5. AFM images of 1 m (left) and 23 m thick (right) CdTe films
deposited by vapor transport on moving substrates in He+O~2~ at 550C.

![](media/image9.jpeg){width="1.5069444444444444in"
height="1.5888888888888888in"}![](media/image10.jpeg){width="1.6319444444444444in"
height="1.6236111111111111in"}

Figure 6. AFM images of 6 m thick CdTe films deposited by vapor
transport on moving substrates in He+O~2~ at 8 m/min (left) and 81 m/min
(right) at 550C.

**Vapor CdCl~2~ Treatment**

Vapor CdCl~2~ treatment yields low surface residue and uniform device
performance, making it an attractive alternative for large-scale
processing \[[^6],[^7]\]. Vapor CdCl~2~ treatment also offers a pathway
for rapid post-deposition treatment by allowing the treatment
temperature and CdCl~2~ concentration to be independently controlled and
by producing surfaces which are free of oxide contamination, reducing
the need for etching. For treatments in which CdCl~2~ is coated on the
CdTe, raising the treatment temperature would simultaneously sublime
CdCl~2~ from the surface and increase diffusion into the CdTe film. The
chemical activity for the diffusion would be \~unity until all CdCl~2~
had sublimed away. With vapor processing, the chemical activity is
controlled by CdCl~2~ partial pressure in the ambient, and shorter
treatment times are achievable by raising the treatment temperature and
reducing the CdCl~2~ concentration. A treatment system for processing 5
cm x 5 cm samples, consisting of a packed-bed CdCl~2~ vapor generator
with N~2~ carrier gas and quartz halogen sample heater, has been
developed \[[^8]\]. Figure 7 shows GIXRD patterns of the surface of VT
CdTe: 1) as-deposited; 2) vapor CdCl~2~ treated; and 3) treated with
solution-applied CdCl~2~ (wet). Baseline CdCl~2~ treatments were carried
out at 415C for 25 minutes. For the vapor treatments, the CdCl~2~
sources were maintained at 400C, which produces a CdCl~2~ partial
pressure of 3.5 mTorr. The GIXRD scan of the as-deposited CdTe shows the
usual CdTe reflections (111), (220), (311) and (400). The vapor treated
sample exhibits a similar pattern. The wet-treated sample, on the other
hand, taken after a water rinse to remove CdCl~2~, contains reflections
from non-soluble phases, indexed as CdO (2 = 33) and a different crystal
form of CdTeO~3~. No grain growth was observed on baseline deposited VT
CdTe, having large as-deposited grains.

![](media/image11.wmf){width="3.372916666666667in"
height="1.9368055555555554in"}

Figure 7. GIXRD patterns of VT CdTe in as-deposited and CdCl~2~ treated
conditions, showing the contrast between wet and vapor treatments.

**Devices**

Baseline VT devices were fabricated by first performing a
post-deposition vapor CdCl~2~ treatment at 415ºC for 20 minutes in
Ar/O~2~ ambient. The CdTe surface was then etched in a three-step "BDH"
process to form a Te layer \[[^9]\]. Primary electrical contact to CdTe
is facilitated by formation of Cu~2~Te. This is accomplished by
sequential evaporation of Cu followed by the current carrying conductor.
The cells are completed by treatment in argon at 180ºC for 30 minutes.
Table 2 lists AM1.5 J-V parameters obtained for the baseline deposition
process and for different deposition conditions and contacts. The J-V
and spectral response behavior of the cell with 13.3% efficiency are
shown in Figures 8 and 9, respectively.

Table 2. Best cell AM1.5 J-V results for devices fabricated with CSD
CdS, baseline VT CdTe and vapor CdCl~2~ treatment.

+-------------+-----------+----------+----------+----------+----------+
| Vapor       | Contact   | Voc      | Jsc      | FF       | Eff      |
| CdCl~2~     |           |          |          |          |          |
|             |           | (mV)     | (mA/     | (%)      | (%)      |
| Temp/time   |           |          |          |          |          |
|             |           |          | cm^2^)   |          |          |
| (C/min)     |           |          |          |          |          |
+-------------+-----------+----------+----------+----------+----------+
| None        | Au        | 570      | 15.9     | 46.9     | 4.2      |
+-------------+-----------+----------+----------+----------+----------+
| 415/25      | Au        | 801      | 23.0     | 71.7     | 13.2     |
+-------------+-----------+----------+----------+----------+----------+
| 415/25      | Ni        | 810      | 23.7     | 70.8     | 13.6     |
+-------------+-----------+----------+----------+----------+----------+
| 415/25      | Cr        | 814      | 23.0     | 62.5     | 11.7     |
+-------------+-----------+----------+----------+----------+----------+
| 410/20      | Au        | 808      | 23.8     | 69.2     | 13.3     |
+-------------+-----------+----------+----------+----------+----------+
| 440/2       | Au        | 634      | 20.4     | 60.2     | 7.8      |
+-------------+-----------+----------+----------+----------+----------+
| 465/2       | Au        | 755      | 24.2     | 60.2     | 11.0     |
+-------------+-----------+----------+----------+----------+----------+

![](media/image12.wmf){width="3.1131944444444444in" height="2.36875in"}

Figure 8. Light (AM1.5, 28ºC) and dark J-V behavior for 13.3% efficient
baseline VT cell.

![](media/image13.wmf){width="3.1416666666666666in"
height="2.4090277777777778in"}

Figure 9. Normalized spectral response (0V, light bias) for 13.3%
efficient baseline VT cell.

In Table 2, the cell processed with no CdCl~2~ treatment suffers from a
poor junction and low current, with 4% efficiency. For cells with
CdCl~2~ treatment at 410-415ºC, comparable cell performance is
demonstrated with Au, Ni and Cr contacts, with best cells having \>13%
efficiency. The last two rows in Table 2 demonstrate that reduced
CdCl~2~ treatment time can be employed but must be offset with increased
treatment temperature to maintain performance at 11% efficiency.
Comparing the short wavelength QE in Figure 9 with the optical
transmission of the CdS in Figure 3, we estimate that the CdS thickness
was reduced during processing by \~20 nm. Not shown are data for cells
made with no intentional Cu, which gave Voc from 740 to 790 mV but FF \<
60% due to severe rollover in forward bias, attributed to the back
contact.

The performance of cells with different CdS thickness and CdTe
deposition conditions but fixed CdCl~2~ treatment and contact are listed
in Table 3. Each row corresponds to a separate deposition. Note that
trials without CdS or Ga~2~O~3~ buffer layers exhibited poor adhesion
after post-deposition processing and cells were not completed. The
initial CdS thicknesses are listed in the table. The first three samples
show constant Voc for 5-7 m thick CdTe with initial CdS thickness of 80
nm, indicating uniform junction quality. Doubling the CdS thickness had
no beneficial impact on the junction behavior but reduced Jsc, verifying
that the baseline CdS coating is sufficiently thick to obtain a high
quality junction. Increasing the growth rate and translation speed
(lower two samples) resulted in poorer junction quality. For the 6 m
thick sample deposited at 81 m/min, this can be understood in terms of
Figure 6-right, which shows that this sample had very fine as-deposited
grain structure. In such a case, the additional grain boundary volume
enhances CdS diffusion into CdTe, allowing more light to reach the
junction, raising Jsc, but also creating discontinuities in the CdS
film, lowering Voc by formation of parallel diodes having higher
recombination current. This sample exhibited secondary
recrystallization, or grain growth, after the vapor CdCl~2~ treatment. A
different argument is needed to explain the last device in the table.
Although it also had small as-deposited grains (Figure 5-left), the
CdCl~2~ treatment temperature was reduced to 390ºC for 15 min, based on
earlier results obtained for PVD cells with 1.3 m thick CdTe \[[^10]\].
In this case, the poorer junction operation is due to intrinsic
properties, not to a loss of CdS. Note that the Jsc is similar to
baseline cells, indicating sufficient CdTe thickness for high current
generation.

Table 3. Best cell AM1.5 J-V results for devices fabricated with
baseline vapor CdCl~2~ treatment (except \*) and with different CdS
thickness and CdTe deposition conditions.

+------------------+------------+--------+---------+-------+--------+
| Window           | CdTe       | Voc    | Jsc     | FF    | Eff    |
|                  |            |        |         |       |        |
|                  | thk/rate   | (mV)   | (mA/    | (%)   | (%)    |
|                  |            |        |         |       |        |
|                  | (m/        |        | cm^2^)  |       |        |
|                  |            |        |         |       |        |
|                  | m/min)     |        |         |       |        |
+------------------+------------+--------+---------+-------+--------+
| 80 nm CdS        | 5/7        | 792    | 23.4    | 66.6  | 12.3   |
+------------------+------------+--------+---------+-------+--------+
| 80 nm CdS        | 6/8        | 808    | 23.8    | 69.2  | 13.3   |
+------------------+------------+--------+---------+-------+--------+
| 80 nm CdS        | 7/10       | 804    | 24.1    | 62.7  | 12.1   |
+------------------+------------+--------+---------+-------+--------+
| 160 nm CdS       | 7/10       | 800    | 21.2    | 63.6  | 10.8   |
+------------------+------------+--------+---------+-------+--------+
| 80 nm CdS        | 6/81       | 736    | 24.8    | 53.4  | 9.7    |
+------------------+------------+--------+---------+-------+--------+
| \*80 nm CdS      | 1/18       | 650    | 23.2    | 54.1  | 8.2    |
+------------------+------------+--------+---------+-------+--------+

**Conclusions**

CSD delivers high CdS growth rate and Cd utilization and yields high
quality CdTe/CdS junctions. For CSD CdS, uniform films deposited with
\>80% utilization of dissolved Cd demonstrated good junction quality in
baseline VT CdTe devices, yielding 13% conversion efficiency. For VT
CdTe, unbaffled batch deposition yields 50% utilization at static
equivalent growth rates up 40 m/min. Much higher utilization would be
expected for continuous deposition since much of the non-utilized CdTe
is lost during the heat-up and substrate translation delay time, and the
chamber would be continuously at steady state. Vapor CdCl~2~ treatment
offers control of CdCl~2~ concentration, temperature and time and yields
a clean CdTe surface. The performance of cells deposited on commercial
SnO~2~/glass substrates with a Ga~2~O~3~ buffer layer, translating at 3
cm/min at 550ºC, demonstrates that high efficiency can be achieved with
a simple, robust process. A post-deposition CdCl~2~ treatment time as
low as 2 minutes was used to fabricate cells with 11% efficiency.
Promising cell results were obtained for cells deposited at very high
growth rates, yielding \~10% efficiency. Finally, VT deposition offers a
path for development of cells with very thin CdTe layers, 1 m thick,
yielding cells with 8% efficiency.

**Acknowledgements**

The authors gratefully acknowledge the technical support of Michael
Angelo, Vicky DiNetta, Ron Dozier, Shannon Fields, Gregory Hanket, Mary
Kondos and Dan Ryan and financial support of the NREL Center of
Excellence, Subcontract ADJ-1-30630-12.

**References**

[^1]: \[?\] B. E. McCandless and W. N. Shafarman, Conf. Rec. WCPEC-3
    (2003)

[^2]: \[?\] B. E. McCandless and W. N. Shafarman, United states Patent
    6,537,845, Mar. 25, 2003.

[^3]: \[?\] B. E. McCandless, R. W. Birkmire, W. A. Buchanan, S. Fields,
    G. M. Hanket, Proc. 29^th^ IEEE PVSC (2002) 547-550.

[^4]: \[?\] R. W. Birkmire, E. Eser, G. M. Hanket, B. E. McCandless,
    United States Patent 6,676,994, Jan. 13, 2004.

[^5]: \[?\] B. E. McCandless, M. G. Engelmann, R. W. Birkmire, J. Appl.
    Phys. 89 (2) (2001) 988-994.

[^6]: \[?\] B. E. McCandless, H. Hichri, G. Hanket, R. W. Birkmire,
    Conf. Rec. 25^th^ IEEE PVSC, (1996) 781-784.

[^7]: \[?\] B. E. McCandless, United States Patent, 6,251,701, Jun. 26,
    2001.

[^8]: \[?\] B. E. McCandless and K. D. Dobson, Int'l Journal of Solar
    Energy (2004) in press

[^9]: \[?\] L. Szabo and W. Biter, United States Patent 4,735,662
    (1988).

[^10]: \[?\] B. E. McCandless and R. W. Birkmire, Conf. Rec. 28^th^ IEEE
    PVSC, (2003) 491-494.