+-----------------------------------------------------------------------+
| ![](media/image1.emf){width="0.9770833333333333in"                    |
| height="0.8333333333333334in"} **Fermilab**                           |
|                                                                       |
| **Particle Physics Division/CDF Upgrade Project**                     |
+-----------------------------------------------------------------------+

**Specification for**

**TRACER_LITE**

Theresa M. Shaw

8/24/99

**TRACER LITE Differences from TRACER**

**The TRACER LITE is a 6U version of the TRACER. It is reduced in
functionality as well as size.**

**The TRACER LITE will NOT provide Clock signals and clock gates to the
backplane**

**The TRACER LITE will NOT provide Trigger signals to the backplane.**

**The TRACER LITE will NOT provide any Local Calibration control.**

**The TRACER LITE wil NOT provide onboard Flash RAM for any constants
storage.**

**The TRACER Lite will NOT provide a path to a Transition module or to
the TBUS lines of the backplane.**

# Important Modifications to Memory Map

The memory map of TRACER LITE was kept identical to the TRACER; but, be
aware that many of the registers used for deleted functionality will now
have no purpose.

**The TRACER LITE is hardwired with a logical address of:**

**A31 - high**

**A30 - low**

**A29 - low**

**A28 - low**

**A27 - low**

**Also be aware, that the FIFO flags of TRACER LITE are different from
that of the TRACER. The TRACER used a Cypress CY7C470 FIFO which is now
obsolete. The TRACER LITE uses a Cypress CY7C260A FIFO.**

**1.0** **Introduction**

The ***TR***igger ***A***nd ***C***lock + ***E***vent ***R***eadout
Module (TRACER) performs the role of system interface for the front end
crates to the rest of the upgraded CDF system. It will be assumed that
the reader is familiar with the readout system described in
CDF/DOC/TRIGGER/CDFR/2288 "A Standard Front-End and Trigger VMEbus Based
Readout Crate for the CDF Upgrade - The CDF Readout Crate".

One of the TRACER\'s functions is to provide an interface to the Master
Clock. The TRACER is used to fanout the precision 132ns clock and three
clocking gates: Beam Zero, Beam Crossing, and Abort. The TRACER does
this by driving the signals it receives from the Master Clock onto the
CDF custom backplane where they are then readily available to all
modules plugged into the crate. No timing adjustment is done to any
signals from the Master Clock. Any custom tuning of the arrival of the
signals will be done in the Clock Fanout Modules.

A second TRACER function is to provide an interface to the Trigger
System Interface (TSI). The TRACER is used to fanout all trigger and
control information received from the TSI. The TRACER receives encoded
information from an optical link, decodes it and passes it onto the CDF
custom backplane. These signals are used by the ADMEMs and other
front-end modules to either pass an event fragment into one of four
Level 2 readout buffers or to throw it away.

The TRACER also provides a path for sending the event data to the VMEbus
Readout Boards (VRBs). Event data may be transmitted in two ways: the
TRACER may act as a \"spy\" on the backplane and place backplane data
into its Event FIFO, or it can receive data written directly into its
Event FIFO from the VRC (VME Readout Controller). Once data exists in
the Event FIFO, a sequencer onboard the TRACER will readout the event
data, serialize it and then transmit the data to the VRB modules over
fiber optic cables. The VRB will transmit the signal VRB_BUSY back to
the TRACER if at any time it cannot accept the next event. If VRB_BUSY
is detected by the TRACER, data transmission will be held off until the
condition clears.

Finally, the TRACER provides a means by which to issue a crate reset.
The VMEbus signal SYSRESET\* will be pulsed low on the backplane if a
reset pulse is detected from the CDF Reset Crate. An RS-422 signal is
sent from the Reset Crate to a TRACER front panel connection if a crate
reset is desired. A crate reset ability is required in the event of a
CPU board hanging. NOTE that this reset ability is separate from the TSI
CDF_RECOVER\~ signal which serves to reset L1 pipeline pointers.

Figure 1 provides a system overview and shows where the TRACER fits in.
Figure 2 provides a block diagram of the TRACER.

![](media/image2.emf)

Figure 1. Block Diagram of Calorimetry DAQ System

![](media/image3.wmf)

Figure 2 Block Diagram of Trigger Fanout/Crate Monitor/Spy Module

**2.0 Interface to the Master Clock**

The TRACER provides a front panel connection to receive a cable from the
Master Clock. The Master Clock will provide the precisely timed 132 ns
clock signal as well as gates which indicate the Beam Zero Crossing,
Beam Crossing and Abort Gaps. The Master Clock signals are received as
differential LVDS signals. The TRACER will provide a 100 ohm terminating
input resistor for each of the signals. A 8-pin Shielded Data Link style
connector will be provided to receive the cable from the Master Clock
(see Appendix C). The shield of this connector will not be connected to
the TRACER's digital ground. The front panel connector pinout will be as
follows:

**[Pin]{.underline}** **[Signal]{.underline}**

1 Master_Clock (132 ns clock)

2 Master_Clock\*

3 Beam_Crossing

4 Beam_Crossing\*

5 Beam_Zero (once around marker)

6 Beam_Zero\*

7 Abort_Gap

8 Abort_Gap\*

The TRACER will receive these signals and drive the following backplane
signals:

CDF_CLK

CDF_CLK\* - 132 ns clock; accurately timed *differential PECL* signal
delivered by the Master Clock.

> CDF_CLK is the only precisely timed signal. All other signals are
> considered gates to the rising edge of CDF \_CLK. All CDF backplane
> signals are guaranteed to be valid for 10ns on either side of the
> rising edge of CDF_CLK.

CDF_BC\* - Beam Crossing (TTL)

CDF_B0\* - Bunch 0 (TTL)

CDF_ABORT\* - Abort Gap (TTL)

The TRACER will simply buffer these signals to the backplane - No timing
adjustments will be done. CDF_B0\~, CDF_BC\~ and CDF_ABORT\~ are active
low gates to the rising edge of the CDF_CLK signal. They are guaranteed
to have at least a 10 ns setup (see Figure 3) and hold time with respect
to the clock edge.

![](media/image4.wmf){width="4.625694444444444in"
height="1.2861111111111112in"}

Figure 3. Backplane Timing Example of CDF_CLOCK and a Clock Gate

**3.0 Interface to Trigger System Interface(TSI)**

**3.1 TSI \<-\> TRACER Optic Link**

The TRACER will provide an interface to the TSI. An optical link using
TAXIchip (AM7969-175JC) protocol, AMP optical receivers (AMP 269050-1),
and operating at two times the CDF_CLK, provides the means for the TSI
to issue commands. The TRACER will take the signals that it receives
from the TSI, decode them and drive the appropriate trigger signals out
onto the custom CDF VMEbus backplane. The TSI \<-\> TRACER protocol is
described in the note \"**Trigger Supervisor Protocols for Run II**\"
written by the CDF Group of Yale University.

The following backplane trigger signals will be driven by the TRACER as
the result of TSI commands:

**FROM TSI Backplane Signal driven by TRACER**

L1 Word bit 2 CDF_L1A\* - Level 1 Accept

bit 3 CDF_L1R\* - Level 1 Reject bit 4 CDF_L2B0\* - Level 1 Accept
Buffer Address 0

bit 5 CDF_L2B1\* - Level 1 Accept Buffer Address 1

bit 6 CDF_GLIVE\* - Level 1 Accept corresponds to live Beam

Crossing

bit 7 CDF_L1_CALIB\* - Indicates L1A event is from a Calibration

bit 8 RSVD_L1W2\* - TSI reserved L1 word bit(8)

L2 Word bit 2 CDF_L2DB0\* - Level 2 Accept Decision Buffer Address 0

bit 3 CDF_L2DB1\* - Level 2 Accept Decision Buffer Address 1

bit 4 CDF_L2A_EN\* - Level 2 Accept Enable signal

bit (8:5) CDF_EVID(3:0)\* - Event Identifier(0)

Calib Word bit (8:2) CDF_CALIB(6:0)\* - Calibration bits which may be
sent by TSI; these currently have no definition

Control Word bit 2 CDF_STOP\* - Set Halt Condition

bit 3 CDF_RECOVER\* - Reset FIFOs/pipelines

bit 4 CDF_TEST\* - Diagnostic bit which will cause TRACER to capture
TAXI link (TSI \<-\> TRACER) data

bit 5 CDF_RUN\* - Clear Halt Condition

bit (8:6) CDF_RL(2:0)\* - Readout List Identifier

**(the following signals are generated by TRACER using above TSI info)**

CDF_HALT\* - Halt filling L1 FIFO/pipelines

\- the HALT condition is set by CDF_STOP\* and cleared by CDF_RUN\*

CDF_CALEN\* - Calibration Enable

\- this is set whenever a TSI Calibration Word is received

CDF_L2A\* - Level 2 Accept

\- this is set whenever a TSI L2 Word is recieved and CDF_L2A_EN\* is
true

CDF_L2R\* - Level 2 Reject

\- this is set whenever a TSI L2 Word is recieved and CDF_L2A_EN\* is
false

All of the above signals are gates to the rising edge of the CDF_CLK
signal. They are guaranteed to have at least a 10 ns setup and hold time
with respect to the clock edge.

**3.2 The Start Scan and Done Registers**

The TRACER will also provide Start Scan and Done Registers which will be
used in communications protocol with the TSI. When the TSI indicates it
is time to read out an event (Start Event Scan), the "Start Scan" bit
will be set in the TRACER's Start Scan Register.

The VMEbus Readout Controller (VRC) can poll this register and begin
readout when it sees the Start Scan bit set, or an interrupt mode may be
enabled by setting the "Interrupt Mode Enable" bit of the TRACER's
Control Register. Interrupt mode causes the TRACER to initiate an
Interrupt cycle upon the reception of Start Scan.

When the VRC has finished its readout cycle, it will write to the Done
Register and set the "Done" bit. The "Done" bit is cleared upon the
reception of the next Start Scan.

**Start Scan Register**

**Description:** Event tagging data for this register comes from the TSI
"Level 2" word.

The "Start Scan" bit is set when a L2 Accept is indicated, and cleared
when the "Done" bit is set in the Done Register.

Bit 16 reflects the state of the open-collector backplane signal
CDF_TDC_DONE.

**[Bit]{.underline}** **[Function]{.underline}**

0-15 Undefined

16 CDF_TDC_DONE

19-17 Undefined

20 Readout List 0

21 Readout List 1

22 Readout List 3

23 Undefined

24 Start Scan

25 L2 Decision Buffer Address 0

26 L2 Decision Buffer Address 1

27 Undefined

28 Event ID 0

29 Event ID 1

30 Event ID 2

31 Event ID 3

**Done Register**

**Description:** The Done bit can be set to a logic high by the VRC,
over VMEbus, when readout is complete. The VMEbus path does not allow
the bit to be set to a logic low. The Done bit will also be set to a
logic high by the "recover" command in the event of a Halt-Recover-Run
sequence.

The Done bit will be set to a logic low with the issuance of a new Start
Event Scan command by the TSI.

The End of Block(EOB) maker may be written over VMEbus. When it is set,
it will cause an EOB to be appended to the data in the Event FIFO. It is
a self-clearing bit and cannot be read back. The EOB marker is an
optional feature - its usage is optional.

Done and EOB have been placed in the same register in order to reduce
the number of VMEbus cycles which the VRC must do at the end of a
readout cycle. Typical usage would have the VRC set both Done and EOB at
the end of a readout cycle. However, if an "early" done is sent to the
TSI, the EOB marker could be sent later, after the data has been
transferred to the Event FIFO.

**[Bit]{.underline}** **[Function]{.underline}**

23-0 Undefined

24 Done (VMEbus can set DONE when bit 24 equals "1",

no reset capability over VMEbus)

30-25 Undefined

31 End of Block (EOB) (write only - self clearing bit)

**3.3 DONE, ERROR and BUSY Signals**

TSI \<-\> TRACER protocol also relies on a parallel copper link which
will allow the TRACER to drive the signals DONE, ERROR and BUSY to the
TSI.

The DONE signal is simply the buffered "Done" bit in the Done Register.

The ERROR signal will be asserted whenever some module in the CDF Crate
is asserting CDF_ERROR\~ on the open-collector backplane signal. The
assertion of ERROR is meant to occur only in the case of a catastrophic
error. It is possible to mask ERROR with a bit in the control register.

The BUSY signal can be asserted to two different ways. The default is to
have the TRACER return BUSY to the TSI whenever the Event FIFO status
flags indicate that the FIFO is greater than half full.

Alternatively, the BUSY signal can be asserted whenever the buffer space
in the VRB (CDF\'s VMEbus Readout Board) becomes full by setting the Bit
0 of the Control Register. A direct optical link between the VRB and the
TRACER, informs the TRACER when the higher level DAQ readout has become
clogged.

This BUSY signal will not be cleared with a Halt-Recover-Run sequence.
In order to clear BUSY, the problem with the status of the Event FIFOs
or with the clogged VRB readout buffers must be fixed.

An eight pin Shielded Modular Data Link Connectors (see Appendix C) will
be provided on the TRACER's Front Panel. The shield of this connector
will be connected to the TRACER's digital ground. The conncector has the
following pinout:

**[Pin]{.underline}** **[Signal]{.underline}**

1 DONE

2 DONE\~

3 ERROR

4 ERROR\~

5 BUSY

6 BUSY\~

7 NC

8 NC

**3.4 TEST Mode**

It is possible for the TSI to turn on input to the TSI Diagnostic FIFO
by sending the "TEST" bit in the TSI Control Word. When "TEST" is sent,
the FIFO is flushed and the next 8K data words received from the TSI are
clocked into a FIFO. In its this operating mode, once the FIFO is full,
no further data recording will be done. In order to repeat the test, the
original "TEST" state must be cleared by toggling the "Reset TSI
Diagnostic FIFO TEST mode" bit in the Control Register.

A second diagnostic mode possible - it will, however, be overriden by
any "TEST" message written from the TSI. In the second mode, it is
possible to save the last \~8K of TSI commands by setting the "Enable
TSI Diagnostic FIFO Save Mode" bit of the Control Register. When this
bit is set the TSI Diagnostic FIFO will be filled by incoming TSI
commands. As the FIFO limit is approached, automatic readout is begun to
clear space for new commands. If at any time a CDF_ERROR\* condition
occurs, the state of the FIFO will be frozen. Hopefully, this will aid
in determining what was going on in the crate at the time of the error.

**4.0 Data Transmission**

The TRACER has an optical data link to the VRB. This link uses the
TAXIchip (AM7968-175JC) protocol and AMP optical driver (AMP 269049-1).
It operates at two times the CDF_CLK.

An 8K by 32 bit Event FIFO feeds this data link. It is possible to fill
this Event FIFO in two ways. One way is to simply do a VMEbus write into
the FIFO. If the VRC is used to do zero suppression and data formatting,
this method would be used. The VRC would first read in raw event data,
do the formatting and then write the formatted data to the Event FIFO.

A second method for getting event data to the VRB would involve using
the TRACER\'s Spy capability. The TRACER will have the capability to spy
on the data as the VMEbus Readout Controller (VRC) reads it out. During
event readout, the TRACER has the ability to clock data into the Event
FIFO. The data which gets clocked into the event FIFO includes any
VMEbus reads of data in the L2 Buffer Space (specified in
CDF/DOC/TRIGGER/CDFR/2288), and any write to the TRACER's Done Register
which sets the EOB marker. This Spy mode would be used only if there is
no need for the VRC to do data formatting.

A sequencer on the TRACER will detect when data is present in the FIFO,
serialize the data through the use of a TAXIchip, and transmit it
upstairs to the Readout Memory (VRB) module via an optical link. The
data can be transmitted to the VRB at a rate of up to one byte every 66
ns (twice the CDF clock). A Taxi Sync signal is sent up at least every 5
bytes; thus, a data rate of 4 Bytes/(5 x66ns), or 12.1 MB/s is
achievable out of the crate.

It is possible to append set an End of Block (EOB) marker on the
transmitted data stream. This is done by writing to the EOB bit in the
Done register. Whenever a logic high is written to this bit, the
equivalent of a 33 bit word will be clocked into the Event FIFO. The
most significant bit will be set high and will indicate the EOB. This
EOB bit will be passed to the TaxiChip as the 9th data bit, which can
then be decoded as EOB by the VRB.

**5.0 Event Data Header Information**

The TRACER will have registers to hold header information which should
be applied to all event fragments which are transmitted to the VRB. The
following header information should mark all events:

Word Count (32 bits) ;downloaded from system or calculated by VRC

Partition ID (3 bits) ;downloaded from system

Crate ID (8 bits) ;downloaded from system

Event ID (4 bits) ;obtained from TSI

L2 Buffer Address (2 bits) ;obtained from TSI

Readout List \# (3 bits) ;obtained from TSI

Calibration Type \# (6 bits) ;obtained from TSI

The Word Count will be used by the VRB as a way of identifying Event
fragments as they pass through it.

This header information can get into the Event FIFO in two ways. If the
VRC is doing event formatting and transmitting the formatted event to
the TRACER\'s Event FIFO, the VRC should apply the header to the
formatted data. In this case, the VRC would need to be told the
Partition ID and Crate ID at start-up. The rest of the header
information would be available to the VRC through (1) reading the Start
Scan register which is being polled in order to know when to initiate
Event readout or (2) reading the Start Scan register upon receiving a
Start Scan interrupt if interrupt mode is enabled.

In the case where the TRACER is in spy mode, and directly stores the raw
event data into its Event FIFO, it is necessary to include the TRACER
word count and header Registers in the beginning of the readout list. As
they are read out, they will be written into the Event FIFO like all
other Event data.

**Word Count Register**

**Description:** this register contains the number of 32 bit words
(inclusive) which make up the event fragment. It must be downloaded if
\"Spy\" mode is used.

**[Bit]{.underline}** **[Function]{.underline}**

31-0 Word Count(31:0)

**Event Header Register**

**Description:** this register contains the minimum amount of
information which must be applied as a header to all event fragments
read out into L3.

**[Bit]{.underline}** **[Function]{.underline}**

7-0 Crate ID(7:0) (r/w)

10-8 Partition ID(2:0) (r/w)

11-15 Undefined

19-16 Event ID(3:0) (r)

21-20 L2 Buffer Address(1:0) (r)

24-22 Scan List #(2:0) (r)

31-25 Calibration #(6:0) (r)

It may also be desirable to mark the end of an event. To do this we
could repeat the Word Count and Event Header information. Two possible
pattern words of A's and 5's will also be available as tags to be added
to these words to aid in the descrambling of event blocks.

**6.0 Reset Function**

It is necessary to provide a remote reset capability for front end
VMEbus crates. The main purpose of the reset will be to reboot a CPU
which has hung. This will be done through the use of a dedicated reset
line which will come in through a front panel connector and be driven by
the CDF Reset Crate.

The reset signal will be driven and received as an RS-422 signal. When
the reset line is pulsed low it will drive the SYSRESET\* line low on
the VMEbus backplane. This will cause all boards to do a reset.

**7.0 TRACER Interrupt Mode**

The TRACER has an interrupt feature which may be used to indicate that a
Start Event Scan message has been received. The enabling of this
interrupt mode is controlled via the "Interrupt Mode Enable" bit of the
TRACER's Control Register. The interrupt feature is provided as an
alternative method to the polling of the Start Event Scan Register.

The Interrupt Level is settable via switches on board, and the set level
is readable through the Control Register.

A separate Interrupt Return Vector Register will allow the user to set
the interrupt return vector.

**8.0 TRACER Front Panel**

**The TRACER Front Panel will contain the following LED indicators:**

**+5V ;LED (red) on when module is powered**

**Module Select ;LED (green) on during VMEbus access**

**TSI_DONE ;LED (green) on when DONE is being returned to TSI**

**TSI_ERROR ;LED (red) on when ERROR is being returned to TSI**

**TSI_BUSY ;LED (yellow) on when BUSY is being returned to TSI**

**The TRACER Front Panel will also hold**

**8-pin Shielded Data Link connector for TSI return signals**

**Connector Ground Shield connected to Board Ground**

**8-pin Shielded Data Link connector to receive Master Clock Signals**

**Connector Ground Shield not connected to Board Ground**

**An optical cable receiver for TSI TAXI-protocol data**

**An optical cable driver for data link to VRB**

**An optical cable receiver for the Busy signal from the VRB**

**An 8-pin module jack to receive a reset signal from the CDF RESET
Crate**

**No ground shield**

**Two 34 pin headers to spy on the special CDF backplane signals (see
Table2)**

**Logic Analyzer Port - On the TRACER**

Tracer Front Panel Ports J will provide ports for easy access to the CDF
backplane trigger and clock signals. These ports will bring TTL level
signals to four 20 pin right angle box headers on the front panel. The
ports can be used by a wide range of oscilloscopes or logic analyzers,
but are specifically designed for ease of use with HP logic analyzers
and the HP Terminator Adapter.

![](media/image5.png){width="5.99375in" height="4.384027777777778in"}

Hewlett Packard Pinout on Terminator Adapter (HP part number
01650-63203)

  -------- ------------------------- --------- ---------------------------
  Pin      Signal                    Pin       Signal

  20       GND                       19        D0

  18       D1                        17        D2

  16       D3                        15        D4

  14       D5                        13        D6

  12       D7                        11        D8

  10       D9                        9         D10

  8        D11                       7         D12

  6        D13                       5         D14

  4        D15                       3         CLK1

  2        CLK2                      1         +5V
  -------- ------------------------- --------- ---------------------------

CDF Signals are connected to the Port as follows:

**Port J4 - POD 1**

  -------- ------------------------- --------- ---------------------------
  Pin      Signal                    Pin       Signal

  20       GND                       19        ***CDF_L2R\****

  18       ***CDF_L2DB0\****         17        ***CDF_L2DB1\****

  16       ***CDF_EVID0\****         15        ***CDF_L2_EN\****

  14       ***CDF_EVID2\****         13        ***CDF_EVID1\****

  12       ***CDF_STOP1\****         11        ***CDF_EVI31\****

  10       ***CDF_TEST1\****         9         ***CDF_RECOVER\****

  8        ***CDF_RL0\****           7         ***CDF_RUN\****

  6        ***CDF_RL2\****           5         ***CDF_RL1\****

  4        ***CDF_HALT\****          3         CDF_CLOCK

  2        No Connect                1         No Connect
  -------- ------------------------- --------- ---------------------------

Port J5 - POD 2

  -------- ------------------------- --------- ---------------------------
  Pin      Signal                    Pin       Signal

  20       GND                       19        ***CDF_CLOCK\****

  18       ***CDF_ABORT\****         17        ***CDF_B0\****

  16       ***CDF_BC\****            15        ***CDF_L1A\****

  14       ***CDF_L1R\****           13        ***CDF_L2B0\****

  12       ***CDF_GLIVE\****         11        ***CDF_L2B1\****

  10       ***CDF_L1RSVD\****        9         ***CDF_CALIB\****

  8        ***CDF_CAL0\****          7         ***CDF_CALEN\****

  6        ***CDF_CAL2\****          5         ***CDF_CAL1\****

  4        ***CDF_L2A\****           3         CDF_CLOCK

  2        No Connect                1         No Connect
  -------- ------------------------- --------- ---------------------------

**9.0 Power Requirements**

**The TRACER uses approximately 5Amps @ 5V for a power consumption of 25
Watts.**

**10.0 VMEbus Slave Interface**

The TRACER will implement a modified version of a VMEbus slave
interface. Only 32 bit aligned data transfers will be supported; these
may be either single word transfers or block transfers. Only extended
(32-bit) addressing modes will be supported. All boards will be assigned
a unique geographical address through use of backplane pins on the CDF
Custom J2 backplane. The TRACER will respond to all address spaces.
Therefore, TRACER modules will respond to the following address modifier
codes: 09, and 0B.

**Memory Map**

YY00 0000 Diagnostic Register (32 bit Read/Write) (r/w)

YY00 0004 Control Register

Please Note all reset lines must be toggled by the user - they are not
self-clearing.

**[Bit]{.underline}** **[Function]{.underline}**

0 Select VRB busy as Trigger System Return Busy source (r/w)

default state - low

0 - TS Busy will be derived from Event FIFO status

1 - TS Busy will be derived from VRB busy

1.  Undefined

2.  Undefined

3.  Undefined

6-4 Interrupt Level (2:0) (r)

*allows readback of the Jumper settings of the interrupt level*

7 Error (r)

*reflects the active state (inverted) of CDF_ERROR\* on the backplane*

8 VRB Busy (r)

*reflects the state of VRB_Busy signal coming from the VRB*

> 9 TSI Diagnostic FIFO FF\~ (r) (Full Flag)

10 TSI Diagnostic FIFO EF\~ (r) (Empty Flag)

11 TSI Diagnostic FIFO HF\~ (r) (Half Full Flag)

> 12 TSI Taxi Error (r)

*TaxiChip violation has been detected*

> 13 Event FIFO FF\~ (r) (Full Flag)
>
> 14 Event FIFO EF\~ (r) (Empty Flag)

15 Event FIFO HF\~ (r) (Half Full Flag)

> 16 Undefined
>
> 17 Enable TBUS Divers (r/w)
>
> default state - low
>
> set high to drive output of TBUS Register onto Backplane (P0) TBUS
> lines

18 Reset the Event FIFO (r/w)

default state - low

*toggle hi-lo to clear the Event FIFO*

19 Reset the TSI TaxiChip Receiver (r/w)

default state - low

*toggle hi-lo to reset TaxiChip*

20 Reset the Event Data TaxiChip Transmitter (r/w)

default state - low

*toggle hi-lo to reset TaxiCh*ip

21 Enable TSI Diagnostic FIFO Save Mode (r/w)

default state - high

*when set, TSI Diagnostic FIFO will save last 8K TSI commands*

22 Reset TSI Diagnostic FIFO "TEST" mode (r/w)

default state - low

*toggle hi-lo to reset "TEST" message from TSI*

23 Reset TSI Diagnostic FIFO (r/w)

default state - low

*toggle hi-lo to reset the TSI Diagnostic FIFO*

> 24 Reset TSI Taxi Error (r/w)

default state - low

*toggle hi-lo to clear TSI Taxi violation error state, and reset the TSI
TAXI Violation Counter Register*

25 Undefined

26 Select CDF Trigger Signal source (r/w)

default state - low

0 - TSI Interface

1 - Local Calibration Sequencer

27 Interrupt Mode Enable (r/w)

default state - low

*when set, enables interrupts when Start Event Scan received from TSI*

28 Mask CDF_ERROR (r/w)

default state - low

*when set, will mask out any errors being sent to the TSI*

29 Event Data Taxi Enable (r/w)

default state - high

*when set, the onboard sequencer will begin reading out the Event FIFO
and streaming the data to the VRB*

30 Spy Mode Enable (r/w)

default state - low

*when set, L2 buffer space data will be captured from the backplane and
put into the Event FIFO*

31 Software Reset (r/w)

default state - low

*resets TSI interface registers*

YY00 0008 Start Scan Register (r)

**[Bit]{.underline}** **[Function]{.underline}**

0 Calibration 0

1 Calibration 1

2 Calibration 2

3 Calibration 3

4 Calibration 4

5 Calibration 5

6 Calibration 6

15-7 Undefined

16 CDF_TDC_DONE

19-17 Undefined

20 Readout List 0

21 Readout List 1

22 Readout List 3

23 Undefined

24 Start Scan

25 L2 Decision Buffer Address 0

26 L2 Decision Buffer Address 1

27 Undefined

28 Event ID 0

29 Event ID 1

30 Event ID 2

31 Event ID 3

YY00 000C Done Register (r/w)

**[Bit]{.underline}** **[Function]{.underline}**

23-0 Undefined

24 Done (VMEbus can set DONE when bit 24 equals "1",

no reset capability over VMEbus)

30-25 Undefined

31 End of Block (EOB) (write only - self clearing bit)

YY00 0024 Interrupt Return Vector Register (32 bit Read/Write) (r/w)

YY10 0000 - YY10 007C ID PROM (upper 8 bits) (r)

YY40 XXXX TSI_Diagnostic FIFO (r)

bits (31:23) represent Taxi bits (8:0)

(holds first 8K data words sent down TSI optic link after the receipt of
the TEST signal)

YY50 XXXX Event Data FIFO (r/w)

YY80 0000 Word Count Register (r/w)

**[Bit]{.underline}** **[Function]{.underline}**

31-0 Count of 32 bit Words in Event Record

YY80 0004 Event Header Register

**[Bit]{.underline}** **[Function]{.underline}**

7-0 Crate ID(7:0) (r/w)

10-8 Partition ID(2:0) (r/w)

11-15 Undefined

19-16 Event ID(3:0) (r)

21-20 L2 Buffer Address(1:0) (r)

24-22 Scan List #(2:0) (r)

31-25 Calibration #(6:0) (r)

YY80 0008 TSI TAXI Violation Counter Register

YY80 000C A's Pattern Register (r)

This word will contain (hex)AAAAAAAA

YY80 0010 5's Pattern Register (r)

This word will contain (hex)55555555