**FPHX prototype test results**

Tom Zimmerman, Fermilab

11/25/08

A limited set of bench tests were performed on the [analog front
end]{.underline} of the FPHX chip at Fermilab. A quick summary of these
tests is given here.

**[Response]{.underline}**

In general, the integrator and shaper analog responses are very similar
to what is predicted by simulation:

![](media/image1.jpeg){width="2.870138888888889in"
height="4.709722222222222in"}

**Figure1.** Integrator and shaper buffered outputs for Qin = 0.5 fC,
Cin = 1.90 pF, all settings at **default** (except for BW = 0).
**Measured gain = 79 mV/fC**.

![](media/image2.jpeg){width="2.870138888888889in"
height="4.709722222222222in"}![](media/image2.jpeg){width="2.870138888888889in"
height="4.709722222222222in"}

**Figure 2.** Qin = 2.0 fC. **Figure 3.** Qin = 5.0 fC

![](media/image3.jpeg){width="2.870138888888889in"
height="4.709722222222222in"}

> **Figure 4.** Qin = 8.0 fC.

As the input pulse magnitude increases from 0.5 fC to 8.0 fC, the shaper
output peaking time changes from 66 ns to 84 ns. This is predicted by
simulation, and is due to the fact that for small signals, the
integrator feedback acts like a resistor (which results in an RC decay),
and for large signals, the integrator feedback acts like a constant
current (which gives a constant and proportionally slower decay rate).

The response of the FPHX over its full dynamic range was measured by
stepping the threshold setting (the DAC for comparator 0) and finding
the input charge necessary to flip comparator 0. The result is shown in
Figure 5. The response is fairly linear, except for the fact that the
slope changes somewhat at around 1.5 fC. This can be seen Figure 6. The
error from the linear fit over the whole range is shown in Figure 7. A
linear fit for just the lower end of the range (\< 1 fC) is done in
Figure 8, showing the different slope. Note that this test was done with
a single comparator, so there is no comparator dispersion effect
present. Dispersion from multiple comparators will add random offsets.

![](media/image4.wmf){width="5.997916666666667in"
height="3.7118055555555554in"}

**Figure 5.** FPHX amplitude response over full dynamic range

![](media/image5.wmf){width="5.997916666666667in"
height="3.7118055555555554in"}

**Figure 6.** FPHX amplitude response zoomed in to \< 2 fC

![](media/image6.wmf){width="5.991666666666666in"
height="4.093055555555556in"}

**Figure 7.** FPHX deviation from linear fit over whole range

![](media/image7.wmf){width="5.997916666666667in"
height="3.7118055555555554in"}

**Figure 8.** FPHX linear fit for Qin \< 1 fC

**[Noise]{.underline}**

\\During testing, it was noticed that the FPHX integrator is prone to
low-level oscillation at about 25 MHz, depending on the programmable
settings. This oscillation can only be confirmed by looking at the
Channel 0 integrator buffer output, since it can be at a relatively low
level and may not result in obviously pathological chip behavior. This
oscillation is undoubtedly due to the fact that on the test bench, none
of the channels (except for Ch. 0) are connected to an input
capacitance. If all channels are loaded (by connecting to a detector,
for example), then this oscillation should disappear. However, this
should be thoroughly checked. No further prototype submissions should
occur until multiple chips have been connected to detectors on one test
board and it is confirmed that no oscillation is present.

The channel-to-channel dispersion in threshold setting is seen to be
around several mV, which is equivalent to several hundred electrons
(rms). This is probably too big if the threshold is set at around 2000
electrons (some channels with the larger offsets will fire randomly).
Either the threshold must be set higher (say 4000 electrons), or the
design must be modified to reduce the dispersion. It is possible to
consider reducing the threshold dispersion by moving some transistors
closer together and increasing the transistor sizes. This is recommended
for the next submission.

The noise was measured on channels 0 -- 14 to look at the effect of
different input transistor sizes. Unfortunately, it was discovered
afterward that low-level oscillation was probably present for some of
the measurements. Even so, the pattern is fairly clear and the input
transistor choice obvious. The noise intercept measurement is done with
the channel wire bond removed. The lowest noise for a discrete added
input capacitance of 1.90 pF plus wirebond capacitance of approximately
0.3 pF is around 300 electrons. This is obtained with an input W/L of
222/0.6 or 168/0.6, under the condition of no oscillation. The 112/0.6
input transistor results may have been somewhat contaminated by
oscillation, but in any case gives higher noise than channels 0 and 2.
The channel 0 (W/L = 168/0.6) noise slope was initially measured at 64
e/pF, but this measurement was found to be done with low-level
oscillation present. Without oscillation, it was measured at 56 e/pF
(this value shown in Table 1). Channels 0 and 2 give essentially
identical noise results, so W/L = 222/0.6 is a good choice for input
transistor dimension.

# Table 1. Noise vs. input transistor W/L

  --------- --------------- --------------------- --------------------------
  **Ch#**   **W/L**         **Noise slope (e)**   **Noise intercept (e)**

  0         168/0.6         56                    \--

  1         112/0.6         66                    172

  2         222/0.6         56                    169

  3         140/0.25        110                   194

  5         280/0.25        98                    190

  6         112/0.32        90                    208

  9         112/0.45        79                    176

  11        252/0.45        62                    162

  12        84/0.8          68                    165

  14        196/0.8         72                    180
  --------- --------------- --------------------- --------------------------

**[Noise vs. input transistor bias current setting]{.underline}**

The noise was measured on Channel 0 (168/0.6) for different settings of
P1Sel, which controls the DC bias current through the input transistor.
The results are shown in Table 2. The discrete input capacitance (not
including bondwire stray C) for this set of measurements was Cin = 1.9
pF, and all other settings were nominal, except for BW = 2.

# Table 2. Noise vs. input transistor bias current

  ------------------------ ------------------------ ----------------------
  **P1Sel**                **Bias (uA)**            **Noise (e)**

  000                      10                       366

  001                      14                       323

  101                      30                       294

  111                      38                       287
  ------------------------ ------------------------ ----------------------

The noise level is not very sensitive to bias current, therefore it may
be desirable to trade power for noise. For example, P1Sel could be set
to 010 or even 000 to reduce power. The BW parameter should then be set
accordingly.

![](media/image8.jpeg){width="2.979861111111111in"
height="3.2645833333333334in"}![](media/image9.jpeg){width="2.988888888888889in"
height="3.2715277777777776in"}

**Figure 9.** Integrator and shaper out for different settings of BW and
P1Sel (Cin=1.90pF)

**[Comparator output histograms]{.underline}**

A number of histograms of the Ch. 0 buffered comparator output are shown
in Figures 9 and 10. For a given input capacitance, histograms are taken
for three different input charge magnitudes, representing three points
on the S-curve: 88%, 50%, and 12%. The histograms show the average delay
and comparator pulse width (for nominal settings) and the effect of
noise.

![](media/image10.jpeg){width="2.6347222222222224in"
height="4.304166666666666in"}![](media/image11.jpeg){width="2.6256944444444446in"
height="4.299305555555556in"}

![](media/image12.jpeg){width="2.6458333333333335in"
height="4.368055555555555in"}

![](media/image13.jpeg){width="2.6972222222222224in"
height="4.370138888888889in"}![](media/image14.jpeg){width="2.720138888888889in"
height="4.39375in"}![](media/image15.jpeg){width="2.7256944444444446in"
height="4.427083333333333in"}

**[Test pulse]{.underline}**

One source of confusion about the digital test pulse is that it is
triggered by a **high-to-low** transition on the inject input line, not
low-to-high. If low-to-high is desired, it would be a trivial change in
the next prototype submission.

The analog test pulse was used for all bench tests. The inject capacitor
is very close to nominal (25 fF). There is a small parasitic from the
test pulse input to all channels (fraction of a fF), so that even if a
channel is masked off, it still receives a small charge injection (on
order of 1% of the magnitude it would get if it were not masked).

There is almost no crosstalk between neighbor channels. If a large test
pulse is given to one channel, its immediate neighbor sees no more than
a channel located at the opposite end of the chip.

The output pulse shape is somewhat dependent on the number of channels
receiving the test pulse. See Figure 12. Adding a bypass capacitor to
the BIAS pin has little effect. However, this problem seems small enough
to be buried in the noise.

![](media/image16.jpeg){width="3.170138888888889in"
height="3.473611111111111in"}

**[Comparator speed]{.underline}**

The comparator speed can be adjusted with two programmable parameters,
P2Sel (mainly rising edge delay) and P3Sel (mainly falling edge delay).
The following comparator histograms in Figure 13 illustrate the effect
of these parameters. In all cases, the input signal magnitude is
adjusted so that the comparator trips 50% of the time. The resultant
leading-edge delay and pulse width measurements (*average*) are given.
Faster comparator speed results in slightly higher noise, but less than
a 10% increase worst case.

![](media/image17.jpeg){width="2.986111111111111in"
height="3.2715277777777776in"}![](media/image18.jpeg){width="2.966666666666667in"
height="3.2506944444444446in"}

![](media/image19.jpeg){width="2.982638888888889in"
height="3.261111111111111in"}![](media/image20.jpeg){width="2.957638888888889in"
height="3.2402777777777776in"}

**Figure 13.**