**DFE Meeting**

Present: Mrinmoy Bhattacharjee, Fred Borcherding, Jerry Blazey, Stefan
Gruenendahl, Jamieson Olson, Levan Babukhadia, Yildirim Mustaf; Manuel
Martin, David Evans.

**Status of DB Assembly**

SWDBs testing has resumed at the CD. All twenty-one boards remaining at
Feynmann have problems. Three boards have been recently re-examined and
each had bit errors in the inputs or links. The CD technician will
examine the boards and prepare evaluations reports. Jamieson plans on
using the reports and completing the tests and repairs himself.

Circuit Service has had difficulty with the software that controls
temperature profiles and estimates a week will be required to repair the
software and mount FPGAs on the sample DWDB. Jamieson will contact
Circuit Service to discuss a visit and opportunities to assist.

The only difference between the DWDBs and successfully assembled SWDBs
are the board size and the plating. The DWDBs have gold plating that may
fail under heating. Jamieson will discuss the plating with the vendors
to see if they have a preference. In a week's time, if no progress has
been made with construction of the DWDBs we will start investigating
additional vendors.

The socketed board built by NexTek is under test. There are many opens
between the pin socket and the pad. NexTek is using the same methodology
(heating the entire board) as the previous unsuccessful vendors. \[Note
added in proof: The testing has been completed and over 100 open
connections discovered. The board will be returned to NexTek. Jamieson
is arranging a conference call to discuss process improvement.\]

**Specification of FPGAs**

All DB FPGAs are on hand except those required for the CPSst and STT
boards. Levan and Manuel will make recommendations for the size and
number of gates at the Thursday (June 21^st^) trigger meeting. Jamieson
will provide a current FPGA inventory listing so that the recommendation
can include spares.

# Mixer Schedule

The mixer schedule has not been modified since the last meeting. A few
ideas for accelerating the schedule were bandied about that could shave
2-3 weeks off the schedule. If the risk is acceptable, the cards could
be manufactured immediately on five-day turnaround. Stuffing of the
cards (a point of no return since lead-times for parts are six weeks or
more) could occur as soon as testing is complete. A minimal test might
be error free communication between two boards via the backplane. D0
personnel could also assist with board checkout. Fred will arrange a
meeting with the CD engineers to discuss these options.

**Occupancy Trigger**

The DFE occupancy trigger code has been written and has been debugged in
simulations. The data-pump will now be used to provide four inputs to
the DFE. After the four-input test an AFE-DFE pair will be tested on
DAB3.

The latest software has been downloaded to the AFE. There is still
difficulty with the frame markers. The AFE is generating two markers.
Likely the AFE needs both firmware and hardware modifications to
condition the signals. This will require consultation with John
Anderson. This problem is seriously impeding progress with platform
commissioning and is currently the highest priority. Fred, John, and
Stefan will continue to address the issue.

**Understanding the data delivered to Examine (Mrinmoy)**

The "mangling" of the readout form the DFEs to L3 has been corrected,
and the "bare-bones" examine is now working. The new code will be
released in CVS by the end of the week. Mrinmoy will contact the other
examine authors when appropriate.

Further progress awaits readout of a greater number of events. With the
current configuration readout is usually unsuccessful on an
event-by-event basis because of the lack AFE control signals. No effort
will be expended on correcting this. A large number of events must wait
until event control on the platform is available.