# SUBCONTRACT TITLE: *ADVANCED PROCESSING OF CdTe- AND CuIn~X~Ga~1-x~Se~2~- BASED SOLAR CELLS*

# 

# SUBCONTRACT NO: NDJ-2-30630-18

# REPORT FOR: Phase I/Quarter III

# 

# SUBMITTED TO: Ken Zweibel

#  National Renewable Energy Laboratory

# PRINCIPAL INVESTIGATORS: C. S. Ferekides and D. L. Morel

# University of South Florida

# Department of Electrical Engineering

# 4202 East Fowler Avenue

# Tampa, FL 33620

# 

# 

This is the progress report for the 3rd quarter of Phase I for the
months of July '02 through September '02. The project covers two thin
film technologies: CdTe and CIGS. The focus areas include: (a) CdTe --
stability, novel back/front contacts, and the development of
manufacturing friendly processes; (b) CIGS -- development of two-step
non-co-evaporation technology.

A. CdTe

Stability

In our previous report we indicated that we were initiating a study on
stability that included devices annealed with varying CdCl~2~ heat
treatment (CdCl~2~ HT) conditions. Average initial solar cell
performance data have been provided in a previous report. In this report
we provide some of the initial results from this study. The cells are
being light soaked in 4 hrs ON/4 hrs OFF time intervals. The light
intensity is equivalent to 100 ±15% mW/cm^2^. The cells are being kept
in a chamber which is continuously being purged with high purity N~2~
(after having been evacuated several times). The temperature of the
sample stage is monitored and *the J-V measurements are being taken at
the "operating temperature" under illumination*. Cell temperatures are
estimated to reach 60°C. The only data available to-date are light J-V
characteristics; additional characterization will be carried out at a
later time when the cells are removed from the stress chamber. Initially
the cells were measured during every 4 hour interval, but currently data
is collected twice a week. The *light J-V characteristics are measured
twice during the ON cycle, during the first and during the fourth hour*,
to determine whether the cells exhibit any transient behavior. Figure A1
in the appendix shows the temperature of the sample stage during the ON
cycle as measured at two locations on the sample stage[^1]. Typically,
for each processing condition, two devices are held at J~SC~ and two at
V~OC~.

Figures 1 and 2 show the V~OC~ of four cells (from the same substrate)
CdCl~2~ HT at 400°C -- i.e. optimum range - and being light soaked at
V~OC~ (Fig. 1) and J~SC~ (Fig. 2). The V~OC~ measured during the 4^th^
hour of the ON cycle appears to be consistently 20-30 mV lower than the
value measured during the 1^st^ hour. Based on the cell operating
temperature and the profile shown in appendix A, this difference could
be entirely attributed to a rise in temperature and therefore it is not
due to any transient mechanisms. Overall all devices appear to exhibit a
drop of approximately 30 mV in V~OC~ during the first 200 hours of light
soaking. Although, the V~OC~ of devices light soaked at J~SC~ appears to
be 10-20 mV lower than the V~OC~ of those kept at V~OC~, it is too early
at this time to identify any significant differences in the behavior of
V~OC~ due to the sample bias conditions.

![](media/image1.wmf){width="4.614566929133859in"
height="3.8019685039370077in"}![](media/image2.wmf){width="4.611023622047244in"
height="3.805511811023622in"}

The FF's for the cells of Figs 1 and 2 are shown in Figs 3 and 4. The
devices being stressed at V~OC~ exhibit an increase in their FF during
the first 100 hours, which subsequently has leveled off, and
![](media/image3.wmf){width="4.623622047244094in"
height="3.8165354330708663in"}![](media/image4.wmf){width="4.633464566929134in"
height="3.798031496062992in"}seems to be slightly decreasing (to-date it
remains at higher levels than the initial values). The FF of the cells
kept at J~SC~ has undergone an initial decrease during the first 100
hours, and currently appears to be increasing. No significant
differences exist in either case, between the measurements taken during
the 1^st^ hour of light soaking and those taken approx. 3 hrs later.
Therefore, the observed FF changes appear to follow "opposite" trends --
at least during the initial stages of light soaking - for the cells kept
at V~OC~ vs. those kept at J~SC~.

Appendix B (Figs B1 and B2) contains similar data for cells CdCl~2~ heat
treated at 380°C; this condition is at the low temperature end of a
range considered to be "optimum" for the CdCl~2~ HT. These devices
exhibit subtle differences compared to the four devices of Figs 1
through 4. The V~OC~ for the cells light-soaked at V~OC~ remains
relatively unchanged compared to those kept at J~SC~, which show a
gradual decrease (the change in V~OC~ due to the rise in temperature is
also evident in this data set). The FFs of the devices kept at V~OC~
increased slightly (currently appear to be leveling off) similar to the
cells CdCl~2~ HT art 400°C; the cells kept at J~SC~ exhibit a gradual
decrease in the FF, unlike the cells HT at 400°C. It is noteworthy that
one of the devices included in Fig B2 (the lowest FF; less than 50%) is
exhibiting a very "stable" FF to this point (after 200 hrs of light
soaking). Although the initial J-V characteristics of this cell
exhibited excessive shunting, its present characteristics remained
essentially unchanged, unlike the rest of the cells discussed in this
report. The overall behavior of V~OC~ and J~SC~ is in general similar
for the cells CdCl~2~ HT at 400 and 380°C, with the only difference in
the FF of the sample HT at 380°C and kept @ J~SC~.

Figure B3 shows the J-V characteristics of the two cells CdCl~2~ HT at
400°C and held at V~OC~ during the light soaking process (cells of Figs
1-4). The changes in these cells can be summarized as follows:

(a) The devices exhibit an increase, in what we'll refer to in this
    discussion as "dark shunting"; this is evident from the increase in
    the dark current at low voltages. It is difficult to estimate
    changes in junction parameters, such as A and J~O~, due to the
    extensive shunting effect.

(b) The linear J-V shift towards lower voltages (approximately 0.2
    volts); this shift was observed in the past in devices thermally
    stressed while kept in the dark; more recent measurements based on
    monochromatic light J-V seem to suggest this "shift" is due to
    changes in CdTe and not necessarily in CdS as we have previously
    claimed. However, this issue will be further addressed as we expect
    to measure the monochromatic characteristics of these cells when
    they are removed from the stress chamber.

(c) The light J-V of these cells show a lower V~OC~ after light soaking,
    but as noted in the figure, the initial measurements were taken at a
    lower temperature, and therefore only a small part of the V~OC~ loss
    is real (about 20-30 mV). These data also indicate a change in the
    light series resistance after light soaking (lower).

(d) An apparent small loss in J~SC~ may be due to variations/changes in
    the light intensity in our stressing system and at this time no
    conclusions can be drawn from these data. We have collected SR data
    for all devices which we'll use to determine if J~SC~ changes during
    the light soaking process.

(e) The light shunt resistance remains in a range that does not impact
    the FF significantly (greater than 2kΩ-cm^2^). We have recently
    changed our method of measuring R~SH~; we now base our measurements
    on the slope of the light J-V at a reverse bias of at least 1-2
    Volts, instead of using the slope at J~SC~. The slope at J~SC~
    includes collection losses and often does not represent R~SH~.

Similar data are shown in Fig B4 for the cells CdCl~2~ HT at 400°C but
held at J~SC~. Although some of the observed changes are similar there
also exist differences between these devices and the ones of Fig B3
described above.

(a) The dark shunting has increased as was the case for the cells held
    at V~OC~. Again, extracting junction parameters A and J~O~ is not
    possible.

(b) The shift (linear J-V) toward lower voltages is much smaller
    suggesting that the CdTe is affected to a lesser extent (assuming
    that the shift is due to changes in the CdTe properties).

(c) The similarity in the slopes of the light J-V (linear) data,
    suggests that the light R~S~ remains unchanged.

These results represent a fraction of the entire data set currently
under study, and the complete data set will be presented in future
reports. Based on the results included here, there exist distinct
differences in cell behavior depending on bias (which has been shown
numerous times by others in the past) or processing method. It is
anticipated that further light soaking will further enhance these
differences and provide more insights on the mechanisms responsible for
degradation in CdTe cells.

Vapor Chloride Treatment

Our work with the vapor CdCl~2~ HT (VT) has recently focused on all-CSS
devices (i.e. both CdS and CdTe deposited by the CSS process). Early
experiments suggest that all-CSS devices behave differently than cells
based on CBD-CdS when subjected to the VT process. This was expected
based on our past experience with all-CSS cells. Our efforts are now
focused on optimizing the CdCl~2~ vapor process for all-CSS devices, and
plan to study the effect of temperature, time and ambient. Currently the
performance of such devices is limited by relatively low V~OC~'s and
FF's which are in the mid to high 700's mV and mid 60's respectively.

TCO's/Buffer Layers

![](media/image5.wmf){width="3.319291338582677in"
height="3.152755905511811in"}We recently investigated the role of
In~2~O~3~ as a "buffer" layer (i.e. high resistivity). Indium oxide
films are reactively sputtered from an Indium target in oxygen ambient.
The resistivity of these films is in the range of 0.1 -- 12 Ω-cm
depending on the deposition temperature. The main objective is to
determine whether "thin" CdS films can be effectively utilized with
In~2~O~3~ as a buffer layer, and if possible improve on the performance
of cells with SnO~2~ buffer layers. The spectral response of several
cells with In~2~O~3~ as a "buffer" and CdS of varying thickness is shown
in Fig. 5. One of the interesting features in these data is the fact
that the increase in the blue response is not accompanied by losses in
the red (collection). On the contrary it appears that collection in the
700-850 nm range increases with decreasing CdS thickness. The V~OC~'s
for all devices were above 820 mV, and the FF's were 64-72%, with the
lowest FF resulting from the thinnest CdS cell. Further analysis of
these cells is underway along with fabrication of "baseline" cells to
provide a benchmark for evaluating the performance of In~2~O~3~.

Large Area Deposition System

We are continuing to evaluate the thickness uniformity of the large area
CdTe films. During this phase, we received the repaired large area
heaters and installed them in the system. After partially optimizing the
deposition process for thickness uniformity, we begun experimenting with
depositions on moving substrates. The substrates are initially
positioned away from the CdTe source; once the substrate and source
temperatures are adjusted to their desired values the substrate carrier
rolls at a constant speed over the source and eventually passed it. We
currently use two substrate configurations. In a single deposition we
can coat one large substrate (10 x 10 cm^2^) or four small ones (3 x 3
cm^2^). We have already deposited films with thickness uniformity of
±15% and are currently processing these into cells. As the thickness
uniformity is currently deemed satisfactory, we will now turn our
attention to optimizing the process for solar cell performance.

Appendix A

![](media/image6.wmf){width="4.633464566929134in"
height="3.8165354330708663in"}

Appendix B

![](media/image7.wmf){width="7.5in" height="3.1133858267716534in"}

![](media/image8.wmf){width="7.5in" height="3.0811023622047244in"}

![](media/image9.wmf){width="3.230708661417323in"
height="8.993700787401576in"}![](media/image10.wmf){width="3.245275590551181in"
height="8.997244094488188in"}

![](media/image11.wmf){width="5.993700787401575in"
height="8.32283464566929in"}

B. CIGS

**CIGS Processing**

In previous reports we have been discussing our observations regarding
processing details in our new in-line chamber. The main idea of the new
chamber was to allow deposition of the Cu/Ga precursor layers in a
selenium-free environment. We expected improvements in Voc, and there
have been. However, we are also learning of additional complexities of
our process that were not apparent or even accessible using single
chamber processing. In transferring our process to the new in-line
chamber there were three primary differences in device performance.

-   We had to lower the Ga layer thickness from our standard 600  to
    400  to achieve adhesion.

-   While the band gaps of our good devices from the single chamber were
    typically in the range 0.98 -- 1.03 eV, band gaps in the new chamber
    were always at 0.95 eV. We tentatively associated this with the
    lower Ga level.

-   In the single chamber our QE plots were typically square with Jsc's
    regularly at 40 mA/cm^2^. In the new chamber Jsc's are lower due to
    drop-off toward the red in the QE spectrum.

![](media/image12.png)

We first address the concerns that we had expressed regarding deposition
of the Cu/Ga precursor layer in the presence of background Se. An
obvious question is whether the Ga layer, the Cu layer or both are
adversely affected by the presence of Se. To sort this out we deposited
the Cu layer in chamber 2 that should have a background flux similar to
that in the single chamber. We then transferred the substrate to chamber
1 to deposit Ga in the selenium-free environment. Following Ga
deposition the substrate would then follow the standard procedure of
transfer to chamber 2 for In/Se deposition and selenization in Se flux.
The initial results from this sequence were a bit confusing, and it was
only after several runs that we noticed an interesting pattern emerging.
A major new occurrence was the occasional production of devices with
band gaps in the 1.1 eV range. Using our standard process for the
in-line chamber we have not seen band gaps above 0.95 eV, so the
up-shift in Eg is clearly attributable to the new process sequence.
However, the shift is not consistent. It seemingly comes and goes from
run to run. Voc's are jumping around as well. We suspected that this
again has to do with the environment inside the chamber and proceeded to
test the effect of those conditions. To sort this out we vented one or
the other of the chambers or both before runs and then tracked behavior
in subsequent runs. The results of a recent run sequence are shown in
figure 2. Prior to run 12 both chambers(c1 and c2) were vented. As
indicated, the device peeled from the substrate. In run 13 Voc was 320
mV and in 14 and 15 up to 440 mV. Prior to run 16 c1 and c2 were vented
again, and Voc dropped down to the 380 mV range. Before run 18 only c2
was vented. There was already some evidence that Voc was climbing, and
in run 19 it was up to 450. C2 was again vented before run 20 and Voc
dropped slightly to 430 mV. It is apparent that the primary cause of the
Voc swings is venting chamber 1. A smaller effect may be attributable to
chamber 2. The bottom line is that Voc is down by about 70 mV following
venting. These swings in Voc
![](media/image13.wmf){width="4.0582677165354335in"
height="2.3751968503937007in"}are accompanied by band gap shifts as
well. Since this was not observed previously, it is clear that the
combination of depositing Cu in chamber 2(notably in the presence of Se)
and the condition of the chambers relative to venting are dramatically
affecting the band gap and Voc's. The results attained thus far support
an explanation based upon the formation of Cu~x~Se~y~ species in chamber
2, and the discussion that follows is based accordingly. However, we
have not yet completely ruled out the possibility that the moisture
level in chamber 1 is by itself responsible for the results.

These observations from the process sequence modification are helping to
understand the three issues listed above for the new chamber. First, the
need to lower the Ga thickness to 400  to achieve adhesion is likely
due to the fact that all of the Ga was not being properly incorporated
into the film. As indicated, there was no band gap shift as well,
another sign that Ga was not entering the lattice in large quantities.
In the modified process apparently the deposition of Cu in the presence
of a background Se flux produces a Cu~x~Se~y~ species that facilitates
the incorporation of Ga. This results in a band gap shift and
effectively utilizes the available Ga. However, this does not occur if
the chamber is not adequately pumped. It takes a couple of runs after
venting before the effect kicks in. The likely culprit is water vapor.
In chamber 1 where the metals are deposited the turbo pump achieves
pressures in the low 10^-6^ T range. While this is acceptable for
deposition, it takes a long time( a couple of runs) to lower the
residual water vapor to an acceptable level. In the single chamber
system we apparently achieve acceptable levels of residual water vapor
by pumping for only a couple of hours before conducting the depositions.
This is due to the combination of a large diffusion pump and LN2 cold
trap on this chamber.

The issue having to do with drop off in the QE spectrum toward the red
for the standard process in the new chamber is also likely associated
with this same effect. That is, we have discussed numerous times that
improperly bonded Ga results in defects that hurt performance.
Apparently in the absence of this Cu~x~Se~y~ species even the reduced
400  thickness of Ga is not properly bonding. The Ga is entering the
bulk of the absorber film, and some fraction of it is entering the space
charge region. However, an insufficient amount is forming CIGS to raise
the band gap. The residual improperly bonded Ga is creating defects that
are lowering the collection efficiency and resulting in drop-off in the
red QE.

Another interesting observation that is tied-in to Ga bonding is that
the band gap seems to shift from 0.95 up to 1.1 eV in a bimodal fashion.
That is, a continuum of band gaps between these two end points is not
accessible. This leads into the issue of how we determine band gap. This
can get a little tricky because the slopes of the band edge absorption
can change as well as shifting of the edge. We are presently analyzing
the QE spectra from a sequence of runs to sort this out and will report
our findings in the next report.

![](media/image14.wmf){width="3.3751968503937007in" height="2.9in"}These
results and observations are surprising and a bit perplexing. We had
determined that the formation of Cu~x~Se~y~ and Ga~x~Se~y~ species due
to background Se during deposition of the metals in the single chamber
system was limiting performance. Now it seems that we are confronted
with the observation that we nevertheless need a small amount of these
species to achieve proper Ga bonding. While this is somewhat of a
conundrum, it may also be an opportunity. In the single chamber system
these species are inherent, however, we likely always have more than we
need, and the excess is harmful. In the new chamber we have none in the
original configuration, but can modify the process to generate whatever
level we desire. These experiments are currently under way. We hope to
find that there is a peak in performance between these two end points
that will result in improved performance.

These results are important from a fundamentals perspective. They
indicate that it may not be possible to achieve proper Ga bonding if Ga
is not provided a preferential opportunity over In to enter the lattice.
That is, the process must first allow Cu, Ga and Se to interact in the
absence of In in sequential deposition processes. CGS may be a key
precursor. While this may be generic to all sequential deposition
processes that utilize solid source selenization, it does not apply to
the same extent to those processes utilizing H~2~Se. Providing Se that
is bonded to H allows free Ga to compete more effectively with In to
form compounds.

**ZnSe Buffer Layers**

![](media/image15.wmf){width="3.4338582677165355in"
height="2.9598425196850395in"}

![](media/image16.wmf){width="3.367322834645669in"
height="2.6271653543307085in"}In our last report we reported preliminary
results for ZnSe layers that are intended as buffer layers to replace
CdS. We showed data that indicated that the optical properties were
influenced by the presence of Se flux during ZnSe deposition. On closer
examination it appears that the primary effect of the flux was a
reduction in the ZnSe sticking coefficient. There are nevertheless
subtle effects on the film properties, but these are difficult to
observe through standard optical procedures. Consequently we decided to
start incorporating the layers in devices as a more sensitive way of
observing their properties as well as their behavior as buffer layers.
Devices were deposited in standard format. ZnSe was deposited by
evaporation in place of the CBD CdS layer. For these devices the ZnSe
was deposited in the CIGS chamber, although there was a vacuum break
following CIGS deposition. The usual two-layer ZnO deposition then
followed in a separate chamber. A variety of Se flux profiles and
substrate temperatures were tried. Unfortunately to date none of the
variations that we have tried has resulted in even reasonably good
performance. Although this is disappointing, it is nevertheless useful
to understand why performance is poorer than the other zinc-based buffer
layer options. In figure 3 we show the IV curve that is typical of the
results. In this case there was no Se flux and the layer was deposited
to a thickness of 200  at room temperature. As can be seen, all
parameters are low. The primary telltale, however, is the slope under
reverse bias. This indicates a significant carrier collection loss
problem. Our early thoughts on this are that the ZnSe layer is too
resistive and is causing parasitic voltage loss. The QE plot for a
companion device is shown in figure 4. The integrated Jsc is 11.6
mA/cm^2^, and as can be seen, the profile is square, but the entire
curve has been shifted down nearly a factor of four relative to a
typical CdS device. In fact, if the proper Jsc of 40 mA/cm^2^ were being
generated, based upon the dark IV curve Voc would exceed 400 mV as
expected. This offers some hope. The dark IV is reasonably proper, so
the overall performance shortfall is related to carrier collection.

We have observed such behavior previously with the undoped ZnO layer in
standard CdS buffer layer devices. In figure 5 is shown IV data for
standard ZnO(doped)/ZnO(undoped)/CdS/CIGS devices as a function of the
undoped ZnO layer thickness. The stretching out of the IV curve as the
thickness increases is evident, and gives rise to a large slope under
reverse bias similar to that above for ZnSe buffer layer devices.
However, unlike ZnO the IV curve for ZnSe above does not exhibit
substantial crossover. We observe some crossover in for other ZnSe
devices, but it is substantially less than that for ZnO. We have been
simulating the behavior exhibited by the various buffer layer options
with AMPS and are gaining insights to the underlying mechanisms.
Crossover, for example seems to arise from a combination of factors
rather than a single one. Further details will be provided in upcoming
reports. Meanwhile we will continue efforts to relax the parasitic
voltage behavior of the ZnSe layers that we have deposited thus far. If
this can be achieved, we expect significant improvement in performance.

[^1]: ^†^ We estimated that the cell temperature exceeds the stage
    temperature by approximately 10°C.