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| ![](media/image1.emf){width="0.9770833333333333in"                    |
| height="0.8333333333333334in"} **Fermilab**                           |
|                                                                       |
| **Experiment Electronic Systems Group**                               |
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**DRAFT**

**Specification for**

**ADC/Memory Module**

**(ADMEM)**

Research Division

Electrical/Electronics Department

Experiment Electronic Systems

T. M. Shaw, \...

4/19/93

Revised 5/28/97

1.0 Introduction

The upgraded CDF data acquisition (DAQ) system will be capable of
running at a rate of 1000 Hz into the Level 3 processing farm and will
approach a \"deadtimeless\" system. To accomplish this goal it becomes
necessary to digitize the detector data at every beam crossing (132 ns).

Figure 1 presents an overview of part of the digital readout system,
showing the data path from the digital front-end crates to the Scanner
CPU (SCPU) which will service the network switch into Level 3. The
calorimetry analog information is received by the **AD**C/**MEM**ory
(ADMEM) modules.

The function of ADMEM module will be to receive analog signals, digitize
them at a rate of up to 7.6 MHz, store them in a buffer, and move the
data that passes Level 1 and Level 2 triggers into one of four L2 Accept
buffers. The L2 Accept buffers will be accessible as slave memory
through VMEbus. Figure 2 provides a functional block diagram of the
module.

The ADMEM board also provides phototube channel sums to the L1 Trigger.
Channel values from the ADCs will be digitally summed together across up
to four channels. Weighting will be done through running the digital sum
through a lookup table.

The data in the L2 Accept buffers will be read out via a VMEbus Readout
Controller (VRC) and sent upstream on serial lines to VMEbus Readout
Buffer (VRB) modules. These Readout Memory modules will serve to
concentrate the data for readout by the SCPU over VMEbus. The SCPU will
service the movement of the data onto the data switch, from which it is
routed into the Level 3 processing farm.

2.0 Analog Front-end Paddle Boards

The Analog Front-end portion of the ADMEM board will be implemented on
removeable Paddle boards. The Paddle boards utililize 72-pin SIMM
sockets, identical to those used by PC memory. A single Paddle Board
will be used to instrument each analog channel being fed into the ADMEM.

Paddle boards will contain QIE digitizing chips and the Flash RAM lookup
tables which will be used to adjust for gains and offsets.

![](media/image2.emf){width="6.01875in" height="6.635416666666667in"}

Figure 1. Digital Data Path Overview

![](media/image3.emf)

Figure 2. Block Diagram of FE/ADC/Memory Module

3.0 Look-up Table Memory

The result of the ADC conversion will be run through a memory look-up
table that will be preloaded to take out any range and offset
information. The 16-bit data will then be loaded into the digital
storage pipeline.

It is also possible to set a pass-through mode on the lookup memories,
so that one is able to send the raw data through the device.

4.0 Digital Pipeline and L2 Buffers

The ADCs on the ADMEM module are required to digitize analog detector
information every beam crossing (132 ns). This digitized data must be
stored in a digital pipeline for a period of (4+)us or 42 crossings.
This is the period of time it takes the Level 1 trigger decision to
reach the front-end crates. A Level 1 Accept causes the data to be
written into one of four buffers based upon the buffer address supplied
by the Trigger System Interface (TSI). A Level 1 Reject will cause the
data at the end of the storage pipeline to be thrown away.

The TSI will keep track of all Level 2 buffer status information.
Buffers will be overwritten with new Level 1 Accept data if a Level 2
Reject has occurred on a given buffered event.

A Level 2 Accept will cause the VMEbus Readout Controller (VRC) to
address each ADMEM card within the crate and do a block read of all
channel data for a particular buffer address.

The digital pipeline and Level 2 buffers will be implemented with Xilinx
FPGAs, see Figure 3. These devices will take input from four channels
and form trigger sums. A separate diagnostic path allows the user to
send a pre-determined set of diagnostic data through the pipeline chip
at speed. The diagnostic data can be directed through a single channel
or all channels and comes from the Diagnostic FIFO shown in the ADMEM
block diagram (Fig. 2). The FIFO data is 8k deep and will loop back on
itself when the FIFO empties. **The following is not implemented: A path
is also provided to allow the user to read out the Pipeline RAM after
the system has been put into a "halt" condition.**

The depth of the Pipeline and its offset is programmable on the board
level. The depth of the pipeline should be 42 stages minus any stages
taken up in the analog section. The offset should equal the number of
stages in the analog section. The offset is used upon startup following
a halt condition - the first valid information following the clearing of
a halt condition will take the number of analog stages following a Beam
Zero crossing before valid data should begin filling the pipeline.

5.0 Trigger Interface

The communication with the Trigger System Interface (TSI) requires the
passing of several protocol signals between it and the front end crates.
At the front end crate, all signals passing between it and the TSI will
be handled by the **TR**igger **A**nd **C**lock + **E**vent **R**eadout
Module (TRACER) located in Slot 2 of the VMEbus crate.

The TRACER will receive signals from the Trigger supervisor, digitally
process them and then fan them out to the ADMEM modules. The J2
backplane will be used to transmit these lines. CDF Note 2388 defines
the exact pinout of the custom J2 backplane and the custom signals it
routes.

![](media/image4.emf)

Figure 3. Block Diagram of the ADMEM's Digital Pipeline

6.0 Trigger Sums

ADMEM boards must provide phototube channel sums to the Trigger. Channel
values from up to 4 channels will summed together digitally. The
pipeline chip will provide up to 15 trigger sum bits. The bits will the
be fed into the lookup memories where they are mapped into 10 output
bits. Et weighting will be done through the lookup memories. It is
possible to bypass Et weighting by setting a pass-through bit.

The sums will be transmitted to the trigger system on parallel copper
cable through connectors on the front panel at a rate of one sum per
crossing (where a crossing is assumed to be 132 ns).

7.0 VME Slave Interface

The ADMEM will implement a modified version of a VMEbus slave interface.
Only 32 bit aligned data transfers will be supported; these may be
either single word transfers or block transfers. Only extended (32-bit)
addressing modes will be supported. All boards will be assigned a unique
geographical address through use of backplane pins on the CDF Custom J2
backplane. ADMEM modules will respond to the following address modifier
codes: 09, and 0B.

**Memory Map**

YYY0 0000 Diagnostic Register (32 bits) **(R/W)**

YYY0 0004 Control

**[Bit]{.underline}** **[Function]{.underline}**

31 Software Reset (clears the Diagnostic FIFO) **(R/W)**

30 Enable Pass through mode on QIE data lookup tables **(R/W)**

Lookup table will utilize upper half of 1Mb range

29 Enable VMEbus access to Flash RAM data lookup tables **(R/W)**

VMEbus write control over Flash RAM will be allowed

28 Enable VMEbus read of Pipeline data (R/W)

**NOT Implemented**

27 Enable Diagnostic Pipeline Data **(R/W)**

Data from Diagnostic FIFO will be used for channels indicated in the
Pipeline Diagnostic Channels Enable Register

26 Enable Pass through mode on Trigger Sum data **(R/W)**

Lookup table will utilize upper half of 1Mb range

25 Undefined

24 Undefined

23 Diagnostic FIFO E/F\* **(R)**

22 Diagnostic FIFO H/F\* **(R)**

21 Diagnostic FIFO PAFE\* **(R)**

20 Undefined

19 Undefined

18 Undefined

17 Undefined

16 Undefined

YYY0 0008 Access Register for Flash RAM **(R/W)**

**(must be set to 0xBEAD0000 in order to write to Flash RAM)**

**[Bit]{.underline}** **[Function]{.underline}**

31 Enable Vmebus write to FRAM code (15)

30 Enable Vmebus write to FRAM code (14)

29 Enable Vmebus write to FRAM code (13)

28 Enable Vmebus write to FRAM code (12)

27 Enable Vmebus write to FRAM code (11)

26 Enable Vmebus write to FRAM code (10)

25 Enable Vmebus write to FRAM code (9)

24 Enable Vmebus write to FRAM code (8)

23 Enable Vmebus write to FRAM code (7)

22 Enable Vmebus write to FRAM code (6)

21 Enable Vmebus write to FRAM code (5)

20 Enable Vmebus write to FRAM code (4)

19 Enable Vmebus write to FRAM code (3)

18 Enable Vmebus write to FRAM code (2)

17 Enable Vmebus write to FRAM code (1)

16 Enable Vmebus write to FRAM code (0)

YY00 000C Pipeline Length **(R/W)**

Description: Depth of pipeline will be 42 minus the number of stages in
analog circuitry.

**[Bit]{.underline}** **[Function]{.underline}**

24-31 Programmable pipeline depth

YY00 0010 Pipeline Offset **(R/W)**

Description: Offset will equal #stages in analog circuitry.

**[Bit]{.underline}** **[Function]{.underline}**

24-31 Programmable pipeline depth

YY00 0014 Flash Ram Select **(R/W)**

Description: Selects which channel of FRAM is being addressed over
VMEbus.

**[Bit]{.underline}** **[Function]{.underline}**

31 Undefined

30 Undefined

29 Undefined

28 Select Flash RAM Channel(4)

27 Select Flash RAM Channel(3)

26 Select Flash RAM Channel(2)

25 Select Flash RAM Channel(1)

24 Select Flash RAM Channel(0)

23-0 Undefined

**Channel 0-19 map to digital paddle boards 0-19**

**Channel 20-26 map to trigger sum lookup table (0-6)**

**Channel 27 maps to pipeline download PROM**

YY00 0018 Pipeline Diagnostic Channels Enable Register **(R/W)**

Description: Selects channels through which diagnostic data from the
Diagnostic Pipeline FIFO will be pumped. Either all channels, or a
single channel may be selected. The "Enable Diagnostic Pipeline Data"
bit in the Control Register must also be set.

**[Bit]{.underline}** **[Function]{.underline}**

31 Select All Channels for Diagnostic Data

30 Undefined

29 Undefined

28 Select Diagnostic Data Channel(4)

27 Select Diagnostic Data Channel(3)

26 Select Diagnostic Data Channel(2)

25 Select Diagnostic Data Channel(1)

24 Select Diagnostic Data Channel(0)

23-0 Undefined

YY10 0000 - YY10 007F ID PROM (upper 8 bits) **(R)**

**READOUT of the DIGITAL PIPELINE is NOT Implemented**

**NOTE: Digital Pipeline is READ only, each read will advance the
Pipeline Address by one. The Enable Pipeline Read bit must be set in the
control register. Pipeline Read is only done as a diagnostic after a
HALT condition has been set.**

YY40 0000 - YY40 0XXX Pipeline Contents channel 0 **(R)**

YY40 1000 - YY40 1XXX Pipeline Contents channel 1 **(R)**

YY40 2000 - YY40 2XXX Pipeline Contents channel 2 **(R)**

YY40 3000 - YY40 3XXX Pipeline Contents channel 3 **(R)**

YY40 4000 - YY40 4XXX Pipeline Contents channel 4 **(R)**

YY40 5000 - YY40 5XXX Pipeline Contents channel 5 **(R)**

YY40 6000 - YY40 6XXX Pipeline Contents channel 6 **(R)**

YY40 7000 - YY40 7XXX Pipeline Contents channel 7 **(R)**

YY40 8000 - YY40 8XXX Pipeline Contents channel 8 **(R)**

YY40 9000 - YY40 9XXX Pipeline Contents channel 9 **(R)**

YY40 A000 - YY40 AXXX Pipeline Contents channel 10 **(R)**

YY40 B000 - YY40 BXXX Pipeline Contents channel 11 **(R)**

YY40 C000 - YY40 CXXX Pipeline Contents channel 12 **(R)**

YY40 D000 - YY40 DXXX Pipeline Contents channel 13 **(R)**

YY40 E000 - YY40 EXXX Pipeline Contents channel 14 **(R)**

YY40 F000 - YY40 FXXX Pipeline Contents channel 15 **(R)**

YY41 0000 - YY41 0XXX Pipeline Contents channel 16 **(R)**

YY41 1000 - YY41 1XXX Pipeline Contents channel 17 **(R)**

YY41 2000 - YY41 2XXX Pipeline Contents channel 18 **(R)**

YY41 3000 - YY41 3XXX Pipeline Contents channel 19 **(R)**

YY50 0000 - YY5C FFFC Flash RAM Data Register **(R/W)**

(Read/Write only when enables set in control register)

YY60 0000 - YY6X XXXX Diagnostic Pipeline Data FIFO **(R/W)**

**NOTE: All L2 Buffers are Read Only**

YY80 0000 L2 Buffer 0 Header Word **(R)**

**[Bit]{.underline}** **[Function]{.underline}**

0-7 Bunch ID: 8 bit counter from Bunch Zero

8-12 Geographical Address

13-22 Board Serial Number

23-31 Board Type

YY80 0004 Channel 0,1 L2 Buffer 0 **(R)**

YY80 0008 Channel 2,3 L2 Buffer 0 **(R)**

YY80 000C Channel 4,5 L2 Buffer 0 **(R)**

YY80 0010 Channel 6,7 L2 Buffer 0 **(R)**

YY80 0014 Channel 8,9 L2 Buffer 0 **(R)**

YY80 0018 Channel 10,11 L2 Buffer 0 **(R)**

YY80 001C Channel 12,13 L2 Buffer 0 **(R)**

YY80 0020 Channel 14,15 L2 Buffer 0 **(R)**

YY80 0024 Channel 16,17 L2 Buffer 0 **(R)**

YY80 0028 Channel 18,19 L2 Buffer 0 **(R)**

YY90 0000 L2 Buffer 1 Header Word **(R)**

**[Bit]{.underline}** **[Function]{.underline}**

0-7 Bunch ID: 8 bit counter from Bunch Zero

8-12 Geographical Address

13-22 Board Serial Number

23-31 Board Type

YY90 0004 Channel 0,1 L2 Buffer 1 **(R)**

YY90 0008 Channel 2,3 L2 Buffer 1 **(R)**

YY90 000C Channel 4,5 L2 Buffer 1 **(R)**

YY90 0010 Channel 6,7 L2 Buffer 1 **(R)**

YY90 0014 Channel 8,9 L2 Buffer 1 **(R)**

YY90 0018 Channel 10,11 L2 Buffer 1 **(R)**

YY90 001C Channel 12,13 L2 Buffer 1 **(R)**

YY90 0020 Channel 14,15 L2 Buffer 1 **(R)**

YY90 0024 Channel 16,17 L2 Buffer 1 **(R)**

YY90 0028 Channel 18,19 L2 Buffer 1 **(R)**

YYA0 0000 L2 Buffer 2 Header Word **(R)**

**[Bit]{.underline}** **[Function]{.underline}**

0-7 Bunch ID: 8 bit counter from Bunch Zero

8-12 Geographical Address

13-22 Board Serial Number

23-31 Board Type

YYA0 000C Channel 4,5 L2 Buffer 2 **(R)**

YYA0 0010 Channel 6,7 L2 Buffer 2 **(R)**

YYA0 0014 Channel 8,9 L2 Buffer 2 **(R)**

YYA0 0018 Channel 10,11 L2 Buffer 2 **(R)**

YYA0 001C Channel 12,13 L2 Buffer 2 **(R)**

YYA0 0020 Channel 14,15 L2 Buffer 2 **(R)**

YYA0 0024 Channel 16,17 L2 Buffer 2 **(R)**

YYA0 0028 Channel 18,19 L2 Buffer 2 **(R)**

YYB0 0000 L2 Buffer 3 Header Word **(R)**

**[Bit]{.underline}** **[Function]{.underline}**

0-7 Bunch ID: 8 bit counter from Bunch Zero

8-12 Geographical Address

13-22 Board Serial Number

23-31 Board Type

YYB0 0004 Channel 0,1 L2 Buffer 3 **(R)**

YYB0 0008 Channel 2,3 L2 Buffer 3 **(R)**

YYB0 000C Channel 4,5 L2 Buffer 3 **(R)**

YYB0 0010 Channel 6,7 L2 Buffer 3 **(R)**

YYB0 0014 Channel 8,9 L2 Buffer 3 **(R)**

YYB0 0018 Channel 10,11 L2 Buffer 3 **(R)**

YYB0 001C Channel 12,13 L2 Buffer 3 **(R)**

YYB0 0020 Channel 14,15 L2 Buffer 3 **(R)**

YYB0 0024 Channel 16,17 L2 Buffer 3 **(R)**

YYB0 0028 Channel 18,19 L2 Buffer 3 **(R)**

**YY** is the VME geographical address of the ADMEM.

![](media/image5.emf){width="5.992361111111111in"
height="7.904166666666667in"}

Figure 4. PCB Placement of Prototype "digital" ADMEM