Status of Neural Network Hardware in High Energy Physics

Bruce Denby

Université de Versailles and

Laboratoire des Instruments et Systèmes, Paris, France

**Abstract.** This paper examines the current status of hardware
implementations of neural networks in high energy physics experiments,
as reflected in the applications presented at ACAT 2000, Fermilab,
October, 2000.

# 

# Introduction {#introduction .INTRODUCTION}

It has now been 8 years since the first simple test of neural network
hardware in high energy physics \[1\]. Today, the technique is well
established in running experiments and has been proposed for LHC.
Currently, efforts are hampered by a lack of available commercial NN
products, obliging physicists to examine other solutions for
implementing NN in their experiments. We present here some of the more
recent NN applications as well as some possible solutions for future
developments.

# Use of Nn in the triggers of running experiments

Two currently running experiments, Dirac at CERN and H1 at DESY use NN
hardware directly in the trigger.

## The Dirac Experiment at CERN

Neural network hardware is used in the first level trigger of the Dirac
experiment at the CERN PS \[2\]. The experimental setup is illustrated
in Fig. 1. The experiment is designed to detect pionium production on a
copper target with a 34 GeV proton beam and to measure the lifetime of
pionium.

![](media/image1.png){width="3.265277777777778in"
height="2.558333333333333in"}

**Figure 1.** Experimental setup of the Dirac experiment at CERN. A
proton beam impinges on a copper target. Two --track event are analyzed
in a dipole magnet followed by hodoscopes.

Tracks produced in the collisions are detected in hodoscopes following a
dipole magnet. Hodoscope positions are read out as binary words. As
shown in Fig. 2, the hodoscope information passes first into a data
formatting and event selection card, which essentially reduces the
dimensionality of the hodoscope data and reformats it, and then is
passed into 4 neural network cards. All of the electronics was produced
at the University of Basel.

Fig. 3 shows the architecture of the Basel NN cards. The unique feature
of these cards is that the synaptic multiplications and the transfer
function evaluations are all subsumed into memory lookups. This enables
the neural networks to produce a result in only 60 ns. Full level-1
trigger processing occurs in only 210 ns.

![](media/image2.wmf){width="3.1666666666666665in"
height="1.7361111111111112in"}

**Figure 2.** Trigger electronics schematic of the Dirac experiment at
CERN showing preprocessing and reformating card and the 4 neural net
cards.

![](media/image3.wmf){width="3.1145833333333335in" height="1.575in"}

**Figure 3.** Schematic of the basel NN cards. Synaptic multiply and
activation function are performed in memories. The MLP structure is
55-2-1.

The Dirac trigger achieves an overall background reduction factor of 2.5
and is 95% efficient for the pionium events under study. The trigger is
functioning normally as an integral part of the Dirac experiment.

## The H1 Experiment at DESY

The H1 experiment of the HERA accelerator at DESY in Hamburg has adopted
a completely neural architecture for its level 2 trigger \[3\]. An
initial 10 MHz data rate off the detectors is reduced to 1 kHz by a
hardwired level-1 trigger with a 2.3 microsecond latency. Then the
level-2 trigger, which performs its function in under 20 microseconds,
takes effect, reducing the background by an additional factor of 20. The
background is predominantly from beam-gas events.

The hardware chosen is the CNAPS chip from Cromemco in Germany, which is
a 64 processor SIMD architecture. Twelve separate CNAPS cards are used,
each one tuned to a particular physics channel. The networks have
typically several tens of variables at the input, several tens of hidden
units, and a single output unit which simply signals whether the
corresponding physics process is believed to be present or not.

It is important to realize that in online NN applications, any
preprocessing must also be done online. In the case of H1, this is done
in data distribution bus DDB boards constructed at MPI in Munich using
FPGA technology. The entire procedure must be completed in 4
microseconds which is a challenging electronics task. The overall system
is illustrated in Fig. 4.

![](media/image4.png){width="3.029166666666667in" height="2.0875in"}

**Figure 4.** Schematic Diagram of the H1 NN trigger including the DDB
preprocessing cards and the 12 corresponding CNAPS NN cards.

The H1 NN trigger has been in operation for 5 years and has enabled the
H1 collaboration to produce physics results which would otherwise have
been unattainable, particularly in the realm of vector meson
photoproduction (phi, psi, etc.). The additional acceptance for these
channels is due to the intelligent triggering of the NN hardware.

# Future developements foreseen

Apart from the currently running NN trigger applications mentioned
above, there are also a certain number of new projects that are being
planned using these techniques. We shall speak here about the upgrade to
H1 and a possible application to a muon trigger in ATLAS at CERN, and
conclude with some new approaches to NN hardware.

## The H1 Upgrade

For its next run, the H1 experiment will be upgrading its NN trigger
\[3,4\]. The number of CNAPS cards will be extended to 16 and a new
DDBII preprocessing system will be built. The DDBII is based on
intelligent preprocessing achieved in only 4 microseconds, and are
implemented in FPGA using the Virtex family of Xylinx chips. The overall
plan is to execute the preprocessing in 4 steps: clustering in the
individual detectors; matching of corresponding clusters between devices
into physics objects; ordering of phyics objects by energy or other
criteria; and finally construction of the network in put variables. The
procedure is shown schematically in Fig. 5.

![](media/image5.png){width="3.0631944444444446in"
height="1.9854166666666666in"}

**Figure 5.** Schematic of the DDBII architecture for the H1 upgrade.
The circuit will be implemented with FPGA's.

The DDBII's have shown, in simulation, to be able to improve rather
dramatically the ability of H1 to study certain processes, in particular
photoproduction of phi's.

## A Possible Muon Trigger for ATLAS

As the magnetic field in the ATLAS experiment is rather non-uniform, the
mapping between raw track parameters (slopes and intercepts in two
planes) and physics quantities such as the 3-vector and charge of a muon
is a complicated function which varies with position around the ATLAS
detector. In an experimental simulation \[5\], it was shown that this
mapping can be learned by a 4-7-7-4 multilayer perceptron architecture
with very good accuracy. Given the parallel nature of neural networks,
it is interesting to ask the question as to whether or not this
architecture could also be realized at the trigger level to providean
'intelligent' muon trigger. This will be addressed in a preliminary way
in the next section.

## Future Hardware Approaches

It is worth noting that the CNAPS chips is no longer manufactured. Many
of the other sorts of NN chips such as the ETANN which used to exist
have also over the years been discontinued. One may ask the question
today, if one wanted to build an NN trigger, what hardware should be
used?

One approach, as already cited \[2\], is to implement the NN, both
synaptic multiply and transfer function using memory lookups. Another
method, proposed by a group in Paris \[6\], is to use some the new of
FPGA's coming out today to build an NN architecture directly. Such a
circuit, named MAHARADJAH, is illustrated in Fig. 6.

![](media/image6.png){width="3.0631944444444446in"
height="3.0631944444444446in"}

**Figure 6.** Architecture of the MAHARADJAH system for evaluating NN in
realtime. Implementation is in FPGA's.

The architecture consists of four UNE units containing
multiply-accumulators, in communication with memory banks holding
synaptic weights and lookup tables of activation function. Control is
via a simple microcontroller. Such a circuit can equal the performance
of a Pentium III or a Sparc Ultra workstation while running at only 40
MHz. As a test, the architecture was benchmarked against the ATLAS
4-7-7-4 network presented in the previous section. The predicted
execution time was of the order of only 2 microseconds, which would be
quite acceptable at trigger level and is thus very interesting.

# CONCLUSIONS

Neural network triggers have been incorporated into a certain number of
running experiments and are being used to produce physics. In the case
of H1, the NN trigger has been instrumental in obtaining certain classes
of physics. For the future, H1 will be upgraded and along with it the NN
trigger, which will include a new, more intelligent preprocessor based
on FPGA's. Additionally, there is a possibility of a neural muon trigger
for ATLAS.

In a general sense, neural network hardware is difficult to find; a
number of longstanding products are no longer available. In future, it
should be possible to turn for example to full-FPGA solutions such as
the MAHARADJAH architecture cited above, or other digital approaches
such as memory lookups.

# Acknowledgments

The author is indebted to the authors of the presentations which served
as the basis for this rapporteur's summary.

# References

1\. C.S. Lindsey et. al,, *Nucl. Instrum. Meth.* **A317** (1992) 346.

2\. Sotirios Vlachos, these proceedings.

3\. Christophe Kiesling, these proceedings.

4\. Jean-Christophe Prévotet, these proceedings.

5.  Erez Etzion, these proceedings.

6.  Bertrand Granado, these proceedings.