**[Phenix LDRD Pixel Plane Specifications]{.smallcaps}**

Version 1

Jeff Andresen, Guilherme Cardoso

April 19, 2007

1.  Introduction

This document describes the specifications for the pixel plane utilized
by the Phenix LDRD project. The pixel plane described here is the
prototype for the LDRD. The goal of this pixel plane is the test of:

a group of 10 8-chip pixel modules working together in a system.

different power supply schemes.

different grounding schemes.

preliminary cooling using carbon-TPG substrate.

different interfaces to the DAQ.

2.  Electrical Specifications

    1.  Charge Injection

A triangular-shaped analog voltage waveform can be used to inject charge
on the preamplifier of the FPIX2.1 chips. Since the FPIX2.1 chips don't
have an internal pulser, an external voltage pulse must be supplied to
calibrate the system once in operation. The pulser must comply to the
following specifications

1- Triangular waveform

The issues to be considered in the design of the pulser are:

Each 8 chip module will have its own charge inject signal and ground
coming into the pixel plane. A 24 pin Hirose DF11-24DP-2DS right angle
through hole connector is used on the pixel plane for these signals.
Once on the pixel plane, the ground is the common analog ground plane.
Table 1 has the connector pinout for the charge injection.

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 INJECTIN_1        2                 ANALOG GND

  3                 INJECTIN_2        4                 ANALOG GND

  5                 INJECTIN_3        6                 ANALOG GND

  7                 INJECTIN_4        8                 ANALOG GND

  9                 INJECTIN_5        10                ANALOG GND

  11                INJECTIN_6        12                ANALOG GND

  13                INJECTIN_7        14                ANALOG GND

  15                INJECTIN_8        16                ANALOG GND

  17                INJECTIN_9        18                ANALOG GND

  19                INJECTIN_10       20                ANALOG GND

  21                NO CONNECT        22                NO CONNECT

  23                SHIELD GND        24                SHIELD GND
  ----------------- ----------------- ----------------- -----------------

> Table 1: Charge Inject Connector Pinout

2- Charge in the chip's preamplifier is collected in the falling edge of
the triangular waveform.

2.  Power Supplies

Hv and Lv power supplies

Each 8 chip module will have its own low voltage digital power, low
voltage analog power, and high voltage power. Three 24 pin Hirose
DF11-24DP-2DS connectors are used on the pixel plane for these powers.
The low voltage digital powers have separate grounds at the connector
where it becomes a common digital ground on the pixel plane. The low
voltage analog powers and high voltage powers have separate grounds at
the connector where it becomes a common analog ground on the pixel
plane. Table 2, table 3, and table 4 have the power supply connector
pinouts.

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 VDDD_10           2                 DGND

  3                 VDDD_9            4                 DGND

  5                 VDDD_8            6                 DGND

  7                 VDDD_7            8                 DGND

  9                 VDDD_6            10                DGND

  11                VDDD_5            12                DGND

  13                VDDD_4            14                DGND

  15                VDDD_3            16                DGND

  17                VDDD_2            18                DGND

  19                VDDD_1            20                DGND

  21                +3.3V             22                DGND

  23                SHIELD GND        24                SHIELD GND
  ----------------- ----------------- ----------------- -----------------

Table 2: Low Voltage Digital Power Supply Connector

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 VDDA_1            2                 AGND

  3                 VDDA_2            4                 AGND

  5                 VDDA_3            6                 AGND

  7                 VDDA_4            8                 AGND

  9                 VDDA_5            10                AGND

  11                VDDA_6            12                AGND

  13                VDDA_7            14                AGND

  15                VDDA_8            16                AGND

  17                VDDA_9            18                AGND

  19                VDDA_10           20                AGND

  21                +3.3V             22                DGND

  23                SHIELD GND        24                SHIELD GND
  ----------------- ----------------- ----------------- -----------------

Table 3: Low Voltage Analog Power Supply Connector

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 VDET_1_IN         2                 AGND

  3                 VDET_2_IN         4                 AGND

  5                 VDET_3_IN         6                 AGND

  7                 VDET_4_IN         8                 AGND

  9                 VDET_5_IN         10                AGND

  11                VDET_6_IN         12                AGND

  13                VDET_7_IN         14                AGND

  15                VDET_8_IN         16                AGND

  17                VDET_9_IN         18                AGND

  19                VDET_10_IN        20                AGND

  21                NO CONNECT        22                NO CONNECT

  23                SHIELD GND        24                SHIELD GND
  ----------------- ----------------- ----------------- -----------------

Table 4: High Voltage Connector

The digital powers have National Semiconductor LP3874EPM-2.5 fixed 2.5V
output regulators located under the HDIs near the VDDD wire bond pad.
The analog powers have Maxim MAX1793EUE25+ variable output regulators
located under the HDIs near the VDDA wire bond pad. There are two
resistors that set the desired output voltage. The Pixel Plane PCB can
operate without regulators if the regulators are not left off of the PCB
and the input is shorted to the output. As this PCB is inside the
detector, voltage protection will be done before this PCB.

3.  Interface to DAQ

The DAQ signals will interface with the PTA through 10 3M
P50LE-050P1-SML-TGF connectors. All signals are differential pairs.
There are 6 control signals for each HDI module. There is 1 data signal
for each chip for a total of 8 data signals for each module. As the 8
chip module has data signals at both ends, there are 5 connectors on
each side of the 10 modules. Table 5 through table 10 have the connector
pinouts for the data and control signals of the 8 chip HDI modules.

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 OUT5_1_10         2                 OUT5_1_10\*

  3                 OUT6_1_10         4                 OUT6_1_10\*

  5                 SCK\_+A           6                 SCK\_\*A

  7                 FFR1              8                 FFR1\*

  9                 FFR2              10                FFR2\*

  11                PTAGND            12                PTAGND

  13                FFR3              14                FFR3\*

  15                SHIFTOUT1         16                SHIFTOUT1\*

  17                SHIFTOUT2         18                SHIFTOUT2\*

  19                SHIFTOUT3         20                SHIFTOUT3\*

  21                PTAGND            22                PTAGND

  23                OUT8_1_1          24                OUT8\_\*1_1

  25                OUT7_1_1          26                OUT7\_\*1_1

  27                OUT6_1_1          28                OUT6\_\*1_1

  29                OUT5_1_1          30                OUT5\_\*1_1

  31                PTAGND            32                PTAGND

  33                OUT8_1_2          34                OUT8\_\*1_2

  35                OUT7_1_2          36                OUT7\_\*1_2

  37                OUT6_1_2          38                OUT6\_\*1_2

  39                OUT5_1_2          40                OUT5\_\*1_2

  41                PTAGND            42                PTAGND

  43                OUT8_1_3          44                OUT8\*\_1_3

  45                OUT7_1_3          46                OUT7\*\_1_3

  47                OUT6_1_3          48                OUT6\*\_1_3

  49                OUT5_1_3          50                OUT5\*\_1_3
  ----------------- ----------------- ----------------- -----------------

Table 5: Left Side PTA Connector J1

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 SHIFTOUT10        2                 SHIFTOUT\*10

  3                 FFR10             4                 FFR\*10

  5                 SCK\_+B           6                 SCK\_\*B

  7                 FFR4              8                 FFR\*4

  9                 FFR5              10                FFR\*5

  11                PTAGND            12                PTAGND

  13                FFR6              14                FFR\*6

  15                SHIFTOUT4         16                SHIFTOUT\*4

  17                SHIFTOUT5         18                SHIFTOUT\*5

  19                SHIFTOUT6         20                SHIFTOUT\*6

  21                PTAGND            22                PTAGND

  23                OUT8_1_4          24                OUT8\_\*1_4

  25                OUT7_1_4          26                OUT7\_\*1_4

  27                OUT6_1_4          28                OUT6\_\*1_4

  29                OUT5_1_4          30                OUT5\_\*1_4

  31                PTAGND            32                PTAGND

  33                OUT8_1_5          34                OUT8\_\*1_5

  35                OUT7_1_5          36                OUT7\_\*1_5

  37                OUT6_1_5          38                OUT6\_\*1_5

  39                OUT5_1_5          40                OUT5\_\*1_5

  41                PTAGND            42                PTAGND

  43                OUT8_1_6          44                OUT8\_\*1_6

  45                OUT7_1_6          46                OUT7\_\*1_6

  47                OUT6_1_6          48                OUT6\_\*1_6

  49                OUT5_1_6          50                OUT5\_\*1_6
  ----------------- ----------------- ----------------- -----------------

Table 6: Left Side PTA Connector J2

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 OUT7_1_10         2                 OUT7\_\*1_10

  3                 OUT8_1_10         4                 OUT8\_\*1_10

  5                 SCK_CNTRL         6                 SCK_CNTRL\*

  7                 FFR7              8                 FFR\*7

  9                 FFR8              10                FFR\*8

  11                PTAGND            12                PTAGND

  13                FFR9              14                FFR\*9

  15                SHIFTOUT7         16                SHIFTOUT\*7

  17                SHIFTOUT8         18                SHIFTOUT\*8

  19                SHIFTOUT9         20                SHIFTOUT\*9

  21                PTAGND            22                PTAGND

  23                OUT8_1_7          24                OUT8\_\*1_7

  25                OUT7_1_7          26                OUT7\_\*1_7

  27                OUT6_1_7          28                OUT6\_\*1_7

  29                OUT5_1_4          30                OUT5\_\*1_4

  31                PTAGND            32                PTAGND

  33                OUT8_1_8          34                OUT8\_\*1_8

  35                OUT7_1_8          36                OUT7\_\*1_8

  37                OUT6_1_8          38                OUT6\_\*1_8

  39                OUT5_1_8          40                OUT5\_\*1_8

  41                PTAGND            42                PTAGND

  43                OUT8_1_9          44                OUT8\_\*1_9

  45                OUT7_1_9          46                OUT7\_\*1_9

  47                OUT6_1_9          48                OUT6\_\*1_9

  49                OUT5_1_9          50                OUT5\_\*1_9
  ----------------- ----------------- ----------------- -----------------

Table 7: Left Side PTA Connector J5

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 OUT1_1_10         2                 OUT1\_\*1_10

  3                 OUT2_1_10         4                 OUT2\_\*1_10

  5                 BCO+A             6                 BCO+A

  7                 SHIFTCTRL1        8                 SHIFTCTRL\*1

  9                 SHIFTCTRL2        10                SHIFTCTRL\*2

  11                PTAGND            12                PTAGND

  13                SHIFTCTRL3        14                SHIFTCTRL\*3

  15                SHIFTIN1          16                SHIFTIN\*1

  17                SHIFTIN2          18                SHIFTIN\*2

  19                SHIFTIN3          20                SHIFTIN\*3

  21                PTAGND            22                PTAGND

  23                OUT4_1_1          24                OUT4\_\*1_1

  25                OUT3_1_1          26                OUT3\_\*1_1

  27                OUT2_1_1          28                OUT2\_\*1_1

  29                OUT1_1_1          30                OUT1\_\*1_1

  31                PTAGND            32                PTAGND

  33                OUT4_1_2          34                OUT4\_\*1_2

  35                OUT3_1_2          36                OUT3\_\*1_2

  37                OUT2_1_2          38                OUT2\_\*1_2

  39                OUT1_1_2          40                OUT1\_\*1_2

  41                PTAGND            42                PTAGND

  43                OUT4_1_3          44                OUT4\_\*1_3

  45                OUT3_1_3          46                OUT3\_\*1_3

  47                OUT2_1_3          48                OUT2\_\*1_3

  49                OUT1_1_3          50                OUT1\_\*1_3
  ----------------- ----------------- ----------------- -----------------

Table 8: Right Side PTA Connector J3

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 OUT4_1_10         2                 OUT4\_\*1_10

  3                 SHIFTIN10         4                 SHIFTIN\*10

  5                 BCO+B             6                 BCO\*B

  7                 SHIFTCTRL4        8                 SHIFTCTRL\*4

  9                 SHIFTCTRL5        10                SHIFTCTRL\*5

  11                PTAGND            12                PTAGND

  13                SHIFTCTRL6        14                SHIFTCTRL\*6

  15                SHIFTIN4          16                SHIFTIN\*4

  17                SHIFTIN5          18                SHIFTIN\*5

  19                SHIFTIN6          20                SHIFTIN\*6

  21                PTAGND            22                PTAGND

  23                OUT4_1_4          24                OUT4\_\*1_4

  25                OUT3_1_4          26                OUT3\_\*1_4

  27                OUT2_1_4          28                OUT2\_\*1_4

  29                OUT1_1_4          30                OUT1\_\*1_4

  31                PTAGND            32                PTAGND

  33                OUT4_1_5          34                OUT4\_\*1_5

  35                OUT3_1_5          36                OUT3\_\*1_5

  37                OUT2_1_5          38                OUT2\_\*1_5

  39                OUT1_1_5          40                OUT1\_\*1_5

  41                PTAGND            42                PTAGND

  43                OUT4_1_6          44                OUT4\_\*1_6

  45                OUT3_1_6          46                OUT3\_\*1_6

  47                OUT2_1_6          48                OUT2\_\*1_6

  49                OUT1_1_6          50                OUT1\_\*1_6
  ----------------- ----------------- ----------------- -----------------

Table 9: Right Side PTA Connector J4

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 OUT3_1_10         2                 OUT3_1_10

  3                 SHIFTCTRL10       4                 SHIFTCTRL\*10

  5                 BCO_CNTRL         6                 BCO_CNTRL\*

  7                 SHIFTCTRL7        8                 SHIFTCTRL\*7

  9                 SHIFTCTRL8        10                SHIFTCTRL\*8

  11                PTAGND            12                PTAGND

  13                SHIFTCTRL9        14                SHIFTCTRL\*9

  15                SHIFTIN7          16                SHIFTIN\*7

  17                SHIFTIN8          18                SHIFTIN\*8

  19                SHIFTIN9          20                SHIFTIN\*9

  21                PTAGND            22                PTAGND

  23                OUT4_1_7          24                OUT4\_\*1_7

  25                OUT3_1_7          26                OUT3\_\*1_7

  27                OUT2_1_7          28                OUT2\_\*1_7

  29                OUT1_1_7          30                OUT1\_\*1_7

  31                PTAGND            32                PTAGND

  33                OUT4_1_8          34                OUT4\_\*1_8

  35                OUT3_1_8          36                OUT3\_\*1_8

  37                OUT2_1_8          38                OUT2\_\*1_8

  39                OUT1_1_8          40                OUT1\_\*1_8

  41                PTAGND            42                PTAGND

  43                OUT4_1_9          44                OUT4\_\*1_9

  45                OUT3_1_9          46                OUT3\_\*1_9

  47                OUT2_1_9          48                OUT2\_\*1_9

  49                OUT1_1_9          50                OUT1\_\*1_9
  ----------------- ----------------- ----------------- -----------------

Table 10: Right Side PTA Connector J7

4.  Clock Fanouts

Figure 1 shows the Micrel SY89828L clock fanout I.C.

![](media/image1.png){width="5.997222222222222in"
height="4.143055555555556in"}

Figure 1: Micrel SY8928L Clock Fanout I.C.

This I.C. will be used for the fanout of SCLK 1:10 and BCOCLK 1:10.
Using this I.C. lessens the number of clock pins required on the PTA
connectors, provides signal redundancy, and increases signal quality
with less skew. There is an A and B LVDS input clock for redundancy. The
CLK_SEL inputs are pulled low which always uses the LVDS inputs. The SEL
inputs selects which LVDS input is used. The OE pins selects whether
outputs Q0-Q9 are used or Q10-19 are used for further redundancy. A pair
of Maxim MAX9130 I.C.s control the SEL and OE inputs.

5.  Chip Hit

The OUT 6 data pair for each FPIX2 chip on the HDI can be wire bonded on
the HDI so that those pads are the CHIPHIT pair instead. On the PIXEL
Plane PCB, these pads will be used for CHIPHIT. The CHIPHIT signals for
HDI modules 1 through 10 will be on 4 PTA connectors. Table 11 through
table 14 have the pinouts for the CHIPHIT connectors.

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 NO CONNECT        2                 NO CONNECT

  3                 CHIPHIT8_1        4                 CHIPHIT\*8_1

  5                 CHIPHIT7_1        6                 CHIPHIT\*7_1

  7                 CHIPHIT6_1        8                 CHIPHIT\*6_1

  9                 CHIPHIT5_1        10                CHIPHIT\*5_1

  11                PTAGND            12                PTAGND

  13                CHIPHIT8_2        14                CHIPHIT\*8_2

  15                CHIPHIT7_2        16                CHIPHIT\*7_2

  17                CHIPHIT6_2        18                CHIPHIT\*6_2

  19                CHIPHIT5_2        20                CHIPHIT\*5_2

  21                PTAGND            22                PTAGND

  23                CHIPHIT8_3        24                CHIPHIT\*8_3

  25                CHIPHIT7_3        26                CHIPHIT\*7_3

  27                CHIPHIT6_3        28                CHIPHIT\*6_3

  29                CHIPHIT5_3        30                CHIPHIT\*5_3

  31                PTAGND            32                PTAGND

  33                CHIPHIT8_4        34                CHIPHIT\*8_4

  35                CHIPHIT7_4        36                CHIPHIT\*7_4

  37                CHIPHIT6_4        38                CHIPHIT\*6_4

  39                CHIPHIT5_4        40                CHIPHIT\*5_4

  41                PTAGND            42                PTAGND

  43                CHIPHIT8_5        44                CHIPHIT\*8_5

  45                CHIPHIT7_5        46                CHIPHIT\*7_5

  47                CHIPHIT6_5        48                CHIPHIT\*6_5

  49                CHIPHIT5_5        50                CHIPHIT\*5_5
  ----------------- ----------------- ----------------- -----------------

Table 11: Left Side PTA Connector J6

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 NO CONNECT        2                 NO CONNECT

  3                 CHIPHIT8_6        4                 CHIPHIT\*8_6

  5                 CHIPHIT7_6        6                 CHIPHIT\*7_6

  7                 CHIPHIT6_6        8                 CHIPHIT\*6_6

  9                 CHIPHIT5_6        10                CHIPHIT\*5_6

  11                PTAGND            12                PTAGND

  13                CHIPHIT8_7        14                CHIPHIT\*8_7

  15                CHIPHIT7_7        16                CHIPHIT\*7_7

  17                CHIPHIT6_7        18                CHIPHIT\*6_7

  19                CHIPHIT5_7        20                CHIPHIT\*5_7

  21                PTAGND            22                PTAGND

  23                CHIPHIT8_8        24                CHIPHIT\*8_8

  25                CHIPHIT7_8        26                CHIPHIT\*7_8

  27                CHIPHIT6_8        28                CHIPHIT\*6_8

  29                CHIPHIT5_8        30                CHIPHIT\*5_8

  31                PTAGND            32                PTAGND

  33                CHIPHIT8_9        34                CHIPHIT\*8_9

  35                CHIPHIT7_9        36                CHIPHIT\*7_9

  37                CHIPHIT6_9        38                CHIPHIT\*6_9

  39                CHIPHIT5_9        40                CHIPHIT\*5_9

  41                PTAGND            42                PTAGND

  43                CHIPHIT8_10       44                CHIPHIT\*8_10

  45                CHIPHIT7_10       46                CHIPHIT\*7_10

  47                CHIPHIT6_10       48                CHIPHIT\*6_10

  49                CHIPHIT5_10       50                CHIPHIT\*5_10
  ----------------- ----------------- ----------------- -----------------

Table 12: Left Side PTA Connector J13

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 NO CONNECT        2                 NO CONNECT

  3                 CHIPHIT4_1        4                 CHIPHIT\*4_1

  5                 CHIPHIT3_1        6                 CHIPHIT\*3_1

  7                 CHIPHIT2_1        8                 CHIPHIT\*2_1

  9                 CHIPHIT1_1        10                CHIPHIT\*1_1

  11                PTAGND            12                PTAGND

  13                CHIPHIT4_2        14                CHIPHIT\*4_2

  15                CHIPHIT3_2        16                CHIPHIT\*3_2

  17                CHIPHIT2_2        18                CHIPHIT\*2_2

  19                CHIPHIT1_2        20                CHIPHIT\*1_2

  21                PTAGND            22                PTAGND

  23                CHIPHIT4_3        24                CHIPHIT\*4_3

  25                CHIPHIT3_3        26                CHIPHIT\*3_3

  27                CHIPHIT2_3        28                CHIPHIT\*2_3

  29                CHIPHIT1_3        30                CHIPHIT\*1_3

  31                PTAGND            32                PTAGND

  33                CHIPHIT4_4        34                CHIPHIT\*4_4

  35                CHIPHIT3_4        36                CHIPHIT\*3_4

  37                CHIPHIT2_4        38                CHIPHIT\*2_4

  39                CHIPHIT1_4        40                CHIPHIT\*1_4

  41                PTAGND            42                PTAGND

  43                CHIPHIT4_5        44                CHIPHIT\*4_5

  45                CHIPHIT3_5        46                CHIPHIT\*3_5

  47                CHIPHIT2_5        48                CHIPHIT\*2_5

  49                CHIPHIT1_5        50                CHIPHIT\*1_5
  ----------------- ----------------- ----------------- -----------------

Table 13: Right Side PTA Connector J8

  ----------------- ----------------- ----------------- -----------------
  PIN \#            SIGNAL            PIN \#            SIGNAL

  1                 NO CONNECT        2                 NO CONNECT

  3                 CHIPHIT4_6        4                 CHIPHIT\*4_6

  5                 CHIPHIT3_6        6                 CHIPHIT\*3_6

  7                 CHIPHIT2_6        8                 CHIPHIT\*2_6

  9                 CHIPHIT1_6        10                CHIPHIT\*1_6

  11                PTAGND            12                PTAGND

  13                CHIPHIT4_7        14                CHIPHIT\*4_7

  15                CHIPHIT3_7        16                CHIPHIT\*3_7

  17                CHIPHIT2_7        18                CHIPHIT\*2_7

  19                CHIPHIT1_7        20                CHIPHIT\*1_7

  21                PTAGND            22                PTAGND

  23                CHIPHIT4_8        24                CHIPHIT\*4_8

  25                CHIPHIT3_8        26                CHIPHIT\*3_8

  27                CHIPHIT2_8        28                CHIPHIT\*2_8

  29                CHIPHIT1_8        30                CHIPHIT\*1_8

  31                PTAGND            32                PTAGND

  33                CHIPHIT4_9        34                CHIPHIT\*4_9

  35                CHIPHIT3_9        36                CHIPHIT\*3_9

  37                CHIPHIT2_9        38                CHIPHIT\*2_9

  39                CHIPHIT1_9        40                CHIPHIT\*1_9

  41                PTAGND            42                PTAGND

  43                CHIPHIT4_10       44                CHIPHIT\*4_10

  45                CHIPHIT3_10       46                CHIPHIT\*3_10

  47                CHIPHIT2_10       48                CHIPHIT\*2_10

  49                CHIPHIT1_10       50                CHIPHIT\*1_10
  ----------------- ----------------- ----------------- -----------------

Table 14: Right Side PTA Connector J15

6.  Layout considerations

The Pixel Plane PCB has 8 layers. The digital data, chiphit, and control
signals are differential pairs that will have 100 ohm edge coupled
controlled impedance. The PCB layer stackup is as follows.

Layer 1: Top, trace layer 1.

Layer 2: IN3, trace layer 2

Layer 3: GND, digital ground plane, impedance reference for layer 1 and
layer 2

Layer 4: PWR, +3V and VDDAs power plane

Layer 5: IN1, VDDDs and AGND power plane

Layer 6: IN2, digital ground plane, impedance reference for layer 7 and
layer 8

Layer 7: IN4, trace layer 3

Layer 8: BOT, trace layer 4

There will be a large cutout in the Pixel Plane PCB under the active
area of the 8 chip modules. This area will be filled with TPG with a
.018" thickness. A cooling pipe will be on the back of the TPG. The
Pixel Plane PCB will have a thickness of .093". The Pixel Plane PCB must
be rigid enough to support the 10 8 chip modules. The Pixel Plane PCB
will be mounted face to face to a second Pixel Plane PCB with a 6.2 mm
offset. The connectors will be on the back of the Pixel Plane PCB. High
voltage minimum clearances will be required. The Pixel Plane PCB is
under a size restriction which makes the layout and the cable routing a
challenge.

7.  Grounding

The low voltage digital powers have separate grounds at the connector
where it becomes a common digital ground on the Pixel Plane PCB. The low
voltage analog powers and high voltage powers have separate grounds at
the connector where it becomes a common analog ground on the pixel
plane. The connectors for are 24 pin for the 10 HDI modules. This
provides an unused bottom pair of pins that can be used for SHIELD
GROUND as an option. There is a large digital ground pad near each power
connector to allow for the connection of a cable ground shield to
digital ground if it is needed. There are pads for a zero ohm resistor
in several spots on the Pixel Plane PCB to allow the connecting of
analog ground to digital ground if it is needed.

8.  Dimensions of the board

Figure 2 is the Pixel Plane PCB layout. The outer circle is the detector
barrel which has a radius of 180mm. The lower circle of the Pixel Plane
PCB is the beam pipe area with a diameter of 31.2mm. The Pixel Plane PCB
has a maximum width of 353.16mm and a maximum height of 173.8mm. The PCB
has a cutout under the HDI detectors that is 74mm wide and 133.0mm in
height. This cutout area will be filled with a carbon-TPG substrate and
contain a cooling pipe.

![](media/image2.wmf) Figure 2: Pixel Plane PCB

The two Pixel Plane PCBs will be mounted face to face with the
connectors mounted on the back side of the PCBs.

3.3 Pixel Plane PCB Design Schematic.

![](media/image3.png){width="5.7125in" height="8.9875in"}

![](media/image4.png){width="5.663888888888889in" height="8.9875in"}

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