Operation of the DØ Silicon Detector and Read-out System in the DØ
Assembly and Collision Hall

**Silicon Group**

##### Abstract

> This document describes in detail the planned operation of the silicon
> detector in the assembly and collision hall and all safety-related
> features. Its purpose is to provide complete documentation and a
> complete set of instructions to obtain operational readiness clearance
> for operation of the silicon detector.

Introduction [3](#introduction)

Silicon Read-out Sequence [4](#silicon-read-out-sequence)

High Density Interconnect and Low Mass Cable
[5](#high-density-interconnect-and-low-mass-cable)

Interface Board [6](#interface-board)

Sequencers [11](#sequencers)

#   {#section .unnumbered}

# Introduction

The DØ silicon microstrip tracker carries a very high programmatic value
for the physics program of the DØ experiment and the laboratory as a
whole. As such, considerable effort was spent on designing a system that
is safe to operate and has multiple levels of safeguards in case of an
emergency. Barring acts of God, nothing is allowed to happen to the
device. This document describes in detail every aspect of the operation
of the detector and the safety features that were implemented. Review
and approval of this documentation by the review panel of the laboratory
will allow the experiment to operate the device in an unattended mode.

The silicon detector is build and assembled in the cleanrooms of the
Silicon Detector Facility of Fermilab. After completing the assembly of
the detector, it will have to be transported to the DØ assembly hall and
installed in the bore of the scintillating fiber tracker. The next
section will describe how this transport is planned. All job hazard
analyses and procedures for the various tasks can be found in the
appendix. The next section gives an overview of the silicon readout
system, which is followed by a detailed description of each component
The last sections describe the cooling, interlock and monitoring systems
of the silicon detector.

# Silicon Read-out Sequence

Figure 1 shows a schematic of the read-out chain. The silicon detectors
are read-out using the SVXIIE chip. The chips, which read out 128
channels each, are mounted on a High Density Interconnect (HDI). The HDI
is a flexible circuit which provides all relevant control, data, and
power lines to operate the chip. The SVXIIE chip is operated using two
power sources for the analogue section of the chip (AVDD and AVDD2) and
one source for the digital section (DVDD). The nominal voltages are 5.1
V, 3.5V and 5.0V. The HDI is connected by means of a Hirose connector to
a low mass cable, which carries the signals along the mounting shell of
the silicon detector out of the interaction region to the region between
the central and end calorimeters. The low mass cable is connected to a
30 foot 3M/80 conductor cable by means of a passive daughter card which
connects to an Interface Board (IB). All control and data signals are
refreshed at the IB. It is at the Interface Board where the power to
operate the SVX chips and the bias voltage for the silicon detectors is
provided and distributed to the 80-conductor cable which in turn
transfers the voltages to the low mass cable. The data signals the
Interface Board receives are sent down a 25 foot long 3M/50 conductor
cable to the Sequencer, where they are serialized and converted to
optical signals. The optical signals are sent at a rate of 1 Gbit/sec
through optical fibers to the VME Readoot Buffer (VRB) board, which will
server as buffers for the data pending trigger decisions. The data for
those events with a L1 accept are transferred through the VME backplane
to the VBD (VME Buffer Driver) and sent to the L3 trigger framework.

![](media/image1.jpeg){width="6.559722222222222in"
height="4.597222222222222in"}

> Figure 1. Silicon readout data flow.

# High Density Interconnect and Low Mass Cable 

The SVX chips are mounted three, six, eight or nine chips at a time onto
flexible copper-on-kapton printed circuits called HDI's. Each HDI
connects to a miniature Hirosi connector at one end of a kapton low mass
cable. The low mass cable and hdi carry the svx power lines and the bias
voltages for the silicon detectors. Figure 2 shows the connections and
the current densities for the various traces on the hdi and low mass
cable.

![](media/image2.wmf)

# Interface Board

The Interface Board can be regarded as the hub for all relevant silicon
signals and all signal management is performed by this board. The
Interface Board is at the junction of the 50-conductor to 80-conductor
3M cables. The 80-conductor cables are input to the Interface Board and
the signals are routed to the J2 and J3 backplanes, which hold the
50-conductor cables. These backplanes are identical to the Sequencer
backplanes. The power to operate the SVX chips and the bias voltage for
the silicon detectors is provided through a special J1 backplane. This
power is provided to the detector through the additional lines in the
80-conductor cable. The board also refreshes the data and control
signals of the SVX chip. The clock signals that are received from the
Sequencer that drive the SVX chip are split off at the Interface Board
and are launched onto special coaxial cables that run parallel to the
80-conductor and low mass cables. In addition, the Interface Board has a
1553 interface, which provides monitoring of the silicon hybrids. The
power supply for the Interface Board is interlocked to the cooling
system. A brief description of each of the tasks of the Interface Board
is given in the next paragraphs.

SVX Power control and current limiting. Power control for turn-on and
overcurrent trip is through an Altera PLD. The current limiters for
AVDD, AVDD2, and DVDD are designed to trip at 0.7 A. Response time is
expected to be \<\< 2 ms (as soon as a trip condition is sensed and the
Altera PLD can respond). The time constant for integrated signals
(output of current monitor) is 100ms so as not to trip on glitches. Each
SVX power line is monitored, for a total of 24 current limiter circuits
per board. The control PLD also controls the power turn-on sequence to
properly initialize the SVX chip.

HDI High temperature trip. A temperature trip whose value set by a
reference resistor (nominally at 40 degrees C) is input to the power
monitor PLD. The circuit will not trip due to an open or short circuit
to accommodate HDIs which are not equipped with RTDs.

DVALID treatment including pulse shaping and deglitching.

Monitoring of voltages, currents, temperature and card status.
Monitoring of SVX voltages and currents and the monitoring of the hybrid
temperature is done by a 1553 interface and a multiplexed serial ADC.

The items being monitored and the 8-bit ADC limit values are:

  ------------------------ --------------------- ------------------------
  AVDD                     Current               1 A

  AVDD2                    Current               1 A

  DVDD                     Current               1 A

  Temperature                                    -15 to 100 deg C

  AVDD                     Voltage               8 V

  AVDD2                    Voltage               8 V

  DVDD                     Voltage               8 V

                                                 
  ------------------------ --------------------- ------------------------

Detector bias HV control on the interface card is done using the HDI-
enable circuit, and photovoltaic relays (no moving parts). There are two
HV lines provided per HDI to allow operation of double-sided detectors
in split bias mode. HV is supplied via 34-conductor twist & flat strip
cable to a connector on the J1 backplane.

The Interface Board operates on two voltages: +15V to run the analogue
parts of the board, which is fused at 1.5 A, and +5 V for the control of
the various drivers on the board, which is fused at 7 A.

As mentioned above already, fed to the Interface Board is the SVX power
and the power to operate the board itself. The power is provided by a
VICOR MegaPAC supply. It provides ten separate voltages. The power
levels are shown in attachments #3 and #3A. In addition if any voltage
or current exceeds a set level all output voltages will be disabled.
Settings for the trip levels are implemented via the use of
'personality' plug-in modules. Information on the personality modules
can be found on attachments #3B and #3C. This is done to prevent the
application of partial power to the KSU IB.

The power is distributed via the Fuse Panel (shown in attachment #4).
The power is brought via #10 wires from the power supply to the
distribution strips of the Fuse Panel. This wiring and the hardware of
the distribution strips can accommodate the maximum current that a
single power module can produce (worst case is 26A for the three VCC
modules, hardware and wiring are adequate to 30 A). This is particularly
important for VCC(1) and VCC(2) that are not fused (or monitored) inside
the supply. Fuses after the distribution strips limit the maximum
current that can be delivered to an individual Interface Board and
protect all circuitry beyond that point. Values of these fuses can be
found in attachments #4 and #8.

The supplies are fused on the primary 208VAC input and the DC output (DC
fusing exists only for the eight that are instrumented). The fuses (30
A) are located on the control board as indicated in attachment #5. A
solid state 3-phase relay is used to control application of AC power to
all of the Vicor supply. This relay is used as part of the interlock
system as will be described later.

A front panel is used to provide control function and indicator lights.
There will be a local On/Off, Reset and Local/Remote switch on the front
panel. There are LED indicators on the front panel showing the status of
the supply. A drawing is provided in attachment #6A and a schematic on
attachment #6B. It should be noted that for the eight instrumented
modules a remote potentiometer is used to adjust the voltages. This
adjustment is used to accommodate voltage drops in the long cable runs
and is of importance for the HDI voltages (AVDD, AVDD2 and DVDD). This
adjustment is in essence a modification of the Vicor supply.

Power is distributed from the fuse panel to each individual slot of the
J1 back plane (and thus to each individual KSU IB card) via a wire
harness composed of 14 wires of either 14 or 18 gauge. Details are shown
in attachment #7.

The J1 back is described in attachment #8, where the current carrying
capacities of the traces and the DIN connector are listed, as well as
the fuses to be used at the appropriate spigot of the Fuse Panel. The
schematic is shown in attachment #9.

The Vicor supplies have built-in analog temperature sensing that are
used for monitoring. This signal is 2.5V/25 degrees C and has a range of
0-100 degrees C. There are signals for Phase Fault, Over Temperature
Warning and AC Power OK that will be inputs to the logic control
circuitry.

-   The Phase Fault signal, which is active high, drops low when the
    input reaches the overcurrent level of 30 Amps due to a missing
    phase or severe line imbalance.

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-   The AC Power OK signal, active high, will drop low about 3ms before
    the output regulation is lost. An AC Power Fail signal is the
    compliment of the AC Power OK.

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-   The Over Temperature Warning signal, normally high, drops low
    somewhere between 65-76ºC. The recovery point is 1ºC below the
    actual trip point. This is built-in protection that activates when
    the inlet temperature exceeds 70-81 degrees C. Recovery is 10ºC
    below the actual trip level. This signal is directly ANDed with the
    External Interlock signal and controls the 208 AC input by operating
    the solid state relay.

There will be two conditions that will turn the supply off in the event
of a fault condition. The first condition occurs when a monitored supply
exceeds a preset level for more than 8 milliseconds. This can be
considered a normal fault condition. This type of fault only inhibits
the outputs of the Vicor and latches the fault until cleared.

The second condition occurs when either an External Interlock, phase
fault or temperature warning from the Vicor is false. The main 208 AC
power to the supply will be removed when this occurs. The thought here
is that a more serious fault or problem has happened and more direct
measures should be taken. This might be caused by a direct failure of a
module which fails to respond to a normal inhibit signal or smoke or
loss of cooling for the silicon detector was detected.

Also note that each HDI has its own temperature monitor, an RTD. If the
HDI temperature is above normal (60 Centigrade) circuitry in the KSU IB
will cut off the power and bias voltage to that HDI (an exception is the
F-disks where the only one of the two HDI's has an RTD). Additionally
for every HDI the current consumption of AVDD, AVDD2, and AVDD3 are
monitored and if they exceed a safe level (0.7 A) power and bias voltage
to that HDI are cut off.

A third and final level of protection will be an in-line fuse on each
output from the supply. This will ensure that wire currents will not
exceed a safe level. The fusing will be above the normal operating
levels and should not open under a normal fault condition.

Logic control will be implemented with a programmable logic gate array.
This provides the best flexibility and size reduction for the power
supply system. This flexibility comes at the price of making logical
errors. Such errors have been discovered at early running of this supply
and presently the external interlock is passed directly to the cut-off
relay, with the only requirement that it has to be on for more than 10
msec to guard against glitches and noise spikes.

Control power (+5V and +/- 15V) will be a separate supply that will be
ON whenever the AC is applied to the box. This small supply has a line
fuse.

![](media/image3.jpeg){width="3.129861111111111in"
height="2.545138888888889in"}

Figure 1

Vicor MegaPAC Supply

![](media/image4.png){width="3.4in" height="2.4145833333333333in"}

Figure 2

> PS Assembly.

![](media/image5.jpeg){width="3.4159722222222224in"
height="1.9041666666666666in"}

Figure 3

Powerpole Output Connector Arrangement

![](media/image6.jpeg){width="3.234722222222222in"
height="2.4444444444444446in"}

Figure 4

Input Power Lexan Cover.

The power supply is interlocked with the cooling system. The philosophy
behind the cooling system interlock is that the silicon detectors should
not be allowed to get too hot (and burn up) or too cold (so as to
condense humidity on them). Since the first failure can be quite severe
a two tiered protection system is used.

The first tier is inside the KSU IB card where power is turned off to an
HDI if a high temperature situation is detected or if the power
consumption is too high.

The second tier is provided by monitoring the incoming water temperature
of the water manifold used in cooling the barrel under test at the 10%
setup. An RTD is used in conjunction with a Watlow series 965 controller
(model 3CD0-0000). The relay contact output of this controller is set so
as to open if the temperature is too high (nominally set at a value less
or equal to 60 Fahrenheit) and interrupts a 5 V level.

In addition the coolant flow through the barrel's bulkhead is monitored.
A GF-Signet model 2000 Micro Flow Sensor with an 8550-3 transmitter are
used. The open collector (essentially an FET switch) is used in series
with the previously mentioned Watlow temperature sensor to interrupt the
5 V level. A minimum flow of 10 gph is the nominal set point for this
alarm; the FET switch will open if the flow is too low,

The 5V level is obtained from the water output of the RMI of the rack
containing the KSU IB crate. It is passed in series through the
temperature and flow switches and fed back to the RMI. At the RMI the
logical sum (OR) of the smoke detector and the interlock signal is used
to trip the KSU IB power supply via its external interlock input. In
addition the same interlock, via the AC distribution box is used to turn
off the fan in this rack.

A dew point meter (Vaisala HMP230 transmitter with HMP 231 sensor) is
used to monitor the dew point in the dry box that encloses the barrel.
If the dew point is too high, relay contacts in the transmitter are used
to interrupt the compressor of the water chiller. In this fashion the
water is no longer cooled and the temperature of the system will
ultimately rise. The nominal dew point setting used is 30 Fahrenheit for
high temperaure running (50 degree F coolant) or 0 degrees F for low
temperature running.

A pressure switch (Wasco TP700) is set to close if the dry air pressure
is low (below 80 psi, nominal air pressure is 100 psi) which is an
indication that the SiDet compressor(s) have failed. In such a case in
anticipation of an expected increase in the humidity the same action as
in the case of high humidity (i.e. turn the cooling off, but maintain
coolant flow) is taken.

# Sequencers

The sequencers receive the 50-conducter 3M cables from the Interface
Boards and are located on the platform. The 50-conductor cables only
carry the data, control and monitoring signals from the silicon hybrids.
No power is carried by these cables. The sequencers serialize the data
and turn them into an optical signal with 1Gbyte optical drivers. The
signals are transmitted from the sequencers through fibers with a 50μ 
aperture to the second floor of the movable counting house where they
are received by the VME Transition Modules (VTM).

Figure 3 shows a schematic of the power distribution for the sequencers.
The sequencers are powered by VICOR PFC MINI PM2-03-511 power supplies,
which generate +5 V ( at 160 A) and --5.2 V (at 76.9 A). AC to the power
supply is provided via an AC cord (208 3 phase plug, 5 conductor 12
gauge cord) which is fused by two 10 A conventional fuses. Each leg is
fed through a CRYDOM solid state relay (10 A). These two relays are used
to turn off the supply if the TTL level in the interlock input gets
removed. This interlock is provided by the RMI chassis, which has enough
drive current capability to drive the two CRYDOM relays in parallel. The
system has been tested and it does trip off if the TTL level is removed.

The output current is carried by #4 multistrand wire (THHN grade). Two
such runs are used for the +5 V (160 A) circuit, an arrangement which
can carry 170 A. Internally to the chassis a copper bus is used in many
locations -- the minimum cross section is 1/8" by 3/8", which is used to
carry 50% of the 160 A load and is adequate for a temperature rise of 35
C. 100 A shunts (100A gives a 50 mV drop) are used to monitor the
current. The front panel test points are isolated by 1000 Ω resistors.
The 160 A circuit uses two shunts in parallel. The current is fed to the
J1 backplane of the sequencer crate where it is distributed via a 1/16"
thick copper bus with a minimum width of 2". This bus can carry at least
220 A.

The SVX Sequencer J1 backplane (D0 Engineering Note Number
3823.110-EN-478) was measured for temperature rise at expected operating
current. The backplanes provide the sequencers with +5 V and -5.2 V
power. The backplane was specified by Fermilab and designed and built by
Interlogic Industries of Melville, NY. It is a six layer board with two
layers for signals, two identical layers for ground, and two identical
layers sharing the two power planes. When calculations were made to
determine the current density, some fairly large numbers resulted, most
frequently for the -5.2 V plane. The results are tabulated in tables 1
and 2.

> [Location]{.underline} [Current Density (A/sq. in.)]{.underline}
>
> Vertical channel above power bug 17,708
>
> Above slot 17, below screw hole 24,000
>
> Above slot 16 14,545
>
> Above slot 15 13,636
>
> Above slot 4 3636

Table 1: Current density calculations for portions of the J1 -5.2 V
plane. The

first two were the largest values expected due to conductor geometry.

> [Location]{.underline} [Current Density (A/sq. in.)]{.underline}
>
> Copper Channel into slot 5 5555
>
> Copper Channel into slot 9 4348
>
> Copper Channel into slots 18-21 3077
>
> Copper Channel into slots 20-21 7143
>
> Copper Channels into slot 1 27,800

Table 2. Current density calculations for portions of the J1 +5 V plane.
The

last entry was the largest value expected due to conductor geometry.

The temperature test consisted of installing power resistors in each
slot downstream (slots 2 - 15) of the suspected worst case conducting
channel, connected between the -5.2V pins and ground and powering-up the
crate. The temperature was them measured at various points until thermal
equilibrium was reached. The resistors were sized to draw slightly more
current per slot (3.3 A) than the Sequencers (3.0 A). Results are shown
in Table 3.

[Time]{.underline} [Temp at Resistors]{.underline} [Temp above slot
17]{.underline} [Temp above slot 11]{.underline}

(min) ( ^o^ F ) ( ^o^ F ) ( ^o^ F )

0 71 71 71

5 357 95 102

10 422 103 118

15 465 113 144

20 480 120 155

25 484 124 162

40 489 126 166

> Table 3. Measured temperature of the -5.2 V portion of the backplane
> at intervals after being powered. The higher temperatures at slot 11
> are due to the fact that the resistors were heating the backplane due
> to their proximity. There is actually less current through this
> portion of the backplane. The resistor in slot 15 was probably close
> enough to affect the temperature above slot 17.

The most suspect portion of the +5 V plane, the narrow conductor
channels carrying current to the two power pins of slot 1, was also
tested with a 3.3 A current draw. The temperature rise in this area was
two degrees C after thirty minutes. We conlude that the high current
density above slot 17 of the -5.2 V portion of the backplane results in
at most a 55 degree F (30 degree C) temperature rise in that area of the
backplane. This is likely to be the worst case for this board.