# Summary and Status after Run2b silicon design meeting, Friday 8/24/01

KSU and Washington were connected by speakerphone and about 10-15 people
were in attendance in the Lab A conference room

[L2-L5 geometry]{.underline}

We are converging on an outer layer design that employs stiff staves,
all 5-chip wide sensors with a pitch of 60 microns. All outer layers
will be split at z=0. Staves have in-board cooling. All outer layers
will have in-board readout with ceramic BeO hybrids. Flatness of the
substrates is an issue. The hybrids will employ "fingers" between the
SVX4 chips. The SVX4 padring layout will be identical for Dzero and CDF.
No pitch adapter is foreseen. Digital cables are attached to the hybrid
with a connector, but other options are still being considered. Current
understanding is that a 50-pin connector, 1.5 mm in height will be
adequate. Digital cables will run on top of the stave to a mini-junction
card. The thickness of the digital cable is assumed to be at most 250
microns. One mini-junction card will service two digital cables. The
digital cables will be soldered to the junction card. The connection
from the junction card to the adapter card will use twisted pair cables.
The option to be pursued is that all lines, including all power lines,
will be part of the twisted pair bundle. Two four-point RTD's will be
used per stave for temperature monitoring. The RTD's will be mounted on
the backside of the sensors. Leads will be guided between the cooling
tubes to the mini-junction card. Additional temperature monitoring on
the hybrid is to be pursued.

It should be checked if there is enough clearance between the layers
with this design. There is also a question whether this works with the
STT trigger. The assumption is that there are 20-degree sectors for the
STT. Rich Partridge will contact Uli to ensure that there are no
problems with the trigger. The whole layout with the new re-optimized
stave design should be reevaluated given that 20-degree sectors can be
employed in the trigger.

[L0-L1]{.underline}

There is a general consensus that the beampipe should be installed when
the full silicon detector is installed in the collision hall. This
implies a minimum inner radius for L0 of about 18mm to leave enough
clearance. There is also a clear preference not to have any structure
mounted on the beam pipe.

Three candidates for inner layer design still being considered are:

1.  Castellated geometry ala CDF's L00 from Bill Cooper. This is layout
    is shown in the figure below. It has 12-fold symmetry, with 2-chip
    wide sensors on the inner layer, 53 micron pitch, and 3-chip wide
    sensors on layer 1 with 55 micron pitch. The structure is split at
    z=0 and has an inner radius of 18mm.

2.  Pinwheeel geometry, shown in the second figure below, from Jim Fast.
    It has only 3-chip wide sensors, with 50 micron pitch with 6-fold
    symmetry. Inner radius is 15 mm.

3.  Layer 0b suspended from layer 1a. Layer 0a has about 70% coverage in
    phi. The inner radius is 18mm and the sensors have a pitch of 55
    micron. 2-chip wide sensors are used. Layer 0b has in-board cooling

The large cluster size of the pinwheel geometry at the edges is
unappealing. The number of analogue cables and sensors, however, is
reduced by a factor of 2. Ron Lipton showed results on impact parameter
resolution that he will try to refine. He is also going to implement
parametrized cluster size and hit resolution to simulate the edge
effects and he was going to vary the mass of layer 1.

There seemed to be a preference for on-board electronics for layer 1.
Initial carbon-foam cooling studies show that indeed the silicon can be
kept at a temperature of --9 degrees C. This needs to be tested with a
real prototype. At the moment both the on-board and off-board
electronics option for layer 1 was left open. We are, however, leaning
towards 3-chip wide sensors for L1 with 12-fold phi geometry.

There were some suggestions of making a L0/L1 unit that is dismountable
but then the trigger alignment tolerances come into question for L1.
There was also a discussion of the maximum number of chips that can be
readout in a reasonable accommodation of the DAQ rates in L0/L1.
Discussions after the meeting seemed to converge assuming that if you
can tolerate 10 chips at Layer 2 then you can accommodate 6 chips
readout (a double-ended 3 chip hybrid) in Layer 1. Rich will send around
a note if possible for L0, but our initial calculations show that 3
chips per hybrid is probably pushing the envelope. Calculations of the
number of inputs in L0 for the STT then say:

a\) L0 must be 6 fold and not 12 fold

b\) if design is 12 fold, 4 chips must be readout which seems very bad

c\) L0 is not in STT

A merging of the castellated design with a pinwheel for layer 0 seemed
to emerge during the meeting as a viable option. It was going to be
studied if a pinwheel design with a minimum inner radius of 18mm is
possible, split at z=0. The University of Washington will come up with a
design for layer 1 and will also address some of the cooling issues.
Other questions that still need to be addressed are:

-   can two 3-chip sensors be laid out on a 4 inch wafer

-   is the design acceptable for the STT

-   What should we do with STT for L0

-   Should L0 be split at Z=0

-   Should only L0 be dismountable or both L0 and L1

-   What is the limit on the number of readout chips for a hybrid for
    layer 0?

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