FPIX3 chip tests

Feb. 9, 2007

Tom Zimmerman

Fermilab - Particle Physics Division

Tests were performed on the FPIX3 chip in order to better understand
sources of instability, and to arrive at an optimal configuration. A
simplified diagram of the relevant circuits is shown below.

![](media/image1.png){width="5.99375in" height="4.940972222222222in"}

The pixel sensor feeds a charge integrator, followed by a X4 gain stage.
One master DC bias current of approximately 1 uA drives multiple current
DACs that can be programmed to set the required internal bias voltages
and bias currents.

**General biasing issues**

Programmable bias currents are derived from internal current mirrors
that are driven by current DACs (which are all referenced to the master
bias current set by an external resistor). Programmable bias voltages
are generated from current DACs that drive internal 80K resistors. One
very important programmable voltage reference is **Vref**, which sets
the output operating voltage of the second stage. The output of this
stage directly drives a PMOS transistor (MCOMP in the diagram) that
serves as the input stage of an 8-stage comparator. All of the 8
comparator thresholds are independently set by DACs. The effective
threshold of any comparator is then determined by the difference between
its threshold setting and the Vref setting.

The comparator bias current Icomp is a critically important parameter.
It affects both the comparator delay and, unintentionally and
unfortunately, the stability of the chip (which will be addressed in a
later section). Icomp is determined by (Vgs-Vt)\^2 of the MCOMP PMOS
transistor, and should nominally sit at about 0.8uA. Vt is dependent on
process variations, temperature, and radiation dose. Vgs is simply (Vref
-- Vdda), so it depends on [both]{.underline} Vref and Vdda.

Two options are available for setting the master bias current for the
chip, with different implications for the comparator bias. These are
discussed below.

**[Biasing options:]{.underline}**

The master bias can be set in one of two ways: with a resistor from
RefRes to ground, or with a resistor from Vmaster to ground, with
different implications for the chip sensitivity to variations in
parameters like process variables, threshold shifts, temperature, analog
supply voltage, etc.

1\. When using a resistor from RefRes to ground, the master current is
very stable and is determined only by a diode drop voltage that is
duplicated across the external resistor. Internal bias currents and
voltages (like Vref) are thus very insensitive to parameter and Vdda
variations, ***except*** for the comparator bias current Icomp, which is
quite sensitive since it depends not only on the Vref setting but also
on Vdda. For example, lowering Vdda by 4% (100 mV) has almost no effect
on the value of Vref or on the internal threshold (Vref -- Vth0), but
causes an 18% reduction in Icomp.

2\. When using a resistor from Vmaster to ground, the master current is
somewhat affected by parameter variations and Vdda, meaning that the
internal bias currents and voltages are also somewhat affected. However,
the Icomp sensitivity is considerably lower than with the RefRes method,
since both Vdda and Vref tend to move together. For example, lowering
Vdda by 4% (100 mV) decreases both the threshold level *and* Icomp by
about 5%.

Run-to-run (or even wafer-to-wafer) variations could thus have a
noticeable impact on comparator current draw and power dissipation when
using method 1. Method 2 results in some variation in internal bias
levels (not a big problem), but offers a more consistent comparator bias
level (desirable). Since the comparator bias level is critical to
stability, **method 2 is highly recommended**.

The following tests were performed with the two different biasing
methods, and show the sensitivity of Vref and Vth0 to the value of the
bias resistor and changes in Vdda. For these tests, the Vref DAC was set
to 202 (the default FFR value), and the Vth0 DAC to 182. Notice that
with method 1, the digital to analog conversion factor (∆ Vth/count)
remains very stable with varying Vdda, but the supply current draw
varies substantially (due to variation in comparator bias). With method
2, the conversion factor varies somewhat with Vdda, as does comparator
bias, but the comparator bias variation is much smaller than observed
with method 1.

**[REFRES bias (method #1)]{.underline}**

  -------------- ------------ ----------- ------------- -------------------
  Rbias1         Vdd - Vref   Iavdd       Vref - Vth0   (∆ Vth)/(DAC count)
                              (total)                   

  561K           0.654 V      65 mA       172 mV        9.2 mV

  585K           0.734 V      75          165           8.7

  618K           0.832 V      90          156           8.2
  -------------- ------------ ----------- ------------- -------------------

Use Rbias = 585K, and vary Vdd:

  -------------- ------------ ----------- ------------- -------------------
  Vdda           Vdd - Vref   Iavdd       Vref - Vth0   (∆ Vth)/(DAC count)
                              (total)                   

  2.4            0.639 V      60 mA       165 mV        8.7 mV

  2.5            0.734 V      75          165           8.7

  2.6            0.834 V      90          165           8.7
  -------------- ------------ ----------- ------------- -------------------

**[Vmaster bias (method #2)]{.underline}**

  -------------- ------------ ----------- ------------- -------------------
  Rbias1         Vdd - Vref   Iavdd       Vref - Vth0   (∆ Vth)/(DAC count)
                              (total)                   

  1.382 Meg      0.71 V       75 mA       170 mV        8.5 mV

  1.440 Meg      0.78 V       80          161           8.5

  1.500 Meg      0.84 V       90          154           8.2
  -------------- ------------ ----------- ------------- -------------------

Use Rbias = 1.440 Meg, and vary Vdd:

  -------------- ------------ ----------- ------------- -------------------
  Vdda           Vdd - Vref   Iavdd       Vref - Vth0   (∆ Vth)/(DAC count)
                              (total)                   

  2.4            0.771 V      75 mA       152 mV        8.1 mV

  2.5            0.776 V      80          161           8.5

  2.6            0.781 V      85          170           9.0
  -------------- ------------ ----------- ------------- -------------------

**Biasing for FFR stability**

The resistor values chosen in the previous section were based on
achieving the nominal DC bias conditions with the FFR (Fire Fighter
Reset) register settings. Unfortunately, the FFR default conditions
usually result in oscillation, obviously not a desired result of any
master reset. (The major reason for the oscillation is that FFR turns on
all 8 comparators -- more on this later). Therefore, a revised Vmaster
bias resistor of 910K is suggested, which essentially kills the bias of
the second stage and comparators, inhibiting oscillation and allowing a
"clean" FFR. This changes the granularity of all the DACs. For example,
the reference voltage granularity changes from approximately 7.5
mV/count to 12 mV/count, which is still acceptable.

**[The FFR default register settings are:]{.underline}**

Ibp1=100

Ibp2=74

Ibb=29

Iff=13

Vref=202

Vfb2=172 (always 30 counts less than Vref)

Voltage reference DACs are approximately 7.5 mV/count (varies chip to
chip) with a 1.44Meg resistor on Vmaster

**[With a bias resistor of 910K on Vmaster, the registers should be
programmed as follows:]{.underline}**

Ibp1=0

Ibp2=0

Ibb=18

Iff=8

Vref=122 (this depends on the desired comparator bias and speed)

Vfb2=103 (always 19 counts less than Vref)

Voltage reference DACs are approximately 12 mV/count (varies chip to
chip)

**Comparator bias issues**

The comparator bias is probably the most important parameter that can be
controlled by the user (through the Vref setting), since it affects the
chip stability. The total comparator bias current is affected by Vref,
which sets the current per comparator stage, and the threshold settings
Vth0-7, which determine how many of the eight comparator stages are
enabled. Comparator bias levels were measured on an 8-chip module with a
sensor. The revised master bias resistor value of 910K was used, and
Vdda was set at 2.3. The following table shows the measured comparator
bias level (per comparator) on one chip as a function of Vref.

+--------------------+--------------------+----------------------------+
| Vref DAC           | Vdda - Vref        | Ibias per                  |
|                    |                    |                            |
|                    |                    | comparator                 |
+--------------------+--------------------+----------------------------+
| 138                | 0.65 V             | 0.13 uA                    |
+--------------------+--------------------+----------------------------+
| 135                | 0.69 V             | 0.17 uA                    |
+--------------------+--------------------+----------------------------+
| 130                | 0.75 V             | 0.35 uA                    |
+--------------------+--------------------+----------------------------+
| 125                | 0.81 V             | 0.58 uA                    |
+--------------------+--------------------+----------------------------+
| 120                | 0.87 V             | 0.87 uA                    |
+--------------------+--------------------+----------------------------+
| 115                | 0.93 V             | 1.22 uA                    |
+--------------------+--------------------+----------------------------+
| 110                | 0.99 V             | 1.62 uA                    |
+--------------------+--------------------+----------------------------+

Over all 8 chips, there is a chip to chip spread in comparator bias
current for a given Vref setting. In the module tested, this spread was
a substantial 50% from the lowest to the highest. The results shown in
the table are for the chip that has the lowest comparator bias for a
given Vref setting, so probably represent the "low case" more than the
"nominal case". If consistent chip to chip comparator delay is desired,
then the Vref setting may need to be "tweaked" for each chip based on
measurements.

The comparator speed is directly affected by the bias level.
Measurements are shown below for a chip that has a charge gain of 340
mV/fC and a DAC granularity of 12 mV/count. The threshold is always set
to 10 counts below Vref, but there is a threshold offset of several
counts, which results in an effective threshold setting of about 1400 e.
These measurements were performed by applying a "triangular" input pulse
to the FPIX test injection input, with a 60 ns leading edge and a 2 us
trailing edge. The delay is measured from the time that the comparator
input crosses the set threshold. The time walk effect from different
pulse amplitudes is [not]{.underline} taken into account here, so would
need to be added to the measured delay.

**[Input = 1600 e]{.underline}**

+-----------------------+-----------------------+-----------------------+
| Vref DAC              | Vth0 DAC              | Delay from            |
|                       |                       |                       |
|                       |                       | threshold             |
|                       |                       |                       |
|                       |                       | crossing              |
+-----------------------+-----------------------+-----------------------+
| 125                   | 115                   | \-\--                 |
+-----------------------+-----------------------+-----------------------+
| 120                   | 110                   | \-\--                 |
+-----------------------+-----------------------+-----------------------+
| 115                   | 105                   | 99 ns                 |
+-----------------------+-----------------------+-----------------------+
| 110                   | 100                   | 78 ns                 |
+-----------------------+-----------------------+-----------------------+

**[Input = 1800 e]{.underline}**

+-----------------------+-----------------------+-----------------------+
| Vref DAC              | Vth0 DAC              | Delay from            |
|                       |                       |                       |
|                       |                       | threshold             |
|                       |                       |                       |
|                       |                       | crossing              |
+-----------------------+-----------------------+-----------------------+
| 127                   | 117                   | \-\--                 |
+-----------------------+-----------------------+-----------------------+
| 125                   | 115                   | 176 ns                |
+-----------------------+-----------------------+-----------------------+
| 120                   | 110                   | 111 ns                |
+-----------------------+-----------------------+-----------------------+
| 115                   | 105                   | 89 ns                 |
+-----------------------+-----------------------+-----------------------+

**[Input = 2000 e]{.underline}**

+-----------------------+-----------------------+-----------------------+
| Vref DAC              | Vth0 DAC              | Delay from            |
|                       |                       |                       |
|                       |                       | threshold             |
|                       |                       |                       |
|                       |                       | crossing              |
+-----------------------+-----------------------+-----------------------+
| 133                   | 123                   | \-\--                 |
+-----------------------+-----------------------+-----------------------+
| 130                   | 120                   | 186 ns                |
+-----------------------+-----------------------+-----------------------+
| 125                   | 115                   | 119 ns                |
+-----------------------+-----------------------+-----------------------+
| 120                   | 110                   | 83 ns                 |
+-----------------------+-----------------------+-----------------------+
| 115                   | 105                   | 61 ns                 |
+-----------------------+-----------------------+-----------------------+

**[Input = 2400 e]{.underline}**

+-----------------------+-----------------------+-----------------------+
| Vref DAC              | Vth0 DAC              | Delay from            |
|                       |                       |                       |
|                       |                       | threshold             |
|                       |                       |                       |
|                       |                       | crossing              |
+-----------------------+-----------------------+-----------------------+
| \>141                 |                       | \-\--                 |
+-----------------------+-----------------------+-----------------------+
| 141                   | 131                   | 275 ns                |
+-----------------------+-----------------------+-----------------------+
| 135                   | 125                   | 169 ns                |
+-----------------------+-----------------------+-----------------------+
| 130                   | 120                   | 119 ns                |
+-----------------------+-----------------------+-----------------------+
| 125                   | 115                   | 85 ns                 |
+-----------------------+-----------------------+-----------------------+
| 120                   | 110                   | 68 ns                 |
+-----------------------+-----------------------+-----------------------+
| 115                   | 105                   | 54 ns                 |
+-----------------------+-----------------------+-----------------------+

**[Input = 3600 e]{.underline}**

+-----------------------+-----------------------+-----------------------+
| Vref DAC              | Vth0 DAC              | Delay from            |
|                       |                       |                       |
|                       |                       | threshold             |
|                       |                       |                       |
|                       |                       | crossing              |
+-----------------------+-----------------------+-----------------------+
| 135                   | 125                   | 93 ns                 |
+-----------------------+-----------------------+-----------------------+
| 125                   | 115                   | 57 ns                 |
+-----------------------+-----------------------+-----------------------+
| 115                   | 105                   | 42 ns                 |
+-----------------------+-----------------------+-----------------------+

**[Input = 7200 e]{.underline}**

+-----------------------+-----------------------+-----------------------+
| Vref DAC              | Vth0 DAC              | Delay from            |
|                       |                       |                       |
|                       |                       | threshold             |
|                       |                       |                       |
|                       |                       | crossing              |
+-----------------------+-----------------------+-----------------------+
| 135                   | 125                   | 60 ns                 |
+-----------------------+-----------------------+-----------------------+
| 125                   | 115                   | 43 ns                 |
+-----------------------+-----------------------+-----------------------+
| 115                   | 105                   | 33 ns                 |
+-----------------------+-----------------------+-----------------------+

**Gain and calibration issues**

The sensor capacitance from a standard pixel input to the sensor
backside is 10 fF. This is found by measuring the total backside
capacitance of a sensor and dividing by 23\*128\*(# of chips). (There
are 20 columns of 128 standard size pixels and 2 columns of 128 pixels
that are 50% larger, giving effectively "23 columns of standard size
pixels"). This measurement is quite consistent and varies very little
over different sensors. By applying a known voltage step to the sensor
backside, a known charge can be injected into each pixel, thereby
allowing an absolute calibration of the FPIX chip. When this is done
over a number of FPIX chips, the gain is found to vary substantially.
This is not too surprising, since this gain is set mostly by the
integrator feedback capacitance, which is formed using field oxide that
is not well controlled. The gain observed over a limited number of chips
was in the range of 290 - 500 mV/fC, which is quite a large variation
chip to chip. It may therefore be desirable to calibrate each chip in a
system by using this method.

**Stability problems**

FPIX chips are observed to have serious stability problems, especially
when they are coupled with sensors. Oscillation can result from any or
all of *several* on-chip unintended positive feedback paths. These paths
are enabled by the presence of parasitic resistance in the analog ground
and supply lines, as shown in the FPIX block diagram. Each of these
positive feedback paths will be discussed.

In one potential feedback path, a change in comparator current couples
through the Vdda parasitic resistance back to the DAC reference circuits
and causes a reduction in DAC currents, which in turn causes a reduction
in Vref, propagating through the second stage and causing a further
change in comparator current that reinforces the original change. The
gain of this positive feedback path can easily be killed by bypassing
Vref externally with 0.1 uF or more. (Any bypass capacitor on Vmaster
must be at least 10 times smaller than the Vref bypass to insure that
this positive feedback path is suppressed).

A DC stability problem exists in the same area of the circuit that can
be caused by internal transistor leakage current. There is an
unintentional leakage current (labeled Ileak in the block diagram) from
the DAC programming switches that can divert a significant portion of
the master Ibias under certain circumstances. There are 14 DACs, each
with 256 sections, so even a small leakage current per switch transistor
can have a big effect. The leakage is very dependent on the Vgs of the
switch (and on other parameters like temperature), and can vary
substantially from run to run. The Vgs seen by the switch is (Vddd --
Vdda), since the logic driving the switches is powered by the digital
supply. (Vgs here is normally negative, since the transistor is PMOS).
On the particular chip tested, the leakage current becomes noticeable
for Vgs \< 0, so if the value of Vdda is raised above Vddd, the leakage
begins robbing significant current from the master reference. The
portion of the master Ibias current seen by its PMOS mirror transistor
thus begins decreasing significantly. This means that all programmed
bias currents and voltages on the chip begin decreasing, including Vref.
Lowering Vref *increases* the comparator bias current significantly,
raising the Vdda current. The end result is that when Vdda is raised
above Vddd, the internal biases are corrupted and the Vdda supply
current increases rapidly with voltage. This unintended behavior leads
to the following constraint: Vdda should always be set to a value that
is approximately 0.2 volts lower than Vddd. This insures that the
unintentional leakage current always remains insignificant, even with
elevated temperatures and/or process variations over different wafers.

Two other more problematic positive feedback paths exist, both of them
from the comparator section back to the integrator. These paths are
enabled by the parasitic ground and supply resistance. A changing
comparator current causes voltage changes on both supply and ground,
which each couple charge to the integrator input through a capacitance
(parasitic capacitance from Vdda to input, and sensor capacitance from
ground to input). In both cases, the parasitic charge coupled to the
integrator causes a voltage change at the output of the second stage
that reinforces the original change in comparator current, resulting in
positive feedback. (This behavior could have been avoided by using
separate supply nets for the comparators).

Multiple factors affect the strength of this feedback, some of which are
under user control and others which are not:

-   Comparator gm (depends on comparator bias **[and]{.underline}** \#
    of sections used)

-   Parasitic R in ground supply bus (shunted somewhat by the substrate)

-   Parasitic R in Vdda supply bus

-   Parasitic C from Vdda to integrator input (several fF)

-   Sensor C from external ground to integrator input

-   Integrator feedback C (sets the FPIX charge gain)

Unfortunately, there can be a substantial chip to chip variation in most
of these factors. This results in an unavoidable chip to chip variation
in sensitivity to oscillation, given identical master bias and DAC
settings.

**Stability tests with an 8-chip module**

A module with 8 chips bump bonded to a sensor was used to investigate
stability as a function of

-   How many of the 8 comparator sections on each chip are enabled (a
    comparator is disabled by setting its threshold to 255)

-   Vref setting

-   How many of the 8 chips on the module are enabled

The module has one common Vdda supply and one common Vddd supply. In the
following tables, "Min. Vref" is the minimum Vref register value found
to result in stability. However, since a Vref value any lower would
result in oscillation, practical values of Vref for operation should be
well above the minimum Vref for safety margin.

**[3 comparator sections enabled per chip]{.underline}**

+---------------------------------+------------------------------------+
| Chips                           | Min. Vref                          |
|                                 |                                    |
| enabled                         |                                    |
+---------------------------------+------------------------------------+
| 1                               | 118                                |
+---------------------------------+------------------------------------+
| 2                               | 118                                |
+---------------------------------+------------------------------------+
| 3                               | 116                                |
+---------------------------------+------------------------------------+
| 4                               | 114                                |
+---------------------------------+------------------------------------+
| 5                               | 115                                |
+---------------------------------+------------------------------------+
| 6                               | 112                                |
+---------------------------------+------------------------------------+
| 7                               | 114                                |
+---------------------------------+------------------------------------+
| 8                               | 122                                |
+---------------------------------+------------------------------------+
| 1-8 (all)                       | 135                                |
+---------------------------------+------------------------------------+
| 1-7                             | 122                                |
+---------------------------------+------------------------------------+
| 4,5,6,7                         | 118                                |
+---------------------------------+------------------------------------+
| 4,6,7,8                         | 126                                |
+---------------------------------+------------------------------------+
| 6,7,8                           | 126                                |
+---------------------------------+------------------------------------+
| 4,6,7                           | 117                                |
+---------------------------------+------------------------------------+

**[8 comparator sections enabled per chip]{.underline}**

+---------------------------------+------------------------------------+
| Chips                           | Min. Vref                          |
|                                 |                                    |
| enabled                         |                                    |
+---------------------------------+------------------------------------+
| 1-8 (all)                       | 147                                |
+---------------------------------+------------------------------------+
| 1-7                             | 137                                |
+---------------------------------+------------------------------------+
| 8                               | 138                                |
+---------------------------------+------------------------------------+
| 4                               | 130                                |
+---------------------------------+------------------------------------+

**[4 comparator sections enabled per chip]{.underline}**

+---------------------------------+------------------------------------+
| Chips                           | Min. Vref                          |
|                                 |                                    |
| enabled                         |                                    |
+---------------------------------+------------------------------------+
| 1-8 (all)                       | 139                                |
+---------------------------------+------------------------------------+
| 1-7                             | 127                                |
+---------------------------------+------------------------------------+
| 8                               | 126                                |
+---------------------------------+------------------------------------+
| 4                               | 120                                |
+---------------------------------+------------------------------------+
| 4,5,6,7                         | 124                                |
+---------------------------------+------------------------------------+
| 4,5,6,8                         | 135                                |
+---------------------------------+------------------------------------+

**[2 comparator sections enabled per chip]{.underline}**

+---------------------------------+------------------------------------+
| Chips                           | Min. Vref                          |
|                                 |                                    |
| enabled                         |                                    |
+---------------------------------+------------------------------------+
| 1-8 (all)                       | 130                                |
+---------------------------------+------------------------------------+
| 1-7                             | 113                                |
+---------------------------------+------------------------------------+
| 8                               | 122                                |
+---------------------------------+------------------------------------+
| 4                               | 104                                |
+---------------------------------+------------------------------------+

**[1 comparator section enabled per chip]{.underline}**

+---------------------------------+------------------------------------+
| Chips                           | Min. Vref                          |
|                                 |                                    |
| enabled                         |                                    |
+---------------------------------+------------------------------------+
| 1-8 (all)                       | 100 (not consistent)               |
+---------------------------------+------------------------------------+
| 8                               | 100                                |
+---------------------------------+------------------------------------+
| 4                               | 84                                 |
+---------------------------------+------------------------------------+

The test results show that if any one chip oscillates, all chips begin
to oscillate. In addition, when more than chip is enabled, the
oscillation begins earlier than with any of the individual chips.
Presumably, this is due to interaction between chips on a common
(non-zero impedance) supply. Unfortunately, the sensitivity of multiple
chips to oscillation is determined by the **one most sensitive chip**.

**The "best" configuration**

Following is a summary of all important recommendations for biasing and
operating FPIX chips:

-   Vdda = 2.3V, Vddd = 2.5V

-   Bias with 910K resistor from Vmaster to ground (no REFRES resistor)

-   0.1 uF or bigger bypass from Vref to ground

-   0.1 uF or bigger bypass from Vbp1 to ground

-   0.1 uF or bigger bypass from Vth0 to ground (for threshold
    stability)

-   Minimize Vdda and ground resistance on PCB

-   0.01 uF bypass from Vmaster to Vdda (for ESD protection only). Note
    this cap must be at least a factor of 10 smaller than the Vref
    bypass to avoid oscillation.

-   Suggested DAC settings with 910K bias resistor: Vref=122, Vfb2=103
    (always Vref-19), Ibp1=0, Ibp2=0, Ibb=18, and Iff=8.

**Summary**

Attention to biasing, bypassing, etc., can help the immunity to
oscillation, but by far the two most important factors are:

-   **The comparator bias current level**

-   **The number of comparator sections used**

At present, only one 8-chip module with a sensor has been tested. There
is significant chip to chip variation in the sensitivity to oscillation.
The sensitivity of the module as a whole is unfortunately determined by
the most sensitive chip. With a reasonable comparator bias current
(giving reasonable comparator delay), operating all chips with one
comparator seems safe. Using more than one comparator per chip is risky
unless the comparator bias is reduced. Separating the integrator and
comparator supply nets would resolve the stability problem, allowing any
number of comparator sections to be used. However, this would require a
new fabrication run.