HEP008 Project Description and Definition:

Prototype SVX -- HDI Test Stand Interface Module

Version: 3.

Prepared by the

Electronics Design Laboratory

Kansas State University

November 12, 2023

Table of Contents

1 Introduction [1](#introduction)

1.1 Document Information [1](#document-information)

1.2 Method of Contact [1](#method-of-contact)

1.3 The Electronics Design Laboratory (EDL)
[1](#the-electronics-design-laboratory-edl)

2 Project Overview [2](#project-overview)

2.1 Current Status [2](#current-status)

2.2 Estimated Milestones [2](#estimated-milestones)

2.3 General Assumptions [2](#general-assumptions)

2.4 Project Completion [2](#project-completion)

3 Project Description and Definition
[3](#project-description-and-definition)

3.1 Physical Embodiment [3](#physical-embodiment)

3.2 Connectors [3](#connectors)

3.2.1 SVX Sequencer Cable Connector 1 (J001)
[3](#svx-sequencer-cable-connector-1-j001)

3.2.2 SVX Sequencer Cable Connector 2 (J003)
[4](#svx-sequencer-cable-connector-2-j003)

3.2.3 HDI Interface Connector (J008, J002)
[4](#hdi-interface-connector-j008-j002)

3.2.4 Detector Bias Voltage Connector (J009, J006)
[5](#detector-bias-voltage-connector-j009-j006)

3.2.5 SVX Power Supply Connector (J004)
[5](#svx-power-supply-connector-j004)

3.2.6 Module Power Connector (J005) [5](#module-power-connector-j005)

3.2.7 Monitor Cable Connector (J007) [6](#monitor-cable-connector-j007)

3.3 Power Requirements [7](#power-requirements)

3.3.1 Board Power Supply [7](#board-power-supply)

3.3.2 SVX Input Power Supply [7](#svx-input-power-supply)

3.3.3 SVX Output Power Supply [7](#svx-output-power-supply)

3.4 Board Functions [8](#board-functions)

3.4.1 Digital Signal Buffering and Termination
[8](#digital-signal-buffering-and-termination)

3.4.2 Temperature Monitoring [8](#temperature-monitoring)

3.4.3 Power Control [9](#power-control)

3.4.4 Low-voltage Current Monitoring
[9](#low-voltage-current-monitoring)

3.4.5 High-voltage Current Monitoring (phased-out)
[9](#high-voltage-current-monitoring-phased-out)

# 1 Introduction

This section gives the details of this Project Definition document and
contact information for the people directly involved with this document
and this project.

## 1.1 Document Information

> Creation Date: 6/19/1998
>
> Revision Date: 3/23/1999 12:59 AM
>
> Version: 3.
>
> Project Manager:
>
> Author: Dean Hall

## 1.2 Method of Contact

The primary contact for this project is:

Tim Sobering

Director, Electronics Design Laboratory

ksuedl@ksu.edu

\(785\) 532-7826

The secondary contact for this project is:

Dean Hall

Design Intern, Electronics Design Laboratory

dwhall@ksu.edu

\(785\) 532-2097

## 1.3 The Electronics Design Laboratory (EDL)

The EDL is a department under the office of the Vice Provost for
Research at Kansas State University. The EDL was created to support the
research programs at the University by providing expertise in the
development of high-end electronics and computer-based data acquisition
systems. The goals of the EDL are to:

-   Give the faculty easier access to advanced electronics technologies.

-   Assist with integrating new electronics technologies into the
    research programs.

-   Transfer those technologies to the users.

**Contact information for the EDL:**

> The Electronics Design Laboratory
>
> 124 Burt Hall
>
> Kansas State University
>
> Manhattan, KS 66506-0400
>
> voice: (785) 532-7826
>
> fax: (785) 532-2092
>
> email: ksuedl@ksu.edu
>
> www: http://www.ksu.edu/ksuedl

# 2 

# Project Overview

## 2.1 Current Status

We are collecting project specification data and defining our own
specifications where no data is available. We are working primarily from
M. Matulik's "Test Stand Interface Module" drawings (Drawing Number:
3823.112-EB-330146) dated Mar. 17, 1998. Other sources of working data
include the D0 Silicon Upgrade Net Specifications dated 03/16/98, the D0
Silicon Detector Parts List (not dated), and miscellaneous emails from
R. Lipton, M. Matulik, and M. Utes. Work will proceed according to the
milestones listed below.

## 2.2 Estimated Milestones

6/19/1998 Project definition complete

6/26 Project definition approval

7/17 Schematic design complete

7/24 Schematic design approval

8/14 PCB layout complete

9/11 Fabrication/stuff of 16 prototypes complete

9/18 Delivery of first prototype

10/2 Board bench-testing complete

10/5 Delivery of 16 prototypes complete

## 2.3 General Assumptions

We are working from the data we have, will ask questions over missing
data that appears critical, and will make our own design decisions
elsewhere. We will not design anything that is not specified.

## 2.4 Project Completion

The first prototype interface card will be delivered on (or about) 9/18.
Based on results, requirements will be modified and work will continue
on the design and development of a final product.

# 3 

# Project Description and Definition

## 3.1 Physical Embodiment

The prototype SVX-HDI Test Stand Interface Module (hereafter referred to
as "board") is to be one printed circuit board (PCB). After the first
board is tested, 15 more boards will be created. The board dimensions
are not specified, but are approximately 280mm by 200mm from an obsolete
drawing by M. Matulik dated 02/10/97. An attempt will be made to design
the board for commercial VME packaging (6U by 180mm if possible,
otherwise 9U by 280mm board holder with no backplane). The board will
contain all the electronic parts necessary to realize its function. The
board will feature nine connectors. The layout of the connectors will
reflect logical flow of the data. The board will be housed in a rack
stored at room temperature (26°C), with temperatures reaching 30°C
maximum.

## 3.2 Connectors

The following table lists the known connectors needed:

  --------- -------- ---------- --------------- -------------- -----------------------
  **Conn.   **Mod.   **Mfg.**   **Part No.**    **Contacts**   **Description**
  No.**     No.**                                              

  J001      M001     3M         3433-5302       50 male        SVX sequencer cable
                                                               conn. 1

  J003      M004     3M         N10250-5242VC   50 female      SVX sequencer cable
                                                               conn. 2

  J002      M007     3M         3764-5302       64 male        HDI interface conn.

  J008      M003     3M         3764-5302       64 male        HDI interface conn.

  J004      M030     Molex      26-61-5060      6 male         SVX power conn.

  J005      M031     Molex      26-61-5120      12 male        Module power conn.

  J006      M020     Molex      26-61-5100      10 male        Detector bias voltage
                                                               conn.

  J009      M009     Molex      26-61-5100      10 male        Detector bias voltage
                                                               conn.

  J007      M032     3M         3431-5302       34 male        Monitor cable conn.
  --------- -------- ---------- --------------- -------------- -----------------------

All pin assignments for every connector in the following sections come
from M. Matulik's schematics.

### 3.2.1 SVX Sequencer Cable Connector 1 (J001)

Schematic M004 indicates that J001is a 50 contact 3M 3433-5302 male
connector. This connector will be placed on the prototype boards, but
will be phased-out for the final boards. The following table describes
the pin assignment for this connector:

  ------- ---------------- ------- ---------------- ------- ----------------
  **Pin   **Signal**       **Pin   **Signal**       **Pin   **Signal**
  No.**                    No.**                    No.**   

  1       GNDD             18      D4               35      GNDD

  2       NC               19      D3               36      MODE0

  3       NC               20      GNDD             37      NC

  4       NC               21      NC               38      NC

  5       GNDD             22      NC               39      VCAL

  6       NC               23      D0               40      GNDD

  7       DVALID           24      D5               41      MODE1

  8       NC               25      GNDD             42      CHANGE_MODE

  9       NC               26      NC               43      NC

  10      GNDD             27      D2               44      NC

  11      NC               28      D1               45      GNDD

  12      NC               29      NC               46      NC

  13      NC               30      GNDD             47      PRIORITY_OUT

  14      PRIORITY_IN      31      DIR              48      NC

  15      GNDD             32      HDI_ENABLE       49      NC

  16      D7               33      /CLK             50      GNDD

  17      D6               34      CLK                      
  ------- ---------------- ------- ---------------- ------- ----------------

### 3.2.2 SVX Sequencer Cable Connector 2 (J003)

The 2-channel SVX sequencer cable connector (J003) is a 3M
N10250-5242VC, 50-contact, female, right angle, Mini-D receptacle. The
following table describes the pin assignment for this connector:

  ------- ---------------- ------- ---------------- ------- ----------------
  **Pin   **Signal**       **Pin   **Signal**       **Pin   **Signal**
  No.**                    No.**                    No.**   

  1       NC               18      DB3              35      DA0

  2       GNDD             19      DB5              36      DVALID_A

  3       /CLK_A           20      DB7              37      DIR_A

  4       NC               21      MODE1_B          38      VCAL_B

  5       CHG_MODE_A       22      PRIORITY_IN_B    39      PRIORITY_OUT_B

  6       MODE0_A          23      NC               40      HDI_ENABLE_B

  7       DA6              24      CLK_B            41      DB1

  8       DA4              25      NC               42      DB2

  9       DA2              26      NC               43      DB4

  10      DA1              27      CLK_A            44      DB6

  11      HDI_ENABLE_A     28      NC               45      MODE0_B

  12      PRIORITY_OUT_A   29      PRIORITY_IN_A    46      CHANGE_MODE_B

  13      VCAL_A           30      MODE1_A          47      NC

  14      DIR_B            31      DA7              48      /CLK_B

  15      DVALID_B         32      DA5              49      GNDD

  16      DB0              33      DA3              50      NC

  17      GNDD             34      GNDD                     
  ------- ---------------- ------- ---------------- ------- ----------------

### 3.2.3 HDI Interface Connector (J008, J002)

The HDI interface connectors (J008 and J002) are 3M 3764-5302,
64-contact, male, right angle latch/ejector headers. A design note in
module M003 says that since analog ground and digital ground are
different nets, they must be connected in one place just before the HDI
connector. The pin assignment for both connectors can be altered for
better layout in the final revision, but the prototype assignment is as
follows:

  ------------- ---------------------- ------------- ---------------------
  **Pin         **Signal**             **Pin         **Signal**
  Number**                             Number**      

  1             PRIORITY_OUT           33            PRIORITY_IN

  2             GNDD                   34            GNDD

  3             DVALID                 35            AVDD

  4             GNDD                   36            GNDD

  5             VCAL                   37            AVDD

  6             GNDD                   38            GNDD

  7             MODE0                  39            AVDD2

  8             GNDD                   40            GNDD

  9             MODE1                  41            AVDD2

  10            GNDD                   42            GNDD

  11            CHANGE_MODE            43            DVDD

  12            GNDD                   44            GNDD

  13            /CLK                   45            DVDD

  14            GNDD                   46            GNDD

  15            CLK                    47            TEMP

  16            GNDD                   48            GNDD

  17            D0                     49            TEMP_RET

  18            GNDD                   50            GNDD

  19            D1                     51            NC

  20            GNDD                   52            GNDD

  21            D2                     53            PRIM_BIAS

  22            GNDD                   54            GNDD

  23            D3                     55            NC

  24            GNDD                   56            GNDD

  25            D4                     57            PRIM_GUARD

  26            GNDD                   58            GNDD

  27            D5                     59            NC

  28            GNDD                   60            GNDD

  29            D6                     61            SEC_BIAS

  30            GNDD                   62            GNDD

  31            D7                     63            P_STOP

  32            GNDD                   64            GNDD
  ------------- ---------------------- ------------- ---------------------

### 3.2.4 Detector Bias Voltage Connector (J009, J006)

The detector bias voltage connectors (J009 and J006) are Molex
26-61-5100, 10-contact, male, right angle friction locks. The pin
assignment is as follows:

  -------------------------------- --------------------------------------
  **Pin Number**                   **Signal**

  1                                PRIM_BIAS

  2                                GNDA

  3                                PRIM_GUARD

  4                                GNDA

  5                                SEC_BIAS

  6                                GNDA

  7                                P_STOP

  8                                GNDA

  9                                NC

  10                               GNDA
  -------------------------------- --------------------------------------

### 3.2.5 SVX Power Supply Connector (J004)

The SVX power supply connector (J004) is a Molex 26-61-5060, 6-contact,
male, right angle friction lock. The pin assignment is as follows:

  ----------------------------- -----------------------------------------
  **Pin Number**                **Signal**

  1                             AVDD

  2                             AVDD-

  3                             AVDD2

  4                             AVDD2-

  5                             DVDD

  6                             DVDD-
  ----------------------------- -----------------------------------------

### 3.2.6 Module Power Connector (J005)

The module power connector (J005) is a Molex 26-61-5120, 12-contact,
male, right angle friction lock. The pin assignment is as follows:

  ----------------------------- -----------------------------------------
  **Pin Number**                **Signal**

  1                             15V+

  2                             GNDA

  3                             15V-

  4                             GNDA

  5                             5V+

  6                             GNDD

  7                             NC

  8                             NC

  9                             ISO_15V+ (phased-out)

  10                            GNDI (phased-out)

  11                            ISO_15V- (phased-out)

  12                            GNDI (phased-out)
  ----------------------------- -----------------------------------------

### 3.2.7 Monitor Cable Connector (J007)

The monitor cable connector (J007) is a 3M 3431-5302, 34-contact, male,
right angle, dual-row, latch/ejector header. The pin assignment is as
follows:

  ------------- ---------------------- ------------- ---------------------
  **Pin         **Signal**             **Pin         **Signal**
  Number**                             Number**      

  1             I_AVDD_A               18            GNDA

  2             GNDA                   19            I_AVDD2_B

  3             I_AVDD2_A              20            GNDA

  4             GNDA                   21            I_DVDD_B

  5             I_DVDD_A               22            GNDA

  6             GNDA                   23            I_PRIM_BIAS_B

  7             I_PRIM_BIAS_A          24            GNDA

  8             GNDA                   25            I_PRIM_GUARD_B

  9             I_PRIM_GUARD_A         26            GNDA

  10            GNDA                   27            I_SEC_BIAS_B

  11            I_SEC_BIAS_A           28            GNDA

  12            GNDA                   29            I_P_STOP_B

  13            I_P_STOP_A             30            GNDA

  14            GNDA                   31            TEMP_B

  15            TEMP_A                 32            GNDA

  16            GNDA                   33            NC

  17            I_AVDD_B               34            GNDA
  ------------- ---------------------- ------------- ---------------------

## 3.3 

## Power Requirements

The board handles two categories of power supplies: board power supply
and SVX power supply. The board power supply is meant only for devices
on the board while the SVX power supply is meant only for the SVX chips.
Since the SVX power supply has input and output connectors, two
specifications must be determined.

### 3.3.1 Board Power Supply

The board is supplied power from outside sources through connector J005
(in module M031). The outside power sources are regulated, and only
on-board decoupling is necessary. Since the supply is externally
regulated, exact values may be specified; this removes any TBD value for
the voltages. No power is shared from the SVX input power supply. The
isolated power supply will not be needed since the high-voltage current
monitoring subsystem is phased out. The following table shows the power
requirements taken from D0 Silicon Upgrade Net Specifications.

+-------------+--------------+--------------+-------------------------+
| **Net**     | **Voltage**  | **Max.       | **Description**         |
|             |              | Current**    |                         |
|             | **(V)**      |              |                         |
|             |              | **(mA)**     |                         |
+-------------+--------------+--------------+-------------------------+
| +15V        | +15          | 200          | Positive analog supply  |
+-------------+--------------+--------------+-------------------------+
| -15V        | -15          | 200          | Negative analog supply  |
+-------------+--------------+--------------+-------------------------+
| +5V         | +5           | 500          | Digital supply          |
+-------------+--------------+--------------+-------------------------+
| +15V(ISO)   | NA           | NA           | Isolated 15V supply     |
|             |              |              | (phased-out)            |
+-------------+--------------+--------------+-------------------------+
| -15V(ISO)   | NA           | NA           | Isolated -15V supply    |
|             |              |              | (phased-out)            |
+-------------+--------------+--------------+-------------------------+

### 3.3.2 SVX Input Power Supply

Connector J004 (in M030) supplies power meant for the SVX. This is an
externally regulated power supply. As such, the input power supply can
be set to an exact voltage with a limited current.

+---------+-------------+-------------+-------------+-----------------+
| #       | #### Min.   | #### Max.   | #### Max. C | #               |
| ### Net | Voltage (V) | Voltage (V) | urrent (mA) | ### Description |
+---------+-------------+-------------+-------------+-----------------+
| AVDD    | 5           | 6           | 800         | raw AVDD supply |
+---------+-------------+-------------+-------------+-----------------+
| AVDD2   | 2.5         | 4.5         | 600         | raw AVDD2       |
|         |             |             |             | supply          |
+---------+-------------+-------------+-------------+-----------------+
| DVDD    | 5           | 6           | 400         | input DVDD      |
|         |             |             |             | supply          |
+---------+-------------+-------------+-------------+-----------------+

### 3.3.3 SVX Output Power Supply

The board passes the SVX Input power supply (J004) to the SVX Output
power supply that goes to the HDI interface connectors (J002, J008).
Adjusting the input power supply can compensate for any voltage drop due
to current measurement. Hence, minimum and maximum voltages are not
determined by this board, but by the operator.

+--------------+--------------------+---------------------------------+
| #### Net     | ####               | #### Description                |
|              |  Max. Current (mA) |                                 |
+--------------+--------------------+---------------------------------+
| AVDD_A       | 400                | AVDD supply for "A" HDI         |
+--------------+--------------------+---------------------------------+
| AVDD_B       | 400                | AVDD supply for "B" HDI         |
+--------------+--------------------+---------------------------------+
| AVDD2_A      | 300                | AVDD2 supply for "A" HDI        |
+--------------+--------------------+---------------------------------+
| AVDD2_B      | 300                | AVDD2 supply for "B" HDI        |
+--------------+--------------------+---------------------------------+
| DVDD_A       | 200                | DVDD supply for "A" HDI         |
+--------------+--------------------+---------------------------------+
| DVDD_B       | 200                | DVDD supply for "B" HDI         |
+--------------+--------------------+---------------------------------+

## 3.4 

## Board Functions

The board performs exactly four main functions: digital signal buffering
and termination, temperature monitoring, power control, and low-voltage
current monitoring. High-voltage current monitoring will not be
incorporated because it is phased-out.

### 3.4.1 Digital Signal Buffering and Termination

Digital signal buffering and termination occur in schematic modules M002
and M005. Fifteen digital signals per HDI Channel (30 total) are
buffered. The eight data signals (D0-D7) are bi-directional. The seven
remaining digital signals are unidirectional. Two of these signals are
CLOCK and /CLOCK. These two signals can be successfully buffered using
TTL. The digital signals must also be terminated. On the HDI-side of the
buffer, the digital lines must be single-end terminated. Signals VCAL
and DIR are not buffered.

Two 74ABT543A devices buffer sixteen digital signals per HDI Channel (32
signals and four '543 devices total). The '543 device properly drives
the signals according to a telephone interview with M. Utes (06/05/98).
The eight data signals (D0-D7) are bi-directional. The eight remaining
digital signals are unidirectional. Two of these signals (DVALID and
PRIORITY_OUT) travel from the SVX chip to the Sequencer, the remaining
six signals travel from the Sequencer to the SVX chip.

Two of the digital signals are CLOCK and /CLOCK. These two signals are
TTL and require 1-2ns-max rise and fall times. The clock signals range
in frequency from 7.59 to 53.1 MHz. The CLOCK and /CLOCK signals may
differ in phase by 180° with an unknown amount of error. The allowable
jitter on the clock signal is also unknown. Despite theses unknown
tolerances, 74ABT buffers have been proven to work in lab
experimentation according to email from M. Matulik dated 06/16/98.

The DIR signal (one of the sixteen) controls the direction of the data
signals. When DIR is Low, data flows from SVX Sequencer Cable Connector
to HDI interface connector (Sequencer to SVX chip). When DIR is High,
data flows in the opposite direction (SVX chip to Sequencer).

Termination on both the Sequencer-side and the HDI-side of the
transceiver is not necessary for all signals; however, users of the
board may want to experiment with termination, so place-holding
resistors will be inserted into the design. Surface mount resistors of
package type 1206 will be used as per the Parts List.

The FNAL D0 Engineering Note #3823.110-EN-480 states that a TI
74ABT162500 drives the digital signals on an 82Ω line. This note is
deemed outdated: the 74ABT162500 device will not be used; however, the
82Ω impedance will be considered when determining the appropriate
termination network.

### 3.4.2 Temperature Monitoring

Temperature monitoring happens in schematic modules M006 and M008. A
platinum RTD is embedded in an environment whose temperature is to be
measured. The two terminals of the RTD come in from each the two HDI
interface connectors (J008 and J002). A circuit must be designed to
properly apply a current across the RTDs so that the corresponding
voltages will represent the temperature.

The temperature monitor is a Platinum RTD with the following specs:
1000Ω at 0°C and ∆3.85Ω/°C. The current supply to the RTD must not
exceed 1mA. The medium being measured is normally around

‑10°C and may reach --20°C and 30°C extreme values.

The proper circuit for this module will be designed by the EDL. The
voltage will be scaled so that there is roughly 100mV change per degree
Celsius (with 1V output @ 0°C). The resulting voltages are output
through the Monitor Cable Connector (J007).

### 3.4.3 Power Control

Power control happens in schematic module M015. One enable signal for
each HDI channel (two signals total) comes in on the SVX Sequencer Cable
Connector (J003). When the enable signal is asserted, four power
supplies turn on in a specific order. Likewise, when the enable signal
is de-asserted, the supplies turn off in the reverse order. The time
delay between enabling each individual power supply is not critical, but
is in the millisecond range.

When the HDI Enable signal transition from Low to High, the following
power supplies are enabled (in this order) AVDD, AVDD2, DVDD, BUFFER.
AVDD, AVDD2, and DVDD are power supplies for the SVX chips and are sent
out the HDI interface connector (J008 ch. A, J002 ch. B). BUFFER
supplies power to the on-board digital signal termination network (M002,
M005). A High-to-Low transition on the HDI Enable signal will disable
the power supplies in reverse order. The time delay between enabling
each individual power supply is not critical, but is in the millisecond
range. Schematic notes indicate that M. Utes has looked into realizing
this circuit with an Altera EPLD. A new circuit for the prototype board
will be designed by the EDL.

### 3.4.4 Low-voltage Current Monitoring

Low-voltage current monitoring happens in schematic modules M016--M019
and M026--M029. The currents on the nets coming in from the SVX Power
Supply Connector (J004) are monitored. That is, a corresponding voltage
is output through the Monitor Cable Connector (J007).

This circuit has one input, three power inputs, and two outputs. The
input enables a power FET (PVN012). The power FET allows current to flow
from the VIN power input through the resistor network of the current
monitor to the fused output VOUT. The current-monitoring output, I_MON,
will vary its voltage to reflect the amount of current passing from VIN
to VOUT. I_MON will be scaled so that its voltage will vary 15mV for
every milliamp of current being drawn. This scaling factor comes from an
email from M. Matulik dated 06/11/98.

The schematics have a circuit to perform current monitoring, but this
circuit may be redesigned by the EDL. Since this circuit will be
designed, all unknown part types and values (formerly TBDs) will be at
the discretion of the EDL.

### 3.4.5 High-voltage Current Monitoring (phased-out)

The currents on the nets coming in from the Detector Bias Voltage
Connector (J009 and J006) are not monitored per Ron Lipton. Monitoring
will not be required on the final design.