D0 Muon Scintillator Electronics

**SRC-To-Remote Host Protocol**

Kwame Bowie

Xinyi Chen

Carmen Rotolo

Marcus Larwill

Tom Fitzpatrick

May 5, 1999

Revised: June 28, 2000

**[INTRODUCTION:]{.underline}**

During normal operation, the front-end crates need to be monitored,
maintained, and updated. In order to accomplish this task, the crates
must be remotely accessible to subsystem engineers and control boards
not located within the crate. Parameters must be monitored and changed,
memories must be updated, and devices must be reset. All of these
functions as well as various others will need to be performed by remote
link. However, it was decided that a high-speed network connection such
as Ethernet should not be present in the front-end crates. Two systems
provide the necessary support for the remote links: the 1553 military
standard transceiver system, and the SCC serial port system.

The 1553 military standard transceiver system is composed of a 1553
remote terminal (RT) and a 1553 controller. The remote terminal (RT) is
the portion of the 1553 system that resides on the SRC. The 1553
controller board is located in a different crate and communicates with
the external host computer via Ethernet. The 1553 controller board then
forwards this information to the SRC via coaxial cabling.

The SCC system consists of two boards with SCC chips and their cable
drivers. The Muon Scintillator SCC system is used to establish
communications between the SRC and the MRC boards. Information is
transferred to the MRC via Ethernet and the MRC transfers this
information to the SRC via strip cabling.

In order to communicate with the SRC, the 1553 transceiver and SCC
serial port systems, store data in a four-port RAM on the SRC dedicated
to remote communications. The four port RAM acts as a mailbox and
accepts all types of data and commands from both the SCC serial port and
the 1553 transceiver system, and arranges the data in a known format.
This report describes the data format of the four-port RAM, the expected
groupings of related commands, and the supported functions of the remote
link. Although functionality is provided for some test procedures, it is
decided that testing will be done through a different interface. The
block diagram below shows the system level functionality.

**Fig. 1 Block Diagram of SRC to Remote Host Communication**

**[COMMUNICATION PROCEDURE:]{.underline}**

The SRC-to-remote host communication system is a half-duplex system.
This means that the data can be sent both ways, but not simultaneously.
In order to maintain adequate functionality, there must be two types of
transactions: a WRITE transaction, and a READ transaction. The WRITE
transaction denotes the transaction between the SRC and the remote host
in which the remote host is sending data to the SRC. The READ
transaction is the transaction between the SRC and the remote host in
which data is sent from the SRC to the remote host.

**1553 TRANSACTION PROCEDURE:**

Although data may be sent in both directions, only the 1553 controller
may request a transaction. The 1553 controller sends a command word and
depending on the value of the T/R bit, it sends data or prepares to
accept data. In order for any transaction to occur, a valid RT Address
must be received by the SRC. The communications PLD accepts two (2) RT
addresses for each DIP-switch setting. The RT Address is a 5-bit field,
but the DIP-switch is only mapped to the upper 4 bits. This mapping was
necessary to enable the SLP board to be controlled using the 1553 system
on the SRC. *As a result, all even RT Addresses are mapped to SRC and
SFE commands, and all odd RT-Addresses are mapped to SLP commands*. To
ensure that the data transaction occurred without failure, a status word
is sent back to the 1553 controller. The position of the status word
varies depending on the type of transmission: it comes before the data
for a READ and after the data for a WRITE. The bit mapping of the
command and status words are shown below.

  ------------------ --------- ----- ------------ ---- ---------- ------- ----- ---- ----- ----
  Command Word       RT        T/R   Subaddress                   Word                     
                     Address                                      Count                    

  Status Word        RT        ME    INS          SR   RESERVED   BCR     BSY   SF   DBC   TF
                     Address                                                               
  ------------------ --------- ----- ------------ ---- ---------- ------- ----- ---- ----- ----

**WRITE transaction**:

The write transaction is accessed by lowering the transmit bit in the
1553 command word. The remote terminal on the SRC sees the T/R bit low.
After issuing the WRITE command, the 1553 controller, immediately sends
the data. After the last data word is sent, the communications PLD on
the SRC issues a level 7 VME interrupt. The crate processor is then
required to send back an interrupt acknowledge signal. The 1553 spec
indicates that the Status Word must be received at the 1553 controller
within the response time of 10 to 16 microseconds. The communications
PLD on the SRC generates a valid status word as long as the IACK arrives
on time (within 7.5 μs of the interrupt) from the crate processor. If
the IACK is late, the subsystem flag bit within the status word is set.
The status word signals the end of a transaction

Response time (10 -- 16 us)

...

**1553 Controller**

**1553 BUS**

**RT on SRC**

**Fig. 2: 1553 WRITE Transaction Diagram**

**READ transaction:**

The read transaction is accessed by asserting the receive bit in the
1553 command word. The remote terminal on the SRC sees the T/R bit high.
After receiving the READ command word, the RT issues a VME interrupt. To
produce a valid status word, the crate processor should deliver an IACK
signal within 7.5 μs of the interrupt. Otherwise the subsystem flag bit
in the status word is set to signify a processor timeout. In the READ
transaction, the last data word signals the end of the transaction.

Response time (10 -- 16 us)

**1553 Controller**

**1553 BUS**

**RT on SRC**

...

**Fig. 3: 1553 READ Transaction Diagram**

**1553 Multi-block Commands**

In order to load (or read) RAM devices on the SRC, large blocks of data
must be loaded into consecutive locations. These multi-block commands
require the crate processor to remember the last address loaded and
restart just after that position on the next transaction. The 1553
command word specifies the starting address by selecting a subaddress
code corresponding to the RAM device to be loaded (or read). Once the
memory device is finished being loaded (or read), the correct Reset RAM
Pointer mode command is issued. There are two (2) Reset RAM pointer mode
commands, one for writes and one for reads. This enables reads and
writes to be interspersed so that one RAM device may be loaded while
another is read.

**SCC SERIAL PORT TRANSACTION PROCEDURE:**

The transaction procedure when using the SCC serial port is
substantially different from the 1553 procedure. The 1553 system is
essentially a synchronous system where a data buffer is loaded and then
data is streamed out at a constant word rate only after a transmit (or
receive) command is sent. Also, in most cases the command word comes at
regular intervals. Conversely, the SCC serial port is an asynchronous
connection where data is sent out of the SCC device as soon as data
enters the data register. There is not a set interval length between
transmissions or even between the individual data words in a
transmission. The system level procedure is software controlled from the
MRC and is yet to be fully developed. The SCC serial port system on the
SRC is a slave device just the same as the 1553 RT on the SRC. As a
result, commands and data are simply loaded into the appropriate
positions when the MRC requests the transactions.

The first major difference between the two systems is that the SCC
serial port does not require a confirmation word in order to show that
the connection is made; a valid connection is simply assumed. The 1553
system requires a confirmation of connection in the form of a status
word for every transaction. For the SCC serial port, there is not
connection confirmation in hardware since all transactions are
single-byte on the hardware level. Confirmation of a single-byte
transfer would add an unreasonable data overhead for larger
transmissions. However, connection confirmation may be embedded within
the data in the form of parity bits. Embedding parity bits or some other
form of confirmation in the data would be a software issue and beyond
the scope of this document.

The other major difference between the SCC serial port system and the
1553 system is the word spacing. The 1553 controller has a data buffer
memory so that data words may be packed together with no delays between
words. Due to the buffering, there is a maximum transaction length of 32
words. This is not the case for the SCC serial port. The SCC serial port
is asynchronous and data is sent whenever it is provided by the MRC. As
a result, word spacing may be variable and transaction time has no
predefined limit based on hardware.

The final major difference between the 1553 system and the SCC system is
the fact that the SCC system has only three preset functions: WRITE,
READ, and SYSRESET. Whereas the 1553 system had each subaddress mapped
to a different function or register, the SCC system has no preset
function or register mapping. The SCC is to be used as a console port to
the crate processor. Thus all information about functions or registers
to be accessed is contained within the data.

**WRITE Transaction:**

The WRITE transaction for SCC system is initiated when the MRC sends the
command word: (DXXX) hex, where the X's represent the word count. It is
important to remember that the command word just like all SCC data must
be entered into the MRC 8 bits-at-a-time. The word count is 12 bits,
which means that the entire 4-Port RAM may be filled starting at
location 64. The SCC serial port controller PLD on the SRC keeps track
of the number of words moved into the 4-Port RAM. As soon as the
transaction word count is equivalent to the word count in the command
word, the connection is closed and the VME interrupt is issued. It
should be noted that the command word appears in the 4-Port RAM as a
16-bit word, but the data in the subsequent addresses is only saved as
8-bit words. Thus only the lower byte of each location contains valid
data.

**READ Transaction**:

The READ transaction proceeds slightly differently than the WRITE
transaction. First, the READ transaction does not use more than one
location of the 4-Port RAM. The first step of the READ transaction is
the MRC requesting data from the SRC. The command word (EXXX) hex is
placed in the first location of the serial port section of the 4-Port
RAM (location 64) and then an interrupt is issued. The crate processor
then writes one byte at a time to the SCC data register itself,
completely bypassing the 4-Port RAM. The MRC must remember how many
words it requested so that it knows which data is associated with which
request. The SRC will continue sending data until the word count is
reached. Once the word count is reached, the crate processor will issue
the Terminate Transaction command. Care must be taken that the data is
not overwritten within the MRC.

**[4-PORT RAM DATA FORMAT]{.underline}:**

The 4-Port RAM data format was selected to enable access through all
four ports while maintaining a known data structure. A major concern was
enabling the 1553 system to fit seamlessly into the EPICS slow control
system. To accomplish this goal, the 1553 controller must be able to
access the registers on the SRC that it needs in a timely manner. As a
result, one segment of the 4-Port RAM is dedicated to holding data
related to the 1553 system. To simplify the mapping of the 4-Port RAM,
the two sections: 1553 memory and SCC memory start on page boundaries.
The 1553 memory starts at location zero (0) and the SCC memory starts at
location 64. More specific information on the ordering of words, bytes,
and bits are shown in the sections below.

.

**1553 Data Format**

The 1553 section is located in the first few (33) locations of the
4-Port RAM. This section provides enough buffering memory for one
1553-transaction block. The specifics of the word and bit locations are
shown in Fig. 4 below.

**1553 Transactions:**

**WRITE Transaction**:

+-------+-----------+------+---+----------------+--------------------+
| Loc   | Command   | RT   | T | Subaddress     | Word Count         |
| ation | Word      | Add  | / |                |                    |
| 1     |           | ress | R |                |                    |
+-------+-----------+------+---+----------------+--------------------+
| Loc   | 1^st^     | 16   |   |                |                    |
| ation | Data Word | -Bit |   |                |                    |
| 2     |           | Data |   |                |                    |
+-------+-----------+------+---+----------------+--------------------+
| > ... | > ...     | 16   |   |                |                    |
|       |           | -Bit |   |                |                    |
|       |           | Data |   |                |                    |
+-------+-----------+------+---+----------------+--------------------+
| Loc   | Last Data | 16   |   |                |                    |
| ation | Word      | -Bit |   |                |                    |
| 33    | (MAX. 32) | Data |   |                |                    |
+-------+-----------+------+---+----------------+--------------------+

READ Transaction:

  ---------- ------------ --------- ----- ----------------- --------------------
  Location 1 Command Word RT        T/R   Subaddress        Word Count
                          Address                           

  Location 2 1^st^ Data   16-Bit                            
             Word         Data                              

  ...        ...          16-Bit                            
                          Data                              

  Location   Last Data    16-Bit                            
  33         Word (MAX    Data                              
             32)                                            
  ---------- ------------ --------- ----- ----------------- --------------------

###### Fig. 4 1553 Transaction Block Format

###### SCC Serial Port Data Format

The SCC serial port RAM section has enough locations to enable
reasonably large chunks of data to be processed (roughly 4Kbytes at a
time). There is command word associated with all data transactions for
the SCC system. The SRC parses the command word for function code and
word count and then places it in the 4-Port RAM. The three function
codes are as follows: READ, WRITE, and SYSRESET. The function codes are
mapped to the most significant nibble of the first byte. The word count
is composed of the remaining nibble in the first command byte along with
the next command byte, totaling 12 bits. The SCC chips only have 8-bit
data ports so all words are transmitted 8 bits at a time. For a WRITE
transaction, up to 4031 8-bit data words may be sent following the
16-bit command word. For a READ transaction, the front-end crate
processor sends one byte at a time directly to the SCC data register,
bypassing the 4-Port RAM. The specifics of bit and word locations are
shown in Fig. 5 below.

**SCC Serial Port Transactions:**

WRITE Transaction:

  ---------- --------- -------- -------------------------------------------
  Location   Command   Fcn Code Word Count
  64         Word      = D      
                       (hex)    

  Location   1^st^     8-Bit    
  65         Data Word Data     

  ...        ...       8-Bit    
                       Data     

  Location   Last Data 8-Bit    
  4096       Word      Data     
             (Max.              
             512)               
  ---------- --------- -------- -------------------------------------------

READ Transaction:

+------------------+-------+-------------------------------------------+
| Command Word     | FCN   | Word Count                                |
|                  | Code  |                                           |
|                  |       |                                           |
|                  | = E   |                                           |
|                  | (hex) |                                           |
+------------------+-------+-------------------------------------------+

# 

# Fig. 5 SCC Serial Port Transaction Format

## [INTERRUPTS]{.underline}:

One of the most important aspects of the SRC-to-Remote host
communication system is the need to update parameters and read status
via the 1553 system. The 1553 system has fairly strict timing
requirements, so any 1553 transaction must be handled immediately. It
was decided that the best way to handle both the 1553 and SCC systems
using the same memory was to use two different interrupts. By using two
interrupts, the crate processor's interrupt handler can handle an
interrupt while accepting other interrupts. By setting the interrupt
level for 1553 transactions to level 7, 1553 transactions become the
first priority of the crate processor. Interrupt level 6 was selected
for the SCC system, so SCC transactions are handled only after the 1553
transaction is finished.

**[APPENDIX A:]{.underline}**

**SAMPLE TRANSACTIONS:**

##### 1553 WRITE

Subaddress = 0x10, RT Address = 2, Word count =0x20

**Send Command and Data (1553 Controller)**

1)  Load Controller with header word (2) 0x0002  ControllerBase +
    Location

2)  Load Controller w/ command word 0x1020  ControllerBase + Location +
    2

3)  Load Controller w/ data 0xXYZ  ControllerBase + Location + 4

4)  Repeat 2 until you reach word count 0xXYZ  ControllerBase +
    Location + 4 + 2\*I

5)  Issue execute command instruction Location / 2  ControllerBase +
    0xfffc

6)  Check status: valid transaction =0z1000 Controller Base  0x1000?

**Receive and Check Data: (SRC)**

1)  Check command word on SRC: SRC_BASE + 0x780000  0x1020?

2)  Check data words SRC_BASE + 0x780000 + 4  0xXYZ

3)  Continue 3 until reach word count SRC_BASE + 0x7800000 + 4\*I 
    0xXYZ

##### 1553 READ

Subaddress = 0xC, RT Address = 2, Word count = 6

**Send Command (1553 Controller)**

1)  Load Controller w/ command word: 0x1586  ControllerBase + Location

2)  Issue execute command instruction: Location / 2  ControllerBase +
    0xfffc

**Write Data to 4-Port (SRC)**

1)  Read Command word (get function and word count) SRC_BASE + 0x780000
     0x1586

2)  Read Data from location pointed by subaddress: SRC_BASE + 0x880000 +
    4\*I  0xXYZ

3)  Write Data Word to 4-Port(starting at location2 ): 0xXYZSRC_BASE +
    0x780004 + 4\*I

4)  Repeat 2 and 3 until word count is reached

###### Read Status and Data from 1553 Controller

1)  Read Command word ControllerBase + Location + 2  0x1586

2)  Read Data word ControllerBase + Location + 4  0xXYZ

3)  Read data words until reach word count ControllerBase + Location +
    4 + 2\*I  0xXYZ

4)  Read Status Word ControllerBase + Location + 4 + 2\*words  0x1000

**[SCC WRITE]{.underline}**

Word count = 0x456

**Send Command and Data (MRC)**

1)  Reset SCC chip on MRC 0  MRC_BASE + 0xC00C

2)  Write command word 1^st^ byte to SCC on MRC 0xD4  MRC_BASE + 0xC00C

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3)  Write command word 2^nd^ byte to SCC on MRC 0x56  MRC_BASE + 0xC00C

4)  Write data byte to SCC on MRC 0xXYZ  MRC_BASE + 0xC00C

5)  Continue 4 until word count is reached 0xXYZ  MRC_BASE + 0xC00C

**Read/Check Data (SRC)**

1)  Read back data from 4-Port RAM SRC_BASE + 0x780100  0xXYZ?

##### SCC READ

Word count = 0x234

**Send Command Word (MRC)**

1)  Initialize MRC for READ (read 2 nulls) MRC_BASE + 0xC00C  0

MRC_BASE + 0xC00C  0

2)  Write command word 1^st^ byte to SCC on MRC 0xE2  MRC_BASE + 0xC00C

3)  Write command word 2nd byte to SCC on MRC 0x34  MRC_BASE + 0xC00C

**Send Back Data (SRC)**

1)  Read 4-Port RAM for word count SRC_BASE + 0x780100  0x234?

2)  Write Data directly to SCC Data Register 0x00YZ  SRC_BASE +
    0x600008

**Read Received Data (MRC)**

1)  Read received data from upper byte MRC_BASE + 0xC00C  0xYZ00

\*\*After word count is reached

**Terminate READ transaction (SRC)**

1)  Write to terminate transaction register 0  SRC_BASE + 0x600014

**[APPENDIX B:]{.underline}**

### 1553 Subaddress/Mode Code Map

SubAddress Register/Function R/W #words

+----+------------------+------------------+--------+----------------+
| 0  | MODE Command     |                  | W      | \-             |
+----+------------------+------------------+--------+----------------+
| 1  | SRC VME CSR1     |                  | R      | 1 word         |
+----+------------------+------------------+--------+----------------+
|    | SRC Readout      |                  |        | 1 word         |
|    | Controller CSR1  |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFE0 VME CSR1    |                  |        | 16 words       |
+----+------------------+------------------+--------+----------------+
|    | .                |                  |        |                |
|    |                  |                  |        |                |
|    | .                |                  |        |                |
|    |                  |                  |        |                |
|    | .                |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    |                  |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    |                  |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFEF VME CSR1    |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 2  | SFE Write-only:  |                  | W      | 1 word         |
|    | Reset SFE boards |                  |        |                |
|    | CSR              |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    | Clear latched    |                  |        | 1 word         |
|    | errors CSR       |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    | Reset output     |                  |        | 1 word         |
|    | FIFO read        |                  |        |                |
|    | pointer CSR      |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    | Reset output     |                  |        | 1 word         |
|    | FIFO CSR         |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    | Reset TMCs CSR   |                  |        | 1 word         |
+----+------------------+------------------+--------+----------------+
|    | Reset ADC FIFO   |                  |        | 1 word         |
|    | CSR              |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 3  | Group A Chan     |                  | R/W    | 32 words       |
|    | En./ Analog chan |                  |        |                |
|    | sel.             |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 4  | Croup B Chan     |                  | R/W    | 32 words       |
|    | En./ Analog      |                  |        |                |
|    | chan. sel.       |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 5  | Group C Chan     |                  | R/W    | 32 words       |
|    | En./ Analog      |                  |        |                |
|    | chan. sel.       |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 6  | SFE Master       |                  | R/W    | 16 words       |
|    | Controller CSR0  |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 7  | Readout          |                  | R/W    | 4 words        |
|    | Controller       |                  |        |                |
|    | CSR0-3           |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 8  | Trigger Manager  |                  | R/W    | 7 words        |
|    | CSR0-6           |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 9  | HOTLINK CSRs: L2 |                  | R/W    | 2 words        |
|    | & L3             |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    | LAT_PRE          |                  | R/W    | 16 words       |
+----+------------------+------------------+--------+----------------+
|    | ADC_DEL \*\*     |                  |        | 16 words       |
+----+------------------+------------------+--------+----------------+
|    | L1_DEL           |                  | R/W    | 16 words       |
+----+------------------+------------------+--------+----------------+
|    | L1STRG_LAT       |                  |        | 16 words       |
+----+------------------+------------------+--------+----------------+
|    | Crate Analog     |                  | R      | 7 words        |
|    | Data: A_Crate0   |                  |        |                |
|    | (Voltage, temp,  |                  |        |                |
|    | etc.)            |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    | .                |                  |        |                |
|    |                  |                  |        |                |
|    | .                |                  |        |                |
|    |                  |                  |        |                |
|    | .                |                  |        |                |
+----+------------------+------------------+--------+----------------+
|    | Crate Analog     |                  |        |                |
|    | Data: A_Crate6   |                  |        |                |
+----+------------------+------------------+--------+----------------+
| D  | SRC Board Main   |                  | R/W    | 1 word         |
|    | CSR0             |                  |        |                |
+----+------------------+------------------+--------+----------------+
| E  | All TMCs CSR0    | All TMCs CSR1    | R/W    | 32 words       |
+----+------------------+------------------+--------+----------------+
|    | All TMCs CSR2    | All TMCs CSR3    |        |                |
+----+------------------+------------------+--------+----------------+
| F  | Interrupt        |                  | R/W    | 1 word         |
|    | Vectors          |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 10 | SFE Thresholds 0 | SFE Thresholds 1 | R/W    | 32 words       |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds 2 | SFE Thresholds 3 |        |                |
+----+------------------+------------------+--------+----------------+
| 11 | SFE Thresholds 4 | SFE Thresholds 5 | R/W    | 32 words       |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds 6 | SFE Thresholds 7 |        |                |
+----+------------------+------------------+--------+----------------+
| 12 | SFE Thresholds 8 | SFE Thresholds 9 | R/W    | 32 words       |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds   | SFE Thresholds   |        |                |
|    | 10               | 11               |        |                |
+----+------------------+------------------+--------+----------------+
| 13 | SFE Thresholds   | SFE Thresholds   | R/W    | 32 words       |
|    | 12               | 13               |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds   | SFE Thresholds   |        |                |
|    | 14               | 15               |        |                |
+----+------------------+------------------+--------+----------------+
| 14 | SFE Thresholds   | SFE Thresholds   | R/W    | 32 words       |
|    | 16               | 17               |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds   | SFE Thresholds   |        |                |
|    | 18               | 19               |        |                |
+----+------------------+------------------+--------+----------------+
| 15 | SFE Thresholds   | SFE Thresholds   | R/W    | 32 words       |
|    | 20               | 21               |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds   | SFE Thresholds   |        |                |
|    | 22               | 23               |        |                |
+----+------------------+------------------+--------+----------------+
| 16 | SFE Thresholds   | SFE Thresholds   | R/W    | 32 words       |
|    | 24               | 25               |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds   | SFE Thresholds   |        |                |
|    | 26               | 27               |        |                |
+----+------------------+------------------+--------+----------------+
| 17 | SFE Thresholds   | SFE Thresholds   | R/W    | 32 words       |
|    | 28               | 29               |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds   | SFE Thresholds   |        |                |
|    | 30               | 31               |        |                |
+----+------------------+------------------+--------+----------------+
| 18 | SFE Thresholds   | SFE Thresholds   | R/W    | 32 words       |
|    | 32               | 33               |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds   | SFE Thresholds   |        |                |
|    | 34               | 35               |        |                |
+----+------------------+------------------+--------+----------------+
| 19 | SFE Thresholds   | SFE Thresholds   | R/W    | 32 words       |
|    | 36               | 37               |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds   | SFE Thresholds   |        |                |
|    | 38               | 39               |        |                |
+----+------------------+------------------+--------+----------------+
| 1A | SFE Thresholds   | SFE Thresholds   | R/W    | 32 words       |
|    | 40               | 41               |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds   | SFE Thresholds   |        |                |
|    | 42               | 43               |        |                |
+----+------------------+------------------+--------+----------------+
| 1B | SFE Thresholds   | SFE Thresholds   | R/W    | 32 words       |
|    | 44               | 45               |        |                |
+----+------------------+------------------+--------+----------------+
|    | SFE Thresholds   | SFE Thresholds   |        |                |
|    | 46               | 47               |        |                |
+----+------------------+------------------+--------+----------------+
| 1C | Port D Four Port |                  | R/W    | Multi-block    |
|    | RAM              |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 1D | DSP Flash RAM    |                  | R/W    | Multi-block    |
+----+------------------+------------------+--------+----------------+
| 1E | DSP Dual Port    |                  | R/W    | Multi-block    |
|    | RAM              |                  |        |                |
+----+------------------+------------------+--------+----------------+
| 1F | MODE command     |                  | W      | \-             |
+----+------------------+------------------+--------+----------------+

MODE COMMAND CODES:

MC R/W

  -------- ----------------------------------- ------------ --------------
  09       Reset RAM WRITE pointer             (T/R = 0)    None

  0A       Reset SRC                           (T/R = 0)    None

  0B       DSP Service Request                 (T/R = 0)    None

  0C       L2 & L3 FIFO Reset                  (T/R = 0)    None

  0D       SRC CLR_ERRS                        (T/R = 0)    None

  0E       SYSRESET                            (T/R = 0)    None

  0F       Reset RAM READ pointer              (T/R = 0)    None
  -------- ----------------------------------- ------------ --------------

**[APPENDIX C:]{.underline}**

[**TYPICAL** **PROCEDURES:**]{.underline}

The following are groups of essential procedures to be performed by the
SRC. The groups are divided into large procedures, which can later be
subdivided and/or shortened. Several of these groups contain no
specified procedures. This is because it is assumed that other I/O
methods would be better suited for performing that group's associated
procedures. The address map is provided in the following section.

I)  **Initialize after power fail**: Initialization after power failure
    includes resetting all devices, setting all parameters, and setting
    modes on all devices. Basically everything except rewriting flash
    RAMs and FLEX devices.

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1)  Reset output FIFO Address write (no data necessary)

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1)  Reset output FIFO pointer Address write (no data necessary)

2)  Reset SFE boards Address write (no data necessary)

3)  Reset TMCs Address write (no data necessary)

4)  Reset ADC FIFO Address write (no data necessary)

5)  Reset SRC board Address write (no data necessary)

6)  Reset DSP Address write (no data necessary)

7)  Reset L2 & L3 FIFOs Address write (no data necessary)

8)  Clear latched errors Address write (no data necessary)

9)  SFE: Set TMC(0-B) CSR (0-2) 36 registers of 8-bit data **OR**

> 3 registers of 8-bits sets CSRs
>
> for all 12 TMCs with same values

10) SFE: Set Group A-C thresholds 48 registers of 8-bit data

11) SFE: Load threshold and TP-DAC? Address write (no data necessary)

12) SFE: Set Group A-C trigger gate registers 3 registers of 13-bit data

13) SFE: Set Group A-C analog gate registers 3 registers of 13-bit data

14) SFE: Enable Group A-C channels 3 registers of 16-bit data

15) SFE: Set Master Controller CSR0 1 register of 16-bit data

16) SFE: Read Master Controller CSR1 1 register of 16-bit data

17) SFE: Set L1 timing data preset 1 register of 8-bit data

18) SFE: Set ADC data trigger latency 1 register of 6-bit data

19) SFE: Select analog group select (A, B, or C) 3 registers of 4-bit
    data

20) SRC: Set VME controller CSR0 1 register of 16-bit data

21) SRC: Read VME Controller CSR1 1 register of 16-bit data

22) SRC: Set readout controller CSRs 4 registers of 16-bit data

23) SRC: Set trigger manager CSRs 7 registers of 8-bit data

24) SRC: Set L2 and L3 HOTLINK CSRs 2 registers of 8-bit data

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I)  **Parameter setting:** Parameter setting, simply sets all parameters
    not used for testing.

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1)  Set CSRs 0-2 for TMCs 0-11 36 registers of 8-bit data **OR**

> 3 registers of 8-bits sets CSRs
>
> for all 12 TMCs with same values

1)  Set discriminator thresholds: Groups A-C 48 registers of 8-bit data

2)  Load threshold and TP_DAC? Address write (no data necessary)

3)  SFE: Load Group A-C trigger gate registers 3 registers of 13-bit
    data

4)  SFE: Load Group A-C analog gate registers 3 registers of 13-bit data

5)  SFE: Enable Group A-C channels 3 registers of 16-bit data

6)  SFE: Load Master Controller CSR0 1 register of 16-bit data

7)  SFE: Load timing data latency preset 1 register of 8-bit data

8)  SFE: Load ADC data L1 trigger latency 1 register of 6-bit data

9)  SFE: Select analog Group A, B, or C channels 3 registers of 4-bit
    data

10) SRC: Set VME CSR0 1 register of 16-bit data

11) SRC: Set readout controller CSRs 4 registers of 16-bit data

12) SRC: Set trigger manager CSRs 7 registers of 8-bit data

13) SRC: Set L2 & L3 HOTLINK CSRs 2 registers of 8 bit data

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II) **Online error and status monitoring**: Checks a few CSRs
    periodically to ensure that no errors have occurred.

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1)  Check SFE CSR1: Control status of Test Output FIFO and Error Status
    of Trigger and Analog gate timing

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1)  Check SRC VME Controller CSR1: Error status information for VME
    communications

2)  Check SRC Readout controller's second CSR to see SFE timeout
    information.

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III) **Testing**: Perform all procedures required by the desired test.
     Advisable to implement using a method other than 1553 or serial
     port for the sake of speed and real-time data acquisition.

IV) **Reconfiguration:** Rewrite all PLDs, FPGAs and flash RAMs. Also
    advisable to use other I/O modality do to the very large memory
    arrays.

###### [APPENDIX D:]{.underline}

###### 

###### Address Map of All Available Functions:

This is a list of all functions that may be performed under VME control.
These functions are all available to the Remote Host. Many may not be
ideally suited for transmission via 1553 or SCC serial port, but they
may nonetheless be performed.

**[SFEs]{.underline}:**

1\) Configure FLEX 10Ks : Wà000000

2\) Configure FLEX 10K flash RAM R/W à 100000 -- 1FFFFC

3\) Read FLEX 10K INIT DONE register Rà 200000

4\) Read FLEX 10K STATUS register Rà 300000

5\) Clear latched errors Wà 400000

> 6\) Start TMCs W/R pointers Wà 500000
>
> 7\) Stop TMCs W/R pointers Wà 600000
>
> 8-19) Delay Buffer x(0:B) DP RAM R/Wà 808x00 -- 808xFC

20) Master controller DP RAM R/Wà 808C00 -- 808CFC

    32. TMC x(0:B) CSR0 R/Wà 809x00

> 33-44) TMC x(0:B) CSR1 R/Wà 809x04

56. TMC x(0:B) CSR2 R/Wà 809x08

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68. TMC x(0:B) CSR3 R/Wà 809x0C

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72. All TMCs CSRs Wà 809C00-8090C

> 73\) Group A threshold settings R/Wà 80A000 -- 80A03C
>
> 74\) Group B threshold settings R/Wà 80A100 -- 80A13C
>
> 75\) Group C threshold settings R/Wà 80A200 -- 80A23C
>
> 76\) Analog Test Pulse amplitude R/Wà 80A300
>
> 77\) Load threshold and TP-DAC settings Wà80A400
>
> 78-80) Group A timing gate registers (Ch. 0-47) R/Wà 80B000, 80B300,
> 80B600
>
> 81-83) Group B timing gate registers (Ch. 0-47) R/Wà 80B100, 80B400,
> 80B700
>
> 84-86) Group C timing gate registers (Ch. 0-47) R/Wà 80B200, 80B500,
> 80B800
>
> 87\) Master controller CSR0 R/Wà 80C000
>
> 88\) Master controller CSR1 Error and Status readout Rà 80C100
>
> 89\) Timing data L1 trigger latency preset R/Wà80C200
>
> 90\) Test Pulse crossing preset R/Wà 80C204
>
> 91\) Test Pulse L1 crossing preset R/Wà 80C208
>
> 92\) ADC data L1 trigger latency R/Wà 80C20C
>
> 93\) Group A analog Ch. 0:15 select R/Wà 80C210
>
> 94\) Group B analog Ch. 16:31 select R/Wà 80C214
>
> 95\) Group C analog Ch. 32-47 select R/Wà 80C218
>
> 96\) Delay buffer page PG0/PG1 Rà 80C21C
>
> 97\) Delay buffer HIT_Or \<0:7\> Rà 80C220
>
> 98\) Delay buffer HIT_OR\<8:11\> plus OUT_EN Rà 80C224
>
> 99\) L1 self test trigger latency R/Wà 80C228
>
> 100\) Read output FIFO Rà 80C300
>
> 101\) Reset output FIFO Wà80C400
>
> 102\) Reset output FIFO pointer Wà80C500
>
> 103\) Reset board Wà 80D000
>
> 104\) Reset TMCs Wà 80D100
>
> 105\) Reset ADC FIFO Wà 80D200
>
> 106\) Arm test pulse Wà 80E000
>
> 107\) Test readout Wà 80E100
>
> **[SRC:]{.underline}**
>
> 108\) FLEX 10K configure Wà 000000
>
> 109\) FLEX 10K flash RAM R/Wà
>
> 110\) Interrupt vector register R/Wà 080000
>
> 111\) SRC VME CSR0 R/Wà100000
>
> 112\) SRC VME CSR1 Rà 180000
>
> 113\) Clear latched errors Wà 200000
>
> 114\) Reset board Wà 280000
>
> 115\) L2 & L3 FIFO reset Wà 300000
>
> 116\) DSP reset Wà 380000
>
> 117\) Test pulse arm Wà400000

####### Readout controller

> 118\) SFE_MASK R/Wà480000

119\) TO_SET, TO_ERR_ADDR,

SFE_TO_ERR, and FULL_ERR R/Wà480004

120\) PG_FULL R/Wà480008

121\) L1_COUNT, PAGE R/Wà48000C

**Trigger Manager**

122\) TP_PRE, LAT_PRE R/Wà 500000

123\) TP_PRE R/Wà 500004

124\) L1TST_PRE R/Wà 500008

125\) TP_DLY_PRE R/Wà 50000C

126\) BEAM_DLY R/Wà 500010

127\) TP_REP_PRE R/Wà 500014

128\) LOC_L1_DLY R/Wà 500018

**DMA Controller**

129\) L2 HOTLINK CSR R/Wà 580000

130\) L3 HOTLINK CSR R/Wà 580004

**Serial port**

131\) Write command to SCC Wà 600004

132\) Write data to SCC Wà 600008

133\) Read command from SCC Rà 600014

134\) Read data from SCC Rà 600018

**VME commands for DSP access**

135\) DSP flash RAM address R/Wà 680000 -- 69FFFF

136\) DSP dual port RAM address R/Wà700000 -- 703FFF

137\) VME access to port D of the four-port RAM R/Wà 780000 -- 780FFF

138\) DSP service request-interrupt Wà800000

139\) ADC data read address Rà 880000-880014

**DSP (own commands)**

140\) Internal RAM R/Wà 000000 -- 001FFF

141\) Dual Port Ram R/Wà 400000 -- 403FFF

142\) ROM (Flash RAM) R/Wà 800000 -- 81FFFF

143\) Four-Port RAM R/Wà C00000 -- C00FFF

I/O Space commands

144\) L2 FIFO read Rà 00

145\) L1 crossing number read Rà 01

146\) Send L3 HOTLINK leading control

byte DSP_D(0:7) Wà 03

147\) Send L3 HOTLINK trailing control

byte DSP_D(8:15) Wà 04

148\) Send L3 HOTLINK data word DSP_D(0:15) Wà 05

149\) L2 turn number read Rà 08

150\) L2 crossing number read Rà 09

151\) DMA word count and L2 data transfer Wà 1A