**August 7, 1999**

**Silicon Subsystem Report**

**July 1999**

**Subsystem Manager's Summary (M. Gilchriese)**

[Cost and Schedule Summary Status]{.underline}

Milestones corresponding to the baseline schedule are marked with a \*.
Additional milestones are included, and will be included, as needed to
monitor progress

1.  Pixel System

Costs are within allocated limits. Seven of 12 prototype sectors from
Energy Science Laboratory, Inc have been delivered but the rate is
slower than desired. The planarity uniformity of some sectors is not
within specification and iterations with ESLI are partly responsible for
the delay. The fabrication of the first prototype disk support ring is
near completion, and final machining should be completed by mid-August
and the ring delivered to LBNL for inspection and measurement.
Preparations for testing a full disk with dummy heat loads and cooling
accelerated rapidly in July. A suitable power supply(1kW), chillers and
instrumentation were either found, ordered or specified for tests at
LBNL and coordinated with Hytec, Inc that will perform TV holographic
testing at their facility. Final drawings for fabrication of two
prototype frame panels and the connecting joint were completed by Hytec,
Inc and tooling preparations for assembly are underway at Allcomp, Inc.
Although we are some months behind the baseline schedule (particularly
for fabrication of the first prototype ring), progress remains steady
and we addressing many of the systems issues that must be solved to
fabricate real disk structures. At the moment, we don\'t foresee a long
term impact on the mechanics schedule from these delays. However, the
cooling interface(nominally a non-US responsibility) remains a major
concern. The validation of evaporative cooling made at the review in May
has led to the tentative adoption of C~3~F~8~ as the nominal working
fluid(for both pixels and SCT), although other fluids are still being
tested. This fluid requires an 8-10 bar pressure to operate and,
although the pressures within the pixel structure are much less than
this(nominally 3-4 bar), we remain very concerned about startup and
fault conditions that may cause an overpressure within the pixel
structure itself. At best overpressure would result in permanent
deformations of the low mass structure, and, at worst, rupture of the
cooling lines or connections. We are in the process of urging the ID
management to perform a failure analysis ASAP and are trying to
determine what expertise we can bring to this as part of a review.
Should this process drag on beyond about November, we will be delayed in
our part of the mechanical design.

The 2^nd^ round prototype sensors are under fabrication with one vendor
and should begin shortly with the second. How these sensors will be
studied in detail remains to be determined since they will be delivered
too late for testing in the usual SPS beams. At a minimum laser testing
will be done, but this type of testing still needs to correlated
carefully with assemblies already tested in the beam. New Mexico has
volunteered to try to take the lead in this. Alternative test beam
locations are under study but with little enthusiasm, pending the
outcome of laser testing.

Considerable progress was made in solving the last problems before
submitting the FE-D IC to Temic for fabrication. The origin of the large
time dispersion seen in existing prototype chips is now understood and
reproduced in simulation, and has been fixed. Other circuit problems are
also now understood and fixed, and FE-D is in the final verification and
simulation stage with submission expected by mid-August and
delivery(with incentive payments made) planned for mid-October. The
collaboration has agreed on a plan to begin work on the Honeywell
version(FE-H) as best it can given the continued absence of Technical
Assistance Agreements with European groups. According to Honeywell, no
new concerns have been raised(yet) by the U.S. government, and TAA
approval should occur sometime between mid-September and mid-November.
We are planning on the later date and have organized the available
design team as best possible under the circumstances. It will be some
months before we have a handle on the real schedule for FE-H submission.

We continue to experience delays with the US vendor(R&D Circuits) of the
flex 1.x hybrid. Production of 1.x is on schedule at CERN after some
initial delay, and tested parts should be delivered by the end of
August. This will be barely in time to assembly flex modules for the
September test beam period(starting around September 20). Additional
vendors are being investigated in the US.

Planning for production module assembly is proceeding slowly. Among the
most difficult issues is the dispensing of adhesive that glues the flex
hybrid to the back of the sensor on a module. This must be done
carefully and to relatively high precision to both allow automated wire
bonding on a good, hard surface and to avoid putting glue in undesirable
spots on the sensor. A number of methods have been tried and rejected,
and now a precision gluing station is being designed at LBNL. The
difficulties we had thinning recent dummy wafers have been understood to
be faults in the wafer fabrication, not the thinning process. New dummy
wafers are under fabrication and we expect to thin the first full FE-B
wafers in August as well. We have re-evaluated the module envelope
dimensions including uncertainties in the dimensions of the thinning,
passive components, flex hybrid, etc. The layout of the barrel region is
very sensitive(to the few hundred micron level) to the module envelope
dimensions and we are studying the trade-off between a conservative
module envelope, which reduces the acceptance for low PT tracks and an
aggressive envelope that assumes success in thinning, finding smaller
components, etc. We hope this process converges by the end of September.
At the same time we expect final simulation results comparing a 300
micron-pixel-length B-layer with a 400 micron one.

2.  Silicon Strip System

Cost are within allocated limits(including recent BCPs). For a change,
the news is, so far, encouraging on the IC electronics. The CAFE-P
continues to perform well. Six CAFE-Ps have been mounted successfully on
a hybrid with old digital read-out chips from the SSC era and the
performance is good. Good results were obtained just at the end of the
month when connecting these chips to a 12 cm detector. Threshold
uniformity, noise values and stability all look good. One of these chips
was irradiated to 17 Mrad and the performance is still good. The result
of negotiations with Temic regarding the ABCD wafers that had three
potentially relevant parameters out of spec was (1) delivery of two
wafers for free to CERN for testing and (2) agreement to reprocess a lot
for delivery by mid-September. It is expected that the parameters out of
spec will not affect the performance and so far this is borne out by
measurements. The new ABCD with trim DACs in each channel to adjust the
threshold (to be more uniform) are stable even without backside
metallization and appear to function well (pre-rad) in all respects
tested so far on a handful of chips. Six ABCDs have been mounted on a
hybrid and tested successfully and then bonded to a 12 cm long detector
also with success. The operation appears to be stable, the threshold
uniformity good(after trimming) and the noise levels as expected. This
single-sided module will be tested in a beam in early August. So far all
work on the ABCD has been done at CERN. Honeywell completed fabrication
of the ABC wafers a week ahead of schedule, but one parameter was
slightly out of spec pre-rad but in spec post rad(up to 25 Mrad).
Negotiations with Honeywell resulted in the delivery of one wafer to
LBNL in early August and the very first (one day) test results are very
encouraging. This wafer will be diced and CAFE-P/ABCs mounted on hybrid
in early August. A decision will be made by mid-August about how to
proceed with Honeywell - to grant them a waiver and accept all of the
wafers or ask them to reprocess. At the moment, the US view is to grant
the waiver, given that all parameters are within spec post-rad.

Negotiations on the conditions of the Frame Contract continued and the
first meeting with Honeywell was held (after multiple meetings with
Temic). This is going slowly since we are attempting to define with both
Temic and Honeywell a mechanism for a yield guarantee for production
quantities.

Hybrid delivery is on track to meet the need for testing ICs and
fabrication of a few modules at LBNL for the September test beam.
Preassembly of parts for these modules has started.

3.  ReadOut Driver System

Costs are within allocated limits. A workshop was help at University
College London \\on July 19-20 to review the state of the SCT and pixel
off detector electronics. Representatives of all the ROD interfaces were
present (timing interface module, ROD crate processor, back of the crate
card (optical interface), and ROD software. Updated status presentations
on each of the areas were presented. It is clear that the interface
definitions are improving. Completing the interface definitions is
essential to the ROD development. This will be an ongoing effort. The
next meeting will be held the week of September 20 at CERN.

Progress has been made on the interfaces, Architecture and simulation
code. A short version of the meeting notes is shown below:

Latency and Module Mapping

John Lane presented the current status of the latency. There were no
problems in this area. The written feedback that describes the latency
was not all in. There is a possibility that the latency of the ROD will
be reduced from 3 to 2 clock ticks.

Mapping of modules to the ROD data stream is proceeding. It appears that
ROI mapping is preferred. This area should be better understood in a
month or two.

Read Out Driver (ROD)

The ROD design and schedule was presented. The schedule which includes
the production (current ROD US ATLAS baseline) was agreed to by SCT and
pixel community. The ROD interfaces will also adopt a similar schedule.
This is important because these interface cards are needed to test the
complete functionality of the ROD. The ROD discussion was centered
around the following items.

A new model of the ROD was presented by Richard Jared. The model was
completed by Mark Nagel. The contents of the model was generally
excepted. The model has the decoder FIFO (192 words) incorporated in the
decoder FPGA.

A new function was pointed out by Gareth Moorhead. This was to issue the
calibration strobe to all but a few modules and triggers to all modules.
This has not been part of the requirements. The request is quite
reasonable for it provides for testing of cross-talk between modules.
This request will have to be included in the requirements.

It was also pointed out that the model did not cover the need to issue
commands of very long length to one module at a time. This will be
included into the model.

Throttle was discussed. The current status is that the SCT will probably
not need throttling. The pixel needs are not completely understood at
this time. Currently the ROD will not have throttling but will have the
capability to incorporate it if needed.

ROD Crate Controller (RCC)

The RCC functionality was presented by John Hill. The drawing will be
updated and placed on the web. The RCC discussion was centered around
the interfaces.

The TIM RCC VME interface will use A24 D16 for communication.

The RCC ROD VME interface will use A24 D32 for communication.

The ROD FPGA serial PROM will be written by the RCC over VME.

John Hill will determine if VME Broadcast in the VME64x standard.

Back Of Crate (BOC) (Optical interface to the front end modules)

Maurice Goodrick presented the BOC material. Maurice will provide new
updated (draft form) diagrams and a short write up of the BOC and
related interfaces, to be placed on web.

Maurice will determine what the current interlock system is for the
fibers. This needs to be understood for it will effect the prototype
card design.

Power utilization of the BOC needs to be completed so that the number of
power pins on the back plane can be checked. This information is also
needed to determine cooling and power supply requirements.

The Pixel MCC will always start data output on the same phase of the
40MHz clock.

Timing Interface Module TIM

John Lane presented the TIM material. John will provide new updated
diagrams and a short write up of the TIM and related interfaces, to be
placed on the web sight.

The following issues are decisions were made:

The busy logic will be on the TIM.

The busy signal from the ROD to TIM will be on the back plane.

The TTC0-7 lines in the ROD TIM Interface document need the following
changes (Lane).

TTC4 was 1 start bit + 24L1 ID bits + 12 BC ID bits (+trigger type)

should be 1 start bit + 24L1 ID bits + 12 BC ID bits

TTC5 was ROD Clear

Should be 1 start bit +8 trigger type bits.

TTC6 was unused

should be reserved for periodic reset.

Latency adjustment to the fast signal Level 1 Accept (L1A), Event
Counter Reset (ECR) and Bunch Counter Reset (BCR) and Calibration signal
(CAL) will be done in the TCC system. This means that there will be no
latency adjust on the ROD.

A simulated beam crossover counter and level 1 counters will be needed
in the ROD to provide the BC ID value for ROD initiated calibration
related triggers and resets. The beam crossover counter may require a
preset value on reset.

At what time are the ECR and BCR issued in the TCC system? Are the
signal generation times time-critical? What is the correct definition of
the two signals? These questions need addressing.

P3/J3 Back Plane

Richard Jared presented the P3/J3 Back Plane material. Richard will
provide updated (draft form) diagrams and a short write up of the P3/J3
Back Plane, to be placed on the web sight.

Martin Postranecky presented a variant of the P3 back plane that was
accepted.

The clock signal will go to the BOC card and then sent to the ROD.

The TIM will be in slot 6 (Lane).

Philippe Farthouat must be contacted to determine the connector type for
P3/J3.

Roy Wastie will layout the P3/J3 back plane.

Timing calibration

Richard Nickerson presented the timing calibration of the front end
modules. These document were created over one year ago.

The accuracy of the timing needed at the modules is 0.5ns, 1.0ns is
probably suitable.

One document of the set of 3 is missing. Richard will make an attempt to
find the document and pace it on the web.

Richard Nickerson and Tony Weidberg are no longer in a position to
support the timing calibration effort. It was agreed the Cambridge is
the logical place to support the timing calibration effort because to
the BOC effort at that institute. The off detector electronics group
recommended that Andy Parker take on the timing and calibration
responsibility. In the advent that Cambridge can not support the effort,
it should be supported by John Lane from UCL. Recommendations will be
made to Alex.

ROD Primitives

Richard Jared presented a first draft of possible ROD primitives. The
ROD is currently based on a register based I/O system. This means that
there are only 5 addresses that the RCC can read or write to. Primitives
that access the ROD were described.

It is clear that this list processing concept must be evaluated to see
that it will not break and provide the needed compatibility with the
software.

Simulation

Damon Fasching presented simulations of the ROD for Pixels and SCT RODs.
The results show that the SCT 96 link ROD will work with the 192 word
decoder FIFO at 2.5 times normal occupancy and that there is sufficient
bandwidth for the Pixels The event generator of the pixels needs
updating.

Architecture of the ROD is very near completion. There are no major
changes that resulted from the meeting.

Test beam support is continuing at a low level.

# Detailed Reports

1.  Pixel System

1.1.1.1 Mechanics (E. Anderssen, D. Bintinger, M. Gilchriese)

  ---------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}     [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*ID Eng. Review at CERN     20-Oct-98                20-Oct-98                                        Done

  Select prototype ring        1-Nov-98                 1-Feb-99                                         Done
  concept                                                                                                

  Select materials for frame   15-Mar-99                7-Apr-99                                         Done
  proto.                                                                                                 

  Complete fab 1^st^ prototype 1-Apr-99                 30-Jun-99                15-Aug-99               Delay
  ring                                                                                                   

  Complete frame Phase I       1-Jul-99                 1-Jul-99                 15 Aug-99               Delay

  Complete fab 1^st^ prototype 1-Jul-99                 1-Jul-99                 15 Sep-99               Delay
  disk                                                                                                   

  \*Select sector baseline     1-Sep-99                 1-Sep-99                 1-Oct-99                Delay
  concept                                                                                                

  \*Module attachment CDR      1-Sep-99                 1-Sep-99                 1-Oct-99                Delay

  \*Compl test of 5-disk       1-Sep-99                 1-Sep-99                 1-Oct-99                Delay
  prototypes                                                                                             

  Complete frame Phase II      1-Oct-99                 1-Oct-99                 1-Oct-99                OK

  Complete frame Phase III     1-Feb-00                 1-Feb-00                 1-Feb-00                OK
  ---------------------------- ------------------------ ------------------------ ----------------------- ----------------------

LBNL

1.1.1.1.1 Design

Design studies by Hytec, Inc for the overall pixel support frame
continue. An analytical FE model of the support frame sandwich panel has
been prepared and steps are underway to check the adequacy of
representation. The model, and modifications thereof, will be used to
compare with test results of prototype panels. The design for aluminum
tube prototype sector 5 was completed and drawings for parts were
submitted for fabrication. Aluminum tube prototype sector 5 is designed
for the 66 module (11 sectors) disk of the June 99 pixel layout.

1.1.1.1.2 Development and Prototypes

ESLI, San Diego, has delivered 4 of the planned 12 prototype sectors to
be used in fabricating the first prototype pixel disk. The delivery of 3
further sectors is expected the first week of August with the remaining
five to be delivered by mid-August. The first 4 sectors have good
general appearances and the weights indicate acceptable average
radiation lengths. However of these first four sectors, 2 meet our
planarity requirements and 2 do not. The 2 that do not are still useful
for a prototype disk. The planarity problem has been discussed with ESLI
and ESLI is now selecting interior glassy carbon coolant tubes with
better planarity, which should result in more planar sectors.

The prototype disk support ring, the precision support for the disk
sectors, is presently being bonded together. After curing, the ring will
have the precision mounting holes for the sectors machined into it. It
is estimated that the ring bonded assembly will be completed by 15
August. A clean space at LBNL has been chosen for the fabrication and
testing of the prototype disk.

Infrared imaging of the Genoa fabricated pixel barrel stave was
completed. This stave showed the expected heat profile with powers of
80, 100, and 120 Watts. Pictures were posted on the web.

Replacement honeycomb was ordered and received from YLA for prototype
panels of the Pixel Overall Support Frame. The original honeycomb had
one rough edge that that did not allow proper bonding to facing sheets.
The new honeycomb is made from XN50 woven cloth that has a tighter weave
pattern due to the much lower number of fibers per tow. YLA also
exercised greater care in machining the second batch. Sanding of the
honeycomb is an option to improve the edge quality, a step to be avoided
from an obvious cost implication. The first panel using the replacement
honeycomb has been completed. Another panel using a densified form of
reticulated viterous carbon foam as core will also be fabricated. The
panels will be tested for static stiffness and then lightweighted by
cutting out portions of the panel to achieve the proposed ATLAS frame
design geometry. Stiffness tests will then be repeated to evaluate the
effect of the cut-outs

The corner block design for the overall support frame panels is being
finalized in preparation for the next frame prototype phase. The corner
blocks are used in joining the frame panels together to form the support
structure. Tooling for producing the corner elements is partially
completed awaiting the final dimensions of the corner elements.

1.1.1.1.3 Disk Production

No activity.

1.1.1.2 Pixel Sensors (S. Seidel)

  --------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}    [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*Start market survey       2-Nov-98                 1-Dec-98                                         Done

  \*2^nd^ prototype PDR       1-Dec-98                 1-Dec-98                                         Done

  \*Complete market survey    5-Mar-99                 12-Feb-99                                        Done

  \*2^nd^ prototype FDR       29-Mar-99                22-Feb-99                                        Done

  \*Compl. Test 1^st^         13-Apr-99                13-Apr-99                                        Done
  prototypes                                                                                            

  \*Compl. 2^nd^ prototype    27-Apr-99                1-May-99                                         Done
  design                                                                                                

  \*Compl. Fab of 2^nd^       21-Sep-99                21-Sep-99                21-Sep-99               OK
  prototypes                                                                                            
  --------------------------- ------------------------ ------------------------ ----------------------- ----------------------

1.1.1.2.1 Design

No activity.

1.1.1.2.2 Development and Prototypes

Following final characterization, six Prototype 1c wafers were shipped
from UNM to IZM and 2 to Udine for dicing and assembly into modules. UNM
ordered and received 2 new radioactive sources for improved calibration
of the pixel DAQ test stand. M. Hoeferkamp, P. Skubic, and J. Snow
participated at the test beam with other ATLAS collaborators.

1.1.1.2.3 Production

UNM obtained FY '00 external funding for 2 undergraduate technicians to
conduct the characterization of the Second Prototypes and the Production
wafers. One has now been fully trained; the second will begin training
on 16 August.

1.  Pixel Electronics (K. Einsweiler, R. Kass)

  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}   [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  Compl. Design HSOI test    16-Apr-98                1-Nov-98                                         Done
  die                                                                                                  

  Compl. Fab HSOI test die   26-Aug-98                31-Mar-99                                        Done

  Compl. Design DMILL test   15-Dec-98                15-Dec-98                                        Done
  device                                                                                               

  Submit 2^nd^ Honeywell SoI 15-Jan-99                                                                 Not known
  test die                                                                                             

  1^st^ design review of     25-Jan-99                23-Feb-99                                        Done
  DMILL proto                                                                                          

  \*FDR DMILL 1^st^          25-Jan-99                15-Jun-99                21-Jul-99               Done
  prototype                                                                                            

  \*Compl. Design DMILL      26-Feb-99                30-Jun-99                9-Aug-99                Delay
  1^st^ proto.                                                                                         

  1^st^ design review of     1-Jun-99                 1-Oct-99                 1-Oct-99                Delay
  Honey. Proto                                                                                         

  Compl. Eval. HSOI test die 1-Jul-99                 1-Aug-99                 1-Sep-99                Delay

  \*FDR Honeywell SoI 1^st^  5-Mar-99                 15-Nov-99                15-Nov-99               Delay
  prototype                                                                                            

  \*Compl. Design Honey. SoI 2-Apr-99                 1-Dec-99                 1-Dec-99                Delay
  proto.                                                                                               

  \*Compl. Fab of DMILL      23-Jul-99                15-Oct-99                15-Oct-99               Delay
  1^st^ proto.                                                                                         

  \*Compl. Fab of Honey. SoI 25-Aug-99                1-Mar-00                 1-Mar-00                Delay
  1^st^ proto                                                                                          

  \*Compl eval. DMILL        9-Dec-99                 1-Jun-00                 1-Jun-00                Delay
  prototype                                                                                            

  \*Compl eval HSOI          15-Feb-00                1-Jun-00                 1-Jun-00                Delay
  prototype                                                                                            

  \*Review design approach   19-Jan-00                15-Jun-00                15-Jun-00               Delay

  \*Select rad-hard vendor   29-Jan-00                15-Jul-00                15-Jul-00               Delay
  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------

1.1.1.3.1 Design

LBNL

Our highest priority remains the DMILL front-end chip submission (FE-D).
The schematic and layout for the entire chip is now completely frozen,
and we are completing the last few verifications and simulations. After
a working week in Bonn in late July, all technical issues have been
resolved, and we are quite pleased with the design of the chip.

The major technical hurdles at the beginning of July included revisions
to the front-end design to deal with problems uncovered by LBL
measurements, completion of a new design for the sense amplifiers at the
bottom of column for data readout, and completion of the intricate
placement and routing of all remaining digital blocks in the bottom of
the chip.

For the front-end, a very large effort has been made by CPPM in the last
month, and our recent lab measurements, showing large channel to channel
variations in timing, have been confirmed. After some effort, it was
possible to reproduce the measurement results with decent accuracy in
SPICE simulations. The problem was that the output node of the
discriminator was much more sensitive to capacitive loading than the
designer had realized. Under some biasing conditions, risetimes of 100ns
could be seen. Small channel variations on these poor risetimes then led
to the large observed variations. A modification of the design has been
made, which involved taking the final output from a different node in
the discriminator. In simulation this leads to much improved
performance. In addition, it was realized that there were much more
serious problems with capacitive loading in the BiCMOS design than
anticipated as well. Although the BiCMOS design has better performance
for timewalk due to very small charges, its timing dispersion is quite
poor, and no acceptable improvements were found. Hence, for the final
submission, we have returned to the previous all CMOS version of the
front-end. Some last attempts are being made to improve its marginal
timewalk performance by reducing parasitic capacitances on critical
nodes. We will have to evaluate the final chips before and after
irradiation to see whether they meet our requirements for ATLAS. It is
possible that we will have to accept a higher in-time threshold than we
would like,which could potentially reduce the lifetime of the detector
somewhat.

For the sense amplifiers, which have the difficult task of recovering
the data from the bus in the column pair which connects all of the pixel
back-ends to the end of column logic. The drivers that one could fit
into the 400m pixel in DMILL are just barely adequate to the task, and
after irradiation become very marginal. A very effective sense amplifier
design was needed to recover the data signals at 20 MHz readout rate. A
new bipolar design, which is a joint LBL/Bonn/Marseille design, appears
to work extremely well. It uses bipolar input transistors, which have
many advantages in this case. In particular, they produce a very large
gain with very stable current thresholds, while providing a very low
input impedance to the data bus (which gives data line swings of only
about 50mV). We will operate these circuits at a rather low bias (about
10uA each), and be able to adjust their current threshold in the few uA
region, which appears to give excellent performance, even after
irradiation. The layout of the design was done by Bonn, and many
simulations have been performed over the last week in LBL.

Finally, the last bits of digital layout at the bottom of the chip have
been completed in Bonn. After extensive large digital simulations in
LBL, two very minor changes were made to the schematic. The digital
readout has now successfully gone through SPICE simulations of several
hundred ms of hits at above design luminosity (several thousand random
hits have been processed). These large and CPU intensive simulations are
now being repeated for the final schematic, including the new sense
amplifiers. Several process corners are being investigated, but we do
not anticipate any surprises at this time.

The complete reticle for this TEMIC DMILL engineering run has been
finalized. We received an example GDS file for the layout of the scribe
regions, and so we are planning to do the entire reticle layout in Bonn.
This should insure that the geometry to the layout is exactly what we
want. The reticle will include two pixel array chips (FE-D). It will
also include an MCC prototype from Genova containing many improvements
towards a final version, but not yet representing a complete chip. There
are also prototypes of opto-link chips (all CMOS versions of the driver
and receiver chips). The opto-electronics designs are based on those of
the SCT, but have been transferred from a commercial rad-soft bipolar
process to DMILL by Siegen and Ohio State University. A special process
monitor bar has been developed by LBL to allow reliable extraction of
SPICE models from the FE-D wafers so that we can cross-check our design
performance against expectations. Finally, a rad-hard LVDS buffer is
included which will allow us to make a complete rad-hard version of the
single-chip support card that we use for testing single chips in the lab
and testbeam. With this buffer, we have the capability to operate a
single pixel chip (or electronics/sensor assembly) while it is being
irradiated to LHC fluences.

We now expect to submit the GDS files to TEMIC about Aug. 9. We have
arranged to accelerate the fabrication time to roughly 9 weeks instead
of the usual 12, in order to get results as quickly as possible from the
submission. Hence, we expect to be testing these new wafers in our labs
roughly around Oct. 15. We already have appropriate wafer probing
capability set up in our lab for testing these chips, but we will be
upgrading the corresponding software over the next few weeks in order to
be fully ready when the wafers return. The probing is likely to be
divided between Bonn and LBL, and we have also supplies Bonn with an
appropriate interface card, and some chip testing software.

In order to exercise the chips to the fullest extent possible, and in
particular to develop the capability to label chips as "known good die",
and be sure that this classification will remain true after exposure to
the full radiation doses of ATLAS, we are developing an improved test
system. This system uses many of the same techniques present in
commercial IC testers, but applies them in a focussed way to the
specific chip testing problem that we have. We believe this is essential
to do parametric testing of certain parts of the chip (modified clock
frequencies, power supply voltages, and signal phasing), and evaluate
for each die how far away they are from our specifications. Many chips
would then be characterized before and after irradiation. This will
allow us to develop "strict selection criteria" which a chip should pass
before irradiation, in order to be sure that it would pass "standard
selection criteria" after irradiation. The initial conceptual design of
this system is complete, and we hope to complete the detailed schematics
over the coming two months, in order to have working boards by late Fall
this year. This system should be critical for evaluating our upcoming
rad-hard pixel chip submissions, and arriving at the optimal final chip
design and vendor for ATLAS late in 00.

Ohio State

The radiation hard version of the DORIC4 chip is now ready for
submission in a multi-project run with other pixel chips . The layout
bug in the current version of the bias circuit for LVDS cells has been
fixed in Bonn. The circuit was simulated using DMILL corner models with
BSIM3 and ELDO (included post-radiation) and some minor improvements
were made in response to the result of the simulation. The design is
expected to be submitted in mid-August and we expect the chip delivery
in October.

We are still discussing ITAR agreement compliance and security with OSU
officials. Hopefully, all remaining issues will be resolved soon.

The installation of CADENCE on our workstation(s) is proceeding and
progress has been made in learning to simulate some circuits.

1.1.1.3.2 Development and Prototypes

LBNL

The Honeywell SOI multi-project submission which we made in Nov. 98 has
returned to LBL and undergone preliminary evaluation. A test program
written by our engineer for the CERN IC tester in Geneva is now working,
and we expect to get extensive new results within the next month. We
have therefore delayed our plans to irradiate several die in the 88"
cyclotron at LBL until after the end of the several month shut-down. We
expect to irradiate some of these devices in Sept. or Oct. timeframe. We
have also received corner models for the HSOI process from Honeywell,
which we will be evaluating in more detail by making systematic
comparisons to the test chip performance.

1.1.1.3.3 Production

No activity.

2.  Pixel Hybrids (R. Boyd, S. Timm)

  ---------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}     [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \* Compl. Assembly of 1^st^  14-Jan-99                10-Nov-98                                        Done
  proto.                                                                                                 

  \* 1^st^ prototype design    18-Feb-99                18-Feb-99                                        Done
  review                                                                                                 

  \* Compl. Tests of 1.0       15-Apr-99                15-Mar-99                                        Done
  protos.                                                                                                

  \* Select hybrid type        15-Apr-99                1- Mar-99                                        Done

  Compl. Design of 1.x         1 - Apr- 99              21-Apr-99                                        Done
  proto^.^                                                                                               

  Fabrication of 1.x compl                              1-Aug-99                 1-Sep-99                Delay

  Singulate 1.x proto compl                             15-Aug-99                15-Sep-99               Delay

  Assembly of 1.x proto compl                           1-Sep-99                 17-Sep-99               Delay

  Prototype 1.x tests complete                          15-Oct-99                15-Nov-99               Delay

  Module assy with 1.x compl                            15-Sep-99                15-Oct-99               Delay

  Design of proto 2.0 begins                            1-Sep-99                 13-Jul-99               OK
  ---------------------------- ------------------------ ------------------------ ----------------------- ----------------------

1.1.1.4.1 Design

Oklahoma

Delivery of v1.2 Flex Hybrids from R&D circuits has once again been
delayed. Processing of a third batch was begun the last week of June,
but was abandoned when it was discovered that they were using the wrong
base metalization (rolled Cu instead of sputtered/plated) and in order
to take advantage of better photoresist materials which were received in
late July. At this writing, they are unable to complete drilling of the
via holes because of equipment problems. They have been working on this
problem for about one week and estimate that it will take about one week
to complete fabrication after this problem is solved. Several sample
circuits were received in early July from previous failed runs and one
has been assembled. It will be sent on to Albany for evaluation of
testing assembled circuits.

The v1.1 Flex Hybrid delivery from CERN has also been delayed for
unknown reasons. The via holes have been etched and production is
proceeding, with delivery (after testing) expected by the end of August.
Due to the late delivery, one panel of circuits will be delivered to
LBNL so that at least one or two can be singulated by hand for
construction of a module for the September test beam. Three panels are
to be delivered to OU where, likewise, at least one will be singulated
by hand for module assembly. The balance will be delivered to
Spectralytics for laser singulation.

The delays have a one month impact on the rest of this year\'s schedule
and may delay the completion of design for v2.0, since some evaluation
of v1.x Flex Hybrids will be required so that what is learned from them
can be incorporated into the new design.

We have also received a quotation of \$3200 from Compunetics
(Monroeville, MA) for construction of 50 v1.x Flex Hybrids and an
estimated delivery of 4 weeks ARO. We have asked for a cost estimate on
a delivery of 2 weeks ARO. They also quoted a price of \$34.50/flex
circuit for production of 3500 pieces (for budgetary purposes). They are
currently fabricating flex circuits for D0 at Fermilab which have
similar details.

Dyconex of Zurich has declined to quote on the design, stating that it
is not within their capabilities.

Several design meetings for v2.0 were held in July between LBNL and OU,
with Genoa being included in one of those. The greatest challenge is the
very restrictive envelope proposed for the barrels. Several iterations
will be required to find a compromise between electronic, mechanical and
physics requirements to come to an appropriate layout scheme. Drawings
clarifying the constraints will be developed and circulated by R. Boyd
and M. Olcese (Genoa) for discussions in meetings to take place in
September. Issues to be resolved include minimum clearance available in
r, placement of components and maximum component height.

1.1.1.4.2 Development

OU

No activity.

Albany

The probe card for testing the FE pads of the flex hybrid is now on its
way to us. We will use two VAMUX64 chips (designed by OU) to multiplex
the outputs from the probe card into a multimeter to measure resistance.
Once the probe card is received, we will forward connector details to OU
so that the circuit board design for the VAMUX64 chips can be finalized.

We now have a complete VME setup for module testing here at Albany,
complete with PLL, PCC, and all required power supplies. We are in the
process of debugging the system and establishing communications between
the software and hardware. A module will be required shortly to complete
the configuration and begin test verification.

1.1.1.4.3 Production

No activity.

1.1.1.5 Pixel Modules (R. Boyd, K. Einsweiler, K. K. Gan, M. Gilchriese)

  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}   [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*Compl. 1^st^ proto.      29-Oct-98                1-Mar-99                                         Done
  Design                                                                                               

  \*1^st^ proto. Design      18-Feb-99                18-Feb-99                                        Done
  review                                                                                               

  \*Compl. Tests of 1^st^    18-Mar-99                17-Sep-99                17-Sep-99               Delay
  protos.                                                                                              

  \*Select module type                                18-Mar-99                22-Feb-99               Done

  \*2^nd^ proto. Design      17-Sep-99                10-Sep-99                10-Sep-99               OK
  review                                                                                               
  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------

1.1.1.5.1 Design/Engineering

LBNL

Difficulties thinning dummy wafers from IZM in Berlin reported last
month have been understood. These dummy wafers were not fabricated to
specifications expected for real wafers. In particular, there was a
substantial build up of material on the edges of the wafer and (contrary
to requests) the wafers were not coated with photoresist by IZM. The
wafers are held by tape (on the bumped side) on a chuck for the thinning
process. The absence of photoresist and the high points at the wafer
edges caused the wafer to be supported at a few spots rather than
uniformly (the tape adhesive was not deep enough to solve this problem).
At some point in the grinding process the wafer becomes so thin that its
intrinsic strength is too low and it cracks under the grinding pressure.
This was explained to IZM and they have promised to make dummy wafers
without the \"flash\" on the edges for new trials in August. Real wafers
(FE-B from Alenia with indium bumps protected by photoresist) are also
expected in early August.

Design work for tooling for module assembly continued this month under
the direction of F. Goozen. The major issue under study in July was the
controlled dispensing of adhesive that glues the flex to the back side
of the sensor. This must be done carefully to provide a uniform, hard
surface for wire bonding and control the location of the glue. A number
of different techniques were tried with limited success and the current
thinking is to make a precision glue dispenser based on x-,y- and z-axis
stages and a controlled \"syringe\".

1.1.1.5.2 Development and Prototypes

LBNL

We had expected to have several new modules for the July H8 testbeam.
However, due to delays in module assembly by IZM (bump-bonding delays),
PC board fabrication delays, and Flex fabrication delays, none of the
new assemblies is yet ready. We decided to bring our existing Flex 1.0
module back to the testbeam to further explore the readout problems that
we had observed at CERN in the May testbeam. This has been a very
productive effort, involving close collaboration between LBL and Genova.
LBL provides the expertise on the pixel chips, and also the DAQ and test
software, whereas Genova is the designer of the MCC chip which readouts
out the module. We have uncovered several classes of minor problems, and
have significantly improved out diagnostic capability for operating
modules.

The first minor problem involved the observation of synchronization
errors on the module. In this case, about every 10K events, one of the
pixel chips on the module would not produce the proper "end of event"
words that are required for the MCC to carry out error-free event
building. The geographical distribution of the errors suggests a signal
quality problem in the distribution of the fast LV1 trigger signal
around the Flex. We will now examine the signal quality in more detail
in the lab. It seems likely that the problem arises due to the larger
than expected capacitive loads that the long and narrow distribution
busses on the Flex create. Future versions of the MCC and Flex may be
modified to reduce the fanout of 16 in the present design to a fanout of
8, by using two separate busses for the two sides of the module.

The other remaining problems appeared to be an interaction between
occasional "large" events observed in the testbeam due to peculiar noise
environment. The result was that about once every 15 minutes, one of
these large events would cause the MCC to fail in its event building
task, and require a software reset to continue data taking. There are
two different problems here. The first is, what are the large noise
events ? Normally, the 50K channel pixel module produces 1-2 real hits,
no noise hits, and the correct end-of-event words). Here, the primary
suspicion is that the very minimal decoupling available in the first
version of the Flex design does not provide adequate noise immunity. The
second problem, mpre serious, is that there seems to be a weakness in
the MCC when handling large events. The chip is known to handle obvious
problems correctly, but further simulations and should in explaining the
observed distribution of error flags, and the occasional failure of the
event builder. Again, now that we can monitor the problem in more
detail, we can try harder to duplicate the effects in our labs. Up to
know, the modules have always performed quite well in the lab, and no
sign of event building failure has been observed.

These "system test" results are critical to finalizing the MCC design
for the next generation submission, to be made in early 00. That chip
should be very close to a pre-production version, and should be capable
of reliable operation even under quite noise conditions.

Ohio State

Work is continuing on the packaging of VCSELs. We now have a procedure
for depositing Au/Cr traces on Macor after several attempts. A test run
of 26 wire bonds has 100% success rate. The pull strength on 3 test
bonds are high, 10, 11, and 12 grams. This is well above the minimum of
6 grams considered acceptable. The 3-dimensional mask for depositing the
traces has been redesigned. The previous version has machined slits on a
bend brass sheet. This has the disadvantage of a round corner at the
bend and the fine metal traces are weak and prompt to breakage. In the
new mask, we use two metal sheets with fine teeth mounted at right angle
to form slits. The teeth are significantly stronger than the slits from
the previous prototype. We have successfully deposited traces using the
new mask.

We prototyped two VCSEL mounting jigs. The first prototyped has the
VCSEL placed face down in a pocket and the orientation of the chip is
observed via a small hole (125 μm) under the chip. Unfortunately, the
drilling of a 3-mm long hole is not practical. The next prototype is a
three-piece design with the VCSEL placed face up: a base piece for
housing the base of the optical package, a 50 μm stainless steel sheet
with three pockets for the VCSEL and PIN, and a top piece to push the
sheet against the base piece. The prototype is also not satisfactory
because it is not possible to mount the thin sheet flat to the level of
25 μm. We are working on a third prototype in which the jig is made out
of one piece of aluminum with a small area machined down to 50 μm to
replace the stainless steel sheet. If this is successful, we can then
mount the VCSELs and measure the coupled optical power.

1.1.1.5.3 Production

No activity.

1.1.2 Silicon Strips

1.1.2.1 IC Electronics (A.A. Grillo)

  --------------------------- ------------------------- ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}    [Baseline]{.underline}    [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*Send out market survey    1-Sep-98                  17-Aug-98                17-Aug-98               Done

  \*FDR for 2nd CAFÉ-M        15-Sep-98                 11-Sep-98                11-Sep-98               Done

  \*Procurement in place for  9-Oct-98                  13-Nov-98                13-Nov-98               Done
  2nd proto                                                                                              

  \*FDR for 2nd ABC           23-Oct-98                 26-Jan-99                26-Jan-99               Done

  \*Closing date for market   26-Oct-98                 25-Sep-98                25-Sep-98               Done
  survey                                                                                                 

  \*Submit 2nd CAFÉ-M         30-Oct-98                 26-Jan-99                26-Jan-99               Done

  \*Issue call for tender     9-Nov-98                  9-Nov-98                 9-Nov-98                Done

  \*Submit 2nd ABC            16-Nov-98                 1-May-99                 1-May-99                Done

  \*FDR for 2nd ABCD          11-Dec-98                 15-Dec-99                15-Dec-99               Done

  \*Closing date for tender   21-Dec-98                 22-Jan-99                22-Jan-99               Done

  \*Submit 2nd ABCD           27-Jan-99                 8-Apr-99                 8-Apr-99                Done

  \*CERN finance comm.        15-Mar-99                 15-Mar-99                15-Mar-99               Done
  Approval                                                                                               

  \*Frame contract in place   15-Apr-99                 30-Sep-99                30-Sep-99               OK

  \*Compl. Fab of 2nd CAFÉ-M  19-Apr-99                 8-Apr-99                 8-Apr-99                Done

  \*Compl. Fab of 2nd ABC     19-Apr-99                 3-Aug-99                 3-Aug-99                OK?

  \*Test systems complete     26-Apr-99                 31-Jul-99                20Aug-99                Delay

  \*1st ICs avail. For 2nd    18-May-99                 30-Aug-99                30-Aug-99               OK
  proto hybrid                                                                                           

  \*Compl. Fab of 2nd ABCD    30-Jun-99                 26-Jun-99                30-Sep-99               Delay

  Compl. metallization 1^st^  \-\-\-\-\-\-\-\-\-\-\--   15-Jul-99                7-Aug-99                Hold
  ABCD                                                                                                   
  --------------------------- ------------------------- ------------------------ ----------------------- ----------------------

1.1.2.1.1 Design/Engineering

LBNL & UCSC

Continued simulations of the fix for the ABC bug (See June's report.)
are still positive. There is some difficulty fitting the fix into the
existing chip floor plan. It is not clear yet whether the die size will
have to increase but RAL is working to make it fit. Final, post-layout,
simulations are awaiting that conclusion.

The CAFÉ-P tester has been exercised with the old (CAFÉ-M) probe card to
test 44 channels and works correctly. We are still waiting the new probe
card to be able to test all 128 channels together. The probe card was
delayed but is due by 9-Aug. If needed, we will screen sufficient
CAFÉ-Ps for the first single sided CAFÉ-P/ABC module with the old probe
card. We are also working on engineering of enhancements to the tester
which will be needed for large volume production testing.

The hardware design for the new ABC tester is complete. There is still
considerable amount of software to write for full test capability.
However, there is capability to run simple data patterns for a
rudimentary wafer screen. More complete testing of the chips will be
done on hybrids for the initial evaluation. It is still expected that
RAL will do the bulk of the wafer screening of this pending prototype
lot. LBNL will screen a few chips for the first couple of evaluation
modules and then focus on detailed ABC chip performance evaluation.

1.1.2.1.2 Development and Prototypes

LBNL & UCSC

The issue with the ABCD wafers was resolved this month. Formally, CERN
has rejected the lot of wafers because three PCM parameters are out of
spec. Temic has agreed to give us two wafers free of charge for
evaluation. They have further agreed to process a new engineering lot of
wafers to be completed by 15-Sep. They also have given us an offer to
purchase the remaining 6 wafers from the existing lot at a reduced price
of 30150 FRF/wafer (roughly \$4,900/wafer). The two wafers received by
CERN have been tested at wafer probe showing a yield of 40% and 38%
each. This is approximately what is expected from a normal lot. One
wafer has been diced and two 6-chip hybrids have been built using each
of the 2 ABCD designs on the wafer. The plan is to connect these each to
a 12cm detector so that the design and, in particular, the stability
issues can be evaluated. Depending upon the results of these tests, the
collaboration will decide whether or not to purchase the remaining 6
wafers or not. The main purpose for purchasing the extra wafers will be
to get the module building program moving without waiting for the new
lot in mid-September and to provide extra chips beyond the number
available on the expected 8 wafers for more module building.

Honeywell completed fabrication of the ABC wafers the last week of July,
a bit earlier than targeted by the amended PO to accelerate the process.
However, we have a similar problem as with ABCD in that one of their
process monitor parameters was found to be out of spec. The parameter
(VTN, threshold voltage for NMOS devices) is 25mV below the lower limit
for pre-rad measurements. However, it is within spec by more than 100mV
for the post-rad measurements. The designers are confident that this
will not cause the chips to be non-functional. Some of our European
collaborators have expressed concern, as they did with the Temic lot,
that we should not base our technology decision in December upon a wafer
lot which is not typical. The difficult question to answer is how
"representative" is this lot. Honeywell has agreed for now to give us
one wafer to evaluate so that we can better determine the effects of
this VTN value and aide our decision in granting the waiver they seek
for the remaining wafers. We expect to test this wafer the first week of
August and to negotiate a resolution to this issue with Honeywell and
our European collaborators shortly after that.

We have mounted our existing CAFÉ-P hybrid on a 12 cm detector to
continue the chip evaluation. In the absence of ABCs, we are using the
few remaining CDPs we have left from SSC days. The performance with 2
CAFÉ-Ps and 2 CDPs is quite good with expected noise levels and
stability limits. We are now completing the single-sided module with 4
more chip pairs so that we can test the performance of all 6 and look
for any noise or stability issues induced by the added chips.

1.1.2.1.3 Production

Temic and CERN have exchanged responses to the proposals made at our
7-Jun meeting on the Frame Contract. There doesn't seem to be any
"show-stoppers" but details are still being ironed out. We had a similar
meeting with Honeywell on 29-Jul. Overall the meeting was positive and
both sides are trying to be flexible concerning legal and administrative
differences. We are hopeful that we can come to a common agreement soon
but there are many issues still to resolve, most of them are business
and not technical in nature. We have another meeting scheduled with
Honeywell on 19-Aug.

1.1.2.2 Silicon Strip Hybrids (C. Haber)

  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}   [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  Complete design of 1st     17-Nov-97                17-Nov-97                                        Done
  prototype                                                                                            

  Complete fab of 1st        2-Feb-98                 23-Mar-98                                        Done
  prototype                                                                                            

  Preliminary design review  3-Aug-98                 7-Dec-99                 7-Dec-99                Delay

  \*Compl. 2nd proto subs.   29-Oct-98                15-Jun-99                15-Jun-99               Done
  design                                                                                               

  \*Compl. 2nd proto cable   29-Oct-98                1-Sep-99                 1-Sep-99                Delay
  design                                                                                               

  \*Compl. 2nd proto fanout  29-Oct-98                1-Sep-99                 1-Sep-99                Delay
  design                                                                                               

  \*Compl fab of 2nd proto   11-Mar-99                15-Aug-99                15-Aug-99               Delay
  substrate                                                                                            

  \*Compl fab of 2nd proto   11-Mar-99                1-Oct-99                 1-Oct-99                Delay
  cable                                                                                                

  \*Compl fab of 2nd proto   11-Mar-99                1-Nov-99                 1-Nov-99                Delay
  fanout                                                                                               

  \*Compl procure of 2nd     11-Mar-99                1-Jul-99                 15-Aug-99               Delay
  proto comps                                                                                          

  \*Compl. 2nd proto         17-May-99                1-Sep-99                 1-Sep-99                Delay
  assembly                                                                                             

  \*1st 2nd proto hybrids    14-Jun-99                1-Sep-99                 1-Sep-99                Delay
  available                                                                                            
  -------------------------- ------------------------ ------------------------ ----------------------- ----------------------

LBNL

1.1.2.2.1 Design

The new hybrid layout for the Cafe-P and ABC chips was completed last
month, checked and sent to the vendor for fabrication. The vendor
requested some small modifications to assist in alignment during
fabrication and we provided these.

1.1.2.2.2 Development and prototype fab

The vendor is fabricating the hybrids and we await shipment.

1.1.2.2.3 Production

No activity.

1.1.2.3 Modules for Silicon Strips(C. Haber)

  ------------------------------ ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}       [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*Preliminary design review    3-Aug-98                 1-Apr-99                 T BD                    Delay

  Complete fabrication of 1st    15-Aug-98                15-Aug-98                                        Done
  dummy modules                                                                                            

  Prototype tooling complete     1-Apr-99                 1-Aug-99                 1-Sep-99                Delay

  \*Compl. Design of proto       14-Jun-99                15-Nov-99                15-Nov-99               Delay
  assy/test                                                                                                

  \*Compl. Fab of tooling for    14-Jun-99                15-Nov-99                15-Nov-99               Delay
  proto                                                                                                    
  ------------------------------ ------------------------ ------------------------ ----------------------- ----------------------

LBNL

1.1.2.3.1 Design of Assembly and Test

New drawings of the assembly fixtures were received from RAL and these
are being reviewed. Design continues on a folding fixture for the
hybrids.

1.1.2.3.2 Development and prototypes

The new calibration plate was submitted for fabrication and received
last month. The plates included optical map data. This data was
presented to us in an unusable form. We have discussed this with the
vendor and they have agreed to re-map the plates. We are currently
evaluating to determine whether a simpler approach to the mapping than
originally specified will be acceptable.

An attempt was made to machine some of the PG for the test of thermal
performance last month but it was unsuccessful. We pursued some
alternate approaches based upon suggestions received from Europe and
last month were able to finally get a good result. This material was
used to produce a full two-sided module for thermal studies. This module
is now ready for preliminary tests.

As part of the ASIC testing program a fully loaded single sided module
was built to test the Cafe-P with old CDP chips. This was built using
the up-to-date construction jigs and methods and bonded with a program
written for the automatic wirebonder. The construction and bonding
exercise was successful.

1.1.2.3.3 Production

No activity.

1.1.3 ReadOut Drivers(R. Jared, A. Lankford)

  ----------------------------- ------------------------ ------------------------ ----------------------- ----------------------
  [Milestones]{.underline}      [Baseline]{.underline}   [Previous]{.underline}   [Current]{.underline}   [Status]{.underline}

  \*Select PreROD               30-Oct-98                26-Mar-99                                        Done
  implementation                                                                                          

  \*Requirements review         30-Nov-98                18-Nov-98                                        Done

  \*Compl. System design        28-Dec-98                15-Jul-99                                        Done

  Compl. SCT ROD simulation     N/A                      7-Jul-99                                         Done

  Compl. Pixel ROD simulation   N/A                      1-Aug-99                 1-Aug-99                OK

  Compl. DSP eval. Setup        N/A                      15-Aug-99                15-Aug-99               OK

  \*System design review        11-Jan-99                20-Aug-99                20-Aug-99               OK

  Compl. Decoder VHDL code      N/A                      1-Oct-99                 1-Oct-99                OK

  Compl. gather VHDL code       N/A                      1-Oct-99                 1-Oct-99                OK

  \*Compl. PreROD layout        15-Feb-99                1-Oct-99                 1-Oct-99                OK

  \*Compl. PreROD procure       1-Mar-99                 1-Oct-99                 1-Oct-99                OK

  \*Compl. PreROD PCB fab       16-Mar-99                15-Oct-99                15-Oct-99               OK

  Compl. Mux VHDL code          N/A                      1-Nov-99                 1-Nov-99                OK

  Compl. Controller VHDL code   N/A                      1-Nov-99                 1-Nov-99                OK

  \*Compl. PreRod Design        29-Jan-99                1-Nov-99                 1-Nov-99                OK

  \*Compl. PreROD 1^st^         30-Mar-99                1-Nov-99                 1-Nov-99                OK
  assembly                                                                                                

  Compl DSP C code              N/A                      1-Dec-99                 1-Dec-99                OK

  Compl. Initial test stand SW  N/A                      1-Dec-99                 1-Dec-99                OK

  \*Compl. protoROD debug/test  9-Jul-99                 1-Feb-00                 1-Feb-00                OK

  PreROds prod. Fab complete    N/A/                     1-Jul-00                 1-Jul-00                OK
  ----------------------------- ------------------------ ------------------------ ----------------------- ----------------------

1.1.3.1.1 Strip Test Beam Support (A. Lankford)

UC Irvine

Hardware and software support for laboratory and beam tests of SCT
electronics and modules is ongoing. Activity in July consisted of
providing technical support to users of systems already in the field.

1.1.3.1.2 Pixel Test Beam Support (R. Jared)

> Minor support effort was supplied in July.

1.1.3.2.1 ROD Requirements (R. Jared)

Contacts have been made with the user community to define and/or justify
the following requirements:

1.  The calibration strobes and triggers will be issued independently to
    a user defined number of front end length. This will allow for
    testing of cross-talk between modules

2.  Capability to dynamic throttling of individual links during data
    taking will not be performed, but the capability will be maintained
    in the ROD design.

3.  The ROD will provide of arbitrary long command lengths to the front
    end modules.

These issues were discussed at the pixel and SCT workshop in Europe.
Initial consensus was reached on many of the requirement issues. It is
expected that September meeting at CERN will provide the concurrence to
start the change procedure of the requirements.

1.1.3.2.2 ROD Essential Model (R. Jared)

The essential model defines the essential functionality of the ROD and
defines the interfaces of the ROD to other functional units. It is
complete, except for refinements that are ongoing during the development
of the implementation model. No refinements of the essential model were
made during June

1.1.3.2.3 ROD Implementation Model (R. Jared)

The architectural definition of the ROD has progressed to the point were
the interfaces between FPGAs is the focus of the effort. As these
interfaces are clarified, coding will commence. The simulation of the
SCT ROD have been essential to this progress.

1.1.3.3.7 Preprototype ROD (R. Jared)

Complete simulation of the SCT ROD data path have been performed. These
simulation show that 96 links will satisfy the bandwidth for an
occupancy the is 2.5 times the TDR occupancy. Simulation of the pixel
RODs is proceeding. There is a need to improve the pixel event
generator. Architectural studies are completed.