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| ![](media/image1.emf){width="0.9770833333333333in"                    |
| height="0.8333333333333334in"} **Fermilab**                           |
|                                                                       |
| **Experiment Electronic Systems Group**                               |
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**DRAFT**

**Specification for**

**Trigger Sum Cable Driver Module**

**(TSCD)**

T. M. Shaw

7/3/95

Revised

8/29/95

1.0 Introduction

A module, the Trigger Sum Cable Driver (TSCD), is required which will
drive \"trigger sums\" on cables received by the DRAW boards being
designed at University of Chicago. These boards will be of a purely
diagnostic purpose - they will be used to test cable, transceiver and
connector integrity. In normal operation, trigger sums will be driven by
the ADMEM boards. The ADMEM boards will incorporate some, but not all of
the diagnostic features included in the TSCD board.

2.0 Features

A block diagram of the board is shown in Figure 1. The board features a
group of eight FIFO blocks which can be read or written over VMEbus. The
board can be put into a special mode which causes the output of the
FIFOs to be driven out to the cable. The FIFO can also be made to cycle
through itself in an endless loop.

Socketed Transceivers - All trigger sum cable drivers will be socketed
so that different types of drivers may be tested. Dip sockets will be
used.

Eight Channels - The board will provide the ability to drive 8 channels
worth of Trigger Sums.

Independent Control - Each of the eight trigger sum paths may be
individually downloaded with a pattern of data 8K deep. Additionally,
each channel may be turned on/off at the driver.

Shield Ground - The cable shield will be optionally grounded to the
board through a jumper.

Clock Source - The onboard clock can be derived from an internal
oscillator or from the backplane of the CDF Custom Crate.

3.0 Cable/Connector Pinout of Trigger Sum Cables

Pin Signal Pin Signal

1 A(0) 2 A\*(0)

3 A(1) 4 A\*(1)

5 A(2) 6 A\*(2)

7 A(3) 8 A\*(3)

9 A(4) 10 A\*(4)

11 A(5) 12 A\*(5)

13 A(6) 14 A\*(6)

15 A(7) 16 A\*(7)

17 A(8) 18 A\*(8)

19 A(9) 20 A\*(9)

4.0 VME Slave Interface

The TSCD will implement a modified version of a VMEbus slave interface.
Only 32 bit aligned data transfers will be supported; these may be
either single word transfers or block transfers. Only extended (32-bit)
addressing modes will be supported. All boards will be assigned a unique
geographical address through use of backplane pins on the CDF Custom J2
backplane. TSCD modules will respond to the following address modifier
codes: 09, and 0B.

![](media/image2.emf){width="5.271527777777778in"
height="7.175694444444445in"}

**Memory Map**

YY00 0000 Diagnostic Register (32 bit Read/Write)

YY00 0004 Control (default state of all bits is zero)

**[Bit]{.underline}** **[Function]{.underline}**

0-29 Undefined

30 CLK_ON ; =1 will use internal ocsillator

31 Software Reset ; =1 will issue software Reset

YY00 0008 FIFO Control Register

**[Bit]{.underline}** **[Function]{.underline}**

0 FIFO 0 Reset ; = 1 will cause FIFO to reset

1 FIFO 1 Reset

1 FIFO 2 Reset

3 FIFO 3 Reset

4 FIFO 4 Reset

5 FIFO 5 Reset

6 FIFO 6 Reset

7 FIFO 7 Reset

8 Enable TrigSum 0 ; =1 will enable TrigSum drivers

9 Enable TrigSum 1

10 Enable TrigSum 2

11 Enable TrigSum 3

12 Enable TrigSum 4

13 Enable TrigSum 5

14 Enable TrigSum 6

15 Enable TrigSum 7

16 Enable FIFO Loop 0 ; = 1 will cause FIFO to Loop on empty

17 Enable FIFO Loop 1 state when DIAG_ON is enabled

18 Enable FIFO Loop 2

19 Enable FIFO Loop 3

20 Enable FIFO Loop 4

21 Enable FIFO Loop 5

22 Enable FIFO Loop 6

23 Enable FIFO Loop 7

24 DIAG_ON 0 ; = 1 will cause FIFOs to empty contents

25 DIAG_ON 1 to Trigger Sum Drivers(no VME access)

26 DIAG_ON 2 = 0 will allow VME access

27 DIAG_ON 3

28 DIAG_ON 4

29 DIAG_ON 5

30 DIAG_ON 6

31 DIAG_ON 7

YY00 000C Status Register

**[Bit]{.underline}** **[Function]{.underline}**

0 FIFO 0 HF\*

1 FIFO 0 EF\*

2 FIFO 0 PAFE\*

3 Undefined

4 FIFO 1 HF\*

5 FIFO 1 EF\*

6 FIFO 1 PAFE\*

7 Undefined

8 FIFO 2 HF\*

9 FIFO 2 EF\*

10 FIFO 2 PAFE\*

11 Undefined

12 FIFO 3 HF\*

13 FIFO 3 EF\*

14 FIFO 3 PAFE\*

15 Undefined

16 FIFO 4 HF\*

17 FIFO 4 EF\*

18 FIFO 4 PAFE\*

19 Undefined

20 FIFO 5 HF\*

21 FIFO 5 EF\*

22 FIFO 5 PAFE\*

23 Undefined

24 FIFO 6 HF\*

25 FIFO 6 EF\*

26 FIFO 6 PAFE\*

27 Undefined

28 FIFO 7 HF\*

29 FIFO 7 EF\*

30 FIFO 7 PAFE\*

31 Undefined

YY10 0020 - YY10 009C ID PROM (upper 8 bits)

YY20 0000 - YY20 7FFF FIFO 0

YY21 0000 - YY21 7FFF FIFO 1

YY22 0000 - YY22 7FFF FIFO 2

YY23 0000 - YY23 7FFF FIFO 3

YY24 0000 - YY24 7FFF FIFO 4

YY25 0000 - YY25 7FFF FIFO 5

YY26 0000 - YY26 7FFF FIFO 6

YY27 0000 - YY27 7FFF FIFO 7

**YY** is the VME geographical address of the TSCD.

Sample program flow to turn on Trigger Sum outputs

write 0x40000000 to register 0x4 ; turns on clock (assumes no backplane
clock)

write 0xFF to register 0x8

write 0x0 to register 0x8 ; resets all FIFOs

block write to register 0x200000

block write to register 0x210000

block write to register 0x220000

block write to register 0x230000

block write to register 0x240000

block write to register 0x250000

block write to register 0x260000

block write to register 0x270000 ; write to all FIFOs

write 0x00FFFF00 to register 0x8 ; turn on looping mode and enable
drivers

write 0xFFFFFF00 to register 0x8 ; start transmission

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height="8.474305555555556in"}