![](media/image1.emf){width="5.722222222222222in"
height="0.9444444444444444in"}

**SVX II Silicon Strip Detector Upgrade Project**

**Dense Optical Interface Module (DOIM)**

**\--PRELIMINARY\--**

March, 1996

Minglee Chu, Maotung Cheng, Yi-Cheng Liu

**Academia Sinica**

1.  GENERAL INFORMATION [1](#general-information)

    FUNCTION AND INTERFACE OF DOIM TO SVXII [1](#_Ref354825946)

    0.  Functional Description of the DOIM
        [2](#functional-description-of-the-doim)

        The Interface of DOIMs to SVXII system [4](#section)

        Basic Requirements of DOIM [5](#basic-requirements-of-doim)

    SPECIFICATIONS [6](#specifications)

    0.  Packaging, Physical Size and Material
        [6](#packaging-physical-size-and-material)

        Pin Configurations and Signal Description
        [8](#pin-configurations-and-signal-description)

        Electrical I/O Levels [11](#electrical-io-levels)

        Electrical Specifications [11](#electrical-specifications)

        Power Requirements [13](#power-requirements)

        Cooling Requirements [14](#cooling-requirements)

        Environmental Requirements [14](#environmental-requirements)

    OPTICAL POWER BUDGET [15](#optical-power-budget)

    QALITY ASSURANCE PROCEDURES [15](#qality-assurance-procedures)

    0.  Quality Control Procedures in Production
        [16](#quality-control-procedures-in-production)

        Quality Assurance before Installation
        [18](#quality-assurance-before-installation)

    REFERENCES: [19](#references)

APPENDIX A A-1

#  GENERAL INFORMATION

The Dense Optical Interface Module (DOIM) is a parallel byte-wide
(w/clock) optical link used to transfer data from the **Port Card \[\]**
of SVXII detector to the **Fiber Interface Board**s (**FIB**)\[\]. It
replaces the conventional copper wires with optical fibers as the major
data transmission medium due to its high bandwidth and EMI immunity.
With the high luminosity and short bunch spacing in RUN II of Tevatron,
the data rate is expected to be very large in the silicon vertex
detector. The data transmission rate must be high enough to be ready for
the level two triggers. Fiber optical technology has the benefit of high
speed, however, the commercially available connection scheme do not meet
the space limitation in SVXII environment. Therefore, a custom
interconnection scheme has to be developed. The purpose of this document
is to provide sufficient information for circuit designers to interface
with the DOIM. Refer to the Appendices for the internal details of the
DOIMs.[]{#_Ref354825946 .anchor}

#  FUNCTION AND INTERFACE OF DOIM TO SVXII

The function of DOIM is to replace the standard multi-channel line
driver and receiver pairs by utilizing fiber optical technology. From a
circuit designer point of view, there is little or no difference
between using DOIM or a standard driver-receiver pair, except that DOIM
sends data through optical fiber with optical signal and DOIM is capable
of operating at higher data rates and the copper has been replaced with
optical fibers.

##  Functional Description of the DOIM

There are two modules making up one DOIM pair, one **Transmitter Module
(TX),** and one **Receiver Module(RX)**. Each TX and RX pair have nine
identical channels. With externally defined 8-bit data channels and one
bit clock channel, one pair of DOIM TX-RX provides one byte parallel
transmitter and receiver pair.

The function of the TX is to accept nine independent digital electrical
signals, and convert the electrical ighor owsignals to optical nand
ffsignals. The function of the RX is to accept the nine channels of
optical signals from remote TX, then convert the optical signals back to
electrical signals.

Each module of the DOIM TX and RX consist of a hybrid package and a
short optical ribbon fiber pigtail. The electrical contacts to the
exterior of the modules are made with metal traces on the ceramic
substrate for wire-bonding. The ribbon pigtail is the optical
output(input) of TX(RX). The other end of the pigtail is terminated with
standard MT type connector. The package of the TX module contains a
custom chip and a **Laser Diode Array (LDA)**. The chip internal to the
TX accepts the electrical digital signals from other circuit outside TX
and translates them to the proper current level to drive each LD in the
LDA. The optical outputs from LDA are then coupled to the fiber ribbon
output pigtail.

Internal to the package of RX, there is a custom receiver chip and a
**Photo Diode Array (PDA)**. The optical signals were fed into RX
through a fiber ribbon pigtail. Each channel of the fiber ribbon is
aligned with each PD of the PDA. The custom chip of the RX amplifies and
digitizes the small current signals from PDs of PDA. The electrical
output of the RX is standard digital differential ECL signals.

To provide complete data transmission link over a distance greater than
few meters to a few ten of meters, fiber ribbon with MT connectors on
both ends as interconnection are required. Figure 2-1 shows the idea of
a complete data link implementing a DOIM TX-RX pair.

![](media/image2.emf){width="6.027777777777778in"
height="8.041666666666666in"}

**Figure 2-1** Block diagram of one byte DOIM data link

##   

## The Interface of DOIMs to SVXII system

The TX will be implemented on the port card which is mounted at the edge
of the SVXII barrels. The TX receives the digital input signal from the
data bus of port card. The design of port card provide **Low Current
differential signal (LCDS) \[\]** digital signals to the TX. The RX will
be implemented on the Fiber Interface Boards (FIB) which is mounted
outside the detector. The output of DOIM RX is differential ECL signals
to FIB.

There will be five DOIM TXs on each port card. In the current design of
SVXII, there are three barrels with 12 wedges per barrel and 2 port
cards per wedge. The total number of DOIMs needed for the SVXII project
is 360 pairs (spares are not included).

##  Basic Requirements of DOIM 

As a digital data transfer device, it was essential to perform data
transfer in designated data rate with reasonable low **Bit Error Rate
(BER).** The requirements for the SVXII upgrade requires that the DOIMs
operate at a data rate of 53Mbyte/sec/DOIM. Since the DOIM is designed
for parallel data transfers, special care should be taken on the signal
switching characteristic as well as the matching of timing between
channels of the DOIM.

Other than the electrical and optical properties, radiation hardness,
high density package, low total mass and low power dissipation is
essential for TX to be used inside collider detector. A radiation
hardness of 200 Krad is estimated to be sufficient for the RUNII
experiment. As for the package size, mass and power dissipation, it is
asked to be as small as reasonably possible .

#  SPECIFICATIONS

Both the DOIM TX and RX should be viewed as a device from a circuit
designer point of view. The format of data I/O is straightforward.
However, the requirement of minimizing the package size implies
non-standard pin configuration and special circuit board placement
methods. Additional precautions should also be taken for the optical
nature of the transmission medium during the handling and testing of
DOIMs.

##  Packaging, Physical Size and Material

Figure 3-1 gives the outline and dimensions of TX as well as RX. The
package size of DOIM are 18mm x 8mm x 3.5mm and 15mm x 8mm x 3.5mm for
TX and RX, respectively. The pitch of the I/O pins are 350um Both for TX
and RX. (Refer to Appendix for details)

There are four plastic nuts on the bottom of the substrate for both the
TX and the RX. It is required to have holes on the port card and the FIB
to provide good thermal contact between the port card/FIB and the DOIM
substrate. The location of and minimum hole size are as shown in Figure
3-1 .

Table 3-1 lists the material used in DOIM.

![](media/image3.emf){width="6.135416666666667in"
height="5.7347222222222225in"}

> **Figure 3-1** Outline and dimensions of DOIM and the example of the
> hole on the port card and FIB to accept the nut of TX and RX
> respectively. The black shapes represent the corners of DOIM on
> circuit board. The half circles are the minimum holes required to
> accept the nuts of DOIM.( unit : μm )

+-------------------+-----------+-----------------+-------------------+
| Components        | Material  | Dimensions (in  |                   |
|                   |           | mm)             |                   |
+-------------------+-----------+-----------------+-------------------+
|                   |           | TX              | RX                |
+-------------------+-----------+-----------------+-------------------+
| Substrate         | > BeO or  | 18 x 8 x 0.5    | 15 x 8 x 0.5      |
|                   | >         |                 |                   |
|                   | Al~2~O~3~ |                 |                   |
+-------------------+-----------+-----------------+-------------------+
| Submount          | > BeO or  | 4.5 x 4 x 0.3   | 6.2 x 2 x 1.5     |
|                   | >         |                 |                   |
|                   | Al~2~O~3~ |                 |                   |
+-------------------+-----------+-----------------+-------------------+
| Si groove        | > Si      | 4.5 x 4 x 1     |                   |
+-------------------+-----------+-----------------+-------------------+
| O/E,E/O chip      | > GaAs    | 3.5 x 0.3 x 0.3 | 3.5 x 0.3 x 0.3   |
+-------------------+-----------+-----------------+-------------------+
| IC chip           | > Si or   | 3.5 x 2 x 0.3   | 3.5 x 2 x 0.3     |
|                   | > GaAs    |                 |                   |
+-------------------+-----------+-----------------+-------------------+
| Cover             | > Plastic | outline:        | > outline:        |
|                   | >         |                 |                   |
|                   | > (Epoxy) | 5.  x 8 x 0.5   | 5.  x 8 x 0.5     |
|                   |           |                 |                   |
|                   |           | > wall          | > wall thickness: |
|                   |           | > thickness:    | >                 |
|                   |           | >               | > \~ 1            |
|                   |           | > \~ 1          |                   |
+-------------------+-----------+-----------------+-------------------+

**Table 3-1** Materials of DOIM ( fiber ribbon and connector not
included)

##  Pin Configurations and Signal Description

Figure 3-2 and Table 3-2 shows the pin out of both the TX and the RX of
DOIM. The I~1p~, I~1n~ to I~9p~, I~9n~ [^1] pins are the digital inputs
of the TX. The Npin is the enable control which serve the purpose of
saving power by turning off all LDs while data transmission is not
needed. The O~1p~,O~1n~ to O~9p~, O~9n~ pins are the digital outputs of
the RX.

The electrical connection of the DOIM TX or RX to printed circuit board
of the port card or FIB should be wire-bonded. The thin film gold metal
on the bottom side of DOIM is connected to V~ee~ internally for both TX
and RX.

![](media/image4.emf){width="4.652777777777778in"
height="2.4770833333333333in"}

**Figure 3-2** Pin out of DOIM TX and RX.

+-----+------+----------------------------+--------+-------------------+
|     | **T  |                            | **Rece |                   |
|     | rans |                            | iver** |                   |
|     | mitt |                            |        |                   |
|     | er** |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **  | *    | > **description**          | **pin  | > **description** |
| Pin | *pin |                            | name** |                   |
| \   | na   |                            |        |                   |
| #** | me** |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **  | V    | > ground                   | V~ee~  | > ground          |
| 1** | ~ee~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **  | en   | > enable/disable LDA       | V~ee~  | > ground          |
| 2** | able |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **  | I    | > 1st channel input        | O~1p~  | > 1st channel out |
| 3** | ~1p~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **  | I    | > 1st channel input        | O~1n~  | > 1st channel ut |
| 4** | ~1n~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **  | I    | > 2nd channel input        | O~2p~  | > 2nd channel out |
| 5** | ~2p~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **  | I    | > 2nd channel input        | O~2n~  | > 2nd channel out |
| 6** | ~2n~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **  | I    | > 3rd channel input        | O~3p~  | > 3rd channel out |
| 7** | ~3p~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **  | I    | > 3rd channel input        | O~3n~  | > 3rd channel ut |
| 8** | ~3n~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **  | I    | > 4th channel input        | O~4p~  | > 4th channel out |
| 9** | ~4p~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **1 | I    | > 4th channel input        | O~4n~  | > 4th channel out |
| 0** | ~4n~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **1 | I    | > 5th channel input        | O~5p~  | > 5th channel out |
| 1** | ~5p~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **1 | I    | > 5th channel input        | O~5n~  | > 5th channel ut |
| 2** | ~5n~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **1 | I    | > 6th channel input        | O~6p~  | > 6th channel out |
| 3** | ~6p~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **1 | I    | > 6th channel input        | O~6n~  | > 6th channel out |
| 4** | ~6n~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **1 | I    | > 7th channel input        | O~7p~  | > 7th channel out |
| 5** | ~7p~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **1 | I    | > 7th channel input        | O~7n~  | > 7th channel ut |
| 6** | ~7n~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **1 | I    | > 8th channel input        | O~8p~  | > 8th channel out |
| 7** | ~8p~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **1 | I    | > 8th channel input        | O~8n~  | > 8th channel out |
| 8** | ~8n~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **1 | I    | > 9th channel input        | O~9p~  | > 9th channel out |
| 9** | ~9p~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **2 | I    | > 9th channel input        | O~9n~  | > 9th channel out |
| 0** | ~9n~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **2 | V    | > +5V supply               | V~cc~  | > \+ 5V supply    |
| 1** | ~cc~ |                            |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **2 | V    | > power supply connect to  | V~ee~  | > ground          |
| 2** | ~ld~ | > the common cathode of    |        |                   |
|     |      | > LDA                      |        |                   |
+-----+------+----------------------------+--------+-------------------+
| **2 | V    | > power supply connect to  | V~ee~  | > ground          |
| 3** | ~ld~ | > the common cathode of    |        |                   |
|     |      | > LDA                      |        |                   |
+-----+------+----------------------------+--------+-------------------+

**Table 3-2** The pin name and functional description of DOIM

##  Electrical I/O Levels

**[Transmitter]{.underline}**

Each input of DOIM TX accepts differential voltage signals, with a
voltage difference (V~di~=\|V(I~ip~)- V(I~in~)\|) greater than 100mV.
DOIM TXs interpret V~dx~ \> +100mV as a logical high and V~di~ \< -
100mV as a logical low. Together with the termination resistor on the
port card, the input of the TX complies with the required LCDS interface
protocol.

The active low enable pin accept standard TTL level signals.

**[Receiver]{.underline}**

The outputs of the RX are compatible with differential ECL. As standard
ECL devices, the output can be configured as positive ECL or negative
ECL depending on the power supply configuration. By connecting +5V to
V~cc~ and ground to V~ee~ the outputs are positive ECL. By connecting
ground to V~cc~ and -5V to V~ee~ the outputs become standard ECL.

##  Electrical Specifications

Table 3-3 lists the electrical specification of DOIM.

+------------------------------------+---------------------------------+
| > Common to TX and RX , over       |                                 |
| > operating temperature range      |                                 |
+------------------------------------+---------------------------------+
| > nominal data rate                | > 53Mbytes/sec                  |
+------------------------------------+---------------------------------+
| > bit error rate                   | > \< 10^-12^                    |
+------------------------------------+---------------------------------+
| > skew between each channel        | > \< 0.5ns                      |
| >                                  |                                 |
| > (from the input of TX to output  |                                 |
| > of RX, including the optical     |                                 |
| > cable)                           |                                 |
+------------------------------------+---------------------------------+
| > timing jitter                    | > \< 0.5ns                      |
| >                                  |                                 |
| > (from the input of TX to output  |                                 |
| > of RX)                           |                                 |
+------------------------------------+---------------------------------+
| > RX output duty cycle range of    | > 45 to 55 %                    |
| > each channel                     |                                 |
| >                                  |                                 |
| > (with 26.5Mhz, 50% duty cycle    |                                 |
| > input from TX)                   |                                 |
+------------------------------------+---------------------------------+
| > operating temperature range      | > -10to 35                      |
| > (substrate)                      |                                 |
+------------------------------------+---------------------------------+

**Table 3.3a** Common specifications of DOIM

+-----------------------------------+-----------------------------------+
| > DOIM Transmitter (TX)           |                                   |
+-----------------------------------+-----------------------------------+
| > input protocol                  | > digital LCDS (differential      |
|                                   | > voltage resulting with external |
|                                   | > termination resistor should be  |
|                                   | > greater than 100mV)             |
+-----------------------------------+-----------------------------------+
| > input switching characteristic  | > t~r~, t~f~ \<2ns                |
+-----------------------------------+-----------------------------------+
| > Optical wavelength              | > 1550mm (10 mm)                  |
+-----------------------------------+-----------------------------------+
| > optical output power            | > \> 200μW/channel, on^\*^        |
| >                                 | >                                 |
| > (output from pigtail)           | > \< 800μW/channel, on^\*\*^      |
|                                   | >                                 |
|                                   | > \< 10μW/channel, off            |
+-----------------------------------+-----------------------------------+
| > optical switching               | > t~r~, t~f~ \<2ns ( time between |
| > characteristic                  | > 10μW and 200μW)                 |
+-----------------------------------+-----------------------------------+
| > enable control signal           | > low active, TTL                 |
+-----------------------------------+-----------------------------------+
| > Power supply                    | > 5V(0.5V ) and an additional     |
|                                   | > voltage sinker with voltage     |
|                                   | > V~cc~-3V(0.5V). See next        |
|                                   | > section for details             |
+-----------------------------------+-----------------------------------+
| > Power dissipation               | > \< 2W/TX (total)                |
|                                   | >                                 |
|                                   | > \< 1W to turn all LDs on,       |
|                                   | >                                 |
|                                   | > 1W constant for other circuit   |
|                                   | > elements                        |
+-----------------------------------+-----------------------------------+
| > Radiation hardness              | > \> 500Krad^\*^                  |
+-----------------------------------+-----------------------------------+
| > Package dimension (not          | > 18mm x 8mm x 3.5mm              |
| > including pigtail)              |                                   |
+-----------------------------------+-----------------------------------+

^\*^ 200μW/channel optical power is for non-irradiated TXs. After
500Krad accepted the output power may degrade but should still be
greater than 100μW.

^\*\*^ Maximum output power of TX is required to keep the RX from being
saturated.

**Table 3.3b** Specifications of TX

+-----------------------------------+-----------------------------------+
| > DOIM Receiver (RX)              |                                   |
+-----------------------------------+-----------------------------------+
| > input sensitivity range         | > \>50μW(1550mm) for digital      |
| >                                 | >                                 |
| > (input from optical link)       | > usable up to 800μW              |
|                                   | >                                 |
|                                   | > \<10μW for digital '            |
+-----------------------------------+-----------------------------------+
| > Output protocol                 | > differential ECL                |
+-----------------------------------+-----------------------------------+
| > output switching characteristic | > t~r~, t~f~ \<2.5ns ( with 20%   |
|                                   | > and 80 % between high and low)  |
+-----------------------------------+-----------------------------------+
| > Power supply                    | > 5V(0.5V )                       |
+-----------------------------------+-----------------------------------+
| > Power dissipation               | \<1.1W/RX, internal, constant     |
|                                   |                                   |
|                                   | \~0.9W/RX, external, constant     |
|                                   | \*\*                              |
+-----------------------------------+-----------------------------------+
| > Package dimension (not          | > 15mm x 8mm x 3.5mm              |
| > including pigtail)              |                                   |
+-----------------------------------+-----------------------------------+

> \* The input sensitivity varies smoothly within the wavelength range
> from 1550mm to 1300mm. The input power requirement increase about 1.3
> times if input wavelength is 1300mm.
>
> \*\* Assuming 390Ω pull down to ground resistor connected to all
> outputs.

**Table 3-3c** Specifications of and RX

##  Power Requirements

**[Transmitter]{.underline}**

There are 3 pins for the power connection, V~cc~, V~ee~ and V~LD~ .
V~cc~ and V~ee~ should be connected to 5V(0.5V ) and ground,
respectively. The V~LD~ pin is the common to the cathodes of the laser
diode arrays (LDA)s internal to the TX. V~LD~ should be connected to a
precise, adjustable supply which can sink current at voltage about -3V
referenced from V~cc~, as in Figure 3-3 . It is important to keep V~LD~
referenced to V~cc~ in order to keep the driving current to LDA stable.
The constant voltage current sinker at V~LD~ is required to sink up to
300mA per TX (with all the LDs are turned on). The voltage of the V~LD~
controls the output optical power of the LDs. The adjustable range will
be decided later, 0.5V should be sufficient.

![](media/image5.emf){width="1.6666666666666667in" height="1.125in"}

**Figure 3-3** Power supply connection of TX.

**[Receiver]{.underline}**

The power supply for the RX is V~cc~ - V~ee~ = 5V(0.5V ). It is helpful
to use another 3V supply (referenced from V~ee~ ) to reduce external
power dissipation on the pull down resistor. In the case of dual supply,
50Ω to 100Ω of pull down resistors are recommended.

##  Cooling Requirements

The output power of the Laser Diode is quite sensitive to the
temperature. Although the specified operation temperature range is
between -10 to 35, good thermal conduction and cooling is recommended
for the TXs to keep the substrate temperature within the range from 0 to
20. The RXs will operate at less stringent conditions.

##  Environmental Requirements

The dimension and material requirements of DOIM pose the limit that DOIM
can not be hermetically sealed. The opto-electronic devices inside DOIM
are sensitive to humidity. Controlled humidity environment is required
in any time to keep DOIM from damage. It is also suggested that care be
taken with the temperature difference between DOIM and ambient
(especially when in higher ambient temperature while DOIM itself is
cold) to prevent water vapor condensation on the surface of
opto-electronic device.

#  OPTICAL POWER BUDGET

Optical output level of TX and the sensitivity of RX is the most
important factor to keep DOIM link operate. According to the preliminary
study, we know that optical fiber is the only non-radhard component in
the DOIM data link. With about 50Krad of dosage accepted by standard
glass fiber, the transmission lost is as much as 30% to 50%. Table 4-1
lists the optical power budget for DOIM, based on the assumption that
the radiation induced lost is within 50%, from TX to RX. Refer to the
Appendix for the radiation properties of the components of DOIM.

+---------------------------+--------------------+--------------------+
|                           | > Fresh            | > End of RUNII     |
+---------------------------+--------------------+--------------------+
| > Output from TX pigtail  | > 200 μW to 800 μW | > 100 μW to 400 μW |
+---------------------------+--------------------+--------------------+
| > Coupling efficency      | > \>70 %           |                    |
| >                         |                    |                    |
| > (2 MT to MT connection) |                    |                    |
+---------------------------+--------------------+--------------------+
| > Coupled to RX           | > 140 μW to 560 μW | > 70 μW to 280 μW  |
+---------------------------+--------------------+--------------------+
| > Input high threshold of | > \<50μW           |                    |
| > RX                      |                    |                    |
+---------------------------+--------------------+--------------------+
| > Max. Input power of RX  | > 800μW            |                    |
+---------------------------+--------------------+--------------------+
| > Threshold power Margin  | > \>90 μW          | > \> 20 μW         |
| > of RX                   |                    |                    |
+---------------------------+--------------------+--------------------+

**Table 4-1** Optical power budget of DOIM link

#  QALITY ASSURANCE PROCEDURES

Quality assurance will be achieved by performing tests on each
sub-component as well as on the completed packages of DOIM while in
production. Double-check are also scheduled to be performed in Fermilab
before installing on port card/FIB.

##  Quality Control Procedures in Production

Figure 5-1 explain the flow chart of the assembling process of DOIM.
Dashed blocks indicate the tests which will be performed .The tests of
the LDA/PDA on the sub-mounts and the test of chips on the substrates
serve the purpose for selecting good semiconductor devices. DC
performance tests before and after burn-in on sub-component level are
usually enough to give component to pick out most failed devices.

After the DOIMs have been produced, a series of tests will be performed.
Table 5-1 is the list of these tests. Note that some tests such as
BER\[\] and reliability(lifetime) will be performed only by sampling for
practical reasons. Only the DOIMs which pass all the tests after burn-in
will be shipped to Fermilab.

![](media/image6.emf){width="5.625in" height="7.180555555555555in"}

**Figure 5-1** The Assembly Process of DOIM

(refer to the appendix for the detail inside DOIM)

##  

## Quality Assurance before Installation

The packaged DOIM modules will go through component-level testing and
quality control as described in the previous section. After the shipment
to Fermilab, a final stage testing should be carried out to ensure that
quality of DOIM is within the specification. Since all the DOIMs should
have gone through all the tests and give reasonable degradation
comparisons before and after burn-in, the double-checks in Fermilab
should be enough to confirm the reliability of them. Basically, one can
do all the tests listed in Table 5-1 to confirm the qualities. Follow
the priority recommendations in the last column of Table 5-1 to arrange
the testing procedures. Small quantity burn-in and reliability tests can
also be done in Fermilab.

DC tests

Input voltage threshold (TX) \*

Output optical power (TX) \*\*\*

Input optical power range (RX) \*

Output voltage level (RX) \*

Supply voltage range (TX,RX) s+,\*

Supply current (TX,RX) s+,\*

Power dissipation (TX,RX) s-,\*

AC tests

Optical switching characteristics (TX) \*\*

Optical skew (TX) s+,\*

Optical jitter (TX) s+,\*

Electrical switching characteristics (RX) \*\*

Electrical skew (RX) \*

Electrical jitter (RX) \*

Duty cycle (TX+RX) s-

BER (TX+RX, sampling) s-,\*\*\*

> Note. Input/Output level DC tests will be performed before and after
> burn-in. All other tests will be performed only after burn-in.
>
> Last column is the recommendation on the tests in fermilab
>
> s test by sampling only, +/- means more/less percentage of sampling
> recommended
>
> \* test in Fermilab recommendations, more \* means more care should be
> taken for the test.
>
> **Table 5-1** list of the tests which will be performed before
> shipping.
>
> ( the last column is the note to suggest the double check tests in
> Fermilab. )

#  REFERENCES:

> \[\] J. Andresen, K. Treptow, S. Zimmermann \-- **Port Card for the
> SVXIII Chip (1995).**
>
> \[\] K. Woodbury \-- **Fiber Interface Board (1995).**
>
> \[\] E. Barsotti, S. Zimmermann **Low Current Differential Signal,**
> ESE-SVX-950605 (1995)
>
> \[\] D. Husby \-- **BERT, Bit Error Rate Tester (1995). (** Note : The
> outputs of the current version of BERT is not LCDS, level-conversion
> adapter board is required for testing the DOIM TXs. )

[^1]: I~ip~ ( I~in~ ) means the positive (negative ) input pin of the
    i-th channel.