**Titl*e:* Reliability Assessment of Microvias for Spaceborne
Electronics**

**(Check one):** New Proposal Continuing NEPP Work

##### Total \$ Requested for FY02: \$120,000 

**Technology Type:** Newly Available (COTS) Emerging/Advanced

**(check one)**

**Project Area:** Parts Packaging Radiation

**(check one)**

**Proposing Centers:** JPL

**([Estimated]{.underline} Center** % GSFC % GRC % LaRC 100 % JPL

**Participation, %\$):** % MSFC % JSC Other

**Collaborators (include %\$, if any, to collaborators):** 50% JHU/APL

**Point of Contact:** Mr. David Mih, (818-354-9218),
[david.t.mih@jpl.nasa.gov](../david.t.mih@jpl.nasa.gov)

**Investigator(s):** Mr. David Mih (NASA/JPL), (818-354-9218),
[david.t.mih@jpl.nasa.gov](../david.t.mih@jpl.nasa.gov)

Mr. Binh Le (JHU/APL), (240-228-4711),
[binh.le@jhuapl.edu](../binh.le@jhuapl.edu)

Dr. Sharon Ling (JHU/APL), (240-228-8139),
[sharon.ling@jhuapl.edu](../sharon.ling@jhuapl.edu)

> Objective(s):

-   Design and fabricate test boards with microvias (buried and blind
    vias), leveraged from commercial technologies.

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-   Perform microsection evaluation on printed wiring board test coupons
    to form a referenced basis for the reliability study.

-   Perform temperature cycling test (MIL standard temperatures and
    extended temperature range to support missions to Mars).

-   Implement non-destructive evaluation (NDE) methods to evaluate the
    integrity of the microvias before and after thermal cycling tests.

-   Perform finite element analyses to correlate test results and NDE
    for reliability prediction.

-   Establish guidelines for reliable, cost-effective microvias design
    and fabrication procedures that can be verified through standard
    test coupon verification.

**Task Description:**

The team of NASA/JPL and the Johns Hopkins University Applied Physics
Laboratory (JHU/APL) proposes to evaluate the reliability of microvia
technology (buried and blind vias) in high density printed wiring board
(PWB) design. We will also define criterion for reliable microvia PWB
design standards and reliability testing procedures. This project
leverages from previous NASA ATD project conducted at JHU/APL. To be
more focused and effective, we will evaluate microvias in the
conventional PWBs with etch-back process only, since this process has
been typically applied in space electronics. The task will also employ
novel NDE techniques to inspect microvia PWB, and analytical approaches
to acquire in-depth understanding of microvia behavior in temperature
cycling environment as well as to predict the reliability of microvias.

### Task Approach to meeting NEPP Objectives: 

### The work proposed in this project meet the NEPP program objectives in many areas:

### 

### *Assessing Reliability:* As PWB hole sizes are getting smaller, maintaining the minimum copper wall thickness of 0.001 inch (as required by the MIL standards) becomes very difficult, especially for high-aspect-ratio vias. The question of whether the integrity of the vias relies on the copper plating thickness or the interface between the plated vias and the inner layer annular rings, is still the subject for many research projects. To understand the characteristics and performances of the microvias developed by different manufacturing processes, a fundamental test plan is developed in this project on specific PWB technology for the reliability assessment of microvia for future space application. This project will also assess the reliability of PWB technology with microvias for temperature ranges beyond the typical MIL standard requirements, where no data are available from commercial companies, yet a situation that will be encountered for future space missions to Mars. 

### *Expediting Infusion Paths:* Microvia technology has been used in commercial products to support miniaturized consumer electronics. However, the reliability of the microvia technology needs to be thoroughly and carefully studied before implementation for space electronics. Once the behavior of the microvias is quantified, and reliability qualified, we will then work with future NASA programs to leverage from this existing technology and to ensure that it is available for infusion into space programs.

###  

### *Provide Validation Guidelines:* One of the goals of this project is to establish criterion for validation PWB with microvias. Existing MIL standards do not address the microvia issues, and the commercial IPC standards do not have definitive requirements and convincing test data to support microvias for high reliability application. Upon completion of this project, we will provide guidelines on the minimum plating thickness and minimum via size requirements, as well as tools to predict life expectancy for microvias in space application.

> *[Disseminating Information to]{.underline}*
>
> *[the NASA Community:]{.underline}* The results from this study will
> be disseminated to the NASA community via NEPP publications, the NASA
> Tech-Digest, and publications in technical journals. We will actively
> participate and inform the two on-going programs: X2000 and MESSENGER
> on the status of this technology for potential technology insertion.

## 

> Technical Background:
>
> Miniaturization in consumer electronics has resulted in implementation
> of small electronic components in the form of flip chip,
> micro-ball-grid array, and chip-scale surface-mount packages. To
> support the miniaturized electronic systems, innovative PWB
> technologies with microvias and very fine feature were developed. The
> typical microvia-hole diameters range from 0.002 inch to 0.008 inch.
> These vias are divided into three categories: blind, buried and
> through-hole. Blind vias provide interconnections from the external
> signal layer to an internal one; whereas buried vias interconnect only
> among internal signal layers. Both the blind and buried vias can
> effectively divert signals from high I/O density ICs for routing
> without compromising significant board surface area. In conventional
> PWB fabrication process, mechanical drilling is used when via size is
> greater than 0.010 inch. For smaller holes, laser-drilling processes
> are required.
>
> Two laser-drilling processes: conformal-mask drilling and full-via
> formation drilling will be evaluated in this project. In the
> conformal-mask drilling method, the external copper is chemically
> pre-etched using a photolithographic process to expose the dielectric
> layer. A CO~2~ laser beam is then focused onto the surface of the PWB
> to ablate the dielectric material thus, form the via. A post drill
> clean with plasma or chemical etching prior to electroless copper
> plating is required for conformal-mask drilling, to ensure a clean
> surface for subsequent plating steps. Full-via formation drilling
> process uses dual laser sources, the UV laser and the CO~2~ laser. The
> UV laser source is used for ablating the copper layer, and the CO~2~
> laser is used subsequently to ablate the dielectric material to form
> the vias. A post-drill clean prior to the electroless copper plating
> is also required. The potential advantage of the full-via formation
> drilling process is the elimination of the tedious inspection step
> that is needed in conformal-mask drilling process, to ensure proper
> removal of copper before the laser drilling step. A critical step in
> high quality microvia fabrication is the electroless copper deposition
> after the drilling and cleaning of via holes. Two plating processes
> will be evaluated in this study: the conventional DC plating process
> and the pulsed plating process. In the pulsed plating process, the
> supplied electrical input is turned on and off repetitively with
> adjustable duty cycle and frequency. The agitated/regulated current
> induces more evenly ion distribution, which leads to better Cu ion
> deposition and plating quality, especially for blind holes with high
> aspect ratios.

## 

> Defining systematic design procedures and inspection guidelines for
> reliable printed wiring boards with microvias will provide important
> building blocks for satellite electronics miniaturization.
> Understanding the performance of microvias and limitation of
> manufacturing processes will avoid problems in making design decisions
> (Figs. 1). The trend in PWB fabrication is more towards
> manufacturability than qualification, especially when MIL standards
> are in the process of being replaced by commercial IPC standards
> \[1,2\]. Problems could occur when the PWB coupon does not represent
> the board features, and successful inspection of the coupon does not
> necessarily guarantee the quality of the board. A good example of the
> non-representative coupon inspection failing to reveal PWB process
> problem is the CHANDRA spacecraft \[3\]. The PWB failure was
> discovered in a late stage of spacecraft integration, resulting in
> extra cost and schedule delay to replace the defect PWB from the
> flight hardware. Although there are studies supported by ITRI \[4\] in
> the area of microvia technologies, the studies are mainly focused on
> statistical results rather than establishing criterion and procedures
> to qualify PWB. Furthermore, there is no existence of test data to
> support the reliability assessments of microvias for temperature
> ranges that are beyond the typical MIL standard requirements, such as
> the extremely low temperatures that will be encountered for missions
> to Mars \[5\].

Therefore, our approach for this project is to fabricate microvia PWBs
with controlled processes to facilitate the verification steps with NDE
and analytical techniques. Our tests will cover not only the typical MIL
standard ranges, but also at lower temperatures to support future
missions to Mars. With NDE and analytical techniques we will provide a
fundamental study for reliability assessments of microvias. Our goal is
to define criterion for reliable microvia PWB designs, and to ensure
that once the test coupons associated with each PWB panel pass the
acceptance tests, the PWB will be reliable for flight.

![](media/image1.jpeg){width="2.0083333333333333in" height="1.4875in"}
![](media/image2.jpeg){width="1.9833333333333334in" height="1.475in"}

**Figure 1:** Micro-sections of (left) defect microvia (poor plating,
over etching), and (right) buried-filled via (voids, plating fold, and
misalignment).

## 

**Technical Approach:**

+----------------+--------------------------+-------------------------+
| **Task**       | **Approach**             | **Comment**             |
+----------------+--------------------------+-------------------------+
| Design and     | PWBs with CO2 laser      | JHU/APL and two         |
| fabrication of | drilled vias.            | Commercial PWB Vendors: |
| test boards    |                          | *[To build the test     |
| with microvias | PWBs with UV/CO2 laser   | boards.]{.underline}*   |
| (blind, buried | drilled vias             |                         |
| vias)          |                          | Independent processes   |
|                | PWBs with pulsed plating | from different vendors  |
|                |                          | will be evaluated.      |
|                | PWBs with DC plating     | JHU/APL test samples    |
|                |                          | will serve as           |
|                | PWBs with unfilled       | referenced test         |
|                | buried vias              | samples.                |
|                |                          |                         |
|                | PWBs with filled buried  |                         |
|                | vias                     |                         |
+----------------+--------------------------+-------------------------+
| Environmental  | -   Perform thermal      | **JHU/APL:** *[Perform  |
| Testing        |     shock, and thermal   | the environmental       |
|                |     cycling tests        | tests]{.underline}*     |
|                |                          |                         |
|                |                          | Leverage from test      |
|                |                          | fixtures and software   |
|                |                          | developed from the      |
|                |                          | previous NASA ATD       |
|                |                          | project.                |
+----------------+--------------------------+-------------------------+
| Destructive    | Perform microsection     | **JHU/APL:** Perform    |
| Inspection     | inspection of test       | the microsection        |
|                | coupons to form a basis  | evaluation using its    |
|                | reliability reference    | existing facility.      |
|                | for the test boards      |                         |
+----------------+--------------------------+-------------------------+
| N              | -   Inspect microvias    | **NASA/JPL:** *[Apply   |
| on-destructive |     with real time       | the NDE                 |
| Evaluation     |     Microfocus X-ray     | process.]{.underline}*  |
|                |     technique.           |                         |
|                |                          | Applying reliable NDE   |
|                |                          | is crucial to ensure    |
|                |                          | reliability of microvia |
|                |                          | technology insertion    |
|                |                          | for future space        |
|                |                          | missions.               |
+----------------+--------------------------+-------------------------+

**NASA Customers:**

Since the work developed in this project is at the basic electronic
packaging level, the results from this study will supports all future
NASA programs. The near-term potential applications are for the X2000,
the MESSENGER, and future Mars programs where miniaturization of
electronics is critical for mission success.

**Clearly Stated Deliverables:**

1.  Test boards with microvias (blind and buried) with size variation
    and built-in test structure.

2.  Test plan for qualification of microvia PWBs to simulate flight
    environments.

3.  Procedures for NDE for reliability evaluation of microvias.

4.  Reliability assessment procedures using finite element analysis that
    correlates test results for reliability prediction

5.  NASA Technical Report that summarizes evaluations and
    recommendations on the microvia technology based on our test
    results.

**Top Level Schedule:**

> Major activities and milestones of the proposal are shown in the
> following table. The NASA/JPL and JHU/APL team will conduct weekly
> telephone conference to ensure adequate information exchange and
> timely discussions of management of technical, cost and schedule
> issues.

  ------------------------------ ---------- ---------- ---------- ----------
  **Major Milestone**            **Q1**     **Q2**     **Q3**     **Q4**

  Test board design                                               

  Test board manufacturing                                        

  Development of test plan                                        

  Test fixture, software                                          
  development                                                     

  Environmental tests                                             

  Nondestructive Evaluation                                       

  Report                                                          
  ------------------------------ ---------- ---------- ---------- ----------

**List of Procurements (over \$5K):**

## 

In this project, the major procuring cost is \$25K, for test boards from
two commercial vendors as well as JHU/APL.

Manpower Loading:

+-----------------+-------------+------------+-----------+------------+
|                 | ###### Q1   | **Q2**     | **Q3**    | **Q4**     |
+-----------------+-------------+------------+-----------+------------+
| NASA/JPL        | 0.1         | 0.2        | 0.25      | 0.25       |
+-----------------+-------------+------------+-----------+------------+

**Leveraging:**

> This work will leverage from existing facilities and expertise at
> NASA/JPL and the PWB facility at JHU/APL, gathered over many years of
> DOD and NASA technology development and research activities. No
> capital equipment will be procured, nor will facilities be
> significantly developed to perform this effort.

**Task Budget:**

  -------------- ------------- --------------- -------------- -------------
                 **(FY00)**    **FY01**        **FY02**       **FY03**

  Task \$                                      \$120,000      
                                               (total)        

  Procurements                                 \$60,000       
  -------------- ------------- --------------- -------------- -------------

JHU/AP Labor: \$48K: PWB procurement: \$20K; Supplies: \$5K

**References:**

1.  MIL-PRF-31032 Performance Specification for Printed Wiring Boards.

2.  IPC IPC-6012 Standards for Printed Wiring Boards.

3.  TRW Presentation at the Manufacturing Problem Prevention Program
    (MP3) workshop, the Aerospace Corporation (ASC) in El Segundo, CA
    June 27-28, 2000.

4.  <http://www/itri.org/>

5.  <http://nmp.jpl.nasa.gov/ds2/tech/microcontroller.html>

[**Attachment**]{.underline}

> Keywords:

-   Microvias

-   Blind / Buried Vias

-   Low Cost

-   High Reliability

-   Nondestructive Evaluation

**Proposal Abstract:**

The team of NASA/JPL and the Johns Hopkins University Applied Physics
Laboratory (JHU/APL) proposes to evaluate the reliability of microvia
technology (buried and blind vias) in high density printed wiring board
(PWB) design. We will also define criterion for reliable microvia PWB
design standards and reliability testing procedures. This project
leverages from previous NASA ATD project conducted at JHU/APL. To be
more focused and effective, we will evaluate microvias in the
conventional PWBs with etch-back process only, since this process has
been typically applied in space electronics. The task will also employ
novel NDE techniques to inspect microvia PWB, and analytical approaches
to acquire in-depth understanding of microvia behavior in temperature
cycling environment as well as to predict the reliability of microvias.

**Funding Summary:**

  ---------------- -------------- -------------- ------------- ------------
                                  **FY01**       **FY02**      **FY03**

  Task Total                                     \$120,000     

  Proposing Center NASA/JPL                      \$ 47,000     

  Supporting       JHU/APL                       \$ 73,000     
  Centers                                                      
  ---------------- -------------- -------------- ------------- ------------

**Deliverables:**

1.  Qualification Test Matrix (January, 2002)

2.  Microvias Test Boards (April, 2002)

3.  NDE Procedures (August, 2002)

4.  Reliability Assessment Procedures (August, 2002)

5.  NASA Technical Report (September, 2002)