MCU with ultra low energy gpio input I am working on a project with an energy friendly MCU from Silicon Labs. The EFR32BG1B132F256GM32 to be exact. My goal is to use as little power as possible to maximize the lifespan of the CR2032 battery I am using to power the application. The consumption in idle and the lowest energy mode possible for what I am doing turns out to be like 4uA which is to be expected according to the datasheet. Now the problem: 
I have a reed switch, one side is hooked up to the VDD rail and the other side to a GPIO pin. The GPIO features pull up or pull down and button debouncing internally. In my case I have button debouncing and the pull down enabled. If the reed switch is open, the current draw remains at 4uA, but if it closes, the current goes up to 80uA and remains there until the switch is open again. I assume since there is a path from VDD to GND via the pull down resistor power gets dissipated according to its resistance (unknown - could not find it in the datasheet..). But the problem is, that the application I want to use the reed switch in, holds it closed like 50% of the time and I cannot afford the high current draw during this time. I also tested it with pull up and the other side of the reed connected to GND - obviously same result. What could I do to resolve this? I thought about letting the pin floating and use a very high pull down like 10M externally but I also do not want the switch to trigger if it gets touched or something. Any comments are appreciated!

Use 2 GPIOs (we'll call them GPIO 1 and 2) to monitor the switch, and test for switch closure by checking for continuity.
This works as follows:


*

*Wake up the CPU

*set GPIO 1 high, check GPIO 2 state

*set GPIO 1 low, check GPIO 2 state


If GPIO2 followed GPIO1, then the switch was closed. If not, no.
This improves on pull-up or pull-down since there's no energy wasted even while the polling is happening.

Use a second DIO to control the pull-up voltage. The output is normally low. Set it high momentarily, read the DIO input, set the output low.

simulate this circuit – Schematic created using CircuitLab

Build a low-pass filter.
If you don't mind a delay when the switch opens, you could use, e.g. a 1M R from VDD feeding a cap, and then a 1K or so (only to keep from stressing the cap on discharge) from the cap to your switch/GPIO node. (Other side of cap to gnd of course.)
Size the cap according to the max delay you can tolerate for switch-off, and then decide if its presence reduces the impedance at the switch enough to reassure you.
If you have a lot of margin after that exercise, increase the R to 2M.  Or decrease it for lower impedance at the cost of higher current.