// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.3
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================

`timescale 1 ns / 1 ps

module process_frame (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        nofSample,
        incr_V,
        m_axi_cos_out_V_AWVALID,
        m_axi_cos_out_V_AWREADY,
        m_axi_cos_out_V_AWADDR,
        m_axi_cos_out_V_AWID,
        m_axi_cos_out_V_AWLEN,
        m_axi_cos_out_V_AWSIZE,
        m_axi_cos_out_V_AWBURST,
        m_axi_cos_out_V_AWLOCK,
        m_axi_cos_out_V_AWCACHE,
        m_axi_cos_out_V_AWPROT,
        m_axi_cos_out_V_AWQOS,
        m_axi_cos_out_V_AWREGION,
        m_axi_cos_out_V_AWUSER,
        m_axi_cos_out_V_WVALID,
        m_axi_cos_out_V_WREADY,
        m_axi_cos_out_V_WDATA,
        m_axi_cos_out_V_WSTRB,
        m_axi_cos_out_V_WLAST,
        m_axi_cos_out_V_WID,
        m_axi_cos_out_V_WUSER,
        m_axi_cos_out_V_ARVALID,
        m_axi_cos_out_V_ARREADY,
        m_axi_cos_out_V_ARADDR,
        m_axi_cos_out_V_ARID,
        m_axi_cos_out_V_ARLEN,
        m_axi_cos_out_V_ARSIZE,
        m_axi_cos_out_V_ARBURST,
        m_axi_cos_out_V_ARLOCK,
        m_axi_cos_out_V_ARCACHE,
        m_axi_cos_out_V_ARPROT,
        m_axi_cos_out_V_ARQOS,
        m_axi_cos_out_V_ARREGION,
        m_axi_cos_out_V_ARUSER,
        m_axi_cos_out_V_RVALID,
        m_axi_cos_out_V_RREADY,
        m_axi_cos_out_V_RDATA,
        m_axi_cos_out_V_RLAST,
        m_axi_cos_out_V_RID,
        m_axi_cos_out_V_RUSER,
        m_axi_cos_out_V_RRESP,
        m_axi_cos_out_V_BVALID,
        m_axi_cos_out_V_BREADY,
        m_axi_cos_out_V_BRESP,
        m_axi_cos_out_V_BID,
        m_axi_cos_out_V_BUSER,
        m_axi_sin_out_V_AWVALID,
        m_axi_sin_out_V_AWREADY,
        m_axi_sin_out_V_AWADDR,
        m_axi_sin_out_V_AWID,
        m_axi_sin_out_V_AWLEN,
        m_axi_sin_out_V_AWSIZE,
        m_axi_sin_out_V_AWBURST,
        m_axi_sin_out_V_AWLOCK,
        m_axi_sin_out_V_AWCACHE,
        m_axi_sin_out_V_AWPROT,
        m_axi_sin_out_V_AWQOS,
        m_axi_sin_out_V_AWREGION,
        m_axi_sin_out_V_AWUSER,
        m_axi_sin_out_V_WVALID,
        m_axi_sin_out_V_WREADY,
        m_axi_sin_out_V_WDATA,
        m_axi_sin_out_V_WSTRB,
        m_axi_sin_out_V_WLAST,
        m_axi_sin_out_V_WID,
        m_axi_sin_out_V_WUSER,
        m_axi_sin_out_V_ARVALID,
        m_axi_sin_out_V_ARREADY,
        m_axi_sin_out_V_ARADDR,
        m_axi_sin_out_V_ARID,
        m_axi_sin_out_V_ARLEN,
        m_axi_sin_out_V_ARSIZE,
        m_axi_sin_out_V_ARBURST,
        m_axi_sin_out_V_ARLOCK,
        m_axi_sin_out_V_ARCACHE,
        m_axi_sin_out_V_ARPROT,
        m_axi_sin_out_V_ARQOS,
        m_axi_sin_out_V_ARREGION,
        m_axi_sin_out_V_ARUSER,
        m_axi_sin_out_V_RVALID,
        m_axi_sin_out_V_RREADY,
        m_axi_sin_out_V_RDATA,
        m_axi_sin_out_V_RLAST,
        m_axi_sin_out_V_RID,
        m_axi_sin_out_V_RUSER,
        m_axi_sin_out_V_RRESP,
        m_axi_sin_out_V_BVALID,
        m_axi_sin_out_V_BREADY,
        m_axi_sin_out_V_BRESP,
        m_axi_sin_out_V_BID,
        m_axi_sin_out_V_BUSER
);

parameter    ap_ST_fsm_state1 = 3'b1;
parameter    ap_ST_fsm_pp0_stage0 = 3'b10;
parameter    ap_ST_fsm_state27 = 3'b100;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv3_0 = 3'b000;
parameter    ap_const_lv2_0 = 2'b00;
parameter    ap_const_lv4_0 = 4'b0000;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv31_0 = 31'b0000000000000000000000000000000;
parameter    ap_const_lv2_3 = 2'b11;
parameter    ap_const_lv31_1 = 31'b1;
parameter    ap_const_lv32_2 = 32'b10;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [31:0] nofSample;
input  [31:0] incr_V;
output   m_axi_cos_out_V_AWVALID;
input   m_axi_cos_out_V_AWREADY;
output  [31:0] m_axi_cos_out_V_AWADDR;
output  [0:0] m_axi_cos_out_V_AWID;
output  [31:0] m_axi_cos_out_V_AWLEN;
output  [2:0] m_axi_cos_out_V_AWSIZE;
output  [1:0] m_axi_cos_out_V_AWBURST;
output  [1:0] m_axi_cos_out_V_AWLOCK;
output  [3:0] m_axi_cos_out_V_AWCACHE;
output  [2:0] m_axi_cos_out_V_AWPROT;
output  [3:0] m_axi_cos_out_V_AWQOS;
output  [3:0] m_axi_cos_out_V_AWREGION;
output  [0:0] m_axi_cos_out_V_AWUSER;
output   m_axi_cos_out_V_WVALID;
input   m_axi_cos_out_V_WREADY;
output  [15:0] m_axi_cos_out_V_WDATA;
output  [1:0] m_axi_cos_out_V_WSTRB;
output   m_axi_cos_out_V_WLAST;
output  [0:0] m_axi_cos_out_V_WID;
output  [0:0] m_axi_cos_out_V_WUSER;
output   m_axi_cos_out_V_ARVALID;
input   m_axi_cos_out_V_ARREADY;
output  [31:0] m_axi_cos_out_V_ARADDR;
output  [0:0] m_axi_cos_out_V_ARID;
output  [31:0] m_axi_cos_out_V_ARLEN;
output  [2:0] m_axi_cos_out_V_ARSIZE;
output  [1:0] m_axi_cos_out_V_ARBURST;
output  [1:0] m_axi_cos_out_V_ARLOCK;
output  [3:0] m_axi_cos_out_V_ARCACHE;
output  [2:0] m_axi_cos_out_V_ARPROT;
output  [3:0] m_axi_cos_out_V_ARQOS;
output  [3:0] m_axi_cos_out_V_ARREGION;
output  [0:0] m_axi_cos_out_V_ARUSER;
input   m_axi_cos_out_V_RVALID;
output   m_axi_cos_out_V_RREADY;
input  [15:0] m_axi_cos_out_V_RDATA;
input   m_axi_cos_out_V_RLAST;
input  [0:0] m_axi_cos_out_V_RID;
input  [0:0] m_axi_cos_out_V_RUSER;
input  [1:0] m_axi_cos_out_V_RRESP;
input   m_axi_cos_out_V_BVALID;
output   m_axi_cos_out_V_BREADY;
input  [1:0] m_axi_cos_out_V_BRESP;
input  [0:0] m_axi_cos_out_V_BID;
input  [0:0] m_axi_cos_out_V_BUSER;
output   m_axi_sin_out_V_AWVALID;
input   m_axi_sin_out_V_AWREADY;
output  [31:0] m_axi_sin_out_V_AWADDR;
output  [0:0] m_axi_sin_out_V_AWID;
output  [31:0] m_axi_sin_out_V_AWLEN;
output  [2:0] m_axi_sin_out_V_AWSIZE;
output  [1:0] m_axi_sin_out_V_AWBURST;
output  [1:0] m_axi_sin_out_V_AWLOCK;
output  [3:0] m_axi_sin_out_V_AWCACHE;
output  [2:0] m_axi_sin_out_V_AWPROT;
output  [3:0] m_axi_sin_out_V_AWQOS;
output  [3:0] m_axi_sin_out_V_AWREGION;
output  [0:0] m_axi_sin_out_V_AWUSER;
output   m_axi_sin_out_V_WVALID;
input   m_axi_sin_out_V_WREADY;
output  [15:0] m_axi_sin_out_V_WDATA;
output  [1:0] m_axi_sin_out_V_WSTRB;
output   m_axi_sin_out_V_WLAST;
output  [0:0] m_axi_sin_out_V_WID;
output  [0:0] m_axi_sin_out_V_WUSER;
output   m_axi_sin_out_V_ARVALID;
input   m_axi_sin_out_V_ARREADY;
output  [31:0] m_axi_sin_out_V_ARADDR;
output  [0:0] m_axi_sin_out_V_ARID;
output  [31:0] m_axi_sin_out_V_ARLEN;
output  [2:0] m_axi_sin_out_V_ARSIZE;
output  [1:0] m_axi_sin_out_V_ARBURST;
output  [1:0] m_axi_sin_out_V_ARLOCK;
output  [3:0] m_axi_sin_out_V_ARCACHE;
output  [2:0] m_axi_sin_out_V_ARPROT;
output  [3:0] m_axi_sin_out_V_ARQOS;
output  [3:0] m_axi_sin_out_V_ARREGION;
output  [0:0] m_axi_sin_out_V_ARUSER;
input   m_axi_sin_out_V_RVALID;
output   m_axi_sin_out_V_RREADY;
input  [15:0] m_axi_sin_out_V_RDATA;
input   m_axi_sin_out_V_RLAST;
input  [0:0] m_axi_sin_out_V_RID;
input  [0:0] m_axi_sin_out_V_RUSER;
input  [1:0] m_axi_sin_out_V_RRESP;
input   m_axi_sin_out_V_BVALID;
output   m_axi_sin_out_V_BREADY;
input  [1:0] m_axi_sin_out_V_BRESP;
input  [0:0] m_axi_sin_out_V_BID;
input  [0:0] m_axi_sin_out_V_BUSER;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg m_axi_cos_out_V_AWVALID;
reg m_axi_cos_out_V_WVALID;
reg m_axi_cos_out_V_BREADY;
reg m_axi_sin_out_V_AWVALID;
reg m_axi_sin_out_V_WVALID;
reg m_axi_sin_out_V_BREADY;

(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
wire   [0:0] ap_CS_fsm_state1;
reg    cos_out_V_blk_n_AW;
reg    ap_enable_reg_pp0_iter18;
reg    cos_out_V_blk_n_W;
reg    ap_enable_reg_pp0_iter19;
reg    cos_out_V_blk_n_B;
reg    ap_enable_reg_pp0_iter24;
reg    sin_out_V_blk_n_AW;
reg    sin_out_V_blk_n_W;
reg    sin_out_V_blk_n_B;
reg   [30:0] i_cast6_reg_98;
wire   [0:0] tmp4_fu_120_p2;
wire   [31:0] i_cast6_cast_fu_126_p1;
reg   [31:0] i_cast6_cast_reg_179;
wire   [0:0] ap_CS_fsm_pp0_stage0;
reg    ap_sig_ioackin_m_axi_cos_out_V_AWREADY;
reg    ap_sig_ioackin_m_axi_sin_out_V_AWREADY;
reg    ap_sig_ioackin_m_axi_cos_out_V_WREADY;
reg    ap_sig_ioackin_m_axi_sin_out_V_WREADY;
reg   [31:0] ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179;
reg   [31:0] ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179;
wire   [30:0] i_fu_130_p2;
reg   [30:0] i_reg_185;
reg    ap_enable_reg_pp0_iter0;
wire   [0:0] tmp_fu_140_p2;
reg   [0:0] tmp_reg_190;
reg   [15:0] dds_cos_V_reg_194;
reg   [15:0] dds_sin_V_reg_199;
reg    ap_enable_reg_pp0_iter1;
reg    ap_enable_reg_pp0_iter2;
reg    ap_enable_reg_pp0_iter3;
reg    ap_enable_reg_pp0_iter4;
reg    ap_enable_reg_pp0_iter5;
reg    ap_enable_reg_pp0_iter6;
reg    ap_enable_reg_pp0_iter7;
reg    ap_enable_reg_pp0_iter8;
reg    ap_enable_reg_pp0_iter9;
reg    ap_enable_reg_pp0_iter10;
reg    ap_enable_reg_pp0_iter11;
reg    ap_enable_reg_pp0_iter12;
reg    ap_enable_reg_pp0_iter13;
reg    ap_enable_reg_pp0_iter14;
reg    ap_enable_reg_pp0_iter15;
reg    ap_enable_reg_pp0_iter16;
reg    ap_enable_reg_pp0_iter17;
reg    ap_enable_reg_pp0_iter20;
reg    ap_enable_reg_pp0_iter21;
reg    ap_enable_reg_pp0_iter22;
reg    ap_enable_reg_pp0_iter23;
wire    grp_process_r_fu_109_ap_start;
wire    grp_process_r_fu_109_ap_done;
wire    grp_process_r_fu_109_ap_idle;
wire    grp_process_r_fu_109_ap_ready;
reg    grp_process_r_fu_109_ap_ce;
wire   [15:0] grp_process_r_fu_109_ap_return_0;
wire   [15:0] grp_process_r_fu_109_ap_return_1;
reg   [30:0] i_cast6_phi_fu_102_p4;
reg    ap_reg_grp_process_r_fu_109_ap_start;
reg    ap_reg_ioackin_m_axi_cos_out_V_AWREADY;
reg    ap_reg_ioackin_m_axi_cos_out_V_WREADY;
reg    ap_reg_ioackin_m_axi_sin_out_V_AWREADY;
reg    ap_reg_ioackin_m_axi_sin_out_V_WREADY;
wire   [31:0] i_cast_fu_136_p1;
wire   [0:0] ap_CS_fsm_state27;
reg   [2:0] ap_NS_fsm;
reg    ap_condition_425;
reg    ap_condition_182;
reg    ap_condition_431;
reg    ap_condition_434;
reg    ap_condition_437;

// power-on initialization
initial begin
#0 ap_CS_fsm = 3'b1;
#0 ap_enable_reg_pp0_iter18 = 1'b0;
#0 ap_enable_reg_pp0_iter19 = 1'b0;
#0 ap_enable_reg_pp0_iter24 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter6 = 1'b0;
#0 ap_enable_reg_pp0_iter7 = 1'b0;
#0 ap_enable_reg_pp0_iter8 = 1'b0;
#0 ap_enable_reg_pp0_iter9 = 1'b0;
#0 ap_enable_reg_pp0_iter10 = 1'b0;
#0 ap_enable_reg_pp0_iter11 = 1'b0;
#0 ap_enable_reg_pp0_iter12 = 1'b0;
#0 ap_enable_reg_pp0_iter13 = 1'b0;
#0 ap_enable_reg_pp0_iter14 = 1'b0;
#0 ap_enable_reg_pp0_iter15 = 1'b0;
#0 ap_enable_reg_pp0_iter16 = 1'b0;
#0 ap_enable_reg_pp0_iter17 = 1'b0;
#0 ap_enable_reg_pp0_iter20 = 1'b0;
#0 ap_enable_reg_pp0_iter21 = 1'b0;
#0 ap_enable_reg_pp0_iter22 = 1'b0;
#0 ap_enable_reg_pp0_iter23 = 1'b0;
#0 ap_reg_grp_process_r_fu_109_ap_start = 1'b0;
#0 ap_reg_ioackin_m_axi_cos_out_V_AWREADY = 1'b0;
#0 ap_reg_ioackin_m_axi_cos_out_V_WREADY = 1'b0;
#0 ap_reg_ioackin_m_axi_sin_out_V_AWREADY = 1'b0;
#0 ap_reg_ioackin_m_axi_sin_out_V_WREADY = 1'b0;
end

process_r grp_process_r_fu_109(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_process_r_fu_109_ap_start),
    .ap_done(grp_process_r_fu_109_ap_done),
    .ap_idle(grp_process_r_fu_109_ap_idle),
    .ap_ready(grp_process_r_fu_109_ap_ready),
    .ap_ce(grp_process_r_fu_109_ap_ce),
    .incr_V(incr_V),
    .ap_return_0(grp_process_r_fu_109_ap_return_0),
    .ap_return_1(grp_process_r_fu_109_ap_return_1)
);

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter0 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & (1'b0 == tmp_fu_140_p2))) begin
            ap_enable_reg_pp0_iter0 <= 1'b0;
        end else if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0) & ~(1'b0 == tmp4_fu_120_p2))) begin
            ap_enable_reg_pp0_iter0 <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter1 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))))) begin
            ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
        end else if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0) & ~(1'b0 == tmp4_fu_120_p2))) begin
            ap_enable_reg_pp0_iter1 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter10 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter11 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter12 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter13 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter14 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter15 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter16 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter17 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter18 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter19 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter2 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter20 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter21 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter22 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter23 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter24 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23;
        end else if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0) & ~(1'b0 == tmp4_fu_120_p2))) begin
            ap_enable_reg_pp0_iter24 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter3 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter4 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter5 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter6 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter7 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter8 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter9 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
            ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_process_r_fu_109_ap_start <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
            ap_reg_grp_process_r_fu_109_ap_start <= 1'b1;
        end else if ((1'b1 == grp_process_r_fu_109_ap_ready)) begin
            ap_reg_grp_process_r_fu_109_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ioackin_m_axi_cos_out_V_AWREADY <= 1'b0;
    end else begin
        if ((1'b1 == ap_enable_reg_pp0_iter18)) begin
            if ((ap_condition_182 == 1'b1)) begin
                ap_reg_ioackin_m_axi_cos_out_V_AWREADY <= 1'b0;
            end else if ((ap_condition_425 == 1'b1)) begin
                ap_reg_ioackin_m_axi_cos_out_V_AWREADY <= 1'b1;
            end
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ioackin_m_axi_cos_out_V_WREADY <= 1'b0;
    end else begin
        if ((1'b1 == ap_enable_reg_pp0_iter19)) begin
            if ((ap_condition_182 == 1'b1)) begin
                ap_reg_ioackin_m_axi_cos_out_V_WREADY <= 1'b0;
            end else if ((ap_condition_431 == 1'b1)) begin
                ap_reg_ioackin_m_axi_cos_out_V_WREADY <= 1'b1;
            end
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ioackin_m_axi_sin_out_V_AWREADY <= 1'b0;
    end else begin
        if ((1'b1 == ap_enable_reg_pp0_iter18)) begin
            if ((ap_condition_182 == 1'b1)) begin
                ap_reg_ioackin_m_axi_sin_out_V_AWREADY <= 1'b0;
            end else if ((ap_condition_434 == 1'b1)) begin
                ap_reg_ioackin_m_axi_sin_out_V_AWREADY <= 1'b1;
            end
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ioackin_m_axi_sin_out_V_WREADY <= 1'b0;
    end else begin
        if ((1'b1 == ap_enable_reg_pp0_iter19)) begin
            if ((ap_condition_182 == 1'b1)) begin
                ap_reg_ioackin_m_axi_sin_out_V_WREADY <= 1'b0;
            end else if ((ap_condition_437 == 1'b1)) begin
                ap_reg_ioackin_m_axi_sin_out_V_WREADY <= 1'b1;
            end
        end
    end
end

always @ (posedge ap_clk) begin
    if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0) & ~(1'b0 == tmp4_fu_120_p2))) begin
        i_cast6_reg_98 <= ap_const_lv31_0;
    end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & (1'b1 == ap_enable_reg_pp0_iter1) & ~(1'b0 == tmp_reg_190))) begin
        i_cast6_reg_98 <= i_reg_185;
    end
end

always @ (posedge ap_clk) begin
    if (~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))))) begin
        ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179[30 : 0];
        ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179[30 : 0] <= ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179[30 : 0];
        dds_cos_V_reg_194 <= grp_process_r_fu_109_ap_return_0;
        dds_sin_V_reg_199 <= grp_process_r_fu_109_ap_return_1;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))))) begin
        ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179[30 : 0] <= i_cast6_cast_reg_179[30 : 0];
        i_cast6_cast_reg_179[30 : 0] <= i_cast6_cast_fu_126_p1[30 : 0];
        tmp_reg_190 <= tmp_fu_140_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
        i_reg_185 <= i_fu_130_p2;
    end
end

always @ (*) begin
    if ((((1'b0 == ap_start) & (ap_CS_fsm_state1 == 1'b1)) | (1'b1 == ap_CS_fsm_state27))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (ap_CS_fsm_state1 == 1'b1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == ap_CS_fsm_state27)) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if ((1'b0 == ap_reg_ioackin_m_axi_cos_out_V_AWREADY)) begin
        ap_sig_ioackin_m_axi_cos_out_V_AWREADY = m_axi_cos_out_V_AWREADY;
    end else begin
        ap_sig_ioackin_m_axi_cos_out_V_AWREADY = 1'b1;
    end
end

always @ (*) begin
    if ((1'b0 == ap_reg_ioackin_m_axi_cos_out_V_WREADY)) begin
        ap_sig_ioackin_m_axi_cos_out_V_WREADY = m_axi_cos_out_V_WREADY;
    end else begin
        ap_sig_ioackin_m_axi_cos_out_V_WREADY = 1'b1;
    end
end

always @ (*) begin
    if ((1'b0 == ap_reg_ioackin_m_axi_sin_out_V_AWREADY)) begin
        ap_sig_ioackin_m_axi_sin_out_V_AWREADY = m_axi_sin_out_V_AWREADY;
    end else begin
        ap_sig_ioackin_m_axi_sin_out_V_AWREADY = 1'b1;
    end
end

always @ (*) begin
    if ((1'b0 == ap_reg_ioackin_m_axi_sin_out_V_WREADY)) begin
        ap_sig_ioackin_m_axi_sin_out_V_WREADY = m_axi_sin_out_V_WREADY;
    end else begin
        ap_sig_ioackin_m_axi_sin_out_V_WREADY = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == ap_enable_reg_pp0_iter18)) begin
        cos_out_V_blk_n_AW = m_axi_cos_out_V_AWREADY;
    end else begin
        cos_out_V_blk_n_AW = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == ap_enable_reg_pp0_iter24)) begin
        cos_out_V_blk_n_B = m_axi_cos_out_V_BVALID;
    end else begin
        cos_out_V_blk_n_B = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == ap_enable_reg_pp0_iter19)) begin
        cos_out_V_blk_n_W = m_axi_cos_out_V_WREADY;
    end else begin
        cos_out_V_blk_n_W = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))))) begin
        grp_process_r_fu_109_ap_ce = 1'b1;
    end else begin
        grp_process_r_fu_109_ap_ce = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & ~(1'b0 == tmp_reg_190))) begin
        i_cast6_phi_fu_102_p4 = i_reg_185;
    end else begin
        i_cast6_phi_fu_102_p4 = i_cast6_reg_98;
    end
end

always @ (*) begin
    if (((1'b1 == ap_enable_reg_pp0_iter18) & ~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b0 == ap_reg_ioackin_m_axi_cos_out_V_AWREADY))) begin
        m_axi_cos_out_V_AWVALID = 1'b1;
    end else begin
        m_axi_cos_out_V_AWVALID = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_enable_reg_pp0_iter24) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))))) begin
        m_axi_cos_out_V_BREADY = 1'b1;
    end else begin
        m_axi_cos_out_V_BREADY = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_enable_reg_pp0_iter19) & ~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b0 == ap_reg_ioackin_m_axi_cos_out_V_WREADY))) begin
        m_axi_cos_out_V_WVALID = 1'b1;
    end else begin
        m_axi_cos_out_V_WVALID = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_enable_reg_pp0_iter18) & ~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b0 == ap_reg_ioackin_m_axi_sin_out_V_AWREADY))) begin
        m_axi_sin_out_V_AWVALID = 1'b1;
    end else begin
        m_axi_sin_out_V_AWVALID = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_enable_reg_pp0_iter24) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))))) begin
        m_axi_sin_out_V_BREADY = 1'b1;
    end else begin
        m_axi_sin_out_V_BREADY = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_enable_reg_pp0_iter19) & ~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b0 == ap_reg_ioackin_m_axi_sin_out_V_WREADY))) begin
        m_axi_sin_out_V_WVALID = 1'b1;
    end else begin
        m_axi_sin_out_V_WVALID = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == ap_enable_reg_pp0_iter18)) begin
        sin_out_V_blk_n_AW = m_axi_sin_out_V_AWREADY;
    end else begin
        sin_out_V_blk_n_AW = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == ap_enable_reg_pp0_iter24)) begin
        sin_out_V_blk_n_B = m_axi_sin_out_V_BVALID;
    end else begin
        sin_out_V_blk_n_B = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == ap_enable_reg_pp0_iter19)) begin
        sin_out_V_blk_n_W = m_axi_sin_out_V_WREADY;
    end else begin
        sin_out_V_blk_n_W = 1'b1;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            if ((~(ap_start == 1'b0) & ~(1'b0 == tmp4_fu_120_p2))) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end else if ((~(ap_start == 1'b0) & (1'b0 == tmp4_fu_120_p2))) begin
                ap_NS_fsm = ap_ST_fsm_state27;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end
        end
        ap_ST_fsm_pp0_stage0 : begin
            if (~((1'b1 == ap_enable_reg_pp0_iter24) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & ~(1'b1 == ap_enable_reg_pp0_iter23))) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end else if (((1'b1 == ap_enable_reg_pp0_iter24) & ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0)))) & ~(1'b1 == ap_enable_reg_pp0_iter23))) begin
                ap_NS_fsm = ap_ST_fsm_state27;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end
        end
        ap_ST_fsm_state27 : begin
            ap_NS_fsm = ap_ST_fsm_state1;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[ap_const_lv32_1];

assign ap_CS_fsm_state1 = ap_CS_fsm[ap_const_lv32_0];

assign ap_CS_fsm_state27 = ap_CS_fsm[ap_const_lv32_2];

always @ (*) begin
    ap_condition_182 = ~(((1'b1 == ap_enable_reg_pp0_iter18) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_AWREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) | ((1'b1 == ap_enable_reg_pp0_iter19) & ((1'b0 == ap_sig_ioackin_m_axi_cos_out_V_WREADY) | (1'b0 == ap_sig_ioackin_m_axi_sin_out_V_WREADY))) | ((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))));
end

always @ (*) begin
    ap_condition_425 = ((1'b1 == m_axi_cos_out_V_AWREADY) & ~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))));
end

always @ (*) begin
    ap_condition_431 = (~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b1 == m_axi_cos_out_V_WREADY));
end

always @ (*) begin
    ap_condition_434 = (~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b1 == m_axi_sin_out_V_AWREADY));
end

always @ (*) begin
    ap_condition_437 = (~((1'b1 == ap_enable_reg_pp0_iter24) & ((m_axi_cos_out_V_BVALID == 1'b0) | (m_axi_sin_out_V_BVALID == 1'b0))) & (1'b1 == m_axi_sin_out_V_WREADY));
end

assign grp_process_r_fu_109_ap_start = ap_reg_grp_process_r_fu_109_ap_start;

assign i_cast6_cast_fu_126_p1 = i_cast6_phi_fu_102_p4;

assign i_cast_fu_136_p1 = i_fu_130_p2;

assign i_fu_130_p2 = (i_cast6_phi_fu_102_p4 + ap_const_lv31_1);

assign m_axi_cos_out_V_ARADDR = ap_const_lv32_0;

assign m_axi_cos_out_V_ARBURST = ap_const_lv2_0;

assign m_axi_cos_out_V_ARCACHE = ap_const_lv4_0;

assign m_axi_cos_out_V_ARID = 1'b0;

assign m_axi_cos_out_V_ARLEN = ap_const_lv32_0;

assign m_axi_cos_out_V_ARLOCK = ap_const_lv2_0;

assign m_axi_cos_out_V_ARPROT = ap_const_lv3_0;

assign m_axi_cos_out_V_ARQOS = ap_const_lv4_0;

assign m_axi_cos_out_V_ARREGION = ap_const_lv4_0;

assign m_axi_cos_out_V_ARSIZE = ap_const_lv3_0;

assign m_axi_cos_out_V_ARUSER = 1'b0;

assign m_axi_cos_out_V_ARVALID = 1'b0;

assign m_axi_cos_out_V_AWADDR = ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179;

assign m_axi_cos_out_V_AWBURST = ap_const_lv2_0;

assign m_axi_cos_out_V_AWCACHE = ap_const_lv4_0;

assign m_axi_cos_out_V_AWID = 1'b0;

assign m_axi_cos_out_V_AWLEN = ap_const_lv32_1;

assign m_axi_cos_out_V_AWLOCK = ap_const_lv2_0;

assign m_axi_cos_out_V_AWPROT = ap_const_lv3_0;

assign m_axi_cos_out_V_AWQOS = ap_const_lv4_0;

assign m_axi_cos_out_V_AWREGION = ap_const_lv4_0;

assign m_axi_cos_out_V_AWSIZE = ap_const_lv3_0;

assign m_axi_cos_out_V_AWUSER = 1'b0;

assign m_axi_cos_out_V_RREADY = 1'b0;

assign m_axi_cos_out_V_WDATA = dds_cos_V_reg_194;

assign m_axi_cos_out_V_WID = 1'b0;

assign m_axi_cos_out_V_WLAST = 1'b0;

assign m_axi_cos_out_V_WSTRB = ap_const_lv2_3;

assign m_axi_cos_out_V_WUSER = 1'b0;

assign m_axi_sin_out_V_ARADDR = ap_const_lv32_0;

assign m_axi_sin_out_V_ARBURST = ap_const_lv2_0;

assign m_axi_sin_out_V_ARCACHE = ap_const_lv4_0;

assign m_axi_sin_out_V_ARID = 1'b0;

assign m_axi_sin_out_V_ARLEN = ap_const_lv32_0;

assign m_axi_sin_out_V_ARLOCK = ap_const_lv2_0;

assign m_axi_sin_out_V_ARPROT = ap_const_lv3_0;

assign m_axi_sin_out_V_ARQOS = ap_const_lv4_0;

assign m_axi_sin_out_V_ARREGION = ap_const_lv4_0;

assign m_axi_sin_out_V_ARSIZE = ap_const_lv3_0;

assign m_axi_sin_out_V_ARUSER = 1'b0;

assign m_axi_sin_out_V_ARVALID = 1'b0;

assign m_axi_sin_out_V_AWADDR = ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179;

assign m_axi_sin_out_V_AWBURST = ap_const_lv2_0;

assign m_axi_sin_out_V_AWCACHE = ap_const_lv4_0;

assign m_axi_sin_out_V_AWID = 1'b0;

assign m_axi_sin_out_V_AWLEN = ap_const_lv32_1;

assign m_axi_sin_out_V_AWLOCK = ap_const_lv2_0;

assign m_axi_sin_out_V_AWPROT = ap_const_lv3_0;

assign m_axi_sin_out_V_AWQOS = ap_const_lv4_0;

assign m_axi_sin_out_V_AWREGION = ap_const_lv4_0;

assign m_axi_sin_out_V_AWSIZE = ap_const_lv3_0;

assign m_axi_sin_out_V_AWUSER = 1'b0;

assign m_axi_sin_out_V_RREADY = 1'b0;

assign m_axi_sin_out_V_WDATA = dds_sin_V_reg_199;

assign m_axi_sin_out_V_WID = 1'b0;

assign m_axi_sin_out_V_WLAST = 1'b0;

assign m_axi_sin_out_V_WSTRB = ap_const_lv2_3;

assign m_axi_sin_out_V_WUSER = 1'b0;

assign tmp4_fu_120_p2 = (($signed(nofSample) > $signed(32'b00000000000000000000000000000000)) ? 1'b1 : 1'b0);

assign tmp_fu_140_p2 = (($signed(i_cast_fu_136_p1) < $signed(nofSample)) ? 1'b1 : 1'b0);

always @ (posedge ap_clk) begin
    i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179[31] <= 1'b0;
    ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179[31] <= 1'b0;
end

endmodule //process_frame


// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.3
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================

`timescale 1 ns / 1 ps

module process_r (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        ap_ce,
        incr_V,
        ap_return_0,
        ap_return_1
);

parameter    ap_ST_fsm_pp0_stage0 = 1'b1;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv32_1E = 32'b11110;
parameter    ap_const_lv32_1F = 32'b11111;
parameter    ap_const_lv32_14 = 32'b10100;
parameter    ap_const_lv32_1D = 32'b11101;
parameter    ap_const_lv32_B = 32'b1011;
parameter    ap_const_lv32_13 = 32'b10011;
parameter    ap_const_lv10_0 = 10'b0000000000;
parameter    ap_const_lv18_0 = 18'b000000000000000000;
parameter    ap_const_lv32_11 = 32'b10001;
parameter    ap_const_lv2_0 = 2'b00;
parameter    ap_const_lv2_1 = 2'b1;
parameter    ap_const_lv2_3 = 2'b11;
parameter    ap_const_lv17_0 = 17'b00000000000000000;
parameter    ap_const_lv18_1FFFF = 18'b11111111111111111;
parameter    ap_const_lv18_20001 = 18'b100000000000000001;
parameter    ap_const_lv25_0 = 25'b0000000000000000000000000;
parameter    ap_const_lv32_2B = 32'b101011;
parameter    ap_const_lv32_2A = 32'b101010;
parameter    ap_const_lv26_0 = 26'b00000000000000000000000000;
parameter    ap_const_lv32_1B = 32'b11011;
parameter    ap_const_lv32_1A = 32'b11010;
parameter    ap_const_lv32_F = 32'b1111;
parameter    ap_const_lv15_0 = 15'b000000000000000;
parameter    ap_const_lv16_7FFF = 16'b111111111111111;
parameter    ap_const_lv16_8001 = 16'b1000000000000001;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input   ap_ce;
input  [31:0] incr_V;
output  [15:0] ap_return_0;
output  [15:0] ap_return_1;

reg ap_done;
reg ap_idle;
reg ap_ready;

(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
wire   [0:0] ap_CS_fsm_pp0_stage0;
wire    ap_enable_reg_pp0_iter0;
reg    ap_enable_reg_pp0_iter1;
reg    ap_enable_reg_pp0_iter2;
reg    ap_enable_reg_pp0_iter3;
reg    ap_enable_reg_pp0_iter4;
reg    ap_enable_reg_pp0_iter5;
reg    ap_enable_reg_pp0_iter6;
reg    ap_enable_reg_pp0_iter7;
reg    ap_enable_reg_pp0_iter8;
reg    ap_enable_reg_pp0_iter9;
reg    ap_enable_reg_pp0_iter10;
reg    ap_enable_reg_pp0_iter11;
reg    ap_enable_reg_pp0_iter12;
reg    ap_enable_reg_pp0_iter13;
reg    ap_enable_reg_pp0_iter14;
reg    ap_enable_reg_pp0_iter15;
reg    ap_enable_reg_pp0_iter16;
reg    ap_enable_reg_pp0_iter17;
reg   [31:0] dds_0_acc_V;
wire   [9:0] dds_0_cos_lut_V_address0;
reg    dds_0_cos_lut_V_ce0;
wire   [16:0] dds_0_cos_lut_V_q0;
wire   [9:0] dds_0_cos_lut_V_address1;
reg    dds_0_cos_lut_V_ce1;
wire   [16:0] dds_0_cos_lut_V_q1;
wire   [8:0] dds_0_fine_lut_V_address0;
reg    dds_0_fine_lut_V_ce0;
wire   [15:0] dds_0_fine_lut_V_q0;
reg   [1:0] msb_V_reg_952;
reg   [1:0] ap_pipeline_reg_pp0_iter1_msb_V_reg_952;
reg   [1:0] ap_pipeline_reg_pp0_iter2_msb_V_reg_952;
reg   [1:0] ap_pipeline_reg_pp0_iter3_msb_V_reg_952;
reg   [1:0] ap_pipeline_reg_pp0_iter4_msb_V_reg_952;
reg   [9:0] lsb_V_reg_959;
reg   [9:0] ap_pipeline_reg_pp0_iter1_lsb_V_reg_959;
reg   [8:0] p_Result_8_reg_966;
reg   [8:0] ap_pipeline_reg_pp0_iter1_p_Result_8_reg_966;
reg   [8:0] ap_pipeline_reg_pp0_iter2_p_Result_8_reg_966;
reg   [8:0] ap_pipeline_reg_pp0_iter3_p_Result_8_reg_966;
reg   [8:0] ap_pipeline_reg_pp0_iter4_p_Result_8_reg_966;
reg   [8:0] ap_pipeline_reg_pp0_iter5_p_Result_8_reg_966;
reg   [8:0] ap_pipeline_reg_pp0_iter6_p_Result_8_reg_966;
wire   [9:0] sin_adr_V_fu_169_p2;
reg   [9:0] sin_adr_V_reg_971;
wire   [0:0] tmp_2_fu_178_p2;
reg   [0:0] tmp_2_reg_981;
reg   [0:0] ap_pipeline_reg_pp0_iter3_tmp_2_reg_981;
reg   [0:0] ap_pipeline_reg_pp0_iter4_tmp_2_reg_981;
reg   [0:0] ap_pipeline_reg_pp0_iter5_tmp_2_reg_981;
reg   [16:0] p_Val2_6_reg_996;
reg   [16:0] p_Val2_4_reg_1001;
reg   [16:0] ap_pipeline_reg_pp0_iter4_p_Val2_4_reg_1001;
reg   [16:0] ap_pipeline_reg_pp0_iter5_p_Val2_4_reg_1001;
wire   [17:0] dds_0_cos_lut_V_load_fu_187_p1;
reg   [17:0] dds_0_cos_lut_V_load_reg_1007;
reg   [17:0] ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_reg_1007;
reg   [17:0] ap_pipeline_reg_pp0_iter6_dds_0_cos_lut_V_load_reg_1007;
wire   [17:0] dds_0_cos_lut_V_load_2_fu_190_p1;
reg   [17:0] dds_0_cos_lut_V_load_2_reg_1014;
reg   [17:0] ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_2_reg_1014;
wire   [17:0] p_Val2_5_fu_193_p2;
reg   [17:0] p_Val2_5_reg_1019;
reg   [17:0] ap_pipeline_reg_pp0_iter5_p_Val2_5_reg_1019;
reg   [0:0] isneg_reg_1025;
wire   [17:0] p_Val2_7_fu_207_p2;
reg   [17:0] p_Val2_7_reg_1030;
reg   [17:0] ap_pipeline_reg_pp0_iter5_p_Val2_7_reg_1030;
reg   [17:0] ap_pipeline_reg_pp0_iter6_p_Val2_7_reg_1030;
reg   [0:0] isneg_1_reg_1036;
wire   [16:0] tmp_27_fu_221_p1;
reg   [16:0] tmp_27_reg_1041;
wire   [16:0] tmp_28_fu_225_p1;
reg   [16:0] tmp_28_reg_1046;
wire   [0:0] tmp_s_fu_229_p2;
reg   [0:0] tmp_s_reg_1051;
wire   [0:0] tmp_3_fu_234_p2;
reg   [0:0] tmp_3_reg_1058;
wire   [0:0] tmp_6_fu_239_p2;
reg   [0:0] tmp_6_reg_1063;
wire   [0:0] underflow_fu_249_p2;
reg   [0:0] underflow_reg_1069;
wire   [0:0] underflow_1_fu_259_p2;
reg   [0:0] underflow_1_reg_1076;
reg   [0:0] ap_pipeline_reg_pp0_iter6_underflow_1_reg_1076;
wire   [0:0] sel_tmp1_fu_264_p2;
reg   [0:0] sel_tmp1_reg_1084;
wire   [0:0] sel_tmp18_demorgan_fu_269_p2;
reg   [0:0] sel_tmp18_demorgan_reg_1090;
wire   [17:0] p_Val2_74_mux_fu_280_p3;
reg   [17:0] p_Val2_74_mux_reg_1096;
wire   [16:0] p_Val2_0_i_i_fu_286_p3;
reg   [16:0] p_Val2_0_i_i_reg_1101;
wire   [17:0] p_Val2_1_fu_303_p3;
reg   [17:0] p_Val2_1_reg_1106;
reg   [17:0] ap_pipeline_reg_pp0_iter7_p_Val2_1_reg_1106;
wire   [17:0] p_Val2_0_i_i1_fu_321_p3;
reg   [17:0] p_Val2_0_i_i1_reg_1114;
wire   [0:0] sel_tmp9_fu_329_p2;
reg   [0:0] sel_tmp9_reg_1119;
wire   [0:0] sel_tmp5_fu_338_p2;
reg   [0:0] sel_tmp5_reg_1124;
wire   [0:0] sel_tmp7_fu_343_p2;
reg   [0:0] sel_tmp7_reg_1129;
wire   [0:0] sel_tmp12_fu_357_p2;
reg   [0:0] sel_tmp12_reg_1134;
wire   [0:0] sel_tmp14_fu_362_p2;
reg   [0:0] sel_tmp14_reg_1140;
reg   [0:0] ap_pipeline_reg_pp0_iter7_sel_tmp14_reg_1140;
wire   [0:0] sel_tmp17_fu_378_p2;
reg   [0:0] sel_tmp17_reg_1146;
reg   [0:0] ap_pipeline_reg_pp0_iter7_sel_tmp17_reg_1146;
wire   [0:0] sel_tmp20_fu_394_p2;
reg   [0:0] sel_tmp20_reg_1152;
reg   [0:0] ap_pipeline_reg_pp0_iter7_sel_tmp20_reg_1152;
wire   [17:0] sel_tmp23_fu_414_p3;
reg   [17:0] sel_tmp23_reg_1158;
wire   [17:0] p_Val2_0_i_i_cast_fu_422_p1;
reg   [17:0] p_Val2_0_i_i_cast_reg_1163;
wire   [17:0] sel_tmp13_fu_448_p3;
reg   [17:0] sel_tmp13_reg_1168;
wire   [17:0] p_Val2_1_8_fu_474_p3;
reg   [17:0] p_Val2_1_8_reg_1173;
reg  signed [17:0] ap_pipeline_reg_pp0_iter8_p_Val2_1_8_reg_1173;
reg   [17:0] ap_pipeline_reg_pp0_iter9_p_Val2_1_8_reg_1173;
reg   [17:0] ap_pipeline_reg_pp0_iter10_p_Val2_1_8_reg_1173;
wire   [17:0] p_Val2_8_fu_495_p3;
reg  signed [17:0] p_Val2_8_reg_1184;
reg   [17:0] ap_pipeline_reg_pp0_iter9_p_Val2_8_reg_1184;
reg   [17:0] ap_pipeline_reg_pp0_iter10_p_Val2_8_reg_1184;
reg   [15:0] fine_word_V_reg_1190;
wire   [33:0] OP2_V_cast_fu_504_p1;
wire  signed [43:0] grp_fu_930_p3;
reg  signed [43:0] p_Val2_9_reg_1221;
reg  signed [43:0] ap_pipeline_reg_pp0_iter13_p_Val2_9_reg_1221;
reg   [0:0] signbit_reg_1228;
reg   [0:0] ap_pipeline_reg_pp0_iter13_signbit_reg_1228;
reg   [0:0] ap_pipeline_reg_pp0_iter14_signbit_reg_1228;
reg   [0:0] ap_pipeline_reg_pp0_iter15_signbit_reg_1228;
wire   [25:0] tmp_31_fu_539_p1;
reg   [25:0] tmp_31_reg_1236;
reg   [0:0] tmp_32_reg_1241;
reg   [0:0] ap_pipeline_reg_pp0_iter13_tmp_32_reg_1241;
reg   [0:0] ap_pipeline_reg_pp0_iter14_tmp_32_reg_1241;
reg   [0:0] ap_pipeline_reg_pp0_iter15_tmp_32_reg_1241;
wire  signed [43:0] grp_fu_941_p3;
reg  signed [43:0] p_Val2_13_reg_1247;
reg  signed [43:0] ap_pipeline_reg_pp0_iter13_p_Val2_13_reg_1247;
reg   [0:0] signbit_1_reg_1254;
reg   [0:0] ap_pipeline_reg_pp0_iter13_signbit_1_reg_1254;
reg   [0:0] ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254;
reg   [0:0] ap_pipeline_reg_pp0_iter15_signbit_1_reg_1254;
wire   [25:0] tmp_38_fu_556_p1;
reg   [25:0] tmp_38_reg_1262;
reg   [0:0] tmp_39_reg_1267;
reg   [0:0] ap_pipeline_reg_pp0_iter13_tmp_39_reg_1267;
reg   [0:0] ap_pipeline_reg_pp0_iter14_tmp_39_reg_1267;
reg   [0:0] ap_pipeline_reg_pp0_iter15_tmp_39_reg_1267;
wire   [0:0] r_fu_566_p2;
reg   [0:0] r_reg_1273;
wire   [0:0] r_1_fu_571_p2;
reg   [0:0] r_1_reg_1278;
wire   [15:0] p_Val2_11_fu_614_p2;
reg   [15:0] p_Val2_11_reg_1283;
reg   [15:0] ap_pipeline_reg_pp0_iter15_p_Val2_11_reg_1283;
reg   [15:0] ap_pipeline_reg_pp0_iter16_p_Val2_11_reg_1283;
reg   [0:0] newsignbit_reg_1289;
reg   [0:0] ap_pipeline_reg_pp0_iter15_newsignbit_reg_1289;
wire   [14:0] tmp_35_fu_628_p1;
reg   [14:0] tmp_35_reg_1297;
wire   [15:0] p_Val2_15_fu_670_p2;
reg   [15:0] p_Val2_15_reg_1302;
reg   [15:0] ap_pipeline_reg_pp0_iter15_p_Val2_15_reg_1302;
reg   [15:0] ap_pipeline_reg_pp0_iter16_p_Val2_15_reg_1302;
reg   [0:0] newsignbit_1_reg_1308;
reg   [0:0] ap_pipeline_reg_pp0_iter15_newsignbit_1_reg_1308;
wire   [14:0] tmp_42_fu_684_p1;
reg   [14:0] tmp_42_reg_1316;
wire   [0:0] overflow_fu_720_p2;
reg   [0:0] overflow_reg_1321;
reg   [0:0] ap_pipeline_reg_pp0_iter16_overflow_reg_1321;
wire   [0:0] tmp_16_fu_742_p2;
reg   [0:0] tmp_16_reg_1327;
wire   [0:0] overflow_1_fu_780_p2;
reg   [0:0] overflow_1_reg_1332;
reg   [0:0] ap_pipeline_reg_pp0_iter16_overflow_1_reg_1332;
wire   [0:0] tmp_24_fu_802_p2;
reg   [0:0] tmp_24_reg_1338;
wire   [0:0] underflow_2_fu_823_p2;
reg   [0:0] underflow_2_reg_1343;
wire   [0:0] underflow_3_fu_843_p2;
reg   [0:0] underflow_3_reg_1350;
wire   [31:0] tmp_1_fu_174_p1;
wire   [31:0] tmp_4_fu_183_p1;
wire   [31:0] tmp_8_fu_480_p1;
wire   [31:0] p_Val2_3_fu_127_p2;
wire   [0:0] tmp_5_fu_244_p2;
wire   [0:0] tmp_7_fu_254_p2;
wire   [17:0] p_Val2_s_7_fu_297_p3;
wire   [0:0] underflow_12_not_fu_275_p2;
wire   [0:0] sel_tmp2_fu_316_p2;
wire   [17:0] sel_tmp_fu_309_p3;
wire   [0:0] sel_tmp4_fu_333_p2;
wire   [0:0] sel_tmp10_fu_347_p2;
wire   [0:0] sel_tmp11_fu_352_p2;
wire   [0:0] underflow_14_not_fu_292_p2;
wire   [0:0] sel_tmp33_demorgan_fu_368_p2;
wire   [0:0] sel_tmp16_fu_372_p2;
wire   [0:0] sel_tmp42_demorgan_fu_383_p2;
wire   [0:0] sel_tmp19_fu_388_p2;
wire   [17:0] sel_tmp21_fu_400_p3;
wire   [17:0] sel_tmp22_fu_407_p3;
wire   [17:0] sel_tmp3_fu_431_p3;
wire   [17:0] sel_tmp6_fu_436_p3;
wire   [17:0] sel_tmp8_fu_442_p3;
wire   [17:0] p_Val2_77_mux_fu_425_p3;
wire   [17:0] sel_tmp24_fu_455_p3;
wire   [17:0] sel_tmp25_fu_460_p3;
wire   [17:0] sel_tmp26_fu_467_p3;
wire   [17:0] sel_tmp15_fu_484_p3;
wire   [17:0] sel_tmp18_fu_489_p3;
wire  signed [42:0] tmp_9_fu_510_p3;
wire  signed [42:0] tmp_17_fu_521_p3;
wire   [0:0] tmp_33_fu_592_p3;
wire   [0:0] r_i_i_fu_599_p2;
wire   [0:0] qbit_fu_585_p3;
wire   [0:0] qb_assign_1_fu_604_p2;
wire   [15:0] tmp_11_fu_610_p1;
wire   [15:0] p_Val2_10_fu_576_p4;
wire   [0:0] tmp_40_fu_648_p3;
wire   [0:0] r_i_i1_fu_655_p2;
wire   [0:0] qbit_1_fu_641_p3;
wire   [0:0] qb_assign_3_fu_660_p2;
wire   [15:0] tmp_19_fu_666_p1;
wire   [15:0] p_Val2_14_fu_632_p4;
wire   [0:0] tmp_12_fu_688_p2;
wire   [0:0] carry_fu_693_p2;
wire   [0:0] tmp_13_fu_698_p2;
wire   [0:0] p_not_i_fu_710_p2;
wire   [0:0] brmerge_i4_fu_715_p2;
wire   [0:0] deleted_ones_fu_703_p3;
wire   [0:0] brmerge40_demorgan_i_fu_726_p2;
wire   [0:0] tmp_15_fu_737_p2;
wire   [0:0] brmerge40_i_fu_731_p2;
wire   [0:0] tmp_20_fu_748_p2;
wire   [0:0] carry_1_fu_753_p2;
wire   [0:0] tmp_21_fu_758_p2;
wire   [0:0] p_not_i1_fu_770_p2;
wire   [0:0] brmerge_i5_fu_775_p2;
wire   [0:0] deleted_ones_1_fu_763_p3;
wire   [0:0] brmerge40_demorgan_i_1_fu_786_p2;
wire   [0:0] tmp_23_fu_797_p2;
wire   [0:0] brmerge40_i1_fu_791_p2;
wire   [0:0] p_Result_2_not_fu_808_p2;
wire   [0:0] tmp_14_fu_813_p2;
wire   [0:0] tmp_fu_818_p2;
wire   [0:0] p_Result_11_not_fu_828_p2;
wire   [0:0] tmp_22_fu_833_p2;
wire   [0:0] tmp9_fu_838_p2;
wire   [0:0] underflow_16_not_fu_852_p2;
wire   [0:0] brmerge_i_i4_fu_848_p2;
wire   [0:0] brmerge6_fu_857_p2;
wire   [15:0] p_Val2_87_mux_fu_862_p3;
wire   [15:0] p_Val2_4_9_fu_869_p3;
wire   [0:0] underflow_17_not_fu_887_p2;
wire   [0:0] brmerge_i_i5_fu_883_p2;
wire   [0:0] brmerge7_fu_892_p2;
wire   [15:0] p_Val2_91_mux_fu_897_p3;
wire   [15:0] p_Val2_5_10_fu_904_p3;
wire   [15:0] cos_dds_V_fu_875_p3;
wire   [15:0] sin_dds_V_fu_910_p3;
wire   [15:0] grp_fu_930_p1;
wire   [15:0] grp_fu_941_p0;
reg    grp_fu_930_ce;
reg    grp_fu_941_ce;
reg   [0:0] ap_NS_fsm;
reg    ap_pipeline_idle_pp0;

// power-on initialization
initial begin
#0 ap_CS_fsm = 1'b1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter6 = 1'b0;
#0 ap_enable_reg_pp0_iter7 = 1'b0;
#0 ap_enable_reg_pp0_iter8 = 1'b0;
#0 ap_enable_reg_pp0_iter9 = 1'b0;
#0 ap_enable_reg_pp0_iter10 = 1'b0;
#0 ap_enable_reg_pp0_iter11 = 1'b0;
#0 ap_enable_reg_pp0_iter12 = 1'b0;
#0 ap_enable_reg_pp0_iter13 = 1'b0;
#0 ap_enable_reg_pp0_iter14 = 1'b0;
#0 ap_enable_reg_pp0_iter15 = 1'b0;
#0 ap_enable_reg_pp0_iter16 = 1'b0;
#0 ap_enable_reg_pp0_iter17 = 1'b0;
#0 dds_0_acc_V = 32'b00000000000000000000000000000000;
end

process_r_dds_0_cbkb #(
    .DataWidth( 17 ),
    .AddressRange( 1024 ),
    .AddressWidth( 10 ))
dds_0_cos_lut_V_U(
    .clk(ap_clk),
    .reset(ap_rst),
    .address0(dds_0_cos_lut_V_address0),
    .ce0(dds_0_cos_lut_V_ce0),
    .q0(dds_0_cos_lut_V_q0),
    .address1(dds_0_cos_lut_V_address1),
    .ce1(dds_0_cos_lut_V_ce1),
    .q1(dds_0_cos_lut_V_q1)
);

process_r_dds_0_fcud #(
    .DataWidth( 16 ),
    .AddressRange( 512 ),
    .AddressWidth( 9 ))
dds_0_fine_lut_V_U(
    .clk(ap_clk),
    .reset(ap_rst),
    .address0(dds_0_fine_lut_V_address0),
    .ce0(dds_0_fine_lut_V_ce0),
    .q0(dds_0_fine_lut_V_q0)
);

dds_mac_mulsub_18dEe #(
    .ID( 1 ),
    .NUM_STAGE( 4 ),
    .din0_WIDTH( 18 ),
    .din1_WIDTH( 16 ),
    .din2_WIDTH( 43 ),
    .dout_WIDTH( 44 ))
dds_mac_mulsub_18dEe_U0(
    .clk(ap_clk),
    .reset(ap_rst),
    .din0(ap_pipeline_reg_pp0_iter8_p_Val2_1_8_reg_1173),
    .din1(grp_fu_930_p1),
    .din2(tmp_9_fu_510_p3),
    .ce(grp_fu_930_ce),
    .dout(grp_fu_930_p3)
);

dds_mac_muladd_16eOg #(
    .ID( 1 ),
    .NUM_STAGE( 4 ),
    .din0_WIDTH( 16 ),
    .din1_WIDTH( 18 ),
    .din2_WIDTH( 43 ),
    .dout_WIDTH( 44 ))
dds_mac_muladd_16eOg_U1(
    .clk(ap_clk),
    .reset(ap_rst),
    .din0(grp_fu_941_p0),
    .din1(p_Val2_8_reg_1184),
    .din2(tmp_17_fu_521_p3),
    .ce(grp_fu_941_ce),
    .dout(grp_fu_941_p3)
);

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter1 <= 1'b0;
    end else begin
        if (((ap_CS_fsm_pp0_stage0 == 1'b1) & ~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce)))) begin
            ap_enable_reg_pp0_iter1 <= ap_start;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter10 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter11 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter12 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter13 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter14 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter15 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter16 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter17 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter2 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter3 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter4 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter5 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter6 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter7 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter8 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter9 <= 1'b0;
    end else begin
        if (~(((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) | ~(1'b1 == ap_ce))) begin
            ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin
        ap_pipeline_reg_pp0_iter10_p_Val2_1_8_reg_1173 <= ap_pipeline_reg_pp0_iter9_p_Val2_1_8_reg_1173;
        ap_pipeline_reg_pp0_iter10_p_Val2_8_reg_1184 <= ap_pipeline_reg_pp0_iter9_p_Val2_8_reg_1184;
        ap_pipeline_reg_pp0_iter13_p_Val2_13_reg_1247 <= p_Val2_13_reg_1247;
        ap_pipeline_reg_pp0_iter13_p_Val2_9_reg_1221 <= p_Val2_9_reg_1221;
        ap_pipeline_reg_pp0_iter13_signbit_1_reg_1254 <= signbit_1_reg_1254;
        ap_pipeline_reg_pp0_iter13_signbit_reg_1228 <= signbit_reg_1228;
        ap_pipeline_reg_pp0_iter13_tmp_32_reg_1241 <= tmp_32_reg_1241;
        ap_pipeline_reg_pp0_iter13_tmp_39_reg_1267 <= tmp_39_reg_1267;
        ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254 <= ap_pipeline_reg_pp0_iter13_signbit_1_reg_1254;
        ap_pipeline_reg_pp0_iter14_signbit_reg_1228 <= ap_pipeline_reg_pp0_iter13_signbit_reg_1228;
        ap_pipeline_reg_pp0_iter14_tmp_32_reg_1241 <= ap_pipeline_reg_pp0_iter13_tmp_32_reg_1241;
        ap_pipeline_reg_pp0_iter14_tmp_39_reg_1267 <= ap_pipeline_reg_pp0_iter13_tmp_39_reg_1267;
        ap_pipeline_reg_pp0_iter15_newsignbit_1_reg_1308 <= newsignbit_1_reg_1308;
        ap_pipeline_reg_pp0_iter15_newsignbit_reg_1289 <= newsignbit_reg_1289;
        ap_pipeline_reg_pp0_iter15_p_Val2_11_reg_1283 <= p_Val2_11_reg_1283;
        ap_pipeline_reg_pp0_iter15_p_Val2_15_reg_1302 <= p_Val2_15_reg_1302;
        ap_pipeline_reg_pp0_iter15_signbit_1_reg_1254 <= ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254;
        ap_pipeline_reg_pp0_iter15_signbit_reg_1228 <= ap_pipeline_reg_pp0_iter14_signbit_reg_1228;
        ap_pipeline_reg_pp0_iter15_tmp_32_reg_1241 <= ap_pipeline_reg_pp0_iter14_tmp_32_reg_1241;
        ap_pipeline_reg_pp0_iter15_tmp_39_reg_1267 <= ap_pipeline_reg_pp0_iter14_tmp_39_reg_1267;
        ap_pipeline_reg_pp0_iter16_overflow_1_reg_1332 <= overflow_1_reg_1332;
        ap_pipeline_reg_pp0_iter16_overflow_reg_1321 <= overflow_reg_1321;
        ap_pipeline_reg_pp0_iter16_p_Val2_11_reg_1283 <= ap_pipeline_reg_pp0_iter15_p_Val2_11_reg_1283;
        ap_pipeline_reg_pp0_iter16_p_Val2_15_reg_1302 <= ap_pipeline_reg_pp0_iter15_p_Val2_15_reg_1302;
        ap_pipeline_reg_pp0_iter2_msb_V_reg_952 <= ap_pipeline_reg_pp0_iter1_msb_V_reg_952;
        ap_pipeline_reg_pp0_iter2_p_Result_8_reg_966 <= ap_pipeline_reg_pp0_iter1_p_Result_8_reg_966;
        ap_pipeline_reg_pp0_iter3_msb_V_reg_952 <= ap_pipeline_reg_pp0_iter2_msb_V_reg_952;
        ap_pipeline_reg_pp0_iter3_p_Result_8_reg_966 <= ap_pipeline_reg_pp0_iter2_p_Result_8_reg_966;
        ap_pipeline_reg_pp0_iter3_tmp_2_reg_981 <= tmp_2_reg_981;
        ap_pipeline_reg_pp0_iter4_msb_V_reg_952 <= ap_pipeline_reg_pp0_iter3_msb_V_reg_952;
        ap_pipeline_reg_pp0_iter4_p_Result_8_reg_966 <= ap_pipeline_reg_pp0_iter3_p_Result_8_reg_966;
        ap_pipeline_reg_pp0_iter4_p_Val2_4_reg_1001 <= p_Val2_4_reg_1001;
        ap_pipeline_reg_pp0_iter4_tmp_2_reg_981 <= ap_pipeline_reg_pp0_iter3_tmp_2_reg_981;
        ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_2_reg_1014[16 : 0] <= dds_0_cos_lut_V_load_2_reg_1014[16 : 0];
        ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_reg_1007[16 : 0] <= dds_0_cos_lut_V_load_reg_1007[16 : 0];
        ap_pipeline_reg_pp0_iter5_p_Result_8_reg_966 <= ap_pipeline_reg_pp0_iter4_p_Result_8_reg_966;
        ap_pipeline_reg_pp0_iter5_p_Val2_4_reg_1001 <= ap_pipeline_reg_pp0_iter4_p_Val2_4_reg_1001;
        ap_pipeline_reg_pp0_iter5_p_Val2_5_reg_1019 <= p_Val2_5_reg_1019;
        ap_pipeline_reg_pp0_iter5_p_Val2_7_reg_1030 <= p_Val2_7_reg_1030;
        ap_pipeline_reg_pp0_iter5_tmp_2_reg_981 <= ap_pipeline_reg_pp0_iter4_tmp_2_reg_981;
        ap_pipeline_reg_pp0_iter6_dds_0_cos_lut_V_load_reg_1007[16 : 0] <= ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_reg_1007[16 : 0];
        ap_pipeline_reg_pp0_iter6_p_Result_8_reg_966 <= ap_pipeline_reg_pp0_iter5_p_Result_8_reg_966;
        ap_pipeline_reg_pp0_iter6_p_Val2_7_reg_1030 <= ap_pipeline_reg_pp0_iter5_p_Val2_7_reg_1030;
        ap_pipeline_reg_pp0_iter6_underflow_1_reg_1076 <= underflow_1_reg_1076;
        ap_pipeline_reg_pp0_iter7_p_Val2_1_reg_1106 <= p_Val2_1_reg_1106;
        ap_pipeline_reg_pp0_iter7_sel_tmp14_reg_1140 <= sel_tmp14_reg_1140;
        ap_pipeline_reg_pp0_iter7_sel_tmp17_reg_1146 <= sel_tmp17_reg_1146;
        ap_pipeline_reg_pp0_iter7_sel_tmp20_reg_1152 <= sel_tmp20_reg_1152;
        ap_pipeline_reg_pp0_iter8_p_Val2_1_8_reg_1173 <= p_Val2_1_8_reg_1173;
        ap_pipeline_reg_pp0_iter9_p_Val2_1_8_reg_1173 <= ap_pipeline_reg_pp0_iter8_p_Val2_1_8_reg_1173;
        ap_pipeline_reg_pp0_iter9_p_Val2_8_reg_1184 <= p_Val2_8_reg_1184;
        dds_0_cos_lut_V_load_2_reg_1014[16 : 0] <= dds_0_cos_lut_V_load_2_fu_190_p1[16 : 0];
        dds_0_cos_lut_V_load_reg_1007[16 : 0] <= dds_0_cos_lut_V_load_fu_187_p1[16 : 0];
        fine_word_V_reg_1190 <= dds_0_fine_lut_V_q0;
        isneg_1_reg_1036 <= p_Val2_7_fu_207_p2[ap_const_lv32_11];
        isneg_reg_1025 <= p_Val2_5_fu_193_p2[ap_const_lv32_11];
        newsignbit_1_reg_1308 <= p_Val2_15_fu_670_p2[ap_const_lv32_F];
        newsignbit_reg_1289 <= p_Val2_11_fu_614_p2[ap_const_lv32_F];
        overflow_1_reg_1332 <= overflow_1_fu_780_p2;
        overflow_reg_1321 <= overflow_fu_720_p2;
        p_Val2_0_i_i1_reg_1114 <= p_Val2_0_i_i1_fu_321_p3;
        p_Val2_0_i_i_reg_1101 <= p_Val2_0_i_i_fu_286_p3;
        p_Val2_11_reg_1283 <= p_Val2_11_fu_614_p2;
        p_Val2_15_reg_1302 <= p_Val2_15_fu_670_p2;
        p_Val2_1_8_reg_1173 <= p_Val2_1_8_fu_474_p3;
        p_Val2_1_reg_1106 <= p_Val2_1_fu_303_p3;
        p_Val2_5_reg_1019 <= p_Val2_5_fu_193_p2;
        p_Val2_74_mux_reg_1096 <= p_Val2_74_mux_fu_280_p3;
        p_Val2_7_reg_1030 <= p_Val2_7_fu_207_p2;
        p_Val2_8_reg_1184 <= p_Val2_8_fu_495_p3;
        r_1_reg_1278 <= r_1_fu_571_p2;
        r_reg_1273 <= r_fu_566_p2;
        sel_tmp12_reg_1134 <= sel_tmp12_fu_357_p2;
        sel_tmp14_reg_1140 <= sel_tmp14_fu_362_p2;
        sel_tmp17_reg_1146 <= sel_tmp17_fu_378_p2;
        sel_tmp18_demorgan_reg_1090 <= sel_tmp18_demorgan_fu_269_p2;
        sel_tmp1_reg_1084 <= sel_tmp1_fu_264_p2;
        sel_tmp20_reg_1152 <= sel_tmp20_fu_394_p2;
        sel_tmp23_reg_1158 <= sel_tmp23_fu_414_p3;
        sel_tmp5_reg_1124 <= sel_tmp5_fu_338_p2;
        sel_tmp7_reg_1129 <= sel_tmp7_fu_343_p2;
        sel_tmp9_reg_1119 <= sel_tmp9_fu_329_p2;
        signbit_1_reg_1254 <= grp_fu_941_p3[ap_const_lv32_2B];
        signbit_reg_1228 <= grp_fu_930_p3[ap_const_lv32_2B];
        tmp_16_reg_1327 <= tmp_16_fu_742_p2;
        tmp_24_reg_1338 <= tmp_24_fu_802_p2;
        tmp_27_reg_1041 <= tmp_27_fu_221_p1;
        tmp_28_reg_1046 <= tmp_28_fu_225_p1;
        tmp_2_reg_981 <= tmp_2_fu_178_p2;
        tmp_31_reg_1236 <= tmp_31_fu_539_p1;
        tmp_32_reg_1241 <= grp_fu_930_p3[ap_const_lv32_2A];
        tmp_35_reg_1297 <= tmp_35_fu_628_p1;
        tmp_38_reg_1262 <= tmp_38_fu_556_p1;
        tmp_39_reg_1267 <= grp_fu_941_p3[ap_const_lv32_2A];
        tmp_3_reg_1058 <= tmp_3_fu_234_p2;
        tmp_42_reg_1316 <= tmp_42_fu_684_p1;
        tmp_6_reg_1063 <= tmp_6_fu_239_p2;
        tmp_s_reg_1051 <= tmp_s_fu_229_p2;
        underflow_1_reg_1076 <= underflow_1_fu_259_p2;
        underflow_2_reg_1343 <= underflow_2_fu_823_p2;
        underflow_3_reg_1350 <= underflow_3_fu_843_p2;
        underflow_reg_1069 <= underflow_fu_249_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((ap_CS_fsm_pp0_stage0 == 1'b1) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin
        ap_pipeline_reg_pp0_iter1_lsb_V_reg_959 <= lsb_V_reg_959;
        ap_pipeline_reg_pp0_iter1_msb_V_reg_952 <= msb_V_reg_952;
        ap_pipeline_reg_pp0_iter1_p_Result_8_reg_966 <= p_Result_8_reg_966;
        lsb_V_reg_959 <= {{p_Val2_3_fu_127_p2[ap_const_lv32_1D : ap_const_lv32_14]}};
        msb_V_reg_952 <= {{p_Val2_3_fu_127_p2[ap_const_lv32_1F : ap_const_lv32_1E]}};
        p_Result_8_reg_966 <= {{p_Val2_3_fu_127_p2[ap_const_lv32_13 : ap_const_lv32_B]}};
        sin_adr_V_reg_971 <= sin_adr_V_fu_169_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((ap_CS_fsm_pp0_stage0 == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter0) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin
        dds_0_acc_V <= p_Val2_3_fu_127_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (sel_tmp17_reg_1146 == 1'b0) & (sel_tmp20_reg_1152 == 1'b0))) begin
        p_Val2_0_i_i_cast_reg_1163[16 : 0] <= p_Val2_0_i_i_cast_fu_422_p1[16 : 0];
    end
end

always @ (posedge ap_clk) begin
    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter12))) begin
        p_Val2_13_reg_1247 <= grp_fu_941_p3;
        p_Val2_9_reg_1221 <= grp_fu_930_p3;
    end
end

always @ (posedge ap_clk) begin
    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
        p_Val2_4_reg_1001 <= dds_0_cos_lut_V_q1;
        p_Val2_6_reg_996 <= dds_0_cos_lut_V_q0;
    end
end

always @ (posedge ap_clk) begin
    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (sel_tmp17_reg_1146 == 1'b0) & (sel_tmp20_reg_1152 == 1'b0) & (sel_tmp14_reg_1140 == 1'b0))) begin
        sel_tmp13_reg_1168 <= sel_tmp13_fu_448_p3;
    end
end

always @ (*) begin
    if ((((1'b0 == ap_start) & (ap_CS_fsm_pp0_stage0 == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter0)) | (~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter17)))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (ap_CS_fsm_pp0_stage0 == 1'b1) & (1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter9) & (1'b0 == ap_enable_reg_pp0_iter10) & (1'b0 == ap_enable_reg_pp0_iter11) & (1'b0 == ap_enable_reg_pp0_iter12) & (1'b0 == ap_enable_reg_pp0_iter13) & (1'b0 == ap_enable_reg_pp0_iter14) & (1'b0 == ap_enable_reg_pp0_iter15) & (1'b0 == ap_enable_reg_pp0_iter16) & (1'b0 == ap_enable_reg_pp0_iter17))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter9) & (1'b0 == ap_enable_reg_pp0_iter10) & (1'b0 == ap_enable_reg_pp0_iter11) & (1'b0 == ap_enable_reg_pp0_iter12) & (1'b0 == ap_enable_reg_pp0_iter13) & (1'b0 == ap_enable_reg_pp0_iter14) & (1'b0 == ap_enable_reg_pp0_iter15) & (1'b0 == ap_enable_reg_pp0_iter16))) begin
        ap_pipeline_idle_pp0 = 1'b1;
    end else begin
        ap_pipeline_idle_pp0 = 1'b0;
    end
end

always @ (*) begin
    if (((ap_CS_fsm_pp0_stage0 == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter0) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
        dds_0_cos_lut_V_ce0 = 1'b1;
    end else begin
        dds_0_cos_lut_V_ce0 = 1'b0;
    end
end

always @ (*) begin
    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
        dds_0_cos_lut_V_ce1 = 1'b1;
    end else begin
        dds_0_cos_lut_V_ce1 = 1'b0;
    end
end

always @ (*) begin
    if ((~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
        dds_0_fine_lut_V_ce0 = 1'b1;
    end else begin
        dds_0_fine_lut_V_ce0 = 1'b0;
    end
end

always @ (*) begin
    if (((ap_CS_fsm_pp0_stage0 == 1'b1) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin
        grp_fu_930_ce = 1'b1;
    end else begin
        grp_fu_930_ce = 1'b0;
    end
end

always @ (*) begin
    if (((ap_CS_fsm_pp0_stage0 == 1'b1) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_start == 1'b0)) & (1'b1 == ap_ce))) begin
        grp_fu_941_ce = 1'b1;
    end else begin
        grp_fu_941_ce = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_pp0_stage0 : begin
            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign OP2_V_cast_fu_504_p1 = fine_word_V_reg_1190;

assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[ap_const_lv32_0];

assign ap_enable_reg_pp0_iter0 = ap_start;

assign ap_return_0 = cos_dds_V_fu_875_p3;

assign ap_return_1 = sin_dds_V_fu_910_p3;

assign brmerge40_demorgan_i_1_fu_786_p2 = (newsignbit_1_reg_1308 & deleted_ones_1_fu_763_p3);

assign brmerge40_demorgan_i_fu_726_p2 = (newsignbit_reg_1289 & deleted_ones_fu_703_p3);

assign brmerge40_i1_fu_791_p2 = (brmerge40_demorgan_i_1_fu_786_p2 ^ 1'b1);

assign brmerge40_i_fu_731_p2 = (brmerge40_demorgan_i_fu_726_p2 ^ 1'b1);

assign brmerge6_fu_857_p2 = (ap_pipeline_reg_pp0_iter16_overflow_reg_1321 | underflow_16_not_fu_852_p2);

assign brmerge7_fu_892_p2 = (ap_pipeline_reg_pp0_iter16_overflow_1_reg_1332 | underflow_17_not_fu_887_p2);

assign brmerge_i4_fu_715_p2 = (newsignbit_reg_1289 | p_not_i_fu_710_p2);

assign brmerge_i5_fu_775_p2 = (newsignbit_1_reg_1308 | p_not_i1_fu_770_p2);

assign brmerge_i_i4_fu_848_p2 = (underflow_2_reg_1343 | ap_pipeline_reg_pp0_iter16_overflow_reg_1321);

assign brmerge_i_i5_fu_883_p2 = (underflow_3_reg_1350 | ap_pipeline_reg_pp0_iter16_overflow_1_reg_1332);

assign carry_1_fu_753_p2 = (ap_pipeline_reg_pp0_iter14_tmp_39_reg_1267 & tmp_20_fu_748_p2);

assign carry_fu_693_p2 = (ap_pipeline_reg_pp0_iter14_tmp_32_reg_1241 & tmp_12_fu_688_p2);

assign cos_dds_V_fu_875_p3 = ((brmerge6_fu_857_p2[0:0] === 1'b1) ? p_Val2_87_mux_fu_862_p3 : p_Val2_4_9_fu_869_p3);

assign dds_0_cos_lut_V_address0 = tmp_1_fu_174_p1;

assign dds_0_cos_lut_V_address1 = tmp_4_fu_183_p1;

assign dds_0_cos_lut_V_load_2_fu_190_p1 = p_Val2_4_reg_1001;

assign dds_0_cos_lut_V_load_fu_187_p1 = p_Val2_6_reg_996;

assign dds_0_fine_lut_V_address0 = tmp_8_fu_480_p1;

assign deleted_ones_1_fu_763_p3 = ((carry_1_fu_753_p2[0:0] === 1'b1) ? tmp_21_fu_758_p2 : ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254);

assign deleted_ones_fu_703_p3 = ((carry_fu_693_p2[0:0] === 1'b1) ? tmp_13_fu_698_p2 : ap_pipeline_reg_pp0_iter14_signbit_reg_1228);

assign grp_fu_930_p1 = OP2_V_cast_fu_504_p1;

assign grp_fu_941_p0 = OP2_V_cast_fu_504_p1;

assign overflow_1_fu_780_p2 = (brmerge_i5_fu_775_p2 & tmp_21_fu_758_p2);

assign overflow_fu_720_p2 = (brmerge_i4_fu_715_p2 & tmp_13_fu_698_p2);

assign p_Result_11_not_fu_828_p2 = (ap_pipeline_reg_pp0_iter15_tmp_39_reg_1267 ^ 1'b1);

assign p_Result_2_not_fu_808_p2 = (ap_pipeline_reg_pp0_iter15_tmp_32_reg_1241 ^ 1'b1);

assign p_Val2_0_i_i1_fu_321_p3 = ((sel_tmp2_fu_316_p2[0:0] === 1'b1) ? p_Val2_74_mux_fu_280_p3 : sel_tmp_fu_309_p3);

assign p_Val2_0_i_i_cast_fu_422_p1 = p_Val2_0_i_i_reg_1101;

assign p_Val2_0_i_i_fu_286_p3 = ((ap_pipeline_reg_pp0_iter5_tmp_2_reg_981[0:0] === 1'b1) ? ap_const_lv17_0 : ap_pipeline_reg_pp0_iter5_p_Val2_4_reg_1001);

assign p_Val2_10_fu_576_p4 = {{ap_pipeline_reg_pp0_iter13_p_Val2_9_reg_1221[ap_const_lv32_2A : ap_const_lv32_1B]}};

assign p_Val2_11_fu_614_p2 = (tmp_11_fu_610_p1 + p_Val2_10_fu_576_p4);

assign p_Val2_14_fu_632_p4 = {{ap_pipeline_reg_pp0_iter13_p_Val2_13_reg_1247[ap_const_lv32_2A : ap_const_lv32_1B]}};

assign p_Val2_15_fu_670_p2 = (tmp_19_fu_666_p1 + p_Val2_14_fu_632_p4);

assign p_Val2_1_8_fu_474_p3 = ((sel_tmp20_reg_1152[0:0] === 1'b1) ? p_Val2_74_mux_reg_1096 : sel_tmp26_fu_467_p3);

assign p_Val2_1_fu_303_p3 = ((underflow_1_reg_1076[0:0] === 1'b1) ? ap_const_lv18_20001 : ap_pipeline_reg_pp0_iter5_p_Val2_7_reg_1030);

assign p_Val2_3_fu_127_p2 = (incr_V + dds_0_acc_V);

assign p_Val2_4_9_fu_869_p3 = ((underflow_2_reg_1343[0:0] === 1'b1) ? ap_const_lv16_8001 : ap_pipeline_reg_pp0_iter16_p_Val2_11_reg_1283);

assign p_Val2_5_10_fu_904_p3 = ((underflow_3_reg_1350[0:0] === 1'b1) ? ap_const_lv16_8001 : ap_pipeline_reg_pp0_iter16_p_Val2_15_reg_1302);

assign p_Val2_5_fu_193_p2 = (ap_const_lv18_0 - dds_0_cos_lut_V_load_2_fu_190_p1);

assign p_Val2_74_mux_fu_280_p3 = ((underflow_reg_1069[0:0] === 1'b1) ? ap_const_lv18_1FFFF : ap_pipeline_reg_pp0_iter5_p_Val2_5_reg_1019);

assign p_Val2_77_mux_fu_425_p3 = ((ap_pipeline_reg_pp0_iter6_underflow_1_reg_1076[0:0] === 1'b1) ? ap_const_lv18_1FFFF : ap_pipeline_reg_pp0_iter6_p_Val2_7_reg_1030);

assign p_Val2_7_fu_207_p2 = (ap_const_lv18_0 - dds_0_cos_lut_V_load_fu_187_p1);

assign p_Val2_87_mux_fu_862_p3 = ((brmerge_i_i4_fu_848_p2[0:0] === 1'b1) ? ap_const_lv16_7FFF : ap_pipeline_reg_pp0_iter16_p_Val2_11_reg_1283);

assign p_Val2_8_fu_495_p3 = ((ap_pipeline_reg_pp0_iter7_sel_tmp20_reg_1152[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter7_p_Val2_1_reg_1106 : sel_tmp18_fu_489_p3);

assign p_Val2_91_mux_fu_897_p3 = ((brmerge_i_i5_fu_883_p2[0:0] === 1'b1) ? ap_const_lv16_7FFF : ap_pipeline_reg_pp0_iter16_p_Val2_15_reg_1302);

assign p_Val2_s_7_fu_297_p3 = ((underflow_reg_1069[0:0] === 1'b1) ? ap_const_lv18_20001 : ap_pipeline_reg_pp0_iter5_p_Val2_5_reg_1019);

assign p_not_i1_fu_770_p2 = (ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254 ^ carry_1_fu_753_p2);

assign p_not_i_fu_710_p2 = (ap_pipeline_reg_pp0_iter14_signbit_reg_1228 ^ carry_fu_693_p2);

assign qb_assign_1_fu_604_p2 = (r_i_i_fu_599_p2 & qbit_fu_585_p3);

assign qb_assign_3_fu_660_p2 = (r_i_i1_fu_655_p2 & qbit_1_fu_641_p3);

assign qbit_1_fu_641_p3 = ap_pipeline_reg_pp0_iter13_p_Val2_13_reg_1247[ap_const_lv32_1A];

assign qbit_fu_585_p3 = ap_pipeline_reg_pp0_iter13_p_Val2_9_reg_1221[ap_const_lv32_1A];

assign r_1_fu_571_p2 = ((tmp_38_reg_1262 != ap_const_lv26_0) ? 1'b1 : 1'b0);

assign r_fu_566_p2 = ((tmp_31_reg_1236 != ap_const_lv26_0) ? 1'b1 : 1'b0);

assign r_i_i1_fu_655_p2 = (tmp_40_fu_648_p3 | r_1_reg_1278);

assign r_i_i_fu_599_p2 = (tmp_33_fu_592_p3 | r_reg_1273);

assign sel_tmp10_fu_347_p2 = (sel_tmp18_demorgan_reg_1090 ^ 1'b1);

assign sel_tmp11_fu_352_p2 = (tmp_6_reg_1063 & sel_tmp10_fu_347_p2);

assign sel_tmp12_fu_357_p2 = (sel_tmp11_fu_352_p2 & underflow_1_reg_1076);

assign sel_tmp13_fu_448_p3 = ((sel_tmp12_reg_1134[0:0] === 1'b1) ? p_Val2_0_i_i_cast_fu_422_p1 : sel_tmp8_fu_442_p3);

assign sel_tmp14_fu_362_p2 = (sel_tmp11_fu_352_p2 & underflow_14_not_fu_292_p2);

assign sel_tmp15_fu_484_p3 = ((ap_pipeline_reg_pp0_iter7_sel_tmp14_reg_1140[0:0] === 1'b1) ? p_Val2_0_i_i_cast_reg_1163 : sel_tmp13_reg_1168);

assign sel_tmp16_fu_372_p2 = (sel_tmp33_demorgan_fu_368_p2 ^ 1'b1);

assign sel_tmp17_fu_378_p2 = (ap_pipeline_reg_pp0_iter5_tmp_2_reg_981 & sel_tmp16_fu_372_p2);

assign sel_tmp18_demorgan_fu_269_p2 = (tmp_s_fu_229_p2 | tmp_3_fu_234_p2);

assign sel_tmp18_fu_489_p3 = ((ap_pipeline_reg_pp0_iter7_sel_tmp17_reg_1146[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter7_p_Val2_1_reg_1106 : sel_tmp15_fu_484_p3);

assign sel_tmp19_fu_388_p2 = (sel_tmp42_demorgan_fu_383_p2 ^ 1'b1);

assign sel_tmp1_fu_264_p2 = (ap_pipeline_reg_pp0_iter4_tmp_2_reg_981 ^ 1'b1);

assign sel_tmp20_fu_394_p2 = (underflow_12_not_fu_275_p2 & sel_tmp19_fu_388_p2);

assign sel_tmp21_fu_400_p3 = ((sel_tmp9_fu_329_p2[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_2_reg_1014 : p_Val2_s_7_fu_297_p3);

assign sel_tmp22_fu_407_p3 = ((sel_tmp5_fu_338_p2[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_reg_1007 : sel_tmp21_fu_400_p3);

assign sel_tmp23_fu_414_p3 = ((sel_tmp7_fu_343_p2[0:0] === 1'b1) ? ap_const_lv18_0 : sel_tmp22_fu_407_p3);

assign sel_tmp24_fu_455_p3 = ((sel_tmp12_reg_1134[0:0] === 1'b1) ? p_Val2_1_reg_1106 : sel_tmp23_reg_1158);

assign sel_tmp25_fu_460_p3 = ((sel_tmp14_reg_1140[0:0] === 1'b1) ? p_Val2_77_mux_fu_425_p3 : sel_tmp24_fu_455_p3);

assign sel_tmp26_fu_467_p3 = ((sel_tmp17_reg_1146[0:0] === 1'b1) ? ap_const_lv18_0 : sel_tmp25_fu_460_p3);

assign sel_tmp2_fu_316_p2 = (underflow_12_not_fu_275_p2 & sel_tmp1_reg_1084);

assign sel_tmp33_demorgan_fu_368_p2 = (sel_tmp18_demorgan_reg_1090 | tmp_6_reg_1063);

assign sel_tmp3_fu_431_p3 = ((sel_tmp9_reg_1119[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter6_dds_0_cos_lut_V_load_reg_1007 : p_Val2_1_reg_1106);

assign sel_tmp42_demorgan_fu_383_p2 = (sel_tmp33_demorgan_fu_368_p2 | ap_pipeline_reg_pp0_iter5_tmp_2_reg_981);

assign sel_tmp4_fu_333_p2 = (tmp_s_reg_1051 ^ 1'b1);

assign sel_tmp5_fu_338_p2 = (tmp_3_reg_1058 & sel_tmp4_fu_333_p2);

assign sel_tmp6_fu_436_p3 = ((sel_tmp5_reg_1124[0:0] === 1'b1) ? p_Val2_0_i_i1_reg_1114 : sel_tmp3_fu_431_p3);

assign sel_tmp7_fu_343_p2 = (tmp_s_reg_1051 & ap_pipeline_reg_pp0_iter5_tmp_2_reg_981);

assign sel_tmp8_fu_442_p3 = ((sel_tmp7_reg_1129[0:0] === 1'b1) ? ap_pipeline_reg_pp0_iter6_dds_0_cos_lut_V_load_reg_1007 : sel_tmp6_fu_436_p3);

assign sel_tmp9_fu_329_p2 = (tmp_s_reg_1051 & sel_tmp1_reg_1084);

assign sel_tmp_fu_309_p3 = ((ap_pipeline_reg_pp0_iter5_tmp_2_reg_981[0:0] === 1'b1) ? ap_const_lv18_0 : p_Val2_s_7_fu_297_p3);

assign sin_adr_V_fu_169_p2 = (ap_const_lv10_0 - lsb_V_reg_959);

assign sin_dds_V_fu_910_p3 = ((brmerge7_fu_892_p2[0:0] === 1'b1) ? p_Val2_91_mux_fu_897_p3 : p_Val2_5_10_fu_904_p3);

assign tmp9_fu_838_p2 = (tmp_22_fu_833_p2 & tmp_24_reg_1338);

assign tmp_11_fu_610_p1 = qb_assign_1_fu_604_p2;

assign tmp_12_fu_688_p2 = (newsignbit_reg_1289 ^ 1'b1);

assign tmp_13_fu_698_p2 = (ap_pipeline_reg_pp0_iter14_signbit_reg_1228 ^ 1'b1);

assign tmp_14_fu_813_p2 = (ap_pipeline_reg_pp0_iter15_newsignbit_reg_1289 | p_Result_2_not_fu_808_p2);

assign tmp_15_fu_737_p2 = ((tmp_35_reg_1297 == ap_const_lv15_0) ? 1'b1 : 1'b0);

assign tmp_16_fu_742_p2 = (tmp_15_fu_737_p2 | brmerge40_i_fu_731_p2);

assign tmp_17_fu_521_p3 = {{ap_pipeline_reg_pp0_iter10_p_Val2_1_8_reg_1173}, {ap_const_lv25_0}};

assign tmp_19_fu_666_p1 = qb_assign_3_fu_660_p2;

assign tmp_1_fu_174_p1 = ap_pipeline_reg_pp0_iter1_lsb_V_reg_959;

assign tmp_20_fu_748_p2 = (newsignbit_1_reg_1308 ^ 1'b1);

assign tmp_21_fu_758_p2 = (ap_pipeline_reg_pp0_iter14_signbit_1_reg_1254 ^ 1'b1);

assign tmp_22_fu_833_p2 = (ap_pipeline_reg_pp0_iter15_newsignbit_1_reg_1308 | p_Result_11_not_fu_828_p2);

assign tmp_23_fu_797_p2 = ((tmp_42_reg_1316 == ap_const_lv15_0) ? 1'b1 : 1'b0);

assign tmp_24_fu_802_p2 = (tmp_23_fu_797_p2 | brmerge40_i1_fu_791_p2);

assign tmp_27_fu_221_p1 = p_Val2_5_fu_193_p2[16:0];

assign tmp_28_fu_225_p1 = p_Val2_7_fu_207_p2[16:0];

assign tmp_2_fu_178_p2 = ((ap_pipeline_reg_pp0_iter1_lsb_V_reg_959 == ap_const_lv10_0) ? 1'b1 : 1'b0);

assign tmp_31_fu_539_p1 = grp_fu_930_p3[25:0];

assign tmp_33_fu_592_p3 = ap_pipeline_reg_pp0_iter13_p_Val2_9_reg_1221[ap_const_lv32_1B];

assign tmp_35_fu_628_p1 = p_Val2_11_fu_614_p2[14:0];

assign tmp_38_fu_556_p1 = grp_fu_941_p3[25:0];

assign tmp_3_fu_234_p2 = ((ap_pipeline_reg_pp0_iter4_msb_V_reg_952 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign tmp_40_fu_648_p3 = ap_pipeline_reg_pp0_iter13_p_Val2_13_reg_1247[ap_const_lv32_1B];

assign tmp_42_fu_684_p1 = p_Val2_15_fu_670_p2[14:0];

assign tmp_4_fu_183_p1 = sin_adr_V_reg_971;

assign tmp_5_fu_244_p2 = ((tmp_27_reg_1041 == ap_const_lv17_0) ? 1'b1 : 1'b0);

assign tmp_6_fu_239_p2 = ((ap_pipeline_reg_pp0_iter4_msb_V_reg_952 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign tmp_7_fu_254_p2 = ((tmp_28_reg_1046 == ap_const_lv17_0) ? 1'b1 : 1'b0);

assign tmp_8_fu_480_p1 = ap_pipeline_reg_pp0_iter6_p_Result_8_reg_966;

assign tmp_9_fu_510_p3 = {{ap_pipeline_reg_pp0_iter10_p_Val2_8_reg_1184}, {ap_const_lv25_0}};

assign tmp_fu_818_p2 = (tmp_14_fu_813_p2 & tmp_16_reg_1327);

assign tmp_s_fu_229_p2 = ((ap_pipeline_reg_pp0_iter4_msb_V_reg_952 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign underflow_12_not_fu_275_p2 = (underflow_reg_1069 ^ 1'b1);

assign underflow_14_not_fu_292_p2 = (underflow_1_reg_1076 ^ 1'b1);

assign underflow_16_not_fu_852_p2 = (underflow_2_reg_1343 ^ 1'b1);

assign underflow_17_not_fu_887_p2 = (underflow_3_reg_1350 ^ 1'b1);

assign underflow_1_fu_259_p2 = (isneg_1_reg_1036 & tmp_7_fu_254_p2);

assign underflow_2_fu_823_p2 = (tmp_fu_818_p2 & ap_pipeline_reg_pp0_iter15_signbit_reg_1228);

assign underflow_3_fu_843_p2 = (tmp9_fu_838_p2 & ap_pipeline_reg_pp0_iter15_signbit_1_reg_1254);

assign underflow_fu_249_p2 = (isneg_reg_1025 & tmp_5_fu_244_p2);

always @ (posedge ap_clk) begin
    dds_0_cos_lut_V_load_reg_1007[17] <= 1'b0;
    ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_reg_1007[17] <= 1'b0;
    ap_pipeline_reg_pp0_iter6_dds_0_cos_lut_V_load_reg_1007[17] <= 1'b0;
    dds_0_cos_lut_V_load_2_reg_1014[17] <= 1'b0;
    ap_pipeline_reg_pp0_iter5_dds_0_cos_lut_V_load_2_reg_1014[17] <= 1'b0;
    p_Val2_0_i_i_cast_reg_1163[17] <= 1'b0;
end

endmodule //process_r


// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.3
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================

`timescale 1 ns / 1 ps
module process_r_dds_0_cbkb_rom (
addr0, ce0, q0, addr1, ce1, q1, clk);

parameter DWIDTH = 17;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;

input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;

reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];

initial begin
    $readmemh("./process_r_dds_0_cbkb_rom.dat", ram);
end

always @(posedge clk)
begin
    if (ce0)
    begin
        q0 <= ram[addr0];
    end
end

always @(posedge clk)
begin
    if (ce1)
    begin
        q1 <= ram[addr1];
    end
end

endmodule

`timescale 1 ns / 1 ps
module process_r_dds_0_cbkb(
    reset,
    clk,
    address0,
    ce0,
    q0,
    address1,
    ce1,
    q1);

parameter DataWidth = 32'd17;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;

process_r_dds_0_cbkb_rom process_r_dds_0_cbkb_rom_U(
    .clk( clk ),
    .addr0( address0 ),
    .ce0( ce0 ),
    .q0( q0 ),
    .addr1( address1 ),
    .ce1( ce1 ),
    .q1( q1 ));

endmodule


// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.3
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================

`timescale 1 ns / 1 ps
module process_r_dds_0_fcud_rom (
addr0, ce0, q0, clk);

parameter DWIDTH = 16;
parameter AWIDTH = 9;
parameter MEM_SIZE = 512;

input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;

reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];

initial begin
    $readmemh("./process_r_dds_0_fcud_rom.dat", ram);
end

always @(posedge clk)
begin
    if (ce0)
    begin
        q0 <= ram[addr0];
    end
end

endmodule

`timescale 1 ns / 1 ps
module process_r_dds_0_fcud(
    reset,
    clk,
    address0,
    ce0,
    q0);

parameter DataWidth = 32'd16;
parameter AddressRange = 32'd512;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;

process_r_dds_0_fcud_rom process_r_dds_0_fcud_rom_U(
    .clk( clk ),
    .addr0( address0 ),
    .ce0( ce0 ),
    .q0( q0 ));

endmodule