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// IP VLNV: xilinx.com:ip:xsdbm:3.0
// IP Revision: 0

`timescale 1ns/1ps

(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_a493_xsdbm_0 (
  update,
  capture,
  reset,
  runtest,
  tck,
  tms,
  tdi,
  sel,
  shift,
  drck,
  tdo,
  bscanid_en,
  clk
);

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan UPDATE" *)
input wire update;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan CAPTURE" *)
input wire capture;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan RESET" *)
input wire reset;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan RUNTEST" *)
input wire runtest;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TCK" *)
input wire tck;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TMS" *)
input wire tms;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TDI" *)
input wire tdi;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan SEL" *)
input wire sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan SHIFT" *)
input wire shift;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan DRCK" *)
input wire drck;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TDO" *)
output wire tdo;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN" *)
input wire bscanid_en;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_clock, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire clk;

  xsdbm_v3_0_0_xsdbm #(
    .C_FIFO_STYLE("SUBCORE"),
    .C_XDEVICEFAMILY("virtexuplus"),
    .C_MAJOR_VERSION(14),
    .C_MINOR_VERSION(1),
    .C_BUILD_REVISION(0),
    .C_CORE_MAJOR_VER(1),
    .C_CORE_MINOR_VER(0),
    .C_CORE_MINOR_ALPHA_VER(97),
    .C_XSDB_NUM_SLAVES(0),
    .C_XSDB_PERIOD_INT(10),
    .C_XSDB_PERIOD_FRC(0),
    .C_USE_BUFR(0),
    .C_DCLK_HAS_RESET(0),
    .C_EN_INT_SIM(1),
    .C_CORE_TYPE(1),
    .C_USER_SCAN_CHAIN(1),
    .C_CLKFBOUT_MULT_F(4.000),
    .C_DIVCLK_DIVIDE(1),
    .C_CLKOUT0_DIVIDE_F(12.000),
    .C_CLK_INPUT_FREQ_HZ(300000000),
    .C_ENABLE_CLK_DIVIDER(0),
    .C_USE_EXT_BSCAN(1),
    .C_USE_STARTUP_CLK(0),
    .C_EN_BSCANID_VEC(0),
    .C_TWO_PRIM_MODE(0),
    .C_USER_SCAN_CHAIN1(1),
    .C_BSCANID(76546592),
    .C_BSCAN_MODE(0),
    .C_BSCAN_MODE_WITH_CORE(0),
    .C_NUM_BSCAN_MASTER_PORTS(0)
  ) inst (
    .sl_iport0_o(),
    .sl_iport1_o(),
    .sl_iport2_o(),
    .sl_iport3_o(),
    .sl_iport4_o(),
    .sl_iport5_o(),
    .sl_iport6_o(),
    .sl_iport7_o(),
    .sl_iport8_o(),
    .sl_iport9_o(),
    .sl_iport10_o(),
    .sl_iport11_o(),
    .sl_iport12_o(),
    .sl_iport13_o(),
    .sl_iport14_o(),
    .sl_iport15_o(),
    .sl_iport16_o(),
    .sl_iport17_o(),
    .sl_iport18_o(),
    .sl_iport19_o(),
    .sl_iport20_o(),
    .sl_iport21_o(),
    .sl_iport22_o(),
    .sl_iport23_o(),
    .sl_iport24_o(),
    .sl_iport25_o(),
    .sl_iport26_o(),
    .sl_iport27_o(),
    .sl_iport28_o(),
    .sl_iport29_o(),
    .sl_iport30_o(),
    .sl_iport31_o(),
    .sl_iport32_o(),
    .sl_iport33_o(),
    .sl_iport34_o(),
    .sl_iport35_o(),
    .sl_iport36_o(),
    .sl_iport37_o(),
    .sl_iport38_o(),
    .sl_iport39_o(),
    .sl_iport40_o(),
    .sl_iport41_o(),
    .sl_iport42_o(),
    .sl_iport43_o(),
    .sl_iport44_o(),
    .sl_iport45_o(),
    .sl_iport46_o(),
    .sl_iport47_o(),
    .sl_iport48_o(),
    .sl_iport49_o(),
    .sl_iport50_o(),
    .sl_iport51_o(),
    .sl_iport52_o(),
    .sl_iport53_o(),
    .sl_iport54_o(),
    .sl_iport55_o(),
    .sl_iport56_o(),
    .sl_iport57_o(),
    .sl_iport58_o(),
    .sl_iport59_o(),
    .sl_iport60_o(),
    .sl_iport61_o(),
    .sl_iport62_o(),
    .sl_iport63_o(),
    .sl_iport64_o(),
    .sl_iport65_o(),
    .sl_iport66_o(),
    .sl_iport67_o(),
    .sl_iport68_o(),
    .sl_iport69_o(),
    .sl_iport70_o(),
    .sl_iport71_o(),
    .sl_iport72_o(),
    .sl_iport73_o(),
    .sl_iport74_o(),
    .sl_iport75_o(),
    .sl_iport76_o(),
    .sl_iport77_o(),
    .sl_iport78_o(),
    .sl_iport79_o(),
    .sl_iport80_o(),
    .sl_iport81_o(),
    .sl_iport82_o(),
    .sl_iport83_o(),
    .sl_iport84_o(),
    .sl_iport85_o(),
    .sl_iport86_o(),
    .sl_iport87_o(),
    .sl_iport88_o(),
    .sl_iport89_o(),
    .sl_iport90_o(),
    .sl_iport91_o(),
    .sl_iport92_o(),
    .sl_iport93_o(),
    .sl_iport94_o(),
    .sl_iport95_o(),
    .sl_iport96_o(),
    .sl_iport97_o(),
    .sl_iport98_o(),
    .sl_iport99_o(),
    .sl_iport100_o(),
    .sl_iport101_o(),
    .sl_iport102_o(),
    .sl_iport103_o(),
    .sl_iport104_o(),
    .sl_iport105_o(),
    .sl_iport106_o(),
    .sl_iport107_o(),
    .sl_iport108_o(),
    .sl_iport109_o(),
    .sl_iport110_o(),
    .sl_iport111_o(),
    .sl_iport112_o(),
    .sl_iport113_o(),
    .sl_iport114_o(),
    .sl_iport115_o(),
    .sl_iport116_o(),
    .sl_iport117_o(),
    .sl_iport118_o(),
    .sl_iport119_o(),
    .sl_iport120_o(),
    .sl_iport121_o(),
    .sl_iport122_o(),
    .sl_iport123_o(),
    .sl_iport124_o(),
    .sl_iport125_o(),
    .sl_iport126_o(),
    .sl_iport127_o(),
    .sl_iport128_o(),
    .sl_iport129_o(),
    .sl_iport130_o(),
    .sl_iport131_o(),
    .sl_iport132_o(),
    .sl_iport133_o(),
    .sl_iport134_o(),
    .sl_iport135_o(),
    .sl_iport136_o(),
    .sl_iport137_o(),
    .sl_iport138_o(),
    .sl_iport139_o(),
    .sl_iport140_o(),
    .sl_iport141_o(),
    .sl_iport142_o(),
    .sl_iport143_o(),
    .sl_iport144_o(),
    .sl_iport145_o(),
    .sl_iport146_o(),
    .sl_iport147_o(),
    .sl_iport148_o(),
    .sl_iport149_o(),
    .sl_iport150_o(),
    .sl_iport151_o(),
    .sl_iport152_o(),
    .sl_iport153_o(),
    .sl_iport154_o(),
    .sl_iport155_o(),
    .sl_iport156_o(),
    .sl_iport157_o(),
    .sl_iport158_o(),
    .sl_iport159_o(),
    .sl_iport160_o(),
    .sl_iport161_o(),
    .sl_iport162_o(),
    .sl_iport163_o(),
    .sl_iport164_o(),
    .sl_iport165_o(),
    .sl_iport166_o(),
    .sl_iport167_o(),
    .sl_iport168_o(),
    .sl_iport169_o(),
    .sl_iport170_o(),
    .sl_iport171_o(),
    .sl_iport172_o(),
    .sl_iport173_o(),
    .sl_iport174_o(),
    .sl_iport175_o(),
    .sl_iport176_o(),
    .sl_iport177_o(),
    .sl_iport178_o(),
    .sl_iport179_o(),
    .sl_iport180_o(),
    .sl_iport181_o(),
    .sl_iport182_o(),
    .sl_iport183_o(),
    .sl_iport184_o(),
    .sl_iport185_o(),
    .sl_iport186_o(),
    .sl_iport187_o(),
    .sl_iport188_o(),
    .sl_iport189_o(),
    .sl_iport190_o(),
    .sl_iport191_o(),
    .sl_iport192_o(),
    .sl_iport193_o(),
    .sl_iport194_o(),
    .sl_iport195_o(),
    .sl_iport196_o(),
    .sl_iport197_o(),
    .sl_iport198_o(),
    .sl_iport199_o(),
    .sl_iport200_o(),
    .sl_iport201_o(),
    .sl_iport202_o(),
    .sl_iport203_o(),
    .sl_iport204_o(),
    .sl_iport205_o(),
    .sl_iport206_o(),
    .sl_iport207_o(),
    .sl_iport208_o(),
    .sl_iport209_o(),
    .sl_iport210_o(),
    .sl_iport211_o(),
    .sl_iport212_o(),
    .sl_iport213_o(),
    .sl_iport214_o(),
    .sl_iport215_o(),
    .sl_iport216_o(),
    .sl_iport217_o(),
    .sl_iport218_o(),
    .sl_iport219_o(),
    .sl_iport220_o(),
    .sl_iport221_o(),
    .sl_iport222_o(),
    .sl_iport223_o(),
    .sl_iport224_o(),
    .sl_iport225_o(),
    .sl_iport226_o(),
    .sl_iport227_o(),
    .sl_iport228_o(),
    .sl_iport229_o(),
    .sl_iport230_o(),
    .sl_iport231_o(),
    .sl_iport232_o(),
    .sl_iport233_o(),
    .sl_iport234_o(),
    .sl_iport235_o(),
    .sl_iport236_o(),
    .sl_iport237_o(),
    .sl_iport238_o(),
    .sl_iport239_o(),
    .sl_iport240_o(),
    .sl_iport241_o(),
    .sl_iport242_o(),
    .sl_iport243_o(),
    .sl_iport244_o(),
    .sl_iport245_o(),
    .sl_iport246_o(),
    .sl_iport247_o(),
    .sl_iport248_o(),
    .sl_iport249_o(),
    .sl_iport250_o(),
    .sl_iport251_o(),
    .sl_iport252_o(),
    .sl_iport253_o(),
    .sl_iport254_o(),
    .sl_iport255_o(),
    .sl_oport0_i(1'B0),
    .sl_oport1_i(1'B0),
    .sl_oport2_i(1'B0),
    .sl_oport3_i(1'B0),
    .sl_oport4_i(1'B0),
    .sl_oport5_i(1'B0),
    .sl_oport6_i(1'B0),
    .sl_oport7_i(1'B0),
    .sl_oport8_i(1'B0),
    .sl_oport9_i(1'B0),
    .sl_oport10_i(1'B0),
    .sl_oport11_i(1'B0),
    .sl_oport12_i(1'B0),
    .sl_oport13_i(1'B0),
    .sl_oport14_i(1'B0),
    .sl_oport15_i(1'B0),
    .sl_oport16_i(1'B0),
    .sl_oport17_i(1'B0),
    .sl_oport18_i(1'B0),
    .sl_oport19_i(1'B0),
    .sl_oport20_i(1'B0),
    .sl_oport21_i(1'B0),
    .sl_oport22_i(1'B0),
    .sl_oport23_i(1'B0),
    .sl_oport24_i(1'B0),
    .sl_oport25_i(1'B0),
    .sl_oport26_i(1'B0),
    .sl_oport27_i(1'B0),
    .sl_oport28_i(1'B0),
    .sl_oport29_i(1'B0),
    .sl_oport30_i(1'B0),
    .sl_oport31_i(1'B0),
    .sl_oport32_i(1'B0),
    .sl_oport33_i(1'B0),
    .sl_oport34_i(1'B0),
    .sl_oport35_i(1'B0),
    .sl_oport36_i(1'B0),
    .sl_oport37_i(1'B0),
    .sl_oport38_i(1'B0),
    .sl_oport39_i(1'B0),
    .sl_oport40_i(1'B0),
    .sl_oport41_i(1'B0),
    .sl_oport42_i(1'B0),
    .sl_oport43_i(1'B0),
    .sl_oport44_i(1'B0),
    .sl_oport45_i(1'B0),
    .sl_oport46_i(1'B0),
    .sl_oport47_i(1'B0),
    .sl_oport48_i(1'B0),
    .sl_oport49_i(1'B0),
    .sl_oport50_i(1'B0),
    .sl_oport51_i(1'B0),
    .sl_oport52_i(1'B0),
    .sl_oport53_i(1'B0),
    .sl_oport54_i(1'B0),
    .sl_oport55_i(1'B0),
    .sl_oport56_i(1'B0),
    .sl_oport57_i(1'B0),
    .sl_oport58_i(1'B0),
    .sl_oport59_i(1'B0),
    .sl_oport60_i(1'B0),
    .sl_oport61_i(1'B0),
    .sl_oport62_i(1'B0),
    .sl_oport63_i(1'B0),
    .sl_oport64_i(1'B0),
    .sl_oport65_i(1'B0),
    .sl_oport66_i(1'B0),
    .sl_oport67_i(1'B0),
    .sl_oport68_i(1'B0),
    .sl_oport69_i(1'B0),
    .sl_oport70_i(1'B0),
    .sl_oport71_i(1'B0),
    .sl_oport72_i(1'B0),
    .sl_oport73_i(1'B0),
    .sl_oport74_i(1'B0),
    .sl_oport75_i(1'B0),
    .sl_oport76_i(1'B0),
    .sl_oport77_i(1'B0),
    .sl_oport78_i(1'B0),
    .sl_oport79_i(1'B0),
    .sl_oport80_i(1'B0),
    .sl_oport81_i(1'B0),
    .sl_oport82_i(1'B0),
    .sl_oport83_i(1'B0),
    .sl_oport84_i(1'B0),
    .sl_oport85_i(1'B0),
    .sl_oport86_i(1'B0),
    .sl_oport87_i(1'B0),
    .sl_oport88_i(1'B0),
    .sl_oport89_i(1'B0),
    .sl_oport90_i(1'B0),
    .sl_oport91_i(1'B0),
    .sl_oport92_i(1'B0),
    .sl_oport93_i(1'B0),
    .sl_oport94_i(1'B0),
    .sl_oport95_i(1'B0),
    .sl_oport96_i(1'B0),
    .sl_oport97_i(1'B0),
    .sl_oport98_i(1'B0),
    .sl_oport99_i(1'B0),
    .sl_oport100_i(1'B0),
    .sl_oport101_i(1'B0),
    .sl_oport102_i(1'B0),
    .sl_oport103_i(1'B0),
    .sl_oport104_i(1'B0),
    .sl_oport105_i(1'B0),
    .sl_oport106_i(1'B0),
    .sl_oport107_i(1'B0),
    .sl_oport108_i(1'B0),
    .sl_oport109_i(1'B0),
    .sl_oport110_i(1'B0),
    .sl_oport111_i(1'B0),
    .sl_oport112_i(1'B0),
    .sl_oport113_i(1'B0),
    .sl_oport114_i(1'B0),
    .sl_oport115_i(1'B0),
    .sl_oport116_i(1'B0),
    .sl_oport117_i(1'B0),
    .sl_oport118_i(1'B0),
    .sl_oport119_i(1'B0),
    .sl_oport120_i(1'B0),
    .sl_oport121_i(1'B0),
    .sl_oport122_i(1'B0),
    .sl_oport123_i(1'B0),
    .sl_oport124_i(1'B0),
    .sl_oport125_i(1'B0),
    .sl_oport126_i(1'B0),
    .sl_oport127_i(1'B0),
    .sl_oport128_i(1'B0),
    .sl_oport129_i(1'B0),
    .sl_oport130_i(1'B0),
    .sl_oport131_i(1'B0),
    .sl_oport132_i(1'B0),
    .sl_oport133_i(1'B0),
    .sl_oport134_i(1'B0),
    .sl_oport135_i(1'B0),
    .sl_oport136_i(1'B0),
    .sl_oport137_i(1'B0),
    .sl_oport138_i(1'B0),
    .sl_oport139_i(1'B0),
    .sl_oport140_i(1'B0),
    .sl_oport141_i(1'B0),
    .sl_oport142_i(1'B0),
    .sl_oport143_i(1'B0),
    .sl_oport144_i(1'B0),
    .sl_oport145_i(1'B0),
    .sl_oport146_i(1'B0),
    .sl_oport147_i(1'B0),
    .sl_oport148_i(1'B0),
    .sl_oport149_i(1'B0),
    .sl_oport150_i(1'B0),
    .sl_oport151_i(1'B0),
    .sl_oport152_i(1'B0),
    .sl_oport153_i(1'B0),
    .sl_oport154_i(1'B0),
    .sl_oport155_i(1'B0),
    .sl_oport156_i(1'B0),
    .sl_oport157_i(1'B0),
    .sl_oport158_i(1'B0),
    .sl_oport159_i(1'B0),
    .sl_oport160_i(1'B0),
    .sl_oport161_i(1'B0),
    .sl_oport162_i(1'B0),
    .sl_oport163_i(1'B0),
    .sl_oport164_i(1'B0),
    .sl_oport165_i(1'B0),
    .sl_oport166_i(1'B0),
    .sl_oport167_i(1'B0),
    .sl_oport168_i(1'B0),
    .sl_oport169_i(1'B0),
    .sl_oport170_i(1'B0),
    .sl_oport171_i(1'B0),
    .sl_oport172_i(1'B0),
    .sl_oport173_i(1'B0),
    .sl_oport174_i(1'B0),
    .sl_oport175_i(1'B0),
    .sl_oport176_i(1'B0),
    .sl_oport177_i(1'B0),
    .sl_oport178_i(1'B0),
    .sl_oport179_i(1'B0),
    .sl_oport180_i(1'B0),
    .sl_oport181_i(1'B0),
    .sl_oport182_i(1'B0),
    .sl_oport183_i(1'B0),
    .sl_oport184_i(1'B0),
    .sl_oport185_i(1'B0),
    .sl_oport186_i(1'B0),
    .sl_oport187_i(1'B0),
    .sl_oport188_i(1'B0),
    .sl_oport189_i(1'B0),
    .sl_oport190_i(1'B0),
    .sl_oport191_i(1'B0),
    .sl_oport192_i(1'B0),
    .sl_oport193_i(1'B0),
    .sl_oport194_i(1'B0),
    .sl_oport195_i(1'B0),
    .sl_oport196_i(1'B0),
    .sl_oport197_i(1'B0),
    .sl_oport198_i(1'B0),
    .sl_oport199_i(1'B0),
    .sl_oport200_i(1'B0),
    .sl_oport201_i(1'B0),
    .sl_oport202_i(1'B0),
    .sl_oport203_i(1'B0),
    .sl_oport204_i(1'B0),
    .sl_oport205_i(1'B0),
    .sl_oport206_i(1'B0),
    .sl_oport207_i(1'B0),
    .sl_oport208_i(1'B0),
    .sl_oport209_i(1'B0),
    .sl_oport210_i(1'B0),
    .sl_oport211_i(1'B0),
    .sl_oport212_i(1'B0),
    .sl_oport213_i(1'B0),
    .sl_oport214_i(1'B0),
    .sl_oport215_i(1'B0),
    .sl_oport216_i(1'B0),
    .sl_oport217_i(1'B0),
    .sl_oport218_i(1'B0),
    .sl_oport219_i(1'B0),
    .sl_oport220_i(1'B0),
    .sl_oport221_i(1'B0),
    .sl_oport222_i(1'B0),
    .sl_oport223_i(1'B0),
    .sl_oport224_i(1'B0),
    .sl_oport225_i(1'B0),
    .sl_oport226_i(1'B0),
    .sl_oport227_i(1'B0),
    .sl_oport228_i(1'B0),
    .sl_oport229_i(1'B0),
    .sl_oport230_i(1'B0),
    .sl_oport231_i(1'B0),
    .sl_oport232_i(1'B0),
    .sl_oport233_i(1'B0),
    .sl_oport234_i(1'B0),
    .sl_oport235_i(1'B0),
    .sl_oport236_i(1'B0),
    .sl_oport237_i(1'B0),
    .sl_oport238_i(1'B0),
    .sl_oport239_i(1'B0),
    .sl_oport240_i(1'B0),
    .sl_oport241_i(1'B0),
    .sl_oport242_i(1'B0),
    .sl_oport243_i(1'B0),
    .sl_oport244_i(1'B0),
    .sl_oport245_i(1'B0),
    .sl_oport246_i(1'B0),
    .sl_oport247_i(1'B0),
    .sl_oport248_i(1'B0),
    .sl_oport249_i(1'B0),
    .sl_oport250_i(1'B0),
    .sl_oport251_i(1'B0),
    .sl_oport252_i(1'B0),
    .sl_oport253_i(1'B0),
    .sl_oport254_i(1'B0),
    .sl_oport255_i(1'B0),
    .update_0(),
    .capture_0(),
    .reset_0(),
    .runtest_0(),
    .tms_0(),
    .tck_0(),
    .tdi_0(),
    .sel_0(),
    .shift_0(),
    .drck_0(),
    .tdo_0(1'B0),
    .update_1(),
    .capture_1(),
    .reset_1(),
    .runtest_1(),
    .tms_1(),
    .tck_1(),
    .tdi_1(),
    .sel_1(),
    .shift_1(),
    .drck_1(),
    .tdo_1(1'B0),
    .update_2(),
    .capture_2(),
    .reset_2(),
    .runtest_2(),
    .tms_2(),
    .tck_2(),
    .tdi_2(),
    .sel_2(),
    .shift_2(),
    .drck_2(),
    .tdo_2(1'B0),
    .update_3(),
    .capture_3(),
    .reset_3(),
    .runtest_3(),
    .tms_3(),
    .tck_3(),
    .tdi_3(),
    .sel_3(),
    .shift_3(),
    .drck_3(),
    .tdo_3(1'B0),
    .update_4(),
    .capture_4(),
    .reset_4(),
    .runtest_4(),
    .tms_4(),
    .tck_4(),
    .tdi_4(),
    .sel_4(),
    .shift_4(),
    .drck_4(),
    .tdo_4(1'B0),
    .update_5(),
    .capture_5(),
    .reset_5(),
    .runtest_5(),
    .tms_5(),
    .tck_5(),
    .tdi_5(),
    .sel_5(),
    .shift_5(),
    .drck_5(),
    .tdo_5(1'B0),
    .update_6(),
    .capture_6(),
    .reset_6(),
    .runtest_6(),
    .tms_6(),
    .tck_6(),
    .tdi_6(),
    .sel_6(),
    .shift_6(),
    .drck_6(),
    .tdo_6(1'B0),
    .update_7(),
    .capture_7(),
    .reset_7(),
    .runtest_7(),
    .tms_7(),
    .tck_7(),
    .tdi_7(),
    .sel_7(),
    .shift_7(),
    .drck_7(),
    .tdo_7(1'B0),
    .update_8(),
    .capture_8(),
    .reset_8(),
    .runtest_8(),
    .tms_8(),
    .tck_8(),
    .tdi_8(),
    .sel_8(),
    .shift_8(),
    .drck_8(),
    .tdo_8(1'B0),
    .update_9(),
    .capture_9(),
    .reset_9(),
    .runtest_9(),
    .tms_9(),
    .tck_9(),
    .tdi_9(),
    .sel_9(),
    .shift_9(),
    .drck_9(),
    .tdo_9(1'B0),
    .update_10(),
    .capture_10(),
    .reset_10(),
    .runtest_10(),
    .tms_10(),
    .tck_10(),
    .tdi_10(),
    .sel_10(),
    .shift_10(),
    .drck_10(),
    .tdo_10(1'B0),
    .update_11(),
    .capture_11(),
    .reset_11(),
    .runtest_11(),
    .tms_11(),
    .tck_11(),
    .tdi_11(),
    .sel_11(),
    .shift_11(),
    .drck_11(),
    .tdo_11(1'B0),
    .update_12(),
    .capture_12(),
    .reset_12(),
    .runtest_12(),
    .tms_12(),
    .tck_12(),
    .tdi_12(),
    .sel_12(),
    .shift_12(),
    .drck_12(),
    .tdo_12(1'B0),
    .update_13(),
    .capture_13(),
    .reset_13(),
    .runtest_13(),
    .tms_13(),
    .tck_13(),
    .tdi_13(),
    .sel_13(),
    .shift_13(),
    .drck_13(),
    .tdo_13(1'B0),
    .update_14(),
    .capture_14(),
    .reset_14(),
    .runtest_14(),
    .tms_14(),
    .tck_14(),
    .tdi_14(),
    .sel_14(),
    .shift_14(),
    .drck_14(),
    .tdo_14(1'B0),
    .update_15(),
    .capture_15(),
    .reset_15(),
    .runtest_15(),
    .tms_15(),
    .tck_15(),
    .tdi_15(),
    .sel_15(),
    .shift_15(),
    .drck_15(),
    .tdo_15(1'B0),
    .bscanid_en_0(),
    .bscanid_en_1(),
    .bscanid_en_2(),
    .bscanid_en_3(),
    .bscanid_en_4(),
    .bscanid_en_5(),
    .bscanid_en_6(),
    .bscanid_en_7(),
    .bscanid_en_8(),
    .bscanid_en_9(),
    .bscanid_en_10(),
    .bscanid_en_11(),
    .bscanid_en_12(),
    .bscanid_en_13(),
    .bscanid_en_14(),
    .bscanid_en_15(),
    .bscanid_0(32'B0),
    .bscanid_1(32'B0),
    .bscanid_2(32'B0),
    .bscanid_3(32'B0),
    .bscanid_4(32'B0),
    .bscanid_5(32'B0),
    .bscanid_6(32'B0),
    .bscanid_7(32'B0),
    .bscanid_8(32'B0),
    .bscanid_9(32'B0),
    .bscanid_10(32'B0),
    .bscanid_11(32'B0),
    .bscanid_12(32'B0),
    .bscanid_13(32'B0),
    .bscanid_14(32'B0),
    .bscanid_15(32'B0),
    .update(update),
    .capture(capture),
    .reset(reset),
    .runtest(runtest),
    .tck(tck),
    .tms(tms),
    .tdi(tdi),
    .sel(sel),
    .shift(shift),
    .drck(drck),
    .tdo(tdo),
    .bscanid_en(bscanid_en),
    .bscanid(),
    .clk(clk)
  );
endmodule


// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

// IP VLNV: xilinx.com:ip:xsdbm:3.0
// IP Revision: 0

(* X_CORE_INFO = "xsdbm_v3_0_0_xsdbm,Vivado 2020.2" *)
(* CHECK_LICENSE_TYPE = "bd_a493_xsdbm_0,xsdbm_v3_0_0_xsdbm,{}" *)
(* CORE_GENERATION_INFO = "bd_a493_xsdbm_0,xsdbm_v3_0_0_xsdbm,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xsdbm,x_ipVersion=3.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FIFO_STYLE=SUBCORE,C_XDEVICEFAMILY=virtexuplus,C_MAJOR_VERSION=14,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=1,C_CORE_MINOR_VER=0,C_CORE_MINOR_ALPHA_VER=97,C_XSDB_NUM_SLAVES=0,C_XSDB_PERIOD_INT=10,C_XSDB_PERIOD_FRC=0,C_USE_BUFR=0,C_DCLK_HAS_RESET=0,C_EN_INT_SIM=1,C_CORE_TYPE=1,C_USER_SCAN_CHAIN\
=1,C_CLKFBOUT_MULT_F=4.000,C_DIVCLK_DIVIDE=1,C_CLKOUT0_DIVIDE_F=12.000,C_CLK_INPUT_FREQ_HZ=300000000,C_ENABLE_CLK_DIVIDER=0,C_USE_EXT_BSCAN=1,C_USE_STARTUP_CLK=0,C_EN_BSCANID_VEC=0,C_TWO_PRIM_MODE=0,C_USER_SCAN_CHAIN1=1,C_BSCANID=76546592,C_BSCAN_MODE=0,C_BSCAN_MODE_WITH_CORE=0,C_NUM_BSCAN_MASTER_PORTS=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_a493_xsdbm_0 (
  update,
  capture,
  reset,
  runtest,
  tck,
  tms,
  tdi,
  sel,
  shift,
  drck,
  tdo,
  bscanid_en,
  clk
);

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan UPDATE" *)
input wire update;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan CAPTURE" *)
input wire capture;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan RESET" *)
input wire reset;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan RUNTEST" *)
input wire runtest;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TCK" *)
input wire tck;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TMS" *)
input wire tms;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TDI" *)
input wire tdi;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan SEL" *)
input wire sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan SHIFT" *)
input wire shift;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan DRCK" *)
input wire drck;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TDO" *)
output wire tdo;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN" *)
input wire bscanid_en;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_clock, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire clk;

  xsdbm_v3_0_0_xsdbm #(
    .C_FIFO_STYLE("SUBCORE"),
    .C_XDEVICEFAMILY("virtexuplus"),
    .C_MAJOR_VERSION(14),
    .C_MINOR_VERSION(1),
    .C_BUILD_REVISION(0),
    .C_CORE_MAJOR_VER(1),
    .C_CORE_MINOR_VER(0),
    .C_CORE_MINOR_ALPHA_VER(97),
    .C_XSDB_NUM_SLAVES(0),
    .C_XSDB_PERIOD_INT(10),
    .C_XSDB_PERIOD_FRC(0),
    .C_USE_BUFR(0),
    .C_DCLK_HAS_RESET(0),
    .C_EN_INT_SIM(1),
    .C_CORE_TYPE(1),
    .C_USER_SCAN_CHAIN(1),
    .C_CLKFBOUT_MULT_F(4.000),
    .C_DIVCLK_DIVIDE(1),
    .C_CLKOUT0_DIVIDE_F(12.000),
    .C_CLK_INPUT_FREQ_HZ(300000000),
    .C_ENABLE_CLK_DIVIDER(0),
    .C_USE_EXT_BSCAN(1),
    .C_USE_STARTUP_CLK(0),
    .C_EN_BSCANID_VEC(0),
    .C_TWO_PRIM_MODE(0),
    .C_USER_SCAN_CHAIN1(1),
    .C_BSCANID(76546592),
    .C_BSCAN_MODE(0),
    .C_BSCAN_MODE_WITH_CORE(0),
    .C_NUM_BSCAN_MASTER_PORTS(0)
  ) inst (
    .sl_iport0_o(),
    .sl_iport1_o(),
    .sl_iport2_o(),
    .sl_iport3_o(),
    .sl_iport4_o(),
    .sl_iport5_o(),
    .sl_iport6_o(),
    .sl_iport7_o(),
    .sl_iport8_o(),
    .sl_iport9_o(),
    .sl_iport10_o(),
    .sl_iport11_o(),
    .sl_iport12_o(),
    .sl_iport13_o(),
    .sl_iport14_o(),
    .sl_iport15_o(),
    .sl_iport16_o(),
    .sl_iport17_o(),
    .sl_iport18_o(),
    .sl_iport19_o(),
    .sl_iport20_o(),
    .sl_iport21_o(),
    .sl_iport22_o(),
    .sl_iport23_o(),
    .sl_iport24_o(),
    .sl_iport25_o(),
    .sl_iport26_o(),
    .sl_iport27_o(),
    .sl_iport28_o(),
    .sl_iport29_o(),
    .sl_iport30_o(),
    .sl_iport31_o(),
    .sl_iport32_o(),
    .sl_iport33_o(),
    .sl_iport34_o(),
    .sl_iport35_o(),
    .sl_iport36_o(),
    .sl_iport37_o(),
    .sl_iport38_o(),
    .sl_iport39_o(),
    .sl_iport40_o(),
    .sl_iport41_o(),
    .sl_iport42_o(),
    .sl_iport43_o(),
    .sl_iport44_o(),
    .sl_iport45_o(),
    .sl_iport46_o(),
    .sl_iport47_o(),
    .sl_iport48_o(),
    .sl_iport49_o(),
    .sl_iport50_o(),
    .sl_iport51_o(),
    .sl_iport52_o(),
    .sl_iport53_o(),
    .sl_iport54_o(),
    .sl_iport55_o(),
    .sl_iport56_o(),
    .sl_iport57_o(),
    .sl_iport58_o(),
    .sl_iport59_o(),
    .sl_iport60_o(),
    .sl_iport61_o(),
    .sl_iport62_o(),
    .sl_iport63_o(),
    .sl_iport64_o(),
    .sl_iport65_o(),
    .sl_iport66_o(),
    .sl_iport67_o(),
    .sl_iport68_o(),
    .sl_iport69_o(),
    .sl_iport70_o(),
    .sl_iport71_o(),
    .sl_iport72_o(),
    .sl_iport73_o(),
    .sl_iport74_o(),
    .sl_iport75_o(),
    .sl_iport76_o(),
    .sl_iport77_o(),
    .sl_iport78_o(),
    .sl_iport79_o(),
    .sl_iport80_o(),
    .sl_iport81_o(),
    .sl_iport82_o(),
    .sl_iport83_o(),
    .sl_iport84_o(),
    .sl_iport85_o(),
    .sl_iport86_o(),
    .sl_iport87_o(),
    .sl_iport88_o(),
    .sl_iport89_o(),
    .sl_iport90_o(),
    .sl_iport91_o(),
    .sl_iport92_o(),
    .sl_iport93_o(),
    .sl_iport94_o(),
    .sl_iport95_o(),
    .sl_iport96_o(),
    .sl_iport97_o(),
    .sl_iport98_o(),
    .sl_iport99_o(),
    .sl_iport100_o(),
    .sl_iport101_o(),
    .sl_iport102_o(),
    .sl_iport103_o(),
    .sl_iport104_o(),
    .sl_iport105_o(),
    .sl_iport106_o(),
    .sl_iport107_o(),
    .sl_iport108_o(),
    .sl_iport109_o(),
    .sl_iport110_o(),
    .sl_iport111_o(),
    .sl_iport112_o(),
    .sl_iport113_o(),
    .sl_iport114_o(),
    .sl_iport115_o(),
    .sl_iport116_o(),
    .sl_iport117_o(),
    .sl_iport118_o(),
    .sl_iport119_o(),
    .sl_iport120_o(),
    .sl_iport121_o(),
    .sl_iport122_o(),
    .sl_iport123_o(),
    .sl_iport124_o(),
    .sl_iport125_o(),
    .sl_iport126_o(),
    .sl_iport127_o(),
    .sl_iport128_o(),
    .sl_iport129_o(),
    .sl_iport130_o(),
    .sl_iport131_o(),
    .sl_iport132_o(),
    .sl_iport133_o(),
    .sl_iport134_o(),
    .sl_iport135_o(),
    .sl_iport136_o(),
    .sl_iport137_o(),
    .sl_iport138_o(),
    .sl_iport139_o(),
    .sl_iport140_o(),
    .sl_iport141_o(),
    .sl_iport142_o(),
    .sl_iport143_o(),
    .sl_iport144_o(),
    .sl_iport145_o(),
    .sl_iport146_o(),
    .sl_iport147_o(),
    .sl_iport148_o(),
    .sl_iport149_o(),
    .sl_iport150_o(),
    .sl_iport151_o(),
    .sl_iport152_o(),
    .sl_iport153_o(),
    .sl_iport154_o(),
    .sl_iport155_o(),
    .sl_iport156_o(),
    .sl_iport157_o(),
    .sl_iport158_o(),
    .sl_iport159_o(),
    .sl_iport160_o(),
    .sl_iport161_o(),
    .sl_iport162_o(),
    .sl_iport163_o(),
    .sl_iport164_o(),
    .sl_iport165_o(),
    .sl_iport166_o(),
    .sl_iport167_o(),
    .sl_iport168_o(),
    .sl_iport169_o(),
    .sl_iport170_o(),
    .sl_iport171_o(),
    .sl_iport172_o(),
    .sl_iport173_o(),
    .sl_iport174_o(),
    .sl_iport175_o(),
    .sl_iport176_o(),
    .sl_iport177_o(),
    .sl_iport178_o(),
    .sl_iport179_o(),
    .sl_iport180_o(),
    .sl_iport181_o(),
    .sl_iport182_o(),
    .sl_iport183_o(),
    .sl_iport184_o(),
    .sl_iport185_o(),
    .sl_iport186_o(),
    .sl_iport187_o(),
    .sl_iport188_o(),
    .sl_iport189_o(),
    .sl_iport190_o(),
    .sl_iport191_o(),
    .sl_iport192_o(),
    .sl_iport193_o(),
    .sl_iport194_o(),
    .sl_iport195_o(),
    .sl_iport196_o(),
    .sl_iport197_o(),
    .sl_iport198_o(),
    .sl_iport199_o(),
    .sl_iport200_o(),
    .sl_iport201_o(),
    .sl_iport202_o(),
    .sl_iport203_o(),
    .sl_iport204_o(),
    .sl_iport205_o(),
    .sl_iport206_o(),
    .sl_iport207_o(),
    .sl_iport208_o(),
    .sl_iport209_o(),
    .sl_iport210_o(),
    .sl_iport211_o(),
    .sl_iport212_o(),
    .sl_iport213_o(),
    .sl_iport214_o(),
    .sl_iport215_o(),
    .sl_iport216_o(),
    .sl_iport217_o(),
    .sl_iport218_o(),
    .sl_iport219_o(),
    .sl_iport220_o(),
    .sl_iport221_o(),
    .sl_iport222_o(),
    .sl_iport223_o(),
    .sl_iport224_o(),
    .sl_iport225_o(),
    .sl_iport226_o(),
    .sl_iport227_o(),
    .sl_iport228_o(),
    .sl_iport229_o(),
    .sl_iport230_o(),
    .sl_iport231_o(),
    .sl_iport232_o(),
    .sl_iport233_o(),
    .sl_iport234_o(),
    .sl_iport235_o(),
    .sl_iport236_o(),
    .sl_iport237_o(),
    .sl_iport238_o(),
    .sl_iport239_o(),
    .sl_iport240_o(),
    .sl_iport241_o(),
    .sl_iport242_o(),
    .sl_iport243_o(),
    .sl_iport244_o(),
    .sl_iport245_o(),
    .sl_iport246_o(),
    .sl_iport247_o(),
    .sl_iport248_o(),
    .sl_iport249_o(),
    .sl_iport250_o(),
    .sl_iport251_o(),
    .sl_iport252_o(),
    .sl_iport253_o(),
    .sl_iport254_o(),
    .sl_iport255_o(),
    .sl_oport0_i(1'B0),
    .sl_oport1_i(1'B0),
    .sl_oport2_i(1'B0),
    .sl_oport3_i(1'B0),
    .sl_oport4_i(1'B0),
    .sl_oport5_i(1'B0),
    .sl_oport6_i(1'B0),
    .sl_oport7_i(1'B0),
    .sl_oport8_i(1'B0),
    .sl_oport9_i(1'B0),
    .sl_oport10_i(1'B0),
    .sl_oport11_i(1'B0),
    .sl_oport12_i(1'B0),
    .sl_oport13_i(1'B0),
    .sl_oport14_i(1'B0),
    .sl_oport15_i(1'B0),
    .sl_oport16_i(1'B0),
    .sl_oport17_i(1'B0),
    .sl_oport18_i(1'B0),
    .sl_oport19_i(1'B0),
    .sl_oport20_i(1'B0),
    .sl_oport21_i(1'B0),
    .sl_oport22_i(1'B0),
    .sl_oport23_i(1'B0),
    .sl_oport24_i(1'B0),
    .sl_oport25_i(1'B0),
    .sl_oport26_i(1'B0),
    .sl_oport27_i(1'B0),
    .sl_oport28_i(1'B0),
    .sl_oport29_i(1'B0),
    .sl_oport30_i(1'B0),
    .sl_oport31_i(1'B0),
    .sl_oport32_i(1'B0),
    .sl_oport33_i(1'B0),
    .sl_oport34_i(1'B0),
    .sl_oport35_i(1'B0),
    .sl_oport36_i(1'B0),
    .sl_oport37_i(1'B0),
    .sl_oport38_i(1'B0),
    .sl_oport39_i(1'B0),
    .sl_oport40_i(1'B0),
    .sl_oport41_i(1'B0),
    .sl_oport42_i(1'B0),
    .sl_oport43_i(1'B0),
    .sl_oport44_i(1'B0),
    .sl_oport45_i(1'B0),
    .sl_oport46_i(1'B0),
    .sl_oport47_i(1'B0),
    .sl_oport48_i(1'B0),
    .sl_oport49_i(1'B0),
    .sl_oport50_i(1'B0),
    .sl_oport51_i(1'B0),
    .sl_oport52_i(1'B0),
    .sl_oport53_i(1'B0),
    .sl_oport54_i(1'B0),
    .sl_oport55_i(1'B0),
    .sl_oport56_i(1'B0),
    .sl_oport57_i(1'B0),
    .sl_oport58_i(1'B0),
    .sl_oport59_i(1'B0),
    .sl_oport60_i(1'B0),
    .sl_oport61_i(1'B0),
    .sl_oport62_i(1'B0),
    .sl_oport63_i(1'B0),
    .sl_oport64_i(1'B0),
    .sl_oport65_i(1'B0),
    .sl_oport66_i(1'B0),
    .sl_oport67_i(1'B0),
    .sl_oport68_i(1'B0),
    .sl_oport69_i(1'B0),
    .sl_oport70_i(1'B0),
    .sl_oport71_i(1'B0),
    .sl_oport72_i(1'B0),
    .sl_oport73_i(1'B0),
    .sl_oport74_i(1'B0),
    .sl_oport75_i(1'B0),
    .sl_oport76_i(1'B0),
    .sl_oport77_i(1'B0),
    .sl_oport78_i(1'B0),
    .sl_oport79_i(1'B0),
    .sl_oport80_i(1'B0),
    .sl_oport81_i(1'B0),
    .sl_oport82_i(1'B0),
    .sl_oport83_i(1'B0),
    .sl_oport84_i(1'B0),
    .sl_oport85_i(1'B0),
    .sl_oport86_i(1'B0),
    .sl_oport87_i(1'B0),
    .sl_oport88_i(1'B0),
    .sl_oport89_i(1'B0),
    .sl_oport90_i(1'B0),
    .sl_oport91_i(1'B0),
    .sl_oport92_i(1'B0),
    .sl_oport93_i(1'B0),
    .sl_oport94_i(1'B0),
    .sl_oport95_i(1'B0),
    .sl_oport96_i(1'B0),
    .sl_oport97_i(1'B0),
    .sl_oport98_i(1'B0),
    .sl_oport99_i(1'B0),
    .sl_oport100_i(1'B0),
    .sl_oport101_i(1'B0),
    .sl_oport102_i(1'B0),
    .sl_oport103_i(1'B0),
    .sl_oport104_i(1'B0),
    .sl_oport105_i(1'B0),
    .sl_oport106_i(1'B0),
    .sl_oport107_i(1'B0),
    .sl_oport108_i(1'B0),
    .sl_oport109_i(1'B0),
    .sl_oport110_i(1'B0),
    .sl_oport111_i(1'B0),
    .sl_oport112_i(1'B0),
    .sl_oport113_i(1'B0),
    .sl_oport114_i(1'B0),
    .sl_oport115_i(1'B0),
    .sl_oport116_i(1'B0),
    .sl_oport117_i(1'B0),
    .sl_oport118_i(1'B0),
    .sl_oport119_i(1'B0),
    .sl_oport120_i(1'B0),
    .sl_oport121_i(1'B0),
    .sl_oport122_i(1'B0),
    .sl_oport123_i(1'B0),
    .sl_oport124_i(1'B0),
    .sl_oport125_i(1'B0),
    .sl_oport126_i(1'B0),
    .sl_oport127_i(1'B0),
    .sl_oport128_i(1'B0),
    .sl_oport129_i(1'B0),
    .sl_oport130_i(1'B0),
    .sl_oport131_i(1'B0),
    .sl_oport132_i(1'B0),
    .sl_oport133_i(1'B0),
    .sl_oport134_i(1'B0),
    .sl_oport135_i(1'B0),
    .sl_oport136_i(1'B0),
    .sl_oport137_i(1'B0),
    .sl_oport138_i(1'B0),
    .sl_oport139_i(1'B0),
    .sl_oport140_i(1'B0),
    .sl_oport141_i(1'B0),
    .sl_oport142_i(1'B0),
    .sl_oport143_i(1'B0),
    .sl_oport144_i(1'B0),
    .sl_oport145_i(1'B0),
    .sl_oport146_i(1'B0),
    .sl_oport147_i(1'B0),
    .sl_oport148_i(1'B0),
    .sl_oport149_i(1'B0),
    .sl_oport150_i(1'B0),
    .sl_oport151_i(1'B0),
    .sl_oport152_i(1'B0),
    .sl_oport153_i(1'B0),
    .sl_oport154_i(1'B0),
    .sl_oport155_i(1'B0),
    .sl_oport156_i(1'B0),
    .sl_oport157_i(1'B0),
    .sl_oport158_i(1'B0),
    .sl_oport159_i(1'B0),
    .sl_oport160_i(1'B0),
    .sl_oport161_i(1'B0),
    .sl_oport162_i(1'B0),
    .sl_oport163_i(1'B0),
    .sl_oport164_i(1'B0),
    .sl_oport165_i(1'B0),
    .sl_oport166_i(1'B0),
    .sl_oport167_i(1'B0),
    .sl_oport168_i(1'B0),
    .sl_oport169_i(1'B0),
    .sl_oport170_i(1'B0),
    .sl_oport171_i(1'B0),
    .sl_oport172_i(1'B0),
    .sl_oport173_i(1'B0),
    .sl_oport174_i(1'B0),
    .sl_oport175_i(1'B0),
    .sl_oport176_i(1'B0),
    .sl_oport177_i(1'B0),
    .sl_oport178_i(1'B0),
    .sl_oport179_i(1'B0),
    .sl_oport180_i(1'B0),
    .sl_oport181_i(1'B0),
    .sl_oport182_i(1'B0),
    .sl_oport183_i(1'B0),
    .sl_oport184_i(1'B0),
    .sl_oport185_i(1'B0),
    .sl_oport186_i(1'B0),
    .sl_oport187_i(1'B0),
    .sl_oport188_i(1'B0),
    .sl_oport189_i(1'B0),
    .sl_oport190_i(1'B0),
    .sl_oport191_i(1'B0),
    .sl_oport192_i(1'B0),
    .sl_oport193_i(1'B0),
    .sl_oport194_i(1'B0),
    .sl_oport195_i(1'B0),
    .sl_oport196_i(1'B0),
    .sl_oport197_i(1'B0),
    .sl_oport198_i(1'B0),
    .sl_oport199_i(1'B0),
    .sl_oport200_i(1'B0),
    .sl_oport201_i(1'B0),
    .sl_oport202_i(1'B0),
    .sl_oport203_i(1'B0),
    .sl_oport204_i(1'B0),
    .sl_oport205_i(1'B0),
    .sl_oport206_i(1'B0),
    .sl_oport207_i(1'B0),
    .sl_oport208_i(1'B0),
    .sl_oport209_i(1'B0),
    .sl_oport210_i(1'B0),
    .sl_oport211_i(1'B0),
    .sl_oport212_i(1'B0),
    .sl_oport213_i(1'B0),
    .sl_oport214_i(1'B0),
    .sl_oport215_i(1'B0),
    .sl_oport216_i(1'B0),
    .sl_oport217_i(1'B0),
    .sl_oport218_i(1'B0),
    .sl_oport219_i(1'B0),
    .sl_oport220_i(1'B0),
    .sl_oport221_i(1'B0),
    .sl_oport222_i(1'B0),
    .sl_oport223_i(1'B0),
    .sl_oport224_i(1'B0),
    .sl_oport225_i(1'B0),
    .sl_oport226_i(1'B0),
    .sl_oport227_i(1'B0),
    .sl_oport228_i(1'B0),
    .sl_oport229_i(1'B0),
    .sl_oport230_i(1'B0),
    .sl_oport231_i(1'B0),
    .sl_oport232_i(1'B0),
    .sl_oport233_i(1'B0),
    .sl_oport234_i(1'B0),
    .sl_oport235_i(1'B0),
    .sl_oport236_i(1'B0),
    .sl_oport237_i(1'B0),
    .sl_oport238_i(1'B0),
    .sl_oport239_i(1'B0),
    .sl_oport240_i(1'B0),
    .sl_oport241_i(1'B0),
    .sl_oport242_i(1'B0),
    .sl_oport243_i(1'B0),
    .sl_oport244_i(1'B0),
    .sl_oport245_i(1'B0),
    .sl_oport246_i(1'B0),
    .sl_oport247_i(1'B0),
    .sl_oport248_i(1'B0),
    .sl_oport249_i(1'B0),
    .sl_oport250_i(1'B0),
    .sl_oport251_i(1'B0),
    .sl_oport252_i(1'B0),
    .sl_oport253_i(1'B0),
    .sl_oport254_i(1'B0),
    .sl_oport255_i(1'B0),
    .update_0(),
    .capture_0(),
    .reset_0(),
    .runtest_0(),
    .tms_0(),
    .tck_0(),
    .tdi_0(),
    .sel_0(),
    .shift_0(),
    .drck_0(),
    .tdo_0(1'B0),
    .update_1(),
    .capture_1(),
    .reset_1(),
    .runtest_1(),
    .tms_1(),
    .tck_1(),
    .tdi_1(),
    .sel_1(),
    .shift_1(),
    .drck_1(),
    .tdo_1(1'B0),
    .update_2(),
    .capture_2(),
    .reset_2(),
    .runtest_2(),
    .tms_2(),
    .tck_2(),
    .tdi_2(),
    .sel_2(),
    .shift_2(),
    .drck_2(),
    .tdo_2(1'B0),
    .update_3(),
    .capture_3(),
    .reset_3(),
    .runtest_3(),
    .tms_3(),
    .tck_3(),
    .tdi_3(),
    .sel_3(),
    .shift_3(),
    .drck_3(),
    .tdo_3(1'B0),
    .update_4(),
    .capture_4(),
    .reset_4(),
    .runtest_4(),
    .tms_4(),
    .tck_4(),
    .tdi_4(),
    .sel_4(),
    .shift_4(),
    .drck_4(),
    .tdo_4(1'B0),
    .update_5(),
    .capture_5(),
    .reset_5(),
    .runtest_5(),
    .tms_5(),
    .tck_5(),
    .tdi_5(),
    .sel_5(),
    .shift_5(),
    .drck_5(),
    .tdo_5(1'B0),
    .update_6(),
    .capture_6(),
    .reset_6(),
    .runtest_6(),
    .tms_6(),
    .tck_6(),
    .tdi_6(),
    .sel_6(),
    .shift_6(),
    .drck_6(),
    .tdo_6(1'B0),
    .update_7(),
    .capture_7(),
    .reset_7(),
    .runtest_7(),
    .tms_7(),
    .tck_7(),
    .tdi_7(),
    .sel_7(),
    .shift_7(),
    .drck_7(),
    .tdo_7(1'B0),
    .update_8(),
    .capture_8(),
    .reset_8(),
    .runtest_8(),
    .tms_8(),
    .tck_8(),
    .tdi_8(),
    .sel_8(),
    .shift_8(),
    .drck_8(),
    .tdo_8(1'B0),
    .update_9(),
    .capture_9(),
    .reset_9(),
    .runtest_9(),
    .tms_9(),
    .tck_9(),
    .tdi_9(),
    .sel_9(),
    .shift_9(),
    .drck_9(),
    .tdo_9(1'B0),
    .update_10(),
    .capture_10(),
    .reset_10(),
    .runtest_10(),
    .tms_10(),
    .tck_10(),
    .tdi_10(),
    .sel_10(),
    .shift_10(),
    .drck_10(),
    .tdo_10(1'B0),
    .update_11(),
    .capture_11(),
    .reset_11(),
    .runtest_11(),
    .tms_11(),
    .tck_11(),
    .tdi_11(),
    .sel_11(),
    .shift_11(),
    .drck_11(),
    .tdo_11(1'B0),
    .update_12(),
    .capture_12(),
    .reset_12(),
    .runtest_12(),
    .tms_12(),
    .tck_12(),
    .tdi_12(),
    .sel_12(),
    .shift_12(),
    .drck_12(),
    .tdo_12(1'B0),
    .update_13(),
    .capture_13(),
    .reset_13(),
    .runtest_13(),
    .tms_13(),
    .tck_13(),
    .tdi_13(),
    .sel_13(),
    .shift_13(),
    .drck_13(),
    .tdo_13(1'B0),
    .update_14(),
    .capture_14(),
    .reset_14(),
    .runtest_14(),
    .tms_14(),
    .tck_14(),
    .tdi_14(),
    .sel_14(),
    .shift_14(),
    .drck_14(),
    .tdo_14(1'B0),
    .update_15(),
    .capture_15(),
    .reset_15(),
    .runtest_15(),
    .tms_15(),
    .tck_15(),
    .tdi_15(),
    .sel_15(),
    .shift_15(),
    .drck_15(),
    .tdo_15(1'B0),
    .bscanid_en_0(),
    .bscanid_en_1(),
    .bscanid_en_2(),
    .bscanid_en_3(),
    .bscanid_en_4(),
    .bscanid_en_5(),
    .bscanid_en_6(),
    .bscanid_en_7(),
    .bscanid_en_8(),
    .bscanid_en_9(),
    .bscanid_en_10(),
    .bscanid_en_11(),
    .bscanid_en_12(),
    .bscanid_en_13(),
    .bscanid_en_14(),
    .bscanid_en_15(),
    .bscanid_0(32'B0),
    .bscanid_1(32'B0),
    .bscanid_2(32'B0),
    .bscanid_3(32'B0),
    .bscanid_4(32'B0),
    .bscanid_5(32'B0),
    .bscanid_6(32'B0),
    .bscanid_7(32'B0),
    .bscanid_8(32'B0),
    .bscanid_9(32'B0),
    .bscanid_10(32'B0),
    .bscanid_11(32'B0),
    .bscanid_12(32'B0),
    .bscanid_13(32'B0),
    .bscanid_14(32'B0),
    .bscanid_15(32'B0),
    .update(update),
    .capture(capture),
    .reset(reset),
    .runtest(runtest),
    .tck(tck),
    .tms(tms),
    .tdi(tdi),
    .sel(sel),
    .shift(shift),
    .drck(drck),
    .tdo(tdo),
    .bscanid_en(bscanid_en),
    .bscanid(),
    .clk(clk)
  );
endmodule


`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
geSCzw9gYjFCv0Dn0YxOXxhH+GZFMePCQPK3AjT+zbjt1urPphGbRmSIP212qcXhU3u6qBayOOuP
zGTUOznyYQ==

`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
OnCSRn8bnLy+eSxgkIEXKk5zY3JDppSX+6N3lQVX9PeSypgnQ/2z4GTpmoL+rdMoco6U9R4G1u4m
E0xhKuM4ba9nEk7cLfAxOQqKqsWQrZaIEmzIr1ET+cp4jOMvYA/MsN4jh93kbuKcSDuJ8zN13DFX
RemIkmekhFjPkyUS5qM=

`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
MSBAO7tnsBVh2XpVImbQvPkv1Ik+6Bw1D0e9n6H/Bw1mXnRXzm0RzPaEYAIFuluPbWglTrw4pQSr
JI/DSdCg6087Xmb+Q5zKawFvuZahx4HgmrKxTL15lZwamiIpmu3LGyxaEH/VbYGM9Ky0jp5PyDKU
Jeskyx64XVUPlRklhMjIKCtYITsgROzqjs+d1jIc494zqnDADEz0msJP38WdzHgwLDQ0NamfpodX
BUqMR71hgPx1Rvdt7HagUbkfyaG3/12LxFvpAblT7W0W6RKBFEFgFrxWRFaDw+jzj4jgl9g+sjY0
cveJYAA4UpZJwPSDIWehjmS+mOinzlnl8UP7jw==

`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
UtIiSU3lZ1iUKAuaJuT083jLC5QokBuxbJC/zVsWXf8ozOCIDAvtpSufF02lDCCaNNheB40dXQFS
I8VBcTtdWzNr2vj/HmW17e10D6T6mqn/8t0HnWx9c3modRuXup0Too1mNTU5gTH+v3utogTO5ztm
HbJZ/+5ov0tPkaeJufJl5L/RZAfLmRnRYybtx5bbc7XiGyWaVk6KunsaWtX5zJtVnMeUOkg0N8oL
RBeyFp3tFqTN7ecNUp7zom6BjZ3fR6euRy36u1XviJsqBjcxzASI1k+bn2lDs3oEdXuMHoRvcuWL
mmMddzjwWr43L7YoB/WBz/Tw7t6iYI5B6imPUA==

`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
AMZ17uwJyVzW4KyzjD/YjCrX2GlLIDwW9HSuEat97pn8ZQ7QpDPhFLNx09klp1fHQ8yb1KlxCqpm
IjAljp4A5oQHWcBw/s+Xhtpin6GMDGjsmd5KmAD2J5DQmzqPazc0M8vNO+pGpCJogvWarX5XrP6U
56l9vH5mfyPmbT/09Kw=

`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
oAGTk8IFmmwAT5eT+h5xMK7MsqYCJnsMll3rq17njNu6wbVX2TAoOlVC5DzNg9T5ce7gVnuLuFG/
FgNSnTJx8TlbP73KxlDubmAVofR56G/yHzaJfJ0fwNhrfXm5AFgmFaKFPTKNkrG/qjdNuwUeA8p4
iHoj1zvPx50myVHXSpHLQ8n92DLWgMUX/57aPLbMHmYu/gsD0kHOuQ8Fr2Mi2DxufAvq1gzT0kc+
lxSntoseL+X1HLSvmKpEkR/sjaz6P9omIzqKlmOhvLeTZVEZcUtukVN1HTrlol+4/pTFDztcz0tZ
XqYZKVNB/igvn1iP/Fej8fpkaeJOrk1YgJZ6xw==

`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
HM0OWTHTT9qkiqicwldwQlaXCXhAavOkOLtzdsXybVEqcdGTuInS8Xvu2i7fjfGdnZjc+o4ZayFd
adCXUGMQZ+7u79Rm71DMtV7WL4PMhXZmItLJgXQmNzajU211AuWse/CyD7Am9ZDJuQcIK0fcqZQI
XVJU6sMESVWiSWdCuqkcQLSuSoBY7TVLmCDoTF9n7MlYfcxCkkK6d+2Xs/gjaWO59GZ3TbWhAQLc
9hHL9YUJUTzZ8yPC8tX+DLS/YrniD3lBpquxXGcl1FxHKFTSpMG/6pTH+7Y5u1s29iqS/KYCCOfR
Pqg3ikxxR4ywBL+umX+Ijv+Hqgol6tBnCkWh/g==

`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
DQuK/YuairmUNmnTZFN/Tbbjjk202ciTMNZWiES7z/c8BYrmlnBses/x7XzAVxFxOTns+S6gcbxv
lho3MoYQI3b1wxR93ymMpbFY2AAKqfTaYrt9nuBi+J66NUkNb4mO5Ysrmk/FyxUuVMw2JeKhCxVf
1Lkw2weXEA2RSHrWxd8764IFSbBqKoKUTMuqLxHovRaQHDy/mOdyefGG7/6ywGbKjVTlE8lXVH8E
8QodSYZ7p8uod81sVFzJL26a9Tqu+u2tOgD/WqMuxrio7zRkYYC5P+/FtxLC4GaIZ6LivaJuTLOF
bkAMneaa5dlfamLnRyzDXUCJu/DFpJtH5s1eLQ==

`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2020_08", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
DL1JbuaDxIhP8ir0jAdx6nea42/rMQ2VXG8PZEGqMkgF/yLmK8+UcPNvmkEnUbVxq6WNxCUUYBOO
eroUXvKd3hB7aza+lE1PkczDRQpe4dZWQ8yHCUSbqj/KnUKU7sMHOSk5MiYcbBazdC+B/zdSxJsr
sUmnOLgp/SqygmZW7/oDYMIYyOExEOrIPD4CH/xXZGlvuNs4OjdmaSus7kQp/iaUxQz03NGaMv3/
EuIfORb3j+mQPwXwEBQhecy81p8ky3bmOS0LK+CPuz0LF3VVvrDnnXUSBCWa2WW6t7burmoHvgPV
oB2jrvwkS6dNjRJ7CoyGvV0N6d60kiD0LjZg6Q==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 2400)
`pragma protect data_block
Nayj+Ml813fDniWORR2jtIBWLUnTKLU73quUTC0r5jwck/h8GoDq9XKw8BqI5v1J3nTgkNVm5atb
cAw/VaO3NkhfBheJQbSR69Nrz/dOO5tggQHH5bhiVgkyJ10J0IJijCkqHTEM7eqAUpRB+C+swn77
0UbAbjpA6iLxZtySLCkfu1IDmIuJVGQQu5gx5HhJOOS9sbBqYLpKFtMkq0ekmdT8uVsJas5Dn/rL
FK6cI0u3hF6jx7C6EuRP9bts5JinWmopHabvdIuMWogq/jEOmvK/YWa2F6a22JfPI9md2SGv001Z
NF3S+OFUqWLkWcQuQiK1EeStnUgfx0DKmP44Rh49vAuwvoCnEGtGPoJcuqCj8kkx2HperJBoPMXF
bwOXyBsVw8smubJpJUklj/jkYQU7Mhn0+1DDK4kkK06W5VS0PwpcHI/NCpCrtst2FFbkesNH2SsO
5KIGW+Cfb4QrEDe5XavyjtAdc7Kf/olEw1ZvNmIwyZXSdJcT54GFCi4KQPPRS9kiaadQLPQS/WUP
wP3P3JdX9YvFC5Sp1yq2sPWuL1eMLRyNl339wIhus+/wM5aQSDi/pHmJmMEl1YLUa+mN6EenORTG
5MU9xnSDDk5SD4ObbT9KWXjRTWogMOCapY1Tv1MWBzOTNzXGtVtAJBw4cxOHMG+OFF0yGvhE/AiV
UJBEeJzP8L2Bj71c8RCxIViFz07rXhaFlBxMGxkdgTscOVxJtGiXqO970qc+E+YhnpZrgzpPog3A
HIxK9BG2bcC2sSeQO+WCrtfMMdvVUNZHntYQpZozeGZF5OTZeeqs2I0PvZblmP7/srlzJ/JzetZ0
CpTygxJF6W9HlXHv9qS2in1MDX5LvPjFtN0zKGyxUv4X8CFSqcYRW0lPxKh8dQ8KfIf1/+JRuMUW
CO3I17UAoMQyc5PLA35Nis/x1CGOS2Zq5QgnlIBPpFv5JGoS0wKJ/bIyq0i0w+v4KWN5TrLYWJ84
sMf45/+/nnmUoNq90k8SrWlnr9pxaqXZeklZOtEGejWc0oYa3+O2lYV0522Cm+XAuCiLIx1oRyxa
+u6HnsKXvR9DGb1osgt9gANalMh//k8N88W7tvMLcXwdkFi3uvBg/oZZeRm+o8p5swkqfDh2gQuZ
GJ1QE8KWN8hTZ9fEsScunk4GbuTk3dg05a1sMGm1gkRzTfiEVCzyn5Hi3pFpbikjAO7g/FLU6yiZ
pKzI2Crm4XPWRCfhwxycS8r2s63JspfJUZBW7tfCcbmQHYqHgxL3ZiEIV4N4tCF6rLQe8eu8xVI4
/ReaCvAsFB9k7r6h7vh2b/kor3j4v+vAAZs3NBd5vlKFfHc3a2phzTdGn9/IodWpqPp66h+D0hMB
8NQHJ3785F0Znfee4XxCQdXvwh03Pq+vWOHfhxdV+GL/oYI5/3eX0cZlwNXNhgrBE/jjCvh+/qf+
EuYKKMASHjIYzBihs/pCIBjKCya9eF6CKxRfp3KTjZ2nu0k/P00aR1alNLtPJR6SD3wEBMa7yNgY
ByaV1EQovQeu24Klh9zavCXFUHc3h3j8MqHxZrNfI/eUyIDoEuURBHymJZ13GIYA+mWIFdrXIC84
SlX5spcjNcB+mHif2EzCB6nJP3AE9aq8cpOJcQjhkcPZHkg2t9l5F5EupuAFUvvfcTXN/y6F3qIr
ThqLyFGwSiGzZX0AwRaNpyXuZKQsNz1WTzj1BjvDSTF1//OlAgzx0F1UZOuh9Hzv4+IBl0yGCHiR
oGXeQvMTSxI1D0BcFoc61ga1nbv3+QY2aYafMEJ+LKq2sz3mGk0Vpzo+swUVCYeveAb11ugkLVq9
Ra5FHeyN5v+RwxysgCDPo+jBUyzguryY6OBJBtBUXJV3Vrg8TEC1JNfIuiaQGmXiWvUj7VD3fgFP
A/Pax3F+Unn9dJaEhfgG23dLGZyo/H32CTtiWZfkWBJV8/W3g040xdKdNl+Y7sBtjuGt0IdS8lWJ
bomc8CybMXpVp9SQkhVlf4135WYYZuozj6Kt0dv581TbcnOPMEkTrRnU/XCQOVj9mHD8kDE8BGPs
u1WPZBZQ1Tfgb5SDwQQf3XYTIQNAnDzjLrEPaxy7I36CFdPTpJXR+DrTmbYH416q/LusHMxfzhkE
w+OkHqm6czWhunOkfPBoECoA9j609E2s6JDyqqdyNGGw3KsGIu3zyudgD+AeIlbr5wvld3VhQu+k
GbD1GKPT9sOuQylU6aG0R75sAjP0/RSbLUhGUdAL1NeNa2Q5utBg4b7xY2znf8k43uQuH9gDftQK
MoCj+4M/kY5vFOehA+mgPmocoo8+ta7JVcwiLjJPyYN/N7RIRvu0bpPfTeQM+6DijB5NSetCHZeW
KLrP7l1+niGT/aEUEZej5w42fhW5sZHSiMRrLyLeDxPtaeUE82Q8OzcJqmXqsrFMkgyVYOS6vWRE
p8+5qxoxSzeQ36exOktW+E2/pJPFVJYv608U/e/KsJ18RpOpuwdPQeazasQl0zwh9u34LrhV6Hgs
G8DKy0o62/rCo+JVEb1RdF37hXvTDGFF//rlcyBQgVtwCOJFFL5geugUbu5A/8AzBEN9Pzw0vxPV
fUaRNNckCcVybD5F7BZ3ielbt42QOneOK6+07rP2GQq6wu4Kocbpi5WXkAwDwn9iEsJT6Vh3Xz9A
GjEIelxMlGde1Ett9oxHhKcMYEnPyv4evAmG7EErwlTCQd+vp8tPPTmVvXbIJEpz4ViA5GiW8eTI
k/BkHd7IGq64iYXdddJ63IxopIFrccFbADHVy2LXr73bfFWYkRzvShUlQXRs2nK8iLqkmlEeNa8u
xaG3JQj0CYQCzTlqrKFs7AK8b8BwqaXmZ3FB9Xfj65H3mkW01gIq4i7sdVBBe4FgjsQAPdA+QPyP
FymbOZEQQPblH3qHCFfiQ9DDi/zDZi26sar4BjLeoS6GuI2juEmSKZLMcHezPShGjMq7TDo25lD6
lTlVWv5FmEIE4aI6UTNu4lJ3xl7a4lWJea95qzcitsplCEQA3mhp4zu9euRzSrneC01njKmDnrPH
mqzSlSiWOcwitRn6BFaIcXktL6gU0l0wbOKHkv4u6Wd4kbpRfHuZGrrcUU9JHlIQn9e7Rhx3a8Le
WewZ4FHJqc4gDvS+d8JPbCOb0K5VOINAjyn78G8320oCOfCyv3IKlkmyNHvqFcKzpNFcaza/1v/w
wP46e8ZI
`pragma protect end_protected


// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

// IP VLNV: xilinx.com:ip:lut_buffer:2.0
// IP Revision: 0

`timescale 1ns/1ps

(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_a493_lut_buffer_0 (
  tdi_i,
  tms_i,
  tck_i,
  drck_i,
  sel_i,
  shift_i,
  update_i,
  capture_i,
  runtest_i,
  reset_i,
  bscanid_en_i,
  tdo_o,
  tdi_o,
  tms_o,
  tck_o,
  drck_o,
  sel_o,
  shift_o,
  update_o,
  capture_o,
  runtest_o,
  reset_o,
  bscanid_en_o,
  tdo_i
);

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TDI" *)
input wire tdi_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TMS" *)
input wire tms_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TCK" *)
input wire tck_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan DRCK" *)
input wire drck_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan SEL" *)
input wire sel_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan SHIFT" *)
input wire shift_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan UPDATE" *)
input wire update_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan CAPTURE" *)
input wire capture_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan RUNTEST" *)
input wire runtest_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan RESET" *)
input wire reset_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN" *)
input wire bscanid_en_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TDO" *)
output wire tdo_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan TDI" *)
output wire tdi_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan TMS" *)
output wire tms_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan TCK" *)
output wire tck_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan DRCK" *)
output wire drck_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan SEL" *)
output wire sel_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan SHIFT" *)
output wire shift_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan UPDATE" *)
output wire update_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan CAPTURE" *)
output wire capture_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan RUNTEST" *)
output wire runtest_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan RESET" *)
output wire reset_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan BSCANID_EN" *)
output wire bscanid_en_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan TDO" *)
input wire tdo_i;

  lut_buffer_v2_0_0_lut_buffer #(
    .C_EN_BSCANID_VEC(0)
  ) inst (
    .tdi_i(tdi_i),
    .tms_i(tms_i),
    .tck_i(tck_i),
    .drck_i(drck_i),
    .sel_i(sel_i),
    .shift_i(shift_i),
    .update_i(update_i),
    .capture_i(capture_i),
    .runtest_i(runtest_i),
    .reset_i(reset_i),
    .bscanid_en_i(bscanid_en_i),
    .tdo_o(tdo_o),
    .bscanid_o(),
    .tdi_o(tdi_o),
    .tms_o(tms_o),
    .tck_o(tck_o),
    .drck_o(drck_o),
    .sel_o(sel_o),
    .shift_o(shift_o),
    .update_o(update_o),
    .capture_o(capture_o),
    .runtest_o(runtest_o),
    .reset_o(reset_o),
    .bscanid_en_o(bscanid_en_o),
    .tdo_i(tdo_i),
    .bscanid_i(32'B0)
  );
endmodule


// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

// IP VLNV: xilinx.com:ip:lut_buffer:2.0
// IP Revision: 0

(* X_CORE_INFO = "lut_buffer_v2_0_0_lut_buffer,Vivado 2020.2" *)
(* CHECK_LICENSE_TYPE = "bd_a493_lut_buffer_0,lut_buffer_v2_0_0_lut_buffer,{}" *)
(* CORE_GENERATION_INFO = "bd_a493_lut_buffer_0,lut_buffer_v2_0_0_lut_buffer,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lut_buffer,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_BSCANID_VEC=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_a493_lut_buffer_0 (
  tdi_i,
  tms_i,
  tck_i,
  drck_i,
  sel_i,
  shift_i,
  update_i,
  capture_i,
  runtest_i,
  reset_i,
  bscanid_en_i,
  tdo_o,
  tdi_o,
  tms_o,
  tck_o,
  drck_o,
  sel_o,
  shift_o,
  update_o,
  capture_o,
  runtest_o,
  reset_o,
  bscanid_en_o,
  tdo_i
);

(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TDI" *)
input wire tdi_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TMS" *)
input wire tms_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TCK" *)
input wire tck_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan DRCK" *)
input wire drck_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan SEL" *)
input wire sel_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan SHIFT" *)
input wire shift_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan UPDATE" *)
input wire update_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan CAPTURE" *)
input wire capture_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan RUNTEST" *)
input wire runtest_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan RESET" *)
input wire reset_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan BSCANID_EN" *)
input wire bscanid_en_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 s_bscan TDO" *)
output wire tdo_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan TDI" *)
output wire tdi_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan TMS" *)
output wire tms_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan TCK" *)
output wire tck_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan DRCK" *)
output wire drck_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan SEL" *)
output wire sel_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan SHIFT" *)
output wire shift_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan UPDATE" *)
output wire update_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan CAPTURE" *)
output wire capture_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan RUNTEST" *)
output wire runtest_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan RESET" *)
output wire reset_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan BSCANID_EN" *)
output wire bscanid_en_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 m_bscan TDO" *)
input wire tdo_i;

  lut_buffer_v2_0_0_lut_buffer #(
    .C_EN_BSCANID_VEC(0)
  ) inst (
    .tdi_i(tdi_i),
    .tms_i(tms_i),
    .tck_i(tck_i),
    .drck_i(drck_i),
    .sel_i(sel_i),
    .shift_i(shift_i),
    .update_i(update_i),
    .capture_i(capture_i),
    .runtest_i(runtest_i),
    .reset_i(reset_i),
    .bscanid_en_i(bscanid_en_i),
    .tdo_o(tdo_o),
    .bscanid_o(),
    .tdi_o(tdi_o),
    .tms_o(tms_o),
    .tck_o(tck_o),
    .drck_o(drck_o),
    .sel_o(sel_o),
    .shift_o(shift_o),
    .update_o(update_o),
    .capture_o(capture_o),
    .runtest_o(runtest_o),
    .reset_o(reset_o),
    .bscanid_en_o(bscanid_en_o),
    .tdo_i(tdo_i),
    .bscanid_i(32'B0)
  );
endmodule


//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Command: generate_target bd_a493.bd
//Design : bd_a493
//Purpose: IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "bd_a493,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_a493,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "cl_debug_bridge.hwdef" *)
module bd_a493
   (S_BSCAN_bscanid_en,
    S_BSCAN_capture,
    S_BSCAN_drck,
    S_BSCAN_reset,
    S_BSCAN_runtest,
    S_BSCAN_sel,
    S_BSCAN_shift,
    S_BSCAN_tck,
    S_BSCAN_tdi,
    S_BSCAN_tdo,
    S_BSCAN_tms,
    S_BSCAN_update,
    clk);
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN" *) input S_BSCAN_bscanid_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE" *) input S_BSCAN_capture;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN DRCK" *) input S_BSCAN_drck;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN RESET" *) input S_BSCAN_reset;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST" *) input S_BSCAN_runtest;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN SEL" *) input S_BSCAN_sel;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT" *) input S_BSCAN_shift;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TCK" *) input S_BSCAN_tck;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TDI" *) input S_BSCAN_tdi;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TDO" *) output S_BSCAN_tdo;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TMS" *) input S_BSCAN_tms;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE" *) input S_BSCAN_update;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, CLK_DOMAIN bd_a493_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000" *) input clk;

  wire S_BSCAN_1_BSCANID_EN;
  wire S_BSCAN_1_CAPTURE;
  wire S_BSCAN_1_DRCK;
  wire S_BSCAN_1_RESET;
  wire S_BSCAN_1_RUNTEST;
  wire S_BSCAN_1_SEL;
  wire S_BSCAN_1_SHIFT;
  wire S_BSCAN_1_TCK;
  wire S_BSCAN_1_TDI;
  wire S_BSCAN_1_TDO;
  wire S_BSCAN_1_TMS;
  wire S_BSCAN_1_UPDATE;
  wire clk_1;
  wire lut_buffer_m_bscan_BSCANID_EN;
  wire lut_buffer_m_bscan_CAPTURE;
  wire lut_buffer_m_bscan_DRCK;
  wire lut_buffer_m_bscan_RESET;
  wire lut_buffer_m_bscan_RUNTEST;
  wire lut_buffer_m_bscan_SEL;
  wire lut_buffer_m_bscan_SHIFT;
  wire lut_buffer_m_bscan_TCK;
  wire lut_buffer_m_bscan_TDI;
  wire lut_buffer_m_bscan_TDO;
  wire lut_buffer_m_bscan_TMS;
  wire lut_buffer_m_bscan_UPDATE;

  assign S_BSCAN_1_BSCANID_EN = S_BSCAN_bscanid_en;
  assign S_BSCAN_1_CAPTURE = S_BSCAN_capture;
  assign S_BSCAN_1_DRCK = S_BSCAN_drck;
  assign S_BSCAN_1_RESET = S_BSCAN_reset;
  assign S_BSCAN_1_RUNTEST = S_BSCAN_runtest;
  assign S_BSCAN_1_SEL = S_BSCAN_sel;
  assign S_BSCAN_1_SHIFT = S_BSCAN_shift;
  assign S_BSCAN_1_TCK = S_BSCAN_tck;
  assign S_BSCAN_1_TDI = S_BSCAN_tdi;
  assign S_BSCAN_1_TMS = S_BSCAN_tms;
  assign S_BSCAN_1_UPDATE = S_BSCAN_update;
  assign S_BSCAN_tdo = S_BSCAN_1_TDO;
  assign clk_1 = clk;
  bd_a493_lut_buffer_0 lut_buffer
       (.bscanid_en_i(S_BSCAN_1_BSCANID_EN),
        .bscanid_en_o(lut_buffer_m_bscan_BSCANID_EN),
        .capture_i(S_BSCAN_1_CAPTURE),
        .capture_o(lut_buffer_m_bscan_CAPTURE),
        .drck_i(S_BSCAN_1_DRCK),
        .drck_o(lut_buffer_m_bscan_DRCK),
        .reset_i(S_BSCAN_1_RESET),
        .reset_o(lut_buffer_m_bscan_RESET),
        .runtest_i(S_BSCAN_1_RUNTEST),
        .runtest_o(lut_buffer_m_bscan_RUNTEST),
        .sel_i(S_BSCAN_1_SEL),
        .sel_o(lut_buffer_m_bscan_SEL),
        .shift_i(S_BSCAN_1_SHIFT),
        .shift_o(lut_buffer_m_bscan_SHIFT),
        .tck_i(S_BSCAN_1_TCK),
        .tck_o(lut_buffer_m_bscan_TCK),
        .tdi_i(S_BSCAN_1_TDI),
        .tdi_o(lut_buffer_m_bscan_TDI),
        .tdo_i(lut_buffer_m_bscan_TDO),
        .tdo_o(S_BSCAN_1_TDO),
        .tms_i(S_BSCAN_1_TMS),
        .tms_o(lut_buffer_m_bscan_TMS),
        .update_i(S_BSCAN_1_UPDATE),
        .update_o(lut_buffer_m_bscan_UPDATE));
  bd_a493_xsdbm_0 xsdbm
       (.bscanid_en(lut_buffer_m_bscan_BSCANID_EN),
        .capture(lut_buffer_m_bscan_CAPTURE),
        .clk(clk_1),
        .drck(lut_buffer_m_bscan_DRCK),
        .reset(lut_buffer_m_bscan_RESET),
        .runtest(lut_buffer_m_bscan_RUNTEST),
        .sel(lut_buffer_m_bscan_SEL),
        .shift(lut_buffer_m_bscan_SHIFT),
        .tck(lut_buffer_m_bscan_TCK),
        .tdi(lut_buffer_m_bscan_TDI),
        .tdo(lut_buffer_m_bscan_TDO),
        .tms(lut_buffer_m_bscan_TMS),
        .update(lut_buffer_m_bscan_UPDATE));
endmodule


// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

// IP VLNV: xilinx.com:ip:debug_bridge:3.0
// IP Revision: 6

`timescale 1ns/1ps

(* DowngradeIPIdentifiedWarnings = "yes" *)
module cl_debug_bridge (
  clk,
  S_BSCAN_bscanid_en,
  S_BSCAN_capture,
  S_BSCAN_drck,
  S_BSCAN_reset,
  S_BSCAN_runtest,
  S_BSCAN_sel,
  S_BSCAN_shift,
  S_BSCAN_tck,
  S_BSCAN_tdi,
  S_BSCAN_tdo,
  S_BSCAN_tms,
  S_BSCAN_update
);

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.clk CLK" *)
input wire clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN" *)
input wire S_BSCAN_bscanid_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE" *)
input wire S_BSCAN_capture;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN DRCK" *)
input wire S_BSCAN_drck;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN RESET" *)
input wire S_BSCAN_reset;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST" *)
input wire S_BSCAN_runtest;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN SEL" *)
input wire S_BSCAN_sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT" *)
input wire S_BSCAN_shift;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TCK" *)
input wire S_BSCAN_tck;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TDI" *)
input wire S_BSCAN_tdi;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TDO" *)
output wire S_BSCAN_tdo;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TMS" *)
input wire S_BSCAN_tms;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE" *)
input wire S_BSCAN_update;

  bd_a493 inst (
    .clk(clk),
    .S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),
    .S_BSCAN_capture(S_BSCAN_capture),
    .S_BSCAN_drck(S_BSCAN_drck),
    .S_BSCAN_reset(S_BSCAN_reset),
    .S_BSCAN_runtest(S_BSCAN_runtest),
    .S_BSCAN_sel(S_BSCAN_sel),
    .S_BSCAN_shift(S_BSCAN_shift),
    .S_BSCAN_tck(S_BSCAN_tck),
    .S_BSCAN_tdi(S_BSCAN_tdi),
    .S_BSCAN_tdo(S_BSCAN_tdo),
    .S_BSCAN_tms(S_BSCAN_tms),
    .S_BSCAN_update(S_BSCAN_update)
  );
endmodule


// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

// IP VLNV: xilinx.com:ip:debug_bridge:3.0
// IP Revision: 6

(* X_CORE_INFO = "bd_a493,Vivado 2020.2" *)
(* CHECK_LICENSE_TYPE = "cl_debug_bridge,bd_a493,{}" *)
(* CORE_GENERATION_INFO = "cl_debug_bridge,bd_a493,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=debug_bridge,x_ipVersion=3.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_DEBUG_MODE=1,C_NUM_BS_MASTER=0,C_BSCAN_MUX=1,C_EN_BSCANID_VEC=false,C_USE_EXT_BSCAN=true,C_USE_STARTUP_CLK=false,C_ENABLE_CLK_DIVIDER=false,C_TWO_PRIM_MODE=false,C_USER_SCAN_CHAIN=1,C_CORE_TYPE=1,C_EN_INT_SIM=1,C_DCLK_HAS_RESET=0,C_USE_BUFR=0,C_XSDB_NUM_SLAVES=0,C_CORE_MINOR_ALPHA_VER=97,C_CORE_MINOR_VER=0,C_\
CORE_MAJOR_VER=1,C_BUILD_REVISION=0,C_MINOR_VERSION=1,C_MAJOR_VERSION=14,C_FIFO_STYLE=SUBCORE,C_DESIGN_TYPE=0,C_MASTER_INTF_TYPE=1,C_EN_PASSTHROUGH=0,C_XVC_HW_ID=0x0001,C_XVC_SW_ID=0x0001,C_PCIE_EXT_CFG_BASE_ADDR=0x400,C_PCIE_EXT_CFG_VSEC_REV_ID=0x0,C_PCIE_EXT_CFG_VSEC_LENGTH=0x020,C_PCIE_EXT_CFG_NEXT_PTR=0x000,C_PCIE_EXT_CFG_VSEC_ID=0x0008,Component_Name=cl_debug_bridge,C_CLK_INPUT_FREQ_HZ=300000000,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5,C_TCK_CLOCK_RATIO=8,C_USE_SOFTBSCAN=1,C_DEVICE_FAMILY\
=0,C_IR_WIDTH=0,C_CHIP_ID=0,C_IR_ID_INSTR=0,C_IR_USER1_INSTR=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module cl_debug_bridge (
  clk,
  S_BSCAN_bscanid_en,
  S_BSCAN_capture,
  S_BSCAN_drck,
  S_BSCAN_reset,
  S_BSCAN_runtest,
  S_BSCAN_sel,
  S_BSCAN_shift,
  S_BSCAN_tck,
  S_BSCAN_tdi,
  S_BSCAN_tdo,
  S_BSCAN_tms,
  S_BSCAN_update
);

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_a493_clk, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.clk CLK" *)
input wire clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN BSCANID_EN" *)
input wire S_BSCAN_bscanid_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN CAPTURE" *)
input wire S_BSCAN_capture;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN DRCK" *)
input wire S_BSCAN_drck;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN RESET" *)
input wire S_BSCAN_reset;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN RUNTEST" *)
input wire S_BSCAN_runtest;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN SEL" *)
input wire S_BSCAN_sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN SHIFT" *)
input wire S_BSCAN_shift;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TCK" *)
input wire S_BSCAN_tck;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TDI" *)
input wire S_BSCAN_tdi;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TDO" *)
output wire S_BSCAN_tdo;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN TMS" *)
input wire S_BSCAN_tms;
(* X_INTERFACE_INFO = "xilinx.com:interface:bscan:1.0 S_BSCAN UPDATE" *)
input wire S_BSCAN_update;

  bd_a493 inst (
    .clk(clk),
    .S_BSCAN_bscanid_en(S_BSCAN_bscanid_en),
    .S_BSCAN_capture(S_BSCAN_capture),
    .S_BSCAN_drck(S_BSCAN_drck),
    .S_BSCAN_reset(S_BSCAN_reset),
    .S_BSCAN_runtest(S_BSCAN_runtest),
    .S_BSCAN_sel(S_BSCAN_sel),
    .S_BSCAN_shift(S_BSCAN_shift),
    .S_BSCAN_tck(S_BSCAN_tck),
    .S_BSCAN_tdi(S_BSCAN_tdi),
    .S_BSCAN_tdo(S_BSCAN_tdo),
    .S_BSCAN_tms(S_BSCAN_tms),
    .S_BSCAN_update(S_BSCAN_update)
  );
endmodule


//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Command: generate_target bd_bf3f_wrapper.bd
//Design : bd_bf3f_wrapper
//Purpose: IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module bd_bf3f_wrapper
   (Clk,
    IO_addr_strobe,
    IO_address,
    IO_byte_enable,
    IO_read_data,
    IO_read_strobe,
    IO_ready,
    IO_write_data,
    IO_write_strobe,
    Reset,
    TRACE_data_access,
    TRACE_data_address,
    TRACE_data_byte_enable,
    TRACE_data_read,
    TRACE_data_write,
    TRACE_data_write_value,
    TRACE_dcache_hit,
    TRACE_dcache_rdy,
    TRACE_dcache_read,
    TRACE_dcache_req,
    TRACE_delay_slot,
    TRACE_ex_piperun,
    TRACE_exception_kind,
    TRACE_exception_taken,
    TRACE_icache_hit,
    TRACE_icache_rdy,
    TRACE_icache_req,
    TRACE_instruction,
    TRACE_jump_hit,
    TRACE_jump_taken,
    TRACE_mb_halted,
    TRACE_mem_piperun,
    TRACE_msr_reg,
    TRACE_new_reg_value,
    TRACE_of_piperun,
    TRACE_pc,
    TRACE_pid_reg,
    TRACE_reg_addr,
    TRACE_reg_write,
    TRACE_valid_instr);
  input Clk;
  output IO_addr_strobe;
  output [31:0]IO_address;
  output [3:0]IO_byte_enable;
  input [31:0]IO_read_data;
  output IO_read_strobe;
  input IO_ready;
  output [31:0]IO_write_data;
  output IO_write_strobe;
  input Reset;
  output TRACE_data_access;
  output [0:31]TRACE_data_address;
  output [0:3]TRACE_data_byte_enable;
  output TRACE_data_read;
  output TRACE_data_write;
  output [0:31]TRACE_data_write_value;
  output TRACE_dcache_hit;
  output TRACE_dcache_rdy;
  output TRACE_dcache_read;
  output TRACE_dcache_req;
  output TRACE_delay_slot;
  output TRACE_ex_piperun;
  output [0:4]TRACE_exception_kind;
  output TRACE_exception_taken;
  output TRACE_icache_hit;
  output TRACE_icache_rdy;
  output TRACE_icache_req;
  output [0:31]TRACE_instruction;
  output TRACE_jump_hit;
  output TRACE_jump_taken;
  output TRACE_mb_halted;
  output TRACE_mem_piperun;
  output [0:14]TRACE_msr_reg;
  output [0:31]TRACE_new_reg_value;
  output TRACE_of_piperun;
  output [0:31]TRACE_pc;
  output [0:7]TRACE_pid_reg;
  output [0:4]TRACE_reg_addr;
  output TRACE_reg_write;
  output TRACE_valid_instr;

  wire Clk;
  wire IO_addr_strobe;
  wire [31:0]IO_address;
  wire [3:0]IO_byte_enable;
  wire [31:0]IO_read_data;
  wire IO_read_strobe;
  wire IO_ready;
  wire [31:0]IO_write_data;
  wire IO_write_strobe;
  wire Reset;
  wire TRACE_data_access;
  wire [0:31]TRACE_data_address;
  wire [0:3]TRACE_data_byte_enable;
  wire TRACE_data_read;
  wire TRACE_data_write;
  wire [0:31]TRACE_data_write_value;
  wire TRACE_dcache_hit;
  wire TRACE_dcache_rdy;
  wire TRACE_dcache_read;
  wire TRACE_dcache_req;
  wire TRACE_delay_slot;
  wire TRACE_ex_piperun;
  wire [0:4]TRACE_exception_kind;
  wire TRACE_exception_taken;
  wire TRACE_icache_hit;
  wire TRACE_icache_rdy;
  wire TRACE_icache_req;
  wire [0:31]TRACE_instruction;
  wire TRACE_jump_hit;
  wire TRACE_jump_taken;
  wire TRACE_mb_halted;
  wire TRACE_mem_piperun;
  wire [0:14]TRACE_msr_reg;
  wire [0:31]TRACE_new_reg_value;
  wire TRACE_of_piperun;
  wire [0:31]TRACE_pc;
  wire [0:7]TRACE_pid_reg;
  wire [0:4]TRACE_reg_addr;
  wire TRACE_reg_write;
  wire TRACE_valid_instr;

  bd_bf3f bd_bf3f_i
       (.Clk(Clk),
        .IO_addr_strobe(IO_addr_strobe),
        .IO_address(IO_address),
        .IO_byte_enable(IO_byte_enable),
        .IO_read_data(IO_read_data),
        .IO_read_strobe(IO_read_strobe),
        .IO_ready(IO_ready),
        .IO_write_data(IO_write_data),
        .IO_write_strobe(IO_write_strobe),
        .Reset(Reset),
        .TRACE_data_access(TRACE_data_access),
        .TRACE_data_address(TRACE_data_address),
        .TRACE_data_byte_enable(TRACE_data_byte_enable),
        .TRACE_data_read(TRACE_data_read),
        .TRACE_data_write(TRACE_data_write),
        .TRACE_data_write_value(TRACE_data_write_value),
        .TRACE_dcache_hit(TRACE_dcache_hit),
        .TRACE_dcache_rdy(TRACE_dcache_rdy),
        .TRACE_dcache_read(TRACE_dcache_read),
        .TRACE_dcache_req(TRACE_dcache_req),
        .TRACE_delay_slot(TRACE_delay_slot),
        .TRACE_ex_piperun(TRACE_ex_piperun),
        .TRACE_exception_kind(TRACE_exception_kind),
        .TRACE_exception_taken(TRACE_exception_taken),
        .TRACE_icache_hit(TRACE_icache_hit),
        .TRACE_icache_rdy(TRACE_icache_rdy),
        .TRACE_icache_req(TRACE_icache_req),
        .TRACE_instruction(TRACE_instruction),
        .TRACE_jump_hit(TRACE_jump_hit),
        .TRACE_jump_taken(TRACE_jump_taken),
        .TRACE_mb_halted(TRACE_mb_halted),
        .TRACE_mem_piperun(TRACE_mem_piperun),
        .TRACE_msr_reg(TRACE_msr_reg),
        .TRACE_new_reg_value(TRACE_new_reg_value),
        .TRACE_of_piperun(TRACE_of_piperun),
        .TRACE_pc(TRACE_pc),
        .TRACE_pid_reg(TRACE_pid_reg),
        .TRACE_reg_addr(TRACE_reg_addr),
        .TRACE_reg_write(TRACE_reg_write),
        .TRACE_valid_instr(TRACE_valid_instr));
endmodule


// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 4

`timescale 1ns/1ps

(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_bf3f_lmb_bram_I_0 (
  clka,
  rsta,
  ena,
  wea,
  addra,
  dina,
  douta,
  clkb,
  rstb,
  enb,
  web,
  addrb,
  dinb,
  doutb,
  rsta_busy,
  rstb_busy
);

(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *)
input wire rsta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [3 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [31 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [31 : 0] dina;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [31 : 0] douta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *)
input wire rstb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *)
input wire [3 : 0] web;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [31 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *)
input wire [31 : 0] dinb;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [31 : 0] doutb;
output wire rsta_busy;
output wire rstb_busy;

  blk_mem_gen_v8_4_4 #(
    .C_FAMILY("virtexuplus"),
    .C_XDEVICEFAMILY("virtexuplus"),
    .C_ELABORATION_DIR("./"),
    .C_INTERFACE_TYPE(0),
    .C_AXI_TYPE(1),
    .C_AXI_SLAVE_TYPE(0),
    .C_USE_BRAM_BLOCK(1),
    .C_ENABLE_32BIT_ADDRESS(1),
    .C_CTRL_ECC_ALGO("NONE"),
    .C_HAS_AXI_ID(0),
    .C_AXI_ID_WIDTH(4),
    .C_MEM_TYPE(2),
    .C_BYTE_SIZE(8),
    .C_ALGORITHM(1),
    .C_PRIM_TYPE(1),
    .C_LOAD_INIT_FILE(0),
    .C_INIT_FILE_NAME("no_coe_file_loaded"),
    .C_INIT_FILE("bd_bf3f_lmb_bram_I_0.mem"),
    .C_USE_DEFAULT_DATA(0),
    .C_DEFAULT_DATA("0"),
    .C_HAS_RSTA(1),
    .C_RST_PRIORITY_A("CE"),
    .C_RSTRAM_A(0),
    .C_INITA_VAL("0"),
    .C_HAS_ENA(1),
    .C_HAS_REGCEA(0),
    .C_USE_BYTE_WEA(1),
    .C_WEA_WIDTH(4),
    .C_WRITE_MODE_A("WRITE_FIRST"),
    .C_WRITE_WIDTH_A(32),
    .C_READ_WIDTH_A(32),
    .C_WRITE_DEPTH_A(16384),
    .C_READ_DEPTH_A(16384),
    .C_ADDRA_WIDTH(32),
    .C_HAS_RSTB(1),
    .C_RST_PRIORITY_B("CE"),
    .C_RSTRAM_B(0),
    .C_INITB_VAL("0"),
    .C_HAS_ENB(1),
    .C_HAS_REGCEB(0),
    .C_USE_BYTE_WEB(1),
    .C_WEB_WIDTH(4),
    .C_WRITE_MODE_B("WRITE_FIRST"),
    .C_WRITE_WIDTH_B(32),
    .C_READ_WIDTH_B(32),
    .C_WRITE_DEPTH_B(16384),
    .C_READ_DEPTH_B(16384),
    .C_ADDRB_WIDTH(32),
    .C_HAS_MEM_OUTPUT_REGS_A(0),
    .C_HAS_MEM_OUTPUT_REGS_B(0),
    .C_HAS_MUX_OUTPUT_REGS_A(0),
    .C_HAS_MUX_OUTPUT_REGS_B(0),
    .C_MUX_PIPELINE_STAGES(0),
    .C_HAS_SOFTECC_INPUT_REGS_A(0),
    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
    .C_USE_SOFTECC(0),
    .C_USE_ECC(0),
    .C_EN_ECC_PIPE(0),
    .C_READ_LATENCY_A(1),
    .C_READ_LATENCY_B(1),
    .C_HAS_INJECTERR(0),
    .C_SIM_COLLISION_CHECK("ALL"),
    .C_COMMON_CLK(0),
    .C_DISABLE_WARN_BHV_COLL(0),
    .C_EN_SLEEP_PIN(0),
    .C_USE_URAM(0),
    .C_EN_RDADDRA_CHG(0),
    .C_EN_RDADDRB_CHG(0),
    .C_EN_DEEPSLEEP_PIN(0),
    .C_EN_SHUTDOWN_PIN(0),
    .C_EN_SAFETY_CKT(1),
    .C_DISABLE_WARN_BHV_RANGE(0),
    .C_COUNT_36K_BRAM("16"),
    .C_COUNT_18K_BRAM("0"),
    .C_EST_POWER_SUMMARY("Estimated Power for IP     :     19.660986 mW")
  ) inst (
    .clka(clka),
    .rsta(rsta),
    .ena(ena),
    .regcea(1'D0),
    .wea(wea),
    .addra(addra),
    .dina(dina),
    .douta(douta),
    .clkb(clkb),
    .rstb(rstb),
    .enb(enb),
    .regceb(1'D0),
    .web(web),
    .addrb(addrb),
    .dinb(dinb),
    .doutb(doutb),
    .injectsbiterr(1'D0),
    .injectdbiterr(1'D0),
    .eccpipece(1'D0),
    .sbiterr(),
    .dbiterr(),
    .rdaddrecc(),
    .sleep(1'D0),
    .deepsleep(1'D0),
    .shutdown(1'D0),
    .rsta_busy(rsta_busy),
    .rstb_busy(rstb_busy),
    .s_aclk(1'H0),
    .s_aresetn(1'D0),
    .s_axi_awid(4'B0),
    .s_axi_awaddr(32'B0),
    .s_axi_awlen(8'B0),
    .s_axi_awsize(3'B0),
    .s_axi_awburst(2'B0),
    .s_axi_awvalid(1'D0),
    .s_axi_awready(),
    .s_axi_wdata(32'B0),
    .s_axi_wstrb(4'B0),
    .s_axi_wlast(1'D0),
    .s_axi_wvalid(1'D0),
    .s_axi_wready(),
    .s_axi_bid(),
    .s_axi_bresp(),
    .s_axi_bvalid(),
    .s_axi_bready(1'D0),
    .s_axi_arid(4'B0),
    .s_axi_araddr(32'B0),
    .s_axi_arlen(8'B0),
    .s_axi_arsize(3'B0),
    .s_axi_arburst(2'B0),
    .s_axi_arvalid(1'D0),
    .s_axi_arready(),
    .s_axi_rid(),
    .s_axi_rdata(),
    .s_axi_rresp(),
    .s_axi_rlast(),
    .s_axi_rvalid(),
    .s_axi_rready(1'D0),
    .s_axi_injectsbiterr(1'D0),
    .s_axi_injectdbiterr(1'D0),
    .s_axi_sbiterr(),
    .s_axi_dbiterr(),
    .s_axi_rdaddrecc()
  );
endmodule