// Amazon FPGA Hardware Development Kit
//
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
//
// Licensed under the Amazon Software License (the "License"). You may not use
// this file except in compliance with the License. A copy of the License is
// located at
//
//    http://aws.amazon.com/asl/
//
// or in the "license" file accompanying this file. This file is distributed on
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
// implied. See the License for the specific language governing permissions and
// limitations under the License.
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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viyKgiHJcWlJF11UMelWbvVoYsF7uDJ90n/5Ww==

`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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HiUek/GVQNWaepFc9Xo=

`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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MBiYAP/4TcshTSjLEVglOzGlp6fbSx9KYr1eCu1tcnF84602dfHBQHUV4WrLSSNvwXOKp/AKyOG7
1ALfiTkaDf2vG5TjkzI=

`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
VeIIJaaPUtlfe1VvZdR/BjuSRIXs9q5wYiTwm+LKSUDNMtXCl0A6nj2xESHweWlx4Lsjnho6VXem
7zwg08AWnw==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7104)
`pragma protect data_block
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xXCZif7Mo6BrziioevLo8huEtAAw8+Y/9tOuqphtPpqeAYMDGngYlyYsyGuCW0asIYXtoGxg2LJP
8FvkDDlIbhZ+glOQeHM8V+yYyluLvF0w9NDH3lJTXhiyvRy6GBGHrDvSkAlHmLrspTMlbco8KxPM
LUElKXg7FTk+kUxDiES9Xv9/TVudeVXWVbGdFGXOF4zVL9WbXxn0z3jT3fj6b+wStTQobBcsTbZT
0O9v0WAuIHt7qcmAEOt+xhDabVhbgDg7+DVz3NfvovIdM46zuYvk6hERp2JYHiB23FXyW/4gjPJ2
xC2AoAUDMLyk5D87xYLZ9vOJzRyOHRL/elpO/a4o92LNShmN
`pragma protect end_protected


// Amazon FPGA Hardware Development Kit
//
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
//
// Licensed under the Amazon Software License (the "License"). You may not use
// this file except in compliance with the License. A copy of the License is
// located at
//
//    http://aws.amazon.com/asl/
//
// or in the "license" file accompanying this file. This file is distributed on
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
// implied. See the License for the specific language governing permissions and
// limitations under the License.
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
YzI6RhCTbTb6xat5gHIeU45bfm2pOxmnaHqAF/ihtojvH1fxm05ID+E4jV65ljsSxg5hk/XNYq68
5CkBs8aMWX2C/dCynTYKfDqEpu1XOG5vhg2rSwLazHMgBBiUX8dd/TfHBU43+45Jtb+i6MJjiXIT
LBsrAhuqqlguwXMgFHWIpVMes70PJFciS4hmicgXcR8ADn99xdNaECHKlsOyP4wal/3xETbCLOgz
rY0WTcy6+DeDqM50GUbu/OwxE/H7hE1bcXDowM9dJ67aUow8Jz9FWmx9rnWha+w0R2idFxiRDIkF
qo2Q/g7aiLrgZhYsdr48/+HQ+hZdLV1ht2cUCw==

`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
xSa4lDWJPFFHiwekdDATEy0KtH6thL6nQyd1iZiJLJlNN0m72osWSdzXVg5vlTAOLu1Djn8YfwAS
8Ci1p8N1sdRHih0qs3bR8EdQIdQgSH6Jvo7IeitExQzPQSHZX2FFBNfeFMSNWqy7rAf966pPa8x4
uVfwS3Iqq45mqDrB+Fo=

`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
MauTOqq1ePQoCVfMD6s8BkjRyvniNKLMVJv97eUg2GNKwdp6+Pq3ihUtha7atOOqdhLkbr2DWntz
DGYI4P4MrI/o9m4u8NYO4xNDlwHAyMABzkf+86pzXRQGz9LFVwrluUGiWtQQ0Y6xlUjx0xJUwINH
sPrEw3NmP7E+F1pVM2A=

`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
T1wGXZJPz+3eyrBmcY4j5dqmG1h41cDh5HE8W3W6NQEuDP2Md6yWbAfQdk8OYIwa/nvJab58+7LM
DngjbM3YwQ==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 2864)
`pragma protect data_block
vR7+IXoeIJpBd3RFIeE3dOK6BypJOZY90p1Ac8F+1N5uMKLd4HYmm/VAQzJiaiYp9plobe/jVyh7
mQpaUK5vPpi7nd2BtL2p8GAoeQOQ2B+uzqNcTJSjA/yudJDdSSkw3xy3GDWxPvHsixMHDu1aDGfJ
8+mwwNJdr7qEJ6MPXswuWq174H6HCrUpQSsWW6qveCd7SOSmP+m9kCj/KdoOlzEfBVqOxVVLDuHE
mdotE8mGo5jbnsJgBE8IuVMnxgHmNq3bhYzIYusn+nX+X9XXBXD1Qupk1OQYf3Nwc8GYoCGPzCk3
ojQwxOvS541fF/xn9NAj3hj1T/tXwrlkkoInomWJ/JS9TdEbKyQBCtyKf59hSolXzqmLfxPRU1/i
6AOKABIOTjDiwOrz2iwIaal/D7d72iPZTY3UExoy9YutY2AmVI0WbL29SyDQDAeiXJiOAEU/8img
bRDyi0c1UO4F10eyBYoWBsW71tV5cBGjrszeS+H5GIS97UVOQ1qVw1mQpd3ZpLztce3VhziNRr5R
L/FYl+AzceFYPLynkpfKUB1UyaZgNypdcNmlvTBb2AtZARRt8TFA5M5KGl1A7lP5Bap1c1HY1hgP
9lZit/phjdAvayLwFKcoOFXpqNhcSGH75lsvcf2a8Cb48BSnfh3vgpRkoLjxoVcaekA6ZrUHTwbB
X6jVLd61+QuRAYZ7f7Yl4dIskRKaYQctxxvT8867KeyNW/Q9xRaUaKS7M6uZRzpRbR2Hd7VaUtx+
kxP7w5bSIASjBIctHZvWgtmvkUGiKHarC/OGkM6vIylCEYOLlBv5YgKX81CvNjZH/4CfAp7GMHdy
rmmy12YztImSsxhrNfHTy1HGxLcnwS1kQxUNlEkq02ZEF+mEMxMumfAGlHdJbOBXn1EE2fMm5zhk
JVI0rja3v33WlGb2R5NHArLna5PNh0UaZSC+exqb8sUxNS89jUypbtCJkBBhVMEHgv6+Iu+c3Orc
4jkk87BGuZI8nnGUbOwO8KCeFUcbT3XrxhokwjpqlcblZ5+D+EbjvE2dAR2dreFckak3RXIuam5h
zKjWbpv4g2qThgwWedMBFBuGEltpMNpZp1S/eng2cVDqrR0xam5E1EwEspWIZvXat+eke0hv5uDC
rpp3/ipF0m/GgD2tmdmBsFNZNLWjK2vpFF5Y+19xYc00QpzR9td2M9pzcmboiA0JHaC4E2wVFabm
wn4sI3BFJEiRj4F8ag8IneahRFxNinQqejokeDQQKMB+b6/TqG4KSnbL05AHAuBYmo93SwKmHlu9
iQXEOaws0ck0A/mWpinx5U4ADgASu7aqFx+7QXYYvepDs1WMF0Jhr1NU9TckcYlQ0aiP1pEKcO4+
dbZanSWH9iolIFNGzBgZtQ+j4dVeSiCwPCyAu8c36i1/bjc+N9wiAJhheLmq6fYOSn3V19ATajp7
pM+hflNQ6GlRXV/FMbNuUM17SVqy+TjJ8LFWFQKUN9bddyJFavGHr30DlQ5U1AgCVVZLI2EuQiok
27B45wfZ2UgyqUHaS2eJggqOS9jsDgjsES64hjIsjorQlyZyRV9nVejQk0L9+Kf6ScRxGD/joWuY
Q9eGnJnkwq0t6nF5xWh5nlNkaBEtZeeaE7P0LqhuE9k2zskOFFF1XOzovKHBEfuCYgE/0KADYDnK
DkDbnj2xDjaJ4qJ0Kh6HUNS/xy5CHRoQAUPJ7H9eJLm3dsWcJQ3PWQodYEKz7vilSsiy6ryMymRo
8X0nQHDQb5vOoxwNOOn7C+LkNow4w4aKhdC2s12H5M7SRmpnQ8CcEsh50ZdxWWlSVrFXHcgPmXHE
KE/y8isAA8ZABU5Wr4Mm+lh2lFyZe5tDT17kiQvkBiJfAoFb9nrc9kvtKxFcbtWAOYq83zVh7sw2
kBaTJ2DxxKMWEKaXwl4xsMuCsZ6OaVhW6UcGIITe1KdfnoBTWBM+xDwv3ck5rKWGb3AUqRnbUMsK
8DgVGU9D8My1BDQgiRzJ5c+abFZ6kTSugULXCEq9ERntrWG1M+kX0IzzMZTVMAvybi4i+lq7jTK4
6tS2Bpzt891+3GezNjhRbQzxlZIsuZ5TQ61RU/j5H44mnEEM61nPmQPcFhcCPx/wnin4WbViJC5a
+UT6qm5fNii4cuiJqEhTBzr0CmdFPfjnv6SSEGvYy+cOcQdo1+gQkEcKWGT5dL8IdCjZSsAQWAFC
+x3MH32YBUYwixG/o1AV2Ko/a9N5LRIX954/UCeYOJCe5hFcD9NKhmprzKMz2xwopfnh4yoXcdMJ
tkkrhoiNs0DjPu5mKH6hoCDZOJeAIiPoPPc01Vo8w0aoTwhCWBHYR9RSu78Dmy0+MSHhDzxzvZYF
GTxyfwwkV1t8YkxY75K1AtaHHhQLmUNoddAFtKroQBuplzNQEYrDosfqC/CFODAVjNC6S9l3FS4T
Wbi+jtJ0lQErhQl2Xr2LEMlp/cN7o9YlZcbp5K+wlVbB4R2RHR+4mqPbm49XOdE97IeqRWR5F7tF
Oj+iOH6D9v0nKJKHLIPnUNmigwODed8KwZ09HI3FLuqIcUqTlTZABuxPhqOc8xXkXLxrH+bzJjyl
GMuLGUwplfc2bLbueKeSWuOQitcyDYjKbPGSky8qrtl4RhW/4YI5Hn3KVmxIad1e9vrOf5Ux7LqL
zRw7be2tFjtsqpKJ/zFMTtK56IN6FXWcisEAn9lkk+pYDkBIr/dQwZarBPmbXJQtrKEPt/iz50kN
3JtjeFB1l3lTNEm4ki+S+kpY6PmLV2P8Xwg9eSMBe606GzPYqWZg9XOPRWuDnP71jx+Ahj5kBiRB
83BM3i9ZyPODeLP6tz+JBiQPNaKRfdzGlBTDUVUM7xUwrRFxbqNYG6KYj+493GKo0Kcn8+yVs78m
uMsPjwBGYieWKbse0kBY3p2T9/KtA39rxUt8p2eISqVordD1KV/vIenzYMqZDok0QHwx768MwWU6
1q57GzzyB8hd+YPOlTz8B8BMrrL1AJId1nJfL0z4W6NNKifE0dZLB4qFxus4d2AXgfnEDT9ZHZiV
wwi3LdybbzpsM2mseT9w2HBSIuTgqwX6kdSfRPLxc/bpn7ZqAODF2bZ/kmm+8o7YI+/CTqfj4TLF
k2+r95/P+ce/2a2g8o+RxpYehSNSiG0BK4oa4Zd8z4zVk7DBde0Yena1bdDCid9GsPyTGcbCWMdP
GRGhsUeNSBcWi1h9gY0V2CGUJAT/rWqV9wwXGQVV6jEfosieq+6DmNYVIav+xvxPshfeulHrknPu
Cx1u5uoilA+a8nCZxYMa8dUYCihg8Ca4ftPjbbTIH3R0+z+GlweFNkdLbSuOGomo97DYoAiuig1Y
YMf9kHMxqu/lmj2fr8kRuDKmk7deHFbxD3TTdX3fa/FhHTCBUTs4zDhko5t1d8vSjSD1HmIiS6lk
wVcYyWoJ8JZOq4D/TJTY3QUualQEE+Vlu6NsX7bTye24cdOhPM+Ou0szgCHhtpweGrPt0l46DKtb
wKZVhN3jMfTSCeAbYN/RjA4Gyb7mlIDSsuKQog9l2jP8yb0dRD0NAZ/c7UPGggwWIX7G8Eei7c2V
obqHNG9fmiQFr1sa4P1qjfM53NzWwEg2AZUaDTn1p0mkJ3YC/GfucgquVbIbz91FjD+m+ehmp3vg
YDzcoZvNKpq5J2VBYs9iKqn9UE6FObH4YupmYYb/xcq7Nu+mjc8wMq+3g6L7cAsayrobefUwCIDP
EoUxh8G2NibYTXadOPt7oH21Z3IDfjxOccCqE7LepfQzE/OH2E500qlTRdKJY/Tmgcekh2bUnwu3
XlQJsZphGfJyyvZyppk=
`pragma protect end_protected


// Amazon FPGA Hardware Development Kit
//
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
//
// Licensed under the Amazon Software License (the "License"). You may not use
// this file except in compliance with the License. A copy of the License is
// located at
//
//    http://aws.amazon.com/asl/
//
// or in the "license" file accompanying this file. This file is distributed on
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
// implied. See the License for the specific language governing permissions and
// limitations under the License.

`pragma protect begin_protected
`pragma protect version = 2
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect begin_commonblock
`pragma protect control error_handling="delegated"
`pragma protect end_commonblock
`pragma protect begin_toolblock
`pragma protect rights_digest_method="sha256"
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinxt_2017_05", key_method = "rsa", key_block
EZ2tH3LeMVv7vukHaN/tv+pQmwZX81o7thyHVDWF7mM93FaXyNhCXTSyDdazJu7/59Py93a+cCj9
EEEG/UMXcssv/u4GhJzoLhNbGUxPXLsX3SIGrTAhYMqUghm1uiPpNdST+Khvq3rfWs5cehEPvsWw
8A52qamT0g71hscVONAjIadCoIAAQvF6wBVGan/xoUsiiuVj/StB/MRCaU1h33zJVnkJChMNuv1u
GcwL2vTjF2mJSTLkMDWU4d3JqnNNe6JLK5eokUOlzu7E90SIv72KLBebeiWgyJXoUTk3vuN6RBcl
1NLulevXSjI5J1IzTMQ8KdMirHBaVA6r1l2Wsw==

`pragma protect control xilinx_configuration_visible = "false"
`pragma protect control xilinx_enable_modification = "false"
`pragma protect control xilinx_enable_probing = "false"
`pragma protect end_toolblock="rUY20Sun5Njk38TaHPm9PEsmv9niNjWSTL+22BD4WpE="
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7104)
`pragma protect data_block
s80ewUsMopuQpWnFB2sB+ONF6yKt/CFEoFhY8eN6Fd++8VwoecJwX+D+xdDD1B4a99zC2wgLlCPa
LpG4B34md3a1iLti2ElPTT75bw6YhUJ3GFvtvWk43x4QV9jMJaVTQIQQC5q0jUynSr0bHfYCiI88
yr6/+srQ6R6y+eENcHfUzONGqx+BfCa29/UbSZohsT1dVC59xufibiI0SvLZRvICksWXk9bL3dow
WxrDptbLgNjVBIhyLPwiuQvDtZ5PMZWKKhwF8c2Kh4IGBpy4tY8doLEbF5CaNIcRp92hAQ/MOEYh
i1gneLVYlLQiQR8nlBGPcYH4u7ymoTFvL+Sx0mMJSAxCrFziTeNdzNWf5te5fh2RxaZ+6l2QS9Zk
OxAMKLy0ZmD/ND/8AXlSsLUughpPYFeij8vZmZ+WsDCp8B5ibGhpEZrjrZQNTgu0HU4wsgr3jbiv
yDCQJIMTSWKKGwDHgVjti4ctxK+IjUu8zYEAdsjlLFKx0rGaJjnCGqD9L0DryHXvfojIT5xfvR8C
qy5bTiLFSQawaXjWjJmXgdvIxazoE7yIsDENaKMCBdSafJsNkx+O/MR0plWJ/Pgx04t/pEP5Cy6W
otlG94pAmM47ogF4MnMHRF+rVpysu9p8m0sl3rUiPHfRhIOFWgHRKk1ZC3HOo4TQmeQaGWyTeWvM
9OlrB+DE2U4vCjeoJV9O+vKiKC8tq3z9IfSvRqcW9Fhk7dEjs3qnCPaD1kYi8+UZCio/j6eYf7UN
UKhq+I9qxsyR1BmhFNu6Af6B3hAY5Qeb6UH/KMbqHCoGlJEhXsfes2Kp8BvqBfl8/CdHhvLpK0aX
tAfF+W+Uh/DfOmIE4/wtmA8TpolUsdEHfd6qFWx74M/+vi1cZgIN2YkyZ8GWTixSjIbciGE3+T5f
eVr2/IrDuPSuAn7sq89UGWxnDYMorw7GGSt1X28kEK3NaFs9f87SLlx0k/Z+/MFXs8PPrf5eIv2W
LC0Y0bSmQY4Fk4j8+thYuNvWqXR/67m6PT0NlzZa5bDgn4+htU2HhH4eLs9ABfPQLT3pa2R5P2HP
scuqY0NDBfGiyCKbUsAAqrURj+BP4avJ0C0mm2SM260c/HYpjQ+unBaY0G0yc9iXMTCmEDor4qav
lQw2qFwUTFdc0WiZoeO80OZd27i9heulJJ301rqnlDvSz/9Fk7cUz7GFiKaHVCTqL+/u5J8xY+O9
N/ahSBFZGwQR/ODX+M3OGTfJi3ZCKECD6qTDlmZqjqXd24O3YWSIo2+IT6QVV4XPZoXkLrOmVDnI
r8LK+396XsuJ8HnkGihELPBRVQgg/Y2U/kCdTPFL9/+0rtJdAxLNGqJOdEeUz5gW9g7i+bvdSiyC
vcYoq8wmOhoVRi+spru+R2/MUsriYLHXx24rxpeMNG04lEU10Hor/xAcwgmTI8tNwDJB4b0r80JM
r+swUyO06BPv9ZsbHycD7I4g10HyBw/mu20EZ/yf5QcjEDjBrIdDIZPl+4FwDjq7McfG2NR6Vwau
D5IS7YrxlAThTO0K1P2pE9MbOgfEQ1Rk4DZWkKil33leAcmvydIcK3HYtwtDU/YQPEcxWx448JRL
+qaDsGmAxIA4wczgpXq7YKRq+f+3Hmu+PfOUTEUnwRQIjVl8R6IOpAh0WOMZQWCdOgrGPjGlCuRG
Sj34xTHAXX0+vONpgapnAJgA4gi493EuFeruDbwCdyanUOvJqUveFWtpF/0aJlHU/Df1tiLryl4G
/GwLb58dMvdwNDSQrE0G3RroxyiyvK+EfLIKkCE+nHmsoBwCOn3V0+ZdOFfuj0Dr6dAyCYx6yDno
yhkLi4iZLHxkUVs6Z8BKFIxza/StaoqYG8iGqRhRdGH0JfU1H7J/A+yjerNS61Ap4SQ7Vm1v/f7h
2iRJeYDTWlK/2fL8HZBAG/PAjHDQf3E9YuObk+Xgu9fN1de5T5A1lQRGuneOwRHOofo/EXNtJAq/
Ol0V+IO/oPnzm9DMJrVbAVHm30VyzW9VxHsCliYJxoVEalwZJybjLwk+FdHFmb9246qlJwJbWnH4
tXbVHikM/TbIGn4q8M4UCERAA1I/krb+5dLwu4egiG7NkuoUuuoABg4oN7dXc/r/Mm8NEFa+P4Hw
e+1sp9vGpG+kHMIhaMTEDLIa/6KzlIXRsYsdYa0QpnyY06TR4l0Gy4ytHNPGLgqBD7PviK+eZzvf
P8nygmraTiTwNwRtqoF5DkLMPY7KrNhHdsJTTgHFL/vhwfvTUgukqPrT5ehF3IK9BvQCfIRVdvDr
gwbBGNbtI4SJJkYmHZH/m/KGnWlqoCOXNVvjVDavftAXr4mNtx5vSqVFx+9OMVmYlyn0EUCCGYtu
EC3KGWAXVkH646lAaw8lNgp5NCLhLM6Hx3e+9V6h/Q6I/QDjA7/6NUF5Zf/Gcjobv2X/ey8c6eDl
284v7ZAE1oBlpj8Y0/yDyt9KKkpq6RP70BnA+rfwWmLP4pygJWuO/cPHybgeC8CqCZ7GoeORZAXA
U4r33uwqrqnIZSGSYXJMsnsybG/GrXXAIwRo3bH6SR0rX6gQJdotqEgabVXMX0P0hpouKaVn0M68
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lfMG4cbHHGmohg8vRFuAyWwTXUlQmISjk6tTQOsdVWJB/BoXku5d98fMhEEnHoZ0jJ1atIFuijgr
828KNwZdmI3SZSmD5lVONV/zLFgtWrlNp7hcnl4q49r1tG8YgA71mEeB7XFAciZXDdRX10DdKQ/8
ueUhQ7XYmyKp+Yl5ILHf7G8htGitx9q5hDLIxDq8h3Z0R4PaX9WK87RP+mog7nObs8ajRs8bI5Rm
u0hIk8VsLXzRr7pT92a89EPnBnGpkAEdBziznE+hxBHR5o4teEJvce0yQl52gWeO2dcql9BozfJE
FL9If/OEfYyQdWi8qzS5fsl53esw7AH11jwoYPsxhQUUmeH1dAxMi+RkW3+WaQOgEJjRZxSIQJqL
33lwu/jfnmRXWEII7s8SpUseLgIeo7HT6+ZmveNMOw8uguta78FJfrif6tpA1KBoCkNnb5bxhmb5
zDhe/Q4Eg0UW7/VSpMZfi7ypuyIGzdWCY1KNWeDovzco0xeg13BFsxiVw29YpKKRcFQTLsJt6OWh
87ouBHuJBg2984G5TcShmKAsBR8D0ZPEACu0MrWXeQw34UPWNdtrmvq996W5xNQHnqN8lPAWBvVI
9rrYk6I2uook//PGmgLi/1WDq3Gix3OSNfPkDtUvbQJA1pEXOgYASEjgdyob1B5NpHQguqAqG/NP
CBILzgyuQZ0/CDtPua+otMbnSz1hhu9UC8Na/QyhKNT0yHY0ug2C9+sruPezZJTWMnmEXRjxRPuz
21KqzD4jhi/g6BMrG4QGVwUhahok3g5FtRrmVakP2xzBwhMX1cg/pKzY9ne9lAVLtwctLnxPlAzs
Gdi5Q7fg8K2NaopGE/r7Pv5DggEiCQ9Hi8nXlRSJMMKJwbFjikNyte8r4eQocIjYNj0UNQETMbk4
pe2gg2x7enboyWj99a97kTLiGsUF9TwCN287ECxoUJxcvX/1kbUGR+Xcp0y1L98rVe0eXeHsju3U
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`pragma protect end_protected


// Amazon FPGA Hardware Development Kit
//
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
//
// Licensed under the Amazon Software License (the "License"). You may not use
// this file except in compliance with the License. A copy of the License is
// located at
//
//    http://aws.amazon.com/asl/
//
// or in the "license" file accompanying this file. This file is distributed on
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
// implied. See the License for the specific language governing permissions and
// limitations under the License.

`pragma protect begin_protected
`pragma protect version = 2
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect begin_commonblock
`pragma protect control error_handling="delegated"
`pragma protect end_commonblock
`pragma protect begin_toolblock
`pragma protect rights_digest_method="sha256"
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinxt_2017_05", key_method = "rsa", key_block
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XaH48z6tgRVlzhHMwLlMvbLnZdz9VLTy0g6N/A==

`pragma protect control xilinx_configuration_visible = "false"
`pragma protect control xilinx_enable_modification = "false"
`pragma protect control xilinx_enable_probing = "false"
`pragma protect end_toolblock="x+L9+fi2J1WDHSxBWt5lueyga5qkA+vDtQM6hMKDc1E="
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 2864)
`pragma protect data_block
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UvDXqRks7iP9II8C2V8=
`pragma protect end_protected


// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.3
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================

`timescale 1 ns / 1 ps

(* CORE_GENERATION_INFO="dds,hls_ip_2016_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xcku040-ffva1156-2-e,HLS_INPUT_CLOCK=2.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.100000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=6,HLS_SYN_DSP=2,HLS_SYN_FF=2200,HLS_SYN_LUT=2536}" *)

module dds (
        ap_clk,
        ap_rst_n,
        m_axi_DDS_OUTPUT_AWVALID,
        m_axi_DDS_OUTPUT_AWREADY,
        m_axi_DDS_OUTPUT_AWADDR,
        m_axi_DDS_OUTPUT_AWID,
        m_axi_DDS_OUTPUT_AWLEN,
        m_axi_DDS_OUTPUT_AWSIZE,
        m_axi_DDS_OUTPUT_AWBURST,
        m_axi_DDS_OUTPUT_AWLOCK,
        m_axi_DDS_OUTPUT_AWCACHE,
        m_axi_DDS_OUTPUT_AWPROT,
        m_axi_DDS_OUTPUT_AWQOS,
        m_axi_DDS_OUTPUT_AWREGION,
        m_axi_DDS_OUTPUT_AWUSER,
        m_axi_DDS_OUTPUT_WVALID,
        m_axi_DDS_OUTPUT_WREADY,
        m_axi_DDS_OUTPUT_WDATA,
        m_axi_DDS_OUTPUT_WSTRB,
        m_axi_DDS_OUTPUT_WLAST,
        m_axi_DDS_OUTPUT_WID,
        m_axi_DDS_OUTPUT_WUSER,
        m_axi_DDS_OUTPUT_ARVALID,
        m_axi_DDS_OUTPUT_ARREADY,
        m_axi_DDS_OUTPUT_ARADDR,
        m_axi_DDS_OUTPUT_ARID,
        m_axi_DDS_OUTPUT_ARLEN,
        m_axi_DDS_OUTPUT_ARSIZE,
        m_axi_DDS_OUTPUT_ARBURST,
        m_axi_DDS_OUTPUT_ARLOCK,
        m_axi_DDS_OUTPUT_ARCACHE,
        m_axi_DDS_OUTPUT_ARPROT,
        m_axi_DDS_OUTPUT_ARQOS,
        m_axi_DDS_OUTPUT_ARREGION,
        m_axi_DDS_OUTPUT_ARUSER,
        m_axi_DDS_OUTPUT_RVALID,
        m_axi_DDS_OUTPUT_RREADY,
        m_axi_DDS_OUTPUT_RDATA,
        m_axi_DDS_OUTPUT_RLAST,
        m_axi_DDS_OUTPUT_RID,
        m_axi_DDS_OUTPUT_RUSER,
        m_axi_DDS_OUTPUT_RRESP,
        m_axi_DDS_OUTPUT_BVALID,
        m_axi_DDS_OUTPUT_BREADY,
        m_axi_DDS_OUTPUT_BRESP,
        m_axi_DDS_OUTPUT_BID,
        m_axi_DDS_OUTPUT_BUSER,
        m_axi_DDS_OUTPUT1_AWVALID,
        m_axi_DDS_OUTPUT1_AWREADY,
        m_axi_DDS_OUTPUT1_AWADDR,
        m_axi_DDS_OUTPUT1_AWID,
        m_axi_DDS_OUTPUT1_AWLEN,
        m_axi_DDS_OUTPUT1_AWSIZE,
        m_axi_DDS_OUTPUT1_AWBURST,
        m_axi_DDS_OUTPUT1_AWLOCK,
        m_axi_DDS_OUTPUT1_AWCACHE,
        m_axi_DDS_OUTPUT1_AWPROT,
        m_axi_DDS_OUTPUT1_AWQOS,
        m_axi_DDS_OUTPUT1_AWREGION,
        m_axi_DDS_OUTPUT1_AWUSER,
        m_axi_DDS_OUTPUT1_WVALID,
        m_axi_DDS_OUTPUT1_WREADY,
        m_axi_DDS_OUTPUT1_WDATA,
        m_axi_DDS_OUTPUT1_WSTRB,
        m_axi_DDS_OUTPUT1_WLAST,
        m_axi_DDS_OUTPUT1_WID,
        m_axi_DDS_OUTPUT1_WUSER,
        m_axi_DDS_OUTPUT1_ARVALID,
        m_axi_DDS_OUTPUT1_ARREADY,
        m_axi_DDS_OUTPUT1_ARADDR,
        m_axi_DDS_OUTPUT1_ARID,
        m_axi_DDS_OUTPUT1_ARLEN,
        m_axi_DDS_OUTPUT1_ARSIZE,
        m_axi_DDS_OUTPUT1_ARBURST,
        m_axi_DDS_OUTPUT1_ARLOCK,
        m_axi_DDS_OUTPUT1_ARCACHE,
        m_axi_DDS_OUTPUT1_ARPROT,
        m_axi_DDS_OUTPUT1_ARQOS,
        m_axi_DDS_OUTPUT1_ARREGION,
        m_axi_DDS_OUTPUT1_ARUSER,
        m_axi_DDS_OUTPUT1_RVALID,
        m_axi_DDS_OUTPUT1_RREADY,
        m_axi_DDS_OUTPUT1_RDATA,
        m_axi_DDS_OUTPUT1_RLAST,
        m_axi_DDS_OUTPUT1_RID,
        m_axi_DDS_OUTPUT1_RUSER,
        m_axi_DDS_OUTPUT1_RRESP,
        m_axi_DDS_OUTPUT1_BVALID,
        m_axi_DDS_OUTPUT1_BREADY,
        m_axi_DDS_OUTPUT1_BRESP,
        m_axi_DDS_OUTPUT1_BID,
        m_axi_DDS_OUTPUT1_BUSER,
        s_axi_PROG_BUS_AWVALID,
        s_axi_PROG_BUS_AWREADY,
        s_axi_PROG_BUS_AWADDR,
        s_axi_PROG_BUS_WVALID,
        s_axi_PROG_BUS_WREADY,
        s_axi_PROG_BUS_WDATA,
        s_axi_PROG_BUS_WSTRB,
        s_axi_PROG_BUS_ARVALID,
        s_axi_PROG_BUS_ARREADY,
        s_axi_PROG_BUS_ARADDR,
        s_axi_PROG_BUS_RVALID,
        s_axi_PROG_BUS_RREADY,
        s_axi_PROG_BUS_RDATA,
        s_axi_PROG_BUS_RRESP,
        s_axi_PROG_BUS_BVALID,
        s_axi_PROG_BUS_BREADY,
        s_axi_PROG_BUS_BRESP,
        interrupt
);

parameter    ap_ST_fsm_state1 = 3'b1;
parameter    ap_ST_fsm_state2 = 3'b10;
parameter    ap_ST_fsm_state3 = 3'b100;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    C_S_AXI_PROG_BUS_DATA_WIDTH = 32;
parameter    ap_const_int64_8 = 8;
parameter    C_S_AXI_PROG_BUS_ADDR_WIDTH = 5;
parameter    C_S_AXI_DATA_WIDTH = 32;
parameter    C_M_AXI_DDS_OUTPUT_ID_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT_ADDR_WIDTH = 32;
parameter    C_M_AXI_DDS_OUTPUT_DATA_WIDTH = 32;
parameter    C_M_AXI_DDS_OUTPUT_AWUSER_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT_ARUSER_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT_WUSER_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT_RUSER_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT_BUSER_WIDTH = 1;
parameter    C_M_AXI_DATA_WIDTH = 32;
parameter    C_M_AXI_DDS_OUTPUT_TARGET_ADDR = 0;
parameter    C_M_AXI_DDS_OUTPUT_USER_VALUE = 0;
parameter    C_M_AXI_DDS_OUTPUT_PROT_VALUE = 0;
parameter    C_M_AXI_DDS_OUTPUT_CACHE_VALUE = 3;
parameter    C_M_AXI_DDS_OUTPUT1_ID_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT1_ADDR_WIDTH = 32;
parameter    C_M_AXI_DDS_OUTPUT1_DATA_WIDTH = 32;
parameter    C_M_AXI_DDS_OUTPUT1_AWUSER_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT1_ARUSER_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT1_WUSER_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT1_RUSER_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT1_BUSER_WIDTH = 1;
parameter    C_M_AXI_DDS_OUTPUT1_TARGET_ADDR = 0;
parameter    C_M_AXI_DDS_OUTPUT1_USER_VALUE = 0;
parameter    C_M_AXI_DDS_OUTPUT1_PROT_VALUE = 0;
parameter    C_M_AXI_DDS_OUTPUT1_CACHE_VALUE = 3;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv3_0 = 3'b000;
parameter    ap_const_lv2_0 = 2'b00;
parameter    ap_const_lv4_0 = 4'b0000;
parameter    ap_const_lv16_0 = 16'b0000000000000000;

parameter C_S_AXI_PROG_BUS_WSTRB_WIDTH = (C_S_AXI_PROG_BUS_DATA_WIDTH / ap_const_int64_8);
parameter C_S_AXI_WSTRB_WIDTH = (C_S_AXI_DATA_WIDTH / ap_const_int64_8);
parameter C_M_AXI_DDS_OUTPUT_WSTRB_WIDTH = (C_M_AXI_DDS_OUTPUT_DATA_WIDTH / ap_const_int64_8);
parameter C_M_AXI_WSTRB_WIDTH = (C_M_AXI_DATA_WIDTH / ap_const_int64_8);
parameter C_M_AXI_DDS_OUTPUT1_WSTRB_WIDTH = (C_M_AXI_DDS_OUTPUT1_DATA_WIDTH / ap_const_int64_8);

input   ap_clk;
input   ap_rst_n;
output   m_axi_DDS_OUTPUT_AWVALID;
input   m_axi_DDS_OUTPUT_AWREADY;
output  [C_M_AXI_DDS_OUTPUT_ADDR_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_AWADDR;
output  [C_M_AXI_DDS_OUTPUT_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_AWID;
output  [7:0] m_axi_DDS_OUTPUT_AWLEN;
output  [2:0] m_axi_DDS_OUTPUT_AWSIZE;
output  [1:0] m_axi_DDS_OUTPUT_AWBURST;
output  [1:0] m_axi_DDS_OUTPUT_AWLOCK;
output  [3:0] m_axi_DDS_OUTPUT_AWCACHE;
output  [2:0] m_axi_DDS_OUTPUT_AWPROT;
output  [3:0] m_axi_DDS_OUTPUT_AWQOS;
output  [3:0] m_axi_DDS_OUTPUT_AWREGION;
output  [C_M_AXI_DDS_OUTPUT_AWUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_AWUSER;
output   m_axi_DDS_OUTPUT_WVALID;
input   m_axi_DDS_OUTPUT_WREADY;
output  [C_M_AXI_DDS_OUTPUT_DATA_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_WDATA;
output  [C_M_AXI_DDS_OUTPUT_WSTRB_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_WSTRB;
output   m_axi_DDS_OUTPUT_WLAST;
output  [C_M_AXI_DDS_OUTPUT_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_WID;
output  [C_M_AXI_DDS_OUTPUT_WUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_WUSER;
output   m_axi_DDS_OUTPUT_ARVALID;
input   m_axi_DDS_OUTPUT_ARREADY;
output  [C_M_AXI_DDS_OUTPUT_ADDR_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_ARADDR;
output  [C_M_AXI_DDS_OUTPUT_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_ARID;
output  [7:0] m_axi_DDS_OUTPUT_ARLEN;
output  [2:0] m_axi_DDS_OUTPUT_ARSIZE;
output  [1:0] m_axi_DDS_OUTPUT_ARBURST;
output  [1:0] m_axi_DDS_OUTPUT_ARLOCK;
output  [3:0] m_axi_DDS_OUTPUT_ARCACHE;
output  [2:0] m_axi_DDS_OUTPUT_ARPROT;
output  [3:0] m_axi_DDS_OUTPUT_ARQOS;
output  [3:0] m_axi_DDS_OUTPUT_ARREGION;
output  [C_M_AXI_DDS_OUTPUT_ARUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_ARUSER;
input   m_axi_DDS_OUTPUT_RVALID;
output   m_axi_DDS_OUTPUT_RREADY;
input  [C_M_AXI_DDS_OUTPUT_DATA_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_RDATA;
input   m_axi_DDS_OUTPUT_RLAST;
input  [C_M_AXI_DDS_OUTPUT_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_RID;
input  [C_M_AXI_DDS_OUTPUT_RUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_RUSER;
input  [1:0] m_axi_DDS_OUTPUT_RRESP;
input   m_axi_DDS_OUTPUT_BVALID;
output   m_axi_DDS_OUTPUT_BREADY;
input  [1:0] m_axi_DDS_OUTPUT_BRESP;
input  [C_M_AXI_DDS_OUTPUT_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_BID;
input  [C_M_AXI_DDS_OUTPUT_BUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT_BUSER;
output   m_axi_DDS_OUTPUT1_AWVALID;
input   m_axi_DDS_OUTPUT1_AWREADY;
output  [C_M_AXI_DDS_OUTPUT1_ADDR_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_AWADDR;
output  [C_M_AXI_DDS_OUTPUT1_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_AWID;
output  [7:0] m_axi_DDS_OUTPUT1_AWLEN;
output  [2:0] m_axi_DDS_OUTPUT1_AWSIZE;
output  [1:0] m_axi_DDS_OUTPUT1_AWBURST;
output  [1:0] m_axi_DDS_OUTPUT1_AWLOCK;
output  [3:0] m_axi_DDS_OUTPUT1_AWCACHE;
output  [2:0] m_axi_DDS_OUTPUT1_AWPROT;
output  [3:0] m_axi_DDS_OUTPUT1_AWQOS;
output  [3:0] m_axi_DDS_OUTPUT1_AWREGION;
output  [C_M_AXI_DDS_OUTPUT1_AWUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_AWUSER;
output   m_axi_DDS_OUTPUT1_WVALID;
input   m_axi_DDS_OUTPUT1_WREADY;
output  [C_M_AXI_DDS_OUTPUT1_DATA_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_WDATA;
output  [C_M_AXI_DDS_OUTPUT1_WSTRB_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_WSTRB;
output   m_axi_DDS_OUTPUT1_WLAST;
output  [C_M_AXI_DDS_OUTPUT1_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_WID;
output  [C_M_AXI_DDS_OUTPUT1_WUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_WUSER;
output   m_axi_DDS_OUTPUT1_ARVALID;
input   m_axi_DDS_OUTPUT1_ARREADY;
output  [C_M_AXI_DDS_OUTPUT1_ADDR_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_ARADDR;
output  [C_M_AXI_DDS_OUTPUT1_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_ARID;
output  [7:0] m_axi_DDS_OUTPUT1_ARLEN;
output  [2:0] m_axi_DDS_OUTPUT1_ARSIZE;
output  [1:0] m_axi_DDS_OUTPUT1_ARBURST;
output  [1:0] m_axi_DDS_OUTPUT1_ARLOCK;
output  [3:0] m_axi_DDS_OUTPUT1_ARCACHE;
output  [2:0] m_axi_DDS_OUTPUT1_ARPROT;
output  [3:0] m_axi_DDS_OUTPUT1_ARQOS;
output  [3:0] m_axi_DDS_OUTPUT1_ARREGION;
output  [C_M_AXI_DDS_OUTPUT1_ARUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_ARUSER;
input   m_axi_DDS_OUTPUT1_RVALID;
output   m_axi_DDS_OUTPUT1_RREADY;
input  [C_M_AXI_DDS_OUTPUT1_DATA_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_RDATA;
input   m_axi_DDS_OUTPUT1_RLAST;
input  [C_M_AXI_DDS_OUTPUT1_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_RID;
input  [C_M_AXI_DDS_OUTPUT1_RUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_RUSER;
input  [1:0] m_axi_DDS_OUTPUT1_RRESP;
input   m_axi_DDS_OUTPUT1_BVALID;
output   m_axi_DDS_OUTPUT1_BREADY;
input  [1:0] m_axi_DDS_OUTPUT1_BRESP;
input  [C_M_AXI_DDS_OUTPUT1_ID_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_BID;
input  [C_M_AXI_DDS_OUTPUT1_BUSER_WIDTH - 1 : 0] m_axi_DDS_OUTPUT1_BUSER;
input   s_axi_PROG_BUS_AWVALID;
output   s_axi_PROG_BUS_AWREADY;
input  [C_S_AXI_PROG_BUS_ADDR_WIDTH - 1 : 0] s_axi_PROG_BUS_AWADDR;
input   s_axi_PROG_BUS_WVALID;
output   s_axi_PROG_BUS_WREADY;
input  [C_S_AXI_PROG_BUS_DATA_WIDTH - 1 : 0] s_axi_PROG_BUS_WDATA;
input  [C_S_AXI_PROG_BUS_WSTRB_WIDTH - 1 : 0] s_axi_PROG_BUS_WSTRB;
input   s_axi_PROG_BUS_ARVALID;
output   s_axi_PROG_BUS_ARREADY;
input  [C_S_AXI_PROG_BUS_ADDR_WIDTH - 1 : 0] s_axi_PROG_BUS_ARADDR;
output   s_axi_PROG_BUS_RVALID;
input   s_axi_PROG_BUS_RREADY;
output  [C_S_AXI_PROG_BUS_DATA_WIDTH - 1 : 0] s_axi_PROG_BUS_RDATA;
output  [1:0] s_axi_PROG_BUS_RRESP;
output   s_axi_PROG_BUS_BVALID;
input   s_axi_PROG_BUS_BREADY;
output  [1:0] s_axi_PROG_BUS_BRESP;
output   interrupt;

reg    ap_rst_n_inv;
wire    ap_start;
reg    ap_done;
reg    ap_idle;
(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
wire   [0:0] ap_CS_fsm_state1;
reg    ap_ready;
wire   [31:0] nofSample;
wire   [31:0] incr_V;
reg    DDS_OUTPUT_AWVALID;
wire    DDS_OUTPUT_AWREADY;
reg    DDS_OUTPUT_WVALID;
wire    DDS_OUTPUT_WREADY;
wire    DDS_OUTPUT_ARREADY;
wire    DDS_OUTPUT_RVALID;
wire   [15:0] DDS_OUTPUT_RDATA;
wire    DDS_OUTPUT_RLAST;
wire   [0:0] DDS_OUTPUT_RID;
wire   [0:0] DDS_OUTPUT_RUSER;
wire   [1:0] DDS_OUTPUT_RRESP;
wire    DDS_OUTPUT_BVALID;
reg    DDS_OUTPUT_BREADY;
wire   [1:0] DDS_OUTPUT_BRESP;
wire   [0:0] DDS_OUTPUT_BID;
wire   [0:0] DDS_OUTPUT_BUSER;
reg    DDS_OUTPUT1_AWVALID;
wire    DDS_OUTPUT1_AWREADY;
reg    DDS_OUTPUT1_WVALID;
wire    DDS_OUTPUT1_WREADY;
wire    DDS_OUTPUT1_ARREADY;
wire    DDS_OUTPUT1_RVALID;
wire   [15:0] DDS_OUTPUT1_RDATA;
wire    DDS_OUTPUT1_RLAST;
wire   [0:0] DDS_OUTPUT1_RID;
wire   [0:0] DDS_OUTPUT1_RUSER;
wire   [1:0] DDS_OUTPUT1_RRESP;
wire    DDS_OUTPUT1_BVALID;
reg    DDS_OUTPUT1_BREADY;
wire   [1:0] DDS_OUTPUT1_BRESP;
wire   [0:0] DDS_OUTPUT1_BID;
wire   [0:0] DDS_OUTPUT1_BUSER;
reg   [31:0] incr_V_read_reg_68;
reg   [31:0] nofSample_read_reg_73;
wire    grp_process_frame_fu_52_ap_start;
wire    grp_process_frame_fu_52_ap_done;
wire    grp_process_frame_fu_52_ap_idle;
wire    grp_process_frame_fu_52_ap_ready;
wire    grp_process_frame_fu_52_m_axi_cos_out_V_AWVALID;
wire   [31:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWADDR;
wire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWID;
wire   [31:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWLEN;
wire   [2:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWSIZE;
wire   [1:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWBURST;
wire   [1:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWLOCK;
wire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWCACHE;
wire   [2:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWPROT;
wire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWQOS;
wire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWREGION;
wire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_AWUSER;
wire    grp_process_frame_fu_52_m_axi_cos_out_V_WVALID;
wire   [15:0] grp_process_frame_fu_52_m_axi_cos_out_V_WDATA;
wire   [1:0] grp_process_frame_fu_52_m_axi_cos_out_V_WSTRB;
wire    grp_process_frame_fu_52_m_axi_cos_out_V_WLAST;
wire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_WID;
wire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_WUSER;
wire    grp_process_frame_fu_52_m_axi_cos_out_V_ARVALID;
wire   [31:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARADDR;
wire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARID;
wire   [31:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARLEN;
wire   [2:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARSIZE;
wire   [1:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARBURST;
wire   [1:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARLOCK;
wire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARCACHE;
wire   [2:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARPROT;
wire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARQOS;
wire   [3:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARREGION;
wire   [0:0] grp_process_frame_fu_52_m_axi_cos_out_V_ARUSER;
wire    grp_process_frame_fu_52_m_axi_cos_out_V_RREADY;
wire    grp_process_frame_fu_52_m_axi_cos_out_V_BREADY;
wire    grp_process_frame_fu_52_m_axi_sin_out_V_AWVALID;
wire   [31:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWADDR;
wire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWID;
wire   [31:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWLEN;
wire   [2:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWSIZE;
wire   [1:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWBURST;
wire   [1:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWLOCK;
wire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWCACHE;
wire   [2:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWPROT;
wire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWQOS;
wire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWREGION;
wire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_AWUSER;
wire    grp_process_frame_fu_52_m_axi_sin_out_V_WVALID;
wire   [15:0] grp_process_frame_fu_52_m_axi_sin_out_V_WDATA;
wire   [1:0] grp_process_frame_fu_52_m_axi_sin_out_V_WSTRB;
wire    grp_process_frame_fu_52_m_axi_sin_out_V_WLAST;
wire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_WID;
wire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_WUSER;
wire    grp_process_frame_fu_52_m_axi_sin_out_V_ARVALID;
wire   [31:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARADDR;
wire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARID;
wire   [31:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARLEN;
wire   [2:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARSIZE;
wire   [1:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARBURST;
wire   [1:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARLOCK;
wire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARCACHE;
wire   [2:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARPROT;
wire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARQOS;
wire   [3:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARREGION;
wire   [0:0] grp_process_frame_fu_52_m_axi_sin_out_V_ARUSER;
wire    grp_process_frame_fu_52_m_axi_sin_out_V_RREADY;
wire    grp_process_frame_fu_52_m_axi_sin_out_V_BREADY;
reg    ap_reg_grp_process_frame_fu_52_ap_start;
wire   [0:0] ap_CS_fsm_state2;
wire   [0:0] ap_CS_fsm_state3;
reg   [2:0] ap_NS_fsm;

// power-on initialization
initial begin
#0 ap_CS_fsm = 3'b1;
#0 ap_reg_grp_process_frame_fu_52_ap_start = 1'b0;
end

dds_PROG_BUS_s_axi #(
    .C_S_AXI_ADDR_WIDTH( C_S_AXI_PROG_BUS_ADDR_WIDTH ),
    .C_S_AXI_DATA_WIDTH( C_S_AXI_PROG_BUS_DATA_WIDTH ))
dds_PROG_BUS_s_axi_U(
    .AWVALID(s_axi_PROG_BUS_AWVALID),
    .AWREADY(s_axi_PROG_BUS_AWREADY),
    .AWADDR(s_axi_PROG_BUS_AWADDR),
    .WVALID(s_axi_PROG_BUS_WVALID),
    .WREADY(s_axi_PROG_BUS_WREADY),
    .WDATA(s_axi_PROG_BUS_WDATA),
    .WSTRB(s_axi_PROG_BUS_WSTRB),
    .ARVALID(s_axi_PROG_BUS_ARVALID),
    .ARREADY(s_axi_PROG_BUS_ARREADY),
    .ARADDR(s_axi_PROG_BUS_ARADDR),
    .RVALID(s_axi_PROG_BUS_RVALID),
    .RREADY(s_axi_PROG_BUS_RREADY),
    .RDATA(s_axi_PROG_BUS_RDATA),
    .RRESP(s_axi_PROG_BUS_RRESP),
    .BVALID(s_axi_PROG_BUS_BVALID),
    .BREADY(s_axi_PROG_BUS_BREADY),
    .BRESP(s_axi_PROG_BUS_BRESP),
    .ACLK(ap_clk),
    .ARESET(ap_rst_n_inv),
    .ACLK_EN(1'b1),
    .ap_start(ap_start),
    .interrupt(interrupt),
    .ap_ready(ap_ready),
    .ap_done(ap_done),
    .ap_idle(ap_idle),
    .nofSample(nofSample),
    .incr_V(incr_V)
);

dds_DDS_OUTPUT_m_axi #(
    .USER_DW( 16 ),
    .USER_AW( 32 ),
    .USER_MAXREQS( 5 ),
    .NUM_READ_OUTSTANDING( 16 ),
    .NUM_WRITE_OUTSTANDING( 16 ),
    .MAX_READ_BURST_LENGTH( 16 ),
    .MAX_WRITE_BURST_LENGTH( 16 ),
    .C_M_AXI_ID_WIDTH( C_M_AXI_DDS_OUTPUT_ID_WIDTH ),
    .C_M_AXI_ADDR_WIDTH( C_M_AXI_DDS_OUTPUT_ADDR_WIDTH ),
    .C_M_AXI_DATA_WIDTH( C_M_AXI_DDS_OUTPUT_DATA_WIDTH ),
    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_DDS_OUTPUT_AWUSER_WIDTH ),
    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_DDS_OUTPUT_ARUSER_WIDTH ),
    .C_M_AXI_WUSER_WIDTH( C_M_AXI_DDS_OUTPUT_WUSER_WIDTH ),
    .C_M_AXI_RUSER_WIDTH( C_M_AXI_DDS_OUTPUT_RUSER_WIDTH ),
    .C_M_AXI_BUSER_WIDTH( C_M_AXI_DDS_OUTPUT_BUSER_WIDTH ),
    .C_TARGET_ADDR( C_M_AXI_DDS_OUTPUT_TARGET_ADDR ),
    .C_USER_VALUE( C_M_AXI_DDS_OUTPUT_USER_VALUE ),
    .C_PROT_VALUE( C_M_AXI_DDS_OUTPUT_PROT_VALUE ),
    .C_CACHE_VALUE( C_M_AXI_DDS_OUTPUT_CACHE_VALUE ))
dds_DDS_OUTPUT_m_axi_U(
    .AWVALID(m_axi_DDS_OUTPUT_AWVALID),
    .AWREADY(m_axi_DDS_OUTPUT_AWREADY),
    .AWADDR(m_axi_DDS_OUTPUT_AWADDR),
    .AWID(m_axi_DDS_OUTPUT_AWID),
    .AWLEN(m_axi_DDS_OUTPUT_AWLEN),
    .AWSIZE(m_axi_DDS_OUTPUT_AWSIZE),
    .AWBURST(m_axi_DDS_OUTPUT_AWBURST),
    .AWLOCK(m_axi_DDS_OUTPUT_AWLOCK),
    .AWCACHE(m_axi_DDS_OUTPUT_AWCACHE),
    .AWPROT(m_axi_DDS_OUTPUT_AWPROT),
    .AWQOS(m_axi_DDS_OUTPUT_AWQOS),
    .AWREGION(m_axi_DDS_OUTPUT_AWREGION),
    .AWUSER(m_axi_DDS_OUTPUT_AWUSER),
    .WVALID(m_axi_DDS_OUTPUT_WVALID),
    .WREADY(m_axi_DDS_OUTPUT_WREADY),
    .WDATA(m_axi_DDS_OUTPUT_WDATA),
    .WSTRB(m_axi_DDS_OUTPUT_WSTRB),
    .WLAST(m_axi_DDS_OUTPUT_WLAST),
    .WID(m_axi_DDS_OUTPUT_WID),
    .WUSER(m_axi_DDS_OUTPUT_WUSER),
    .ARVALID(m_axi_DDS_OUTPUT_ARVALID),
    .ARREADY(m_axi_DDS_OUTPUT_ARREADY),
    .ARADDR(m_axi_DDS_OUTPUT_ARADDR),
    .ARID(m_axi_DDS_OUTPUT_ARID),
    .ARLEN(m_axi_DDS_OUTPUT_ARLEN),
    .ARSIZE(m_axi_DDS_OUTPUT_ARSIZE),
    .ARBURST(m_axi_DDS_OUTPUT_ARBURST),
    .ARLOCK(m_axi_DDS_OUTPUT_ARLOCK),
    .ARCACHE(m_axi_DDS_OUTPUT_ARCACHE),
    .ARPROT(m_axi_DDS_OUTPUT_ARPROT),
    .ARQOS(m_axi_DDS_OUTPUT_ARQOS),
    .ARREGION(m_axi_DDS_OUTPUT_ARREGION),
    .ARUSER(m_axi_DDS_OUTPUT_ARUSER),
    .RVALID(m_axi_DDS_OUTPUT_RVALID),
    .RREADY(m_axi_DDS_OUTPUT_RREADY),
    .RDATA(m_axi_DDS_OUTPUT_RDATA),
    .RLAST(m_axi_DDS_OUTPUT_RLAST),
    .RID(m_axi_DDS_OUTPUT_RID),
    .RUSER(m_axi_DDS_OUTPUT_RUSER),
    .RRESP(m_axi_DDS_OUTPUT_RRESP),
    .BVALID(m_axi_DDS_OUTPUT_BVALID),
    .BREADY(m_axi_DDS_OUTPUT_BREADY),
    .BRESP(m_axi_DDS_OUTPUT_BRESP),
    .BID(m_axi_DDS_OUTPUT_BID),
    .BUSER(m_axi_DDS_OUTPUT_BUSER),
    .ACLK(ap_clk),
    .ARESET(ap_rst_n_inv),
    .ACLK_EN(1'b1),
    .I_ARVALID(1'b0),
    .I_ARREADY(DDS_OUTPUT_ARREADY),
    .I_ARADDR(ap_const_lv32_0),
    .I_ARID(1'b0),
    .I_ARLEN(ap_const_lv32_0),
    .I_ARSIZE(ap_const_lv3_0),
    .I_ARLOCK(ap_const_lv2_0),
    .I_ARCACHE(ap_const_lv4_0),
    .I_ARQOS(ap_const_lv4_0),
    .I_ARPROT(ap_const_lv3_0),
    .I_ARUSER(1'b0),
    .I_ARBURST(ap_const_lv2_0),
    .I_ARREGION(ap_const_lv4_0),
    .I_RVALID(DDS_OUTPUT_RVALID),
    .I_RREADY(1'b0),
    .I_RDATA(DDS_OUTPUT_RDATA),
    .I_RID(DDS_OUTPUT_RID),
    .I_RUSER(DDS_OUTPUT_RUSER),
    .I_RRESP(DDS_OUTPUT_RRESP),
    .I_RLAST(DDS_OUTPUT_RLAST),
    .I_AWVALID(DDS_OUTPUT_AWVALID),
    .I_AWREADY(DDS_OUTPUT_AWREADY),
    .I_AWADDR(grp_process_frame_fu_52_m_axi_cos_out_V_AWADDR),
    .I_AWID(grp_process_frame_fu_52_m_axi_cos_out_V_AWID),
    .I_AWLEN(grp_process_frame_fu_52_m_axi_cos_out_V_AWLEN),
    .I_AWSIZE(grp_process_frame_fu_52_m_axi_cos_out_V_AWSIZE),
    .I_AWLOCK(grp_process_frame_fu_52_m_axi_cos_out_V_AWLOCK),
    .I_AWCACHE(grp_process_frame_fu_52_m_axi_cos_out_V_AWCACHE),
    .I_AWQOS(grp_process_frame_fu_52_m_axi_cos_out_V_AWQOS),
    .I_AWPROT(grp_process_frame_fu_52_m_axi_cos_out_V_AWPROT),
    .I_AWUSER(grp_process_frame_fu_52_m_axi_cos_out_V_AWUSER),
    .I_AWBURST(grp_process_frame_fu_52_m_axi_cos_out_V_AWBURST),
    .I_AWREGION(grp_process_frame_fu_52_m_axi_cos_out_V_AWREGION),
    .I_WVALID(DDS_OUTPUT_WVALID),
    .I_WREADY(DDS_OUTPUT_WREADY),
    .I_WDATA(grp_process_frame_fu_52_m_axi_cos_out_V_WDATA),
    .I_WID(grp_process_frame_fu_52_m_axi_cos_out_V_WID),
    .I_WUSER(grp_process_frame_fu_52_m_axi_cos_out_V_WUSER),
    .I_WLAST(grp_process_frame_fu_52_m_axi_cos_out_V_WLAST),
    .I_WSTRB(grp_process_frame_fu_52_m_axi_cos_out_V_WSTRB),
    .I_BVALID(DDS_OUTPUT_BVALID),
    .I_BREADY(DDS_OUTPUT_BREADY),
    .I_BRESP(DDS_OUTPUT_BRESP),
    .I_BID(DDS_OUTPUT_BID),
    .I_BUSER(DDS_OUTPUT_BUSER)
);

dds_DDS_OUTPUT1_m_axi #(
    .USER_DW( 16 ),
    .USER_AW( 32 ),
    .USER_MAXREQS( 5 ),
    .NUM_READ_OUTSTANDING( 16 ),
    .NUM_WRITE_OUTSTANDING( 16 ),
    .MAX_READ_BURST_LENGTH( 16 ),
    .MAX_WRITE_BURST_LENGTH( 16 ),
    .C_M_AXI_ID_WIDTH( C_M_AXI_DDS_OUTPUT1_ID_WIDTH ),
    .C_M_AXI_ADDR_WIDTH( C_M_AXI_DDS_OUTPUT1_ADDR_WIDTH ),
    .C_M_AXI_DATA_WIDTH( C_M_AXI_DDS_OUTPUT1_DATA_WIDTH ),
    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_DDS_OUTPUT1_AWUSER_WIDTH ),
    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_DDS_OUTPUT1_ARUSER_WIDTH ),
    .C_M_AXI_WUSER_WIDTH( C_M_AXI_DDS_OUTPUT1_WUSER_WIDTH ),
    .C_M_AXI_RUSER_WIDTH( C_M_AXI_DDS_OUTPUT1_RUSER_WIDTH ),
    .C_M_AXI_BUSER_WIDTH( C_M_AXI_DDS_OUTPUT1_BUSER_WIDTH ),
    .C_TARGET_ADDR( C_M_AXI_DDS_OUTPUT1_TARGET_ADDR ),
    .C_USER_VALUE( C_M_AXI_DDS_OUTPUT1_USER_VALUE ),
    .C_PROT_VALUE( C_M_AXI_DDS_OUTPUT1_PROT_VALUE ),
    .C_CACHE_VALUE( C_M_AXI_DDS_OUTPUT1_CACHE_VALUE ))
dds_DDS_OUTPUT1_m_axi_U(
    .AWVALID(m_axi_DDS_OUTPUT1_AWVALID),
    .AWREADY(m_axi_DDS_OUTPUT1_AWREADY),
    .AWADDR(m_axi_DDS_OUTPUT1_AWADDR),
    .AWID(m_axi_DDS_OUTPUT1_AWID),
    .AWLEN(m_axi_DDS_OUTPUT1_AWLEN),
    .AWSIZE(m_axi_DDS_OUTPUT1_AWSIZE),
    .AWBURST(m_axi_DDS_OUTPUT1_AWBURST),
    .AWLOCK(m_axi_DDS_OUTPUT1_AWLOCK),
    .AWCACHE(m_axi_DDS_OUTPUT1_AWCACHE),
    .AWPROT(m_axi_DDS_OUTPUT1_AWPROT),
    .AWQOS(m_axi_DDS_OUTPUT1_AWQOS),
    .AWREGION(m_axi_DDS_OUTPUT1_AWREGION),
    .AWUSER(m_axi_DDS_OUTPUT1_AWUSER),
    .WVALID(m_axi_DDS_OUTPUT1_WVALID),
    .WREADY(m_axi_DDS_OUTPUT1_WREADY),
    .WDATA(m_axi_DDS_OUTPUT1_WDATA),
    .WSTRB(m_axi_DDS_OUTPUT1_WSTRB),
    .WLAST(m_axi_DDS_OUTPUT1_WLAST),
    .WID(m_axi_DDS_OUTPUT1_WID),
    .WUSER(m_axi_DDS_OUTPUT1_WUSER),
    .ARVALID(m_axi_DDS_OUTPUT1_ARVALID),
    .ARREADY(m_axi_DDS_OUTPUT1_ARREADY),
    .ARADDR(m_axi_DDS_OUTPUT1_ARADDR),
    .ARID(m_axi_DDS_OUTPUT1_ARID),
    .ARLEN(m_axi_DDS_OUTPUT1_ARLEN),
    .ARSIZE(m_axi_DDS_OUTPUT1_ARSIZE),
    .ARBURST(m_axi_DDS_OUTPUT1_ARBURST),
    .ARLOCK(m_axi_DDS_OUTPUT1_ARLOCK),
    .ARCACHE(m_axi_DDS_OUTPUT1_ARCACHE),
    .ARPROT(m_axi_DDS_OUTPUT1_ARPROT),
    .ARQOS(m_axi_DDS_OUTPUT1_ARQOS),
    .ARREGION(m_axi_DDS_OUTPUT1_ARREGION),
    .ARUSER(m_axi_DDS_OUTPUT1_ARUSER),
    .RVALID(m_axi_DDS_OUTPUT1_RVALID),
    .RREADY(m_axi_DDS_OUTPUT1_RREADY),
    .RDATA(m_axi_DDS_OUTPUT1_RDATA),
    .RLAST(m_axi_DDS_OUTPUT1_RLAST),
    .RID(m_axi_DDS_OUTPUT1_RID),
    .RUSER(m_axi_DDS_OUTPUT1_RUSER),
    .RRESP(m_axi_DDS_OUTPUT1_RRESP),
    .BVALID(m_axi_DDS_OUTPUT1_BVALID),
    .BREADY(m_axi_DDS_OUTPUT1_BREADY),
    .BRESP(m_axi_DDS_OUTPUT1_BRESP),
    .BID(m_axi_DDS_OUTPUT1_BID),
    .BUSER(m_axi_DDS_OUTPUT1_BUSER),
    .ACLK(ap_clk),
    .ARESET(ap_rst_n_inv),
    .ACLK_EN(1'b1),
    .I_ARVALID(1'b0),
    .I_ARREADY(DDS_OUTPUT1_ARREADY),
    .I_ARADDR(ap_const_lv32_0),
    .I_ARID(1'b0),
    .I_ARLEN(ap_const_lv32_0),
    .I_ARSIZE(ap_const_lv3_0),
    .I_ARLOCK(ap_const_lv2_0),
    .I_ARCACHE(ap_const_lv4_0),
    .I_ARQOS(ap_const_lv4_0),
    .I_ARPROT(ap_const_lv3_0),
    .I_ARUSER(1'b0),
    .I_ARBURST(ap_const_lv2_0),
    .I_ARREGION(ap_const_lv4_0),
    .I_RVALID(DDS_OUTPUT1_RVALID),
    .I_RREADY(1'b0),
    .I_RDATA(DDS_OUTPUT1_RDATA),
    .I_RID(DDS_OUTPUT1_RID),
    .I_RUSER(DDS_OUTPUT1_RUSER),
    .I_RRESP(DDS_OUTPUT1_RRESP),
    .I_RLAST(DDS_OUTPUT1_RLAST),
    .I_AWVALID(DDS_OUTPUT1_AWVALID),
    .I_AWREADY(DDS_OUTPUT1_AWREADY),
    .I_AWADDR(grp_process_frame_fu_52_m_axi_sin_out_V_AWADDR),
    .I_AWID(grp_process_frame_fu_52_m_axi_sin_out_V_AWID),
    .I_AWLEN(grp_process_frame_fu_52_m_axi_sin_out_V_AWLEN),
    .I_AWSIZE(grp_process_frame_fu_52_m_axi_sin_out_V_AWSIZE),
    .I_AWLOCK(grp_process_frame_fu_52_m_axi_sin_out_V_AWLOCK),
    .I_AWCACHE(grp_process_frame_fu_52_m_axi_sin_out_V_AWCACHE),
    .I_AWQOS(grp_process_frame_fu_52_m_axi_sin_out_V_AWQOS),
    .I_AWPROT(grp_process_frame_fu_52_m_axi_sin_out_V_AWPROT),
    .I_AWUSER(grp_process_frame_fu_52_m_axi_sin_out_V_AWUSER),
    .I_AWBURST(grp_process_frame_fu_52_m_axi_sin_out_V_AWBURST),
    .I_AWREGION(grp_process_frame_fu_52_m_axi_sin_out_V_AWREGION),
    .I_WVALID(DDS_OUTPUT1_WVALID),
    .I_WREADY(DDS_OUTPUT1_WREADY),
    .I_WDATA(grp_process_frame_fu_52_m_axi_sin_out_V_WDATA),
    .I_WID(grp_process_frame_fu_52_m_axi_sin_out_V_WID),
    .I_WUSER(grp_process_frame_fu_52_m_axi_sin_out_V_WUSER),
    .I_WLAST(grp_process_frame_fu_52_m_axi_sin_out_V_WLAST),
    .I_WSTRB(grp_process_frame_fu_52_m_axi_sin_out_V_WSTRB),
    .I_BVALID(DDS_OUTPUT1_BVALID),
    .I_BREADY(DDS_OUTPUT1_BREADY),
    .I_BRESP(DDS_OUTPUT1_BRESP),
    .I_BID(DDS_OUTPUT1_BID),
    .I_BUSER(DDS_OUTPUT1_BUSER)
);

process_frame grp_process_frame_fu_52(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst_n_inv),
    .ap_start(grp_process_frame_fu_52_ap_start),
    .ap_done(grp_process_frame_fu_52_ap_done),
    .ap_idle(grp_process_frame_fu_52_ap_idle),
    .ap_ready(grp_process_frame_fu_52_ap_ready),
    .nofSample(nofSample_read_reg_73),
    .incr_V(incr_V_read_reg_68),
    .m_axi_cos_out_V_AWVALID(grp_process_frame_fu_52_m_axi_cos_out_V_AWVALID),
    .m_axi_cos_out_V_AWREADY(DDS_OUTPUT_AWREADY),
    .m_axi_cos_out_V_AWADDR(grp_process_frame_fu_52_m_axi_cos_out_V_AWADDR),
    .m_axi_cos_out_V_AWID(grp_process_frame_fu_52_m_axi_cos_out_V_AWID),
    .m_axi_cos_out_V_AWLEN(grp_process_frame_fu_52_m_axi_cos_out_V_AWLEN),
    .m_axi_cos_out_V_AWSIZE(grp_process_frame_fu_52_m_axi_cos_out_V_AWSIZE),
    .m_axi_cos_out_V_AWBURST(grp_process_frame_fu_52_m_axi_cos_out_V_AWBURST),
    .m_axi_cos_out_V_AWLOCK(grp_process_frame_fu_52_m_axi_cos_out_V_AWLOCK),
    .m_axi_cos_out_V_AWCACHE(grp_process_frame_fu_52_m_axi_cos_out_V_AWCACHE),
    .m_axi_cos_out_V_AWPROT(grp_process_frame_fu_52_m_axi_cos_out_V_AWPROT),
    .m_axi_cos_out_V_AWQOS(grp_process_frame_fu_52_m_axi_cos_out_V_AWQOS),
    .m_axi_cos_out_V_AWREGION(grp_process_frame_fu_52_m_axi_cos_out_V_AWREGION),
    .m_axi_cos_out_V_AWUSER(grp_process_frame_fu_52_m_axi_cos_out_V_AWUSER),
    .m_axi_cos_out_V_WVALID(grp_process_frame_fu_52_m_axi_cos_out_V_WVALID),
    .m_axi_cos_out_V_WREADY(DDS_OUTPUT_WREADY),
    .m_axi_cos_out_V_WDATA(grp_process_frame_fu_52_m_axi_cos_out_V_WDATA),
    .m_axi_cos_out_V_WSTRB(grp_process_frame_fu_52_m_axi_cos_out_V_WSTRB),
    .m_axi_cos_out_V_WLAST(grp_process_frame_fu_52_m_axi_cos_out_V_WLAST),
    .m_axi_cos_out_V_WID(grp_process_frame_fu_52_m_axi_cos_out_V_WID),
    .m_axi_cos_out_V_WUSER(grp_process_frame_fu_52_m_axi_cos_out_V_WUSER),
    .m_axi_cos_out_V_ARVALID(grp_process_frame_fu_52_m_axi_cos_out_V_ARVALID),
    .m_axi_cos_out_V_ARREADY(1'b0),
    .m_axi_cos_out_V_ARADDR(grp_process_frame_fu_52_m_axi_cos_out_V_ARADDR),
    .m_axi_cos_out_V_ARID(grp_process_frame_fu_52_m_axi_cos_out_V_ARID),
    .m_axi_cos_out_V_ARLEN(grp_process_frame_fu_52_m_axi_cos_out_V_ARLEN),
    .m_axi_cos_out_V_ARSIZE(grp_process_frame_fu_52_m_axi_cos_out_V_ARSIZE),
    .m_axi_cos_out_V_ARBURST(grp_process_frame_fu_52_m_axi_cos_out_V_ARBURST),
    .m_axi_cos_out_V_ARLOCK(grp_process_frame_fu_52_m_axi_cos_out_V_ARLOCK),
    .m_axi_cos_out_V_ARCACHE(grp_process_frame_fu_52_m_axi_cos_out_V_ARCACHE),
    .m_axi_cos_out_V_ARPROT(grp_process_frame_fu_52_m_axi_cos_out_V_ARPROT),
    .m_axi_cos_out_V_ARQOS(grp_process_frame_fu_52_m_axi_cos_out_V_ARQOS),
    .m_axi_cos_out_V_ARREGION(grp_process_frame_fu_52_m_axi_cos_out_V_ARREGION),
    .m_axi_cos_out_V_ARUSER(grp_process_frame_fu_52_m_axi_cos_out_V_ARUSER),
    .m_axi_cos_out_V_RVALID(1'b0),
    .m_axi_cos_out_V_RREADY(grp_process_frame_fu_52_m_axi_cos_out_V_RREADY),
    .m_axi_cos_out_V_RDATA(ap_const_lv16_0),
    .m_axi_cos_out_V_RLAST(1'b0),
    .m_axi_cos_out_V_RID(1'b0),
    .m_axi_cos_out_V_RUSER(1'b0),
    .m_axi_cos_out_V_RRESP(ap_const_lv2_0),
    .m_axi_cos_out_V_BVALID(DDS_OUTPUT_BVALID),
    .m_axi_cos_out_V_BREADY(grp_process_frame_fu_52_m_axi_cos_out_V_BREADY),
    .m_axi_cos_out_V_BRESP(DDS_OUTPUT_BRESP),
    .m_axi_cos_out_V_BID(DDS_OUTPUT_BID),
    .m_axi_cos_out_V_BUSER(DDS_OUTPUT_BUSER),
    .m_axi_sin_out_V_AWVALID(grp_process_frame_fu_52_m_axi_sin_out_V_AWVALID),
    .m_axi_sin_out_V_AWREADY(DDS_OUTPUT1_AWREADY),
    .m_axi_sin_out_V_AWADDR(grp_process_frame_fu_52_m_axi_sin_out_V_AWADDR),
    .m_axi_sin_out_V_AWID(grp_process_frame_fu_52_m_axi_sin_out_V_AWID),
    .m_axi_sin_out_V_AWLEN(grp_process_frame_fu_52_m_axi_sin_out_V_AWLEN),
    .m_axi_sin_out_V_AWSIZE(grp_process_frame_fu_52_m_axi_sin_out_V_AWSIZE),
    .m_axi_sin_out_V_AWBURST(grp_process_frame_fu_52_m_axi_sin_out_V_AWBURST),
    .m_axi_sin_out_V_AWLOCK(grp_process_frame_fu_52_m_axi_sin_out_V_AWLOCK),
    .m_axi_sin_out_V_AWCACHE(grp_process_frame_fu_52_m_axi_sin_out_V_AWCACHE),
    .m_axi_sin_out_V_AWPROT(grp_process_frame_fu_52_m_axi_sin_out_V_AWPROT),
    .m_axi_sin_out_V_AWQOS(grp_process_frame_fu_52_m_axi_sin_out_V_AWQOS),
    .m_axi_sin_out_V_AWREGION(grp_process_frame_fu_52_m_axi_sin_out_V_AWREGION),
    .m_axi_sin_out_V_AWUSER(grp_process_frame_fu_52_m_axi_sin_out_V_AWUSER),
    .m_axi_sin_out_V_WVALID(grp_process_frame_fu_52_m_axi_sin_out_V_WVALID),
    .m_axi_sin_out_V_WREADY(DDS_OUTPUT1_WREADY),
    .m_axi_sin_out_V_WDATA(grp_process_frame_fu_52_m_axi_sin_out_V_WDATA),
    .m_axi_sin_out_V_WSTRB(grp_process_frame_fu_52_m_axi_sin_out_V_WSTRB),
    .m_axi_sin_out_V_WLAST(grp_process_frame_fu_52_m_axi_sin_out_V_WLAST),
    .m_axi_sin_out_V_WID(grp_process_frame_fu_52_m_axi_sin_out_V_WID),
    .m_axi_sin_out_V_WUSER(grp_process_frame_fu_52_m_axi_sin_out_V_WUSER),
    .m_axi_sin_out_V_ARVALID(grp_process_frame_fu_52_m_axi_sin_out_V_ARVALID),
    .m_axi_sin_out_V_ARREADY(1'b0),
    .m_axi_sin_out_V_ARADDR(grp_process_frame_fu_52_m_axi_sin_out_V_ARADDR),
    .m_axi_sin_out_V_ARID(grp_process_frame_fu_52_m_axi_sin_out_V_ARID),
    .m_axi_sin_out_V_ARLEN(grp_process_frame_fu_52_m_axi_sin_out_V_ARLEN),
    .m_axi_sin_out_V_ARSIZE(grp_process_frame_fu_52_m_axi_sin_out_V_ARSIZE),
    .m_axi_sin_out_V_ARBURST(grp_process_frame_fu_52_m_axi_sin_out_V_ARBURST),
    .m_axi_sin_out_V_ARLOCK(grp_process_frame_fu_52_m_axi_sin_out_V_ARLOCK),
    .m_axi_sin_out_V_ARCACHE(grp_process_frame_fu_52_m_axi_sin_out_V_ARCACHE),
    .m_axi_sin_out_V_ARPROT(grp_process_frame_fu_52_m_axi_sin_out_V_ARPROT),
    .m_axi_sin_out_V_ARQOS(grp_process_frame_fu_52_m_axi_sin_out_V_ARQOS),
    .m_axi_sin_out_V_ARREGION(grp_process_frame_fu_52_m_axi_sin_out_V_ARREGION),
    .m_axi_sin_out_V_ARUSER(grp_process_frame_fu_52_m_axi_sin_out_V_ARUSER),
    .m_axi_sin_out_V_RVALID(1'b0),
    .m_axi_sin_out_V_RREADY(grp_process_frame_fu_52_m_axi_sin_out_V_RREADY),
    .m_axi_sin_out_V_RDATA(ap_const_lv16_0),
    .m_axi_sin_out_V_RLAST(1'b0),
    .m_axi_sin_out_V_RID(1'b0),
    .m_axi_sin_out_V_RUSER(1'b0),
    .m_axi_sin_out_V_RRESP(ap_const_lv2_0),
    .m_axi_sin_out_V_BVALID(DDS_OUTPUT1_BVALID),
    .m_axi_sin_out_V_BREADY(grp_process_frame_fu_52_m_axi_sin_out_V_BREADY),
    .m_axi_sin_out_V_BRESP(DDS_OUTPUT1_BRESP),
    .m_axi_sin_out_V_BID(DDS_OUTPUT1_BID),
    .m_axi_sin_out_V_BUSER(DDS_OUTPUT1_BUSER)
);

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        ap_reg_grp_process_frame_fu_52_ap_start <= 1'b0;
    end else begin
        if ((1'b1 == ap_CS_fsm_state2)) begin
            ap_reg_grp_process_frame_fu_52_ap_start <= 1'b1;
        end else if ((1'b1 == grp_process_frame_fu_52_ap_ready)) begin
            ap_reg_grp_process_frame_fu_52_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0))) begin
        incr_V_read_reg_68 <= incr_V;
        nofSample_read_reg_73 <= nofSample;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin
        DDS_OUTPUT1_AWVALID = grp_process_frame_fu_52_m_axi_sin_out_V_AWVALID;
    end else begin
        DDS_OUTPUT1_AWVALID = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin
        DDS_OUTPUT1_BREADY = grp_process_frame_fu_52_m_axi_sin_out_V_BREADY;
    end else begin
        DDS_OUTPUT1_BREADY = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin
        DDS_OUTPUT1_WVALID = grp_process_frame_fu_52_m_axi_sin_out_V_WVALID;
    end else begin
        DDS_OUTPUT1_WVALID = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin
        DDS_OUTPUT_AWVALID = grp_process_frame_fu_52_m_axi_cos_out_V_AWVALID;
    end else begin
        DDS_OUTPUT_AWVALID = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin
        DDS_OUTPUT_BREADY = grp_process_frame_fu_52_m_axi_cos_out_V_BREADY;
    end else begin
        DDS_OUTPUT_BREADY = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3))) begin
        DDS_OUTPUT_WVALID = grp_process_frame_fu_52_m_axi_cos_out_V_WVALID;
    end else begin
        DDS_OUTPUT_WVALID = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state3) & ~(1'b0 == grp_process_frame_fu_52_ap_done))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (ap_CS_fsm_state1 == 1'b1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state3) & ~(1'b0 == grp_process_frame_fu_52_ap_done))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            if (~(ap_start == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end
        end
        ap_ST_fsm_state2 : begin
            ap_NS_fsm = ap_ST_fsm_state3;
        end
        ap_ST_fsm_state3 : begin
            if (~(1'b0 == grp_process_frame_fu_52_ap_done)) begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state3;
            end
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_CS_fsm_state1 = ap_CS_fsm[ap_const_lv32_0];

assign ap_CS_fsm_state2 = ap_CS_fsm[ap_const_lv32_1];

assign ap_CS_fsm_state3 = ap_CS_fsm[ap_const_lv32_2];

always @ (*) begin
    ap_rst_n_inv = ~ap_rst_n;
end

assign grp_process_frame_fu_52_ap_start = ap_reg_grp_process_frame_fu_52_ap_start;

endmodule //dds