//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Command: generate_target bd_d2ea.bd
//Design : bd_d2ea
//Purpose: IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "bd_d2ea,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_d2ea,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}" *) (* HW_HANDOFF = "ddr4_core_d_microblaze_mcs.hwdef" *)
module bd_d2ea
   (Clk,
    IO_addr_strobe,
    IO_address,
    IO_byte_enable,
    IO_read_data,
    IO_read_strobe,
    IO_ready,
    IO_write_data,
    IO_write_strobe,
    Reset,
    TRACE_data_access,
    TRACE_data_address,
    TRACE_data_byte_enable,
    TRACE_data_read,
    TRACE_data_write,
    TRACE_data_write_value,
    TRACE_dcache_hit,
    TRACE_dcache_rdy,
    TRACE_dcache_read,
    TRACE_dcache_req,
    TRACE_delay_slot,
    TRACE_ex_piperun,
    TRACE_exception_kind,
    TRACE_exception_taken,
    TRACE_icache_hit,
    TRACE_icache_rdy,
    TRACE_icache_req,
    TRACE_instruction,
    TRACE_jump_hit,
    TRACE_jump_taken,
    TRACE_mb_halted,
    TRACE_mem_piperun,
    TRACE_msr_reg,
    TRACE_new_reg_value,
    TRACE_of_piperun,
    TRACE_pc,
    TRACE_pid_reg,
    TRACE_reg_addr,
    TRACE_reg_write,
    TRACE_valid_instr);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_d2ea_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000" *) input Clk;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE" *) output IO_addr_strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS" *) output [31:0]IO_address;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE" *) output [3:0]IO_byte_enable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA" *) input [31:0]IO_read_data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE" *) output IO_read_strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READY" *) input IO_ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA" *) output [31:0]IO_write_data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE" *) output IO_write_strobe;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH" *) input Reset;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS" *) output TRACE_data_access;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS" *) output [0:31]TRACE_data_address;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE" *) output [0:3]TRACE_data_byte_enable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ" *) output TRACE_data_read;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE" *) output TRACE_data_write;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE" *) output [0:31]TRACE_data_write_value;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT" *) output TRACE_dcache_hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY" *) output TRACE_dcache_rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ" *) output TRACE_dcache_read;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ" *) output TRACE_dcache_req;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT" *) output TRACE_delay_slot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN" *) output TRACE_ex_piperun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND" *) output [0:4]TRACE_exception_kind;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN" *) output TRACE_exception_taken;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT" *) output TRACE_icache_hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY" *) output TRACE_icache_rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ" *) output TRACE_icache_req;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION" *) output [0:31]TRACE_instruction;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT" *) output TRACE_jump_hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN" *) output TRACE_jump_taken;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED" *) output TRACE_mb_halted;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN" *) output TRACE_mem_piperun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG" *) output [0:14]TRACE_msr_reg;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE" *) output [0:31]TRACE_new_reg_value;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN" *) output TRACE_of_piperun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PC" *) output [0:31]TRACE_pc;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PID_REG" *) output [0:7]TRACE_pid_reg;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR" *) output [0:4]TRACE_reg_addr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE" *) output TRACE_reg_write;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR" *) output TRACE_valid_instr;

  wire Clk2;
  wire [0:0]IO_Rst;
  wire [0:0]LMB_Rst2;
  wire MB_Reset;
  wire Reset;
  wire [0:31]dlmb_ABUS;
  wire dlmb_ADDRSTROBE;
  wire [0:3]dlmb_BE;
  wire dlmb_CE;
  wire [0:31]dlmb_READDBUS;
  wire dlmb_READSTROBE;
  wire dlmb_READY;
  wire dlmb_UE;
  wire dlmb_WAIT;
  wire [0:31]dlmb_WRITEDBUS;
  wire dlmb_WRITESTROBE;
  wire [0:31]dlmb_port_2_ADDR;
  wire dlmb_port_2_CLK;
  wire [0:31]dlmb_port_2_DIN;
  wire [31:0]dlmb_port_2_DOUT;
  wire dlmb_port_2_EN;
  wire dlmb_port_2_RST;
  wire [0:3]dlmb_port_2_WE;
  wire [0:31]dlmb_port_ADDR;
  wire dlmb_port_CLK;
  wire [0:31]dlmb_port_DIN;
  wire [31:0]dlmb_port_DOUT;
  wire dlmb_port_EN;
  wire dlmb_port_RST;
  wire [0:3]dlmb_port_WE;
  wire [0:31]dlmb_sl_0_ABUS;
  wire dlmb_sl_0_ADDRSTROBE;
  wire [0:3]dlmb_sl_0_BE;
  wire dlmb_sl_0_CE;
  wire [0:31]dlmb_sl_0_READDBUS;
  wire dlmb_sl_0_READSTROBE;
  wire dlmb_sl_0_READY;
  wire dlmb_sl_0_UE;
  wire dlmb_sl_0_WAIT;
  wire [0:31]dlmb_sl_0_WRITEDBUS;
  wire dlmb_sl_0_WRITESTROBE;
  wire dlmb_sl_1_CE;
  wire [0:31]dlmb_sl_1_READDBUS;
  wire dlmb_sl_1_READY;
  wire dlmb_sl_1_UE;
  wire dlmb_sl_1_WAIT;
  wire dlmb_sl_2_CE;
  wire [0:31]dlmb_sl_2_READDBUS;
  wire dlmb_sl_2_READY;
  wire dlmb_sl_2_UE;
  wire dlmb_sl_2_WAIT;
  wire [0:31]ilmb_ABUS;
  wire ilmb_ADDRSTROBE;
  wire ilmb_CE;
  wire [0:31]ilmb_READDBUS;
  wire ilmb_READSTROBE;
  wire ilmb_READY;
  wire ilmb_UE;
  wire ilmb_WAIT;
  wire [0:31]ilmb_port_2_ADDR;
  wire ilmb_port_2_CLK;
  wire [0:31]ilmb_port_2_DIN;
  wire [31:0]ilmb_port_2_DOUT;
  wire ilmb_port_2_EN;
  wire ilmb_port_2_RST;
  wire [0:3]ilmb_port_2_WE;
  wire [0:31]ilmb_port_ADDR;
  wire ilmb_port_CLK;
  wire [0:31]ilmb_port_DIN;
  wire [31:0]ilmb_port_DOUT;
  wire ilmb_port_EN;
  wire ilmb_port_RST;
  wire [0:3]ilmb_port_WE;
  wire [0:31]ilmb_sl_0_ABUS;
  wire ilmb_sl_0_ADDRSTROBE;
  wire [0:3]ilmb_sl_0_BE;
  wire ilmb_sl_0_CE;
  wire [0:31]ilmb_sl_0_READDBUS;
  wire ilmb_sl_0_READSTROBE;
  wire ilmb_sl_0_READY;
  wire ilmb_sl_0_UE;
  wire ilmb_sl_0_WAIT;
  wire [0:31]ilmb_sl_0_WRITEDBUS;
  wire ilmb_sl_0_WRITESTROBE;
  wire ilmb_sl_1_CE;
  wire [0:31]ilmb_sl_1_READDBUS;
  wire ilmb_sl_1_READY;
  wire ilmb_sl_1_UE;
  wire ilmb_sl_1_WAIT;
  wire [31:0]iomodule_0_IO_ADDRESS;
  wire iomodule_0_IO_ADDR_STROBE;
  wire [3:0]iomodule_0_IO_BYTE_ENABLE;
  wire iomodule_0_IO_READY;
  wire [31:0]iomodule_0_IO_READ_DATA;
  wire iomodule_0_IO_READ_STROBE;
  wire [31:0]iomodule_0_IO_WRITE_DATA;
  wire iomodule_0_IO_WRITE_STROBE;
  wire microblaze_I_Trace_DATA_ACCESS;
  wire [0:31]microblaze_I_Trace_DATA_ADDRESS;
  wire [0:3]microblaze_I_Trace_DATA_BYTE_ENABLE;
  wire microblaze_I_Trace_DATA_READ;
  wire microblaze_I_Trace_DATA_WRITE;
  wire [0:31]microblaze_I_Trace_DATA_WRITE_VALUE;
  wire microblaze_I_Trace_DCACHE_HIT;
  wire microblaze_I_Trace_DCACHE_RDY;
  wire microblaze_I_Trace_DCACHE_READ;
  wire microblaze_I_Trace_DCACHE_REQ;
  wire microblaze_I_Trace_DELAY_SLOT;
  wire [0:4]microblaze_I_Trace_EXCEPTION_KIND;
  wire microblaze_I_Trace_EXCEPTION_TAKEN;
  wire microblaze_I_Trace_EX_PIPERUN;
  wire microblaze_I_Trace_ICACHE_HIT;
  wire microblaze_I_Trace_ICACHE_RDY;
  wire microblaze_I_Trace_ICACHE_REQ;
  wire [0:31]microblaze_I_Trace_INSTRUCTION;
  wire microblaze_I_Trace_JUMP_HIT;
  wire microblaze_I_Trace_JUMP_TAKEN;
  wire microblaze_I_Trace_MB_HALTED;
  wire microblaze_I_Trace_MEM_PIPERUN;
  wire [0:14]microblaze_I_Trace_MSR_REG;
  wire [0:31]microblaze_I_Trace_NEW_REG_VALUE;
  wire microblaze_I_Trace_OF_PIPERUN;
  wire [0:31]microblaze_I_Trace_PC;
  wire [0:7]microblaze_I_Trace_PID_REG;
  wire [0:4]microblaze_I_Trace_REG_ADDR;
  wire microblaze_I_Trace_REG_WRITE;
  wire microblaze_I_Trace_VALID_INSTR;

  assign Clk2 = Clk;
  assign IO_addr_strobe = iomodule_0_IO_ADDR_STROBE;
  assign IO_address[31:0] = iomodule_0_IO_ADDRESS;
  assign IO_byte_enable[3:0] = iomodule_0_IO_BYTE_ENABLE;
  assign IO_read_strobe = iomodule_0_IO_READ_STROBE;
  assign IO_write_data[31:0] = iomodule_0_IO_WRITE_DATA;
  assign IO_write_strobe = iomodule_0_IO_WRITE_STROBE;
  assign TRACE_data_access = microblaze_I_Trace_DATA_ACCESS;
  assign TRACE_data_address[0:31] = microblaze_I_Trace_DATA_ADDRESS;
  assign TRACE_data_byte_enable[0:3] = microblaze_I_Trace_DATA_BYTE_ENABLE;
  assign TRACE_data_read = microblaze_I_Trace_DATA_READ;
  assign TRACE_data_write = microblaze_I_Trace_DATA_WRITE;
  assign TRACE_data_write_value[0:31] = microblaze_I_Trace_DATA_WRITE_VALUE;
  assign TRACE_dcache_hit = microblaze_I_Trace_DCACHE_HIT;
  assign TRACE_dcache_rdy = microblaze_I_Trace_DCACHE_RDY;
  assign TRACE_dcache_read = microblaze_I_Trace_DCACHE_READ;
  assign TRACE_dcache_req = microblaze_I_Trace_DCACHE_REQ;
  assign TRACE_delay_slot = microblaze_I_Trace_DELAY_SLOT;
  assign TRACE_ex_piperun = microblaze_I_Trace_EX_PIPERUN;
  assign TRACE_exception_kind[0:4] = microblaze_I_Trace_EXCEPTION_KIND;
  assign TRACE_exception_taken = microblaze_I_Trace_EXCEPTION_TAKEN;
  assign TRACE_icache_hit = microblaze_I_Trace_ICACHE_HIT;
  assign TRACE_icache_rdy = microblaze_I_Trace_ICACHE_RDY;
  assign TRACE_icache_req = microblaze_I_Trace_ICACHE_REQ;
  assign TRACE_instruction[0:31] = microblaze_I_Trace_INSTRUCTION;
  assign TRACE_jump_hit = microblaze_I_Trace_JUMP_HIT;
  assign TRACE_jump_taken = microblaze_I_Trace_JUMP_TAKEN;
  assign TRACE_mb_halted = microblaze_I_Trace_MB_HALTED;
  assign TRACE_mem_piperun = microblaze_I_Trace_MEM_PIPERUN;
  assign TRACE_msr_reg[0:14] = microblaze_I_Trace_MSR_REG;
  assign TRACE_new_reg_value[0:31] = microblaze_I_Trace_NEW_REG_VALUE;
  assign TRACE_of_piperun = microblaze_I_Trace_OF_PIPERUN;
  assign TRACE_pc[0:31] = microblaze_I_Trace_PC;
  assign TRACE_pid_reg[0:7] = microblaze_I_Trace_PID_REG;
  assign TRACE_reg_addr[0:4] = microblaze_I_Trace_REG_ADDR;
  assign TRACE_reg_write = microblaze_I_Trace_REG_WRITE;
  assign TRACE_valid_instr = microblaze_I_Trace_VALID_INSTR;
  assign iomodule_0_IO_READY = IO_ready;
  assign iomodule_0_IO_READ_DATA = IO_read_data[31:0];
  bd_d2ea_dlmb_0 dlmb
       (.LMB_ABus(dlmb_sl_0_ABUS),
        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),
        .LMB_BE(dlmb_sl_0_BE),
        .LMB_CE(dlmb_CE),
        .LMB_Clk(Clk2),
        .LMB_ReadDBus(dlmb_READDBUS),
        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),
        .LMB_Ready(dlmb_READY),
        .LMB_UE(dlmb_UE),
        .LMB_Wait(dlmb_WAIT),
        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),
        .M_ABus(dlmb_ABUS),
        .M_AddrStrobe(dlmb_ADDRSTROBE),
        .M_BE(dlmb_BE),
        .M_DBus(dlmb_WRITEDBUS),
        .M_ReadStrobe(dlmb_READSTROBE),
        .M_WriteStrobe(dlmb_WRITESTROBE),
        .SYS_Rst(LMB_Rst2),
        .Sl_CE({dlmb_sl_0_CE,dlmb_sl_1_CE,dlmb_sl_2_CE}),
        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),
        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),
        .Sl_UE({dlmb_sl_0_UE,dlmb_sl_1_UE,dlmb_sl_2_UE}),
        .Sl_Wait({dlmb_sl_0_WAIT,dlmb_sl_1_WAIT,dlmb_sl_2_WAIT}));
  (* BMM_INFO_ADDRESS_SPACE = "byte  0x00000000 32 >  bd_d2ea lmb_bram_I bd_d2ea second_lmb_bram_I" *)
  (* KEEP_HIERARCHY = "yes" *)
  bd_d2ea_dlmb_cntlr_0 dlmb_cntlr
       (.BRAM_Addr_A(dlmb_port_ADDR),
        .BRAM_Clk_A(dlmb_port_CLK),
        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),
        .BRAM_Dout_A(dlmb_port_DIN),
        .BRAM_EN_A(dlmb_port_EN),
        .BRAM_Rst_A(dlmb_port_RST),
        .BRAM_WEN_A(dlmb_port_WE),
        .LMB_ABus(dlmb_sl_0_ABUS),
        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),
        .LMB_BE(dlmb_sl_0_BE),
        .LMB_Clk(Clk2),
        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),
        .LMB_Rst(LMB_Rst2),
        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),
        .Sl_CE(dlmb_sl_0_CE),
        .Sl_DBus(dlmb_sl_0_READDBUS),
        .Sl_Ready(dlmb_sl_0_READY),
        .Sl_UE(dlmb_sl_0_UE),
        .Sl_Wait(dlmb_sl_0_WAIT));
  bd_d2ea_ilmb_0 ilmb
       (.LMB_ABus(ilmb_sl_0_ABUS),
        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),
        .LMB_BE(ilmb_sl_0_BE),
        .LMB_CE(ilmb_CE),
        .LMB_Clk(Clk2),
        .LMB_ReadDBus(ilmb_READDBUS),
        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),
        .LMB_Ready(ilmb_READY),
        .LMB_UE(ilmb_UE),
        .LMB_Wait(ilmb_WAIT),
        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),
        .M_ABus(ilmb_ABUS),
        .M_AddrStrobe(ilmb_ADDRSTROBE),
        .M_BE({1'b0,1'b0,1'b0,1'b0}),
        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_ReadStrobe(ilmb_READSTROBE),
        .M_WriteStrobe(1'b0),
        .SYS_Rst(LMB_Rst2),
        .Sl_CE({ilmb_sl_0_CE,ilmb_sl_1_CE}),
        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),
        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),
        .Sl_UE({ilmb_sl_0_UE,ilmb_sl_1_UE}),
        .Sl_Wait({ilmb_sl_0_WAIT,ilmb_sl_1_WAIT}));
  bd_d2ea_ilmb_cntlr_0 ilmb_cntlr
       (.BRAM_Addr_A(ilmb_port_ADDR),
        .BRAM_Clk_A(ilmb_port_CLK),
        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),
        .BRAM_Dout_A(ilmb_port_DIN),
        .BRAM_EN_A(ilmb_port_EN),
        .BRAM_Rst_A(ilmb_port_RST),
        .BRAM_WEN_A(ilmb_port_WE),
        .LMB_ABus(ilmb_sl_0_ABUS),
        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),
        .LMB_BE(ilmb_sl_0_BE),
        .LMB_Clk(Clk2),
        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),
        .LMB_Rst(LMB_Rst2),
        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),
        .Sl_CE(ilmb_sl_0_CE),
        .Sl_DBus(ilmb_sl_0_READDBUS),
        .Sl_Ready(ilmb_sl_0_READY),
        .Sl_UE(ilmb_sl_0_UE),
        .Sl_Wait(ilmb_sl_0_WAIT));
  bd_d2ea_iomodule_0_0 iomodule_0
       (.Clk(Clk2),
        .IO_Addr_Strobe(iomodule_0_IO_ADDR_STROBE),
        .IO_Address(iomodule_0_IO_ADDRESS),
        .IO_Byte_Enable(iomodule_0_IO_BYTE_ENABLE),
        .IO_Read_Data(iomodule_0_IO_READ_DATA),
        .IO_Read_Strobe(iomodule_0_IO_READ_STROBE),
        .IO_Ready(iomodule_0_IO_READY),
        .IO_Write_Data(iomodule_0_IO_WRITE_DATA),
        .IO_Write_Strobe(iomodule_0_IO_WRITE_STROBE),
        .LMB_ABus(dlmb_sl_0_ABUS),
        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),
        .LMB_BE(dlmb_sl_0_BE),
        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),
        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),
        .Rst(IO_Rst),
        .Sl_CE(dlmb_sl_1_CE),
        .Sl_DBus(dlmb_sl_1_READDBUS),
        .Sl_Ready(dlmb_sl_1_READY),
        .Sl_UE(dlmb_sl_1_UE),
        .Sl_Wait(dlmb_sl_1_WAIT));
  bd_d2ea_lmb_bram_I_0 lmb_bram_I
       (.addra({dlmb_port_ADDR[0],dlmb_port_ADDR[1],dlmb_port_ADDR[2],dlmb_port_ADDR[3],dlmb_port_ADDR[4],dlmb_port_ADDR[5],dlmb_port_ADDR[6],dlmb_port_ADDR[7],dlmb_port_ADDR[8],dlmb_port_ADDR[9],dlmb_port_ADDR[10],dlmb_port_ADDR[11],dlmb_port_ADDR[12],dlmb_port_ADDR[13],dlmb_port_ADDR[14],dlmb_port_ADDR[15],dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],dlmb_port_ADDR[30],dlmb_port_ADDR[31]}),
        .addrb({ilmb_port_ADDR[0],ilmb_port_ADDR[1],ilmb_port_ADDR[2],ilmb_port_ADDR[3],ilmb_port_ADDR[4],ilmb_port_ADDR[5],ilmb_port_ADDR[6],ilmb_port_ADDR[7],ilmb_port_ADDR[8],ilmb_port_ADDR[9],ilmb_port_ADDR[10],ilmb_port_ADDR[11],ilmb_port_ADDR[12],ilmb_port_ADDR[13],ilmb_port_ADDR[14],ilmb_port_ADDR[15],ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],ilmb_port_ADDR[30],ilmb_port_ADDR[31]}),
        .clka(dlmb_port_CLK),
        .clkb(ilmb_port_CLK),
        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),
        .dinb({ilmb_port_DIN[0],ilmb_port_DIN[1],ilmb_port_DIN[2],ilmb_port_DIN[3],ilmb_port_DIN[4],ilmb_port_DIN[5],ilmb_port_DIN[6],ilmb_port_DIN[7],ilmb_port_DIN[8],ilmb_port_DIN[9],ilmb_port_DIN[10],ilmb_port_DIN[11],ilmb_port_DIN[12],ilmb_port_DIN[13],ilmb_port_DIN[14],ilmb_port_DIN[15],ilmb_port_DIN[16],ilmb_port_DIN[17],ilmb_port_DIN[18],ilmb_port_DIN[19],ilmb_port_DIN[20],ilmb_port_DIN[21],ilmb_port_DIN[22],ilmb_port_DIN[23],ilmb_port_DIN[24],ilmb_port_DIN[25],ilmb_port_DIN[26],ilmb_port_DIN[27],ilmb_port_DIN[28],ilmb_port_DIN[29],ilmb_port_DIN[30],ilmb_port_DIN[31]}),
        .douta(dlmb_port_DOUT),
        .doutb(ilmb_port_DOUT),
        .ena(dlmb_port_EN),
        .enb(ilmb_port_EN),
        .rsta(dlmb_port_RST),
        .rstb(ilmb_port_RST),
        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),
        .web({ilmb_port_WE[0],ilmb_port_WE[1],ilmb_port_WE[2],ilmb_port_WE[3]}));
  (* BMM_INFO_PROCESSOR = "microblaze-le > bd_d2ea dlmb_cntlr" *)
  (* KEEP_HIERARCHY = "yes" *)
  bd_d2ea_microblaze_I_0 microblaze_I
       (.Byte_Enable(dlmb_BE),
        .Clk(Clk2),
        .DCE(dlmb_CE),
        .DReady(dlmb_READY),
        .DUE(dlmb_UE),
        .DWait(dlmb_WAIT),
        .D_AS(dlmb_ADDRSTROBE),
        .Data_Addr(dlmb_ABUS),
        .Data_Read(dlmb_READDBUS),
        .Data_Write(dlmb_WRITEDBUS),
        .ICE(ilmb_CE),
        .IFetch(ilmb_READSTROBE),
        .IReady(ilmb_READY),
        .IUE(ilmb_UE),
        .IWAIT(ilmb_WAIT),
        .I_AS(ilmb_ADDRSTROBE),
        .Instr(ilmb_READDBUS),
        .Instr_Addr(ilmb_ABUS),
        .Interrupt(1'b0),
        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Read_Strobe(dlmb_READSTROBE),
        .Reset(MB_Reset),
        .Trace_DCache_Hit(microblaze_I_Trace_DCACHE_HIT),
        .Trace_DCache_Rdy(microblaze_I_Trace_DCACHE_RDY),
        .Trace_DCache_Read(microblaze_I_Trace_DCACHE_READ),
        .Trace_DCache_Req(microblaze_I_Trace_DCACHE_REQ),
        .Trace_Data_Access(microblaze_I_Trace_DATA_ACCESS),
        .Trace_Data_Address(microblaze_I_Trace_DATA_ADDRESS),
        .Trace_Data_Byte_Enable(microblaze_I_Trace_DATA_BYTE_ENABLE),
        .Trace_Data_Read(microblaze_I_Trace_DATA_READ),
        .Trace_Data_Write(microblaze_I_Trace_DATA_WRITE),
        .Trace_Data_Write_Value(microblaze_I_Trace_DATA_WRITE_VALUE),
        .Trace_Delay_Slot(microblaze_I_Trace_DELAY_SLOT),
        .Trace_EX_PipeRun(microblaze_I_Trace_EX_PIPERUN),
        .Trace_Exception_Kind(microblaze_I_Trace_EXCEPTION_KIND),
        .Trace_Exception_Taken(microblaze_I_Trace_EXCEPTION_TAKEN),
        .Trace_ICache_Hit(microblaze_I_Trace_ICACHE_HIT),
        .Trace_ICache_Rdy(microblaze_I_Trace_ICACHE_RDY),
        .Trace_ICache_Req(microblaze_I_Trace_ICACHE_REQ),
        .Trace_Instruction(microblaze_I_Trace_INSTRUCTION),
        .Trace_Jump_Hit(microblaze_I_Trace_JUMP_HIT),
        .Trace_Jump_Taken(microblaze_I_Trace_JUMP_TAKEN),
        .Trace_MB_Halted(microblaze_I_Trace_MB_HALTED),
        .Trace_MEM_PipeRun(microblaze_I_Trace_MEM_PIPERUN),
        .Trace_MSR_Reg(microblaze_I_Trace_MSR_REG),
        .Trace_New_Reg_Value(microblaze_I_Trace_NEW_REG_VALUE),
        .Trace_OF_PipeRun(microblaze_I_Trace_OF_PIPERUN),
        .Trace_PC(microblaze_I_Trace_PC),
        .Trace_PID_Reg(microblaze_I_Trace_PID_REG),
        .Trace_Reg_Addr(microblaze_I_Trace_REG_ADDR),
        .Trace_Reg_Write(microblaze_I_Trace_REG_WRITE),
        .Trace_Valid_Instr(microblaze_I_Trace_VALID_INSTR),
        .Write_Strobe(dlmb_WRITESTROBE));
  bd_d2ea_rst_0_0 rst_0
       (.aux_reset_in(1'b1),
        .bus_struct_reset(LMB_Rst2),
        .dcm_locked(1'b1),
        .ext_reset_in(Reset),
        .mb_debug_sys_rst(1'b0),
        .mb_reset(MB_Reset),
        .peripheral_reset(IO_Rst),
        .slowest_sync_clk(Clk2));
  (* BMM_INFO_ADDRESS_RANGE = " " *)
  bd_d2ea_second_dlmb_cntlr_0 second_dlmb_cntlr
       (.BRAM_Addr_A(dlmb_port_2_ADDR),
        .BRAM_Clk_A(dlmb_port_2_CLK),
        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),
        .BRAM_Dout_A(dlmb_port_2_DIN),
        .BRAM_EN_A(dlmb_port_2_EN),
        .BRAM_Rst_A(dlmb_port_2_RST),
        .BRAM_WEN_A(dlmb_port_2_WE),
        .LMB_ABus(dlmb_sl_0_ABUS),
        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),
        .LMB_BE(dlmb_sl_0_BE),
        .LMB_Clk(Clk2),
        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),
        .LMB_Rst(LMB_Rst2),
        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),
        .Sl_CE(dlmb_sl_2_CE),
        .Sl_DBus(dlmb_sl_2_READDBUS),
        .Sl_Ready(dlmb_sl_2_READY),
        .Sl_UE(dlmb_sl_2_UE),
        .Sl_Wait(dlmb_sl_2_WAIT));
  bd_d2ea_second_ilmb_cntlr_0 second_ilmb_cntlr
       (.BRAM_Addr_A(ilmb_port_2_ADDR),
        .BRAM_Clk_A(ilmb_port_2_CLK),
        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),
        .BRAM_Dout_A(ilmb_port_2_DIN),
        .BRAM_EN_A(ilmb_port_2_EN),
        .BRAM_Rst_A(ilmb_port_2_RST),
        .BRAM_WEN_A(ilmb_port_2_WE),
        .LMB_ABus(ilmb_sl_0_ABUS),
        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),
        .LMB_BE(ilmb_sl_0_BE),
        .LMB_Clk(Clk2),
        .LMB_ReadStrobe(ilmb_sl_0_READSTROBE),
        .LMB_Rst(LMB_Rst2),
        .LMB_WriteDBus(ilmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(ilmb_sl_0_WRITESTROBE),
        .Sl_CE(ilmb_sl_1_CE),
        .Sl_DBus(ilmb_sl_1_READDBUS),
        .Sl_Ready(ilmb_sl_1_READY),
        .Sl_UE(ilmb_sl_1_UE),
        .Sl_Wait(ilmb_sl_1_WAIT));
  bd_d2ea_second_lmb_bram_I_0 second_lmb_bram_I
       (.addra({dlmb_port_2_ADDR[0],dlmb_port_2_ADDR[1],dlmb_port_2_ADDR[2],dlmb_port_2_ADDR[3],dlmb_port_2_ADDR[4],dlmb_port_2_ADDR[5],dlmb_port_2_ADDR[6],dlmb_port_2_ADDR[7],dlmb_port_2_ADDR[8],dlmb_port_2_ADDR[9],dlmb_port_2_ADDR[10],dlmb_port_2_ADDR[11],dlmb_port_2_ADDR[12],dlmb_port_2_ADDR[13],dlmb_port_2_ADDR[14],dlmb_port_2_ADDR[15],dlmb_port_2_ADDR[16],dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],dlmb_port_2_ADDR[30],dlmb_port_2_ADDR[31]}),
        .addrb({ilmb_port_2_ADDR[0],ilmb_port_2_ADDR[1],ilmb_port_2_ADDR[2],ilmb_port_2_ADDR[3],ilmb_port_2_ADDR[4],ilmb_port_2_ADDR[5],ilmb_port_2_ADDR[6],ilmb_port_2_ADDR[7],ilmb_port_2_ADDR[8],ilmb_port_2_ADDR[9],ilmb_port_2_ADDR[10],ilmb_port_2_ADDR[11],ilmb_port_2_ADDR[12],ilmb_port_2_ADDR[13],ilmb_port_2_ADDR[14],ilmb_port_2_ADDR[15],ilmb_port_2_ADDR[16],ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],ilmb_port_2_ADDR[30],ilmb_port_2_ADDR[31]}),
        .clka(dlmb_port_2_CLK),
        .clkb(ilmb_port_2_CLK),
        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),
        .dinb({ilmb_port_2_DIN[0],ilmb_port_2_DIN[1],ilmb_port_2_DIN[2],ilmb_port_2_DIN[3],ilmb_port_2_DIN[4],ilmb_port_2_DIN[5],ilmb_port_2_DIN[6],ilmb_port_2_DIN[7],ilmb_port_2_DIN[8],ilmb_port_2_DIN[9],ilmb_port_2_DIN[10],ilmb_port_2_DIN[11],ilmb_port_2_DIN[12],ilmb_port_2_DIN[13],ilmb_port_2_DIN[14],ilmb_port_2_DIN[15],ilmb_port_2_DIN[16],ilmb_port_2_DIN[17],ilmb_port_2_DIN[18],ilmb_port_2_DIN[19],ilmb_port_2_DIN[20],ilmb_port_2_DIN[21],ilmb_port_2_DIN[22],ilmb_port_2_DIN[23],ilmb_port_2_DIN[24],ilmb_port_2_DIN[25],ilmb_port_2_DIN[26],ilmb_port_2_DIN[27],ilmb_port_2_DIN[28],ilmb_port_2_DIN[29],ilmb_port_2_DIN[30],ilmb_port_2_DIN[31]}),
        .douta(dlmb_port_2_DOUT),
        .doutb(ilmb_port_2_DOUT),
        .ena(dlmb_port_2_EN),
        .enb(ilmb_port_2_EN),
        .rsta(dlmb_port_2_RST),
        .rstb(ilmb_port_2_RST),
        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),
        .web({ilmb_port_2_WE[0],ilmb_port_2_WE[1],ilmb_port_2_WE[2],ilmb_port_2_WE[3]}));
endmodule


// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0
// IP Revision: 14

`timescale 1ns/1ps

(* DowngradeIPIdentifiedWarnings = "yes" *)
module ddr4_core_d_microblaze_mcs (
  Clk,
  Reset,
  TRACE_data_access,
  TRACE_data_address,
  TRACE_data_byte_enable,
  TRACE_data_read,
  TRACE_data_write,
  TRACE_data_write_value,
  TRACE_dcache_hit,
  TRACE_dcache_rdy,
  TRACE_dcache_read,
  TRACE_dcache_req,
  TRACE_delay_slot,
  TRACE_ex_piperun,
  TRACE_exception_kind,
  TRACE_exception_taken,
  TRACE_icache_hit,
  TRACE_icache_rdy,
  TRACE_icache_req,
  TRACE_instruction,
  TRACE_jump_hit,
  TRACE_jump_taken,
  TRACE_mb_halted,
  TRACE_mem_piperun,
  TRACE_msr_reg,
  TRACE_new_reg_value,
  TRACE_of_piperun,
  TRACE_pc,
  TRACE_pid_reg,
  TRACE_reg_addr,
  TRACE_reg_write,
  TRACE_valid_instr,
  IO_addr_strobe,
  IO_address,
  IO_byte_enable,
  IO_read_data,
  IO_read_strobe,
  IO_ready,
  IO_write_data,
  IO_write_strobe
);

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_d2ea_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.Clk CLK" *)
input wire Clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.Reset RST" *)
input wire Reset;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS" *)
output wire TRACE_data_access;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS" *)
output wire [0 : 31] TRACE_data_address;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE" *)
output wire [0 : 3] TRACE_data_byte_enable;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ" *)
output wire TRACE_data_read;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE" *)
output wire TRACE_data_write;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE" *)
output wire [0 : 31] TRACE_data_write_value;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT" *)
output wire TRACE_dcache_hit;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY" *)
output wire TRACE_dcache_rdy;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ" *)
output wire TRACE_dcache_read;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ" *)
output wire TRACE_dcache_req;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT" *)
output wire TRACE_delay_slot;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN" *)
output wire TRACE_ex_piperun;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND" *)
output wire [0 : 4] TRACE_exception_kind;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN" *)
output wire TRACE_exception_taken;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT" *)
output wire TRACE_icache_hit;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY" *)
output wire TRACE_icache_rdy;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ" *)
output wire TRACE_icache_req;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION" *)
output wire [0 : 31] TRACE_instruction;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT" *)
output wire TRACE_jump_hit;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN" *)
output wire TRACE_jump_taken;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED" *)
output wire TRACE_mb_halted;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN" *)
output wire TRACE_mem_piperun;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG" *)
output wire [0 : 14] TRACE_msr_reg;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE" *)
output wire [0 : 31] TRACE_new_reg_value;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN" *)
output wire TRACE_of_piperun;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PC" *)
output wire [0 : 31] TRACE_pc;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PID_REG" *)
output wire [0 : 7] TRACE_pid_reg;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR" *)
output wire [0 : 4] TRACE_reg_addr;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE" *)
output wire TRACE_reg_write;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR" *)
output wire TRACE_valid_instr;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE" *)
output wire IO_addr_strobe;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS" *)
output wire [31 : 0] IO_address;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE" *)
output wire [3 : 0] IO_byte_enable;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA" *)
input wire [31 : 0] IO_read_data;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE" *)
output wire IO_read_strobe;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READY" *)
input wire IO_ready;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA" *)
output wire [31 : 0] IO_write_data;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE" *)
output wire IO_write_strobe;

  bd_d2ea inst (
    .Clk(Clk),
    .Reset(Reset),
    .TRACE_data_access(TRACE_data_access),
    .TRACE_data_address(TRACE_data_address),
    .TRACE_data_byte_enable(TRACE_data_byte_enable),
    .TRACE_data_read(TRACE_data_read),
    .TRACE_data_write(TRACE_data_write),
    .TRACE_data_write_value(TRACE_data_write_value),
    .TRACE_dcache_hit(TRACE_dcache_hit),
    .TRACE_dcache_rdy(TRACE_dcache_rdy),
    .TRACE_dcache_read(TRACE_dcache_read),
    .TRACE_dcache_req(TRACE_dcache_req),
    .TRACE_delay_slot(TRACE_delay_slot),
    .TRACE_ex_piperun(TRACE_ex_piperun),
    .TRACE_exception_kind(TRACE_exception_kind),
    .TRACE_exception_taken(TRACE_exception_taken),
    .TRACE_icache_hit(TRACE_icache_hit),
    .TRACE_icache_rdy(TRACE_icache_rdy),
    .TRACE_icache_req(TRACE_icache_req),
    .TRACE_instruction(TRACE_instruction),
    .TRACE_jump_hit(TRACE_jump_hit),
    .TRACE_jump_taken(TRACE_jump_taken),
    .TRACE_mb_halted(TRACE_mb_halted),
    .TRACE_mem_piperun(TRACE_mem_piperun),
    .TRACE_msr_reg(TRACE_msr_reg),
    .TRACE_new_reg_value(TRACE_new_reg_value),
    .TRACE_of_piperun(TRACE_of_piperun),
    .TRACE_pc(TRACE_pc),
    .TRACE_pid_reg(TRACE_pid_reg),
    .TRACE_reg_addr(TRACE_reg_addr),
    .TRACE_reg_write(TRACE_reg_write),
    .TRACE_valid_instr(TRACE_valid_instr),
    .IO_addr_strobe(IO_addr_strobe),
    .IO_address(IO_address),
    .IO_byte_enable(IO_byte_enable),
    .IO_read_data(IO_read_data),
    .IO_read_strobe(IO_read_strobe),
    .IO_ready(IO_ready),
    .IO_write_data(IO_write_data),
    .IO_write_strobe(IO_write_strobe)
  );
endmodule


// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

// IP VLNV: xilinx.com:ip:microblaze_mcs:3.0
// IP Revision: 14

(* X_CORE_INFO = "bd_d2ea,Vivado 2020.2" *)
(* CHECK_LICENSE_TYPE = "ddr4_core_d_microblaze_mcs,bd_d2ea,{}" *)
(* CORE_GENERATION_INFO = "ddr4_core_d_microblaze_mcs,bd_d2ea,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_mcs,x_ipVersion=3.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_CHAIN=2,MICROBLAZE_INSTANCE=microblaze_0,AVOID_PRIMITIVES=0,PATH=mcs_0,FREQ=100.0,OPTIMIZATION=1,DEBUG_ENABLED=0,USE_BSCAN=0,BSCANID=76547328,TRACE=1,ECC=0,MEMSIZE=98304,MEMTYPE=0,USE_IO_BUS=1,USE_UART_RX=0,USE_UART_TX=0,UART_BAUDRATE=9600,UART_PROG_BAUDRATE=0,UART_DATA_BITS=8,UART_USE_PARITY\
=0,UART_ODD_PARITY=0,UART_RX_INTERRUPT=0,UART_TX_INTERRUPT=0,UART_ERROR_INTERRUPT=0,USE_FIT1=0,FIT1_No_CLOCKS=6216,FIT1_INTERRUPT=0,USE_FIT2=0,FIT2_No_CLOCKS=6216,FIT2_INTERRUPT=0,USE_FIT3=0,FIT3_No_CLOCKS=6216,FIT3_INTERRUPT=0,USE_FIT4=0,FIT4_No_CLOCKS=6216,FIT4_INTERRUPT=0,USE_PIT1=0,PIT1_SIZE=32,PIT1_READABLE=1,PIT1_PRESCALER=0,PIT1_INTERRUPT=0,USE_PIT2=0,PIT2_SIZE=32,PIT2_READABLE=1,PIT2_PRESCALER=0,PIT2_INTERRUPT=0,USE_PIT3=0,PIT3_SIZE=32,PIT3_READABLE=1,PIT3_PRESCALER=0,PIT3_INTERRUPT=0,US\
E_PIT4=0,PIT4_SIZE=32,PIT4_READABLE=1,PIT4_PRESCALER=0,PIT4_INTERRUPT=0,USE_GPO1=0,GPO1_SIZE=32,GPO1_INIT=0x00000000,USE_GPO2=0,GPO2_SIZE=32,GPO2_INIT=0x00000000,USE_GPO3=0,GPO3_SIZE=32,GPO3_INIT=0x00000000,USE_GPO4=0,GPO4_SIZE=32,GPO4_INIT=0x00000000,USE_GPI1=0,GPI1_SIZE=32,GPI1_INTERRUPT=0,USE_GPI2=0,GPI2_SIZE=32,GPI2_INTERRUPT=0,USE_GPI3=0,GPI3_SIZE=32,GPI3_INTERRUPT=0,USE_GPI4=0,GPI4_SIZE=32,GPI4_INTERRUPT=0,INTC_USE_EXT_INTR=0,INTC_INTR_SIZE=1,INTC_LEVEL_EDGE=0x0000,INTC_POSITIVE=0xFFFF,INT\
C_ASYNC_INTR=0xFFFF,INTC_NUM_SYNC_FF=2,Component_Name=ddr4_core_d_microblaze_mcs,USE_BOARD_FLOW=false,CLK_BOARD_INTERFACE=Custom,RESET_BOARD_INTERFACE=Custom,GPIO1_BOARD_INTERFACE=Custom,GPIO2_BOARD_INTERFACE=Custom,GPIO3_BOARD_INTERFACE=Custom,GPIO4_BOARD_INTERFACE=Custom,UART_BOARD_INTERFACE=Custom}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ddr4_core_d_microblaze_mcs (
  Clk,
  Reset,
  TRACE_data_access,
  TRACE_data_address,
  TRACE_data_byte_enable,
  TRACE_data_read,
  TRACE_data_write,
  TRACE_data_write_value,
  TRACE_dcache_hit,
  TRACE_dcache_rdy,
  TRACE_dcache_read,
  TRACE_dcache_req,
  TRACE_delay_slot,
  TRACE_ex_piperun,
  TRACE_exception_kind,
  TRACE_exception_taken,
  TRACE_icache_hit,
  TRACE_icache_rdy,
  TRACE_icache_req,
  TRACE_instruction,
  TRACE_jump_hit,
  TRACE_jump_taken,
  TRACE_mb_halted,
  TRACE_mem_piperun,
  TRACE_msr_reg,
  TRACE_new_reg_value,
  TRACE_of_piperun,
  TRACE_pc,
  TRACE_pid_reg,
  TRACE_reg_addr,
  TRACE_reg_write,
  TRACE_valid_instr,
  IO_addr_strobe,
  IO_address,
  IO_byte_enable,
  IO_read_data,
  IO_read_strobe,
  IO_ready,
  IO_write_data,
  IO_write_strobe
);

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN bd_d2ea_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.Clk CLK" *)
input wire Clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.Reset RST" *)
input wire Reset;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS" *)
output wire TRACE_data_access;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS" *)
output wire [0 : 31] TRACE_data_address;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE" *)
output wire [0 : 3] TRACE_data_byte_enable;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ" *)
output wire TRACE_data_read;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE" *)
output wire TRACE_data_write;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE" *)
output wire [0 : 31] TRACE_data_write_value;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT" *)
output wire TRACE_dcache_hit;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY" *)
output wire TRACE_dcache_rdy;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ" *)
output wire TRACE_dcache_read;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ" *)
output wire TRACE_dcache_req;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT" *)
output wire TRACE_delay_slot;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN" *)
output wire TRACE_ex_piperun;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND" *)
output wire [0 : 4] TRACE_exception_kind;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN" *)
output wire TRACE_exception_taken;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT" *)
output wire TRACE_icache_hit;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY" *)
output wire TRACE_icache_rdy;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ" *)
output wire TRACE_icache_req;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION" *)
output wire [0 : 31] TRACE_instruction;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT" *)
output wire TRACE_jump_hit;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN" *)
output wire TRACE_jump_taken;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED" *)
output wire TRACE_mb_halted;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN" *)
output wire TRACE_mem_piperun;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG" *)
output wire [0 : 14] TRACE_msr_reg;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE" *)
output wire [0 : 31] TRACE_new_reg_value;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN" *)
output wire TRACE_of_piperun;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PC" *)
output wire [0 : 31] TRACE_pc;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PID_REG" *)
output wire [0 : 7] TRACE_pid_reg;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR" *)
output wire [0 : 4] TRACE_reg_addr;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE" *)
output wire TRACE_reg_write;
(* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR" *)
output wire TRACE_valid_instr;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE" *)
output wire IO_addr_strobe;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS" *)
output wire [31 : 0] IO_address;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE" *)
output wire [3 : 0] IO_byte_enable;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA" *)
input wire [31 : 0] IO_read_data;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE" *)
output wire IO_read_strobe;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READY" *)
input wire IO_ready;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA" *)
output wire [31 : 0] IO_write_data;
(* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE" *)
output wire IO_write_strobe;

  bd_d2ea inst (
    .Clk(Clk),
    .Reset(Reset),
    .TRACE_data_access(TRACE_data_access),
    .TRACE_data_address(TRACE_data_address),
    .TRACE_data_byte_enable(TRACE_data_byte_enable),
    .TRACE_data_read(TRACE_data_read),
    .TRACE_data_write(TRACE_data_write),
    .TRACE_data_write_value(TRACE_data_write_value),
    .TRACE_dcache_hit(TRACE_dcache_hit),
    .TRACE_dcache_rdy(TRACE_dcache_rdy),
    .TRACE_dcache_read(TRACE_dcache_read),
    .TRACE_dcache_req(TRACE_dcache_req),
    .TRACE_delay_slot(TRACE_delay_slot),
    .TRACE_ex_piperun(TRACE_ex_piperun),
    .TRACE_exception_kind(TRACE_exception_kind),
    .TRACE_exception_taken(TRACE_exception_taken),
    .TRACE_icache_hit(TRACE_icache_hit),
    .TRACE_icache_rdy(TRACE_icache_rdy),
    .TRACE_icache_req(TRACE_icache_req),
    .TRACE_instruction(TRACE_instruction),
    .TRACE_jump_hit(TRACE_jump_hit),
    .TRACE_jump_taken(TRACE_jump_taken),
    .TRACE_mb_halted(TRACE_mb_halted),
    .TRACE_mem_piperun(TRACE_mem_piperun),
    .TRACE_msr_reg(TRACE_msr_reg),
    .TRACE_new_reg_value(TRACE_new_reg_value),
    .TRACE_of_piperun(TRACE_of_piperun),
    .TRACE_pc(TRACE_pc),
    .TRACE_pid_reg(TRACE_pid_reg),
    .TRACE_reg_addr(TRACE_reg_addr),
    .TRACE_reg_write(TRACE_reg_write),
    .TRACE_valid_instr(TRACE_valid_instr),
    .IO_addr_strobe(IO_addr_strobe),
    .IO_address(IO_address),
    .IO_byte_enable(IO_byte_enable),
    .IO_read_data(IO_read_data),
    .IO_read_strobe(IO_read_strobe),
    .IO_ready(IO_ready),
    .IO_write_data(IO_write_data),
    .IO_write_strobe(IO_write_strobe)
  );
endmodule


//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
//  This file contains confidential and proprietary information
//  of Xilinx, Inc. and is protected under U.S. and
//  international copyright and other intellectual property
//  laws.
//
//  DISCLAIMER
//  This disclaimer is not a license and does not grant any
//  rights to the materials distributed herewith. Except as
//  otherwise provided in a valid license issued to you by
//  Xilinx, and to the maximum extent permitted by applicable
//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//  (2) Xilinx shall not be liable (whether in contract or tort,
//  including negligence, or under any other theory of
//  liability) for any loss or damage of any kind or nature
//  related to, arising under or in connection with these
//  materials, including for any direct, or any indirect,
//  special, incidental, or consequential loss or damage
//  (including loss of data, profits, goodwill, or any type of
//  loss or damage suffered as a result of any action brought
//  by a third party) even if such damage or loss was
//  reasonably foreseeable or Xilinx had been advised of the
//  possibility of the same.
//
//  CRITICAL APPLICATIONS
//  Xilinx products are not designed or intended to be fail-
//  safe, or for use in any application requiring fail-safe
//  performance, such as life-support or safety devices or
//  systems, Class III medical devices, nuclear facilities,
//  applications related to the deployment of airbags, or any
//  other applications that could lead to death, personal
//  injury, or severe property or environmental damage
//  (individually and collectively, "Critical
//  Applications"). Customer assumes the sole risk and
//  liability of any use of Xilinx products in Critical
//  Applications, subject only to applicable laws and
//  regulations governing limitations on product liability.
//
//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//  PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
//   A generic module to merge all axi signals into one signal called payload.
//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard:  Verilog 2001
//--------------------------------------------------------------------------
//

`timescale 1ps/1ps
`default_nettype none

(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
  parameter integer C_AXI_PROTOCOL                = 0,
  parameter integer C_AXI_ID_WIDTH                = 4,
  parameter integer C_AXI_ADDR_WIDTH              = 32,
  parameter integer C_AXI_DATA_WIDTH              = 32,
  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,
  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
  parameter integer C_AXI_AWUSER_WIDTH            = 1,
  parameter integer C_AXI_WUSER_WIDTH             = 1,
  parameter integer C_AXI_BUSER_WIDTH             = 1,
  parameter integer C_AXI_ARUSER_WIDTH            = 1,
  parameter integer C_AXI_RUSER_WIDTH             = 1,
  parameter integer C_AWPAYLOAD_WIDTH             = 61,
  parameter integer C_WPAYLOAD_WIDTH              = 73,
  parameter integer C_BPAYLOAD_WIDTH              = 6,
  parameter integer C_ARPAYLOAD_WIDTH             = 61,
  parameter integer C_RPAYLOAD_WIDTH              = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
  // Slave Interface Write Address Ports
  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,
  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,
  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
  input  wire [3-1:0]                               s_axi_awsize,
  input  wire [2-1:0]                               s_axi_awburst,
  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
  input  wire [4-1:0]                               s_axi_awcache,
  input  wire [3-1:0]                               s_axi_awprot,
  input  wire [4-1:0]                               s_axi_awregion,
  input  wire [4-1:0]                               s_axi_awqos,
  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,

  // Slave Interface Write Data Ports
  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,
  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,
  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,
  input  wire                                       s_axi_wlast,
  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,

  // Slave Interface Write Response Ports
  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,
  output wire [2-1:0]                               s_axi_bresp,
  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,

   // Slave Interface Read Address Ports
  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,
  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,
  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
  input  wire [3-1:0]                               s_axi_arsize,
  input  wire [2-1:0]                               s_axi_arburst,
  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
  input  wire [4-1:0]                               s_axi_arcache,
  input  wire [3-1:0]                               s_axi_arprot,
  input  wire [4-1:0]                               s_axi_arregion,
  input  wire [4-1:0]                               s_axi_arqos,
  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,

  // Slave Interface Read Data Ports
  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,
  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,
  output wire [2-1:0]                               s_axi_rresp,
  output wire                                       s_axi_rlast,
  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,

  // payloads
  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,
  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,
  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,
  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,
  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload
);

////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0.vh"

////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////

// AXI4, AXI4LITE, AXI3 packing
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;

assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;

assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];

assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;

assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];

generate
  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;
    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;
    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;
    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;
    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;

    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;
    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;
    end
    else begin : gen_no_axi3_wid_packing
    end

    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];

    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;
    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;
    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;
    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;
    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;

    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];

    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
    end
    else begin : gen_no_region_signals
    end
    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;
      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
    end
    else begin : gen_no_user_signals
      assign s_axi_buser = 'b0;
      assign s_axi_ruser = 'b0;
    end
  end
  else begin : gen_axi4lite_packing
    assign s_axi_bid = 'b0;
    assign s_axi_buser = 'b0;

    assign s_axi_rlast = 1'b1;
    assign s_axi_rid   = 'b0;
    assign s_axi_ruser = 'b0;
  end
endgenerate
endmodule

`default_nettype wire

//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
//  This file contains confidential and proprietary information
//  of Xilinx, Inc. and is protected under U.S. and
//  international copyright and other intellectual property
//  laws.
//
//  DISCLAIMER
//  This disclaimer is not a license and does not grant any
//  rights to the materials distributed herewith. Except as
//  otherwise provided in a valid license issued to you by
//  Xilinx, and to the maximum extent permitted by applicable
//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//  (2) Xilinx shall not be liable (whether in contract or tort,
//  including negligence, or under any other theory of
//  liability) for any loss or damage of any kind or nature
//  related to, arising under or in connection with these
//  materials, including for any direct, or any indirect,
//  special, incidental, or consequential loss or damage
//  (including loss of data, profits, goodwill, or any type of
//  loss or damage suffered as a result of any action brought
//  by a third party) even if such damage or loss was
//  reasonably foreseeable or Xilinx had been advised of the
//  possibility of the same.
//
//  CRITICAL APPLICATIONS
//  Xilinx products are not designed or intended to be fail-
//  safe, or for use in any application requiring fail-safe
//  performance, such as life-support or safety devices or
//  systems, Class III medical devices, nuclear facilities,
//  applications related to the deployment of airbags, or any
//  other applications that could lead to death, personal
//  injury, or severe property or environmental damage
//  (individually and collectively, "Critical
//  Applications"). Customer assumes the sole risk and
//  liability of any use of Xilinx products in Critical
//  Applications, subject only to applicable laws and
//  regulations governing limitations on product liability.
//
//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//  PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------

`timescale 1ps/1ps
`default_nettype none

(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
  parameter         C_FAMILY     = "virtex7",
  parameter integer C_PAYLOAD_WIDTH = 1,
  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
  input  wire                        aclk,    // Clock
  input  wire                        aresetn,  // Reset
  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data
  input  wire                        s_valid, // Input data valid
  output reg                         s_ready, // Input data ready
  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data
  output reg                         m_valid, // Output data valid
  input  wire                        m_ready  // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
  integer s;
  begin
    s = size;
    s = s - 1;
    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
          s = s >> 1;
  end
endfunction // clogb2

////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);

////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;
wire [4-1:0]                        fifo_addr;
wire                                push;
wire                                pop ;
reg                                 areset_r1;

////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////

always @(posedge aclk) begin
  areset_r1 <= ~aresetn;
end

always @(posedge aclk) begin
  if (~aresetn) begin
    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
  end
  else begin
    fifo_index <= push & ~pop ? fifo_index + 1'b1 :
                  ~push & pop ? fifo_index - 1'b1 :
                  fifo_index;
  end
end

assign push = s_valid & s_ready;

always @(posedge aclk) begin
  if (~aresetn) begin
    s_ready <= 1'b0;
  end
  else begin
    s_ready <= areset_r1 ? 1'b1 :
               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
               ~push & pop ? 1'b1 :
               s_ready;
  end
end

assign pop = m_valid & m_ready;

always @(posedge aclk) begin
  if (~aresetn) begin
    m_valid <= 1'b0;
  end
  else begin
    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
               push & ~pop ? 1'b1 :
               m_valid;
  end
end

generate
  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
  end
  else begin : gen_fifo_addr
    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
  end
endgenerate

generate
  genvar i;
  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
    SRL16E
    u_srl_fifo(
      .Q   ( m_payload[i] ) ,
      .A0  ( fifo_addr[0]     ) ,
      .A1  ( fifo_addr[1]     ) ,
      .A2  ( fifo_addr[2]     ) ,
      .A3  ( fifo_addr[3]     ) ,
      .CE  ( push              ) ,
      .CLK ( aclk              ) ,
      .D   ( s_payload[i] )
    );
  end
endgenerate

endmodule

`default_nettype wire

//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
//  This file contains confidential and proprietary information
//  of Xilinx, Inc. and is protected under U.S. and
//  international copyright and other intellectual property
//  laws.
//
//  DISCLAIMER
//  This disclaimer is not a license and does not grant any
//  rights to the materials distributed herewith. Except as
//  otherwise provided in a valid license issued to you by
//  Xilinx, and to the maximum extent permitted by applicable
//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//  (2) Xilinx shall not be liable (whether in contract or tort,
//  including negligence, or under any other theory of
//  liability) for any loss or damage of any kind or nature
//  related to, arising under or in connection with these
//  materials, including for any direct, or any indirect,
//  special, incidental, or consequential loss or damage
//  (including loss of data, profits, goodwill, or any type of
//  loss or damage suffered as a result of any action brought
//  by a third party) even if such damage or loss was
//  reasonably foreseeable or Xilinx had been advised of the
//  possibility of the same.
//
//  CRITICAL APPLICATIONS
//  Xilinx products are not designed or intended to be fail-
//  safe, or for use in any application requiring fail-safe
//  performance, such as life-support or safety devices or
//  systems, Class III medical devices, nuclear facilities,
//  applications related to the deployment of airbags, or any
//  other applications that could lead to death, personal
//  injury, or severe property or environmental damage
//  (individually and collectively, "Critical
//  Applications"). Customer assumes the sole risk and
//  liability of any use of Xilinx products in Critical
//  Applications, subject only to applicable laws and
//  regulations governing limitations on product liability.
//
//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//  PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
//   A generic module to merge all axi signals into one signal called payload.
//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard:  Verilog 2001
//--------------------------------------------------------------------------
//

`timescale 1ps/1ps
`default_nettype none

(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
  parameter integer C_AXI_PROTOCOL                = 0,
  parameter integer C_AXI_ID_WIDTH                = 4,
  parameter integer C_AXI_ADDR_WIDTH              = 32,
  parameter integer C_AXI_DATA_WIDTH              = 32,
  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,
  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
  parameter integer C_AXI_AWUSER_WIDTH            = 1,
  parameter integer C_AXI_WUSER_WIDTH             = 1,
  parameter integer C_AXI_BUSER_WIDTH             = 1,
  parameter integer C_AXI_ARUSER_WIDTH            = 1,
  parameter integer C_AXI_RUSER_WIDTH             = 1,
  parameter integer C_AWPAYLOAD_WIDTH             = 61,
  parameter integer C_WPAYLOAD_WIDTH              = 73,
  parameter integer C_BPAYLOAD_WIDTH              = 6,
  parameter integer C_ARPAYLOAD_WIDTH             = 61,
  parameter integer C_RPAYLOAD_WIDTH              = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
  // Slave Interface Write Address Ports
  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,
  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,
  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
  output wire [3-1:0]                               m_axi_awsize,
  output wire [2-1:0]                               m_axi_awburst,
  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
  output wire [4-1:0]                               m_axi_awcache,
  output wire [3-1:0]                               m_axi_awprot,
  output wire [4-1:0]                               m_axi_awregion,
  output wire [4-1:0]                               m_axi_awqos,
  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,

  // Slave Interface Write Data Ports
  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,
  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,
  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,
  output wire                                       m_axi_wlast,
  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,

  // Slave Interface Write Response Ports
  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,
  input  wire [2-1:0]                               m_axi_bresp,
  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,

   // Slave Interface Read Address Ports
  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,
  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,
  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
  output wire [3-1:0]                               m_axi_arsize,
  output wire [2-1:0]                               m_axi_arburst,
  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
  output wire [4-1:0]                               m_axi_arcache,
  output wire [3-1:0]                               m_axi_arprot,
  output wire [4-1:0]                               m_axi_arregion,
  output wire [4-1:0]                               m_axi_arqos,
  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,

  // Slave Interface Read Data Ports
  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,
  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,
  input  wire [2-1:0]                               m_axi_rresp,
  input  wire                                       m_axi_rlast,
  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,

  // payloads
  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,
  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,
  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,
  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,
  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload
);

////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0.vh"

////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////

// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];

assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];

assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;

assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];

assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;

generate
  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;
    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;
    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;
    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;
    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;

    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;
    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;
    end
    else begin : gen_no_axi3_wid_packing
      assign m_axi_wid = 1'b0;
    end

    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;

    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;
    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;
    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;
    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;
    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;

    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;

    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
    end
    else begin : gen_no_region_signals
      assign m_axi_awregion = 'b0;
      assign m_axi_arregion = 'b0;
    end
    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;
      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;
      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;
    end
    else begin : gen_no_user_signals
      assign m_axi_awuser = 'b0;
      assign m_axi_wuser = 'b0;
      assign m_axi_aruser = 'b0;
    end
  end
  else begin : gen_axi4lite_packing
    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
    assign m_axi_awburst = 'b0;
    assign m_axi_awcache = 'b0;
    assign m_axi_awlen = 'b0;
    assign m_axi_awlock = 'b0;
    assign m_axi_awid = 'b0;
    assign m_axi_awqos = 'b0;

    assign m_axi_wlast = 1'b1;
    assign m_axi_wid = 'b0;

    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
    assign m_axi_arburst = 'b0;
    assign m_axi_arcache = 'b0;
    assign m_axi_arlen = 'b0;
    assign m_axi_arlock = 'b0;
    assign m_axi_arid = 'b0;
    assign m_axi_arqos = 'b0;

    assign m_axi_awregion = 'b0;
    assign m_axi_arregion = 'b0;

    assign m_axi_awuser = 'b0;
    assign m_axi_wuser = 'b0;
    assign m_axi_aruser = 'b0;
  end
endgenerate
endmodule

`default_nettype wire