Aarushhh/wikipedia-simple-splitted huggingface dataset:
Gunnedah is a town in north-western New South Wales, Australia. In 2006 there were 7,542 people living in the town.

Gunnedah is on the Oxley and Kamilaroi Highways. It is 475 kms from  Sydney. There is also a railway to Sydney. There is a daily train service, the Countrylink Xplorer, between Sydney and Moree.

The major business is agriculture. Gunnedah produces cotton, coal, beef, lamb, pork, and cereal and oilseed grains.
Gunnedah is also the home of AgQuip, Australia's largest annual exhibition of agricultural equipment.

History
The Gunnedah area was the home of the Australian Aborigines who spoke the Kamilaroi (Gamilaraay) language. The area of the town was settled by Europeans in 1833 or 1834.

Dorothea Mackellar wrote her famous poem My Country (popularly known as I Love a Sunburnt Country) about her family's farm near Gunnedah. Every year the Dorothea Mackellar Poetry Awards for school students are held in Gunnedah.
Coal was found on Black Jack Hill in 1877. By 1891, 6,000 tons of coal had been dug from shafts. The Gunnedah Colliery Company was registered in May, 1899. One month later a private railway some 5.7 km in length had been completed from the railway station to their mine. In September, 1957, the Government Railway took over the working of the line.

"The Red Chief," by great Australian author Ion L. Idriess, tells the true story of "Red Kangaroo" and his tribe, from this area.

Geography
Gunnedah Shire is 264 metres above sea level on the Liverpool Plains in the Namoi River valley. It is very flat. The tallest hills are only 200 metres above the flat plains. The climate is hot in summer, mild in winter and dry. Rainstorms occasionally cause flooding of the Namoi River. Floods can cut transport links to the town and cut it off from the outside world.

The Gunnedah area has a lot of Australian wildlife, including kangaroos, echidnas and koalas. Koalas can often be seen in trees within the town.
Media 
There is a newspaper, the Namoi Valley Independent. There are 2 radio stations 2MO and 2GGG. 2MO claims to be the first station started in Australia outside the capital cities.

Railway station 
Gunnedah railway station is on the Mungindi (or North West) railway line, 475 km from Sydney. The station was opened in 1879. There is a large station building with single platform.  There is also a passing loop and small goods yard. There is a single daily Xplorer diesel railmotor operating between Sydney and Moree.

Other websites 
Info Gunnedah 
AgQuip
Gunnedah Shire Profile 
Gunnedah Speedway
Gunnedah High School
Gunnedah South Public School

References 

Towns in New South Wales
Instruction pipelining is a technique used in the design of modern microprocessors, microcontrollers and CPUs to increase their instruction throughput (the number of instructions that can be executed in a unit of time).

The main  idea is to divide (termed "split") the processing of a CPU instruction, as defined by the instruction microcode, into a series of independent steps of micro-operations (also called  "microinstructions", "micro-op" or "µop"), with storage at the end of each step.  This allows the CPUs control logic to handle instructions at the processing rate of the slowest step, which is much faster than the time needed to process the instruction as a single step.

The term pipeline refers to the fact that each step is carrying a single microinstruction (like a drop of water), and each step is linked to another step (analogy; similar to water pipes).
Most modern CPUs are driven by a clock. The CPU consists internally of logic and memory (flip flops). When the clock signal arrives, the flip flops store their new value then the logic requires a period of time to decode the flip flops new values. Then the next clock pulse arrives and the flip flops store another values, and so on. By breaking the logic into smaller pieces and inserting flip flops between pieces of logic, the time required by the logic (to decode values till generating valid outputs depending on these values) is reduced. In this way the clock period can be reduced.For example, the RISC pipeline is broken into five stages with a set of flip flops between each stage as follows:
Instruction fetch 
Instruction decode and register fetch 
Execute 
Memory access 
Register write back
Processors with pipelining consist internally of stages (modules) which can semi-independently work on separate microinstructions. Each stage is linked by flip flops to the next stage (like a "chain") so that the stage's output is an input to another stage until the job of processing instructions is done. Such organization of processor internal modules reduces the instruction's overall processing time.

A non-pipeline architecture is not as efficient because some CPU modules are idle while another module is active during the instruction cycle. Pipelining does not completely remove idle time in a pipelined CPU, but making CPU modules work in parallel increases instruction throughput.

An instruction pipeline is said to be fully pipelined if it can accept a new instruction every clock cycle. A pipeline that is not fully pipelined has wait cycles that delay the progress of the pipeline.
Advantages and Disadvantages of Pipelining
Advantages of Pipelining:
The cycle time of the processor is reduced; increasing the instruction throughput. Pipelining doesn't reduce the time it takes to complete an instruction; instead it increases the number of instructions that can be processed simultaneously ("at once") and reduces the delay between completed instructions (called 'throughput').The more pipeline stages a processor has, the more instructions it can process "at once" and the less of a delay there is between completed instructions. Every predominant general purpose microprocessor manufactured today uses at least 2 stages of pipeline up to 30 or 40 stages.
If pipelining is used, the CPU Arithmetic logic unit can be designed faster, but will be more complex.
Pipelining in theory increases performance over an un-pipelined core by a factor of the number of stages (assuming the clock frequency also increases by the same factor) and the code is ideal for pipeline execution.
Disadvantages of  Pipelining:
Pipelining has many disadvantages though there are a lot of techniques used by CPUs and compilers designers to overcome most of them; the following is a list of common drawbacks:
The design of a non-pipelined processor is simpler and cheaper to manufacture, non-pipelined processor executes only a single instruction at a time. This prevents branch delays (in Pipelining, every branch is delayed) as well as problems when serial instructions being executed concurrently.
In pipelined processor, insertion of flip flops between modules increases the instruction latency compared to a non-pipelining processor.
A non-pipelined processor will have a defined instruction throughput. The performance of a pipelined processor is much harder to predict and may vary widely for different programs.
Many designs include pipelines as long as 7, 10, 20, 31 and even more stages; a disadvantage of a long pipeline is when a program branches, the entire pipeline must be flushed (cleared). The higher throughput of pipelines falls short when the executed code contains many branches: the processor cannot know in advance where to read the next instruction, and must wait for the branch instruction to finish, leaving the pipeline behind it empty. This disadvantage can be reduced by predicting whether the a conditional branch instruction will branch based on previous activity. After the branch is resolved, the next instruction has to travel all the way through the pipeline before its result becomes available and the processor resumes "working" again.  In such extreme cases, the performance of a pipelined processor could be worse than non-pipelined processor.
Unfortunately, not all instructions are independent. In a simple pipeline, completing an instruction may require 5 stages.  To operate at full performance, this pipeline will need to run 4 subsequent independent instructions while the first is completing.  Any of those 4 instructions might depend on the output of the first instruction, causing the pipeline control logic to wait and insert a stall or wasted clock cycle into the pipeline until the dependency is resolved.  Fortunately, techniques such as forwarding can significantly reduce the cases where stalling is required.
 Self-modifying programs may fail to execute properly on a pipelined architecture when the instructions being modified are near the instructions being executed. This can be caused by the instructions may already being in the Prefetch Input Queue, so the modification may not take effect for the upcoming execution of instructions. Instruction caches make the problem even worse.
Hazards: When a programmer (or compiler) writes assembly code, they generally assume that each instruction is executed before the next instruction is being executed. When this assumption is not validated by pipelining it causes a program to behave incorrectly, the situation is known as a hazard.Various techniques for resolving hazards or working around such as forwarding and delaying (by inserting a stall or a wasted clock cycle) exist.
Examples

Generic pipeline

To the right is a generic pipeline with four stages:
 Fetch
 Decode
 Execute
 Write-back

The top gray box is the list of instructions waiting to be executed; the bottom gray box is the list of instructions that have been completed; and the middle white box is the pipeline.

Execution is as follows:

Bubble

When a "hiccup" (interruption) in execution occurs, a "bubble" is created in the pipeline in which nothing useful happens. In cycle 2, the fetching of the purple instruction is delayed and the decoding stage in cycle 3 now contains a bubble. Everything behind the purple instruction is delayed as well but everything in front of the purple instruction continues with execution.

Clearly, when compared to the execution above, the bubble yields a total execution time of 8 clock ticks instead of 7.

Bubbles are like stalls (delays), in which nothing useful will happen for the fetch, decode, execute and writeback. It is like a NOP (short for No OPeration) code.
Example 1
A typical instruction to add two numbers might be ADD A, B, C, which adds the values found in memory locations A and B, and then puts the result in memory location C. In a pipelined processor the pipeline controller would break this into a series of tasks similar to:

LOAD A, R1
LOAD B, R2
ADD R1, R2, R3
STORE R3, C
LOAD next instruction

The locations 'R1' and 'R2' are registers in the CPU. The values stored in memory locations labeled 'A' and 'B' are loaded (copied) into these registers, then added, and the result is stored in a memory location labeled 'C'.

In this example the pipeline is three stages long- load, execute, and store. Each of the steps are called pipeline stages.
On a non-pipelined processor, only one stage can be working at a time so the entire instruction has to complete before the next instruction can begin. On a pipelined processor, all of the stages can be working at once on different instructions. So when this instruction is at the execute stage, a second instruction will be at the decode stage and a 3rd instruction will be at the fetch stage.

Example 2
To better understand the concept, we can look at a theoretical 3-stage pipeline:

and a pseudo-code assembly listing to be executed:

LOAD  #40, A      ; load 40 in A
MOVE  A, B        ; copy A in B
ADD   #20, B      ; add 20 to B
STORE B, 0x300    ; store B into memory cell 0x300

This is how it would be executed:

The LOAD instruction is fetched from memory.

The LOAD instruction is executed, while the MOVE instruction is fetched from memory.
The LOAD instruction is in the Store stage, where its result (the number 40) will be stored in the register A.
In the meantime, the MOVE instruction is being executed. 
Since it must move the contents of A into B, it must wait for the ending of the LOAD instruction.

The STORE instruction is loaded, while the MOVE instruction is finishing off and the ADD is calculating.

And so on. Note that, sometimes, an instruction will depend on the result of another one (like our MOVE example). When more than one instruction references a particular location for an operand, either reading it (as an input) or writing it (as an output), executing those instructions in an order different from the original program order can lead to the hazards situation (mentioned above).

Related pages
 Pipeline (computing)
 Parallel computing
 Instruction-level parallelism

Other websites
 Branch Prediction in the Pentium Family
 ArsTechnica article on pipelining
 Counterflow Pipeline Processor Architecture 

Computer architecture
Sami Hyypiä (born 7 October 1973 in Porvoo) is a Finnish football player. He plays for Bayer Leverkusen and the Finland national team.  He is a defender in both of his teams and is captain of Finland and used to be the captain of Liverpool.

Club career statistics

|-
|1992||rowspan="4"|Myllykosken Pallo||rowspan="4"|Veikkausliiga||33||0||||||||||0||0||33||0
|-
|1993||12||0||||||||||1||0||13||0
|-
|1994||25||5||||||||||4||0||29||5
|-
|1995||26||3||||||||||4||0||30||3

|-
|1995/96||rowspan="4"|Willem II||rowspan="4"|Eredivisie||14||0||0||0||colspan="2"|-||0||0||14||0
|-
|1996/97||30||1||5||1||colspan="2"|-||0||0||35||2
|-
|1997/98||30||0||3||0||colspan="2"|-||0||0||33||0
|-
|1998/99||26||2||1||0||colspan="2"|-||4||0||31||2
|-
|1999/00||rowspan="10"|Liverpool||rowspan="10"|Premier League||38||2||2||0||2||0||0||0||42||2
|-
|2000/01||35||3||6||0||6||1||11||0||58||4
|-
|2001/02||37||3||2||0||1||0||16||2||56||5
|-
|2002/03||36||3||3||0||4||0||12||2||55||5
|-
|2003/04||38||4||4||0||1||0||8||1||51||5
|-
|2004/05||32||2||1||0||1||0||15||1||49||3
|-
|2005/06||36||1||6||1||1||0||14||0||57||2
|-
|2006/07||23||2||0||0||1||1||5||0||29||3
|-
|2007/08||27||1||4||1||0||0||13||2||44||4
|-
|2008/09||16||1||1||0||2||1||0||0||19||2

|-
|2009/10||Bayer Leverkusen||Bundesliga||||||||||||||||||||
96||8||||||||||9||0||105||8
100||3||9||1||colspan="2"|-||4||0||113||4
318||22||29||2||19||3||94||8||460||35
0||0||0||0||0||0||0||0||0||0
514||32||38||3||19||3||107||8||678||47
|}

International career statistics
|-
|1992||1||0
|-
|1993||0||0
|-
|1994||2||0
|-
|1995||4||0
|-
|1996||5||0
|-
|1997||4||0
|-
|1998||7||0
|-
|1999||7||1
|-
|2000||6||0
|-
|2001||7||0
|-
|2002||6||1
|-
|2003||9||2
|-
|2004||8||0
|-
|2005||8||0
|-
|2006||7||1
|-
|2007||9||0
|-
|2008||5||0
|-
|2009||8||0
|-
!Total||103||5
|}

Other websites
Thisisanfield.com player profile
Profile at ESPNsoccernet.com

References

1973 births
Living people
Finnish footballers
Tracks
 P!nk – "So What"
 E.G. Daily – "Changing Faces"
 Pussycat Dolls – "When I Grow Up"
 Sarah Robertson – "Exhausted"
 Ne-Yo – "Closer"
 Chris Brown – "Forever"
 Kardinal Offishall featuring Akon – "Dangerous"
 T.I. – "Whatever You Like"
 Lil Wayne featuring T-Pain – "Got Money"
 Savage featuring Soulja Boy Tell 'Em – "Swing"
 Young Jeezy featuring Kanye West – "Put On"
 Yung Berg featuring Casha – "The Business"
 Jordin Sparks – "One Step at a Time"
 Leona Lewis – "Better In Time"
 Boys Like Girls – "Thunder"
 Saving Abel – "Addicted"
 Daughtry – "What About Now"
 Matt Nathanson – "Come On Get Higher"
 Darius Rucker – "Don't Think I Don't Think About It"
 Keith Anderson – "I Still Miss You"
Christina Aguilera - "Reflection"
Rihanna - "Disturbia"
Katy Perry - "Hot 'n' Cold"

Related pages
 Now That's What I Call Music! (U.S. Series)

2009 albums
Compilation albums
Thrissur is one of the fourteen districts of Kerala in southwest India. It is the second largest city in Kerala and 20th largest city in India. At the center of the city is a temple, the Vadakkumnathan temple which has Lord Siva as its presiding deity. It is known as the cultural capital of Kerala because of the city's association with history, culture and archaeological remains. Thrissur was once the capital of the Kingdom of Cochin. It is located 300 kilometers (186 mi) towards north-west of the state capital Thiruvananthapuram. It is famous for Thrissur Pooram which is a temple festival. Thrissur is also known as the “cultural capital of Kerala” as its well known for its cultural, spiritual and religious learnings throughout history.

Other websites 
 Satellite image of Thrissur
 Thrissur District Information- Hotels, Hospitals, Thrissur Places, Shops, Doctors, Banks, etc.

Districts of Kerala
Michigan Territory was a territory of the United States in the early 19th century, between June 30, 1805 and January 26, 1837, when it became Michigan, the 26th state of the Union. Detroit was the territory's capital.

History

The Treaty of Detroit was signed on November 17, 1807 between William Hurt and American Indians from the Odawa, Ojibwe, Potawatomi, and Wyandot people. Those Indian tribes agreed to give the United States the area of Southeast Michigan and a part of Ohio near the Maumee River. The Indians were allowed to own small amounts of land in the area. This helped expand the territory.

Population
These numbers do not count most Native Americans.  In 1800, the whole of the Northwest Territory had 43,365 people living in it. Under the Northwest Ordinance, a territory could apply to become a state once it had 60,000 people living in it.

Governors

References

Other websites
An act to divide Indiana Territory  (the law which created the Michigan Territory)
History of Michigan
1805 establishments in the United States
1837 disestablishments
19th-century disestablishments in the United States
Former territories of the United States
The Syro-Malabar Catholic Church is a Chaldean Rite, Major Archiepiscopal Church in the Roman Catholic Church. It is the largest group among the Saint Thomas Christians. It originates from St. Thomas the Apostle who is believed to have come to India in AD 52. The Syro Malabar Church is the largest St. Thomas Christian community in India. They are also referred to as Syrian Catholics in Kerala. This church has its headquarters in Cochin, Kerala.

Cardinal Mar George Alencherry is the current head of this church.

The first Indian woman Saint, Saint Alphonsa belongs to this church.

Syro-Malabar Church has its presence all over the world. However the proper location is in South India. There are 26 Syro-Malabar dioceses world wide.

Eastern Catholicism
The Jurassic Coast is a stretch of  coast in south-west England. It is between Orcombe Point near Exmouth in East Devon and Old Harry Rocks near Swanage in East Dorset. This is 96 miles long (154 km).  

It is a UNESCO World Heritage Site.

Its entire length can be walked on the South West Coast Path.

Major fossil finds 
Some of the greatest fossil discoveries were made in this area. 
The first ichthyosaur skeleton
The first plesiosaur
The first pterosaur outside Germany
These finds were by Mary Anning in the first part of the 19th century. This area was home to Mary, a collector who searched for fossils of the coastline around Lyme Regis and discovered several complete Ichthyosaur fossils.

Geology 

The Jurassic Coast is made of Triassic, Jurassic and Cretaceous cliffs, spanning 185 million years of geological history.
The site contains a number of special features and shows different landforms, including the natural arch at Durdle Door, the cove and limestone folding at Lulworth Cove and an island, the Isle of Portland.

Chesil Beach (or Chesil Bank) is one of England's three shingle (gravel) beaches. It is a barrier beach which runs parallel to the coastline and connects to Portland Bill (see photo). Between the barrier and the regular coastline is a lagoon.

Golden Cap is the highest place on the south coast of England. It is  high.

Sequence of rocks 
This section notes the main rocks found on the coast, starting with the lowest (earliest).

Blue Lias 

The Blue Lias is a geologic formation in the Jurassic Coast and parts of south Wales. It is part of the Lias Group.
The Blue Lias consists of a sequence of limestone and shale layers. It was laid down in late Triassic and early Jurassic times, between 195 and 200 million years ago. The Blue Lias is famous for its fossils, especially ammonites. Also found were remains of a number of dinosaurs, and the pterosaur Dimorphodon.

The Blue Lias alternates between limestone, (with some clay), and mudstone.

Gateway towns 
These are special towns that are related to the Jurassic Coast:
 Weymouth
 West Bay
 Abbotsbury
 Bridport
 Budleigh Salterton
 Charmouth — Charmouth Heritage Coast Centre
 Exmouth
 Lulworth
 Lyme Regis
 Seaton
 Sidmouth
 Swanage

Pretty much the same rocks can be seen near the Yorkshire coast near Hull (Kingston upon Hull) in Yorkshire near the Humber Estuary. Also the Jurassic and Cretaceous rocks can be followed into northern France.

Gallery

Related pages 
List of World Heritage Sites of the United Kingdom

References

Other websites
Other websites 

 Jurassic Coast official website 
 The South West Coast Path National Trail
 Jurassic Coast UNESCO World Heritage site datasheet

Devon
Dorset
South West England
World Heritage Sites in the United Kingdom
Lagerstätten
Archaeological sites in England
In computer science, an instruction is a single operation of a processor defined by the processor instruction set.

The size or length of an instruction varies widely, from as little as 4-bits in some microcontrollers to many as multiples of a bytes in some very long instruction word (VLIW) systems.  Most modern processors used in personal computers, mainframes, and supercomputers have instruction sizes between 16 and 64 bits. In some architectures, especially Reduced instruction set computers, instructions are of fixed length, typically corresponding with that architecture's word size.

On traditional architectures, an instruction includes an opcode specifying the operation to be performed, such as "add contents of memory to register", and zero or more operand specifiers, which may specify registers, memory locations, or literal data. The operand specifiers may have addressing modes determining their meaning or may be in fixed fields.
In VLIW architectures, which include many microcode architectures, multiple simultaneous operations and operands are specified in a single instruction.

Instructions are rarely specified using their machine code form; they may be specified by programmers using an assembly language or, more commonly, may be generated by compilers.

There is another more general definition for an "instruction" not only related to the processor instruction set, which is: An "instruction" may be any representation of an element of an executable computer program.

Related pages
Machine language

Microprocessor design
Piacenza is a city in the region of Emilia-Romagna in Italy. It is the capital city of the province of Piacenza. 99,897 people live there. Piacenza is famous for its palazzi.

References

Other websites

 
Capital cities in Italy
Superscalar technology supports basic parallel computing (specifically, instruction-level parallelism) on one CPU (processor), which allows more than one instruction in each clock cycle by using more than one execution unit at the same time.

Superscalar processors are often pipelined as well, but that's a different technology that allows more than one instruction at once in each execution unit, rather than using multiple execution units at once.

Superscalar technology usually involves:
 Instructions coming into the processor in order.
 The processor looking for data dependencies while it runs.
 Loading more than one instruction in each clock cycle
The simplest processors are scalar processors. On a scalar processor, instructions usually work with one or two data items at once. On a vector processor, instructions usually work with many data items at once. A superscalar processor is a mix of a scalar process and a vector processor: each instruction processes one data item, but more than one instruction runs at once, so many data items are handled at once by the processor.

In a superscalar processor, it's very important to have an accurate instruction dispatcher, so that the execution units are always busy with work that probably will be needed. If the instruction dispatcher isn't accurate, the processor will have to throw away some work and might not be any faster than a scalar processor. In 2008, all normal CPUs were superscalar, and could have up to 4 ALUs, 2 FPUs, and 2 SIMD units.
Limitations
The efficiency of superscalar design is limited by three things: 
 How much parallelism is in the instruction list
 How long the dispatcher takes to check dependencies and how long register renaming takes
 The branch instruction processing
Existing programs have different levels of parallelism. In some cases, instructions are not dependent on each other and can be executed at the same time. In other cases, they are interdependent: one instruction affects another. The instructions a = b + c; d = e + f can be run in parallel because none of the results depend on other results, but the instructions a = b + c; b = e + f will probably have to be run in a specific order because a depends on b.
Alternatives
 Simultaneous multithreading: often written as "SMT", this is a technique for improving the total speed of superscalar processors. SMT allows many independent threads of execution, to make better use of the resources available inside a modern superscalar processor.
 Multi-core processors: a multi-core CPU has many processors that each have their own instruction lists, rather than just many execution units.
 Pipelined processors: a pipelined CPU supports multiple instructions at different stages of execution inside each execution unit.

All of these techniques can be (and often are) combined in a single CPU, so it is possible to have a multicore CPU is where each core is an independent processor with many parallel superscalar pipelines. Some multicore processors also include vector capability.

Related pages
 Parallel computing
 Instruction-level parallelism
 Simultaneous multithreading (SMT)
 Multi-core processors
References
 Mike Johnson, Superscalar Microprocessor Design, Prentice-Hall, 1991, 
 Sorin Cotofana, Stamatis Vassiliadis, "On the Design Complexity of the Issue Logic of Superscalar Machines", EUROMICRO 1998: 10277-10284
 Steven McGeady, "The i960CA SuperScalar Implementation of the 80960 Architecture", IEEE 1990, pp. 232–240
 Steven McGeady, et al., "Performance Enhancements in the Superscalar i960MM Embedded Microprocessor," ACM Proceedings of the 1991 Conference on Computer Architecture (Compcon), 1991, pp. 4–7

Other websites
 School of Computing, Clemson University

Computer architecture
Abercrombie may refer to:

In places:
 Abercrombie, Fife, a village in Fife, Scotland
 Abercrombie, Alabama, a place in the state of Alabama in the United States
 Abercrombie, North Dakota, a city in Richland County, North Dakota in the United States
 Abercrombie Township, Richland County, North Dakota
 Abercrombie, Texas, a place in the state of Texas in the United States
 Abercrombie River, a river in New South Wales, Australia

In business:
 Abercrombie & Fitch, an American apparel company
 abercrombie kids, (marketed simply as "abercrombie"), a children's subsidiary of Abercrombie & Fitch

Other:
 Abercrombie (horse) (1975–2000), a bay harness racing horse, won the 1978 E. Roland Harriman Award for harness horse of the year
 Abercrombie class monitor, a class of monitors that served in the Royal Navy during the First World War
 HMS Abercrombie, the name of three ships of the Royal Navy
 USS Abercrombie (DE-343), a US Navy John C. Butler-class destroyer escort of World War II
 Abercrombie (surname)
SA80 (Small Arms for the 80s) is the name of a weapons family used by the British Army and Royal Marines. All are of bullpup design: this means the magazine is behind the trigger so the weapon is shorter yet still has a long barrel.

The series includes an assault rifle known as the L85 and a Light Support Weapon (LSW) designated the L86 as well as a carbine variant for helicopter crews and a bolt action army cadet variant. 

The LSW variant is far more accurate than its predecessor, and is used in army FSGs (Fire Support Groups). They are amazingly accurate for their size (Army marksmanship tests were redesigned after the SA80 introduction because it was so accurate). Nevertheless, the SA80 family has been plagued by poor reliability. They have had an upgrade by the German arms company H&K when it was British owned. This resulted in the A2 series, but not all models have been upgraded.
The SA80 also has a cadet force variant (L98 A2 Cadet GP) that is the same size, and is used throughout the ACF. It has a success rate far higher than the old, bolt-action A1 version.

Firearms
British Army equipment
Geoff Bunn is an Anglo-Swedish author and artist. He was born in Birmingham, England in 1963.  He has been in galleries such as the Tate but is better known for placing his work in the ordinary environment rather than 'traditional' art galleries.  During the early 2000s, he worked in France, for a time, with painter Fred Yates.

Bunn has also painted a number of large and rather disturbing canvases of empty interiors. This series of paintings - which Bunn entitles 'Interior Landscapes' - led to Bunn being awarded the Cartazini Prize in 2007.

Bunn has written a number of books, including the best-selling transgender romance Blonde Boy, Red Lipstick.

References 
Documenta Exhibition 2002 

1963 births
Living people
English artists
People from Birmingham
Frederick Joseph Yates (25 July 1922 – 7 July 2008) was an English artist. He  was born in Urmston, His work was very much in the style of the late L. S. Lowry.  Yates lived and worked all over England but in later years he was based in France.

References 

1922 births
2008 deaths
English painters
People from Lancashire
This article is about the dish; the computer game can be seen at Sauerbraten (video game)
Sauerbraten is a meat dish eaten mainly in Germany, but also neighbouring countries. The name comes form sauer (sour) and braten (roast). It refers to the way the dish is prepared: the meat is left in a kind of sour sauce (based on vinegar) to marinate

German food
Meat dishes
The Economist is a magazine published each week in England. It was founded in 1843. It currently has about 1.3 million subscribers.

It was founded in 1843 by Scotsman James Wilson with assistance from the Anti-Corn Law League as a voice against England’s Corn Laws, regulations governing the import and export of grain. Wilson’s son-in-law Walter Bagehot, who served as editor of The Economist from 1861 to 1877, expanded the publication’s coverage into politics and strengthened its focus on U.S. affairs. A later admirer of Bagehot's was Woodrow Wilson, president of the United States from 1913 to 1921.
In 1992 WT Layton was appointed as editor. His editorship was of profound importance to the newspaper, and he was probably the person to whom it owes most thanks for its survival and continued independence.The Economist is classically liberal and economically liberal. It supports free trade, globalization, and the legalization of same-sex marriage and illegal drugs. It targets highly educated readers, as well as famous people such as Bill Gates, Ronald Reagan, Margaret Thatcher, and Ted Turner.

Tone and voice 
The Economist has a consistent voice, partly because its writers are anonymous. It assumes its readers have a basic understanding of economics. Its articles are often witty.

References 

British weekly magazines
Our Lady of Guadalupe (Spanish: Nuestra Señora de Guadalupe) is a name for the Virgin Mary who is said to have appeared at Tepeyac Hills in Guadalupe, a town near Mexico City. She is said to have appeared to a poor native American named Juan Diego. Our Lady of Guadalupe is one of the most popular cultural and religious icons in the Hispanic world. The feast of Our Lady of Guadalupe is celebrated each year by the Catholic Church on December 12, the anniversary of her appearance.

Roman Catholicism
Christian symbols
Mexico City
Marian apparitions
1531
Poison is an American glam metal band from Mechanicsburg, Pennsylvania.  They were formed in 1983. Their lead singer is Bret Michaels. One of their most popular hits was "Every Rose Has Its Thorn" which was the Hot 100 number-one single of December 24, 1988 and lasted until January 7, 1989.

American hard rock bands
Glam metal bands
Musical groups from Pennsylvania
Enigma Records artists
Yao was born at Shanghai Sixth People's Hospital in Shanghai, He is only child by Yao Tzi Yuan and Fong Fengdi , There are professional basketball players by their family,
He started with the Shanghai Sharks as a teenager and played on their senior team for five years in the Chinese Basketball Association (CBA). The team won a championship in his final year. Then he entered the 2002 NBA Draft. The CBA had to release him, and he was selected by the Houston Rockets to play on their team. He had also been chosen to play for the NBA All-Star Game for all six of his seasons. However, the Rockets have not advanced past the first round of the playoffs since he joined the team, and he has also had injuries in each of the past three seasons. On July 20, 2011, Yao announced that he was retiring from basketball after many foot and ankle injuries.
His father, Yao Zhiyuan, is 2.08 m or 6 ft 10 in tall; his mother, Fengdi Fang, is 1.88 m or 6 ft 2 in tall. She was captain of the Chinese national women's basketball team. Yao's parents were the tallest couple in China when he was born.

Yao is married to Ye Li, who used to play for the China women's national basketball team. He is one of China's best-known athletes. He has sponsorships with several major companies, and he has been the richest celebrity in China for six straight years, earning US$51 million (CN¥357 million) in 2008. 

His rookie year in the NBA was the subject of a documentary film, The Year of the Yao, and he recently wrote an autobiography titled Yao: A Life in Two Worlds.

References

Other websites

Yao Ming's NBA profile 

1980 births
Autobiographers
Chinese basketball players
Houston Rockets players
Living people
Sportspeople from Shanghai
Naismith Memorial Basketball Hall of Fame inductees
Emery was given various nicknames over his career, most goes by "Razor" and "Sugar Ray." In the 2001 NHL entry draft, Emery was chosen 99th overall by the Ottawa Senators. Emery was made starting goaltender in the 2006-07 NHL season. That year, the Senators made it to the Stanley Cup finals. On June 20, 2008, after some off-ice incidents, the Senators released Emery. Under one month later, Emery signed a one-year, $2M contract with Atlant Mytishchi of the Russian KHL. After his time in Russia, it was announced on June 10, 2009 that the Philadelphia Flyers had signed him to a one-year deal for $1.5 million. In March 2010, Flyers GM Paul Holmgren announced that Emery would miss the remainder of the season because of avascular necrosis and that a bone graft would be done to alleviate his hip issues. Emery began workout and rehabilitation process and later signed a one-year, two-way contract with the Anaheim Ducks on February 7, 2011
. During his time with the Ducks, he tied for fourth in the league after he posted a 7–2–0 record with a 2.28 goals-against average (GAA) and a .926 save percentage (SV%) in 10 regular season games going into the playoffs. He attended the Chicago Blackhawks training camp on a tryout basis and was later signed by the Blackhawks to a 1-year, $600,000 deal.
Emery has been known for getting into several altercations while playing ice hockey, a rarity for an ice-hockey goaltender. Emery once fought two Buffalo Sabres players, Martin Biron and Andrew Peters in a line brawl during the 2006-07 NHL season. He also fought with his teammate, Brian McGrattan, during a practice in January 2008. He has also fought with teammate's Jason Spezza and Chris Neil.

On June 24, 2013, He won the Stanley Cup with the Blackhawks after they defeated the Boston Bruins 4 games to 2 in the 2013 Stanley Cup Finals.

On July 5, 2013, he signed a $1.65 million, 1-year deal with the Philadelphia Flyers.

Death
On July 15, 2018, Emery accidentally drowned while diving at a yacht club in Hamilton, Ontario, aged 35.

Career statistics

Regular season

Playoffs 

Statistics via Eliteprospects

References

Other websites
Other websites
 

1982 births
2018 deaths
Accidental deaths by drowning
Adirondack Phantoms players
American Hockey League players
Anaheim Ducks players
Binghamton Senators players
Canadian ice hockey goaltenders
Chicago Blackhawks players
Ice hockey people from Ontario
Ontario Hockey League players
Ontario Reign (AHL) players
Ottawa Senators players
People from Hamilton
Philadelphia Flyers players
Stanley Cup champions
Syracuse Crunch players
Toronto Marlies players
The human height is the height of a human body. Factors that influence human height are genetics, what people eat, the human body's natural chemicals, and being sick or healthy.

Overall, average human height increased over the last 100 years. In 1996, the average height around the world was 171 cm for men and 159 cm for women.

Men from Bosnia and Herzegovina, the Netherlands, Croatia, Serbia and Montenegro have the tallest average height.

Related pages 
 Human weight

References 

Human body features
In computer engineering, an execution unit is a part of a CPU (not to be confused with the CPUs main control unit) that performs specific operations or calculations. It may have its own internal control sequence unit, some registers, and other internal units such as a sub-ALU or FPU, or some smaller, more specific components.

Now modern CPUs have multiple parallel execution units, referred to as scalar or superscalar design. The simplest arrangement is to use one, the bus manager, to manage the memory interface, and the others to perform calculations. Additionally, modern CPUs execution units are usually pipelined.

Other websites
 The Department's Computer Science Research Center on the UMass Faculty 

Microprocessor design
The pre-1600 Atlantic hurricane seasons talks about all known Atlantic tropical cyclones before to 1600. While info for every storm that happened is not available, some parts of the coastline had enough people to give info of hurricane happenings. Each season was an event in the annual cycle of tropical cyclone formation in the Atlantic basin. Most tropical cyclone formation occurs between June 1 and November 30.

Atlantic hurricane seasons
Pre-1600 1600s/10s 1620s/30s

Observation info for years before 1492 is completely unavailable because record keeping was non-existent in the pre-Columbian era, and any records that may have once existed have long since been lost. Even info from the early years of the Columbian era is suspect and incomplete because the difference between a hurricane and an extratropical system was not drawn by Renaissance scientists and sailors and because European exploration and colonization of the regions affected by hurricanes did not begin in earnest until the mid-16th century.
However, paleotempestological research allows reconstruction of pre-historic hurricane activity trends on timescales of centuries to millennia. A theory has been postulated that an anti-phase pattern exists between the Gulf of Mexico coast and the Atlantic coast. During the quiescent periods, a more northeasterly position of the Azores High would result in more hurricanes being steered towards the Atlantic coast. During the hyperactive period, more hurricanes were steered towards the Gulf coast as the Azores High—controlled by the North Atlantic Oscillation—was shifted to a more southwesterly position near the Caribbean. In fact, few major hurricanes struck the Gulf coast during 3000–1400 BC and again during the most recent millennium; these quiescent intervals were separated by a hyperactive period during 1400 BC and 1000 AD, when the Gulf coast was struck frequently by catastrophic hurricanes and their landfall probabilities increased by 3–5 times
. On the Atlantic coast, chance of landfalling hurricanes has doubled in the recent millennium compared to the one and a half millennia before.
Storms

Pre-1525

1525-1549

1550-1574

1575-1599

Related pages
List of Atlantic hurricane seasons

References

Further reading

Other websites
http://www.nhc.noaa.gov/pastdeadlyapp1.shtml
http://www.candoo.com/genresources/hurricane.htm 
http://www.hpc.ncep.noaa.gov/research/roth/vahur.htm
http://www.srh.noaa.gov/lch/research/la18hu.php

1599 and before
Valley Parade, also known by its sponsored name of the Coral Windows Stadium is a football stadium in Bradford in England. It is home to the club Bradford City A.F.C. It was built in 1886. In 1985, a fire in one of the stands killed 56 people.

Football stadiums in England
1886 establishments in England
Buildings and structures in Bradford
Levi Lincoln, Sr. (May 15, 1749–April 14, 1820) was an American revolutionary. He was a Minuteman at the beginning of the American Revolutionary War, a state legislator in Massachusetts, Governor of Massachusetts, Lieutenant Governor of Massachusetts, a U.S. Representative, Attorney General for President Thomas Jefferson and Acting Secretary of State.

1749 births
1820 deaths
United States Attorneys General
Lieutenant Governors of Massachusetts
Governors of Massachusetts
Lawyers from Massachusetts
James Rodney Schlesinger (February 15, 1929 - March 27, 2014) was United States Secretary of Defense from 1973 to 1975 under presidents Richard Nixon and Gerald Ford. He became America's first Secretary of Energy under Jimmy Carter.

On March 27, 2014, Schlesinger died from complications of pneumonia at a Baltimore hospital. He was 85.

References

1929 births
2014 deaths
Deaths from pneumonia
Directors of the Central Intelligence Agency
Infectious disease deaths in Maryland
Politicians from New York City
United States Secretaries of Defense
United States Secretaries of Energy
Simultaneous multithreading, acronym SMT, is a technique for improving the overall efficiency of superscalar CPUs with Hardware multithreading. SMT permits multiple independent threads of execution to better utilize the resources provided by modern computer architectures.

Multithreading is similar in concept to multitasking but is implemented at the thread level of execution in modern superscalar processors.

In processor design, there are two ways to increase on-chip parallelism with less resource requirements: 
 Superscalar technique: which tries to increase Instruction level parallelism (ILP) by executing multiple instructions at the same time (termed: simultaneously); by "simultaneously" dispatching instructions (termed: instruction dispatching) to multiple redundant execution units built inside the processor.
 Chip-level multithreading (CMT) technique: using Thread level parallelism (TLP) in order to executes instructions from multiple threads within one processor chip at the same time.
There are many ways to support more than one thread inside a chip, namely:
 Interleaved multithreading (IMT) : Interleaved issue of multiple instructions from different threads, also referred to as Temporal multithreading. It can be further divided into fine-grain multithreading or coarse-grain multithreading depending on the frequency of interleaved issues. Fine-grain multithreading issues instructions for different threads after every cycle, while coarse-grain multithreading only switches to issue  instructions from another thread when the current executing thread causes some long latency events (like page fault etc.). Coarse-grain multithreading is more common for less context switch between threads. For processors with one pipeline per core, interleaved multithreading is the only possible way, because it can only issue up to one instruction per cycle.
 Simultaneous multithreading (SMT): Issue multiple instructions from multiple threads in one cycle. The processor must be superscalar to do so.
Chip-level multiprocessing (CMP or Multi-core processor): integrates two or more superscalar processors into one chip, each executes threads independently.
 Any combination of IMT/SMT/CMP
Examples of modern SMT CPUs
 The Intel Pentium 4 was the first modern desktop processor to implement simultaneous multithreading, starting from the 3.06GHz model released in 2002, and since introduced into a number of their processors. Intel calls the functionality Hyper-Threading Technology (HTT), and provides a basic two-thread SMT engine. Intel claims up to a 30% speed improvement compared against an otherwise identical, non-SMT Pentium 4.
 The latest MIPS architecture designs include an SMT system known as "MIPS MT".
The IBM POWER5, announced in May 2004, comes as either a dual core DCM, or quad-core or 8-core MCM, with each core including a two-thread SMT engine. IBM's implementation is more sophisticated than the previous ones, because it can assign a different priority to the various threads, is more fine-grained, and the SMT engine can be turned on and off dynamically, to better execute those workloads where an SMT processor would not increase performance. This is IBM's second implementation of generally available hardware multithreading.
 The Intel Atom, released in 2008, is the first Intel product to feature SMT (marketed as Hyper-threading) without supporting instruction reordering, speculative execution, or register renaming.
Related pages
 Thread (computer science)
 Parallel computing
 Instruction-level parallelism
 Multi-core processors

References

LE Shar and ES Davidson, "A Multiminiprocessor System Implemented through Pipelining", Computer Feb 1974
D.M. Tullsen, S.J. Eggers, and H.M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism," In 22nd Annual International Symposium on Computer Architecture, June, 1995
D.M. Tullsen, S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, and R.L. Stamm, "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor," In 23rd Annual International Symposium on Computer Architecture, May, 1996

Other websites
SMT news articles and academic papers 
SMT research at the University of Washington
Timeline of multithreading technologies

Computer science
In computer engineering, out-of-order execution, OoOE, is a technique used in most high-performance microprocessors to make use of cycles that would otherwise be wasted by a certain type of costly delay. Most modern CPU designs include support for out of order execution.

The key concept of OoO processing is to allow the processor to avoid a class of delays (termed: "stalls ") that occur when the data needed to perform an operation are unavailable.
OoO processors fill these "slots" in time with other instructions that are ready, then re-order the results at the end to make it appear that the instructions were processed as normal. The way the instructions are ordered in the original computer code is known as program order, in the processor they are handled in data order (the order in which the data, operands, become available in the processor's registers). Fairly complex circuitry is needed to convert from one ordering to the other and maintain a logical ordering of the output; the processor itself appears to be running the instructions in random order.

The benefit of OoO processing grows as the instruction pipeline expands and the speed difference between main memory (or cache memory) and the processor increases. On modern machines, the processor runs many times faster than the memory, so during the time an in-order processor spends waiting for data to arrive, it could have processed a large number of instructions.
In earlier In-order processors, the processing of instructions is normally done in these steps:
 Instruction fetch.
 If input operands are available (in registers for instance), the instruction is dispatched to the appropriate functional unit.  If one or more operands is unavailable during the current clock cycle (generally because they are being fetched from memory), however, the processor stalls until they are available.
 The instruction is executed by the appropriate functional unit.
 The functional unit writes the results back to the register.