error_t xmc4400EthReceivePacket(NetInterface *interface)
{
   error_t error;
   size_t n;
   NetRxAncillary ancillary;

   //The current buffer is available for reading?
   if((rxCurDmaDesc->rdes0 & ETH_RDES0_OWN) == 0)
   {
      //FS and LS flags should be set
      if((rxCurDmaDesc->rdes0 & ETH_RDES0_FS) != 0 &&
         (rxCurDmaDesc->rdes0 & ETH_RDES0_LS) != 0)
      {
         //Make sure no error occurred
         if((rxCurDmaDesc->rdes0 & ETH_RDES0_ES) == 0)
         {
            //Retrieve the length of the frame
            n = (rxCurDmaDesc->rdes0 & ETH_RDES0_FL) >> 16;
            //Limit the number of data to read
            n = MIN(n, XMC4400_ETH_RX_BUFFER_SIZE);

            //Additional options can be passed to the stack along with the packet
            ancillary = NET_DEFAULT_RX_ANCILLARY;

            //Pass the packet to the upper layer
            nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n,
               &ancillary);

            //Valid packet received
            error = NO_ERROR;
         }
         else
         {
            //The received packet contains an error
            error = ERROR_INVALID_PACKET;
         }
      }
      else
      {
         //The packet is not valid
         error = ERROR_INVALID_PACKET;
      }

      //Give the ownership of the descriptor back to the DMA
      rxCurDmaDesc->rdes0 = ETH_RDES0_OWN;
      //Point to the next descriptor in the list
      rxCurDmaDesc = (Xmc4400RxDmaDesc *) rxCurDmaDesc->rdes3;
   }
   else
   {
      //No more data in the receive buffer
      error = ERROR_BUFFER_EMPTY;
   }

   //Clear RU flag to resume processing
   ETH0->STATUS = ETH_STATUS_RU_Msk;
   //Instruct the DMA to poll the receive descriptor list
   ETH0->RECEIVE_POLL_DEMAND = 0;

   //Return status code
   return error;
}
error_t xmc4400EthReceivePacket(NetInterface *interface)
{
   error_t error;
   size_t n;
   NetRxAncillary ancillary;

    
   if((rxCurDmaDesc->rdes0 & ETH_RDES0_OWN) == 0)
   {
       
      if((rxCurDmaDesc->rdes0 & ETH_RDES0_FS) != 0 &&
         (rxCurDmaDesc->rdes0 & ETH_RDES0_LS) != 0)
      {
          
         if((rxCurDmaDesc->rdes0 & ETH_RDES0_ES) == 0)
         {
             
            n = (rxCurDmaDesc->rdes0 & ETH_RDES0_FL) >> 16;
             
            n = MIN(n, XMC4400_ETH_RX_BUFFER_SIZE);

             
            ancillary = NET_DEFAULT_RX_ANCILLARY;

             
            nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n,
               &ancillary);

             
            error = NO_ERROR;
         }
         else
         {
             
            error = ERROR_INVALID_PACKET;
         }
      }
      else
      {
          
         error = ERROR_INVALID_PACKET;
      }

       
      rxCurDmaDesc->rdes0 = ETH_RDES0_OWN;
       
      rxCurDmaDesc = (Xmc4400RxDmaDesc *) rxCurDmaDesc->rdes3;
   }
   else
   {
       
      error = ERROR_BUFFER_EMPTY;
   }

    
   ETH0->STATUS = ETH_STATUS_RU_Msk;
    
   ETH0->RECEIVE_POLL_DEMAND = 0;

    
   return error;
}