pci_emul_msix_tread(struct pci_vdev *dev, uint64_t offset, int size)
{
	char *dest;
	int msix_entry_offset;
	int tab_index;
	uint64_t retval = ~0;

	/*
	 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
	 * table but we also allow 1 byte access to accommodate reads from
	 * ddb.
	 */
	if (size != 1 && size != 4 && size != 8)
		return retval;

	msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;

	/* support only aligned reads */
	if ((msix_entry_offset % size) != 0)
		return retval;

	tab_index = offset / MSIX_TABLE_ENTRY_SIZE;

	if (tab_index < dev->msix.table_count) {
		/* valid MSI-X Table access */
		dest = (char *)(dev->msix.table + tab_index);
		dest += msix_entry_offset;

		if (size == 1)
			retval = *((uint8_t *)dest);
		else if (size == 4)
			retval = *((uint32_t *)dest);
		else
			retval = *((uint64_t *)dest);
	} else if (pci_valid_pba_offset(dev, offset)) {
		/* return 0 for PBA access */
		retval = 0;
	}

	return retval;
}
pci_emul_msix_tread(struct pci_vdev *dev, uint64_t offset, int size)
{
	char *dest;
	int msix_entry_offset;
	int tab_index;
	uint64_t retval = ~0;

	 
	if (size != 1 && size != 4 && size != 8)
		return retval;

	msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;

	 
	if ((msix_entry_offset % size) != 0)
		return retval;

	tab_index = offset / MSIX_TABLE_ENTRY_SIZE;

	if (tab_index < dev->msix.table_count) {
		 
		dest = (char *)(dev->msix.table + tab_index);
		dest += msix_entry_offset;

		if (size == 1)
			retval = *((uint8_t *)dest);
		else if (size == 4)
			retval = *((uint32_t *)dest);
		else
			retval = *((uint64_t *)dest);
	} else if (pci_valid_pba_offset(dev, offset)) {
		 
		retval = 0;
	}

	return retval;
}