Source document: https://docs-lawep.s3.us-east-2.amazonaws.com/1697801239390.pdf (Liberia)
FEATURES ■ Secondary-Side Control for Fast Transient Response ■ Self-Starting Architecture Eliminates Need for Separate Bias Regulator ■ Proprietary Gate Drive Encoding Scheme Reduces System Complexity ■ Current Mode Control Ensures Current Sharing ■ PLL Fixed Frequency: 100kHz to 500kHz ■ ±1% Output Voltage Accuracy ■ OPTI-LOOP Compensation ■ Available in a Narrow 16-Lead SSOP Package APPLICATIO SU ■ Isolated 48V Telecommunication Systems ■ Internet Servers and Routers ■ Distributed Power Step-Down Converters ■ Automotive and Heavy Equipment LTC3726 Secondary-Side Synchronous Forward Controller DESCRIPTIOU The LTC®3726 is a secondary-side controller for synchro- nous forward converters.
When used in conjunction with the LTC3705/LTC3725 gate driver and primary-side con- trollers, the part creates a complete isolated power supply that combines the simplicity of OPTI-LOOP® compensa- tion with the speed of secondary-side control.

The LTC3726 has been designed to simplify the design of highly efficient, secondary-side forward converters.
Work- ing in concert with the LTC3705 or LTC 3725, the LTC3726 forms a robust, self-starting converter that eliminates the need for the separate bias regulator that is commonly used in secondary-side control applications.

In addition, a pro- prietary scheme is used to multiplex gate drive signals and DC bias power across the isolation barrier through a single, tiny pulse transformer.

The LTC3726 is available in a 16-lead SSOP package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a registered trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S.

Patents, including 6144194.

Other patents pending.
TYPICAL APPLICATIOU 36V-72V to 3.3V/20A Isolated Forward Converter + VIN – VIN 1µF 100V x3 Si7852DP MURS120 Si7852DP T1 • • Si7336ADP MURS120 2mΩ 2W 30mΩ 1W L1: COILCRAFT SER2010-122 T1: PULSE PA0807 T2: PULSE PA0297 1µF T2 • • 162k 33nF FQT7N10 100k BAS21 0.22µF 365k 1% 15k 1% 2.2µF 25V 33nF NDRV UVLO VCC SS/FLT BOOST TG TS BG IS FB/IN+ LTC3705 FS/IN– GND PGND VSLMT L1 1.2µH 1.2Ω CMPSH1-4 Si7336ADP ×2 10µF 25V 5k FZT690B 7.5V 2.2µF + VOUT 330µF 6.3V ×3 – VOUT – + IS IS PT+ FG SW SG VCC LTC3726 FS/SYNC FB/PHASE ITH PT– RUN/SS GND PGND SLP MODE 102k 1% 22.6k 1% 3726 TA01 680pF 20k 3726fb 1 LTC3726 U W W W ABSOLUTE MAXIMUM RATINGS (Note 1) VCC ........................................................... – 0.3V to 10V SW ............................................................... –5V to 50V ITH, RUN/SS ............................................... – 0.3V to 7V All Other Pins ............................................ – 0.3V to 10V Operating Ambient Temperature Range (Note 2) LTC3726EGN ...................................... – 40°C to 85°C LTC3726IGN ....................................... – 40°C to 85°C Operating Junction Temperature (Note 3) ........... 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U PACKAGE/ORDER INFORMATION W U SG FG MODE FB/PHASE ITH RUN/SS SLP GND TOP VIEW 16 15 14 13 12 11 10 VCC PT+ PT– PGND SW IS+ IS– 9 FS/SYNC GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 130°C/W ORDER PART NUMBER LTC3726EGN LTC3726IGN Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at TA = 25°C.

VCC = 7V, GND = PGND = 0V, unless otherwise noted.
SYMBOL The ● indicates specifications which apply over the full operating CONDITIONS PARAMETER MIN TYP Regulated Feedback Voltage (Note 4) ITH = 1.2V ● 0.594 Main Control Loop VFB ∆VFB(LINREG) ∆VFB(LOADREG) VISMAX VISOC Feedback Voltage Line Regulation Feedback Voltage Load Regulation Maximum Current Sense Threshold Over-Current Shutdown Threshold VCC = 5V to 10V, ITH = 1.2V Measured in Servo Loop, ITH = 0.5V to 2V RSENSE Mode, VIS = 0V CT Mode, VIS = 0V RSENSE Mode, VIS = 0V CT Mode, VIS = 0V 0.600 0.001 –0.01 78 1.28 100 1.65 2.75 –5 3 0.45 200 1.5 1.5 1.5 1.5 17 ● 68 1.15 87 1.45 2.40 –4 ● 0.4 15 MAX UNITS 0.606 –0.1 88 1.4 113 1.85 3.10 –6 0.5 2.3 2.3 2.3 2.3 19 V %/V % mV V mV V mS µA µA V ns Ω Ω Ω Ω % 3726fb RUN/SS Pin ON Threshold Soft-Start Discharge Current Transconductance Amplifier gm Soft-Start Charge Current gm IRUN/SS(C) IRUN/SS(D) VRUN/SS tON,MIN FG, SG RUP FG, SG RDOWN PT+, PT– RUP PR+, PT– RDOWN PT+, PT– Driver Pull-Down Resistance ∆VFB(OV) FG, SG Driver Pull-Down On Resistance PT+, PT– Driver Pull-Up Resistance FG, SG Driver Pull-Up On Resistance Output Overvoltage Threshold Minimum ON Time VRUN/SS = 2V VRUN/SS Rising FG, SG Low FG, SG High PT+, PT– Low PT+, PT– High VFB Rising 2 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at TA = 25°C.
VCC = 7V, GND = PGND = 0V, unless otherwise noted.
SYMBOL The ● indicates specifications which apply over the full operating CONDITIONS PARAMETER MIN TYP VCC Supply VCCOP ICC Operating Voltage Range Supply Current Operating Shutdown UV Lockout VUVLO VHYS Oscillator and Phase-Locked Loop UV Hysteresis IFS fLOW fHIGH ∆f (RFS) fPLL(MAX) fPLL(MIN) FS/SYNC Pin Sourcing Current Oscillator Low Frequency Set Point Oscillator High Frequency Set Point Oscillator Resistor Set Accuracy Maximum PLL Sync Frequency Minimum PLL Sync Frequency fOSC = 200kHz (Note 5) VRUN/SS = GND VCC Rising VFS/SYNC = GND VFS/SYNC = VCC 75kΩ < RFS/SYNC < 175kΩ 5 ● 4.52 170 255 –20 4.2 700 4.60 0.4 20 200 300 500 75 LTC3726 MAX UNITS 10 4.70 230 345 20 V mA µA V V µA kHz kHz % kHz kHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: The LTC3726E is guaranteed to meet the performance specifications from 0°C to 85°C junction temperature.

Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls.

The LTC3726I is guaranteed and tested over the full – 40°C to 85°C operating temperature range.
Note 3: Operating junction temperature TJ (in °C) is calculated from the ambient temperature TA and the average power dissipation PD (in Watts) by the formula: TJ = TA + θJA • PD Refer to the Applications Information section for details.

Note 4: The LTC3726 is tested in a feedback loop that servos VFB to a voltage near the internal 0.6V reference voltage to obtain the specified ITH voltage (VITH = 1.2V).

Note 5: Operating supply current is measured in test mode.
Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency.

See Typical Performance Characteristics.

3726fb 3 LTC3726 TYPICAL PERFOR A CE CHARACTERISTICS UW TA = 25°C, unless otherwise noted.
VCC Supply Current vs Input Voltage Maximum Current Sense Threshold vs Duty Cycle Maximum Current Sense Threshold vs ITH Voltage 7 6 5 4 ) A m ( T N E R R U C Y L P P U S 3 5 fOSC = 200kHz ALL GATES: CLOAD = 0 INPUT VOLTAGE (V) 100 ) % ( , X A M S I V / S I V 80 60 40 20 0 0 100 RSLP = 0 RSLP = 50k 100kΩ ) % ( , X A M S V / S V I I 80 60 40 20 20 40 60 80 DUTY CYCLE (%) 0 0 0.5 1.0 1.5 2.0 ITH VOLTAGE (V) 2.5 3.0 3726 G01 3726 G03 3726 G04 IS Pins Source Current IS Pins Source Current vs Temperature Maximum Current Sense Threshold vs Temperature CT-MODE: IIS+ RS-MODE: (IIS+ + IIS–) ) A µ ( T N E R R U C E C R U O S N I P S I 265 260 255 250 245 240 235 230 RS-MODE: (IIS+ + IIS–) VIS+ = VIS– = 0V ) % ( , X A M S I V / S I V 101.5 101.0 100.5 100.0 99.5 99.0 –1 0 –50 –25 IS+, IS– COMMON-MODE VOLTAGE (V) 25 0 75 TEMPERATURE (°C) 50 100 125 –50 –25 25 0 75 TEMPERATURE (°C) 50 3726 G05 3726 G06 RUN/SS ON Threshold vs Temperature Oscillator Frequency vs Temperature Oscillator Frequency vs RFS 100 125 3726 G07 ) % ( –1 –2 R = 175KΩ fOSC = 500kHz R = 75KΩ fOSC = 100kHz 100 125 –50 –25 3726 G08 25 0 75 TEMPERATURE (°C) 50 600 500 400 300 200 100 ) z H k ( Y C N E U Q E R F 100 125 3726 G14 0 50 75 100 150 175 200 125 RFS (kΩ) 3726 G09 3726fb ) A µ ( T N E R R U C E C R U O S N I P S I 400 300 200 100 0 –100 –200 –300 –400 ) V m ( S S / N U R V 470 460 450 440 430 420 25 0 75 TEMPERATURE (°C) 50 –50 –25 4 TYPICAL PERFOR A CE CHARACTERISTICS UW FB Voltage vs Temperature FB Voltage Line Regulation 601.0 600.5 ) V m ( B F V 600.0 599.5 599.0 –50 –25 25 0 75 TEMPERATURE (°C) 50 601.0 600.5 ) V m ( B F V 600.0 599.5 599.0 100 125 0 5 LTC3726 Undervoltage Lockout vs Temperature VCC RISING ) V ( E G A T L O V D L O H S E R H T O L V U 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 10 15 VIN SUPPLY VOLTAGE (V) 20 25 30 –50 –25 25 0 75 TEMPERATURE (°C) 50 3726 G15 3726 G11 Gate Driver On-Resistance vs VCC Gate Driver On-Resistance vs Temperature 1.8
 1.7 1.6 1.5 1.4 1.3 1.2 5 VCC = 7V 2.50 2.25 2.00 ) Ω ( N O S D R , 1.75 1.50 1.25 1.00 PULL-DOWN PULL-UP –50 –25 VCC VOLTAGE (V) 3726 G12 25 0 75 TEMPERATURE (°C) 50 100 125 3726 G13 ) Ω ( N O S D R , Efficiency (Figure 5) Load Step (Figure 5) 95 ) % ( Y C N E I C I F F E 90 85 80 0 VIN = 36V VIN = 72V VOUT 100mV/DIV IOUT 10A/DIV LOAD CURRENT (A) 3726 G17 20µs/DIV 3726 G18 VIN = 48V VOUT = 3.3V LOAD STEP = 0A TO 20A 100 125 3726 G16 3726fb 5 LTC3726 UUPI FU CTIO S U SG (Pin 1): Gate Drive for the “Synchronous” MOSFET.
FG (Pin 2): Gate Drive for the “Forward” MOSFET.

MODE (Pin 3): Tie to either GND or VCC to set the maximum duty cycle at either 50% or 75% respectively.

Tie to ground through either a 200k or 100k resistor (50% or 75% maximum duty cycle) to disable pulse encoding.

In this mode, normal PWM signals will be generated at the PT+ pin, while a clock signal is generated at the PT– pin.

FB/PHASE (Pin 4): Inverting input of the main loop Error Amplifier and Control Input to the Phase Selector.
In PolyPhase® Slave applications (where voltage feedback is not needed) this pin is used to determine the phasing of the controller CLK relative to the synchronizing signal at the FS/SYNC pin.

ITH (Pin 5): The Output of the Main Loop Error Amplifier.

Place compensation components between the ITH pin and GND.

RUN/SS (Pin 6): Combination Run Control and Soft-Start Inputs.

A capacitor to ground sets the ramp time of the output voltage.
Holding this pin below 0.4V causes the IC to shut down all internal circuitry.

SLP (Pin 7): Slope Compensation Input.

Place a single resistor to ground to set the desired amount of slope compensation.

GND (Pin 8): Signal Ground.

PolyPhase is a registered trademark of Linear Technology Corporation.

FS/SYNC (Pin 9): Combination Frequency Set and SYNC pin.

Tie to GND or VCC to run at 200kHz and 300kHz respec-tively.
Place a single resistor to ground at this pin to set the frequency between 75kHz and 500kHz.

To synchronize, drive this pin with a clock signal to achieve PLL synchronization from 75kHz to 500kHz.

Sources 20µA of current.

– (Pin 10): Negative Input to the Current Sense Circuit.

IS When using current sense transformers, this pin may be tied to VCC for single-ended sensing with a 1.28V maxi- mum current trip level.

+ (Pin 11): Positive Input to the Current Sense Circuit.
IS Connect to the positive end of a current sense resistor or to the output of a current sense transformer.

SW (Pin 12): Connect to the drain of the “synchronous” MOSFET.

This input is used for adaptive shoot-through prevention and leading edge blanking.

PGND (Pin 13): Gate Driver Ground Pin.

PT–, PT+ (Pins 14, 15): Pulse Transformer Driver Out- puts.

For most applications, these connect to a pulse transformer (with a series DC blocking capacitor).
The PWM information is multiplexed together with DC power and sent through a single pulse transformer to the primary side.

This information may be decoded by the LTC3705 gate driver and primary-side controller.

VCC (Pin 16): Main VCC Input for all Driver and Control Circuitry.
6 3726fb BLOCK DIAGRA W LTC3726 2× 32× C + – 2V + – + – EA gm = 2.8mS RUN/SS + IS 11 – IS 10 ITH 5 0.60V FB/PHASE 4 SLP 7 FS/SYNC 9 MODE 3 DRIVE/DMAX CONTROL + – C ITRP WAIT OVP RESET DOMINANT R S Q 0.25V + – C SKIP DMAX BLANK + – C 3.2V OC OVERCURRENT 2.5V SLOPE COMP 1 BLANK DMAX OSC AND PLL PWM WAIT OVP ZERO CROSSING DETECT DRIVER ENCODING AND LOGIC DRIVE TYPE 4VSB UVLO VCCUV REG 4VSB VREF 1.24V RUN/SS 6 FB VCCUV SOFT- START WAIT GND 8 OC VCC VCC VCC VCC FG 2 PGND 13 SG 1 0.2V SW 12 + – PGND PT+ 15 PT – 14 VCC 19 3726 BD • • PULSE XFMR 3726fb 7 LTC3726 OPERATIOU Main Control Loop The LTC3726 is designed to work in a constant frequency, current mode, one or two transistor forward converter.
During normal operation, the primary-side MOSFET(s) is (are) “clocked” on with the forward MOSFET on the sec- ondary side.

This applies the reflected input voltage across the inductor on the secondary side.

When the current in the inductor has ramped up to the peak value as com- manded by the voltage on the ITH pin, the current sense comparator is tripped, turning off the primary-side and forward MOSFETs.
To avoid turning on the synchronous MOSFET prematurely and causing shoot-through, the voltage on the SW pin is monitored.

This voltage will usually fall below 0V soon after the primary-side MOSFETs have turned completely off.

When this condition is de- tected, the synchronous MOSFET is quickly turned on, causing the inductor current to ramp back downwards.
The error amplifier senses the output voltage, and adjusts the ITH voltage to obtain the peak current needed to maintain the desired main-loop output voltage.

The LTC3726 always operates in a continuous current, syn- chronous switching mode.

This ensures a rapid transient response as well as a stable bias supply voltage at light loads.

A maximum duty cycle (either 50% or 75%) is internally set via clock dividers to prevent saturation of the main transformer.
In the event of an overvoltage on the output, the synchronous MOSFET is quickly turned on to help protect critical loads from damage.

For most forward converter applications, the PT+ and PT– outputs will contain a pulse-encoded PWM signal.

These outputs are driven in a complementary fashion with an essentially constant 50% duty cycle.

This results in a stable volt-second balance as well as an efficient transfer of bias power across the pulse transformer.
As shown in Figure 1, the beginning of the positive half-cycle coincides with the turn-on of the primary-side MOSFET(s).

Likewise, the beginning of the negative half-cycle coincides with the maximum duty cycle (forced turn-off of primary switch(es)).

At the appropriate time during the positive half-cycle, the end of the “on” time (PWM going LOW) is signaled by briefly applying a zero volt differential across the pulse transformer.

Figure 1 illustrates the operation of this multiplexing scheme.
The LTC3705 primary-side controller and gate driver will decode this PWM information as well as extract the power needed for primary-side gate drive.
DUTY CYCLE = 15% DUTY CYCLE = 0% 150ns 150ns 7V VPT1+ – VPT1– –7V 7V –7V 3726 F01 1 CLK PER 1 CLK PER Figure 1: Gate Drive Encoding Scheme (VMODE = GND) Gate Drive Encoding Self-Starting Architecture Since the LTC3726 controller resides on the secondary side of an isolation barrier, communication to the primary- side power MOSFETs is generally done through a trans- former.

Moreover, it is often necessary to generate a low voltage bias supply for the primary-side gate drive cir- cuitry.
In order to reduce the number of isolated windings present in the system, the LTC3726 uses a proprietary scheme to encode the PWM gate drive information and multiplex it together with bias power for the primary-side drive and control, using a single pulse transformer.

Note that, unlike optoisolators and other modulation tech- niques, this multiplexing scheme does not introduce a significant time delay into the system.
When the LTC3726 is used in conjunction with the LTC3705/ LTC3725 primary-side controller and gate driver, a com- plete self-starting isolated supply is formed.

When input voltage is first applied in such an application, the LTC3705/ LTC3725 will begin switching in an “open-loop” fashion, causing the main output to slowly ramp upwards.

This is the primary-side soft-start mode.

On the secondary side, the LTC3726 derives its operating bias voltage from a peak-charged capacitor.
This peak-charged voltage will rise more rapidly than the main output of the converter, so that the LTC3726 will become operational well before the output voltage has reached its final value.

3726fb 8 OPERATIOU When the LTC3726 has adequate operating voltage, it will begin the procedure of assuming control from the primary side.

To do this, it first measures the voltage on the power supply’s main output and then automatically advances its own soft-start voltage to correspond to the main output voltage.
This ensures that the output voltage increases monotonically as the soft-start control is transferred from primary to secondary.

The LTC3726 then begins sending PWM signals to the LTC3705/LTC3725 on the primary side through a pulse transformer.

When the LTC3705/ LTC3725 has detected a stable signal from the secondary controller, it transfers control of the primary switches over to the LTC3726, beginning the secondary-side soft-start mode.
The LTC3726 continues in this mode until the output voltage has ramped up to its final value.

If for any reason, the LTC3726 either stops sending (or initially fails to send) PWM information to the LTC3705/LTC3725, the LTC3705/LTC3725 will detect a FAULT and initiate a soft- start retry (see the LTC3705/LTC3725 data sheet).

Slope Compensation Slope compensation is added at the input of the PWM comparator to improve stability and noise margin of the peak current control loop.
The amount of slope compen- sation can be selected from one of five preprogrammed values using the SLP pin as shown in Table 1.

Note that the amount of slope compensation doubles when the duty cycle exceeds 50%.
Table 1 SLP PIN GND SLOPE (D < 0.5) SLOPE (D > 0.5) 0.05 • ISMAX • fOSC None 0.1 • ISMAX • fOSC None VCC 0.2 • ISMAX • fOSC 0.1 • ISMAX • fOSC 400kΩ to GND 0.3 • ISMAX • fOSC 0.15 • ISMAX • fOSC 200kΩ to GND 0.5 • ISMAX • fOSC 0.25 • ISMAX • fOSC 100kΩ to GND 50kΩ to GND 1.0 • ISMAX • fOSC 0.5 • ISMAX • fOSC In Table 1 above, ISMAX is the maximum current limit, and fOSC is the switching frequency.

LTC3726 the inductor (either high side or ground lead sensing), or in the source of the “forward” switch.
If a current sense – input should be tied to VCC and transformer is used, the IS + pin to the output of the current sense transformer.

the IS This causes the gain of the internal current sense amplifier to be reduced by a factor of 16, so that the maximum current sense voltage (current limit) is increased from 78mV to 1.28V.

An internal, adaptive leading edge blank- ing circuit ensures clean operation for “switch” current sensing applications.
Current limit is achieved in the LTC3726 by limiting the maximum voltage excursion of the error signal (ITH volt- age).

Note that if slope compensation is used, the precise value at which current limit occurs will be a function of duty cycle (see Typical Performance Characteristics).

If a short circuit is applied, an independent overcurrent com- parator may be tripped.

In this case, the LTC3726 will enter a “hiccup” mode using the soft-start circuitry.
Frequency Setting and Synchronization The LTC3726 uses a single pin to set the operating frequency, or to synchronize the internal oscillator to a reference clock with an on-chip phase-locked loop (PLL).

The FS pin may be tied to GND, VCC or have a single resistor to GND to set the switching frequency.

If a clock signal (>2V) is detected at the FS pin, the LTC3726 will automati- cally synchronize to the rising edge of the reference clock.

Table 2 summarizes the operation of the FS pin.


For synchronization between multiple LTC3726s, the PT+ pin of one LTC3726 can be used as a master clock reference and tied to the FS pin of the other LTC3726s.

Table 2 FS PIN GND VCC RFS to GND Reference Clock SWITCHING FREQUENCY 200kHz 300kHz fOSC (Hz) = 4RFS – 200k fOSC = fREF (75kHz to 500kHz) Current Sensing and Current Limit For current sensing, the LTC3726 supports either a cur- rent sense resistor or a current sense transformer.
The current sense resistor may either be placed in series with This will cause all LTC3726s to operate at the same frequency and phase.

The LTC3726 can also be used as a “Slave” in a PolyPhase application.

In this case, the phase angle of each LTC3726 can be set by using the FB/PHASE 3726fb 9 LTC3726 OPERATIOU pin (see Slave Mode Operation).

The Phase angle cannot be adjusted when the FB/PHASE pin is being used for voltage loop regulation.
Soft-Start The soft-start circuitry has four functions: 1) to provide a shutdown, 2) to provide a smooth ramp on the output voltage during start-up, 3) to limit the output current in a short-circuit situation by entering a hiccup mode, and 4) to communicate fault and shutdown information between multiple LTC3726s in a PolyPhase application.

When the RUN/SS pin is pulled to GND, the chip is placed into shutdown mode.

If this pin is released, the RUN/SS pin is initially charged with a 50µA current source.
After the RUN/SS pin gets above 0.5V, the chip is enabled.

At the instant that the LTC3726 is first enabled, the RUN/SS voltage is rapidly preset to a voltage that will correspond to the main output voltage of the DC/DC converter.

(See the Self-Starting Architecture section.)

After this preset interval has completed, the normal soft-start interval begins and the charging current is reduced to 5µA.
The external soft-start voltage is used to internally ramp up the 0.6V reference (positive) input to the error amplifier.

When fully charged, the RUN/SS voltage remains at 3V.

In the event that the sensed switch or inductor current exceeds the overcurrent trip threshold, an internal fault latch is tripped.

When such a fault is detected, the LTC3726 immediately goes to zero duty cycle and initiates a soft- start retry.
Prior to discharging the soft-start capacitor, however, the LTC3726 first puts a voltage pulse on the RUN/SS pin, which trips the fault latch in any other LTC3726 that shares the RUN/SS.

This ensures an orderly shutdown of all phases in a PolyPhase application.

After the soft-start capacitor is fully discharged, the LTC3726 attempts a restart.

If the fault is persistent, the system enters a “hiccup” mode.
Note that in self-starting secondary-side control applica- tions (with the LTC3705 or LTC3725), the presence of the LT3726 bias voltage is dependent upon the regular switch- ing of the primary-side MOSFETs.

Therefore, depending on the details of the application circuit, the LTC3726 may 10 lose its bias voltage after a fault has been detected and before completing a soft-start retry.
In this case, the “hiccup-mode” operation is actually governed by the LTC3705/LTC3725 soft-start circuitry (see the LTC3705/ LTC3725 data sheets).

Drive Mode and Maximum Duty Cycle Although the LTC3726 is primarily intended to be used with the LTC3705/LTC3725 in forward converter applica- tions, the MODE pin provides the flexibility to use the LTC3726 in a wide variety of additional applications.
This pin can be used to defeat the gate drive encoding scheme, as well as change the maximum duty cycle from its default value of 50%.

The use of the MODE pin is summarized in Table 3.

When the gate drive encoding scheme is defeated, a standard PWM-style signal will be present at the PT+ pin and a reference clock (in phase with the PWM signal) will be present at the PT– pin.
These outputs can be used in “standalone” applications (without the LTC3705/LTC3725) to drive the gates of MOSFETs in a conventional manner.
Table 3 MODE PIN GND VCC 200kΩ to GND 100kΩ to GND PT+/PT– Mode (MAX DUTY CYCLE) Encoded PWM (DMAX = 50%) Encoded PWM (DMAX = 75%) Standard PWM (DMAX = 50%) Standard PWM (DMAX = 75%) INTENDED APPLICATION 2-Switch Forward with LTC3705 1-Switch Forward with LTC3725 2-Switch Forward Standalone 1-Switch Forward Standalone Overvoltage Protection This circuit monitors the voltage on the FB input.

If the voltage on the FB pin exceeds 117% of 0.6V (0.7V), an overvoltage (OVP) is detected.
For overvoltage protection, the secondary-side synchronous MOSFET is turned on while all other MOSFETs are turned off.

This protection mode is not latched, so that the overvoltage detection is cleared if the FB voltage falls below 115% of 0.6V (0.69V).
3726fb OPERATIOU Slave Mode Operation When two or more LTC3726 devices are used in PolyPhase systems, one device becomes the “Master” controller, while the others are used as “Slaves.” Slave mode is activated when the FB/PHASE pin is greater than approxi- mately 2V.

In this mode, the ITH pin becomes a high- impedance input, allowing it to be driven by the Master controller.

In this way, equal inductor currents are estab- lished in each of the individual phases.
Also, in slave mode, the soft-start charge/discharge currents are dis- abled, allowing the Master device to control the charging and discharging of the soft-start capacitor.

In slave mode, the phase angle of each LTC3726 can be set by using the FB/PHASE pin.

This pin can be tied to VCC, or LTC3726 have a single resistor to VCC to activate Slave mode and set the phase angle (delay) of the internal oscillator relative to the incoming sync signal on the FS/SYNC pin.
Any one of six preset values can be selected as summarized in Table 4.

Table 4 FB/PHASE PIN VFB/PHASE < 2V VFB/PHASE = VCC 200kΩ to VCC 100kΩ to VCC 50kΩ to VCC PHASE DELAY OPERATING MODE 0° 180° 60° 90° 120° Master Slave Slave Slave Slave APPLICATIO S I FOR ATIOW Start-Up Considerations U U U In self-starting applications, the LTC3705/LTC3725 will initially begin the soft-start of the converter in an open- loop fashion.
After bias is obtained on the secondary side, the LTC3726 assumes control and completes the soft- start interval.

In order to ensure that control is properly transferred from the LTC3705/LTC3725 (primary-side) to the LTC3726 (secondary-side), it is necessary to limit the rate of rise on the primary-side soft-start ramp so that the LTC3726 has adequate time to wake up and assume control before the output voltage gets too high.
This condition is satisfied for many applications if the following relationship is maintained: CSS,SEC ≤ CSS PRI However, care should be taken to ensure that soft-start transfer from primary-side to secondary-side is com- pleted well before the output voltage reaches its target value.

A good design goal is to have the transfer completed when the output voltage is less than one-half of its target value.
Note that the fastest output voltage rise time during primary-side soft-start mode occurs with maximum input voltage and minimum load current.

The open-loop start-up frequency on the LTC3705/LTC3725 is set by placing a resistor from the FB/IN + pin to GND.

Although the exact start-up frequency on the primary side is not critical, it is generally good practice to set this approximately equal to the operating frequency on the secondary side.
The FS/IN– start-up resistor for the LTC3705/LTC3725 may be selected using the following: f PRI ( Hz ) = 10 3 2 10 .

• –/ + FS IN R 10 k In the event that the secondary-side circuitry fails to properly start up and assume control of switching, there are several fail-safe mechanisms to help avoid overvoltage conditions.

First, the LTC3705/LTC3725 contains a volt- second clamp that will keep the primary-side duty cycle at a level that cannot produce an overvoltage condition.
Second, the LTC3705/LTC3725 contains a time-out fea- ture that will detect a FAULT if the LTC3726 fails to start up and deliver PWM signals to the primary side.

Finally, the LTC3726 has an independent overvoltage detection circuit that will crowbar the output of the DC/DC converter using the synchronous MOSFET switch.

In the event that a short circuit is applied to the output of the DC/DC converter prior to start-up, the LTC3726 will generally not receive enough bias voltage to operate.
In this case, the LTC3705/LTC3725 will detect a FAULT for 3726fb 11 LTC3726 U U U APPLICATIO S I FOR ATIOW one of two reasons: 1) the start-up time-out feature will be activated since the LTC3726 never sends signals to the primary side or 2) the primary-side overcurrent circuit will be tripped because of current buildup in the output induc- tor.

In either case, the LTC3705/LTC3725 will initiate a shutdown followed by a soft-start retry.

See the LTC3705/ LTC3725 data sheets for further details.
Bias Supply Generation Figure 2 shows a commonly used method of developing a VCC bias supply for the LTC3726.

During start-up, the circuit of Figure 2 uses a peak detector followed by a simple linear regulator to rapidly develop a VCC voltage for the LTC3726.

Note that this bias voltage must rise faster than the open-loop soft-start that is initiated by the LTC3705/LTC3725.
This ensures that the LTC3726 be- gins switching and assumes control of the soft-start before the output voltage has risen substantially.

The value of R1 should be chosen to keep the peak charging current below the maximum (non-repetitive peak) rating of diode D1, but should otherwise be as small as CMPSH1-4 R1 1.2Ω D1 • • 1 BIAS WINDING NB C1 10µF 25V MAIN TRANSFORMER R2 5K D2 7.5V Q1 FZT690B C2 1µF 16V PEAK CHARGER REGULATOR LTC3726 VCC 3726 F02 Figure 2.
Typical Bias Supply Configuration possible to provide a rapid charging of capacitor C1.

This capacitor serves as a reservoir to provide bias voltage as the LTC3726 begins switching and assumes control of the soft-start from the LTC3705/LTC3725.

Care should be taken to ensure that capacitor C1 is adequately large to provide enough hold-up time for the LTC3726 to assume control and establish a firm bias voltage at the main transformer.
12 The linear regulator of Figure 2 should be designed to handle the total expected ICC current.

For self-starting applications with the LTC3705/LTC3725, this regulator will supply the operating bias current for both primary and secondary side control circuitry.
This current may be approximated using the following: I CC 2 + I Q = ( M f I + CORE 3726 , + M f Q S OSC G SEC , , + Q P OSC G PRI C 20 I Q 3 , V f SNUB CC OSC 7705 + ) where IQ,3705 and IQ,3726 are the operating supply currents of the LTC3705/LTC3725 and LTC3706, MP and MS are the number of power MOSFETs used on the primary and secondary sides, QG,PRI and QG,SEC are the total gate charge of the primary and secondary MOSFETs, ICORE is the core loss current associated with the pulse trans- former, and CSNUB is the snubber capacitor across the pulse transformer.
Note that the current used by the primary side circuitry is doubled by the 2:1 turns ratio of the pulse transformer.

For the Typical Application circuit of Figure 5, the total ICC delivered by the linear regulator is 5mA + 3(50nC)(200kHz) + 2(2(38nC)(200kHz) + 2mA) + 3mA + 13mA = 85mA.
To accommodate this current, Q1 should have a high Beta (>300), and R2 should be chosen to supply adequate base current at low VIN (e.g., at 36V on the converter input), while maintaining a reasonable power dissipation in D2 at high VIN (72V).

The turns ratio (NB) of the bias winding should be chosen to ensure that there is adequate voltage to operate the LTC3726 over the entire range for the DC/DC converter’s input bus voltage (VBUS).

This may be calculated using N B = V ( CC MIN ) + .
1 2 V + V ( BUS MIN ) CC R I 2 ⋅ β Q 1 VCC(MIN) can be as low as 5V (if this provides adequate gate drive voltage to maintain acceptable efficiency), or as high as 7V.

For the Figure 2 circuit if VCC(MIN) = 6V, ICC = 85mA, and VBUS = 36V-72V, this would mean a turns ratio NB = 0.24, or a 9:2 transformer.
Generally, if the output voltage of the DC/DC converter is 3.3V or higher, then the main output of the power transformer (tied to SW node on 3726fb U U APPLICATIO S I FOR ATIOW the LTC3726) can be used as the input to the peak charge circuit of Figure 2.

For lower output voltages, however, it is normally necessary to use a dedicated bias winding to generate adequate bias voltage for the LTC3726.

U Current Sensing The LTC3726 provides considerable flexibility in cur- rent sensing techniques.
It supports two main meth- ods: 1) resistive current sensing and 2) current trans- former current sensing.

Resistive current sensing is generally simpler, smaller and less expensive, while current transformer sensing is more efficient and gen- erally appropriate for higher (> 20A) output currents.

For resistive current sensing, the sense resistor may be placed in any one of three different locations: high side inductor, low side inductor or low side switch, as shown in Figure 3.
Sensing the inductor current (high LTC3726 side or low side) is generally less noisy but dissipates more power than sensing the switch current (Figures 3a and 3b).

High side inductor current sensing pro- vides a more convenient layout than low side (no split ground plane), but can only be used for output volt- ages up to 5.5V, due to the common mode limitations –).

For most of the current sense inputs (IS applications, low side switch current sensing will be a good solution (Figure 3c).
+ and IS For high current applications where efficiency (power dissipation) is very important, a current sense trans- – pin former may be used.

As shown in Figure 3d, the IS should be tied off to VCC when a current sense transformer + pin to become a single ended is used.

This causes the IS (nondifferential) current sense input with a maximum current sense voltage of 1.28V.

Figure 3d shows a typical application circuit using a current transformer.
• • IS LTC3726 IS + – 78mV MAX • • IS LTC3726 IS + – 78mV MAX 3726 F03a 3726 F03b Figure 3a.

High Side Inductor: Easier Layout, Low Noise, Accurate Figure 3b.

Low Side Inductor: Accurate, Low Noise, High VOUT Capable • • IS LTC3726 IS + – 78mV MAX • • • 5Ω TO 50Ω • 1.28V MAX TRIP + IS LTC3726 – VCC IS Figure 3c.

Switch Current Sensing: Easy Layout, Accurate, Higher Efficiency, High VOUT Capable Figure 3d.

Current Transformer: Highest Efficiency, High VOUT Capable 3726 F03c 3726 F03d Figure 3.
Current Sensing Techniques 3726fb 13 LTC3726 APPLICATIO S I FOR ATIOW PolyPhase Applications U U U Figure 4 shows the basic connections for using the LTC3705/LTC3725 and LTC3726 in PolyPhase applica- tions.

One of the phases is always identified as the “mas- ter,” while all other phases are “slaves.” For the LTC3705/ LTC3725 (primary side), the master monitors the VIN voltage for undervoltage, performs the open-loop start-up and supplies the initial VCC voltage for the master and all slaves.
The LTC3705/LTC3725 slaves simply stand by and wait for PWM signals from their respective pulse trans- formers.

Since the SS/FLT pins of each master and slave LTC3705/LTC3725s are interconnected, a FAULT (overcurrent, etc.)

on any one of the phases will perform a shutdown/restart on all phases together.

The LTC3705/ LTC3725 is put into slave mode by omitting the resistor on FS/IN–.
For the LTC3726, the master performs soft-start and voltage-loop regulation by driving all slaves to the same current as the master using the ITH pins.

Faults and shutdowns are communicated via the interconnection of the RUN/SS pins.

The LTC3726 is put into slave mode by tying the FB pin to VCC.
14 + VIN – VIN VBIAS + VOUT • • NDRV UVLO FB/IN+ VCC SS/FLT FS/IN– LTC3705/25 (MASTER) • • NDRV SS/FLT FB/IN+ VCC UVLO FS/IN– LTC3705/25 (SLAVE) VCC FS/SYNC FB/PHASE ITH PT+ PT– RUN/SS LTC3726 (MASTER) VCC RUN/SS FS/SYNC PT+ PT– ITH FB/PHASE LTC3726 (SLAVE) Figure 4.
Connections for PolyPhase Operation 3726 F05 3726fb PACKAGE DESCRIPTIO U LTC3726 GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 ±.005 .189 – .196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .254 MIN .150 – .165 .0165 ± .0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .015 ± .004 (0.38 ± 0.10) × 45° 0° – 8° TYP .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.249) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 .007 – .0098 (0.178 – 0.249) .016 – .050 (0.406 – 1.270) NOTE: 1.
CONTROLLING DIMENSION: INCHES 2.

DIMENSIONS ARE IN INCHES (MILLIMETERS) 3.

DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH.

MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH.

INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use.


Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
3726fb 15 LTC3726 TYPICAL APPLICATIOU + VIN L1 1µH 1µF 100V 1µF 100V x3 – VIN 10Ω 0.25W 1nF 100V 10Ω 0.25W 1nF 100V Si7852DP Si7852DP MURS120 T1 • • 9:2 Si7336ADP MURS120 2.2nF 250V 2mΩ 2W 30mΩ 1W L2 1.2µH + VOUT 1.2Ω CMPSH1-4 Si7336ADP ×2 10µF 25V CZT3019 1µF FZT690B 5K 7.5V 2.2µF 16V 330µF 6.3V ×3 – VOUT 102k 1% 365k 1% 1nF 15k 1% UVLO VCC SS/FLT 33nF 2.2µF 25V 100Ω 680pF 100Ω 100Ω FQT7N10 100k BAS21 0.22µF NDRV BOOST TG TS BG IS FB/IN+ L1: VISHAY IHLP-2525CZ-01 L2: COILCRAFT SER2010-122 T1: PULSE PA0807 T2: PULSE PA0297 1nF – IS + IS PT+ FG SW SG VCC FS/SYNC FB/PHASE ITH LTC3726 T2 • • 1µF LTC3705 100Ω 0.1µF 470pF FS/IN– 5k 2:1 GND PGND VSLMT PT– RUN/SS GND PGND SLP MODE 162k 33nF 100k 680pF 20k 22.6k 1% 3726 F05 Figure 5.
36V-72V to 3.3V/20A Isolated Forward Converter (See Typical Performance Characteristics) RELATED PARTS DESCRIPTION PART NUMBER LT1534 Ultralow Noise 2A Switching Regulator LT1619 Low Voltage Current Mode Controller LT1681/LT3781 Dual Transistor Synchronous Forward Controller LT1725 General Purpose Isolated Flyback Controller Wide Input Range, No RSENSE™ Controller Protected High Side MOSFET Driver COMMENTS Reduces Conducted and Radiated EMI, Low Switching Harmonics, 20kHz to 250kHz Switching Frequency 1.9V ≤ VIN ≤ 18V, 300kHz Operation, Boost, Flyback, SEPIC Operation Up to 72V Maximum No Optoisolator Required, Accurate Regulation Without User Trims, 50kHz to 250kHz Switching Frequency, SSOP-16 Package Operation as Low as 2.5V Input, Boost, Flyback, SEPIC 8V to 48V Supply Range, Protected –15V to 60V Supply Transient LTC1871 LT1910 LT1952 LTC3440 LTC3704 LTC3705 LT3706 LTC3722 LTC3725 Single Switch Forward Controller 25W to 500W; Synchronous Controller Micropower Buck-Boost DC/DC Converter Synchronous, Single Inductor, No Schottky Diode Required Positive-to-Negative DC/DC Controller 2.5V ≤ VIN ≤ 36V, No RSENSE Current Mode Operation, Excellent Transient Response Two-Switch Forward Converter Gate Driver and Controller Use with LTC3726, Isolated Power Supplies, High Speed Gate Drivers PolyPhase Secondary Side Controller Scalable Output Power; Self-Starting Architecture Full Bridge Controller Two-Switch Forward Controller Synchronous; ZVS Operation; 24-Pin SSOP On-Chip Gate-Driver; Fast Startup No RSENSE is a trademark of Linear Technology Corporation.
16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT 0207 REV B • PRINTED IN THE USA 3726fb © LINEAR TECHNOLOGY CORPORATION 2006