Source document: https://docs-lawep.s3.us-east-2.amazonaws.com/1698061153240.pdf (Liberia)
DEMO MANUAL DC252 DESIGN-READY SWITCHER LTC1736 5-Bit VID Constant Frequency Synchronous DC/DC Converter DESCRIPTIOU Demonstration Circuit DC252 is designed for mobile 5-bit VID-programmed notebook CPU applications using the LTC®1736 switching regulator controller.

A high perfor- mance, constant frequency current mode architecture generates a precise low voltage CPU core supply.
Protec- tion features include an externally defeatable overcurrent latchoff and internal current foldback for overload condi- tions.

A soft-latched crowbar monitors the output voltage for overvoltage protection.

OPTI-LOOPTM compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values.

The circuit was designed for a 5V to 24V input range but allows a 4.5V to 28V range (limited by the external MOSFETs).
Strong output drivers easily handle large power MOSFETs effi- ciently.

Output voltages can be configured according to Intel mobile VID standards of 0.9V to 2.0V.

An internal power-good circuit monitors the output voltage for out-of- regulation conditions.
External frequency synchronization is provided, as are three modes of operation: Burst ModeTM operation to reduce switching losses and maintain high operating efficiencies, burst inhibit/forced continuous mode and a low noise pulse-skipping mode that provides constant frequency operation down to 1% maximum load currents with low quiescent current.

This results in a power supply that has very high efficiency, low ripple and fast transient response.

Gerber files for this circuit board are available.


Call the LTC factory.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation.
PERFOR A CE SU UW WW ARY PARAMETER CONDITIONS Input Voltage Range (Maximum Input Voltage Limited By External MOSFET and Input Capacitor) Output Output Voltage (Programmed with a 5-Bit Mobile VID Code) Max Output Current (Continuous) Max Output Current (Peak) VIN Typical Output Ripple Measured with 10MHz Bandwidth (Burst Mode Operation) IO = 100mA Typical Output Ripple Measured with 10MHz Bandwidth (Continuous) IO = 5A Line Regulation 5V to 24V VALUE 5V to 24V 0.9V to 2.0V 11.0A 12A 45mVP-P 20mVP-P 0.002%/V TYPICAL PERFOR A CE CHARACTERISTICS A D BOARD PHOTOS W U U Efficiency Component Side Solder Side 100 ) % ( Y C N E I C I F F E 90 80 70 60 50 40 10mA EXTVCC = 5V VIN = 5V VIN = 24V VIN = 15V 100mA 1A LOAD CURRENT (A) 10A 252 TA01 1 VALUE – 0.3% 950m A 15m A 850m A 1.3V 270kHz 24 23 22 21 20 19 18 17 16 15 14 13 TG BOOST SW VIN INTVCC BG PGND EXTVCC VIDVCC VID4 VID3 VID2 LTC1736CG24 TOP VIEW COSC RUN/SS ITH FCB SGND PGOOD SENSE– SENSE+ VFB VOSENSE VID0 VID1 DEMO MANUAL DC252 DESIGN-READY SWITCHER PERFOR A CE SU UW WW ARY PARAMETER CONDITIONS IOUT IQ IEXTVCC VRUN Frequency Load Regulation: No Load to Full Rated Output Supply Current (Typical), No Load, VIN = 15V, FCB = INTVCC Supply Current in Shutdown (Typical), VIN = 15V EXTVCC Pin Current, VEXTVCC = 5V, VIN = 10V, FCB = INTVCC, No Load, VOUT = 1.6V Run Pin Threshold (Typical) Operating Frequency (Typical), COSC = 47pF W PACKAGE A D SCHE ATIC DIAGRA W U JP2 LATCHOFF R6 680k CF1 0.1µF U1 24 23 22 21 20 19 18 17 16 15 14 13 COSC TG RUN/SS BOOST LTC1736 ITH FCB SW VIN SGND INTVCC PGOOD BG SENSE– PGND SENSE+ EXTVCC VFB VIDVCC VID4 VID3 VID2 VOSENSE VID0 VID1 LSB JP4 B0 JP1 BURST MODE FCB/SYNC E4 RUN E3 OFF ON INTVCC COSC1 47pF CSS1 0.1µF CC1 47pF CC2 330pF RC1 33k PGOOD E1 JP3 PGOOD INTVCC R1 100k CS1 1000pF C1 47pF C3 47pF RF1 4.7Ω R8 0Ω + CIN1 22µF 30V + CIN3 22µF 30V +VIN E10 GND E9 M2 FDS6680A CB1 0.22µF G PACKAGE 24-LEAD PLASTIC SSOP D1 CMDSH-3 L1 1.2µH RCS1 0.004Ω +C2 4.7µF C4 1µF M1, M3 FDS6680A 2X D2
 MBRS340T3 EXTVCC E2 RS1 10Ω VOUT 0.9V TO 2V/11A E7 VOSNS E11 + CO1, CO2, C04, C06 180µF 4V X4 GND E8 MSB B4 R5, 10Ω R2, 10Ω 247 F01 Figure 1.
Demo Board Schematic DEMO MANUAL DC252 DESIGN-READY SWITCHER PARTS LIST REFERENCE C1, C3 C2 C4 CC1 CC2 CB1 CF1, CSS1 CIN1, CIN3 CIN1, CIN3 CO1, CO2, CO4, CO6 CO1, CO2, CO4 CO3, CO5 COSC1 CS1 D1 D2 E1, GND, +VIN, VOSNS, VOUT1 E2, E3, E4, E8, E9, GND, +VIN, +VOUT JP1 JP2, JP3 JP4 L1 M1, M2, M3 R1 R2, R5, RS1 R6 R8 RC1 RCS1 RF1 U1 2 1 1 1 1 1 2 2 1 1 1 1 5 8 1 2 1 1 3 1 3 1 1 1 1 1 1 8 QUANTITY PART NUMBER DESCRIPTION VENDOR 08055A470JAT1A TACR475M010R 0805ZC105MAT1A 47pF 50V 5% NPO Capacitor 4.7m F 10V 20% Tantalum Capacitor 1m F 10V 20% X7R Capacitor 08055A470JAT1A 47pF 50V 5% NPO Capacitor 08055A331MAT1A 08055A224KAT1A 08055A104MAT1A 30SC22M OPT THCR70E1H2262T 4 OPT OPT EEFUE0G181R T510X447MOO6AS 4SP820M 330pF 50V 5% NPO Capacitor 0.22m F 50V 20% X7R Capacitor 0.1m F 50V 20% X7R Capacitor 22m F 30V OS-CON Capacitor 22m F 50V 20% Y5U Capacitor 180m F 4V SP Capacitor 470m F 6.3V Low ESR Tantalum Capacitor 820m F 4V OS-CON Capacitor 08055A470JAT1A 47pF 50V 5% NPO Capacitor 08055A102MAT1A 1000pF 50V 5% NPO Capacitor AVX AVX AVX AVX AVX AVX AVX SANYO MARCON PANASONIC KEMET SANYO AVX AVX CMDSH-3 MBRS340T3 1593-2 1502-2 2802S-03-G2 2802S-02-G2 2202S-05-G2 ETQP6F1R2HFA FDS6680A CR10-104JM CR10-100FM CR10-685JM CR10-0R0JM CR10-333JM LRF2010-01-R004F CR10-470JM LTC1736CG Turret Terminal (Small) Turret Terminal 2mm 3-Pin Header 2mm 2-Pin Header 2mm Dual 5-Pin Header 1.2m H Inductor 30V 0.013W N-Channel MOSFET 100k 1/10W 5% Chip Resistor 10W 1/10W, 1% Chip Resistor 680k 1/10W 5% Chip Resistor 0W 1/10W Chip Resistor 33k 1/10W 5% Chip Resistor 0.004W 4.7W 1/2W 1% Resistor 1/10W, 5% Chip Resistor IC, LTC1736CG24 KEYSTONE KEYSTONE COMM CON COMM CON COMM CON PANASONIC FAIRCHILD TAD TAD TAD TAD TAD IRC TAD LTC CCIJ2mm-138-G JUMPER COMM CON BVR = 30V, 0.1A Schottky Diode CENTRAL BVR = 40V, 3A Schottky Diode ON SEMICONDUCTOR (800) 282-9855 TELEPHONE (843) 946-0362 (207) 282-5111 (843) 946-0362 (843) 946-0362 (843) 946-0362 (843) 946-0362 (843) 946-0362 (619) 661-6835 (847) 696-2000 (201) 348-7522 (408) 986-0424 (619) 661-6835 (843)
 946-0362 (843) 946-0362 (516) 435-1110 (718) 956-8900 (718) 956-8900 (626) 301-4200 (626) 301-4200 (626) 301-4200 (201) 348-7522 (408) 822-2126 (800) 508-1521 (800) 508-1521 (800) 508-1521 (800) 508-1521 (800) 508-1521 (361) 992-7900 (714) 255-9123 (408) 432-1900 (626) 301-4200 3 DEMO MANUAL DC252 DESIGN-READY SWITCHER QUICK START GUIDE This demonstration board is easy to set up to evaluate the performance of the LTC1736.
Please follow the procedure outlined below for proper operation.

Sol- dered wire connections are required to properly evalu- ate the performance of this switching regulator.

• Refer to Figure 2 for proper connection of monitoring and measurement equipment.

• Connect the input power supply to the VIN and GND terminals on the right-hand side of the board with soldered connections.

Do not increase VIN over 28V or the MOSFET(s) WILL BE DAMAGED.

• If an external 5V supply is used, connect it to EXTVCC.
• Set the jumper JP1 so that FCB selects the desired mode: JP1 On Off MODE Burst Mode Operation, Connect PGood to FCB/Sync Forced Continuous Open Apply External Clock to FCB/Sync • Jumper JP2 determines if the overcurrent latchoff is enabled.

With JP2 installed this function is disabled.

Remove JP2 to enable.

• Connect the load between the VOUT and GND termi- nals on the right side of the board with soldered connections.
JP2 Installed Removed OVERCURRENT LATCHOFF Disabled Enabled • The RUN pin can be left unconnected.

To shut down the LTC1736, tie this pin to ground.

• Set jumper JP4 for the desired output voltage.

(See • Active loads can cause confusing results.

Refer to the active load discussion in the Operation section.

Table 1.)
Table 1.)

RUN JP2 LATCHOFF VID CPU POWER CONVERTER OPTIONAL EXTERNAL HIGH FREQUENCY SOURCE CONNECTION EXT CLOCK (REMOVE JP1 IF USED) FCB/SYNC OFF ON JP1 BURST PGOOD EXTVCC JP3 PGOOD JP4 VO PROG B0 B4 GND LTC1736CG DEMO CIRCUIT DC252A (408) 432-1900 +VIN GND GND VOSNS +VOUT + – – + VOUT Figure 2 OPTIONAL REMOTE VOUT SENSE CONNECTION A IIN + – VIN LOAD IOUT A 252 F02 U U I TRODUCTIO The circuit in Figure 1 highlights the capabilities of the LTC1736.
The LTC1736 is a synchronous step-down switching regulator controller that drives external N-channel power MOSFETs using a fixed frequency architecture with OPTI- LOOP compensation.

OPTI-LOOP compensation effectively removes the constraints placed on COUT by other controllers for proper operation (such as restrictions on very low ESRs).

Burst Mode operation provides high efficiency at 4 low load currents.

Operating efficiencies typically exceed 80% over more than two decades of load current range.
Do not use spring clip leads when testing this circuit.

Soldered wire connections are required to properly test the performance of the PC board.

This demonstration circuit is intended for the evaluation of the LTC1736 switching regulator IC and was not designed for any other purpose.

OPERATIOU The operating frequency is set by an external capacitor, COSC1, allowing maximum flexibility in optimizing effi- ciency.

In this application, the frequency is set to 270kHz.
A multifunction control pin, FCB, inhibits Burst Mode operation (reducing noise and RF interference), as well as allowing synchronization to an external oscillator.

Soft-start is provided by an external capacitor, CSS1, which can be used to properly sequence supplies.

The operating current level is user programmable via an exter- nal current sense resistor and is set to 11A.

Short-circuit current is limited to approximately 4A by internal current foldback.
Measuring Voltage Regulation When trying to measure voltage regulation, remember that all measurements must be taken at the point of regulation.

This point is where the LTC1736’s control loop looks for the information to keep the output voltage constant.

In this demonstration board it is located be- tween Pin 5 (SGND) of the LTC1736 and the sense side of RS1.

This point corresponds to the VOSNS terminal of the board.

Output voltage test leads should be attached di- rectly to this terminal.
The load should be placed across the VOUT (E7) and GND (E8) terminals.

Measurements should not be taken at the end of test leads at the load; refer to Figure 2 for the proper monitoring equipment configu- ration.

This applies to line regulation (input to output voltage regulation) as well as load regulation tests.

In doing line regulation tests, always look at the input voltage across the input terminals.
Remote Output Voltage Sensing Remote output voltage sensing can be accomplished by connecting the VOSNS terminal with another wire directly to the load.

A 10W resistor, RS1, connects VOUT to VOSNS to avoid open sense conditions.

Never under any circum- stance connect the load to VOSNS!

Output Voltage Programming The output voltage is digitally set to levels between 0.925V and 2.00V using the voltage identification (VID) inputs B0 to B4 set by jumper JP4.
The internal 5-bit DAC configured DEMO MANUAL DC252 DESIGN-READY SWITCHER as a precision resistor voltage divider sets the output voltage in 50mV/25mV increments according to Table 1.

Table 1.
VID Output Voltage Programming B4 B3 B2 B1 B0 VOUT (V) 2.000V 1.950V 1.900V 1.850V 1.800V 1.750V 1.700V 1.650V 1.600V 1.550V 1.500V 1.450V 1.400V 1.350V 1.300V * 1.275V 1.250V 1.225V 1.200V 1.175V 1.150V 1.125V 1.100V 1.075V 1.050V 1.025V 1.000V 0.975V 0.950V 0.925V ** Note: *, ** Represents codes without a defined output voltage as specified in Intel specifcations.
The LTC1736 interprets these codes as a valid input and produces output voltage as follows: [01111] = 1.250V, [11111] = 0.900V.

5 DEMO MANUAL DC252 DESIGN-READY SWITCHER OPERATIOU The VID codes (00000-11110) are engineered to be com- patible with Intel Mobile Pentium® II Processor specifica- tions for output voltages from 0.925V to 2.00V.

The LSB (B0) represents 50mV increments in the upper voltage range (2.00V to 1.30V) and 25mV increments in the lower voltage range (1.275V to 0.925V).

The MSB is B4.
The MSB is B4.

When all bits are low or grounded, the output voltage is 2.00V.

Each VID digital input is internally pulled up by a 40k resistor in series with a diode from VIDVCC.

Therefore, digital inputs must be grounded to get a digital low input, and digital inputs can be either left unconnected or con- nected to VIDVCC to get a digital high input.

The series diode is used to prevent the digital inputs from being damaged or clamped if they are driven higher than VIDVCC.
The digital inputs accept CMOS voltage levels.

Maximum Input Voltage Considerations The recommended maximum input voltage of this board is 24V for nominal output voltages.

The minimum on-time for the LTC1736 is generally about 200ns and the operat- ing frequency for this board is set to 270kHz.

This imposes a limit on the maximum input voltage when programming low output voltages.
For output voltages below 1.2V the maximum input voltage is limited to: VIN(MAX) < 20 (VOUT) If a higher operating input voltage is required with VOUT < 1.2V, the operating frequency can be decreased by in- creasing COSC1.

Refer to the LTC1736 data sheet for details.

If the duty cycle falls below what can be accommo- dated by the minimum on-time, the LTC1736 will begin to skip cycles.

The output voltage will continue to be regu- lated, but the ripple current and ripple voltage will in- crease.
Power-Good Output A window comparator monitors the output voltage and its open-drain output (E1) is pulled low when the divided output voltage is not within – 7.5% of the reference voltage of 0.8V.

Jumper JP3 connects pull-up resistor R1 from INTVCC to the power-good output, E1.

This jumper is provided to allow other pull-up voltages to be used.

Make 6 sure the maximum voltage on PGOOD is less than 7V.

During shutdown, the PGOOD output is pulled low.


INTVCC Regulator An internal, P-channel, low dropout regulator produces the 5.2V supply that powers the drivers and internal circuitry within the LTC1736.

The INTVCC pin can supply up to 50mA (this includes the gate-drive currents).

Exter- nal loading of the INTVCC pin can be thermally limited (allow 10mA to 20mA for gate-drive currents).
At high input voltages, the maximum junction temperature rating for the LTC1736 may be exceeded if too large an external load is placed on INTVCC.

See the LTC1736 data sheet for details.

EXTVCC Connection The LTC1736 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins.

The switch closes and supplies the INTVCC power when- ever the EXTVCC pin is above 4.7V; it remains closed until EXTVCC drops below 4.5V.
This allows the MOSFET driver and control power to be derived from the EXTVCC pin instead of VIN.

Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC < VIN.

Additional efficiency gains can be realized by powering INTVCC from other high efficiency sources, such as a 5V system power supply.

The following list describes the most common possible connections for EXTVCC for low output voltage applica- tions: 1.
EXTVCC left open (or grounded); this will cause INTVCC to be powered from the internal 5.2V regulator resulting in an efficiency penalty at low load currents and high input voltages.

2.

EXTVCC connected to an external supply ; if an external, high efficiency supply is available in the 5V to 7V range (EXTVCC < VIN), it may be used to power EXTVCC, providing an efficiency boost.

The typical connection in a notebook CPU power solution is to connect it to the main 5V system power supply.
Pentium is registered trademark of Intel Corportion.

OPERATIOU Low Current Modes and Synchronization The FCB input pin, set by jumper JP1 and FCB/Sync terminal E4, allows the selection of the low current oper- ating mode and external frequency synchronization of the switching regulator.

Tying the FCB pin to ground with JP1 forces the controller into PWM or forced continuous mode.

In forced continu- ous mode, the output MOSFETs are always driven, regard- less of output loading conditions.
Operating in this mode allows the switching regulator to source or sink current— but be careful; when the output stage sinks current, power is transferred back into the input supply terminals and the input voltage rises.

Burst Mode operation is enabled when the voltage applied to the FCB pin is greater than 0.8V (i.e., JP1 tied to INTVCC) or if the pin is left open.

A comparator with a precision 0.8V threshold allows the pin to be used to regulate a secondary winding on the switching regulator’s output.
A small amount of hysteresis is included in the design of the comparator to facilitate clean secondary operation.

When the resistively divided secondary output voltage falls be- low the 0.8V threshold, the controller operates in the forced continuous operating mode for as long as it takes to bring the secondary voltage above the 0.8V + hysteresis level.
The internal LTC1736 oscillator can be synchronized to an external oscillator by clocking the FCB pin with a signal above 1.5VP-P (Remember to remove jumper JP1).

When the LTC1736 is synchronized to an external frequency, Burst Mode operation operation is disabled but cycle skipping is allowed at low load currents, since current reversal is inhibited.

The bottom gate will come on every 10 clock cycles to ensure that the bootstrap capacitor CB1 is kept charged.
The rising edge of an external clock applied to the FCB pin starts a new cycle.

When the LTC1736 is synchronized to an external clock, burst inhibit mode allows heavily discontinuous, low audio noise, constant frequency operation down to ap- proximately 1% of maximum designed load current.

This mode results in the elimination of switching frequency subharmonics over 99% of the output load range.
Switch- ing cycles start to be dropped at approximately 1% of DEMO MANUAL DC252 DESIGN-READY SWITCHER maximum designed load current in order to maintain proper output voltage.

The range of synchronization is from 240kHz to 350kHz with COSC = 47pF.

Attempting to synchronize to a higher frequency than 350kHz can result in inadequate slope compensation and cause loop instability with high duty cycles.
If loop instability is observed while synchronized, additional slope compensation can be obtained by simply decreasing COSC.
The following table summarizes the possible states avail- able on the FCB/Sync pin: FCB/SYNC PIN DC Voltage: 0V to 0.7V DC Voltage: ‡ 0.9V CONDITION Burst Disabled/Forced Continuous Current Reversal Enabled Burst Mode Operation, No Current Reversal Feedback Resistors Regulating a Secondary Winding Ext Clock: (0V to VFCB/SYNC) (VFCB/SYNC > 1.5V) Burst Mode Operation Disabled No Current Reversal DC252 Modifications (MOSFETs) The DC252 demo board has various modification provi- sions.
Additional pad locations are available for adding extra output capacitors together with an extra footprint for a parallel topside MOSFET.

When operating at high input voltages, the transition losses of the topside MOSFET (M2) become very signifi- cant.

Be sure to consider power loss due to transition losses as well as RDS(ON) losses.

Don’t over specify the topside MOSFET.

(Refer to the LTC1736 data sheet for details.)


Refer to the LTC1736 data sheet for further information on the internal operation and functionality descriptions of the IC.

DC252 Modifications (Output Capacitors) Four Matsushita SP output capacitors are installed on the demo board.

Other output capacitors may freely be substi- tuted provided they meet the load transient requirements.
OPTI-LOOP compensation allows the transient response to be optiumized over a wide range of output capacitance and ESR values while minimizing output capacitance.

7 DEMO MANUAL DC252 DESIGN-READY SWITCHER OPERATIOU The output capacitors are generally determined by ESR (effective series resistance) and voltage rating rather than capacitance.

The ESR must be small enough that output ripple voltage and any voltage droop due to high load current transients stay within the specifications of the CPU.
The output capacitance must be large enough to hold up the output voltage until the inductor current has ramped up or down to its new value.

With proper OPTI-LOOP compensation components, the response time is opti- mized and the output capacitance is minimized.

The com- pensation components installed on the demo board are appropriate for the output capacitors specified in the parts list.

Additional mounting locations exist for through hole Sanyo OS-CON output capacitors, should they be desired.
Com- binations of different types of capacitors have proved to yield cost effective solutions.

ESL (equivalent series in- ductance), typically not specified, can reduce the effec- tiveness of the ESR at high load current slew rates, so be careful in specifying the output capacitor.

Overcurrent Protection The RUN/SS capacitor, CSS1, is used initially to turn on and limit the inrush current of the controller.
After the control- ler has been started and given adequate time to charge the output capacitor and provide full load current, CSS1 is used as a short-circuit time-out circuit.

If the output voltage falls to less than 70% of its nominal value, CSS1 begins dis- charging on the assumption that the output is in an overcurrent and/or short-circuit condition.
If the condition lasts for a long enough period, as determined by the size of CSS1, the controller will be shut down until the RUN/SS pin voltage is recycled.

This built-in latchoff can be over- ridden by providing >5m A pull-up at a compliance of 4V to the RUN/SS pin by installing jumper JP2.

This current shortens the soft-start period but also prevents net dis- charge of the RUN/SS capacitor during an overcurrent and/or short-circuit condition.
Foldback current limiting is activated when the output voltage falls below 70% of its nominal level, whether or not the short-circuit latchoff circuit is enabled.

cycle the run pin to start.

Refer to the LTC1736 data sheet for details.

Overvoltage Protection The output is protected from overvoltage by a “soft-latch.” When the output voltage exceeds the regulation value by more than 7.5%, the synchronous MOSFET turns on, and remains on for as long as the overvoltage condition is present.
If the output voltage returns to a safe level, normal operation resumes.

This self-resetting action prevents "nuisance trips" due to momentary transients and elimi- nates the need for the Schottky diode that is necessary with conventional OVP to prevent VOUT reversal.

Because of the inherent self-resetting action of the soft- latch, dynamic changing of the VID control bits does not latch off the LTC1736.
When a new output voltage is set via the VID bits, the control loop simply adjusts the output voltage and the overvoltage protection threshold to this new level without causing a fault.

The overvoltage threshold tracks the new output voltage, protecting the load at all times.

Figure 3a and Figure 3b both show an example of a dynamic VID code change resulting in a programmed output voltage change from 1.5V to 1.3V at a constant 5 ampere load current.
At the instant the VID code is changed, the control loop begins to respond to the new output voltage, and the power-good output is asserted low since the new programmed output voltage is outside the 7.5% window.

When the new output voltage is within 7.5% of its new programmed value, the power-good signal goes high.

Figure 3a shows a VID code change with the FCB pin low (Burst Mode operation disabled).

Figure 3b shows a dynamic VID code change with Burst Mode operation active.
If dynamic VID changes are required and Burst Mode operation is desired, connect the PGOOD output (E1) to the FCB/Sync input (E4) and remove jumper JP1.

This connection automatically forces continuous operation whenever the power-good output is low, providing fast response to VID changes regardless of load current.

Active Loads— Beware With the overcurrent latchoff enabled, a slow ramp on the input voltage may cause the circuit to latch off.

Simply re- Beware of active loads!


They are convenient but problem- atic.

Some active loads do not turn on until the applied 8 OPERATIOU VOUT 100mV/ DIV IL 5A/DIV PGOOD 5V/DIV DEMO MANUAL DC252 DESIGN-READY SWITCHER VOUT 100mV/ DIV IL 5A/DIV PGOOD 5V/DIV Figure 3a.

Dynamic VID Change, Burst Mode Operation Defeated Figure 3b.

Dynamic VID Change, Burst Mode Operation Enabled 252 F03a 252 F03b voltage rises above 0.1V to 0.8V.

The turn-on may be delayed as well.


A switching regulator with soft-start may appear to start up, then shut down and, eventually, reach the correct output voltage.

What happens is as follows: at switching regulator turn-on, the output voltage is below the active load’s turn-on requirements.

The switching regulator’s output rises to the correct output voltage level due to the inherent delay in the active load.
The active load turns on after its internal delay and then pulls down the switching regulator’s output because the switcher is in its soft-start interval.

The switching regulator’s output may come up at some later time when the soft-start interval has passed.

A switching regulator with foldback current limit will also have difficulty with the unrealistic I-V characteristic of the active load.
Foldback current limiting will reduce the output current available as the output voltage drops below a threshold level (this level is 70% of nominal VOUT for the LTC1736).

This reduction in available output current will result in the active load immediately pulling down the output because the active load’s current demand remains constant as the output voltage decreases.

Most actual loads do not behave like the active load I-V characteristics.
Actual loads normally have a VIN • C • f dependency, where C is internal chip capacitance and f is the frequency of operation.

To alleviate the active-load problem during testing, the active load should be initially programmed to a much lower current value until the switching regulator’s soft-start interval has passed and then increased to the higher level.

The switching regulator will supply the in- creased current required according to the transient re- sponse of the switching regulator.
Output capacitance needs to be sufficient to accommodate the current step during the transient period, keeping the output voltage at or above the foldback threshold of 70%.

Checking Transient Response OPTI-LOOP compensation effectively removes the con- straints placed on COUT by other controllers (such as restrictions on very low ESRs).
The output capacitors used in this demo board have very low ESRs; other types may be substituted but be carefull to measure the load step transient response and verify the specfications on output voltage continue to be met during transients.

A partial list of low ESR capacitors that are suitable for this application is included in the parts list.

Each has its own cost, size, ESL and other performance trade offs.

Combi- nations of capacitors have been shown to work well, too, so feel free to experiment.
An example of a combination that works well is an OS-CON, 820m F/4V capacitor in parallel with a 180m F/4V Matsushita SP series capacitor.

The SP capacitor tames the ESL-induced characteristic of 9 DEMO MANUAL DC252 DESIGN-READY SWITCHER OPERATIOU the otherwise low ESR OS-CON.

The ITH OPTI-LOOP compensation components shown in Figure 1’s circuit will provide an adequate starting point for most applications.
The load-step response with the output voltage set to 1.6V is shown in Figures 4a and 4b using four 180m F/4V Matsushita SP series for the output capacitors.

Figure␣ 4a is a 0A to 12A load step with Burst Mode operation inhibited (FCB = 0V).

Figure 4b shows the load step response for a 10mA to 12A load current transition with Burst Mode operation enabled (FCB = 5V).

The regulator loop response can be checked by looking at the load current transient response.
Switching regulators take several cycles to respond to a step in DC (resistive) load current.

When a load step occurs, VOUT shifts by an amount equal to D ILOAD (ESR), where ESR is the effective series resistance of COUT.

D ILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem.

OPTI- LOOP compensation allows the transient response to be optimized over a wide range of output capacitances and ESR values.

The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed-loop-response test point.
The DC step, rise time and settling at this test point truly reflect the closed-loop response.

Assuming a pre- dominantly first order system, phase margin and/or damp- ing factor can be estimated using the percentage of overshoot seen at this pin.

The bandwidth can also be estimated by examining the rise time at the pin.

The ITH series RC1–CC2, CC1 filter sets the dominant pole- zero loop compensation.
The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined.

The output capacitors need to be decided upon because the various types and values deter- mine the loop feedback factor gain and phase.
An output current pulse of 20% to 100% of full load current having a rise time of 1m s to 10m s will produce output voltage and VOUT 50mV/DIV IL 5A/DIV Figure 4a.

Load Step Response with Burst Mode Operation Disabled Figure 4b.

Load Step Response with Burst Mode Operation Enabled 252 F04a 252 F04b VOUT 50mV/DIV IL 5A/DIV 10 DEMO MANUAL DC252 DESIGN-READY SWITCHER OPERATIOU ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop.
The AC gain of the loop will be increased by increasing RC1 and the bandwidth of the loop will be increased by decreasing CC2.

If RC1 is increased by the same factor that CC2 is de- creased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop.

The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance.
Capacitor CC2 provides some high frequency decoupling against transients.

Be carefull not to overspecify its value, as the response time to a load step will be degraded.

Again, monitoring the ITH pin will show any slew rate limitations due to CC1.

For further explanation of optimizing loop response, refer to Application Note 76.
PCB LAYOUT A D FIL U W Component Side Silkscreen Component Side Copper (Layer 1) Internal Copper (Layer 2) Internal Copper (Layer 3) Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use.

Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11 DEMO MANUAL DC252 DESIGN-READY SWITCHER PCB LAYOUT A D FIL U W Bottom Side Copper (Layer 4) Bottom Side Silkscreen Bottom Side Paste Mask Component Paste Mask PC FAB DRAWI GU 2.75 10 PLCS D C E E E D D D D G G E E C E C D DF E D D D D D D D B C A A A A NOTES: UNLESS OTHERWISE SPECIFIED 1.

ALL DIMENSIONS ARE IN INCHES, – 0.003.

FINISHED HOLE SIZES ARE +0.003/–0.

2.

FINISHED MATERIAL IS FR4, 0.062 THICK, 1 OZ Cu, 4 LAYERS.
PLATED HOLE WALL THICKNESS 0.001 MIN.

INTERNAL LAYERS 1 OZ Cu.

3.

PROCESS AND PLATING: SMOBC 4.

SOLDERMASK BOTH SIDES USING GLOSSY GREEN LPI.

5.

SILKSCREEN WHITE NONCONDUCTIVE INK BOTH SIDES.


2.10" SYMBOL A B C D E F G DIAMETER 0.100 0.070 0.065 0.045 0.035 0.025 0.020 NUMBER OF HOLES 8 2 5 18 25 2 15 PLATED YES NO YES YES YES YES YES 252 PC Fab Dwg 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear-tech.com dc252f LT/TP 1199 500 • PRINTED IN USA ª LINEAR TECHNOLOGY CORPORATION 1999